VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-hlp.cpp@ 94377

Last change on this file since 94377 was 93115, checked in by vboxsync, 3 years ago

scm --update-copyright-year
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 19.8 KB
Line 
1/* $Id: DevVGA-SVGA3d-hlp.cpp 93115 2022-01-01 11:31:46Z vboxsync $ */
2/** @file
3 * DevVMWare - VMWare SVGA device helpers
4 */
5
6/*
7 * Copyright (C) 2020-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
19#include <VBox/AssertGuest.h>
20
21#ifdef SHADER_VERIFY_STANDALONE
22# include <stdio.h>
23//# define Log3(a) printf a - /** @todo r=bird: This is strictly forbidden. Noone redefines Log macros ever! */
24//# define LogRel(a) printf a - /** @todo r=bird: This is strictly forbidden. Noone redefines Log macros ever! */
25#else
26# include <VBox/log.h>
27#endif
28
29#include <iprt/cdefs.h>
30#include <iprt/errcore.h>
31#include <iprt/types.h>
32#include <iprt/string.h>
33
34#include "DevVGA-SVGA.h"
35
36/** Per shader data is stored in this structure. */
37typedef struct VMSVGA3DSHADERPARSECONTEXT
38{
39 /** Version token. */
40 SVGA3dShaderVersion version;
41
42 SVGA3dShaderOpCodeType currentOpcode;
43 union
44 {
45 SVGA3DOpDclArgs *pDclArgs;
46 } u;
47} VMSVGA3DSHADERPARSECONTEXT;
48
49/** Callback which parses a parameter token.
50 *
51 * @param pCtx The shader data.
52 * @param Op Instruction opcode which the token is used with.
53 * @param Token The parameter token which must be parsed.
54 * @param idxToken Index of the parameter token in the instruction. 0 for the first parameter.
55 *
56 * @return VBox error code.
57 */
58typedef int FNSHADERPARSETOKEN(VMSVGA3DSHADERPARSECONTEXT* pCtx, uint32_t Op, uint32_t Token, uint32_t idxToken);
59typedef FNSHADERPARSETOKEN* PFNSHADERPARSETOKEN;
60
61/** Information about a shader opcode. */
62typedef struct VMSVGA3DSHADERPARSEOP
63{
64 /** Opcode. */
65 SVGA3dShaderOpCodeType Op;
66 /** Maximum number of parameters. */
67 uint32_t Length;
68 /** Pointer to callback, which parse each parameter.
69 * The size is the number of maximum possible parameters: dest + 3 * src
70 */
71 PFNSHADERPARSETOKEN apfnParse[4];
72} VMSVGA3DSHADERPARSEOP;
73
74static int vmsvga3dShaderParseRegOffset(VMSVGA3DSHADERPARSECONTEXT *pCtx,
75 bool fIsSrc,
76 SVGA3dShaderRegType regType,
77 uint32_t off)
78{
79 RT_NOREF(pCtx, fIsSrc);
80
81 switch (regType)
82 {
83 case SVGA3DREG_TEMP:
84 break;
85 case SVGA3DREG_INPUT:
86 break;
87 case SVGA3DREG_CONST:
88 break;
89 case SVGA3DREG_ADDR /* also SVGA3DREG_TEXTURE */:
90 break;
91 case SVGA3DREG_RASTOUT:
92 break;
93 case SVGA3DREG_ATTROUT:
94 break;
95 case SVGA3DREG_TEXCRDOUT /* also SVGA3DREG_OUTPUT */:
96 break;
97 case SVGA3DREG_CONSTINT:
98 break;
99 case SVGA3DREG_COLOROUT:
100 break;
101 case SVGA3DREG_DEPTHOUT:
102 break;
103 case SVGA3DREG_SAMPLER:
104 break;
105 case SVGA3DREG_CONST2:
106 break;
107 case SVGA3DREG_CONST3:
108 break;
109 case SVGA3DREG_CONST4:
110 break;
111 case SVGA3DREG_CONSTBOOL:
112 break;
113 case SVGA3DREG_LOOP:
114 break;
115 case SVGA3DREG_TEMPFLOAT16:
116 break;
117 case SVGA3DREG_MISCTYPE:
118 ASSERT_GUEST_RETURN( off == SVGA3DMISCREG_POSITION
119 || off == SVGA3DMISCREG_FACE, VERR_PARSE_ERROR);
120 break;
121 case SVGA3DREG_LABEL:
122 break;
123 case SVGA3DREG_PREDICATE:
124 break;
125 default:
126 ASSERT_GUEST_FAILED_RETURN(VERR_PARSE_ERROR);
127 }
128
129 return VINF_SUCCESS;
130}
131
132/* Parse a declaration parameter token:
133 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/dcl-instruction
134 *
135 * See FNSHADERPARSETOKEN.
136 */
137static int vmsvga3dShaderParseDclToken(VMSVGA3DSHADERPARSECONTEXT* pCtx, uint32_t Op, uint32_t Token, uint32_t idxToken)
138{
139 RT_NOREF(pCtx, Op, Token, idxToken);
140 return VINF_SUCCESS;
141}
142
143/* Parse a label (D3DSPR_LABEL) parameter token.
144 *
145 * See FNSHADERPARSETOKEN.
146 */
147static int vmsvga3dShaderParseLabelToken(VMSVGA3DSHADERPARSECONTEXT* pCtx, uint32_t Op, uint32_t Token, uint32_t idxToken)
148{
149 RT_NOREF(pCtx, Op, Token, idxToken);
150 return VINF_SUCCESS;
151}
152
153/* Parse a destination parameter token:
154 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/destination-parameter-token
155 * See FNSHADERPARSETOKEN.
156 */
157static int vmsvga3dShaderParseDestToken(VMSVGA3DSHADERPARSECONTEXT* pCtx, uint32_t Op, uint32_t Token, uint32_t idxToken)
158{
159 RT_NOREF(pCtx, Op, idxToken);
160
161 SVGA3dShaderDestToken dest;
162 dest.value = Token;
163
164 SVGA3dShaderRegType const regType = (SVGA3dShaderRegType)(dest.type_upper << 3 | dest.type_lower);
165 Log3(("Dest: type %d, r0 %d, shfScale %d, dstMod %d, mask 0x%x, r1 %d, relAddr %d, num %d\n",
166 regType, dest.reserved0, dest.shfScale, dest.dstMod, dest.mask, dest.reserved1, dest.relAddr, dest.num));
167
168 if (pCtx->currentOpcode == SVGA3DOP_DCL && regType == SVGA3DREG_SAMPLER)
169 {
170 if (pCtx->u.pDclArgs->type == SVGA3DSAMP_UNKNOWN)
171 {
172 Log3(("Replacing SVGA3DSAMP_UNKNOWN with SVGA3DSAMP_2D\n"));
173 pCtx->u.pDclArgs->type = SVGA3DSAMP_2D;
174 }
175 }
176
177 return vmsvga3dShaderParseRegOffset(pCtx, false, regType, dest.num);
178}
179
180/* Parse a source parameter token:
181 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/source-parameter-token
182 * See FNSHADERPARSETOKEN.
183 */
184static int vmsvga3dShaderParseSrcToken(VMSVGA3DSHADERPARSECONTEXT* pCtx, uint32_t Op, uint32_t Token, uint32_t idxToken)
185{
186 RT_NOREF(pCtx, Op, idxToken);
187
188 SVGA3dShaderSrcToken src;
189 src.value = Token;
190
191 SVGA3dShaderRegType const regType = (SVGA3dShaderRegType)(src.type_upper << 3 | src.type_lower);
192 Log3(("Src: type %d, r0 %d, srcMod %d, swizzle 0x%x, r1 %d, relAddr %d, num %d\n",
193 regType, src.reserved0, src.srcMod, src.swizzle, src.reserved1, src.relAddr, src.num));
194
195 return vmsvga3dShaderParseRegOffset(pCtx, true, regType, src.num);
196}
197
198/* Shortcut defines. */
199#define PT_DCL vmsvga3dShaderParseDclToken
200#define PT_LBL vmsvga3dShaderParseLabelToken
201#define PT_DEST vmsvga3dShaderParseDestToken
202#define PT_SRC vmsvga3dShaderParseSrcToken
203
204/* Information about opcodes:
205 * https://docs.microsoft.com/en-us/windows-hardware/drivers/ddi/d3d9types/ne-d3d9types-_d3dshader_instruction_opcode_type
206 */
207static const VMSVGA3DSHADERPARSEOP aOps[] =
208{
209 /* Op Length Parameters */
210 /* 00 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
211 /* 01 */ { SVGA3DOP_MOV, 2, { PT_DEST, PT_SRC, NULL, NULL } },
212 /* 02 */ { SVGA3DOP_ADD, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
213 /* 03 */ { SVGA3DOP_SUB, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
214 /* 04 */ { SVGA3DOP_MAD, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
215 /* 05 */ { SVGA3DOP_MUL, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
216 /* 06 */ { SVGA3DOP_RCP, 2, { PT_DEST, PT_SRC, NULL, NULL } },
217 /* 07 */ { SVGA3DOP_RSQ, 2, { PT_DEST, PT_SRC, NULL, NULL } },
218 /* 08 */ { SVGA3DOP_DP3, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
219 /* 09 */ { SVGA3DOP_DP4, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
220 /* 10 */ { SVGA3DOP_MIN, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
221 /* 11 */ { SVGA3DOP_MAX, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
222 /* 12 */ { SVGA3DOP_SLT, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
223 /* 13 */ { SVGA3DOP_SGE, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
224 /* 14 */ { SVGA3DOP_EXP, 2, { PT_DEST, PT_SRC, NULL, NULL } },
225 /* 15 */ { SVGA3DOP_LOG, 2, { PT_DEST, PT_SRC, NULL, NULL } },
226 /* 16 */ { SVGA3DOP_LIT, 2, { PT_DEST, PT_SRC, NULL, NULL } },
227 /* 17 */ { SVGA3DOP_DST, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
228 /* 18 */ { SVGA3DOP_LRP, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
229 /* 19 */ { SVGA3DOP_FRC, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
230 /* 20 */ { SVGA3DOP_M4x4, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
231 /* 21 */ { SVGA3DOP_M4x3, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
232 /* 22 */ { SVGA3DOP_M3x4, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
233 /* 23 */ { SVGA3DOP_M3x3, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
234 /* 24 */ { SVGA3DOP_M3x2, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
235 /* 25 */ { SVGA3DOP_CALL, 1, { PT_LBL, NULL, NULL, NULL } },
236 /* 26 */ { SVGA3DOP_CALLNZ, 2, { PT_LBL, PT_SRC, NULL, NULL } },
237 /* 27 */ { SVGA3DOP_LOOP, 1, { PT_SRC, NULL, NULL, NULL } },
238 /* 28 */ { SVGA3DOP_RET, 0, { NULL, NULL, NULL, NULL } },
239 /* 29 */ { SVGA3DOP_ENDLOOP, 0, { NULL, NULL, NULL, NULL } },
240 /* 30 */ { SVGA3DOP_LABEL, 1, { PT_LBL, NULL, NULL, NULL } },
241 /* 31 */ { SVGA3DOP_DCL, 2, { PT_DCL, PT_DEST, NULL, NULL } },
242 /* 32 */ { SVGA3DOP_POW, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
243 /* 33 */ { SVGA3DOP_CRS, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
244 /* 34 */ { SVGA3DOP_SGN, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
245 /* 35 */ { SVGA3DOP_ABS, 2, { PT_DEST, PT_SRC, NULL, NULL } },
246 /* 36 */ { SVGA3DOP_NRM, 2, { PT_DEST, PT_SRC, NULL, NULL } },
247 /* 37 */ { SVGA3DOP_SINCOS, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
248 /* 38 */ { SVGA3DOP_REP, 1, { PT_SRC, NULL, NULL, NULL } },
249 /* 39 */ { SVGA3DOP_ENDREP, 0, { NULL, NULL, NULL, NULL } },
250 /* 40 */ { SVGA3DOP_IF, 1, { PT_SRC, NULL, NULL, NULL } },
251 /* 41 */ { SVGA3DOP_IFC, 2, { PT_SRC, PT_SRC, NULL, NULL } },
252 /* 42 */ { SVGA3DOP_ELSE, 0, { NULL, NULL, NULL, NULL } },
253 /* 43 */ { SVGA3DOP_ENDIF, 0, { NULL, NULL, NULL, NULL } },
254 /* 44 */ { SVGA3DOP_BREAK, 0, { NULL, NULL, NULL, NULL } },
255 /* 45 */ { SVGA3DOP_BREAKC, 2, { PT_SRC, PT_SRC, NULL, NULL } },
256 /* 46 */ { SVGA3DOP_MOVA, 2, { PT_DEST, PT_SRC, NULL, NULL } },
257 /* 47 */ { SVGA3DOP_DEFB, 2, { PT_DEST, NULL, NULL, NULL } },
258 /* 48 */ { SVGA3DOP_DEFI, 5, { PT_DEST, NULL, NULL, NULL } },
259 /* 49 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
260 /* 50 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
261 /* 51 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
262 /* 52 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
263 /* 53 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
264 /* 54 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
265 /* 55 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
266 /* 56 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
267 /* 57 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
268 /* 58 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
269 /* 59 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
270 /* 60 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
271 /* 61 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
272 /* 62 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
273 /* 63 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
274 /* 64 */ { SVGA3DOP_TEXCOORD, 2, { PT_DEST, PT_SRC, NULL, NULL } },
275 /* 65 */ { SVGA3DOP_TEXKILL, 1, { PT_DEST, NULL, NULL, NULL } },
276 /* 66 */ { SVGA3DOP_TEX, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } }, // pre-1.4 = tex dest, post-1.4 = texld dest, src, src
277 /* 67 */ { SVGA3DOP_TEXBEM, 2, { PT_DEST, PT_SRC, NULL, NULL } },
278 /* 68 */ { SVGA3DOP_TEXBEML, 2, { PT_DEST, PT_SRC, NULL, NULL } },
279 /* 69 */ { SVGA3DOP_TEXREG2AR, 2, { PT_DEST, PT_SRC, NULL, NULL } },
280 /* 70 */ { SVGA3DOP_TEXREG2GB, 2, { PT_DEST, PT_SRC, NULL, NULL } },
281 /* 71 */ { SVGA3DOP_TEXM3x2PAD, 2, { PT_DEST, PT_SRC, NULL, NULL } },
282 /* 72 */ { SVGA3DOP_TEXM3x2TEX, 2, { PT_DEST, PT_SRC, NULL, NULL } },
283 /* 73 */ { SVGA3DOP_TEXM3x3PAD, 2, { PT_DEST, PT_SRC, NULL, NULL } },
284 /* 74 */ { SVGA3DOP_TEXM3x3TEX, 2, { PT_DEST, PT_SRC, NULL, NULL } },
285 /* 75 */ { SVGA3DOP_RESERVED0, 0, { NULL, NULL, NULL, NULL } },
286 /* 76 */ { SVGA3DOP_TEXM3x3SPEC, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
287 /* 77 */ { SVGA3DOP_TEXM3x3VSPEC, 2, { PT_DEST, PT_SRC, NULL, NULL } },
288 /* 78 */ { SVGA3DOP_EXPP, 2, { PT_DEST, PT_SRC, NULL, NULL } },
289 /* 79 */ { SVGA3DOP_LOGP, 2, { PT_DEST, PT_SRC, NULL, NULL } },
290 /* 80 */ { SVGA3DOP_CND, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
291 /* 81 */ { SVGA3DOP_DEF, 5, { PT_DEST, NULL, NULL, NULL } },
292 /* 82 */ { SVGA3DOP_TEXREG2RGB, 2, { PT_DEST, PT_SRC, NULL, NULL } },
293 /* 83 */ { SVGA3DOP_TEXDP3TEX, 2, { PT_DEST, PT_SRC, NULL, NULL } },
294 /* 84 */ { SVGA3DOP_TEXM3x2DEPTH, 2, { PT_DEST, PT_SRC, NULL, NULL } },
295 /* 85 */ { SVGA3DOP_TEXDP3, 2, { PT_DEST, PT_SRC, NULL, NULL } },
296 /* 86 */ { SVGA3DOP_TEXM3x3, 2, { PT_DEST, PT_SRC, NULL, NULL } },
297 /* 87 */ { SVGA3DOP_TEXDEPTH, 1, { PT_DEST, NULL, NULL, NULL } },
298 /* 88 */ { SVGA3DOP_CMP, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
299 /* 89 */ { SVGA3DOP_BEM, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
300 /* 90 */ { SVGA3DOP_DP2ADD, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
301 /* 91 */ { SVGA3DOP_DSX, 2, { PT_DEST, PT_SRC, NULL, NULL } },
302 /* 92 */ { SVGA3DOP_DSY, 2, { PT_DEST, PT_SRC, NULL, NULL } },
303 /* 93 */ { SVGA3DOP_TEXLDD, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
304 /* 94 */ { SVGA3DOP_SETP, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
305 /* 95 */ { SVGA3DOP_TEXLDL, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
306 /* 96 */ { SVGA3DOP_BREAKP, 1, { PT_SRC, NULL, NULL, NULL } },
307};
308
309#undef PT_DCL
310#undef PT_LBL
311#undef PT_DEST
312#undef PT_SRC
313
314/* Parse the shader code
315 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/shader-code-format
316 */
317int vmsvga3dShaderParse(SVGA3dShaderType type, uint32_t cbShaderData, uint32_t* pShaderData)
318{
319 uint32_t *paTokensStart = (uint32_t*)pShaderData;
320 uint32_t const cTokens = cbShaderData / sizeof(uint32_t);
321
322 ASSERT_GUEST_RETURN(cTokens * sizeof(uint32_t) == cbShaderData, VERR_INVALID_PARAMETER);
323
324 /* Need at least the version token and SVGA3DOP_END instruction token. 48KB is an arbitrary limit. */
325 ASSERT_GUEST_RETURN(cTokens >= 2 && cTokens < (48 * _1K) / sizeof(paTokensStart[0]), VERR_INVALID_PARAMETER);
326
327#ifdef LOG_ENABLED
328 Log3(("Shader code:\n"));
329 const uint32_t cTokensPerLine = 8;
330 for (uint32_t iToken = 0; iToken < cTokens; ++iToken)
331 {
332 if ((iToken % cTokensPerLine) == 0)
333 {
334 if (iToken == 0)
335 Log3(("0x%08X,", paTokensStart[iToken]));
336 else
337 Log3(("\n0x%08X,", paTokensStart[iToken]));
338 }
339 else
340 Log3((" 0x%08X,", paTokensStart[iToken]));
341 }
342 Log3(("\n"));
343#endif
344
345 VMSVGA3DSHADERPARSECONTEXT ctx;
346 RT_ZERO(ctx);
347
348 /* "The first token must be a version token." */
349 ctx.version = *(SVGA3dShaderVersion*)paTokensStart;
350 ASSERT_GUEST_RETURN(ctx.version.type == SVGA3D_VS_TYPE
351 || ctx.version.type == SVGA3D_PS_TYPE, VERR_PARSE_ERROR);
352 /* A vertex shader should not be defined with a pixel shader bytecode (and visa versa)*/
353 ASSERT_GUEST_RETURN((ctx.version.type == SVGA3D_VS_TYPE && type == SVGA3D_SHADERTYPE_VS)
354 || (ctx.version.type == SVGA3D_PS_TYPE && type == SVGA3D_SHADERTYPE_PS), VERR_PARSE_ERROR);
355 ASSERT_GUEST_RETURN(ctx.version.major >= 2 && ctx.version.major <= 4, VERR_PARSE_ERROR);
356
357 /* Scan the tokens. Immediately return an error code on any unexpected data. */
358 uint32_t *paTokensEnd = &paTokensStart[cTokens];
359 uint32_t *pToken = &paTokensStart[1]; /* Skip the version token. */
360 bool bEndTokenFound = false;
361 while (pToken < paTokensEnd)
362 {
363 SVGA3dShaderInstToken const token = *(SVGA3dShaderInstToken*)pToken;
364
365 /* Figure out the instruction length, which is how many tokens follow the instruction token. */
366 uint32_t const cInstLen = token.op == SVGA3DOP_COMMENT
367 ? token.comment_size
368 : token.size;
369
370 Log3(("op %d, cInstLen %d\n", token.op, cInstLen));
371
372 /* Must not be greater than the number of remaining tokens. */
373 ASSERT_GUEST_RETURN(cInstLen < (uintptr_t)(paTokensEnd - pToken), VERR_PARSE_ERROR);
374
375 /* Stop parsing if this is the SVGA3DOP_END instruction. */
376 if (token.op == SVGA3DOP_END)
377 {
378 ASSERT_GUEST_RETURN(token.value == 0x0000FFFF, VERR_PARSE_ERROR);
379 bEndTokenFound = true;
380 break;
381 }
382
383 ctx.currentOpcode = (SVGA3dShaderOpCodeType)token.op;
384
385 /* If this instrution is in the aOps table. */
386 if (token.op <= SVGA3DOP_BREAKP)
387 {
388 VMSVGA3DSHADERPARSEOP const* pOp = &aOps[token.op];
389
390 if (ctx.currentOpcode == SVGA3DOP_DCL)
391 ctx.u.pDclArgs = (SVGA3DOpDclArgs *)&pToken[1];
392
393 /* cInstLen can be greater than pOp->Length.
394 * W10 guest sends a vertex shader MUL instruction with length 4.
395 * So figure out the actual number of valid parameters.
396 */
397 uint32_t const cParams = RT_MIN(cInstLen, pOp->Length);
398
399 /* Parse paramater tokens. */
400 uint32_t i;
401 for (i = 0; i < RT_MIN(cParams, RT_ELEMENTS(pOp->apfnParse)); ++i)
402 {
403 if (!pOp->apfnParse[i])
404 continue;
405
406 int rc = pOp->apfnParse[i](&ctx, token.op, pToken[i + 1], i);
407 if (RT_FAILURE(rc))
408 return rc;
409 }
410 }
411 else if (token.op == SVGA3DOP_PHASE
412 || token.op == SVGA3DOP_COMMENT)
413 {
414 }
415 else
416 ASSERT_GUEST_FAILED_RETURN(VERR_PARSE_ERROR);
417
418 /* Next token. */
419 pToken += cInstLen + 1;
420 }
421
422 if (!bEndTokenFound)
423 {
424 ASSERT_GUEST_FAILED_RETURN(VERR_PARSE_ERROR);
425 }
426
427 return VINF_SUCCESS;
428}
429
430void vmsvga3dShaderLogRel(char const *pszMsg, SVGA3dShaderType type, uint32_t cbShaderData, uint32_t const *pShaderData)
431{
432 /* Dump the shader code. */
433 static int scLogged = 0;
434 if (scLogged < 8)
435 {
436 ++scLogged;
437
438 LogRel(("VMSVGA: %s shader: %s:\n", (type == SVGA3D_SHADERTYPE_VS) ? "VERTEX" : "PIXEL", pszMsg));
439 const uint32_t cTokensPerLine = 8;
440 const uint32_t *paTokens = (uint32_t *)pShaderData;
441 const uint32_t cTokens = cbShaderData / sizeof(uint32_t);
442 for (uint32_t iToken = 0; iToken < cTokens; ++iToken)
443 {
444 if ((iToken % cTokensPerLine) == 0)
445 {
446 if (iToken == 0)
447 LogRel(("0x%08X,", paTokens[iToken]));
448 else
449 LogRel(("\n0x%08X,", paTokens[iToken]));
450 }
451 else
452 LogRel((" 0x%08X,", paTokens[iToken]));
453 }
454 LogRel(("\n"));
455 }
456}
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette