VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-hlp.cpp@ 87766

Last change on this file since 87766 was 86593, checked in by vboxsync, 4 years ago

scm after r140953
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 19.2 KB
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1/* $Id: DevVGA-SVGA3d-hlp.cpp 86593 2020-10-15 21:23:03Z vboxsync $ */
2/** @file
3 * DevVMWare - VMWare SVGA device helpers
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
19#include <VBox/AssertGuest.h>
20
21#ifdef SHADER_VERIFY_STANDALONE
22# include <stdio.h>
23//# define Log3(a) printf a - /** @todo r=bird: This is strictly forbidden. Noone redefines Log macros ever! */
24//# define LogRel(a) printf a - /** @todo r=bird: This is strictly forbidden. Noone redefines Log macros ever! */
25#else
26# include <VBox/log.h>
27#endif
28
29#include <iprt/cdefs.h>
30#include <iprt/errcore.h>
31#include <iprt/types.h>
32#include <iprt/string.h>
33
34#include "DevVGA-SVGA.h"
35
36/** Per shader data is stored in this structure. */
37typedef struct VMSVGA3DSHADERPARSECONTEXT
38{
39 /** Version token. */
40 SVGA3dShaderVersion version;
41} VMSVGA3DSHADERPARSECONTEXT;
42
43/** Callback which parses a parameter token.
44 *
45 * @param pCtx The shader data.
46 * @param Op Instruction opcode which the token is used with.
47 * @param Token The parameter token which must be parsed.
48 * @param idxToken Index of the parameter token in the instruction. 0 for the first parameter.
49 *
50 * @return VBox error code.
51 */
52typedef int FNSHADERPARSETOKEN(VMSVGA3DSHADERPARSECONTEXT* pCtx, uint32_t Op, uint32_t Token, uint32_t idxToken);
53typedef FNSHADERPARSETOKEN* PFNSHADERPARSETOKEN;
54
55/** Information about a shader opcode. */
56typedef struct VMSVGA3DSHADERPARSEOP
57{
58 /** Opcode. */
59 SVGA3dShaderOpCodeType Op;
60 /** Maximum number of parameters. */
61 uint32_t Length;
62 /** Pointer to callback, which parse each parameter.
63 * The size is the number of maximum possible parameters: dest + 3 * src
64 */
65 PFNSHADERPARSETOKEN apfnParse[4];
66} VMSVGA3DSHADERPARSEOP;
67
68static int vmsvga3dShaderParseRegOffset(VMSVGA3DSHADERPARSECONTEXT *pCtx,
69 bool fIsSrc,
70 SVGA3dShaderRegType regType,
71 uint32_t off)
72{
73 RT_NOREF(pCtx, fIsSrc);
74
75 switch (regType)
76 {
77 case SVGA3DREG_TEMP:
78 break;
79 case SVGA3DREG_INPUT:
80 break;
81 case SVGA3DREG_CONST:
82 break;
83 case SVGA3DREG_ADDR /* also SVGA3DREG_TEXTURE */:
84 break;
85 case SVGA3DREG_RASTOUT:
86 break;
87 case SVGA3DREG_ATTROUT:
88 break;
89 case SVGA3DREG_TEXCRDOUT /* also SVGA3DREG_OUTPUT */:
90 break;
91 case SVGA3DREG_CONSTINT:
92 break;
93 case SVGA3DREG_COLOROUT:
94 break;
95 case SVGA3DREG_DEPTHOUT:
96 break;
97 case SVGA3DREG_SAMPLER:
98 break;
99 case SVGA3DREG_CONST2:
100 break;
101 case SVGA3DREG_CONST3:
102 break;
103 case SVGA3DREG_CONST4:
104 break;
105 case SVGA3DREG_CONSTBOOL:
106 break;
107 case SVGA3DREG_LOOP:
108 break;
109 case SVGA3DREG_TEMPFLOAT16:
110 break;
111 case SVGA3DREG_MISCTYPE:
112 ASSERT_GUEST_RETURN( off == SVGA3DMISCREG_POSITION
113 || off == SVGA3DMISCREG_FACE, VERR_PARSE_ERROR);
114 break;
115 case SVGA3DREG_LABEL:
116 break;
117 case SVGA3DREG_PREDICATE:
118 break;
119 default:
120 ASSERT_GUEST_FAILED_RETURN(VERR_PARSE_ERROR);
121 }
122
123 return VINF_SUCCESS;
124}
125
126/* Parse a declaration parameter token:
127 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/dcl-instruction
128 *
129 * See FNSHADERPARSETOKEN.
130 */
131static int vmsvga3dShaderParseDclToken(VMSVGA3DSHADERPARSECONTEXT* pCtx, uint32_t Op, uint32_t Token, uint32_t idxToken)
132{
133 RT_NOREF(pCtx, Op, Token, idxToken);
134 return VINF_SUCCESS;
135}
136
137/* Parse a label (D3DSPR_LABEL) parameter token.
138 *
139 * See FNSHADERPARSETOKEN.
140 */
141static int vmsvga3dShaderParseLabelToken(VMSVGA3DSHADERPARSECONTEXT* pCtx, uint32_t Op, uint32_t Token, uint32_t idxToken)
142{
143 RT_NOREF(pCtx, Op, Token, idxToken);
144 return VINF_SUCCESS;
145}
146
147/* Parse a destination parameter token:
148 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/destination-parameter-token
149 * See FNSHADERPARSETOKEN.
150 */
151static int vmsvga3dShaderParseDestToken(VMSVGA3DSHADERPARSECONTEXT* pCtx, uint32_t Op, uint32_t Token, uint32_t idxToken)
152{
153 RT_NOREF(pCtx, Op, idxToken);
154
155 SVGA3dShaderDestToken dest;
156 dest.value = Token;
157
158 SVGA3dShaderRegType const regType = (SVGA3dShaderRegType)(dest.type_upper << 3 | dest.type_lower);
159 Log3(("Dest: type %d, r0 %d, shfScale %d, dstMod %d, mask 0x%x, r1 %d, relAddr %d, num %d\n",
160 regType, dest.reserved0, dest.shfScale, dest.dstMod, dest.mask, dest.reserved1, dest.relAddr, dest.num));
161
162 return vmsvga3dShaderParseRegOffset(pCtx, false, regType, dest.num);
163}
164
165/* Parse a source parameter token:
166 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/source-parameter-token
167 * See FNSHADERPARSETOKEN.
168 */
169static int vmsvga3dShaderParseSrcToken(VMSVGA3DSHADERPARSECONTEXT* pCtx, uint32_t Op, uint32_t Token, uint32_t idxToken)
170{
171 RT_NOREF(pCtx, Op, idxToken);
172
173 SVGA3dShaderSrcToken src;
174 src.value = Token;
175
176 SVGA3dShaderRegType const regType = (SVGA3dShaderRegType)(src.type_upper << 3 | src.type_lower);
177 Log3(("Src: type %d, r0 %d, srcMod %d, swizzle 0x%x, r1 %d, relAddr %d, num %d\n",
178 regType, src.reserved0, src.srcMod, src.swizzle, src.reserved1, src.relAddr, src.num));
179
180 return vmsvga3dShaderParseRegOffset(pCtx, true, regType, src.num);
181}
182
183/* Shortcut defines. */
184#define PT_DCL vmsvga3dShaderParseDclToken
185#define PT_LBL vmsvga3dShaderParseLabelToken
186#define PT_DEST vmsvga3dShaderParseDestToken
187#define PT_SRC vmsvga3dShaderParseSrcToken
188
189/* Information about opcodes:
190 * https://docs.microsoft.com/en-us/windows-hardware/drivers/ddi/d3d9types/ne-d3d9types-_d3dshader_instruction_opcode_type
191 */
192static const VMSVGA3DSHADERPARSEOP aOps[] =
193{
194 /* Op Length Parameters */
195 /* 00 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
196 /* 01 */ { SVGA3DOP_MOV, 2, { PT_DEST, PT_SRC, NULL, NULL } },
197 /* 02 */ { SVGA3DOP_ADD, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
198 /* 03 */ { SVGA3DOP_SUB, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
199 /* 04 */ { SVGA3DOP_MAD, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
200 /* 05 */ { SVGA3DOP_MUL, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
201 /* 06 */ { SVGA3DOP_RCP, 2, { PT_DEST, PT_SRC, NULL, NULL } },
202 /* 07 */ { SVGA3DOP_RSQ, 2, { PT_DEST, PT_SRC, NULL, NULL } },
203 /* 08 */ { SVGA3DOP_DP3, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
204 /* 09 */ { SVGA3DOP_DP4, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
205 /* 10 */ { SVGA3DOP_MIN, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
206 /* 11 */ { SVGA3DOP_MAX, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
207 /* 12 */ { SVGA3DOP_SLT, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
208 /* 13 */ { SVGA3DOP_SGE, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
209 /* 14 */ { SVGA3DOP_EXP, 2, { PT_DEST, PT_SRC, NULL, NULL } },
210 /* 15 */ { SVGA3DOP_LOG, 2, { PT_DEST, PT_SRC, NULL, NULL } },
211 /* 16 */ { SVGA3DOP_LIT, 2, { PT_DEST, PT_SRC, NULL, NULL } },
212 /* 17 */ { SVGA3DOP_DST, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
213 /* 18 */ { SVGA3DOP_LRP, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
214 /* 19 */ { SVGA3DOP_FRC, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
215 /* 20 */ { SVGA3DOP_M4x4, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
216 /* 21 */ { SVGA3DOP_M4x3, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
217 /* 22 */ { SVGA3DOP_M3x4, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
218 /* 23 */ { SVGA3DOP_M3x3, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
219 /* 24 */ { SVGA3DOP_M3x2, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
220 /* 25 */ { SVGA3DOP_CALL, 1, { PT_LBL, NULL, NULL, NULL } },
221 /* 26 */ { SVGA3DOP_CALLNZ, 2, { PT_LBL, PT_SRC, NULL, NULL } },
222 /* 27 */ { SVGA3DOP_LOOP, 1, { PT_SRC, NULL, NULL, NULL } },
223 /* 28 */ { SVGA3DOP_RET, 0, { NULL, NULL, NULL, NULL } },
224 /* 29 */ { SVGA3DOP_ENDLOOP, 0, { NULL, NULL, NULL, NULL } },
225 /* 30 */ { SVGA3DOP_LABEL, 1, { PT_LBL, NULL, NULL, NULL } },
226 /* 31 */ { SVGA3DOP_DCL, 2, { PT_DCL, PT_DEST, NULL, NULL } },
227 /* 32 */ { SVGA3DOP_POW, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
228 /* 33 */ { SVGA3DOP_CRS, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
229 /* 34 */ { SVGA3DOP_SGN, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
230 /* 35 */ { SVGA3DOP_ABS, 2, { PT_DEST, PT_SRC, NULL, NULL } },
231 /* 36 */ { SVGA3DOP_NRM, 2, { PT_DEST, PT_SRC, NULL, NULL } },
232 /* 37 */ { SVGA3DOP_SINCOS, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
233 /* 38 */ { SVGA3DOP_REP, 1, { PT_SRC, NULL, NULL, NULL } },
234 /* 39 */ { SVGA3DOP_ENDREP, 0, { NULL, NULL, NULL, NULL } },
235 /* 40 */ { SVGA3DOP_IF, 1, { PT_SRC, NULL, NULL, NULL } },
236 /* 41 */ { SVGA3DOP_IFC, 2, { PT_SRC, PT_SRC, NULL, NULL } },
237 /* 42 */ { SVGA3DOP_ELSE, 0, { NULL, NULL, NULL, NULL } },
238 /* 43 */ { SVGA3DOP_ENDIF, 0, { NULL, NULL, NULL, NULL } },
239 /* 44 */ { SVGA3DOP_BREAK, 0, { NULL, NULL, NULL, NULL } },
240 /* 45 */ { SVGA3DOP_BREAKC, 2, { PT_SRC, PT_SRC, NULL, NULL } },
241 /* 46 */ { SVGA3DOP_MOVA, 2, { PT_DEST, PT_SRC, NULL, NULL } },
242 /* 47 */ { SVGA3DOP_DEFB, 2, { PT_DEST, NULL, NULL, NULL } },
243 /* 48 */ { SVGA3DOP_DEFI, 5, { PT_DEST, NULL, NULL, NULL } },
244 /* 49 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
245 /* 50 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
246 /* 51 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
247 /* 52 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
248 /* 53 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
249 /* 54 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
250 /* 55 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
251 /* 56 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
252 /* 57 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
253 /* 58 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
254 /* 59 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
255 /* 60 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
256 /* 61 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
257 /* 62 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
258 /* 63 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
259 /* 64 */ { SVGA3DOP_TEXCOORD, 2, { PT_DEST, PT_SRC, NULL, NULL } },
260 /* 65 */ { SVGA3DOP_TEXKILL, 1, { PT_DEST, NULL, NULL, NULL } },
261 /* 66 */ { SVGA3DOP_TEX, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } }, // pre-1.4 = tex dest, post-1.4 = texld dest, src, src
262 /* 67 */ { SVGA3DOP_TEXBEM, 2, { PT_DEST, PT_SRC, NULL, NULL } },
263 /* 68 */ { SVGA3DOP_TEXBEML, 2, { PT_DEST, PT_SRC, NULL, NULL } },
264 /* 69 */ { SVGA3DOP_TEXREG2AR, 2, { PT_DEST, PT_SRC, NULL, NULL } },
265 /* 70 */ { SVGA3DOP_TEXREG2GB, 2, { PT_DEST, PT_SRC, NULL, NULL } },
266 /* 71 */ { SVGA3DOP_TEXM3x2PAD, 2, { PT_DEST, PT_SRC, NULL, NULL } },
267 /* 72 */ { SVGA3DOP_TEXM3x2TEX, 2, { PT_DEST, PT_SRC, NULL, NULL } },
268 /* 73 */ { SVGA3DOP_TEXM3x3PAD, 2, { PT_DEST, PT_SRC, NULL, NULL } },
269 /* 74 */ { SVGA3DOP_TEXM3x3TEX, 2, { PT_DEST, PT_SRC, NULL, NULL } },
270 /* 75 */ { SVGA3DOP_RESERVED0, 0, { NULL, NULL, NULL, NULL } },
271 /* 76 */ { SVGA3DOP_TEXM3x3SPEC, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
272 /* 77 */ { SVGA3DOP_TEXM3x3VSPEC, 2, { PT_DEST, PT_SRC, NULL, NULL } },
273 /* 78 */ { SVGA3DOP_EXPP, 2, { PT_DEST, PT_SRC, NULL, NULL } },
274 /* 79 */ { SVGA3DOP_LOGP, 2, { PT_DEST, PT_SRC, NULL, NULL } },
275 /* 80 */ { SVGA3DOP_CND, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
276 /* 81 */ { SVGA3DOP_DEF, 5, { PT_DEST, NULL, NULL, NULL } },
277 /* 82 */ { SVGA3DOP_TEXREG2RGB, 2, { PT_DEST, PT_SRC, NULL, NULL } },
278 /* 83 */ { SVGA3DOP_TEXDP3TEX, 2, { PT_DEST, PT_SRC, NULL, NULL } },
279 /* 84 */ { SVGA3DOP_TEXM3x2DEPTH, 2, { PT_DEST, PT_SRC, NULL, NULL } },
280 /* 85 */ { SVGA3DOP_TEXDP3, 2, { PT_DEST, PT_SRC, NULL, NULL } },
281 /* 86 */ { SVGA3DOP_TEXM3x3, 2, { PT_DEST, PT_SRC, NULL, NULL } },
282 /* 87 */ { SVGA3DOP_TEXDEPTH, 1, { PT_DEST, NULL, NULL, NULL } },
283 /* 88 */ { SVGA3DOP_CMP, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
284 /* 89 */ { SVGA3DOP_BEM, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
285 /* 90 */ { SVGA3DOP_DP2ADD, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
286 /* 91 */ { SVGA3DOP_DSX, 2, { PT_DEST, PT_SRC, NULL, NULL } },
287 /* 92 */ { SVGA3DOP_DSY, 2, { PT_DEST, PT_SRC, NULL, NULL } },
288 /* 93 */ { SVGA3DOP_TEXLDD, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
289 /* 94 */ { SVGA3DOP_SETP, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
290 /* 95 */ { SVGA3DOP_TEXLDL, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
291 /* 96 */ { SVGA3DOP_BREAKP, 1, { PT_SRC, NULL, NULL, NULL } },
292};
293
294#undef PT_DCL
295#undef PT_LBL
296#undef PT_DEST
297#undef PT_SRC
298
299/* Parse the shader code
300 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/shader-code-format
301 */
302int vmsvga3dShaderParse(SVGA3dShaderType type, uint32_t cbShaderData, uint32_t const* pShaderData)
303{
304 uint32_t const* paTokensStart = (uint32_t*)pShaderData;
305 uint32_t const cTokens = cbShaderData / sizeof(uint32_t);
306
307 ASSERT_GUEST_RETURN(cTokens * sizeof(uint32_t) == cbShaderData, VERR_INVALID_PARAMETER);
308
309 /* Need at least the version token and SVGA3DOP_END instruction token. 48KB is an arbitrary limit. */
310 ASSERT_GUEST_RETURN(cTokens >= 2 && cTokens < (48 * _1K) / sizeof(paTokensStart[0]), VERR_INVALID_PARAMETER);
311
312#ifdef LOG_ENABLED
313 Log3(("Shader code:\n"));
314 const uint32_t cTokensPerLine = 8;
315 for (uint32_t iToken = 0; iToken < cTokens; ++iToken)
316 {
317 if ((iToken % cTokensPerLine) == 0)
318 {
319 if (iToken == 0)
320 Log3(("0x%08X,", paTokensStart[iToken]));
321 else
322 Log3(("\n0x%08X,", paTokensStart[iToken]));
323 }
324 else
325 Log3((" 0x%08X,", paTokensStart[iToken]));
326 }
327 Log3(("\n"));
328#endif
329
330 VMSVGA3DSHADERPARSECONTEXT ctx;
331 RT_ZERO(ctx);
332
333 /* "The first token must be a version token." */
334 ctx.version = *(SVGA3dShaderVersion*)paTokensStart;
335 ASSERT_GUEST_RETURN(ctx.version.type == SVGA3D_VS_TYPE
336 || ctx.version.type == SVGA3D_PS_TYPE, VERR_PARSE_ERROR);
337 /* A vertex shader should not be defined with a pixel shader bytecode (and visa versa)*/
338 ASSERT_GUEST_RETURN((ctx.version.type == SVGA3D_VS_TYPE && type == SVGA3D_SHADERTYPE_VS)
339 || (ctx.version.type == SVGA3D_PS_TYPE && type == SVGA3D_SHADERTYPE_PS), VERR_PARSE_ERROR);
340 ASSERT_GUEST_RETURN(ctx.version.major >= 2 && ctx.version.major <= 4, VERR_PARSE_ERROR);
341
342 /* Scan the tokens. Immediately return an error code on any unexpected data. */
343 uint32_t const* paTokensEnd = &paTokensStart[cTokens];
344 uint32_t const* pToken = &paTokensStart[1]; /* Skip the version token. */
345 bool bEndTokenFound = false;
346 while (pToken < paTokensEnd)
347 {
348 SVGA3dShaderInstToken const token = *(SVGA3dShaderInstToken*)pToken;
349
350 /* Figure out the instruction length, which is how many tokens follow the instruction token. */
351 uint32_t const cInstLen = token.op == SVGA3DOP_COMMENT
352 ? token.comment_size
353 : token.size;
354
355 Log3(("op %d, cInstLen %d\n", token.op, cInstLen));
356
357 /* Must not be greater than the number of remaining tokens. */
358 ASSERT_GUEST_RETURN(cInstLen < (uintptr_t)(paTokensEnd - pToken), VERR_PARSE_ERROR);
359
360 /* Stop parsing if this is the SVGA3DOP_END instruction. */
361 if (token.op == SVGA3DOP_END)
362 {
363 ASSERT_GUEST_RETURN(token.value == 0x0000FFFF, VERR_PARSE_ERROR);
364 bEndTokenFound = true;
365 break;
366 }
367
368 /* If this instrution is in the aOps table. */
369 if (token.op <= SVGA3DOP_BREAKP)
370 {
371 VMSVGA3DSHADERPARSEOP const* pOp = &aOps[token.op];
372
373 /* cInstLen can be greater than pOp->Length.
374 * W10 guest sends a vertex shader MUL instruction with length 4.
375 * So figure out the actual number of valid parameters.
376 */
377 uint32_t const cParams = RT_MIN(cInstLen, pOp->Length);
378
379 /* Parse paramater tokens. */
380 uint32_t i;
381 for (i = 0; i < RT_MIN(cParams, RT_ELEMENTS(pOp->apfnParse)); ++i)
382 {
383 if (!pOp->apfnParse[i])
384 continue;
385
386 int rc = pOp->apfnParse[i](&ctx, token.op, pToken[i + 1], i);
387 if (RT_FAILURE(rc))
388 return rc;
389 }
390 }
391 else if (token.op == SVGA3DOP_PHASE
392 || token.op == SVGA3DOP_COMMENT)
393 {
394 }
395 else
396 ASSERT_GUEST_FAILED_RETURN(VERR_PARSE_ERROR);
397
398 /* Next token. */
399 pToken += cInstLen + 1;
400 }
401
402 if (!bEndTokenFound)
403 {
404 ASSERT_GUEST_FAILED_RETURN(VERR_PARSE_ERROR);
405 }
406
407 return VINF_SUCCESS;
408}
409
410void vmsvga3dShaderLogRel(char const *pszMsg, SVGA3dShaderType type, uint32_t cbShaderData, uint32_t const *pShaderData)
411{
412 /* Dump the shader code. */
413 static int scLogged = 0;
414 if (scLogged < 8)
415 {
416 ++scLogged;
417
418 LogRel(("VMSVGA: %s shader: %s:\n", (type == SVGA3D_SHADERTYPE_VS) ? "VERTEX" : "PIXEL", pszMsg));
419 const uint32_t cTokensPerLine = 8;
420 const uint32_t *paTokens = (uint32_t *)pShaderData;
421 const uint32_t cTokens = cbShaderData / sizeof(uint32_t);
422 for (uint32_t iToken = 0; iToken < cTokens; ++iToken)
423 {
424 if ((iToken % cTokensPerLine) == 0)
425 {
426 if (iToken == 0)
427 LogRel(("0x%08X,", paTokens[iToken]));
428 else
429 LogRel(("\n0x%08X,", paTokens[iToken]));
430 }
431 else
432 LogRel((" 0x%08X,", paTokens[iToken]));
433 }
434 LogRel(("\n"));
435 }
436}
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