VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.h@ 65298

Last change on this file since 65298 was 65298, checked in by vboxsync, 8 years ago

VMSVGA: Made the FIFO size configurable (still using the 128KB default).
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 14.0 KB
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1/* $Id: DevVGA-SVGA.h 65298 2017-01-14 20:11:22Z vboxsync $ */
2/** @file
3 * VMware SVGA device
4 */
5/*
6 * Copyright (C) 2013-2016 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 */
16
17#ifndef ___DevVGA_SVGA_h___
18#define ___DevVGA_SVGA_h___
19
20#ifndef VBOX_WITH_VMSVGA
21# error "VBOX_WITH_VMSVGA is not defined"
22#endif
23
24#include <VBox/vmm/pdmthread.h>
25
26
27/** Default FIFO size. */
28#define VMSVGA_FIFO_SIZE _128K
29
30/** Default scratch region size. */
31#define VMSVGA_SCRATCH_SIZE 0x100
32/** Surface memory available to the guest. */
33#define VMSVGA_SURFACE_SIZE (512*1024*1024)
34/** Maximum GMR pages. */
35#define VMSVGA_MAX_GMR_PAGES 0x100000
36/** Maximum nr of GMR ids. */
37#define VMSVGA_MAX_GMR_IDS 0x100
38/** Maximum number of GMR descriptors. */
39#define VMSVGA_MAX_GMR_DESC_LOOP_COUNT VMSVGA_MAX_GMR_PAGES
40
41#define VMSVGA_VAL_UNINITIALIZED (unsigned)-1
42
43/** For validating X and width values.
44 * The code assumes it's at least an order of magnitude less than UINT32_MAX. */
45#define VMSVGA_MAX_X _1M
46/** For validating Y and height values.
47 * The code assumes it's at least an order of magnitude less than UINT32_MAX. */
48#define VMSVGA_MAX_Y _1M
49
50/* u32ActionFlags */
51#define VMSVGA_ACTION_CHANGEMODE_BIT 0
52#define VMSVGA_ACTION_CHANGEMODE RT_BIT(VMSVGA_ACTION_CHANGEMODE_BIT)
53
54
55#ifdef DEBUG
56/* Enable to log FIFO register accesses. */
57//# define DEBUG_FIFO_ACCESS
58/* Enable to log GMR page accesses. */
59//# define DEBUG_GMR_ACCESS
60#endif
61
62#define VMSVGA_FIFO_EXTCMD_NONE 0
63#define VMSVGA_FIFO_EXTCMD_TERMINATE 1
64#define VMSVGA_FIFO_EXTCMD_SAVESTATE 2
65#define VMSVGA_FIFO_EXTCMD_LOADSTATE 3
66#define VMSVGA_FIFO_EXTCMD_RESET 4
67#define VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS 5
68
69/** Size of the region to backup when switching into svga mode. */
70#define VMSVGA_VGA_FB_BACKUP_SIZE _512K
71
72/** @def VMSVGA_WITH_VGA_FB_BACKUP
73 * Enables correct VGA MMIO read/write handling when VMSVGA is enabled. It
74 * is SLOW and probably not entirely right, but it helps with getting 3dmark
75 * output and other stuff. */
76#define VMSVGA_WITH_VGA_FB_BACKUP 1
77
78/** @def VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3
79 * defined(VMSVGA_WITH_VGA_FB_BACKUP) && defined(IN_RING3) */
80#if (defined(VMSVGA_WITH_VGA_FB_BACKUP) && defined(IN_RING3)) || defined(DOXYGEN_RUNNING)
81# define VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3 1
82#else
83# undef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3
84#endif
85
86/** @def VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RZ
87 * defined(VMSVGA_WITH_VGA_FB_BACKUP) && !defined(IN_RING3) */
88#if (defined(VMSVGA_WITH_VGA_FB_BACKUP) && !defined(IN_RING3)) || defined(DOXYGEN_RUNNING)
89# define VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RZ 1
90#else
91# undef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RZ
92#endif
93
94
95typedef struct
96{
97 PSSMHANDLE pSSM;
98 uint32_t uVersion;
99 uint32_t uPass;
100} VMSVGA_STATE_LOAD;
101typedef VMSVGA_STATE_LOAD *PVMSVGA_STATE_LOAD;
102
103/** Host screen viewport.
104 * (4th quadrant with negated Y values - usual Windows and X11 world view.) */
105typedef struct VMSVGAVIEWPORT
106{
107 uint32_t x; /**< x coordinate (left). */
108 uint32_t y; /**< y coordinate (top). */
109 uint32_t cx; /**< width. */
110 uint32_t cy; /**< height. */
111 /** Right side coordinate (exclusive). Same as x + cx. */
112 uint32_t xRight;
113 /** First quadrant low y coordinate.
114 * Same as y + cy - 1 in window coordinates. */
115 uint32_t yLowWC;
116 /** First quadrant high y coordinate (exclusive) - yLowWC + cy.
117 * Same as y - 1 in window coordinates. */
118 uint32_t yHighWC;
119 /** Alignment padding. */
120 uint32_t uAlignment;
121} VMSVGAVIEWPORT;
122
123/** Pointer to the private VMSVGA ring-3 state structure.
124 * @todo Still not entirely satisfired with the type name, but better than
125 * the previous lower/upper case only distinction. */
126typedef struct VMSVGAR3STATE *PVMSVGAR3STATE;
127/** Pointer to the private (implementation specific) VMSVGA3d state. */
128typedef struct VMSVGA3DSTATE *PVMSVGA3DSTATE;
129
130
131/**
132 * The VMSVGA device state.
133 *
134 * This instantatiated as VGASTATE::svga.
135 */
136typedef struct VMSVGAState
137{
138 /** The host window handle */
139 uint64_t u64HostWindowId;
140 /** The R3 FIFO pointer. */
141 R3PTRTYPE(uint32_t *) pFIFOR3;
142 /** The R0 FIFO pointer. */
143 R0PTRTYPE(uint32_t *) pFIFOR0;
144 /** R3 Opaque pointer to svga state. */
145 R3PTRTYPE(PVMSVGAR3STATE) pSvgaR3State;
146 /** R3 Opaque pointer to 3d state. */
147 R3PTRTYPE(PVMSVGA3DSTATE) p3dState;
148 /** The separate VGA frame buffer in svga mode.
149 * Unlike the the boch-based VGA device implementation, VMSVGA seems to have a
150 * separate frame buffer for VGA and allows concurrent use of both. The SVGA
151 * SDK is making use of this to do VGA text output while testing other things in
152 * SVGA mode, displaying the result by switching back to VGA text mode. So,
153 * when entering SVGA mode we copy the first part of the frame buffer here and
154 * direct VGA accesses here instead. It is copied back when leaving SVGA mode. */
155 R3PTRTYPE(uint8_t *) pbVgaFrameBufferR3;
156 /** R3 Opaque pointer to an external fifo cmd parameter. */
157 R3PTRTYPE(void * volatile) pvFIFOExtCmdParam;
158
159 /** Guest physical address of the FIFO memory range. */
160 RTGCPHYS GCPhysFIFO;
161 /** Size in bytes of the FIFO memory range. */
162 uint32_t cbFIFO;
163 /** SVGA id. */
164 uint32_t u32SVGAId;
165 /** SVGA extensions enabled or not. */
166 uint32_t fEnabled;
167 /** SVGA memory area configured status. */
168 uint32_t fConfigured;
169 /** Device is busy handling FIFO requests (VMSVGA_BUSY_F_FIFO,
170 * VMSVGA_BUSY_F_EMT_FORCE). */
171 uint32_t volatile fBusy;
172#define VMSVGA_BUSY_F_FIFO RT_BIT_32(0) /**< The normal true/false busy FIFO bit. */
173#define VMSVGA_BUSY_F_EMT_FORCE RT_BIT_32(1) /**< Bit preventing race status flickering when EMT kicks the FIFO thread. */
174 /** Traces (dirty page detection) enabled or not. */
175 uint32_t fTraces;
176 /** Guest OS identifier. */
177 uint32_t u32GuestId;
178 /** Scratch region size. */
179 uint32_t cScratchRegion;
180 /** Scratch array. */
181 uint32_t au32ScratchRegion[VMSVGA_SCRATCH_SIZE];
182 /** Irq status. */
183 uint32_t u32IrqStatus;
184 /** Irq mask. */
185 uint32_t u32IrqMask;
186 /** Pitch lock. */
187 uint32_t u32PitchLock;
188 /** Current GMR id. (SVGA_REG_GMR_ID) */
189 uint32_t u32CurrentGMRId;
190 /** Register caps. */
191 uint32_t u32RegCaps;
192 uint32_t Padding2;
193 /** Physical address of command mmio range. */
194 RTIOPORT BasePort;
195 RTIOPORT Padding3;
196 /** Port io index register. */
197 uint32_t u32IndexReg;
198 /** The support driver session handle for use with FIFORequestSem. */
199 R3R0PTRTYPE(PSUPDRVSESSION) pSupDrvSession;
200 /** FIFO request semaphore. */
201 SUPSEMEVENT FIFORequestSem;
202 /** FIFO external command semaphore. */
203 R3PTRTYPE(RTSEMEVENT) FIFOExtCmdSem;
204 /** FIFO IO Thread. */
205 R3PTRTYPE(PPDMTHREAD) pFIFOIOThread;
206 uint32_t uWidth;
207 uint32_t uHeight;
208 uint32_t uBpp;
209 uint32_t cbScanline;
210 /** Maximum width supported. */
211 uint32_t u32MaxWidth;
212 /** Maximum height supported. */
213 uint32_t u32MaxHeight;
214 /** Viewport rectangle, i.e. what's currently visible of the target host
215 * window. This is usually (0,0)(uWidth,uHeight), but if the window is
216 * shrunk and scrolling applied, both the origin and size may differ. */
217 VMSVGAVIEWPORT viewport;
218 /** Action flags */
219 uint32_t u32ActionFlags;
220 /** SVGA 3d extensions enabled or not. */
221 bool f3DEnabled;
222 /** VRAM page monitoring enabled or not. */
223 bool fVRAMTracking;
224 /** External command to be executed in the FIFO thread. */
225 uint8_t volatile u8FIFOExtCommand;
226 /** Set by vmsvgaR3RunExtCmdOnFifoThread when it temporarily resumes the FIFO
227 * thread and does not want it do anything but the command. */
228 bool volatile fFifoExtCommandWakeup;
229#if defined(DEBUG_GMR_ACCESS) || defined(DEBUG_FIFO_ACCESS)
230 /** GMR debug access handler type handle. */
231 PGMPHYSHANDLERTYPE hGmrAccessHandlerType;
232 /** FIFO debug access handler type handle. */
233 PGMPHYSHANDLERTYPE hFifoAccessHandlerType;
234#endif
235
236 STAMCOUNTER StatRegBitsPerPixelWr;
237 STAMCOUNTER StatRegBusyWr;
238 STAMCOUNTER StatRegCursorXxxxWr;
239 STAMCOUNTER StatRegDepthWr;
240 STAMCOUNTER StatRegDisplayHeightWr;
241 STAMCOUNTER StatRegDisplayIdWr;
242 STAMCOUNTER StatRegDisplayIsPrimaryWr;
243 STAMCOUNTER StatRegDisplayPositionXWr;
244 STAMCOUNTER StatRegDisplayPositionYWr;
245 STAMCOUNTER StatRegDisplayWidthWr;
246 STAMCOUNTER StatRegEnableWr;
247 STAMCOUNTER StatRegGmrIdWr;
248 STAMCOUNTER StatRegGuestIdWr;
249 STAMCOUNTER StatRegHeightWr;
250 STAMCOUNTER StatRegIdWr;
251 STAMCOUNTER StatRegIrqMaskWr;
252 STAMCOUNTER StatRegNumDisplaysWr;
253 STAMCOUNTER StatRegNumGuestDisplaysWr;
254 STAMCOUNTER StatRegPaletteWr;
255 STAMCOUNTER StatRegPitchLockWr;
256 STAMCOUNTER StatRegPseudoColorWr;
257 STAMCOUNTER StatRegReadOnlyWr;
258 STAMCOUNTER StatRegScratchWr;
259 STAMCOUNTER StatRegSyncWr;
260 STAMCOUNTER StatRegTopWr;
261 STAMCOUNTER StatRegTracesWr;
262 STAMCOUNTER StatRegUnknownWr;
263 STAMCOUNTER StatRegWidthWr;
264
265 STAMCOUNTER StatRegBitsPerPixelRd;
266 STAMCOUNTER StatRegBlueMaskRd;
267 STAMCOUNTER StatRegBusyRd;
268 STAMCOUNTER StatRegBytesPerLineRd;
269 STAMCOUNTER StatRegCapabilitesRd;
270 STAMCOUNTER StatRegConfigDoneRd;
271 STAMCOUNTER StatRegCursorXxxxRd;
272 STAMCOUNTER StatRegDepthRd;
273 STAMCOUNTER StatRegDisplayHeightRd;
274 STAMCOUNTER StatRegDisplayIdRd;
275 STAMCOUNTER StatRegDisplayIsPrimaryRd;
276 STAMCOUNTER StatRegDisplayPositionXRd;
277 STAMCOUNTER StatRegDisplayPositionYRd;
278 STAMCOUNTER StatRegDisplayWidthRd;
279 STAMCOUNTER StatRegEnableRd;
280 STAMCOUNTER StatRegFbOffsetRd;
281 STAMCOUNTER StatRegFbSizeRd;
282 STAMCOUNTER StatRegFbStartRd;
283 STAMCOUNTER StatRegGmrIdRd;
284 STAMCOUNTER StatRegGmrMaxDescriptorLengthRd;
285 STAMCOUNTER StatRegGmrMaxIdsRd;
286 STAMCOUNTER StatRegGmrsMaxPagesRd;
287 STAMCOUNTER StatRegGreenMaskRd;
288 STAMCOUNTER StatRegGuestIdRd;
289 STAMCOUNTER StatRegHeightRd;
290 STAMCOUNTER StatRegHostBitsPerPixelRd;
291 STAMCOUNTER StatRegIdRd;
292 STAMCOUNTER StatRegIrqMaskRd;
293 STAMCOUNTER StatRegMaxHeightRd;
294 STAMCOUNTER StatRegMaxWidthRd;
295 STAMCOUNTER StatRegMemorySizeRd;
296 STAMCOUNTER StatRegMemRegsRd;
297 STAMCOUNTER StatRegMemSizeRd;
298 STAMCOUNTER StatRegMemStartRd;
299 STAMCOUNTER StatRegNumDisplaysRd;
300 STAMCOUNTER StatRegNumGuestDisplaysRd;
301 STAMCOUNTER StatRegPaletteRd;
302 STAMCOUNTER StatRegPitchLockRd;
303 STAMCOUNTER StatRegPsuedoColorRd;
304 STAMCOUNTER StatRegRedMaskRd;
305 STAMCOUNTER StatRegScratchRd;
306 STAMCOUNTER StatRegScratchSizeRd;
307 STAMCOUNTER StatRegSyncRd;
308 STAMCOUNTER StatRegTopRd;
309 STAMCOUNTER StatRegTracesRd;
310 STAMCOUNTER StatRegUnknownRd;
311 STAMCOUNTER StatRegVramSizeRd;
312 STAMCOUNTER StatRegWidthRd;
313 STAMCOUNTER StatRegWriteOnlyRd;
314} VMSVGAState;
315
316
317DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
318 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType);
319
320DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t uScreenId,
321 uint32_t x, uint32_t y, uint32_t cx, uint32_t cy);
322
323int vmsvgaInit(PPDMDEVINS pDevIns);
324int vmsvgaReset(PPDMDEVINS pDevIns);
325int vmsvgaDestruct(PPDMDEVINS pDevIns);
326int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
327int vmsvgaLoadDone(PPDMDEVINS pDevIns);
328int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM);
329DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns);
330DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns);
331
332#endif
333
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