DevVGA-SVGA.cpp@ 96588

Last change on this file since 96588 was 96407, checked in by vboxsync, 2 years ago
scm copyright and license note update
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 306.6 KB

Line
1	/* $Id: DevVGA-SVGA.cpp 96407 2022-08-22 17:43:14Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - Log6 for DX shaders.
13	* - Log7 for SVGA command dump.
14	* - LogRel for the usual important stuff.
15	* - LogRel2 for cursor.
16	* - LogRel3 for 3D performance data.
17	* - LogRel4 for HW accelerated graphics output.
18	*/
19
20	/*
21	* Copyright (C) 2013-2022 Oracle and/or its affiliates.
22	*
23	* This file is part of VirtualBox base platform packages, as
24	* available from https://www.virtualbox.org.
25	*
26	* This program is free software; you can redistribute it and/or
27	* modify it under the terms of the GNU General Public License
28	* as published by the Free Software Foundation, in version 3 of the
29	* License.
30	*
31	* This program is distributed in the hope that it will be useful, but
32	* WITHOUT ANY WARRANTY; without even the implied warranty of
33	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
34	* General Public License for more details.
35	*
36	* You should have received a copy of the GNU General Public License
37	* along with this program; if not, see <https://www.gnu.org/licenses>.
38	*
39	* SPDX-License-Identifier: GPL-3.0-only
40	*/
41
42
43	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
44	*
45	* This device emulation was contributed by trivirt AG. It offers an
46	* alternative to our Bochs based VGA graphics and 3d emulations. This is
47	* valuable for Xorg based guests, as there is driver support shipping with Xorg
48	* since it forked from XFree86.
49	*
50	*
51	* @section sec_dev_vmsvga_sdk The VMware SDK
52	*
53	* This is officially deprecated now, however it's still quite useful,
54	* especially for getting the old features working:
55	* http://vmware-svga.sourceforge.net/
56	*
57	* They currently point developers at the following resources.
58	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
59	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
60	* - http://cgit.freedesktop.org/mesa/vmwgfx/
61	*
62	* @subsection subsec_dev_vmsvga_sdk_results Test results
63	*
64	* Test results:
65	* - 2dmark.img:
66	* + todo
67	* - backdoor-tclo.img:
68	* + todo
69	* - blit-cube.img:
70	* + todo
71	* - bunnies.img:
72	* + todo
73	* - cube.img:
74	* + todo
75	* - cubemark.img:
76	* + todo
77	* - dynamic-vertex-stress.img:
78	* + todo
79	* - dynamic-vertex.img:
80	* + todo
81	* - fence-stress.img:
82	* + todo
83	* - gmr-test.img:
84	* + todo
85	* - half-float-test.img:
86	* + todo
87	* - noscreen-cursor.img:
88	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
89	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
90	* visible though.)
91	* - Cursor animation via the palette doesn't work.
92	* - During debugging, it turns out that the framebuffer content seems to
93	* be halfways ignore or something (memset(fb, 0xcc, lots)).
94	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
95	* grow it 0x10 fold (128KB -> 2MB like in WS10).
96	* - null.img:
97	* + todo
98	* - pong.img:
99	* + todo
100	* - presentReadback.img:
101	* + todo
102	* - resolution-set.img:
103	* + todo
104	* - rt-gamma-test.img:
105	* + todo
106	* - screen-annotation.img:
107	* + todo
108	* - screen-cursor.img:
109	* + todo
110	* - screen-dma-coalesce.img:
111	* + todo
112	* - screen-gmr-discontig.img:
113	* + todo
114	* - screen-gmr-remap.img:
115	* + todo
116	* - screen-multimon.img:
117	* + todo
118	* - screen-present-clip.img:
119	* + todo
120	* - screen-render-test.img:
121	* + todo
122	* - screen-simple.img:
123	* + todo
124	* - screen-text.img:
125	* + todo
126	* - simple-shaders.img:
127	* + todo
128	* - simple_blit.img:
129	* + todo
130	* - tiny-2d-updates.img:
131	* + todo
132	* - video-formats.img:
133	* + todo
134	* - video-sync.img:
135	* + todo
136	*
137	*/
138
139
140	/*********************************************************************************************************************************
141	* Header Files *
142	*********************************************************************************************************************************/
143	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
144	#include <VBox/vmm/pdmdev.h>
145	#include <VBox/version.h>
146	#include <VBox/err.h>
147	#include <VBox/log.h>
148	#include <VBox/vmm/pgm.h>
149	#include <VBox/sup.h>
150
151	#include <iprt/assert.h>
152	#include <iprt/semaphore.h>
153	#include <iprt/uuid.h>
154	#ifdef IN_RING3
155	# include <iprt/ctype.h>
156	# include <iprt/mem.h>
157	# ifdef VBOX_STRICT
158	# include <iprt/time.h>
159	# endif
160	#endif
161
162	#include <VBox/AssertGuest.h>
163	#include <VBox/VMMDev.h>
164	#include <VBoxVideo.h>
165	#include <VBox/bioslogo.h>
166
167	#ifdef LOG_ENABLED
168	#include "svgadump/svga_dump.h"
169	#endif
170
171	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
172	#include "DevVGA.h"
173
174	/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
175	#ifdef VBOX_WITH_VMSVGA3D
176	# include "DevVGA-SVGA3d.h"
177	# ifdef RT_OS_DARWIN
178	# include "DevVGA-SVGA3d-cocoa.h"
179	# endif
180	# ifdef RT_OS_LINUX
181	# ifdef IN_RING3
182	# include "DevVGA-SVGA3d-glLdr.h"
183	# endif
184	# endif
185	#endif
186	#ifdef IN_RING3
187	#include "DevVGA-SVGA-internal.h"
188	#endif
189
190
191	/*********************************************************************************************************************************
192	* Defined Constants And Macros *
193	*********************************************************************************************************************************/
194	/**
195	* Macro for checking if a fixed FIFO register is valid according to the
196	* current FIFO configuration.
197	*
198	* @returns true / false.
199	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
200	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
201	*/
202	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
203
204
205	/*********************************************************************************************************************************
206	* Structures and Typedefs *
207	*********************************************************************************************************************************/
208
209
210	/*********************************************************************************************************************************
211	* Internal Functions *
212	*********************************************************************************************************************************/
213	#ifdef IN_RING3
214	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
215	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
216	# endif
217	# ifdef DEBUG_GMR_ACCESS
218	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
219	# endif
220	#endif
221
222
223	/*********************************************************************************************************************************
224	* Global Variables *
225	*********************************************************************************************************************************/
226	#ifdef IN_RING3
227
228	/**
229	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
230	*/
231	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
232	{
233	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
234	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
235	SSMFIELD_ENTRY_TERM()
236	};
237
238	/**
239	* SSM descriptor table for the GMR structure.
240	*/
241	static SSMFIELD const g_aGMRFields[] =
242	{
243	SSMFIELD_ENTRY( GMR, cMaxPages),
244	SSMFIELD_ENTRY( GMR, cbTotal),
245	SSMFIELD_ENTRY( GMR, numDescriptors),
246	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
247	SSMFIELD_ENTRY_TERM()
248	};
249
250	/**
251	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
252	*/
253	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
254	{
255	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
256	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
257	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
258	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
259	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
260	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
261	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
262	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
263	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
264	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
265	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
266	SSMFIELD_ENTRY_VER( VMSVGASCREENOBJECT, cDpi, VGA_SAVEDSTATE_VERSION_VMSVGA_MIPLEVELS),
267	SSMFIELD_ENTRY_TERM()
268	};
269
270	/**
271	* SSM descriptor table for the VMSVGAR3STATE structure.
272	*/
273	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
274	{
275	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
276	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
277	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
278	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
279	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
280	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
281	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
282	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
283	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
284	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
285	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
286	#ifdef VMSVGA_USE_EMT_HALT_CODE
287	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
288	#else
289	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
290	#endif
291	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
292	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
293	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
294	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
295	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
296	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
297	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
298	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
299	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
300	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
301	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
302	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
303	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
304	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
305	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
306	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
307	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
308	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
309	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
310	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
311	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
312	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
313	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
314	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
315	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
316	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
317	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
318	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
319	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
320	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
321	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
322	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
323	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
324	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
325	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
326	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
327	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
328	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
329	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
330	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
331	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
332	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
333	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
334	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
335	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
336	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
337	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
338	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
339	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
340	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
341	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
342	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
343	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
344	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
345	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
346	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
347	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
348	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
349	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
350	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
351	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
352	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
353	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
354
355	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
356	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
357	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
358	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
359
360	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
361	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
362	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
363	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
364	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
365	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
366	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
367	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
368	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
369	# endif
370	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
371	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
372	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
373	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
374
375	SSMFIELD_ENTRY_TERM()
376	};
377
378	/**
379	* SSM descriptor table for the VGAState.svga structure.
380	*/
381	static SSMFIELD const g_aVGAStateSVGAFields[] =
382	{
383	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
384	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
385	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
386	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
387	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
388	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
389	SSMFIELD_ENTRY( VMSVGAState, fBusy),
390	SSMFIELD_ENTRY( VMSVGAState, fTraces),
391	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
392	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
393	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
394	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
395	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
396	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
397	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
398	SSMFIELD_ENTRY( VMSVGAState, u32DeviceCaps),
399	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
400	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
401	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
402	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
403	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
404	SSMFIELD_ENTRY( VMSVGAState, uWidth),
405	SSMFIELD_ENTRY( VMSVGAState, uHeight),
406	SSMFIELD_ENTRY( VMSVGAState, uBpp),
407	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
408	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
409	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
410	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
411	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
412	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
413	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
414	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
415	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
416	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
417	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
421	SSMFIELD_ENTRY_VER( VMSVGAState, au32DevCaps, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
422	SSMFIELD_ENTRY_VER( VMSVGAState, u32DevCapIndex, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
423	SSMFIELD_ENTRY_VER( VMSVGAState, u32RegCommandLow, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
424	SSMFIELD_ENTRY_VER( VMSVGAState, u32RegCommandHigh, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
425
426	SSMFIELD_ENTRY_TERM()
427	};
428	#endif /* IN_RING3 */
429
430
431	/*********************************************************************************************************************************
432	* Internal Functions *
433	*********************************************************************************************************************************/
434	#ifdef IN_RING3
435	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
436	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
437	uint32_t uVersion, uint32_t uPass);
438	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
439	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx);
440	static void vmsvgaR3PowerOnDevice(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, bool fLoadState);
441	#endif /* IN_RING3 */
442
443
444	#define SVGA_CASE_ID2STR(idx) case idx: return #idx
445	#if defined(LOG_ENABLED)
446	/**
447	* Index register string name lookup
448	*
449	* @returns Index register string or "UNKNOWN"
450	* @param pThis The shared VGA/VMSVGA state.
451	* @param idxReg The index register.
452	*/
453	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
454	{
455	AssertCompile(SVGA_REG_TOP == 77); /* Ensure that the correct headers are used. */
456	switch (idxReg)
457	{
458	SVGA_CASE_ID2STR(SVGA_REG_ID);
459	SVGA_CASE_ID2STR(SVGA_REG_ENABLE);
460	SVGA_CASE_ID2STR(SVGA_REG_WIDTH);
461	SVGA_CASE_ID2STR(SVGA_REG_HEIGHT);
462	SVGA_CASE_ID2STR(SVGA_REG_MAX_WIDTH);
463	SVGA_CASE_ID2STR(SVGA_REG_MAX_HEIGHT);
464	SVGA_CASE_ID2STR(SVGA_REG_DEPTH);
465	SVGA_CASE_ID2STR(SVGA_REG_BITS_PER_PIXEL); /* Current bpp in the guest */
466	SVGA_CASE_ID2STR(SVGA_REG_PSEUDOCOLOR);
467	SVGA_CASE_ID2STR(SVGA_REG_RED_MASK);
468	SVGA_CASE_ID2STR(SVGA_REG_GREEN_MASK);
469	SVGA_CASE_ID2STR(SVGA_REG_BLUE_MASK);
470	SVGA_CASE_ID2STR(SVGA_REG_BYTES_PER_LINE);
471	SVGA_CASE_ID2STR(SVGA_REG_FB_START); /* (Deprecated) */
472	SVGA_CASE_ID2STR(SVGA_REG_FB_OFFSET);
473	SVGA_CASE_ID2STR(SVGA_REG_VRAM_SIZE);
474	SVGA_CASE_ID2STR(SVGA_REG_FB_SIZE);
475
476	/* ID 0 implementation only had the above registers, then the palette */
477	SVGA_CASE_ID2STR(SVGA_REG_CAPABILITIES);
478	SVGA_CASE_ID2STR(SVGA_REG_MEM_START); /* (Deprecated) */
479	SVGA_CASE_ID2STR(SVGA_REG_MEM_SIZE);
480	SVGA_CASE_ID2STR(SVGA_REG_CONFIG_DONE); /* Set when memory area configured */
481	SVGA_CASE_ID2STR(SVGA_REG_SYNC); /* See "FIFO Synchronization Registers" */
482	SVGA_CASE_ID2STR(SVGA_REG_BUSY); /* See "FIFO Synchronization Registers" */
483	SVGA_CASE_ID2STR(SVGA_REG_GUEST_ID); /* Set guest OS identifier */
484	SVGA_CASE_ID2STR(SVGA_REG_DEAD); /* (Deprecated) SVGA_REG_CURSOR_ID. */
485	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_X); /* (Deprecated) */
486	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_Y); /* (Deprecated) */
487	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ON); /* (Deprecated) */
488	SVGA_CASE_ID2STR(SVGA_REG_HOST_BITS_PER_PIXEL); /* (Deprecated) */
489	SVGA_CASE_ID2STR(SVGA_REG_SCRATCH_SIZE); /* Number of scratch registers */
490	SVGA_CASE_ID2STR(SVGA_REG_MEM_REGS); /* Number of FIFO registers */
491	SVGA_CASE_ID2STR(SVGA_REG_NUM_DISPLAYS); /* (Deprecated) */
492	SVGA_CASE_ID2STR(SVGA_REG_PITCHLOCK); /* Fixed pitch for all modes */
493	SVGA_CASE_ID2STR(SVGA_REG_IRQMASK); /* Interrupt mask */
494
495	/* Legacy multi-monitor support */
496	SVGA_CASE_ID2STR(SVGA_REG_NUM_GUEST_DISPLAYS); /* Number of guest displays in X/Y direction */
497	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_ID); /* Display ID for the following display attributes */
498	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_IS_PRIMARY); /* Whether this is a primary display */
499	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_X); /* The display position x */
500	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_Y); /* The display position y */
501	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_WIDTH); /* The display's width */
502	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_HEIGHT); /* The display's height */
503
504	SVGA_CASE_ID2STR(SVGA_REG_GMR_ID);
505	SVGA_CASE_ID2STR(SVGA_REG_GMR_DESCRIPTOR);
506	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_IDS);
507	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
508
509	SVGA_CASE_ID2STR(SVGA_REG_TRACES); /* Enable trace-based updates even when FIFO is on */
510	SVGA_CASE_ID2STR(SVGA_REG_GMRS_MAX_PAGES); /* Maximum number of 4KB pages for all GMRs */
511	SVGA_CASE_ID2STR(SVGA_REG_MEMORY_SIZE); /* Total dedicated device memory excluding FIFO */
512	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_LOW); /* Lower 32 bits and submits commands */
513	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_HIGH); /* Upper 32 bits of command buffer PA */
514	SVGA_CASE_ID2STR(SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); /* Max primary memory */
515	SVGA_CASE_ID2STR(SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); /* Suggested limit on mob mem */
516	SVGA_CASE_ID2STR(SVGA_REG_DEV_CAP); /* Write dev cap index, read value */
517	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_LOW);
518	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_HIGH);
519	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_WIDTH);
520	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_HEIGHT);
521	SVGA_CASE_ID2STR(SVGA_REG_MOB_MAX_SIZE);
522	SVGA_CASE_ID2STR(SVGA_REG_BLANK_SCREEN_TARGETS);
523	SVGA_CASE_ID2STR(SVGA_REG_CAP2);
524	SVGA_CASE_ID2STR(SVGA_REG_DEVEL_CAP);
525	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_ID);
526	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION1);
527	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION2);
528	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION3);
529	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MOBID);
530	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_BYTE_SIZE);
531	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_DIMENSION);
532	SVGA_CASE_ID2STR(SVGA_REG_FIFO_CAPS);
533	SVGA_CASE_ID2STR(SVGA_REG_FENCE);
534	SVGA_CASE_ID2STR(SVGA_REG_RESERVED1);
535	SVGA_CASE_ID2STR(SVGA_REG_RESERVED2);
536	SVGA_CASE_ID2STR(SVGA_REG_RESERVED3);
537	SVGA_CASE_ID2STR(SVGA_REG_RESERVED4);
538	SVGA_CASE_ID2STR(SVGA_REG_RESERVED5);
539	SVGA_CASE_ID2STR(SVGA_REG_SCREENDMA);
540	SVGA_CASE_ID2STR(SVGA_REG_GBOBJECT_MEM_SIZE_KB);
541	SVGA_CASE_ID2STR(SVGA_REG_TOP); /* Must be 1 more than the last register */
542
543	default:
544	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
545	return "SVGA_SCRATCH_BASE reg";
546	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
547	return "SVGA_PALETTE_BASE reg";
548	return "UNKNOWN";
549	}
550	}
551	#endif /* LOG_ENABLED */
552
553	#if defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D))
554	static const char *vmsvgaDevCapIndexToString(SVGA3dDevCapIndex idxDevCap)
555	{
556	AssertCompile(SVGA3D_DEVCAP_MAX == 260);
557	switch (idxDevCap)
558	{
559	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_INVALID);
560	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_3D);
561	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LIGHTS);
562	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURES);
563	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CLIP_PLANES);
564	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER_VERSION);
565	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER);
566	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION);
567	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER);
568	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_RENDER_TARGETS);
569	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S23E8_TEXTURES);
570	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S10E5_TEXTURES);
571	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND);
572	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D16_BUFFER_FORMAT);
573	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT);
574	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT);
575	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_QUERY_TYPES);
576	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING);
577	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_POINT_SIZE);
578	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SHADER_TEXTURES);
579	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
580	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
581	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VOLUME_EXTENT);
582	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT);
583	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO);
584	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY);
585	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT);
586	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_INDEX);
587	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS);
588	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS);
589	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS);
590	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS);
591	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_OPS);
592	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);
593	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8);
594	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10);
595	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5);
596	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5);
597	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4);
598	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R5G6B5);
599	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16);
600	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8);
601	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ALPHA8);
602	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8);
603	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D16);
604	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8);
605	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8);
606	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT1);
607	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT2);
608	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT3);
609	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT4);
610	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT5);
611	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8);
612	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10);
613	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8);
614	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8);
615	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_CxV8U8);
616	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S10E5);
617	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S23E8);
618	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5);
619	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8);
620	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5);
621	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8);
622	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MISSING62);
623	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES);
624	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS);
625	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_V16U16);
626	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_G16R16);
627	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16);
628	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_UYVY);
629	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YUY2);
630	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD4); /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
631	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD5); /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
632	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD7); /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
633	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD6); /* SVGA3D_DEVCAP_SUPERSAMPLE */
634	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_AUTOGENMIPMAPS);
635	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_NV12);
636	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD10); /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
637	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CONTEXT_IDS);
638	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SURFACE_IDS);
639	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF16);
640	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF24);
641	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT);
642	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI1);
643	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI2);
644	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD1);
645	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD8); /* SVGA3D_DEVCAP_VIDEO_DECODE */
646	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD9); /* SVGA3D_DEVCAP_VIDEO_PROCESS */
647	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_AA);
648	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_STIPPLE);
649	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LINE_WIDTH);
650	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH);
651	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YV12);
652	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD3); /* Old SVGA3D_DEVCAP_LOGICOPS */
653	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TS_COLOR_KEY);
654	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD2);
655	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXCONTEXT);
656	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD11); /* SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE */
657	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS);
658	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS);
659	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_PROVOKING_VERTEX);
660	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8R8G8B8);
661	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8R8G8B8);
662	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R5G6B5);
663	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X1R5G5B5);
664	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A1R5G5B5);
665	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A4R4G4B4);
666	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D32);
667	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D16);
668	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8);
669	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D15S1);
670	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8);
671	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4);
672	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE16);
673	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8);
674	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT1);
675	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT2);
676	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT3);
677	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT4);
678	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT5);
679	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPU8V8);
680	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5);
681	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8);
682	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1);
683	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5);
684	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8);
685	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2R10G10B10);
686	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V8U8);
687	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8);
688	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_CxV8U8);
689	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8L8V8U8);
690	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2W10V10U10);
691	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ALPHA8);
692	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S10E5);
693	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S23E8);
694	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S10E5);
695	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S23E8);
696	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUFFER);
697	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24X8);
698	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V16U16);
699	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G16R16);
700	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A16B16G16R16);
701	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_UYVY);
702	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YUY2);
703	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_NV12);
704	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2); /* SVGA3D_DEVCAP_DXFMT_AYUV */
705	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS);
706	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT);
707	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT);
708	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS);
709	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT);
710	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT);
711	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT);
712	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS);
713	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT);
714	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM);
715	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT);
716	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS);
717	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_UINT);
718	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_SINT);
719	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS);
720	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT);
721	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24);
722	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT);
723	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS);
724	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT);
725	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT);
726	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS);
727	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM);
728	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB);
729	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT);
730	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT);
731	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS);
732	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UINT);
733	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SINT);
734	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS);
735	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT);
736	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_UINT);
737	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_SINT);
738	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS);
739	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT);
740	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8);
741	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X24_G8_UINT);
742	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS);
743	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM);
744	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UINT);
745	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SINT);
746	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS);
747	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UNORM);
748	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UINT);
749	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SNORM);
750	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SINT);
751	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS);
752	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UNORM);
753	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UINT);
754	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SNORM);
755	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SINT);
756	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_P8);
757	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP);
758	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM);
759	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM);
760	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS);
761	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB);
762	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS);
763	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB);
764	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS);
765	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB);
766	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS);
767	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI1);
768	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_SNORM);
769	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS);
770	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI2);
771	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_SNORM);
772	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM);
773	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS);
774	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB);
775	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS);
776	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB);
777	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF16);
778	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF24);
779	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT);
780	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YV12);
781	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT);
782	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT);
783	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM);
784	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT);
785	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM);
786	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM);
787	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT);
788	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM);
789	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM);
790	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT);
791	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM);
792	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_FLOAT);
793	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D16_UNORM);
794	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8_UNORM);
795	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM);
796	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM);
797	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM);
798	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM);
799	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM);
800	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM);
801	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM);
802	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_UNORM);
803	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_UNORM);
804	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM41);
805	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_2X);
806	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_4X);
807	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MS_FULL_QUALITY);
808	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGICOPS);
809	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGIC_BLENDOPS);
810	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_1);
811	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS);
812	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_UF16);
813	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_SF16);
814	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS);
815	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM);
816	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB);
817	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_2);
818	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM5);
819	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_8X);
820
821	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX);
822
823	default:
824	break;
825	}
826	return "UNKNOWN";
827	}
828	#endif /* defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D)) */
829	#undef SVGA_CASE_ID2STR
830
831
832	#ifdef IN_RING3
833
834	/**
835	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
836	*/
837	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
838	{
839	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
840	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
841
842	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
843	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
844
845	/** @todo Test how it interacts with multiple screen objects. */
846	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
847	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
848	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
849
850	if (x < uWidth)
851	{
852	pThis->svga.viewport.x = x;
853	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
854	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
855	}
856	else
857	{
858	pThis->svga.viewport.x = uWidth;
859	pThis->svga.viewport.cx = 0;
860	pThis->svga.viewport.xRight = uWidth;
861	}
862	if (y < uHeight)
863	{
864	pThis->svga.viewport.y = y;
865	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
866	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
867	pThis->svga.viewport.yHighWC = uHeight - y;
868	}
869	else
870	{
871	pThis->svga.viewport.y = uHeight;
872	pThis->svga.viewport.cy = 0;
873	pThis->svga.viewport.yLowWC = 0;
874	pThis->svga.viewport.yHighWC = 0;
875	}
876
877	# ifdef VBOX_WITH_VMSVGA3D
878	/*
879	* Now inform the 3D backend.
880	*/
881	if (pThis->svga.f3DEnabled)
882	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
883	# else
884	RT_NOREF(OldViewport);
885	# endif
886	}
887
888
889	/**
890	* Updating screen information in API
891	*
892	* @param pThis The The shared VGA/VMSVGA instance data.
893	* @param pThisCC The VGA/VMSVGA state for ring-3.
894	*/
895	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
896	{
897	int rc;
898
899	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
900
901	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
902	{
903	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
904	if (!pScreen->fModified)
905	continue;
906
907	pScreen->fModified = false;
908
909	VBVAINFOVIEW view;
910	RT_ZERO(view);
911	view.u32ViewIndex = pScreen->idScreen;
912	// view.u32ViewOffset = 0;
913	view.u32ViewSize = pThis->vram_size;
914	view.u32MaxScreenSize = pThis->vram_size;
915
916	VBVAINFOSCREEN screen;
917	RT_ZERO(screen);
918	screen.u32ViewIndex = pScreen->idScreen;
919
920	if (pScreen->fDefined)
921	{
922	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
923	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
924	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
925	{
926	Assert(pThis->svga.fGFBRegisters);
927	continue;
928	}
929
930	screen.i32OriginX = pScreen->xOrigin;
931	screen.i32OriginY = pScreen->yOrigin;
932	screen.u32StartOffset = pScreen->offVRAM;
933	screen.u32LineSize = pScreen->cbPitch;
934	screen.u32Width = pScreen->cWidth;
935	screen.u32Height = pScreen->cHeight;
936	screen.u16BitsPerPixel = pScreen->cBpp;
937	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
938	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
939	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
940	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
941	}
942	else
943	{
944	/* Screen is destroyed. */
945	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
946	}
947
948	void *pvVRAM = pScreen->pvScreenBitmap ? pScreen->pvScreenBitmap : pThisCC->pbVRam;
949	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pvVRAM, /fResetInputMapping=/ true);
950	AssertRC(rc);
951	}
952	}
953
954
955	/**
956	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
957	*
958	* Used to update screen offsets (positions) since appearently vmwgfx fails to
959	* pass correct offsets thru FIFO.
960	*/
961	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
962	{
963	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
964	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
965	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
966
967	AssertReturnVoid(pSVGAState);
968
969	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
970	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
971	for (uint32_t i = 0; i < cPositions; ++i)
972	{
973	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
974	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
975	continue;
976
977	if (paPositions[i].x == -1)
978	continue;
979	if (paPositions[i].y == -1)
980	continue;
981
982	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
983	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
984	pSVGAState->aScreens[i].fModified = true;
985	}
986
987	vmsvgaR3VBVAResize(pThis, pThisCC);
988	}
989
990	#endif /* IN_RING3 */
991
992	/**
993	* Read port register
994	*
995	* @returns VBox status code.
996	* @param pDevIns The device instance.
997	* @param pThis The shared VGA/VMSVGA state.
998	* @param pu32 Where to store the read value
999	*/
1000	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
1001	{
1002	#ifdef IN_RING3
1003	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
1004	#endif
1005	int rc = VINF_SUCCESS;
1006	*pu32 = 0;
1007
1008	/* Rough index register validation. */
1009	uint32_t idxReg = pThis->svga.u32IndexReg;
1010	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1011	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1012	VINF_IOM_R3_IOPORT_READ);
1013	#else
1014	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1015	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
1016	VINF_SUCCESS);
1017	#endif
1018	RT_UNTRUSTED_VALIDATED_FENCE();
1019
1020	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1021	if ( idxReg >= SVGA_REG_ID_0_TOP
1022	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1023	{
1024	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1025	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1026	}
1027
1028	switch (idxReg)
1029	{
1030	case SVGA_REG_ID:
1031	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
1032	*pu32 = pThis->svga.u32SVGAId;
1033	break;
1034
1035	case SVGA_REG_ENABLE:
1036	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
1037	*pu32 = pThis->svga.fEnabled;
1038	break;
1039
1040	case SVGA_REG_WIDTH:
1041	{
1042	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
1043	if ( pThis->svga.fEnabled
1044	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
1045	*pu32 = pThis->svga.uWidth;
1046	else
1047	{
1048	#ifndef IN_RING3
1049	rc = VINF_IOM_R3_IOPORT_READ;
1050	#else
1051	*pu32 = pThisCC->pDrv->cx;
1052	#endif
1053	}
1054	break;
1055	}
1056
1057	case SVGA_REG_HEIGHT:
1058	{
1059	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
1060	if ( pThis->svga.fEnabled
1061	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1062	*pu32 = pThis->svga.uHeight;
1063	else
1064	{
1065	#ifndef IN_RING3
1066	rc = VINF_IOM_R3_IOPORT_READ;
1067	#else
1068	*pu32 = pThisCC->pDrv->cy;
1069	#endif
1070	}
1071	break;
1072	}
1073
1074	case SVGA_REG_MAX_WIDTH:
1075	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
1076	*pu32 = pThis->svga.u32MaxWidth;
1077	break;
1078
1079	case SVGA_REG_MAX_HEIGHT:
1080	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
1081	*pu32 = pThis->svga.u32MaxHeight;
1082	break;
1083
1084	case SVGA_REG_DEPTH:
1085	/* This returns the color depth of the current mode. */
1086	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
1087	switch (pThis->svga.uBpp)
1088	{
1089	case 15:
1090	case 16:
1091	case 24:
1092	*pu32 = pThis->svga.uBpp;
1093	break;
1094
1095	default:
1096	case 32:
1097	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
1098	break;
1099	}
1100	break;
1101
1102	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1103	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1104	*pu32 = pThis->svga.uHostBpp;
1105	break;
1106
1107	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1108	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1109	*pu32 = pThis->svga.uBpp;
1110	break;
1111
1112	case SVGA_REG_PSEUDOCOLOR:
1113	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1114	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1115	break;
1116
1117	case SVGA_REG_RED_MASK:
1118	case SVGA_REG_GREEN_MASK:
1119	case SVGA_REG_BLUE_MASK:
1120	{
1121	uint32_t uBpp;
1122
1123	if (pThis->svga.fEnabled)
1124	uBpp = pThis->svga.uBpp;
1125	else
1126	uBpp = pThis->svga.uHostBpp;
1127
1128	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1129	switch (uBpp)
1130	{
1131	case 8:
1132	u32RedMask = 0x07;
1133	u32GreenMask = 0x38;
1134	u32BlueMask = 0xc0;
1135	break;
1136
1137	case 15:
1138	u32RedMask = 0x0000001f;
1139	u32GreenMask = 0x000003e0;
1140	u32BlueMask = 0x00007c00;
1141	break;
1142
1143	case 16:
1144	u32RedMask = 0x0000001f;
1145	u32GreenMask = 0x000007e0;
1146	u32BlueMask = 0x0000f800;
1147	break;
1148
1149	case 24:
1150	case 32:
1151	default:
1152	u32RedMask = 0x00ff0000;
1153	u32GreenMask = 0x0000ff00;
1154	u32BlueMask = 0x000000ff;
1155	break;
1156	}
1157	switch (idxReg)
1158	{
1159	case SVGA_REG_RED_MASK:
1160	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1161	*pu32 = u32RedMask;
1162	break;
1163
1164	case SVGA_REG_GREEN_MASK:
1165	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1166	*pu32 = u32GreenMask;
1167	break;
1168
1169	case SVGA_REG_BLUE_MASK:
1170	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1171	*pu32 = u32BlueMask;
1172	break;
1173	}
1174	break;
1175	}
1176
1177	case SVGA_REG_BYTES_PER_LINE:
1178	{
1179	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1180	if ( pThis->svga.fEnabled
1181	&& pThis->svga.cbScanline)
1182	*pu32 = pThis->svga.cbScanline;
1183	else
1184	{
1185	#ifndef IN_RING3
1186	rc = VINF_IOM_R3_IOPORT_READ;
1187	#else
1188	*pu32 = pThisCC->pDrv->cbScanline;
1189	#endif
1190	}
1191	break;
1192	}
1193
1194	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1195	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1196	*pu32 = pThis->vram_size;
1197	break;
1198
1199	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1200	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1201	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1202	*pu32 = pThis->GCPhysVRAM;
1203	break;
1204
1205	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1206	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1207	/* Always zero in our case. */
1208	*pu32 = 0;
1209	break;
1210
1211	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1212	{
1213	#ifndef IN_RING3
1214	rc = VINF_IOM_R3_IOPORT_READ;
1215	#else
1216	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1217
1218	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1219	if ( pThis->svga.fEnabled
1220	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1221	{
1222	/* Hardware enabled; return real framebuffer size .*/
1223	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1224	}
1225	else
1226	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1227
1228	pu32 = RT_MIN(pThis->vram_size, pu32);
1229	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1230	#endif
1231	break;
1232	}
1233
1234	case SVGA_REG_CAPABILITIES:
1235	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1236	*pu32 = pThis->svga.u32DeviceCaps;
1237	break;
1238
1239	case SVGA_REG_MEM_START: /* FIFO start */
1240	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1241	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1242	*pu32 = pThis->svga.GCPhysFIFO;
1243	break;
1244
1245	case SVGA_REG_MEM_SIZE: /* FIFO size */
1246	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1247	*pu32 = pThis->svga.cbFIFO;
1248	break;
1249
1250	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1251	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1252	*pu32 = pThis->svga.fConfigured;
1253	break;
1254
1255	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1256	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1257	*pu32 = 0;
1258	break;
1259
1260	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1261	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1262	if (pThis->svga.fBusy)
1263	{
1264	#ifndef IN_RING3
1265	/* Go to ring-3 and halt the CPU. */
1266	rc = VINF_IOM_R3_IOPORT_READ;
1267	RT_NOREF(pDevIns);
1268	break;
1269	#else /* IN_RING3 */
1270	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1271	/* The guest is basically doing a HLT via the device here, but with
1272	a special wake up condition on FIFO completion. */
1273	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1274	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1275	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1276	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1277	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1278	if (pThis->svga.fBusy)
1279	{
1280	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1281	rc = PDMDevHlpVMWaitForDeviceReady(pDevIns, idCpu);
1282	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1283	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
1284	}
1285	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1286	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1287	# else
1288
1289	/* Delay the EMT a bit so the FIFO and others can get some work done.
1290	This used to be a crude 50 ms sleep. The current code tries to be
1291	more efficient, but the consept is still very crude. */
1292	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1293	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1294	RTThreadYield();
1295	if (pThis->svga.fBusy)
1296	{
1297	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1298
1299	if (pThis->svga.fBusy && cRefs == 1)
1300	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1301	if (pThis->svga.fBusy)
1302	{
1303	/** @todo If this code is going to stay, we need to call into the halt/wait
1304	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1305	* suffer when the guest is polling on a busy FIFO. */
1306	uint64_t uIgnored1, uIgnored2;
1307	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns), &uIgnored1, &uIgnored2);
1308	if (cNsMaxWait >= RT_NS_100US)
1309	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1310	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1311	RT_MIN(cNsMaxWait, RT_NS_10MS));
1312	}
1313
1314	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1315	}
1316	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1317	# endif
1318	*pu32 = pThis->svga.fBusy != 0;
1319	#endif /* IN_RING3 */
1320	}
1321	else
1322	*pu32 = false;
1323	break;
1324
1325	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1326	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1327	*pu32 = pThis->svga.u32GuestId;
1328	break;
1329
1330	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1331	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1332	*pu32 = pThis->svga.cScratchRegion;
1333	break;
1334
1335	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1336	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1337	*pu32 = SVGA_FIFO_NUM_REGS;
1338	break;
1339
1340	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1341	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1342	*pu32 = pThis->svga.u32PitchLock;
1343	break;
1344
1345	case SVGA_REG_IRQMASK: /* Interrupt mask */
1346	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1347	*pu32 = pThis->svga.u32IrqMask;
1348	break;
1349
1350	/* See "Guest memory regions" below. */
1351	case SVGA_REG_GMR_ID:
1352	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1353	*pu32 = pThis->svga.u32CurrentGMRId;
1354	break;
1355
1356	case SVGA_REG_GMR_DESCRIPTOR:
1357	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1358	/* Write only */
1359	*pu32 = 0;
1360	break;
1361
1362	case SVGA_REG_GMR_MAX_IDS:
1363	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1364	*pu32 = pThis->svga.cGMR;
1365	break;
1366
1367	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1368	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1369	*pu32 = VMSVGA_MAX_GMR_PAGES;
1370	break;
1371
1372	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1373	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1374	*pu32 = pThis->svga.fTraces;
1375	break;
1376
1377	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1378	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1379	*pu32 = VMSVGA_MAX_GMR_PAGES;
1380	break;
1381
1382	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1383	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1384	*pu32 = VMSVGA_SURFACE_SIZE;
1385	break;
1386
1387	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1388	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1389	break;
1390
1391	/* Mouse cursor support. */
1392	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
1393	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1394	*pu32 = pThis->svga.uCursorID;
1395	break;
1396
1397	case SVGA_REG_CURSOR_X:
1398	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1399	*pu32 = pThis->svga.uCursorX;
1400	break;
1401
1402	case SVGA_REG_CURSOR_Y:
1403	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1404	*pu32 = pThis->svga.uCursorY;
1405	break;
1406
1407	case SVGA_REG_CURSOR_ON:
1408	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1409	*pu32 = pThis->svga.uCursorOn;
1410	break;
1411
1412	/* Legacy multi-monitor support */
1413	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1414	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1415	*pu32 = 1;
1416	break;
1417
1418	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1419	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1420	*pu32 = 0;
1421	break;
1422
1423	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1424	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1425	*pu32 = 0;
1426	break;
1427
1428	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1429	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1430	*pu32 = 0;
1431	break;
1432
1433	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1434	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1435	*pu32 = 0;
1436	break;
1437
1438	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1439	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1440	*pu32 = pThis->svga.uWidth;
1441	break;
1442
1443	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1444	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1445	*pu32 = pThis->svga.uHeight;
1446	break;
1447
1448	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1449	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1450	/* We must return something sensible here otherwise the Linux driver
1451	will take a legacy code path without 3d support. This number also
1452	limits how many screens Linux guests will allow. */
1453	*pu32 = pThis->cMonitors;
1454	break;
1455
1456	/*
1457	* SVGA_CAP_GBOBJECTS+ registers.
1458	*/
1459	case SVGA_REG_COMMAND_LOW:
1460	/* Lower 32 bits of command buffer physical address. */
1461	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowRd);
1462	*pu32 = pThis->svga.u32RegCommandLow;
1463	break;
1464
1465	case SVGA_REG_COMMAND_HIGH:
1466	/* Upper 32 bits of command buffer PA. */
1467	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighRd);
1468	*pu32 = pThis->svga.u32RegCommandHigh;
1469	break;
1470
1471	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
1472	/* Max primary (screen) memory. */
1473	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxPrimBBMemRd);
1474	pu32 = pThis->vram_size; /* @todo Maybe half VRAM? */
1475	break;
1476
1477	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
1478	/* Suggested limit on mob mem (i.e. size of the guest mapped VRAM in KB) */
1479	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGBMemSizeRd);
1480	*pu32 = pThis->vram_size / 1024;
1481	break;
1482
1483	case SVGA_REG_DEV_CAP:
1484	/* Write dev cap index, read value */
1485	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapRd);
1486	if (pThis->svga.u32DevCapIndex < RT_ELEMENTS(pThis->svga.au32DevCaps))
1487	{
1488	RT_UNTRUSTED_VALIDATED_FENCE();
1489	*pu32 = pThis->svga.au32DevCaps[pThis->svga.u32DevCapIndex];
1490	}
1491	else
1492	*pu32 = 0;
1493	break;
1494
1495	case SVGA_REG_CMD_PREPEND_LOW:
1496	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowRd);
1497	pu32 = 0; / Not supported. */
1498	break;
1499
1500	case SVGA_REG_CMD_PREPEND_HIGH:
1501	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighRd);
1502	pu32 = 0; / Not supported. */
1503	break;
1504
1505	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
1506	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxWidthRd);
1507	*pu32 = pThis->svga.u32MaxWidth;
1508	break;
1509
1510	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
1511	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxHeightRd);
1512	*pu32 = pThis->svga.u32MaxHeight;
1513	break;
1514
1515	case SVGA_REG_MOB_MAX_SIZE:
1516	/* Essentially the max texture size */
1517	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMobMaxSizeRd);
1518	pu32 = _128M; /* @todo Some actual value. Probably the mapped VRAM size. */
1519	break;
1520
1521	default:
1522	{
1523	uint32_t offReg;
1524	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1525	{
1526	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1527	RT_UNTRUSTED_VALIDATED_FENCE();
1528	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1529	}
1530	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1531	{
1532	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1533	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1534	RT_UNTRUSTED_VALIDATED_FENCE();
1535	uint32_t u32 = pThis->last_palette[offReg / 3];
1536	switch (offReg % 3)
1537	{
1538	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1539	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1540	case 2: pu32 = u32 & 0xff; break; / blue */
1541	}
1542	}
1543	else
1544	{
1545	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1546	rc = VINF_IOM_R3_IOPORT_READ;
1547	#else
1548	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1549
1550	/* Do not assert. The guest might be reading all registers. */
1551	LogFunc(("Unknown reg=%#x\n", idxReg));
1552	#endif
1553	}
1554	break;
1555	}
1556	}
1557	LogFlow(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1558	return rc;
1559	}
1560
1561	#ifdef IN_RING3
1562	/**
1563	* Apply the current resolution settings to change the video mode.
1564	*
1565	* @returns VBox status code.
1566	* @param pThis The shared VGA state.
1567	* @param pThisCC The ring-3 VGA state.
1568	*/
1569	int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1570	{
1571	/* Always do changemode on FIFO thread. */
1572	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1573
1574	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1575
1576	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1577
1578	if (pThis->svga.fGFBRegisters)
1579	{
1580	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1581	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1582	* deletes all screens other than screen #0, and redefines screen
1583	* #0 according to the specified mode. Drivers that use
1584	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1585	*/
1586
1587	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1588	pScreen->fDefined = true;
1589	pScreen->fModified = true;
1590	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1591	pScreen->idScreen = 0;
1592	pScreen->xOrigin = 0;
1593	pScreen->yOrigin = 0;
1594	pScreen->offVRAM = 0;
1595	pScreen->cbPitch = pThis->svga.cbScanline;
1596	pScreen->cWidth = pThis->svga.uWidth;
1597	pScreen->cHeight = pThis->svga.uHeight;
1598	pScreen->cBpp = pThis->svga.uBpp;
1599
1600	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1601	{
1602	/* Delete screen. */
1603	pScreen = &pSVGAState->aScreens[iScreen];
1604	if (pScreen->fDefined)
1605	{
1606	pScreen->fModified = true;
1607	pScreen->fDefined = false;
1608	}
1609	}
1610	}
1611	else
1612	{
1613	/* "If Screen Objects are supported, they can be used to fully
1614	* replace the functionality provided by the framebuffer registers
1615	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1616	*/
1617	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1618	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1619	pThis->svga.uBpp = pThis->svga.uHostBpp;
1620	}
1621
1622	vmsvgaR3VBVAResize(pThis, pThisCC);
1623
1624	/* Last stuff. For the VGA device screenshot. */
1625	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1626	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1627	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1628	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1629	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1630
1631	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1632	if ( pThis->svga.viewport.cx == 0
1633	&& pThis->svga.viewport.cy == 0)
1634	{
1635	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1636	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1637	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1638	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1639	pThis->svga.viewport.yLowWC = 0;
1640	}
1641
1642	return VINF_SUCCESS;
1643	}
1644
1645	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1646	{
1647	VBVACMDHDR cmd;
1648	cmd.x = (int16_t)(pScreen->xOrigin + x);
1649	cmd.y = (int16_t)(pScreen->yOrigin + y);
1650	cmd.w = (uint16_t)w;
1651	cmd.h = (uint16_t)h;
1652
1653	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1654	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1655	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1656	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1657
1658	return VINF_SUCCESS;
1659	}
1660
1661	#endif /* IN_RING3 */
1662	#if defined(IN_RING0) \|\| defined(IN_RING3)
1663
1664	/**
1665	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1666	*
1667	* @param pThis The shared VGA/VMSVGA instance data.
1668	* @param pThisCC The VGA/VMSVGA state for the current context.
1669	* @param fState The busy state.
1670	*/
1671	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1672	{
1673	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1674
1675	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1676	{
1677	/* Race / unfortunately scheduling. Highly unlikly. */
1678	uint32_t cLoops = 64;
1679	do
1680	{
1681	ASMNopPause();
1682	fState = (pThis->svga.fBusy != 0);
1683	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1684	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1685	}
1686	}
1687
1688
1689	/**
1690	* Update the scanline pitch in response to the guest changing mode
1691	* width/bpp.
1692	*
1693	* @param pThis The shared VGA/VMSVGA state.
1694	* @param pThisCC The VGA/VMSVGA state for the current context.
1695	*/
1696	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1697	{
1698	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1699	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1700	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1701	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1702
1703	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1704	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1705	* location but it has a different meaning.
1706	*/
1707	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1708	uFifoPitchLock = 0;
1709
1710	/* Sanitize values. */
1711	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1712	uFifoPitchLock = 0;
1713	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1714	uRegPitchLock = 0;
1715
1716	/* Prefer the register value to the FIFO value.*/
1717	if (uRegPitchLock)
1718	pThis->svga.cbScanline = uRegPitchLock;
1719	else if (uFifoPitchLock)
1720	pThis->svga.cbScanline = uFifoPitchLock;
1721	else
1722	pThis->svga.cbScanline = (uint32_t)pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1723
1724	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1725	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1726	}
1727
1728	#endif /* IN_RING0 \|\| IN_RING3 */
1729
1730	#ifdef IN_RING3
1731
1732	/**
1733	* Sends cursor position and visibility information from legacy
1734	* SVGA registers to the front-end.
1735	*/
1736	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1737	{
1738	/*
1739	* Writing the X/Y/ID registers does not trigger changes; only writing the
1740	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1741	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1742	* register if they don't have to.
1743	*/
1744	uint32_t x, y, idScreen;
1745	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1746
1747	x = pThis->svga.uCursorX;
1748	y = pThis->svga.uCursorY;
1749	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1750
1751	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1752	* were extended as follows:
1753	*
1754	* SVGA_CURSOR_ON_HIDE 0
1755	* SVGA_CURSOR_ON_SHOW 1
1756	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1757	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1758	*
1759	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1760	* distinguish between the non-zero values but still remember them.
1761	*/
1762	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1763	{
1764	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1765	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1766	}
1767	pThis->svga.uCursorOn = uCursorOn;
1768	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1769	}
1770
1771	#endif /* IN_RING3 */
1772
1773
1774	/**
1775	* Write port register
1776	*
1777	* @returns Strict VBox status code.
1778	* @param pDevIns The device instance.
1779	* @param pThis The shared VGA/VMSVGA state.
1780	* @param pThisCC The VGA/VMSVGA state for the current context.
1781	* @param u32 Value to write
1782	*/
1783	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1784	{
1785	#ifdef IN_RING3
1786	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1787	#endif
1788	VBOXSTRICTRC rc = VINF_SUCCESS;
1789	RT_NOREF(pThisCC);
1790
1791	/* Rough index register validation. */
1792	uint32_t idxReg = pThis->svga.u32IndexReg;
1793	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1794	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1795	VINF_IOM_R3_IOPORT_WRITE);
1796	#else
1797	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1798	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1799	VINF_SUCCESS);
1800	#endif
1801	RT_UNTRUSTED_VALIDATED_FENCE();
1802
1803	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1804	if ( idxReg >= SVGA_REG_ID_0_TOP
1805	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1806	{
1807	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1808	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1809	}
1810	#ifdef LOG_ENABLED
1811	if (idxReg != SVGA_REG_DEV_CAP)
1812	LogFlow(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1813	else
1814	LogFlow(("vmsvgaWritePort index=%s (%d) val=%s (%d)\n", vmsvgaIndexToString(pThis, idxReg), idxReg, vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)u32), u32));
1815	#endif
1816	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1817	switch (idxReg)
1818	{
1819	case SVGA_REG_WIDTH:
1820	case SVGA_REG_HEIGHT:
1821	case SVGA_REG_PITCHLOCK:
1822	case SVGA_REG_BITS_PER_PIXEL:
1823	pThis->svga.fGFBRegisters = true;
1824	break;
1825	default:
1826	break;
1827	}
1828
1829	switch (idxReg)
1830	{
1831	case SVGA_REG_ID:
1832	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1833	if ( u32 == SVGA_ID_0
1834	\|\| u32 == SVGA_ID_1
1835	\|\| u32 == SVGA_ID_2)
1836	pThis->svga.u32SVGAId = u32;
1837	else
1838	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1839	break;
1840
1841	case SVGA_REG_ENABLE:
1842	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1843	#ifdef IN_RING3
1844	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1845	&& pThis->svga.fEnabled == false)
1846	{
1847	/* Make a backup copy of the first 512kb in order to save font data etc. */
1848	/** @todo should probably swap here, rather than copy + zero */
1849	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1850	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1851	}
1852
1853	pThis->svga.fEnabled = u32;
1854	if (pThis->svga.fEnabled)
1855	{
1856	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1857	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1858	{
1859	/* Keep the current mode. */
1860	pThis->svga.uWidth = pThisCC->pDrv->cx;
1861	pThis->svga.uHeight = pThisCC->pDrv->cy;
1862	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1863	vmsvgaHCUpdatePitch(pThis, pThisCC);
1864	}
1865
1866	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1867	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1868	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1869	# ifdef LOG_ENABLED
1870	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1871	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1872	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1873	# endif
1874
1875	/* Disable or enable dirty page tracking according to the current fTraces value. */
1876	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1877
1878	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1879	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1880	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1881
1882	/* Make the cursor visible again as needed. */
1883	if (pSVGAState->Cursor.fActive)
1884	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, false, 0, 0, 0, 0, NULL);
1885	}
1886	else
1887	{
1888	/* Make sure the cursor is off. */
1889	if (pSVGAState->Cursor.fActive)
1890	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /fVisible/, false, 0, 0, 0, 0, NULL);
1891
1892	/* Restore the text mode backup. */
1893	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1894
1895	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1896
1897	/* Enable dirty page tracking again when going into legacy mode. */
1898	vmsvgaR3SetTraces(pDevIns, pThis, true);
1899
1900	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1901	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1902	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1903
1904	/* Clear the pitch lock. */
1905	pThis->svga.u32PitchLock = 0;
1906	}
1907	#else /* !IN_RING3 */
1908	rc = VINF_IOM_R3_IOPORT_WRITE;
1909	#endif /* !IN_RING3 */
1910	break;
1911
1912	case SVGA_REG_WIDTH:
1913	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1914	if (u32 != pThis->svga.uWidth)
1915	{
1916	if (u32 <= pThis->svga.u32MaxWidth)
1917	{
1918	#if defined(IN_RING3) \|\| defined(IN_RING0)
1919	pThis->svga.uWidth = u32;
1920	vmsvgaHCUpdatePitch(pThis, pThisCC);
1921	if (pThis->svga.fEnabled)
1922	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1923	#else
1924	rc = VINF_IOM_R3_IOPORT_WRITE;
1925	#endif
1926	}
1927	else
1928	Log(("SVGA_REG_WIDTH: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxWidth));
1929	}
1930	/* else: nop */
1931	break;
1932
1933	case SVGA_REG_HEIGHT:
1934	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1935	if (u32 != pThis->svga.uHeight)
1936	{
1937	if (u32 <= pThis->svga.u32MaxHeight)
1938	{
1939	pThis->svga.uHeight = u32;
1940	if (pThis->svga.fEnabled)
1941	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1942	}
1943	else
1944	Log(("SVGA_REG_HEIGHT: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxHeight));
1945	}
1946	/* else: nop */
1947	break;
1948
1949	case SVGA_REG_DEPTH:
1950	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1951	/** @todo read-only?? */
1952	break;
1953
1954	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1955	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1956	if (pThis->svga.uBpp != u32)
1957	{
1958	if (u32 <= 32)
1959	{
1960	#if defined(IN_RING3) \|\| defined(IN_RING0)
1961	pThis->svga.uBpp = u32;
1962	vmsvgaHCUpdatePitch(pThis, pThisCC);
1963	if (pThis->svga.fEnabled)
1964	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1965	#else
1966	rc = VINF_IOM_R3_IOPORT_WRITE;
1967	#endif
1968	}
1969	else
1970	Log(("SVGA_REG_BITS_PER_PIXEL: New value is out of bounds: %u, max 32\n", u32));
1971	}
1972	/* else: nop */
1973	break;
1974
1975	case SVGA_REG_PSEUDOCOLOR:
1976	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1977	break;
1978
1979	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1980	#ifdef IN_RING3
1981	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1982	pThis->svga.fConfigured = u32;
1983	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1984	if (!pThis->svga.fConfigured)
1985	pThis->svga.fTraces = true;
1986	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1987	#else
1988	rc = VINF_IOM_R3_IOPORT_WRITE;
1989	#endif
1990	break;
1991
1992	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1993	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1994	if ( pThis->svga.fEnabled
1995	&& pThis->svga.fConfigured)
1996	{
1997	#if defined(IN_RING3) \|\| defined(IN_RING0)
1998	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1999	/*
2000	* The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
2001	* at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
2002	*/
2003	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
2004	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
2005	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
2006
2007	/* Kick the FIFO thread to start processing commands again. */
2008	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2009	#else
2010	rc = VINF_IOM_R3_IOPORT_WRITE;
2011	#endif
2012	}
2013	/* else nothing to do. */
2014	else
2015	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
2016
2017	break;
2018
2019	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
2020	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
2021	break;
2022
2023	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
2024	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
2025	pThis->svga.u32GuestId = u32;
2026	break;
2027
2028	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
2029	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
2030	pThis->svga.u32PitchLock = u32;
2031	/* Should this also update the FIFO pitch lock? Unclear. */
2032	break;
2033
2034	case SVGA_REG_IRQMASK: /* Interrupt mask */
2035	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
2036	pThis->svga.u32IrqMask = u32;
2037
2038	/* Irq pending after the above change? */
2039	if (pThis->svga.u32IrqStatus & u32)
2040	{
2041	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
2042	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
2043	}
2044	else
2045	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2046	break;
2047
2048	/* Mouse cursor support */
2049	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
2050	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
2051	pThis->svga.uCursorID = u32;
2052	break;
2053
2054	case SVGA_REG_CURSOR_X:
2055	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
2056	pThis->svga.uCursorX = u32;
2057	break;
2058
2059	case SVGA_REG_CURSOR_Y:
2060	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
2061	pThis->svga.uCursorY = u32;
2062	break;
2063
2064	case SVGA_REG_CURSOR_ON:
2065	#ifdef IN_RING3
2066	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
2067	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
2068	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
2069	#else
2070	rc = VINF_IOM_R3_IOPORT_WRITE;
2071	#endif
2072	break;
2073
2074	/* Legacy multi-monitor support */
2075	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
2076	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
2077	break;
2078	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
2079	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
2080	break;
2081	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
2082	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
2083	break;
2084	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
2085	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
2086	break;
2087	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
2088	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
2089	break;
2090	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
2091	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
2092	break;
2093	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
2094	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
2095	break;
2096	#ifdef VBOX_WITH_VMSVGA3D
2097	/* See "Guest memory regions" below. */
2098	case SVGA_REG_GMR_ID:
2099	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
2100	pThis->svga.u32CurrentGMRId = u32;
2101	break;
2102
2103	case SVGA_REG_GMR_DESCRIPTOR:
2104	# ifndef IN_RING3
2105	rc = VINF_IOM_R3_IOPORT_WRITE;
2106	break;
2107	# else /* IN_RING3 */
2108	{
2109	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
2110
2111	/* Validate current GMR id. */
2112	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
2113	AssertBreak(idGMR < pThis->svga.cGMR);
2114	RT_UNTRUSTED_VALIDATED_FENCE();
2115
2116	/* Free the old GMR if present. */
2117	vmsvgaR3GmrFree(pThisCC, idGMR);
2118
2119	/* Just undefine the GMR? */
2120	RTGCPHYS GCPhys = (RTGCPHYS)u32 << GUEST_PAGE_SHIFT;
2121	if (GCPhys == 0)
2122	{
2123	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
2124	break;
2125	}
2126
2127
2128	/* Never cross a page boundary automatically. */
2129	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
2130	uint32_t cPagesTotal = 0;
2131	uint32_t iDesc = 0;
2132	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2133	uint32_t cLoops = 0;
2134	RTGCPHYS GCPhysBase = GCPhys;
2135	while ((GCPhys >> GUEST_PAGE_SHIFT) == (GCPhysBase >> GUEST_PAGE_SHIFT))
2136	{
2137	/* Read descriptor. */
2138	SVGAGuestMemDescriptor desc;
2139	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2140	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2141
2142	if (desc.numPages != 0)
2143	{
2144	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2145	cPagesTotal += desc.numPages;
2146	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2147
2148	if ((iDesc & 15) == 0)
2149	{
2150	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
2151	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2152	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2153	}
2154
2155	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << GUEST_PAGE_SHIFT;
2156	paDescs[iDesc++].numPages = desc.numPages;
2157
2158	/* Continue with the next descriptor. */
2159	GCPhys += sizeof(desc);
2160	}
2161	else if (desc.ppn == 0)
2162	break; /* terminator */
2163	else /* Pointer to the next physical page of descriptors. */
2164	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << GUEST_PAGE_SHIFT;
2165
2166	cLoops++;
2167	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2168	}
2169
2170	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2171	if (RT_SUCCESS(rc))
2172	{
2173	/* Commit the GMR. */
2174	pSVGAState->paGMR[idGMR].paDesc = paDescs;
2175	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2176	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2177	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * GUEST_PAGE_SIZE;
2178	Assert((pSVGAState->paGMR[idGMR].cbTotal >> GUEST_PAGE_SHIFT) == cPagesTotal);
2179	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2180	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2181	}
2182	else
2183	{
2184	RTMemFree(paDescs);
2185	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2186	}
2187	break;
2188	}
2189	# endif /* IN_RING3 */
2190	#endif // VBOX_WITH_VMSVGA3D
2191
2192	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2193	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2194	if (pThis->svga.fTraces == u32)
2195	break; /* nothing to do */
2196
2197	#ifdef IN_RING3
2198	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2199	#else
2200	rc = VINF_IOM_R3_IOPORT_WRITE;
2201	#endif
2202	break;
2203
2204	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2205	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2206	break;
2207
2208	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2209	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2210	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2211	break;
2212
2213	/*
2214	* SVGA_CAP_GBOBJECTS+ registers.
2215	*/
2216	case SVGA_REG_COMMAND_LOW:
2217	{
2218	/* Lower 32 bits of command buffer physical address and submit the command buffer. */
2219	#ifdef IN_RING3
2220	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowWr);
2221	pThis->svga.u32RegCommandLow = u32;
2222
2223	/* "lower 6 bits are used for the SVGACBContext" */
2224	RTGCPHYS GCPhysCB = pThis->svga.u32RegCommandHigh;
2225	GCPhysCB <<= 32;
2226	GCPhysCB \|= pThis->svga.u32RegCommandLow & ~SVGA_CB_CONTEXT_MASK;
2227	SVGACBContext const CBCtx = (SVGACBContext)(pThis->svga.u32RegCommandLow & SVGA_CB_CONTEXT_MASK);
2228	vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, GCPhysCB, CBCtx);
2229	#else
2230	rc = VINF_IOM_R3_IOPORT_WRITE;
2231	#endif
2232	break;
2233	}
2234
2235	case SVGA_REG_COMMAND_HIGH:
2236	/* Upper 32 bits of command buffer PA. */
2237	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighWr);
2238	pThis->svga.u32RegCommandHigh = u32;
2239	break;
2240
2241	case SVGA_REG_DEV_CAP:
2242	/* Write dev cap index, read value */
2243	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapWr);
2244	pThis->svga.u32DevCapIndex = u32;
2245	break;
2246
2247	case SVGA_REG_CMD_PREPEND_LOW:
2248	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowWr);
2249	/* Not supported. */
2250	break;
2251
2252	case SVGA_REG_CMD_PREPEND_HIGH:
2253	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighWr);
2254	/* Not supported. */
2255	break;
2256
2257	case SVGA_REG_FB_START:
2258	case SVGA_REG_MEM_START:
2259	case SVGA_REG_HOST_BITS_PER_PIXEL:
2260	case SVGA_REG_MAX_WIDTH:
2261	case SVGA_REG_MAX_HEIGHT:
2262	case SVGA_REG_VRAM_SIZE:
2263	case SVGA_REG_FB_SIZE:
2264	case SVGA_REG_CAPABILITIES:
2265	case SVGA_REG_MEM_SIZE:
2266	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2267	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2268	case SVGA_REG_BYTES_PER_LINE:
2269	case SVGA_REG_FB_OFFSET:
2270	case SVGA_REG_RED_MASK:
2271	case SVGA_REG_GREEN_MASK:
2272	case SVGA_REG_BLUE_MASK:
2273	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2274	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2275	case SVGA_REG_GMR_MAX_IDS:
2276	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2277	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
2278	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
2279	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
2280	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
2281	case SVGA_REG_MOB_MAX_SIZE:
2282	/* Read only - ignore. */
2283	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2284	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2285	break;
2286
2287	default:
2288	{
2289	uint32_t offReg;
2290	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2291	{
2292	RT_UNTRUSTED_VALIDATED_FENCE();
2293	pThis->svga.au32ScratchRegion[offReg] = u32;
2294	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2295	}
2296	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2297	{
2298	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2299	Btw, see rgb_to_pixel32. */
2300	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2301	u32 &= 0xff;
2302	RT_UNTRUSTED_VALIDATED_FENCE();
2303	uint32_t uRgb = pThis->last_palette[offReg / 3];
2304	switch (offReg % 3)
2305	{
2306	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2307	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2308	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2309	}
2310	pThis->last_palette[offReg / 3] = uRgb;
2311	}
2312	else
2313	{
2314	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2315	rc = VINF_IOM_R3_IOPORT_WRITE;
2316	#else
2317	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2318	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2319	#endif
2320	}
2321	break;
2322	}
2323	}
2324	return rc;
2325	}
2326
2327	/**
2328	* @callback_method_impl{FNIOMIOPORTNEWIN}
2329	*/
2330	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2331	{
2332	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2333	RT_NOREF_PV(pvUser);
2334
2335	/* Only dword accesses. */
2336	if (cb == 4)
2337	{
2338	switch (offPort)
2339	{
2340	case SVGA_INDEX_PORT:
2341	*pu32 = pThis->svga.u32IndexReg;
2342	break;
2343
2344	case SVGA_VALUE_PORT:
2345	return vmsvgaReadPort(pDevIns, pThis, pu32);
2346
2347	case SVGA_BIOS_PORT:
2348	Log(("Ignoring BIOS port read\n"));
2349	*pu32 = 0;
2350	break;
2351
2352	case SVGA_IRQSTATUS_PORT:
2353	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2354	*pu32 = pThis->svga.u32IrqStatus;
2355	break;
2356
2357	default:
2358	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2359	*pu32 = UINT32_MAX;
2360	break;
2361	}
2362	}
2363	else
2364	{
2365	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2366	*pu32 = UINT32_MAX;
2367	}
2368	return VINF_SUCCESS;
2369	}
2370
2371	/**
2372	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2373	*/
2374	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2375	{
2376	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2377	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2378	RT_NOREF_PV(pvUser);
2379
2380	/* Only dword accesses. */
2381	if (cb == 4)
2382	switch (offPort)
2383	{
2384	case SVGA_INDEX_PORT:
2385	pThis->svga.u32IndexReg = u32;
2386	break;
2387
2388	case SVGA_VALUE_PORT:
2389	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2390
2391	case SVGA_BIOS_PORT:
2392	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2393	break;
2394
2395	case SVGA_IRQSTATUS_PORT:
2396	LogFlow(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2397	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2398	/* Clear the irq in case all events have been cleared. */
2399	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2400	{
2401	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2402	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2403	}
2404	break;
2405
2406	default:
2407	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2408	break;
2409	}
2410	else
2411	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2412
2413	return VINF_SUCCESS;
2414	}
2415
2416	#ifdef IN_RING3
2417
2418	# ifdef DEBUG_FIFO_ACCESS
2419	/**
2420	* Handle FIFO memory access.
2421	* @returns VBox status code.
2422	* @param pVM VM handle.
2423	* @param pThis The shared VGA/VMSVGA instance data.
2424	* @param GCPhys The access physical address.
2425	* @param fWriteAccess Read or write access
2426	*/
2427	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2428	{
2429	RT_NOREF(pVM);
2430	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2431	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2432
2433	switch (GCPhysOffset >> 2)
2434	{
2435	case SVGA_FIFO_MIN:
2436	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2437	break;
2438	case SVGA_FIFO_MAX:
2439	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2440	break;
2441	case SVGA_FIFO_NEXT_CMD:
2442	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2443	break;
2444	case SVGA_FIFO_STOP:
2445	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2446	break;
2447	case SVGA_FIFO_CAPABILITIES:
2448	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2449	break;
2450	case SVGA_FIFO_FLAGS:
2451	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2452	break;
2453	case SVGA_FIFO_FENCE:
2454	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2455	break;
2456	case SVGA_FIFO_3D_HWVERSION:
2457	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2458	break;
2459	case SVGA_FIFO_PITCHLOCK:
2460	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2461	break;
2462	case SVGA_FIFO_CURSOR_ON:
2463	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2464	break;
2465	case SVGA_FIFO_CURSOR_X:
2466	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2467	break;
2468	case SVGA_FIFO_CURSOR_Y:
2469	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2470	break;
2471	case SVGA_FIFO_CURSOR_COUNT:
2472	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2473	break;
2474	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2475	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2476	break;
2477	case SVGA_FIFO_RESERVED:
2478	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2479	break;
2480	case SVGA_FIFO_CURSOR_SCREEN_ID:
2481	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2482	break;
2483	case SVGA_FIFO_DEAD:
2484	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2485	break;
2486	case SVGA_FIFO_3D_HWVERSION_REVISED:
2487	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2488	break;
2489	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2490	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2491	break;
2492	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2493	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2494	break;
2495	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2496	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2497	break;
2498	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2499	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2500	break;
2501	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2502	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2503	break;
2504	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2505	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2506	break;
2507	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2508	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2509	break;
2510	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2511	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2512	break;
2513	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2514	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2515	break;
2516	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2517	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2518	break;
2519	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2520	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2521	break;
2522	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2523	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2524	break;
2525	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2526	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2527	break;
2528	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2529	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2530	break;
2531	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2532	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2533	break;
2534	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2535	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2536	break;
2537	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2538	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2539	break;
2540	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2541	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2542	break;
2543	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2544	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2545	break;
2546	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2547	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2548	break;
2549	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2550	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2551	break;
2552	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2553	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2554	break;
2555	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2556	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2557	break;
2558	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2559	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2560	break;
2561	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2562	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2563	break;
2564	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2565	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2566	break;
2567	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2568	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2569	break;
2570	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2571	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2572	break;
2573	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2574	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2575	break;
2576	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2577	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2578	break;
2579	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2580	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2581	break;
2582	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2583	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2584	break;
2585	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2586	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2587	break;
2588	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2589	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2590	break;
2591	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2592	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2593	break;
2594	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2595	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2596	break;
2597	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2598	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2599	break;
2600	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2601	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2602	break;
2603	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2604	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2605	break;
2606	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2607	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2608	break;
2609	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2610	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2611	break;
2612	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2613	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2614	break;
2615	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2616	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2617	break;
2618	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2619	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2620	break;
2621	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2622	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2623	break;
2624	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2625	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2626	break;
2627	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2628	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2629	break;
2630	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2631	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2632	break;
2633	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2634	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2635	break;
2636	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2637	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2638	break;
2639	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2640	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2641	break;
2642	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2643	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2644	break;
2645	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2646	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2647	break;
2648	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2649	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2650	break;
2651	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2652	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2653	break;
2654	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2655	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2656	break;
2657	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2658	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2659	break;
2660	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2661	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2662	break;
2663	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2664	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2665	break;
2666	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2667	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2668	break;
2669	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2670	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2671	break;
2672	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2673	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2674	break;
2675	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2676	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2677	break;
2678	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2679	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2680	break;
2681	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2682	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2683	break;
2684	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2685	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2686	break;
2687	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2688	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2689	break;
2690	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2691	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2692	break;
2693	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2694	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2695	break;
2696	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD4: /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
2697	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD4 (SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2698	break;
2699	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD5: /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
2700	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD5 (SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2701	break;
2702	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD7: /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
2703	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD7 (SVGA3D_DEVCAP_ALPHATOCOVERAGE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2704	break;
2705	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD6: /* SVGA3D_DEVCAP_SUPERSAMPLE */
2706	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD6 (SVGA3D_DEVCAP_SUPERSAMPLE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2707	break;
2708	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2709	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2710	break;
2711	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2712	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2713	break;
2714	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
2715	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD10 (SVGA3D_DEVCAP_SURFACEFMT_AYUV) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2716	break;
2717	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2718	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2719	break;
2720	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2721	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2722	break;
2723	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2724	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2725	break;
2726	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2727	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2728	break;
2729	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2730	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2731	break;
2732	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI1:
2733	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2734	break;
2735	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI2:
2736	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2737	break;
2738	case SVGA_FIFO_3D_CAPS_LAST:
2739	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2740	break;
2741	case SVGA_FIFO_GUEST_3D_HWVERSION:
2742	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2743	break;
2744	case SVGA_FIFO_FENCE_GOAL:
2745	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2746	break;
2747	case SVGA_FIFO_BUSY:
2748	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2749	break;
2750	default:
2751	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2752	break;
2753	}
2754
2755	return VINF_EM_RAW_EMULATE_INSTR;
2756	}
2757	# endif /* DEBUG_FIFO_ACCESS */
2758
2759	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2760	/**
2761	* HC access handler for the FIFO.
2762	*
2763	* @returns VINF_SUCCESS if the handler have carried out the operation.
2764	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2765	* @param pVM VM Handle.
2766	* @param pVCpu The cross context CPU structure for the calling EMT.
2767	* @param GCPhys The physical address the guest is writing to.
2768	* @param pvPhys The HC mapping of that address.
2769	* @param pvBuf What the guest is reading/writing.
2770	* @param cbBuf How much it's reading/writing.
2771	* @param enmAccessType The access type.
2772	* @param enmOrigin Who is making the access.
2773	* @param pvUser User argument.
2774	*/
2775	static DECLCALLBACK(VBOXSTRICTRC)
2776	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2777	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2778	{
2779	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2780	PVGASTATE pThis = (PVGASTATE)pvUser;
2781	AssertPtr(pThis);
2782
2783	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2784	/*
2785	* Wake up the FIFO thread as it might have work to do now.
2786	*/
2787	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2788	AssertLogRelRC(rc);
2789	# endif
2790
2791	# ifdef DEBUG_FIFO_ACCESS
2792	/*
2793	* When in debug-fifo-access mode, we do not disable the access handler,
2794	* but leave it on as we wish to catch all access.
2795	*/
2796	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2797	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2798	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2799	/*
2800	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2801	*/
2802	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2803	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2804	# endif
2805	if (RT_SUCCESS(rc))
2806	return VINF_PGM_HANDLER_DO_DEFAULT;
2807	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2808	return rc;
2809	}
2810	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2811
2812	#endif /* IN_RING3 */
2813
2814	#ifdef DEBUG_GMR_ACCESS
2815	# ifdef IN_RING3
2816
2817	/**
2818	* HC access handler for GMRs.
2819	*
2820	* @returns VINF_SUCCESS if the handler have carried out the operation.
2821	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2822	* @param pVM VM Handle.
2823	* @param pVCpu The cross context CPU structure for the calling EMT.
2824	* @param GCPhys The physical address the guest is writing to.
2825	* @param pvPhys The HC mapping of that address.
2826	* @param pvBuf What the guest is reading/writing.
2827	* @param cbBuf How much it's reading/writing.
2828	* @param enmAccessType The access type.
2829	* @param enmOrigin Who is making the access.
2830	* @param pvUser User argument.
2831	*/
2832	static DECLCALLBACK(VBOXSTRICTRC)
2833	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2834	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2835	{
2836	PVGASTATE pThis = (PVGASTATE)pvUser;
2837	Assert(pThis);
2838	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2839	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2840
2841	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2842
2843	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2844	{
2845	PGMR pGMR = &pSVGAState->paGMR[i];
2846
2847	if (pGMR->numDescriptors)
2848	{
2849	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2850	{
2851	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2852	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * GUEST_PAGE_SIZE)
2853	{
2854	/*
2855	* Turn off the write handler for this particular page and make it R/W.
2856	* Then return telling the caller to restart the guest instruction.
2857	*/
2858	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2859	AssertRC(rc);
2860	return VINF_PGM_HANDLER_DO_DEFAULT;
2861	}
2862	}
2863	}
2864	}
2865
2866	return VINF_PGM_HANDLER_DO_DEFAULT;
2867	}
2868
2869	/** Callback handler for VMR3ReqCallWaitU */
2870	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2871	{
2872	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2873	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2874	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2875	int rc;
2876
2877	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2878	{
2879	rc = PDMDevHlpPGMHandlerPhysicalRegister(pDevIns, pGMR->paDesc[i].GCPhys,
2880	pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * GUEST_PAGE_SIZE - 1,
2881	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2882	AssertRC(rc);
2883	}
2884	return VINF_SUCCESS;
2885	}
2886
2887	/** Callback handler for VMR3ReqCallWaitU */
2888	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2889	{
2890	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2891	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2892	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2893
2894	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2895	{
2896	int rc = PDMDevHlpPGMHandlerPhysicalDeregister(pDevIns, pGMR->paDesc[i].GCPhys);
2897	AssertRC(rc);
2898	}
2899	return VINF_SUCCESS;
2900	}
2901
2902	/** Callback handler for VMR3ReqCallWaitU */
2903	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2904	{
2905	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2906
2907	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2908	{
2909	PGMR pGMR = &pSVGAState->paGMR[i];
2910
2911	if (pGMR->numDescriptors)
2912	{
2913	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2914	{
2915	int rc = PDMDevHlpPGMHandlerPhysicalReset(pDevIns, pGMR->paDesc[j].GCPhys);
2916	AssertRC(rc);
2917	}
2918	}
2919	}
2920	return VINF_SUCCESS;
2921	}
2922
2923	# endif /* IN_RING3 */
2924	#endif /* DEBUG_GMR_ACCESS */
2925
2926	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2927
2928	#ifdef IN_RING3
2929
2930
2931	/*
2932	*
2933	* Command buffer submission.
2934	*
2935	* Guest submits a buffer by writing to SVGA_REG_COMMAND_LOW register.
2936	*
2937	* EMT thread appends a command buffer to the context queue (VMSVGACMDBUFCTX::listSubmitted)
2938	* and wakes up the FIFO thread.
2939	*
2940	* FIFO thread fetches the command buffer from the queue, processes the commands and writes
2941	* the buffer header back to the guest memory.
2942	*
2943	* If buffers are preempted, then the EMT thread removes all buffers from the context queue.
2944	*
2945	*/
2946
2947
2948	/** Update a command buffer header 'status' and 'errorOffset' fields in the guest memory.
2949	*
2950	* @param pDevIns The device instance.
2951	* @param GCPhysCB Guest physical address of the command buffer header.
2952	* @param status Command buffer status (SVGA_CB_STATUS_*).
2953	* @param errorOffset Offset to the first byte of the failing command for SVGA_CB_STATUS_COMMAND_ERROR.
2954	* errorOffset is ignored if the status is not SVGA_CB_STATUS_COMMAND_ERROR.
2955	* @thread FIFO or EMT.
2956	*/
2957	static void vmsvgaR3CmdBufWriteStatus(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCB, SVGACBStatus status, uint32_t errorOffset)
2958	{
2959	SVGACBHeader hdr;
2960	hdr.status = status;
2961	hdr.errorOffset = errorOffset;
2962	AssertCompile( RT_OFFSETOF(SVGACBHeader, status) == 0
2963	&& RT_OFFSETOF(SVGACBHeader, errorOffset) == 4
2964	&& RT_OFFSETOF(SVGACBHeader, id) == 8);
2965	size_t const cbWrite = status == SVGA_CB_STATUS_COMMAND_ERROR
2966	? RT_UOFFSET_AFTER(SVGACBHeader, errorOffset) /* Both 'status' and 'errorOffset' fields. */
2967	: RT_UOFFSET_AFTER(SVGACBHeader, status); /* Only 'status' field. */
2968	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysCB, &hdr, cbWrite);
2969	}
2970
2971
2972	/** Raise an IRQ.
2973	*
2974	* @param pDevIns The device instance.
2975	* @param pThis The shared VGA/VMSVGA state.
2976	* @param u32IrqStatus SVGA_IRQFLAG_* bits.
2977	* @thread FIFO or EMT.
2978	*/
2979	static void vmsvgaR3CmdBufRaiseIRQ(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t u32IrqStatus)
2980	{
2981	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
2982	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
2983
2984	if (pThis->svga.u32IrqMask & u32IrqStatus)
2985	{
2986	LogFunc(("Trigger interrupt with status %#x\n", u32IrqStatus));
2987	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
2988	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
2989	}
2990
2991	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
2992	}
2993
2994
2995	/** Allocate a command buffer structure.
2996	*
2997	* @param pCmdBufCtx The command buffer context which must allocate the buffer.
2998	* @return Pointer to the allocated command buffer structure.
2999	*/
3000	static PVMSVGACMDBUF vmsvgaR3CmdBufAlloc(PVMSVGACMDBUFCTX pCmdBufCtx)
3001	{
3002	if (!pCmdBufCtx)
3003	return NULL;
3004
3005	PVMSVGACMDBUF pCmdBuf = (PVMSVGACMDBUF)RTMemAllocZ(sizeof(*pCmdBuf));
3006	if (pCmdBuf)
3007	{
3008	// RT_ZERO(pCmdBuf->nodeBuffer);
3009	pCmdBuf->pCmdBufCtx = pCmdBufCtx;
3010	// pCmdBuf->GCPhysCB = 0;
3011	// RT_ZERO(pCmdBuf->hdr);
3012	// pCmdBuf->pvCommands = NULL;
3013	}
3014
3015	return pCmdBuf;
3016	}
3017
3018
3019	/** Free a command buffer structure.
3020	*
3021	* @param pCmdBuf The command buffer pointer.
3022	*/
3023	static void vmsvgaR3CmdBufFree(PVMSVGACMDBUF pCmdBuf)
3024	{
3025	if (pCmdBuf)
3026	RTMemFree(pCmdBuf->pvCommands);
3027	RTMemFree(pCmdBuf);
3028	}
3029
3030
3031	/** Initialize a command buffer context.
3032	*
3033	* @param pCmdBufCtx The command buffer context.
3034	*/
3035	static void vmsvgaR3CmdBufCtxInit(PVMSVGACMDBUFCTX pCmdBufCtx)
3036	{
3037	RTListInit(&pCmdBufCtx->listSubmitted);
3038	pCmdBufCtx->cSubmitted = 0;
3039	}
3040
3041
3042	/** Destroy a command buffer context.
3043	*
3044	* @param pCmdBufCtx The command buffer context pointer.
3045	*/
3046	static void vmsvgaR3CmdBufCtxTerm(PVMSVGACMDBUFCTX pCmdBufCtx)
3047	{
3048	if (!pCmdBufCtx)
3049	return;
3050
3051	if (pCmdBufCtx->listSubmitted.pNext)
3052	{
3053	/* If the list has been initialized. */
3054	PVMSVGACMDBUF pIter, pNext;
3055	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3056	{
3057	RTListNodeRemove(&pIter->nodeBuffer);
3058	--pCmdBufCtx->cSubmitted;
3059	vmsvgaR3CmdBufFree(pIter);
3060	}
3061	}
3062	Assert(pCmdBufCtx->cSubmitted == 0);
3063	pCmdBufCtx->cSubmitted = 0;
3064	}
3065
3066
3067	/** Handles SVGA_DC_CMD_START_STOP_CONTEXT command.
3068	*
3069	* @param pSvgaR3State VMSVGA R3 state.
3070	* @param pCmd The command data.
3071	* @return SVGACBStatus code.
3072	* @thread EMT
3073	*/
3074	static SVGACBStatus vmsvgaR3CmdBufDCStartStop(PVMSVGAR3STATE pSvgaR3State, SVGADCCmdStartStop const *pCmd)
3075	{
3076	/* Create or destroy a regular command buffer context. */
3077	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3078	return SVGA_CB_STATUS_COMMAND_ERROR;
3079	RT_UNTRUSTED_VALIDATED_FENCE();
3080
3081	SVGACBStatus CBStatus = SVGA_CB_STATUS_COMPLETED;
3082
3083	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3084	AssertRC(rc);
3085	if (pCmd->enable)
3086	{
3087	pSvgaR3State->apCmdBufCtxs[pCmd->context] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
3088	if (pSvgaR3State->apCmdBufCtxs[pCmd->context])
3089	vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3090	else
3091	CBStatus = SVGA_CB_STATUS_QUEUE_FULL;
3092	}
3093	else
3094	{
3095	vmsvgaR3CmdBufCtxTerm(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3096	pSvgaR3State->apCmdBufCtxs[pCmd->context] = NULL;
3097	}
3098	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3099
3100	return CBStatus;
3101	}
3102
3103
3104	/** Handles SVGA_DC_CMD_PREEMPT command.
3105	*
3106	* @param pDevIns The device instance.
3107	* @param pSvgaR3State VMSVGA R3 state.
3108	* @param pCmd The command data.
3109	* @return SVGACBStatus code.
3110	* @thread EMT
3111	*/
3112	static SVGACBStatus vmsvgaR3CmdBufDCPreempt(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, SVGADCCmdPreempt const *pCmd)
3113	{
3114	/* Remove buffers from the processing queue of the specified context. */
3115	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3116	return SVGA_CB_STATUS_COMMAND_ERROR;
3117	RT_UNTRUSTED_VALIDATED_FENCE();
3118
3119	PVMSVGACMDBUFCTX const pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[pCmd->context];
3120	RTLISTANCHOR listPreempted;
3121
3122	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3123	AssertRC(rc);
3124	if (pCmd->ignoreIDZero)
3125	{
3126	RTListInit(&listPreempted);
3127
3128	PVMSVGACMDBUF pIter, pNext;
3129	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3130	{
3131	if (pIter->hdr.id == 0)
3132	continue;
3133
3134	RTListNodeRemove(&pIter->nodeBuffer);
3135	--pCmdBufCtx->cSubmitted;
3136	RTListAppend(&listPreempted, &pIter->nodeBuffer);
3137	}
3138	}
3139	else
3140	{
3141	RTListMove(&listPreempted, &pCmdBufCtx->listSubmitted);
3142	pCmdBufCtx->cSubmitted = 0;
3143	}
3144	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3145
3146	PVMSVGACMDBUF pIter, pNext;
3147	RTListForEachSafe(&listPreempted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3148	{
3149	RTListNodeRemove(&pIter->nodeBuffer);
3150	vmsvgaR3CmdBufWriteStatus(pDevIns, pIter->GCPhysCB, SVGA_CB_STATUS_PREEMPTED, 0);
3151	LogFunc(("Preempted %RX64\n", pIter->GCPhysCB));
3152	vmsvgaR3CmdBufFree(pIter);
3153	}
3154
3155	return SVGA_CB_STATUS_COMPLETED;
3156	}
3157
3158
3159	/** @def VMSVGA_INC_CMD_SIZE_BREAK
3160	* Increments the size of the command cbCmd by a_cbMore.
3161	* Checks that the command buffer has at least cbCmd bytes. Will break out of the switch if it doesn't.
3162	* Used by vmsvgaR3CmdBufProcessDC and vmsvgaR3CmdBufProcessCommands.
3163	*/
3164	#define VMSVGA_INC_CMD_SIZE_BREAK(a_cbMore) \
3165	if (1) { \
3166	cbCmd += (a_cbMore); \
3167	ASSERT_GUEST_MSG_STMT_BREAK(cbRemain >= cbCmd, ("size=%#x remain=%#zx\n", cbCmd, (size_t)cbRemain), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR); \
3168	RT_UNTRUSTED_VALIDATED_FENCE(); \
3169	} else do {} while (0)
3170
3171
3172	/** Processes Device Context command buffer.
3173	*
3174	* @param pDevIns The device instance.
3175	* @param pSvgaR3State VMSVGA R3 state.
3176	* @param pvCommands Pointer to the command buffer.
3177	* @param cbCommands Size of the command buffer.
3178	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3179	* @return SVGACBStatus code.
3180	* @thread EMT
3181	*/
3182	static SVGACBStatus vmsvgaR3CmdBufProcessDC(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd)
3183	{
3184	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3185
3186	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3187	uint32_t cbRemain = cbCommands;
3188	while (cbRemain)
3189	{
3190	/* Command identifier is a 32 bit value. */
3191	if (cbRemain < sizeof(uint32_t))
3192	{
3193	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3194	break;
3195	}
3196
3197	/* Fetch the command id. */
3198	uint32_t const cmdId = (uint32_t )pu8Cmd;
3199	uint32_t cbCmd = sizeof(uint32_t);
3200	switch (cmdId)
3201	{
3202	case SVGA_DC_CMD_NOP:
3203	{
3204	/* NOP */
3205	break;
3206	}
3207
3208	case SVGA_DC_CMD_START_STOP_CONTEXT:
3209	{
3210	SVGADCCmdStartStop pCmd = (SVGADCCmdStartStop )&pu8Cmd[cbCmd];
3211	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3212	CBstatus = vmsvgaR3CmdBufDCStartStop(pSvgaR3State, pCmd);
3213	break;
3214	}
3215
3216	case SVGA_DC_CMD_PREEMPT:
3217	{
3218	SVGADCCmdPreempt pCmd = (SVGADCCmdPreempt )&pu8Cmd[cbCmd];
3219	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3220	CBstatus = vmsvgaR3CmdBufDCPreempt(pDevIns, pSvgaR3State, pCmd);
3221	break;
3222	}
3223
3224	default:
3225	{
3226	/* Unsupported command. */
3227	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3228	break;
3229	}
3230	}
3231
3232	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3233	break;
3234
3235	pu8Cmd += cbCmd;
3236	cbRemain -= cbCmd;
3237	}
3238
3239	Assert(cbRemain <= cbCommands);
3240	*poffNextCmd = cbCommands - cbRemain;
3241	return CBstatus;
3242	}
3243
3244
3245	/** Submits a device context command buffer for synchronous processing.
3246	*
3247	* @param pDevIns The device instance.
3248	* @param pThisCC The VGA/VMSVGA state for the current context.
3249	* @param ppCmdBuf Pointer to the command buffer pointer.
3250	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3251	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3252	* @return SVGACBStatus code.
3253	* @thread EMT
3254	*/
3255	static SVGACBStatus vmsvgaR3CmdBufSubmitDC(PPDMDEVINS pDevIns, PVGASTATECC pThisCC, PVMSVGACMDBUF ppCmdBuf, uint32_t poffNextCmd)
3256	{
3257	/* Synchronously process the device context commands. */
3258	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3259	return vmsvgaR3CmdBufProcessDC(pDevIns, pSvgaR3State, (ppCmdBuf)->pvCommands, (ppCmdBuf)->hdr.length, poffNextCmd);
3260	}
3261
3262	/** Submits a command buffer for asynchronous processing by the FIFO thread.
3263	*
3264	* @param pDevIns The device instance.
3265	* @param pThis The shared VGA/VMSVGA state.
3266	* @param pThisCC The VGA/VMSVGA state for the current context.
3267	* @param ppCmdBuf Pointer to the command buffer pointer.
3268	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3269	* @return SVGACBStatus code.
3270	* @thread EMT
3271	*/
3272	static SVGACBStatus vmsvgaR3CmdBufSubmitCtx(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf)
3273	{
3274	/* Command buffer submission. */
3275	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3276
3277	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3278
3279	PVMSVGACMDBUF const pCmdBuf = *ppCmdBuf;
3280	PVMSVGACMDBUFCTX const pCmdBufCtx = pCmdBuf->pCmdBufCtx;
3281
3282	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3283	AssertRC(rc);
3284
3285	if (RT_LIKELY(pCmdBufCtx->cSubmitted < SVGA_CB_MAX_QUEUED_PER_CONTEXT))
3286	{
3287	RTListAppend(&pCmdBufCtx->listSubmitted, &pCmdBuf->nodeBuffer);
3288	++pCmdBufCtx->cSubmitted;
3289	ppCmdBuf = NULL; / Consume the buffer. */
3290	ASMAtomicWriteU32(&pThisCC->svga.pSvgaR3State->fCmdBuf, 1);
3291	}
3292	else
3293	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3294
3295	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3296
3297	/* Inform the FIFO thread. */
3298	if (*ppCmdBuf == NULL)
3299	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3300
3301	return CBstatus;
3302	}
3303
3304
3305	/** SVGA_REG_COMMAND_LOW write handler.
3306	* Submits a command buffer to the FIFO thread or processes a device context command.
3307	*
3308	* @param pDevIns The device instance.
3309	* @param pThis The shared VGA/VMSVGA state.
3310	* @param pThisCC The VGA/VMSVGA state for the current context.
3311	* @param GCPhysCB Guest physical address of the command buffer header.
3312	* @param CBCtx Context the command buffer is submitted to.
3313	* @thread EMT
3314	*/
3315	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx)
3316	{
3317	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3318
3319	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3320	uint32_t offNextCmd = 0;
3321	uint32_t fIRQ = 0;
3322
3323	/* Get the context if the device has the capability. */
3324	PVMSVGACMDBUFCTX pCmdBufCtx = NULL;
3325	if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
3326	{
3327	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3328	pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[CBCtx];
3329	else if (CBCtx == SVGA_CB_CONTEXT_DEVICE)
3330	pCmdBufCtx = &pSvgaR3State->CmdBufCtxDC;
3331	RT_UNTRUSTED_VALIDATED_FENCE();
3332	}
3333
3334	/* Allocate a new command buffer. */
3335	PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pCmdBufCtx);
3336	if (RT_LIKELY(pCmdBuf))
3337	{
3338	pCmdBuf->GCPhysCB = GCPhysCB;
3339
3340	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCB, &pCmdBuf->hdr, sizeof(pCmdBuf->hdr));
3341	if (RT_SUCCESS(rc))
3342	{
3343	LogFunc(("status %RX32 errorOffset %RX32 id %RX64 flags %RX32 length %RX32 ptr %RX64 offset %RX32 dxContext %RX32 (%RX32 %RX32 %RX32 %RX32 %RX32 %RX32)\n",
3344	pCmdBuf->hdr.status,
3345	pCmdBuf->hdr.errorOffset,
3346	pCmdBuf->hdr.id,
3347	pCmdBuf->hdr.flags,
3348	pCmdBuf->hdr.length,
3349	pCmdBuf->hdr.ptr.pa,
3350	pCmdBuf->hdr.offset,
3351	pCmdBuf->hdr.dxContext,
3352	pCmdBuf->hdr.mustBeZero[0],
3353	pCmdBuf->hdr.mustBeZero[1],
3354	pCmdBuf->hdr.mustBeZero[2],
3355	pCmdBuf->hdr.mustBeZero[3],
3356	pCmdBuf->hdr.mustBeZero[4],
3357	pCmdBuf->hdr.mustBeZero[5]));
3358
3359	/* Verify the command buffer header. */
3360	if (RT_LIKELY( pCmdBuf->hdr.status == SVGA_CB_STATUS_NONE
3361	&& (pCmdBuf->hdr.flags & ~(SVGA_CB_FLAG_NO_IRQ \| SVGA_CB_FLAG_DX_CONTEXT)) == 0 /* No unexpected flags. */
3362	&& pCmdBuf->hdr.length <= SVGA_CB_MAX_SIZE))
3363	{
3364	RT_UNTRUSTED_VALIDATED_FENCE();
3365
3366	/* Read the command buffer content. */
3367	pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
3368	if (pCmdBuf->pvCommands)
3369	{
3370	RTGCPHYS const GCPhysCmd = (RTGCPHYS)pCmdBuf->hdr.ptr.pa;
3371	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
3372	if (RT_SUCCESS(rc))
3373	{
3374	/* Submit the buffer. Device context buffers will be processed synchronously. */
3375	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3376	/* This usually processes the CB async and sets pCmbBuf to NULL. */
3377	CBstatus = vmsvgaR3CmdBufSubmitCtx(pDevIns, pThis, pThisCC, &pCmdBuf);
3378	else
3379	CBstatus = vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
3380	}
3381	else
3382	{
3383	ASSERT_GUEST_MSG_FAILED(("Failed to read commands at %RGp\n", GCPhysCmd));
3384	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3385	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3386	}
3387	}
3388	else
3389	{
3390	/* No memory for commands. */
3391	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3392	}
3393	}
3394	else
3395	{
3396	ASSERT_GUEST_MSG_FAILED(("Invalid buffer header\n"));
3397	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3398	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3399	}
3400	}
3401	else
3402	{
3403	LogFunc(("Failed to read buffer header at %RGp\n", GCPhysCB));
3404	ASSERT_GUEST_FAILED();
3405	/* Do not attempt to write the status. */
3406	}
3407
3408	/* Free the buffer if pfnCmdBufSubmit did not consume it. */
3409	vmsvgaR3CmdBufFree(pCmdBuf);
3410	}
3411	else
3412	{
3413	LogFunc(("Can't allocate buffer for context id %#x\n", CBCtx));
3414	AssertFailed();
3415	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3416	}
3417
3418	if (CBstatus != SVGA_CB_STATUS_NONE)
3419	{
3420	LogFunc(("Write status %#x, offNextCmd %#x, fIRQ %#x\n", CBstatus, offNextCmd, fIRQ));
3421	vmsvgaR3CmdBufWriteStatus(pDevIns, GCPhysCB, CBstatus, offNextCmd);
3422	if (fIRQ)
3423	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, fIRQ);
3424	}
3425	}
3426
3427
3428	/** Checks if there are some buffers to be processed.
3429	*
3430	* @param pThisCC The VGA/VMSVGA state for the current context.
3431	* @return true if buffers must be processed.
3432	* @thread FIFO
3433	*/
3434	static bool vmsvgaR3CmdBufHasWork(PVGASTATECC pThisCC)
3435	{
3436	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3437	return RT_BOOL(ASMAtomicReadU32(&pSvgaR3State->fCmdBuf));
3438	}
3439
3440
3441	/** Processes a command buffer.
3442	*
3443	* @param pDevIns The device instance.
3444	* @param pThis The shared VGA/VMSVGA state.
3445	* @param pThisCC The VGA/VMSVGA state for the current context.
3446	* @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
3447	* @param pvCommands Pointer to the command buffer.
3448	* @param cbCommands Size of the command buffer.
3449	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3450	* @param pu32IrqStatus Where to store SVGA_IRQFLAG_ if the IRQ is generated by the last command in the buffer.
3451	* @return SVGACBStatus code.
3452	* @thread FIFO
3453	*/
3454	static SVGACBStatus vmsvgaR3CmdBufProcessCommands(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd, uint32_t *pu32IrqStatus)
3455	{
3456	# ifndef VBOX_WITH_VMSVGA3D
3457	RT_NOREF(idDXContext);
3458	# endif
3459	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3460	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3461
3462	# ifdef VBOX_WITH_VMSVGA3D
3463	# ifdef VMSVGA3D_DX
3464	/* Commands submitted for the SVGA3D_INVALID_ID context do not affect pipeline. So ignore them. */
3465	if (idDXContext != SVGA3D_INVALID_ID)
3466	{
3467	if (pSvgaR3State->idDXContextCurrent != idDXContext)
3468	{
3469	LogFlow(("DXCTX: buffer %d->%d\n", pSvgaR3State->idDXContextCurrent, idDXContext));
3470	vmsvga3dDXSwitchContext(pThisCC, idDXContext);
3471	pSvgaR3State->idDXContextCurrent = idDXContext;
3472	}
3473	}
3474	# endif
3475	# endif
3476
3477	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3478
3479	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3480	uint32_t cbRemain = cbCommands;
3481	while (cbRemain)
3482	{
3483	/* Command identifier is a 32 bit value. */
3484	if (cbRemain < sizeof(uint32_t))
3485	{
3486	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3487	break;
3488	}
3489
3490	/* Fetch the command id.
3491	* 'cmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
3492	* warning. Because we support some obsolete and deprecated commands, which are not included in
3493	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
3494	*/
3495	uint32_t const cmdId = (uint32_t )pu8Cmd;
3496	uint32_t cbCmd = sizeof(uint32_t);
3497
3498	LogFunc(("[cid=%d] %s %d\n", (int32_t)idDXContext, vmsvgaR3FifoCmdToString(cmdId), cmdId));
3499	# ifdef LOG_ENABLED
3500	# ifdef VBOX_WITH_VMSVGA3D
3501	if (SVGA_3D_CMD_BASE <= cmdId && cmdId < SVGA_3D_CMD_MAX)
3502	{
3503	SVGA3dCmdHeader const header = (SVGA3dCmdHeader )pu8Cmd;
3504	svga_dump_command(cmdId, (uint8_t *)&header[1], header->size);
3505	}
3506	else if (cmdId == SVGA_CMD_FENCE)
3507	{
3508	Log7(("\tSVGA_CMD_FENCE\n"));
3509	Log7(("\t\t0x%08x\n", ((uint32_t *)pu8Cmd)[1]));
3510	}
3511	# endif
3512	# endif
3513
3514	/* At the end of the switch cbCmd is equal to the total length of the command including the cmdId.
3515	* I.e. pu8Cmd + cbCmd must point to the next command.
3516	* However if CBstatus is set to anything but SVGA_CB_STATUS_COMPLETED in the switch, then
3517	* the cbCmd value is ignored (and pu8Cmd still points to the failed command).
3518	*/
3519	/** @todo This code is very similar to the FIFO loop command processing. Think about merging. */
3520	switch (cmdId)
3521	{
3522	case SVGA_CMD_INVALID_CMD:
3523	{
3524	/* Nothing to do. */
3525	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdInvalidCmd);
3526	break;
3527	}
3528
3529	case SVGA_CMD_FENCE:
3530	{
3531	SVGAFifoCmdFence pCmd = (SVGAFifoCmdFence )&pu8Cmd[cbCmd];
3532	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3533	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdFence);
3534	Log(("SVGA_CMD_FENCE %#x\n", pCmd->fence));
3535
3536	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3537	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3538	{
3539	pFIFO[SVGA_FIFO_FENCE] = pCmd->fence;
3540
3541	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3542	{
3543	Log(("any fence irq\n"));
3544	*pu32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3545	}
3546	else if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3547	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3548	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmd->fence)
3549	{
3550	Log(("fence goal reached irq (fence=%#x)\n", pCmd->fence));
3551	*pu32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3552	}
3553	}
3554	else
3555	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3556	break;
3557	}
3558
3559	case SVGA_CMD_UPDATE:
3560	{
3561	SVGAFifoCmdUpdate pCmd = (SVGAFifoCmdUpdate )&pu8Cmd[cbCmd];
3562	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3563	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
3564	break;
3565	}
3566
3567	case SVGA_CMD_UPDATE_VERBOSE:
3568	{
3569	SVGAFifoCmdUpdateVerbose pCmd = (SVGAFifoCmdUpdateVerbose )&pu8Cmd[cbCmd];
3570	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3571	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
3572	break;
3573	}
3574
3575	case SVGA_CMD_DEFINE_CURSOR:
3576	{
3577	/* Followed by bitmap data. */
3578	SVGAFifoCmdDefineCursor pCmd = (SVGAFifoCmdDefineCursor )&pu8Cmd[cbCmd];
3579	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3580
3581	/* Figure out the size of the bitmap data. */
3582	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3583	ASSERT_GUEST_STMT_BREAK(pCmd->andMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3584	ASSERT_GUEST_STMT_BREAK(pCmd->xorMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3585	RT_UNTRUSTED_VALIDATED_FENCE();
3586
3587	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
3588	uint32_t const cbAndMask = cbAndLine * pCmd->height;
3589	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
3590	uint32_t const cbXorMask = cbXorLine * pCmd->height;
3591
3592	VMSVGA_INC_CMD_SIZE_BREAK(cbAndMask + cbXorMask);
3593	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
3594	break;
3595	}
3596
3597	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3598	{
3599	/* Followed by bitmap data. */
3600	SVGAFifoCmdDefineAlphaCursor pCmd = (SVGAFifoCmdDefineAlphaCursor )&pu8Cmd[cbCmd];
3601	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3602
3603	/* Figure out the size of the bitmap data. */
3604	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3605
3606	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->width * pCmd->height * sizeof(uint32_t)); /* 32-bit BRGA format */
3607	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
3608	break;
3609	}
3610
3611	case SVGA_CMD_MOVE_CURSOR:
3612	{
3613	/* Deprecated; there should be no driver which requires this command. However, if
3614	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3615	* alignment.
3616	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3617	*/
3618	SVGAFifoCmdMoveCursor pCmd = (SVGAFifoCmdMoveCursor )&pu8Cmd[cbCmd];
3619	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3620	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
3621	break;
3622	}
3623
3624	case SVGA_CMD_DISPLAY_CURSOR:
3625	{
3626	/* Deprecated; there should be no driver which requires this command. However, if
3627	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3628	* alignment.
3629	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3630	*/
3631	SVGAFifoCmdDisplayCursor pCmd = (SVGAFifoCmdDisplayCursor )&pu8Cmd[cbCmd];
3632	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3633	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
3634	break;
3635	}
3636
3637	case SVGA_CMD_RECT_FILL:
3638	{
3639	SVGAFifoCmdRectFill pCmd = (SVGAFifoCmdRectFill )&pu8Cmd[cbCmd];
3640	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3641	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
3642	break;
3643	}
3644
3645	case SVGA_CMD_RECT_COPY:
3646	{
3647	SVGAFifoCmdRectCopy pCmd = (SVGAFifoCmdRectCopy )&pu8Cmd[cbCmd];
3648	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3649	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
3650	break;
3651	}
3652
3653	case SVGA_CMD_RECT_ROP_COPY:
3654	{
3655	SVGAFifoCmdRectRopCopy pCmd = (SVGAFifoCmdRectRopCopy )&pu8Cmd[cbCmd];
3656	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3657	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
3658	break;
3659	}
3660
3661	case SVGA_CMD_ESCAPE:
3662	{
3663	/* Followed by 'size' bytes of data. */
3664	SVGAFifoCmdEscape pCmd = (SVGAFifoCmdEscape )&pu8Cmd[cbCmd];
3665	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3666
3667	ASSERT_GUEST_STMT_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3668	RT_UNTRUSTED_VALIDATED_FENCE();
3669
3670	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->size);
3671	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
3672	break;
3673	}
3674	# ifdef VBOX_WITH_VMSVGA3D
3675	case SVGA_CMD_DEFINE_GMR2:
3676	{
3677	SVGAFifoCmdDefineGMR2 pCmd = (SVGAFifoCmdDefineGMR2 )&pu8Cmd[cbCmd];
3678	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3679	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
3680	break;
3681	}
3682
3683	case SVGA_CMD_REMAP_GMR2:
3684	{
3685	/* Followed by page descriptors or guest ptr. */
3686	SVGAFifoCmdRemapGMR2 pCmd = (SVGAFifoCmdRemapGMR2 )&pu8Cmd[cbCmd];
3687	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3688
3689	/* Calculate the size of what comes after next and fetch it. */
3690	uint32_t cbMore = 0;
3691	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3692	cbMore = sizeof(SVGAGuestPtr);
3693	else
3694	{
3695	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3696	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3697	{
3698	cbMore = cbPageDesc;
3699	pCmd->numPages = 1;
3700	}
3701	else
3702	{
3703	ASSERT_GUEST_STMT_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3704	cbMore = cbPageDesc * pCmd->numPages;
3705	}
3706	}
3707	VMSVGA_INC_CMD_SIZE_BREAK(cbMore);
3708	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
3709	# ifdef DEBUG_GMR_ACCESS
3710	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
3711	# endif
3712	break;
3713	}
3714	# endif /* VBOX_WITH_VMSVGA3D */
3715	case SVGA_CMD_DEFINE_SCREEN:
3716	{
3717	/* The size of this command is specified by the guest and depends on capabilities. */
3718	SVGAFifoCmdDefineScreen pCmd = (SVGAFifoCmdDefineScreen )&pu8Cmd[cbCmd];
3719	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(pCmd->screen.structSize));
3720	ASSERT_GUEST_STMT_BREAK(pCmd->screen.structSize < pThis->svga.cbFIFO, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3721	RT_UNTRUSTED_VALIDATED_FENCE();
3722
3723	VMSVGA_INC_CMD_SIZE_BREAK(RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize) - sizeof(pCmd->screen.structSize));
3724	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
3725	break;
3726	}
3727
3728	case SVGA_CMD_DESTROY_SCREEN:
3729	{
3730	SVGAFifoCmdDestroyScreen pCmd = (SVGAFifoCmdDestroyScreen )&pu8Cmd[cbCmd];
3731	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3732	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
3733	break;
3734	}
3735
3736	case SVGA_CMD_DEFINE_GMRFB:
3737	{
3738	SVGAFifoCmdDefineGMRFB pCmd = (SVGAFifoCmdDefineGMRFB )&pu8Cmd[cbCmd];
3739	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3740	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
3741	break;
3742	}
3743
3744	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3745	{
3746	SVGAFifoCmdBlitGMRFBToScreen pCmd = (SVGAFifoCmdBlitGMRFBToScreen )&pu8Cmd[cbCmd];
3747	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3748	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
3749	break;
3750	}
3751
3752	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3753	{
3754	SVGAFifoCmdBlitScreenToGMRFB pCmd = (SVGAFifoCmdBlitScreenToGMRFB )&pu8Cmd[cbCmd];
3755	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3756	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
3757	break;
3758	}
3759
3760	case SVGA_CMD_ANNOTATION_FILL:
3761	{
3762	SVGAFifoCmdAnnotationFill pCmd = (SVGAFifoCmdAnnotationFill )&pu8Cmd[cbCmd];
3763	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3764	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
3765	break;
3766	}
3767
3768	case SVGA_CMD_ANNOTATION_COPY:
3769	{
3770	SVGAFifoCmdAnnotationCopy pCmd = (SVGAFifoCmdAnnotationCopy )&pu8Cmd[cbCmd];
3771	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3772	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
3773	break;
3774	}
3775
3776	default:
3777	{
3778	# ifdef VBOX_WITH_VMSVGA3D
3779	if ( cmdId >= SVGA_3D_CMD_BASE
3780	&& cmdId < SVGA_3D_CMD_MAX)
3781	{
3782	RT_UNTRUSTED_VALIDATED_FENCE();
3783
3784	/* All 3d commands start with a common header, which defines the identifier and the size
3785	* of the command. The identifier has been already read. Fetch the size.
3786	*/
3787	uint32_t const pcbMore = (uint32_t const )&pu8Cmd[cbCmd];
3788	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pcbMore));
3789	VMSVGA_INC_CMD_SIZE_BREAK(*pcbMore);
3790	if (RT_LIKELY(pThis->svga.f3DEnabled))
3791	{ /* likely */ }
3792	else
3793	{
3794	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", cmdId));
3795	break;
3796	}
3797
3798	/* Command data begins after the 32 bit command length. */
3799	int rc = vmsvgaR3Process3dCmd(pThis, pThisCC, idDXContext, (SVGAFifo3dCmdId)cmdId, *pcbMore, pcbMore + 1);
3800	if (RT_SUCCESS(rc))
3801	{ /* likely */ }
3802	else
3803	{
3804	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3805	break;
3806	}
3807	}
3808	else
3809	# endif /* VBOX_WITH_VMSVGA3D */
3810	{
3811	/* Unsupported command. */
3812	STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
3813	ASSERT_GUEST_MSG_FAILED(("cmdId=%d\n", cmdId));
3814	LogRelMax(16, ("VMSVGA: unsupported command %d\n", cmdId));
3815	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3816	break;
3817	}
3818	}
3819	}
3820
3821	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3822	break;
3823
3824	pu8Cmd += cbCmd;
3825	cbRemain -= cbCmd;
3826
3827	/* If this is not the last command in the buffer, then generate IRQ, if required.
3828	* This avoids a double call to vmsvgaR3CmdBufRaiseIRQ if FENCE is the last command
3829	* in the buffer (usually the case).
3830	*/
3831	if (RT_LIKELY(!(cbRemain && *pu32IrqStatus)))
3832	{ /* likely */ }
3833	else
3834	{
3835	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, *pu32IrqStatus);
3836	*pu32IrqStatus = 0;
3837	}
3838	}
3839
3840	Assert(cbRemain <= cbCommands);
3841	*poffNextCmd = cbCommands - cbRemain;
3842	return CBstatus;
3843	}
3844
3845
3846	/** Process command buffers.
3847	*
3848	* @param pDevIns The device instance.
3849	* @param pThis The shared VGA/VMSVGA state.
3850	* @param pThisCC The VGA/VMSVGA state for the current context.
3851	* @param pThread Handle of the FIFO thread.
3852	* @thread FIFO
3853	*/
3854	static void vmsvgaR3CmdBufProcessBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PPDMTHREAD pThread)
3855	{
3856	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3857
3858	for (;;)
3859	{
3860	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3861	break;
3862
3863	/* See if there is a submitted buffer. */
3864	PVMSVGACMDBUF pCmdBuf = NULL;
3865
3866	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3867	AssertRC(rc);
3868
3869	/* It seems that a higher queue index has a higher priority.
3870	* See SVGACBContext in svga_reg.h from latest vmwgfx Linux driver.
3871	*/
3872	for (unsigned i = RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs); i > 0; --i)
3873	{
3874	PVMSVGACMDBUFCTX pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[i - 1];
3875	if (pCmdBufCtx)
3876	{
3877	pCmdBuf = RTListRemoveFirst(&pCmdBufCtx->listSubmitted, VMSVGACMDBUF, nodeBuffer);
3878	if (pCmdBuf)
3879	{
3880	Assert(pCmdBufCtx->cSubmitted > 0);
3881	--pCmdBufCtx->cSubmitted;
3882	break;
3883	}
3884	}
3885	}
3886
3887	if (!pCmdBuf)
3888	{
3889	ASMAtomicWriteU32(&pSvgaR3State->fCmdBuf, 0);
3890	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3891	break;
3892	}
3893
3894	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3895
3896	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3897	uint32_t offNextCmd = 0;
3898	uint32_t u32IrqStatus = 0;
3899	uint32_t const idDXContext = RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_DX_CONTEXT)
3900	? pCmdBuf->hdr.dxContext
3901	: SVGA3D_INVALID_ID;
3902	/* Process one buffer. */
3903	CBstatus = vmsvgaR3CmdBufProcessCommands(pDevIns, pThis, pThisCC, idDXContext, pCmdBuf->pvCommands, pCmdBuf->hdr.length, &offNextCmd, &u32IrqStatus);
3904
3905	if (!RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_NO_IRQ))
3906	u32IrqStatus \|= SVGA_IRQFLAG_COMMAND_BUFFER;
3907	if (CBstatus == SVGA_CB_STATUS_COMMAND_ERROR)
3908	u32IrqStatus \|= SVGA_IRQFLAG_ERROR;
3909
3910	vmsvgaR3CmdBufWriteStatus(pDevIns, pCmdBuf->GCPhysCB, CBstatus, offNextCmd);
3911	if (u32IrqStatus)
3912	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, u32IrqStatus);
3913
3914	vmsvgaR3CmdBufFree(pCmdBuf);
3915	}
3916	}
3917
3918
3919	/**
3920	* Worker for vmsvgaR3FifoThread that handles an external command.
3921	*
3922	* @param pDevIns The device instance.
3923	* @param pThis The shared VGA/VMSVGA instance data.
3924	* @param pThisCC The VGA/VMSVGA state for ring-3.
3925	*/
3926	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3927	{
3928	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
3929	switch (pThis->svga.u8FIFOExtCommand)
3930	{
3931	case VMSVGA_FIFO_EXTCMD_RESET:
3932	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
3933	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3934
3935	vmsvgaR3ResetScreens(pThis, pThisCC);
3936	# ifdef VBOX_WITH_VMSVGA3D
3937	if (pThis->svga.f3DEnabled)
3938	{
3939	/* The 3d subsystem must be reset from the fifo thread. */
3940	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3941	pSVGAState->pFuncs3D->pfnReset(pThisCC);
3942	}
3943	# endif
3944	break;
3945
3946	case VMSVGA_FIFO_EXTCMD_POWEROFF:
3947	Log(("vmsvgaR3FifoLoop: power off.\n"));
3948	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3949
3950	/* The screens must be reset on the FIFO thread, because they may use 3D resources. */
3951	vmsvgaR3ResetScreens(pThis, pThisCC);
3952	break;
3953
3954	case VMSVGA_FIFO_EXTCMD_TERMINATE:
3955	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
3956	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3957	# ifdef VBOX_WITH_VMSVGA3D
3958	if (pThis->svga.f3DEnabled)
3959	{
3960	/* The 3d subsystem must be shut down from the fifo thread. */
3961	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3962	if (pSVGAState->pFuncs3D && pSVGAState->pFuncs3D->pfnTerminate)
3963	pSVGAState->pFuncs3D->pfnTerminate(pThisCC);
3964	}
3965	# endif
3966	break;
3967
3968	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
3969	{
3970	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
3971	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
3972	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
3973	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
3974	# ifdef VBOX_WITH_VMSVGA3D
3975	if (pThis->svga.f3DEnabled)
3976	{
3977	if (vmsvga3dIsLegacyBackend(pThisCC))
3978	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
3979	# ifdef VMSVGA3D_DX
3980	else
3981	vmsvga3dDXSaveExec(pDevIns, pThisCC, pSSM);
3982	# endif
3983	}
3984	# endif
3985	break;
3986	}
3987
3988	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
3989	{
3990	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
3991	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
3992	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
3993	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3994	# ifdef VBOX_WITH_VMSVGA3D
3995	if (pThis->svga.f3DEnabled)
3996	{
3997	/* The following RT_OS_DARWIN code was in vmsvga3dLoadExec and therefore must be executed before each vmsvga3dLoadExec invocation. */
3998	# ifndef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA.cpp */
3999	/* Must initialize now as the recreation calls below rely on an initialized 3d subsystem. */
4000	vmsvgaR3PowerOnDevice(pDevIns, pThis, pThisCC, /fLoadState=/ true);
4001	# endif
4002
4003	if (vmsvga3dIsLegacyBackend(pThisCC))
4004	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
4005	# ifdef VMSVGA3D_DX
4006	else
4007	vmsvga3dDXLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
4008	# endif
4009	}
4010	# endif
4011	break;
4012	}
4013
4014	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
4015	{
4016	# ifdef VBOX_WITH_VMSVGA3D
4017	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
4018	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
4019	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
4020	# endif
4021	break;
4022	}
4023
4024
4025	default:
4026	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
4027	break;
4028	}
4029
4030	/*
4031	* Signal the end of the external command.
4032	*/
4033	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4034	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
4035	ASMMemoryFence(); /* paranoia^2 */
4036	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
4037	AssertLogRelRC(rc);
4038	}
4039
4040	/**
4041	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
4042	* doing a job on the FIFO thread (even when it's officially suspended).
4043	*
4044	* @returns VBox status code (fully asserted).
4045	* @param pDevIns The device instance.
4046	* @param pThis The shared VGA/VMSVGA instance data.
4047	* @param pThisCC The VGA/VMSVGA state for ring-3.
4048	* @param uExtCmd The command to execute on the FIFO thread.
4049	* @param pvParam Pointer to command parameters.
4050	* @param cMsWait The time to wait for the command, given in
4051	* milliseconds.
4052	*/
4053	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
4054	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
4055	{
4056	Assert(cMsWait >= RT_MS_1SEC * 5);
4057	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
4058	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
4059
4060	int rc;
4061	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
4062	PDMTHREADSTATE enmState = pThread->enmState;
4063	if (enmState == PDMTHREADSTATE_SUSPENDED)
4064	{
4065	/*
4066	* The thread is suspended, we have to temporarily wake it up so it can
4067	* perform the task.
4068	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
4069	*/
4070	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
4071	/* Post the request. */
4072	pThis->svga.fFifoExtCommandWakeup = true;
4073	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4074	pThis->svga.u8FIFOExtCommand = uExtCmd;
4075	ASMMemoryFence(); /* paranoia^3 */
4076
4077	/* Resume the thread. */
4078	rc = PDMDevHlpThreadResume(pDevIns, pThread);
4079	AssertLogRelRC(rc);
4080	if (RT_SUCCESS(rc))
4081	{
4082	/* Wait. Take care in case the semaphore was already posted (same as below). */
4083	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4084	if ( rc == VINF_SUCCESS
4085	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4086	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4087	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4088	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4089
4090	/* suspend the thread */
4091	pThis->svga.fFifoExtCommandWakeup = false;
4092	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
4093	AssertLogRelRC(rc2);
4094	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
4095	rc = rc2;
4096	}
4097	pThis->svga.fFifoExtCommandWakeup = false;
4098	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4099	}
4100	else if (enmState == PDMTHREADSTATE_RUNNING)
4101	{
4102	/*
4103	* The thread is running, should only happen during reset and vmsvga3dsfc.
4104	* We ASSUME not racing code here, both wrt thread state and ext commands.
4105	*/
4106	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
4107	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_POWEROFF);
4108
4109	/* Post the request. */
4110	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4111	pThis->svga.u8FIFOExtCommand = uExtCmd;
4112	ASMMemoryFence(); /* paranoia^2 */
4113	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4114	AssertLogRelRC(rc);
4115
4116	/* Wait. Take care in case the semaphore was already posted (same as above). */
4117	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4118	if ( rc == VINF_SUCCESS
4119	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4120	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
4121	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4122	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4123
4124	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4125	}
4126	else
4127	{
4128	/*
4129	* Something is wrong with the thread!
4130	*/
4131	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
4132	rc = VERR_INVALID_STATE;
4133	}
4134	return rc;
4135	}
4136
4137
4138	/**
4139	* Marks the FIFO non-busy, notifying any waiting EMTs.
4140	*
4141	* @param pDevIns The device instance.
4142	* @param pThis The shared VGA/VMSVGA instance data.
4143	* @param pThisCC The VGA/VMSVGA state for ring-3.
4144	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
4145	* @param offFifoMin The start byte offset of the command FIFO.
4146	*/
4147	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
4148	{
4149	ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO \| VMSVGA_BUSY_F_EMT_FORCE));
4150	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4151	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
4152
4153	/* Wake up any waiting EMTs. */
4154	if (pSVGAState->cBusyDelayedEmts > 0)
4155	{
4156	# ifdef VMSVGA_USE_EMT_HALT_CODE
4157	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
4158	if (idCpu != NIL_VMCPUID)
4159	{
4160	PDMDevHlpVMNotifyCpuDeviceReady(pDevIns, idCpu);
4161	while (idCpu-- > 0)
4162	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
4163	PDMDevHlpVMNotifyCpuDeviceReady(pDevIns, idCpu);
4164	}
4165	# else
4166	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
4167	AssertRC(rc2);
4168	# endif
4169	}
4170	}
4171
4172	/**
4173	* Reads (more) payload into the command buffer.
4174	*
4175	* @returns pbBounceBuf on success
4176	* @retval (void *)1 if the thread was requested to stop.
4177	* @retval NULL on FIFO error.
4178	*
4179	* @param cbPayloadReq The number of bytes of payload requested.
4180	* @param pFIFO The FIFO.
4181	* @param offCurrentCmd The FIFO byte offset of the current command.
4182	* @param offFifoMin The start byte offset of the command FIFO.
4183	* @param offFifoMax The end byte offset of the command FIFO.
4184	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
4185	* always sufficient size.
4186	* @param pcbAlreadyRead How much payload we've already read into the bounce
4187	* buffer. (We will NEVER re-read anything.)
4188	* @param pThread The calling PDM thread handle.
4189	* @param pThis The shared VGA/VMSVGA instance data.
4190	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
4191	* statistics collection.
4192	* @param pDevIns The device instance.
4193	*/
4194	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
4195	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
4196	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
4197	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
4198	{
4199	Assert(pbBounceBuf);
4200	Assert(pcbAlreadyRead);
4201	Assert(offFifoMin < offFifoMax);
4202	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
4203	Assert(offFifoMax <= pThis->svga.cbFIFO);
4204
4205	/*
4206	* Check if the requested payload size has already been satisfied .
4207	* .
4208	* When called to read more, the caller is responsible for making sure the .
4209	* new command size (cbRequsted) never is smaller than what has already .
4210	* been read.
4211	*/
4212	uint32_t cbAlreadyRead = *pcbAlreadyRead;
4213	if (cbPayloadReq <= cbAlreadyRead)
4214	{
4215	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
4216	return pbBounceBuf;
4217	}
4218
4219	/*
4220	* Commands bigger than the fifo buffer are invalid.
4221	*/
4222	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
4223	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
4224	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
4225	NULL);
4226
4227	/*
4228	* Move offCurrentCmd past the command dword.
4229	*/
4230	offCurrentCmd += sizeof(uint32_t);
4231	if (offCurrentCmd >= offFifoMax)
4232	offCurrentCmd = offFifoMin;
4233
4234	/*
4235	* Do we have sufficient payload data available already?
4236	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
4237	*/
4238	uint32_t cbAfter, cbBefore;
4239	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4240	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4241	if (offNextCmd >= offCurrentCmd)
4242	{
4243	if (RT_LIKELY(offNextCmd < offFifoMax))
4244	cbAfter = offNextCmd - offCurrentCmd;
4245	else
4246	{
4247	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4248	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4249	offNextCmd, offFifoMin, offFifoMax));
4250	cbAfter = offFifoMax - offCurrentCmd;
4251	}
4252	cbBefore = 0;
4253	}
4254	else
4255	{
4256	cbAfter = offFifoMax - offCurrentCmd;
4257	if (offNextCmd >= offFifoMin)
4258	cbBefore = offNextCmd - offFifoMin;
4259	else
4260	{
4261	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4262	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4263	offNextCmd, offFifoMin, offFifoMax));
4264	cbBefore = 0;
4265	}
4266	}
4267	if (cbAfter + cbBefore < cbPayloadReq)
4268	{
4269	/*
4270	* Insufficient, must wait for it to arrive.
4271	*/
4272	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
4273	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
4274	for (uint32_t i = 0;; i++)
4275	{
4276	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4277	{
4278	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4279	return (void *)(uintptr_t)1;
4280	}
4281	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
4282	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
4283
4284	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
4285
4286	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4287	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4288	if (offNextCmd >= offCurrentCmd)
4289	{
4290	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
4291	cbBefore = 0;
4292	}
4293	else
4294	{
4295	cbAfter = offFifoMax - offCurrentCmd;
4296	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
4297	}
4298
4299	if (cbAfter + cbBefore >= cbPayloadReq)
4300	break;
4301	}
4302	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4303	}
4304
4305	/*
4306	* Copy out the memory and update what pcbAlreadyRead points to.
4307	*/
4308	if (cbAfter >= cbPayloadReq)
4309	memcpy(pbBounceBuf + cbAlreadyRead,
4310	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4311	cbPayloadReq - cbAlreadyRead);
4312	else
4313	{
4314	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
4315	if (cbAlreadyRead < cbAfter)
4316	{
4317	memcpy(pbBounceBuf + cbAlreadyRead,
4318	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4319	cbAfter - cbAlreadyRead);
4320	cbAlreadyRead = cbAfter;
4321	}
4322	memcpy(pbBounceBuf + cbAlreadyRead,
4323	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
4324	cbPayloadReq - cbAlreadyRead);
4325	}
4326	*pcbAlreadyRead = cbPayloadReq;
4327	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4328	return pbBounceBuf;
4329	}
4330
4331
4332	/**
4333	* Sends cursor position and visibility information from the FIFO to the front-end.
4334	* @returns SVGA_FIFO_CURSOR_COUNT value used.
4335	*/
4336	static uint32_t
4337	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
4338	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
4339	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
4340	{
4341	/*
4342	* Check if the cursor update counter has changed and try get a stable
4343	* set of values if it has. This is race-prone, especially consindering
4344	* the screen ID, but little we can do about that.
4345	*/
4346	uint32_t x, y, fVisible, idScreen;
4347	for (uint32_t i = 0; ; i++)
4348	{
4349	x = pFIFO[SVGA_FIFO_CURSOR_X];
4350	y = pFIFO[SVGA_FIFO_CURSOR_Y];
4351	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
4352	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
4353	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
4354	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
4355	\|\| i > 3)
4356	break;
4357	if (i == 0)
4358	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
4359	ASMNopPause();
4360	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4361	}
4362
4363	/*
4364	* Check if anything has changed, as calling into pDrv is not light-weight.
4365	*/
4366	if ( *pxLast == x
4367	&& *pyLast == y
4368	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
4369	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
4370	else
4371	{
4372	/*
4373	* Detected changes.
4374	*
4375	* We handle global, not per-screen visibility information by sending
4376	* pfnVBVAMousePointerShape without shape data.
4377	*/
4378	*pxLast = x;
4379	*pyLast = y;
4380	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
4381	if (idScreen != SVGA_ID_INVALID)
4382	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
4383	else if (*pfLastVisible != fVisible)
4384	{
4385	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
4386	*pfLastVisible = fVisible;
4387	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
4388	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
4389	}
4390	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
4391	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
4392	}
4393
4394	/*
4395	* Update done. Signal this to the guest.
4396	*/
4397	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
4398
4399	return uCursorUpdateCount;
4400	}
4401
4402
4403	/**
4404	* Checks if there is work to be done, either cursor updating or FIFO commands.
4405	*
4406	* @returns true if pending work, false if not.
4407	* @param pThisCC The VGA/VMSVGA state for ring-3.
4408	* @param uLastCursorCount The last cursor update counter value.
4409	*/
4410	DECLINLINE(bool) vmsvgaR3FifoHasWork(PVGASTATECC pThisCC, uint32_t uLastCursorCount)
4411	{
4412	/* If FIFO does not exist than there is nothing to do. Command buffers also require the enabled FIFO. */
4413	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4414	AssertReturn(pFIFO, false);
4415
4416	if (vmsvgaR3CmdBufHasWork(pThisCC))
4417	return true;
4418
4419	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
4420	return true;
4421
4422	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
4423	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
4424	return true;
4425
4426	return false;
4427	}
4428
4429
4430	/**
4431	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
4432	*
4433	* @param pDevIns The device instance.
4434	* @param pThis The shared VGA/VMSVGA instance data.
4435	* @param pThisCC The VGA/VMSVGA state for ring-3.
4436	*/
4437	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4438	{
4439	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
4440	to recheck it before doing the signalling. */
4441	if ( vmsvgaR3FifoHasWork(pThisCC, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
4442	&& pThis->svga.fFIFOThreadSleeping
4443	&& !ASMAtomicReadBool(&pThis->svga.fBadGuest))
4444	{
4445	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4446	AssertRC(rc);
4447	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
4448	}
4449	}
4450
4451
4452	/**
4453	* Called by the FIFO thread to process pending actions.
4454	*
4455	* @param pDevIns The device instance.
4456	* @param pThis The shared VGA/VMSVGA instance data.
4457	* @param pThisCC The VGA/VMSVGA state for ring-3.
4458	*/
4459	void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4460	{
4461	RT_NOREF(pDevIns);
4462
4463	/* Currently just mode changes. */
4464	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
4465	{
4466	vmsvgaR3ChangeMode(pThis, pThisCC);
4467	# ifdef VBOX_WITH_VMSVGA3D
4468	if (pThisCC->svga.p3dState != NULL)
4469	vmsvga3dChangeMode(pThisCC);
4470	# endif
4471	}
4472	}
4473
4474
4475	/*
4476	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
4477	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
4478	*/
4479	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4480	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
4481	*
4482	* Will break out of the switch on failure.
4483	* Will restart and quit the loop if the thread was requested to stop.
4484	*
4485	* @param a_PtrVar Request variable pointer.
4486	* @param a_Type Request typedef (not pointer) for casting.
4487	* @param a_cbPayloadReq How much payload to fetch.
4488	* @remarks Accesses a bunch of variables in the current scope!
4489	*/
4490	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4491	if (1) { \
4492	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
4493	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
4494	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
4495	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
4496	} else do {} while (0)
4497	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4498	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
4499	* buffer after figuring out the actual command size.
4500	*
4501	* Will break out of the switch on failure.
4502	*
4503	* @param a_PtrVar Request variable pointer.
4504	* @param a_Type Request typedef (not pointer) for casting.
4505	* @param a_cbPayloadReq How much payload to fetch.
4506	* @remarks Accesses a bunch of variables in the current scope!
4507	*/
4508	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4509	if (1) { \
4510	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
4511	} else do {} while (0)
4512
4513	/**
4514	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
4515	*/
4516	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4517	{
4518	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4519	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4520	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4521	int rc;
4522
4523	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4524	return VINF_SUCCESS;
4525
4526	/*
4527	* Special mode where we only execute an external command and the go back
4528	* to being suspended. Currently, all ext cmds ends up here, with the reset
4529	* one also being eligble for runtime execution further down as well.
4530	*/
4531	if (pThis->svga.fFifoExtCommandWakeup)
4532	{
4533	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4534	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4535	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
4536	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
4537	else
4538	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4539	return VINF_SUCCESS;
4540	}
4541
4542
4543	/*
4544	* Signal the semaphore to make sure we don't wait for 250ms after a
4545	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
4546	*/
4547	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4548
4549	/*
4550	* Allocate a bounce buffer for command we get from the FIFO.
4551	* (All code must return via the end of the function to free this buffer.)
4552	*/
4553	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
4554	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
4555
4556	/*
4557	* Polling/sleep interval config.
4558	*
4559	* We wait for an a short interval if the guest has recently given us work
4560	* to do, but the interval increases the longer we're kept idle. Once we've
4561	* reached the refresh timer interval, we'll switch to extended waits,
4562	* depending on it or the guest to kick us into action when needed.
4563	*
4564	* Should the refresh time go fishing, we'll just continue increasing the
4565	* sleep length till we reaches the 250 ms max after about 16 seconds.
4566	*/
4567	RTMSINTERVAL const cMsMinSleep = 16;
4568	RTMSINTERVAL const cMsIncSleep = 2;
4569	RTMSINTERVAL const cMsMaxSleep = 250;
4570	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
4571	RTMSINTERVAL cMsSleep = cMsMaxSleep;
4572
4573	/*
4574	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
4575	*
4576	* Initialize with values that will detect an update from the guest.
4577	* Make sure that if the guest never updates the cursor position, then the device does not report it.
4578	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
4579	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
4580	*/
4581	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4582	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4583	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
4584	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
4585	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
4586
4587	/*
4588	* The FIFO loop.
4589	*/
4590	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
4591	bool fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4592	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4593	{
4594	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
4595	/*
4596	* Should service the run loop every so often.
4597	*/
4598	if (pThis->svga.f3DEnabled)
4599	vmsvga3dCocoaServiceRunLoop();
4600	# endif
4601
4602	/* First check any pending actions. */
4603	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4604
4605	/*
4606	* Unless there's already work pending, go to sleep for a short while.
4607	* (See polling/sleep interval config above.)
4608	*/
4609	if ( fBadOrDisabledFifo
4610	\|\| !vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4611	{
4612	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
4613	Assert(pThis->cMilliesRefreshInterval > 0);
4614	if (cMsSleep < pThis->cMilliesRefreshInterval)
4615	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
4616	else
4617	{
4618	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
4619	int rc2 = PDMDevHlpPGMHandlerPhysicalReset(pDevIns, pThis->svga.GCPhysFIFO);
4620	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
4621	# endif
4622	if ( !fBadOrDisabledFifo
4623	&& vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4624	rc = VINF_SUCCESS;
4625	else
4626	{
4627	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
4628	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
4629	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
4630	}
4631	}
4632	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
4633	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
4634	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4635	{
4636	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
4637	break;
4638	}
4639	}
4640	else
4641	rc = VINF_SUCCESS;
4642	fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4643	if (rc == VERR_TIMEOUT)
4644	{
4645	if (!vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4646	{
4647	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
4648	continue;
4649	}
4650	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
4651
4652	Log(("vmsvgaR3FifoLoop: timeout\n"));
4653	}
4654	else if (vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4655	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
4656	cMsSleep = cMsMinSleep;
4657
4658	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
4659	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
4660	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
4661
4662	/*
4663	* Handle external commands (currently only reset).
4664	*/
4665	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4666	{
4667	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4668	continue;
4669	}
4670
4671	/*
4672	* If guest misbehaves, then do nothing.
4673	*/
4674	if (ASMAtomicReadBool(&pThis->svga.fBadGuest))
4675	{
4676	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4677	cMsSleep = cMsExtendedSleep;
4678	LogRelMax(1, ("VMSVGA: FIFO processing stopped because of the guest misbehavior\n"));
4679	continue;
4680	}
4681
4682	/*
4683	* The device must be enabled and configured.
4684	*/
4685	if ( !pThis->svga.fEnabled
4686	\|\| !pThis->svga.fConfigured)
4687	{
4688	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4689	fBadOrDisabledFifo = true;
4690	cMsSleep = cMsMaxSleep; /* cheat */
4691	continue;
4692	}
4693
4694	/*
4695	* Get and check the min/max values. We ASSUME that they will remain
4696	* unchanged while we process requests. A further ASSUMPTION is that
4697	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
4698	* we don't read it back while in the loop.
4699	*/
4700	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
4701	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
4702	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
4703	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4704	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
4705	\|\| offFifoMax <= offFifoMin
4706	\|\| offFifoMax > pThis->svga.cbFIFO
4707	\|\| (offFifoMax & 3) != 0
4708	\|\| (offFifoMin & 3) != 0
4709	\|\| offCurrentCmd < offFifoMin
4710	\|\| offCurrentCmd > offFifoMax))
4711	{
4712	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4713	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
4714	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4715	fBadOrDisabledFifo = true;
4716	continue;
4717	}
4718	RT_UNTRUSTED_VALIDATED_FENCE();
4719	if (RT_UNLIKELY(offCurrentCmd & 3))
4720	{
4721	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4722	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
4723	offCurrentCmd &= ~UINT32_C(3);
4724	}
4725
4726	/*
4727	* Update the cursor position before we start on the FIFO commands.
4728	*/
4729	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
4730	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
4731	{
4732	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4733	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
4734	{ /* halfways likely */ }
4735	else
4736	{
4737	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
4738	&xLastCursor, &yLastCursor, &fLastCursorVisible);
4739	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
4740	}
4741	}
4742
4743	/*
4744	* Mark the FIFO as busy.
4745	*/
4746	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
4747	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4748	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
4749
4750	/*
4751	* Process all submitted command buffers.
4752	*/
4753	vmsvgaR3CmdBufProcessBuffers(pDevIns, pThis, pThisCC, pThread);
4754
4755	/*
4756	* Execute all queued FIFO commands.
4757	* Quit if pending external command or changes in the thread state.
4758	*/
4759	bool fDone = false;
4760	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
4761	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
4762	{
4763	uint32_t cbPayload = 0;
4764	uint32_t u32IrqStatus = 0;
4765
4766	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
4767
4768	/* First check any pending actions. */
4769	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4770
4771	/* Check for pending external commands (reset). */
4772	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4773	break;
4774
4775	/*
4776	* Process the command.
4777	*/
4778	/* 'enmCmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
4779	* warning. Because we implement some obsolete and deprecated commands, which are not included in
4780	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
4781	*/
4782	uint32_t const enmCmdId = pFIFO[offCurrentCmd / sizeof(uint32_t)];
4783	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4784	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s %d\n",
4785	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
4786	switch (enmCmdId)
4787	{
4788	case SVGA_CMD_INVALID_CMD:
4789	/* Nothing to do. */
4790	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
4791	break;
4792
4793	case SVGA_CMD_FENCE:
4794	{
4795	SVGAFifoCmdFence *pCmdFence;
4796	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
4797	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
4798	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
4799	{
4800	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %#x\n", pCmdFence->fence));
4801	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
4802
4803	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
4804	{
4805	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
4806	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
4807	}
4808	else
4809	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
4810	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
4811	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
4812	{
4813	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%#x)\n", pCmdFence->fence));
4814	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
4815	}
4816	}
4817	else
4818	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
4819	break;
4820	}
4821
4822	case SVGA_CMD_UPDATE:
4823	{
4824	SVGAFifoCmdUpdate *pCmd;
4825	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdate, sizeof(*pCmd));
4826	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
4827	break;
4828	}
4829
4830	case SVGA_CMD_UPDATE_VERBOSE:
4831	{
4832	SVGAFifoCmdUpdateVerbose *pCmd;
4833	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdateVerbose, sizeof(*pCmd));
4834	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
4835	break;
4836	}
4837
4838	case SVGA_CMD_DEFINE_CURSOR:
4839	{
4840	/* Followed by bitmap data. */
4841	SVGAFifoCmdDefineCursor *pCmd;
4842	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, sizeof(*pCmd));
4843
4844	/* Figure out the size of the bitmap data. */
4845	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4846	ASSERT_GUEST_BREAK(pCmd->andMaskDepth <= 32);
4847	ASSERT_GUEST_BREAK(pCmd->xorMaskDepth <= 32);
4848	RT_UNTRUSTED_VALIDATED_FENCE();
4849
4850	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
4851	uint32_t const cbAndMask = cbAndLine * pCmd->height;
4852	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
4853	uint32_t const cbXorMask = cbXorLine * pCmd->height;
4854
4855	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineCursor) + cbAndMask + cbXorMask;
4856	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, cbCmd);
4857	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
4858	break;
4859	}
4860
4861	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
4862	{
4863	/* Followed by bitmap data. */
4864	SVGAFifoCmdDefineAlphaCursor *pCmd;
4865	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCmd));
4866
4867	/* Figure out the size of the bitmap data. */
4868	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4869
4870	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCmd->width * pCmd->height * sizeof(uint32_t) /* 32-bit BRGA format */;
4871	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, cbCmd);
4872	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
4873	break;
4874	}
4875
4876	case SVGA_CMD_MOVE_CURSOR:
4877	{
4878	/* Deprecated; there should be no driver which requires this command. However, if
4879	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4880	* alignment.
4881	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4882	*/
4883	SVGAFifoCmdMoveCursor *pCmd;
4884	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdMoveCursor, sizeof(*pCmd));
4885	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
4886	break;
4887	}
4888
4889	case SVGA_CMD_DISPLAY_CURSOR:
4890	{
4891	/* Deprecated; there should be no driver which requires this command. However, if
4892	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4893	* alignment.
4894	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4895	*/
4896	SVGAFifoCmdDisplayCursor *pCmd;
4897	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDisplayCursor, sizeof(*pCmd));
4898	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
4899	break;
4900	}
4901
4902	case SVGA_CMD_RECT_FILL:
4903	{
4904	SVGAFifoCmdRectFill *pCmd;
4905	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectFill, sizeof(*pCmd));
4906	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
4907	break;
4908	}
4909
4910	case SVGA_CMD_RECT_COPY:
4911	{
4912	SVGAFifoCmdRectCopy *pCmd;
4913	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectCopy, sizeof(*pCmd));
4914	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
4915	break;
4916	}
4917
4918	case SVGA_CMD_RECT_ROP_COPY:
4919	{
4920	SVGAFifoCmdRectRopCopy *pCmd;
4921	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectRopCopy, sizeof(*pCmd));
4922	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
4923	break;
4924	}
4925
4926	case SVGA_CMD_ESCAPE:
4927	{
4928	/* Followed by 'size' bytes of data. */
4929	SVGAFifoCmdEscape *pCmd;
4930	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, sizeof(*pCmd));
4931
4932	ASSERT_GUEST_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape));
4933	RT_UNTRUSTED_VALIDATED_FENCE();
4934
4935	uint32_t const cbCmd = sizeof(SVGAFifoCmdEscape) + pCmd->size;
4936	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, cbCmd);
4937	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
4938	break;
4939	}
4940	# ifdef VBOX_WITH_VMSVGA3D
4941	case SVGA_CMD_DEFINE_GMR2:
4942	{
4943	SVGAFifoCmdDefineGMR2 *pCmd;
4944	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
4945	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
4946	break;
4947	}
4948
4949	case SVGA_CMD_REMAP_GMR2:
4950	{
4951	/* Followed by page descriptors or guest ptr. */
4952	SVGAFifoCmdRemapGMR2 *pCmd;
4953	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
4954
4955	/* Calculate the size of what comes after next and fetch it. */
4956	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
4957	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4958	cbCmd += sizeof(SVGAGuestPtr);
4959	else
4960	{
4961	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
4962	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
4963	{
4964	cbCmd += cbPageDesc;
4965	pCmd->numPages = 1;
4966	}
4967	else
4968	{
4969	ASSERT_GUEST_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
4970	cbCmd += cbPageDesc * pCmd->numPages;
4971	}
4972	}
4973	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
4974	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
4975	# ifdef DEBUG_GMR_ACCESS
4976	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4977	# endif
4978	break;
4979	}
4980	# endif // VBOX_WITH_VMSVGA3D
4981	case SVGA_CMD_DEFINE_SCREEN:
4982	{
4983	/* The size of this command is specified by the guest and depends on capabilities. */
4984	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4985
4986	SVGAFifoCmdDefineScreen *pCmd;
4987	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4988	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4989	RT_UNTRUSTED_VALIDATED_FENCE();
4990
4991	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4992	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4993	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
4994	break;
4995	}
4996
4997	case SVGA_CMD_DESTROY_SCREEN:
4998	{
4999	SVGAFifoCmdDestroyScreen *pCmd;
5000	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
5001	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
5002	break;
5003	}
5004
5005	case SVGA_CMD_DEFINE_GMRFB:
5006	{
5007	SVGAFifoCmdDefineGMRFB *pCmd;
5008	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
5009	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
5010	break;
5011	}
5012
5013	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
5014	{
5015	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
5016	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
5017	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
5018	break;
5019	}
5020
5021	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
5022	{
5023	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
5024	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
5025	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
5026	break;
5027	}
5028
5029	case SVGA_CMD_ANNOTATION_FILL:
5030	{
5031	SVGAFifoCmdAnnotationFill *pCmd;
5032	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
5033	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
5034	break;
5035	}
5036
5037	case SVGA_CMD_ANNOTATION_COPY:
5038	{
5039	SVGAFifoCmdAnnotationCopy *pCmd;
5040	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
5041	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
5042	break;
5043	}
5044
5045	default:
5046	# ifdef VBOX_WITH_VMSVGA3D
5047	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
5048	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
5049	{
5050	RT_UNTRUSTED_VALIDATED_FENCE();
5051
5052	/* All 3d commands start with a common header, which defines the identifier and the size
5053	* of the command. The identifier has been already read from FIFO. Fetch the size.
5054	*/
5055	uint32_t *pcbCmd;
5056	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pcbCmd, uint32_t, sizeof(*pcbCmd));
5057	uint32_t const cbCmd = *pcbCmd;
5058	AssertBreak(cbCmd < pThis->svga.cbFIFO);
5059	uint32_t *pu32Cmd;
5060	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pu32Cmd, uint32_t, sizeof(*pcbCmd) + cbCmd);
5061	pu32Cmd++; /* Skip the command size. */
5062
5063	if (RT_LIKELY(pThis->svga.f3DEnabled))
5064	{ /* likely */ }
5065	else
5066	{
5067	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", enmCmdId));
5068	break;
5069	}
5070
5071	vmsvgaR3Process3dCmd(pThis, pThisCC, SVGA3D_INVALID_ID, (SVGAFifo3dCmdId)enmCmdId, cbCmd, pu32Cmd);
5072	}
5073	else
5074	# endif // VBOX_WITH_VMSVGA3D
5075	{
5076	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
5077	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
5078	LogRelMax(16, ("VMSVGA: unsupported command %d\n", enmCmdId));
5079	}
5080	}
5081
5082	/* Go to the next slot */
5083	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
5084	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
5085	if (offCurrentCmd >= offFifoMax)
5086	{
5087	offCurrentCmd -= offFifoMax - offFifoMin;
5088	Assert(offCurrentCmd >= offFifoMin);
5089	Assert(offCurrentCmd < offFifoMax);
5090	}
5091	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
5092	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
5093
5094	/*
5095	* Raise IRQ if required. Must enter the critical section here
5096	* before making final decisions here, otherwise cubebench and
5097	* others may end up waiting forever.
5098	*/
5099	if ( u32IrqStatus
5100	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
5101	{
5102	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
5103	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
5104
5105	/* FIFO progress might trigger an interrupt. */
5106	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
5107	{
5108	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
5109	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
5110	}
5111
5112	/* Unmasked IRQ pending? */
5113	if (pThis->svga.u32IrqMask & u32IrqStatus)
5114	{
5115	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
5116	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
5117	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
5118	}
5119
5120	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5121	}
5122	}
5123
5124	/* If really done, clear the busy flag. */
5125	if (fDone)
5126	{
5127	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
5128	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
5129	}
5130	}
5131
5132	/*
5133	* Free the bounce buffer. (There are no returns above!)
5134	*/
5135	RTMemFree(pbBounceBuf);
5136
5137	return VINF_SUCCESS;
5138	}
5139
5140	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
5141	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
5142
5143	/**
5144	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5145	* Unblock the FIFO I/O thread so it can respond to a state change.}
5146	*/
5147	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5148	{
5149	RT_NOREF(pDevIns);
5150	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5151	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5152	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5153	}
5154
5155	/**
5156	* Enables or disables dirty page tracking for the framebuffer
5157	*
5158	* @param pDevIns The device instance.
5159	* @param pThis The shared VGA/VMSVGA instance data.
5160	* @param fTraces Enable/disable traces
5161	*/
5162	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5163	{
5164	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5165	&& !fTraces)
5166	{
5167	//Assert(pThis->svga.fTraces);
5168	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5169	return;
5170	}
5171
5172	pThis->svga.fTraces = fTraces;
5173	if (pThis->svga.fTraces)
5174	{
5175	unsigned cbFrameBuffer = pThis->vram_size;
5176
5177	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5178	/** @todo How does this work with screens? */
5179	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5180	{
5181	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5182	Assert(pThis->svga.cbScanline);
5183	# endif
5184	/* Hardware enabled; return real framebuffer size .*/
5185	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5186	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, GUEST_PAGE_SIZE);
5187	}
5188
5189	if (!pThis->svga.fVRAMTracking)
5190	{
5191	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5192	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5193	pThis->svga.fVRAMTracking = true;
5194	}
5195	}
5196	else
5197	{
5198	if (pThis->svga.fVRAMTracking)
5199	{
5200	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5201	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5202	pThis->svga.fVRAMTracking = false;
5203	}
5204	}
5205	}
5206
5207	/**
5208	* @callback_method_impl{FNPCIIOREGIONMAP}
5209	*/
5210	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5211	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5212	{
5213	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5214	int rc;
5215	RT_NOREF(pPciDev);
5216	Assert(pPciDev == pDevIns->apPciDevs[0]);
5217
5218	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5219	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5220	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5221	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5222	, VERR_INTERNAL_ERROR);
5223	if (GCPhysAddress != NIL_RTGCPHYS)
5224	{
5225	/*
5226	* Mapping the FIFO RAM.
5227	*/
5228	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5229	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5230	AssertRC(rc);
5231
5232	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5233	if (RT_SUCCESS(rc))
5234	{
5235	rc = PDMDevHlpPGMHandlerPhysicalRegister(pDevIns, GCPhysAddress,
5236	# ifdef DEBUG_FIFO_ACCESS
5237	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5238	# else
5239	GCPhysAddress + GUEST_PAGE_SIZE - 1,
5240	# endif
5241	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5242	"VMSVGA FIFO");
5243	AssertRC(rc);
5244	}
5245	# endif
5246	if (RT_SUCCESS(rc))
5247	{
5248	pThis->svga.GCPhysFIFO = GCPhysAddress;
5249	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5250	}
5251	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite errors here. */
5252	}
5253	else
5254	{
5255	Assert(pThis->svga.GCPhysFIFO);
5256	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5257	rc = PDMDevHlpPGMHandlerPhysicalDeregister(pDevIns, pThis->svga.GCPhysFIFO);
5258	AssertRC(rc);
5259	# else
5260	rc = VINF_SUCCESS;
5261	# endif
5262	pThis->svga.GCPhysFIFO = 0;
5263	}
5264	return rc;
5265	}
5266
5267	# ifdef VBOX_WITH_VMSVGA3D
5268
5269	/**
5270	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5271	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5272	*
5273	* @param pDevIns The device instance.
5274	* @param pThis The The shared VGA/VMSVGA instance data.
5275	* @param pThisCC The VGA/VMSVGA state for ring-3.
5276	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5277	* UINT32_MAX is used, all surfaces are processed.
5278	*/
5279	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5280	{
5281	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5282	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5283	}
5284
5285
5286	/**
5287	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5288	*/
5289	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5290	{
5291	/* There might be a specific surface ID at the start of the
5292	arguments, if not show all surfaces. */
5293	uint32_t sid = UINT32_MAX;
5294	if (pszArgs)
5295	pszArgs = RTStrStripL(pszArgs);
5296	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5297	sid = RTStrToUInt32(pszArgs);
5298
5299	/* Verbose or terse display, we default to verbose. */
5300	bool fVerbose = true;
5301	if (RTStrIStr(pszArgs, "terse"))
5302	fVerbose = false;
5303
5304	/* The size of the ascii art (x direction, y is 3/4 of x). */
5305	uint32_t cxAscii = 80;
5306	if (RTStrIStr(pszArgs, "gigantic"))
5307	cxAscii = 300;
5308	else if (RTStrIStr(pszArgs, "huge"))
5309	cxAscii = 180;
5310	else if (RTStrIStr(pszArgs, "big"))
5311	cxAscii = 132;
5312	else if (RTStrIStr(pszArgs, "normal"))
5313	cxAscii = 80;
5314	else if (RTStrIStr(pszArgs, "medium"))
5315	cxAscii = 64;
5316	else if (RTStrIStr(pszArgs, "small"))
5317	cxAscii = 48;
5318	else if (RTStrIStr(pszArgs, "tiny"))
5319	cxAscii = 24;
5320
5321	/* Y invert the image when producing the ASCII art. */
5322	bool fInvY = false;
5323	if (RTStrIStr(pszArgs, "invy"))
5324	fInvY = true;
5325
5326	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5327	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5328	}
5329
5330
5331	/**
5332	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5333	*/
5334	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5335	{
5336	/* pszArg = "sid[>dir]"
5337	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5338	*/
5339	char *pszBitmapPath = NULL;
5340	uint32_t sid = UINT32_MAX;
5341	if (pszArgs)
5342	pszArgs = RTStrStripL(pszArgs);
5343	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5344	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5345	if ( pszBitmapPath
5346	&& *pszBitmapPath == '>')
5347	++pszBitmapPath;
5348
5349	const bool fVerbose = true;
5350	const uint32_t cxAscii = 0; /* No ASCII */
5351	const bool fInvY = false; /* Do not invert. */
5352	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5353	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5354	}
5355
5356	/**
5357	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5358	*/
5359	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5360	{
5361	/* There might be a specific surface ID at the start of the
5362	arguments, if not show all contexts. */
5363	uint32_t sid = UINT32_MAX;
5364	if (pszArgs)
5365	pszArgs = RTStrStripL(pszArgs);
5366	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5367	sid = RTStrToUInt32(pszArgs);
5368
5369	/* Verbose or terse display, we default to verbose. */
5370	bool fVerbose = true;
5371	if (RTStrIStr(pszArgs, "terse"))
5372	fVerbose = false;
5373
5374	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5375	}
5376	# endif /* VBOX_WITH_VMSVGA3D */
5377
5378	/**
5379	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5380	*/
5381	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5382	{
5383	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5384	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5385	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5386	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5387	RT_NOREF(pszArgs);
5388
5389	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5390	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5391	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5392	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5393	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5394	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5395	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5396	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5397	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5398	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5399	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5400	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5401	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5402	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5403	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5404	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5405	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5406	pHlp->pfnPrintf(pHlp, "Device Capabilites: %#x\n", pThis->svga.u32DeviceCaps);
5407	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5408	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5409	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5410	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5411	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5412	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5413	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5414
5415	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5416	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5417	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5418	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5419
5420	pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
5421	pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
5422
5423	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
5424	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
5425
5426	# ifdef VBOX_WITH_VMSVGA3D
5427	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5428	# endif
5429	if (pThisCC->pDrv)
5430	{
5431	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5432	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5433	}
5434
5435	/* Dump screen information. */
5436	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5437	{
5438	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5439	if (pScreen)
5440	{
5441	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5442	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5443	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5444	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5445	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5446	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5447	{
5448	pHlp->pfnPrintf(pHlp, " (");
5449	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5450	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5451	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5452	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5453	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5454	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5455	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5456	pHlp->pfnPrintf(pHlp, " BLANKING");
5457	pHlp->pfnPrintf(pHlp, " )");
5458	}
5459	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5460	}
5461	}
5462
5463	}
5464
5465	static int vmsvgaR3LoadBufCtx(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM, PVMSVGACMDBUFCTX pBufCtx, SVGACBContext CBCtx)
5466	{
5467	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5468	PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
5469
5470	uint32_t cSubmitted;
5471	int rc = pHlp->pfnSSMGetU32(pSSM, &cSubmitted);
5472	AssertLogRelRCReturn(rc, rc);
5473
5474	for (uint32_t i = 0; i < cSubmitted; ++i)
5475	{
5476	PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pBufCtx);
5477	AssertPtrReturn(pCmdBuf, VERR_NO_MEMORY);
5478
5479	pHlp->pfnSSMGetGCPhys(pSSM, &pCmdBuf->GCPhysCB);
5480
5481	uint32_t u32;
5482	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
5483	AssertRCReturn(rc, rc);
5484	AssertReturn(u32 == sizeof(SVGACBHeader), VERR_INVALID_STATE);
5485	pHlp->pfnSSMGetMem(pSSM, &pCmdBuf->hdr, sizeof(SVGACBHeader));
5486
5487	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
5488	AssertRCReturn(rc, rc);
5489	AssertReturn(u32 == pCmdBuf->hdr.length, VERR_INVALID_STATE);
5490
5491	if (pCmdBuf->hdr.length)
5492	{
5493	pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
5494	AssertPtrReturn(pCmdBuf->pvCommands, VERR_NO_MEMORY);
5495
5496	rc = pHlp->pfnSSMGetMem(pSSM, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
5497	AssertRCReturn(rc, rc);
5498	}
5499
5500	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
5501	{
5502	vmsvgaR3CmdBufSubmitCtx(pDevIns, pThis, pThisCC, &pCmdBuf);
5503	}
5504	else
5505	{
5506	uint32_t offNextCmd = 0;
5507	vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
5508	}
5509
5510	/* Free the buffer if CmdBufSubmit* did not consume it. */
5511	vmsvgaR3CmdBufFree(pCmdBuf);
5512	}
5513	return rc;
5514	}
5515
5516	static int vmsvgaR3LoadCommandBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5517	{
5518	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5519	PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
5520
5521	bool f;
5522	uint32_t u32;
5523
5524	/* Device context command buffers. */
5525	int rc = vmsvgaR3LoadBufCtx(pDevIns, pThis, pThisCC, pSSM, &pSvgaR3State->CmdBufCtxDC, SVGA_CB_CONTEXT_MAX);
5526	AssertLogRelRCReturn(rc, rc);
5527
5528	/* DX contexts command buffers. */
5529	uint32_t cBufCtx;
5530	rc = pHlp->pfnSSMGetU32(pSSM, &cBufCtx);
5531	AssertLogRelRCReturn(rc, rc);
5532	AssertReturn(cBufCtx == RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs), VERR_INVALID_STATE);
5533	for (uint32_t j = 0; j < cBufCtx; ++j)
5534	{
5535	rc = pHlp->pfnSSMGetBool(pSSM, &f);
5536	AssertLogRelRCReturn(rc, rc);
5537	if (f)
5538	{
5539	pSvgaR3State->apCmdBufCtxs[j] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
5540	AssertPtrReturn(pSvgaR3State->apCmdBufCtxs[j], VERR_NO_MEMORY);
5541	vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[j]);
5542
5543	rc = vmsvgaR3LoadBufCtx(pDevIns, pThis, pThisCC, pSSM, pSvgaR3State->apCmdBufCtxs[j], (SVGACBContext)j);
5544	AssertLogRelRCReturn(rc, rc);
5545	}
5546	}
5547
5548	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
5549	pSvgaR3State->fCmdBuf = u32;
5550	return rc;
5551	}
5552
5553	static int vmsvgaR3LoadGbo(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, VMSVGAGBO *pGbo)
5554	{
5555	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5556
5557	int rc;
5558	pHlp->pfnSSMGetU32(pSSM, &pGbo->fGboFlags);
5559	pHlp->pfnSSMGetU32(pSSM, &pGbo->cTotalPages);
5560	pHlp->pfnSSMGetU32(pSSM, &pGbo->cbTotal);
5561	rc = pHlp->pfnSSMGetU32(pSSM, &pGbo->cDescriptors);
5562	AssertRCReturn(rc, rc);
5563
5564	if (pGbo->cDescriptors)
5565	{
5566	pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAllocZ(pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
5567	AssertPtrReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
5568	}
5569
5570	for (uint32_t iDesc = 0; iDesc < pGbo->cDescriptors; ++iDesc)
5571	{
5572	PVMSVGAGBODESCRIPTOR pDesc = &pGbo->paDescriptors[iDesc];
5573	pHlp->pfnSSMGetGCPhys(pSSM, &pDesc->GCPhys);
5574	rc = pHlp->pfnSSMGetU64(pSSM, &pDesc->cPages);
5575	}
5576
5577	if (pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED)
5578	{
5579	pGbo->pvHost = RTMemAlloc(pGbo->cbTotal);
5580	AssertPtrReturn(pGbo->pvHost, VERR_NO_MEMORY);
5581	rc = pHlp->pfnSSMGetMem(pSSM, pGbo->pvHost, pGbo->cbTotal);
5582	}
5583
5584	return rc;
5585	}
5586
5587	/**
5588	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5589	*/
5590	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5591	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5592	{
5593	RT_NOREF(uPass);
5594
5595	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5596	int rc;
5597
5598	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5599	{
5600	uint32_t cScreens = 0;
5601	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5602	AssertRCReturn(rc, rc);
5603	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5604	("cScreens=%#x\n", cScreens),
5605	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5606
5607	for (uint32_t i = 0; i < cScreens; ++i)
5608	{
5609	VMSVGASCREENOBJECT screen;
5610	RT_ZERO(screen);
5611
5612	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5613	AssertLogRelRCReturn(rc, rc);
5614
5615	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5616	{
5617	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5618	*pScreen = screen;
5619	pScreen->fModified = true;
5620
5621	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_DX)
5622	{
5623	uint32_t u32;
5624	pHlp->pfnSSMGetU32(pSSM, &u32); /* Size of screen bitmap. */
5625	AssertLogRelRCReturn(rc, rc);
5626	if (u32)
5627	{
5628	pScreen->pvScreenBitmap = RTMemAlloc(u32);
5629	AssertPtrReturn(pScreen->pvScreenBitmap, VERR_NO_MEMORY);
5630
5631	pHlp->pfnSSMGetMem(pSSM, pScreen->pvScreenBitmap, u32);
5632	}
5633	}
5634	}
5635	else
5636	{
5637	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5638	}
5639	}
5640	}
5641	else
5642	{
5643	/* Try to setup at least the first screen. */
5644	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5645	pScreen->fDefined = true;
5646	pScreen->fModified = true;
5647	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5648	pScreen->idScreen = 0;
5649	pScreen->xOrigin = 0;
5650	pScreen->yOrigin = 0;
5651	pScreen->offVRAM = pThis->svga.uScreenOffset;
5652	pScreen->cbPitch = pThis->svga.cbScanline;
5653	pScreen->cWidth = pThis->svga.uWidth;
5654	pScreen->cHeight = pThis->svga.uHeight;
5655	pScreen->cBpp = pThis->svga.uBpp;
5656	}
5657
5658	return VINF_SUCCESS;
5659	}
5660
5661	/**
5662	* @copydoc FNSSMDEVLOADEXEC
5663	*/
5664	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5665	{
5666	RT_NOREF(uPass);
5667	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5668	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5669	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5670	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5671	int rc;
5672
5673	/* Load our part of the VGAState */
5674	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5675	AssertRCReturn(rc, rc);
5676
5677	/* Load the VGA framebuffer. */
5678	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5679	uint32_t cbVgaFramebuffer = _32K;
5680	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5681	{
5682	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5683	AssertRCReturn(rc, rc);
5684	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5685	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5686	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5687	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5688	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5689	}
5690	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5691	AssertRCReturn(rc, rc);
5692	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5693	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5694	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5695	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5696
5697	/* Load the VMSVGA state. */
5698	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5699	AssertRCReturn(rc, rc);
5700
5701	/* Load the active cursor bitmaps. */
5702	if (pSVGAState->Cursor.fActive)
5703	{
5704	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5705	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5706
5707	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5708	AssertRCReturn(rc, rc);
5709	}
5710
5711	/* Load the GMR state. */
5712	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5713	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5714	{
5715	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5716	AssertRCReturn(rc, rc);
5717	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5718	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5719	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5720	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5721	}
5722
5723	if (pThis->svga.cGMR != cGMR)
5724	{
5725	/* Reallocate GMR array. */
5726	Assert(pSVGAState->paGMR != NULL);
5727	RTMemFree(pSVGAState->paGMR);
5728	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5729	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5730	pThis->svga.cGMR = cGMR;
5731	}
5732
5733	for (uint32_t i = 0; i < cGMR; ++i)
5734	{
5735	PGMR pGMR = &pSVGAState->paGMR[i];
5736
5737	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5738	AssertRCReturn(rc, rc);
5739
5740	if (pGMR->numDescriptors)
5741	{
5742	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5743	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5744	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5745
5746	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5747	{
5748	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5749	AssertRCReturn(rc, rc);
5750	}
5751	}
5752	}
5753
5754	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_DX)
5755	{
5756	bool f;
5757	uint32_t u32;
5758
5759	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_DX_CMDBUF)
5760	{
5761	/* Command buffers are saved independently from VGPU10. */
5762	rc = pHlp->pfnSSMGetBool(pSSM, &f);
5763	AssertLogRelRCReturn(rc, rc);
5764	if (f)
5765	{
5766	rc = vmsvgaR3LoadCommandBuffers(pDevIns, pThis, pThisCC, pSSM);
5767	AssertLogRelRCReturn(rc, rc);
5768	}
5769	}
5770
5771	rc = pHlp->pfnSSMGetBool(pSSM, &f);
5772	AssertLogRelRCReturn(rc, rc);
5773	pThis->fVMSVGA10 = f;
5774
5775	if (pThis->fVMSVGA10)
5776	{
5777	if (uVersion < VGA_SAVEDSTATE_VERSION_VMSVGA_DX_CMDBUF)
5778	{
5779	rc = vmsvgaR3LoadCommandBuffers(pDevIns, pThis, pThisCC, pSSM);
5780	AssertLogRelRCReturn(rc, rc);
5781	}
5782
5783	/*
5784	* OTables GBOs.
5785	*/
5786	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
5787	AssertLogRelRCReturn(rc, rc);
5788	AssertReturn(u32 == SVGA_OTABLE_MAX, VERR_INVALID_STATE);
5789	for (int i = 0; i < SVGA_OTABLE_MAX; ++i)
5790	{
5791	VMSVGAGBO *pGbo = &pSVGAState->aGboOTables[i];
5792	rc = vmsvgaR3LoadGbo(pDevIns, pSSM, pGbo);
5793	AssertRCReturn(rc, rc);
5794	}
5795
5796	/*
5797	* MOBs.
5798	*/
5799	for (;;)
5800	{
5801	rc = pHlp->pfnSSMGetU32(pSSM, &u32); /* MOB id. */
5802	AssertRCReturn(rc, rc);
5803	if (u32 == SVGA_ID_INVALID)
5804	break;
5805
5806	PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
5807	AssertPtrReturn(pMob, VERR_NO_MEMORY);
5808
5809	rc = vmsvgaR3LoadGbo(pDevIns, pSSM, &pMob->Gbo);
5810	AssertRCReturn(rc, rc);
5811
5812	pMob->Core.Key = u32;
5813	if (RTAvlU32Insert(&pSVGAState->MOBTree, &pMob->Core))
5814	RTListPrepend(&pSVGAState->MOBLRUList, &pMob->nodeLRU);
5815	else
5816	AssertFailedReturn(VERR_NO_MEMORY);
5817	}
5818
5819	# ifdef VMSVGA3D_DX
5820	if (pThis->svga.f3DEnabled)
5821	{
5822	pHlp->pfnSSMGetU32(pSSM, &pSVGAState->idDXContextCurrent);
5823	}
5824	# endif
5825	}
5826	}
5827
5828	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5829	vmsvgaR3PowerOnDevice(pDevIns, pThis, pThisCC, /fLoadState=/ true);
5830	# endif
5831
5832	VMSVGA_STATE_LOAD LoadState;
5833	LoadState.pSSM = pSSM;
5834	LoadState.uVersion = uVersion;
5835	LoadState.uPass = uPass;
5836	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5837	AssertLogRelRCReturn(rc, rc);
5838
5839	return VINF_SUCCESS;
5840	}
5841
5842	/**
5843	* Reinit the video mode after the state has been loaded.
5844	*/
5845	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5846	{
5847	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5848	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5849	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5850
5851	/* VMSVGA is working via VBVA interface, therefore it needs to be
5852	* enabled on saved state restore. See @bugref{10071#c7}. */
5853	if (pThis->svga.fEnabled)
5854	{
5855	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
5856	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
5857	}
5858
5859	/* Set the active cursor. */
5860	if (pSVGAState->Cursor.fActive)
5861	{
5862	/* We don't store the alpha flag, but we can take a guess that if
5863	* the old register interface was used, the cursor was B&W.
5864	*/
5865	bool fAlpha = pThis->svga.uCursorOn ? false : true;
5866
5867	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
5868	true /fVisible/,
5869	fAlpha,
5870	pSVGAState->Cursor.xHotspot,
5871	pSVGAState->Cursor.yHotspot,
5872	pSVGAState->Cursor.width,
5873	pSVGAState->Cursor.height,
5874	pSVGAState->Cursor.pData);
5875	AssertRC(rc);
5876
5877	if (pThis->svga.uCursorOn)
5878	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
5879	}
5880
5881	/* If the VRAM handler should not be registered, we have to explicitly
5882	* unregister it here!
5883	*/
5884	if (!pThis->svga.fVRAMTracking)
5885	{
5886	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5887	}
5888
5889	/* Let the FIFO thread deal with changing the mode. */
5890	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5891
5892	return VINF_SUCCESS;
5893	}
5894
5895	static int vmsvgaR3SaveBufCtx(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PVMSVGACMDBUFCTX pBufCtx)
5896	{
5897	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5898
5899	int rc = pHlp->pfnSSMPutU32(pSSM, pBufCtx->cSubmitted);
5900	AssertLogRelRCReturn(rc, rc);
5901	if (pBufCtx->cSubmitted)
5902	{
5903	PVMSVGACMDBUF pIter;
5904	RTListForEach(&pBufCtx->listSubmitted, pIter, VMSVGACMDBUF, nodeBuffer)
5905	{
5906	pHlp->pfnSSMPutGCPhys(pSSM, pIter->GCPhysCB);
5907	pHlp->pfnSSMPutU32(pSSM, sizeof(SVGACBHeader));
5908	pHlp->pfnSSMPutMem(pSSM, &pIter->hdr, sizeof(SVGACBHeader));
5909	pHlp->pfnSSMPutU32(pSSM, pIter->hdr.length);
5910	if (pIter->hdr.length)
5911	rc = pHlp->pfnSSMPutMem(pSSM, pIter->pvCommands, pIter->hdr.length);
5912	AssertLogRelRCReturn(rc, rc);
5913	}
5914	}
5915	return rc;
5916	}
5917
5918	static int vmsvgaR3SaveGbo(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, VMSVGAGBO *pGbo)
5919	{
5920	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5921
5922	int rc;
5923	pHlp->pfnSSMPutU32(pSSM, pGbo->fGboFlags);
5924	pHlp->pfnSSMPutU32(pSSM, pGbo->cTotalPages);
5925	pHlp->pfnSSMPutU32(pSSM, pGbo->cbTotal);
5926	rc = pHlp->pfnSSMPutU32(pSSM, pGbo->cDescriptors);
5927	for (uint32_t iDesc = 0; iDesc < pGbo->cDescriptors; ++iDesc)
5928	{
5929	PVMSVGAGBODESCRIPTOR pDesc = &pGbo->paDescriptors[iDesc];
5930	pHlp->pfnSSMPutGCPhys(pSSM, pDesc->GCPhys);
5931	rc = pHlp->pfnSSMPutU64(pSSM, pDesc->cPages);
5932	}
5933	if (pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED)
5934	rc = pHlp->pfnSSMPutMem(pSSM, pGbo->pvHost, pGbo->cbTotal);
5935	return rc;
5936	}
5937
5938	/**
5939	* Portion of SVGA state which must be saved in the FIFO thread.
5940	*/
5941	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5942	{
5943	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5944	int rc;
5945
5946	/* Save the screen objects. */
5947	/* Count defined screen object. */
5948	uint32_t cScreens = 0;
5949	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5950	{
5951	if (pSVGAState->aScreens[i].fDefined)
5952	++cScreens;
5953	}
5954
5955	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5956	AssertLogRelRCReturn(rc, rc);
5957
5958	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5959	{
5960	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5961	if (!pScreen->fDefined)
5962	continue;
5963
5964	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5965	AssertLogRelRCReturn(rc, rc);
5966
5967	/*
5968	* VGA_SAVEDSTATE_VERSION_VMSVGA_DX
5969	*/
5970	if (pScreen->pvScreenBitmap)
5971	{
5972	uint32_t const cbScreenBitmap = pScreen->cHeight * pScreen->cbPitch;
5973	pHlp->pfnSSMPutU32(pSSM, cbScreenBitmap);
5974	pHlp->pfnSSMPutMem(pSSM, pScreen->pvScreenBitmap, cbScreenBitmap);
5975	}
5976	else
5977	pHlp->pfnSSMPutU32(pSSM, 0);
5978	}
5979	return VINF_SUCCESS;
5980	}
5981
5982	/**
5983	* @copydoc FNSSMDEVSAVEEXEC
5984	*/
5985	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5986	{
5987	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5988	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5989	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5990	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5991	int rc;
5992
5993	/* Save our part of the VGAState */
5994	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5995	AssertLogRelRCReturn(rc, rc);
5996
5997	/* Save the framebuffer backup. */
5998	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5999	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6000	AssertLogRelRCReturn(rc, rc);
6001
6002	/* Save the VMSVGA state. */
6003	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
6004	AssertLogRelRCReturn(rc, rc);
6005
6006	/* Save the active cursor bitmaps. */
6007	if (pSVGAState->Cursor.fActive)
6008	{
6009	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6010	AssertLogRelRCReturn(rc, rc);
6011	}
6012
6013	/* Save the GMR state */
6014	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
6015	AssertLogRelRCReturn(rc, rc);
6016	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
6017	{
6018	PGMR pGMR = &pSVGAState->paGMR[i];
6019
6020	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
6021	AssertLogRelRCReturn(rc, rc);
6022
6023	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
6024	{
6025	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
6026	AssertLogRelRCReturn(rc, rc);
6027	}
6028	}
6029
6030	/*
6031	* VGA_SAVEDSTATE_VERSION_VMSVGA_DX+
6032	*/
6033	if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
6034	{
6035	rc = pHlp->pfnSSMPutBool(pSSM, true);
6036	AssertLogRelRCReturn(rc, rc);
6037
6038	/* Device context command buffers. */
6039	rc = vmsvgaR3SaveBufCtx(pDevIns, pSSM, &pSVGAState->CmdBufCtxDC);
6040	AssertRCReturn(rc, rc);
6041
6042	/* DX contexts command buffers. */
6043	rc = pHlp->pfnSSMPutU32(pSSM, RT_ELEMENTS(pSVGAState->apCmdBufCtxs));
6044	AssertLogRelRCReturn(rc, rc);
6045	for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->apCmdBufCtxs); ++i)
6046	{
6047	if (pSVGAState->apCmdBufCtxs[i])
6048	{
6049	pHlp->pfnSSMPutBool(pSSM, true);
6050	rc = vmsvgaR3SaveBufCtx(pDevIns, pSSM, pSVGAState->apCmdBufCtxs[i]);
6051	AssertRCReturn(rc, rc);
6052	}
6053	else
6054	pHlp->pfnSSMPutBool(pSSM, false);
6055	}
6056
6057	rc = pHlp->pfnSSMPutU32(pSSM, pSVGAState->fCmdBuf);
6058	AssertRCReturn(rc, rc);
6059	}
6060	else
6061	{
6062	rc = pHlp->pfnSSMPutBool(pSSM, false);
6063	AssertLogRelRCReturn(rc, rc);
6064	}
6065
6066	rc = pHlp->pfnSSMPutBool(pSSM, pThis->fVMSVGA10);
6067	AssertLogRelRCReturn(rc, rc);
6068
6069	if (pThis->fVMSVGA10)
6070	{
6071	/*
6072	* OTables GBOs.
6073	*/
6074	pHlp->pfnSSMPutU32(pSSM, SVGA_OTABLE_MAX);
6075	for (int i = 0; i < SVGA_OTABLE_MAX; ++i)
6076	{
6077	VMSVGAGBO *pGbo = &pSVGAState->aGboOTables[i];
6078	rc = vmsvgaR3SaveGbo(pDevIns, pSSM, pGbo);
6079	AssertRCReturn(rc, rc);
6080	}
6081
6082	/*
6083	* MOBs.
6084	*/
6085	PVMSVGAMOB pIter;
6086	RTListForEach(&pSVGAState->MOBLRUList, pIter, VMSVGAMOB, nodeLRU)
6087	{
6088	pHlp->pfnSSMPutU32(pSSM, pIter->Core.Key); /* MOB id. */
6089	rc = vmsvgaR3SaveGbo(pDevIns, pSSM, &pIter->Gbo);
6090	AssertRCReturn(rc, rc);
6091	}
6092
6093	pHlp->pfnSSMPutU32(pSSM, SVGA_ID_INVALID); /* End marker. */
6094
6095	# ifdef VMSVGA3D_DX
6096	if (pThis->svga.f3DEnabled)
6097	{
6098	pHlp->pfnSSMPutU32(pSSM, pSVGAState->idDXContextCurrent);
6099	}
6100	# endif
6101	}
6102
6103	/*
6104	* Must save some state (3D in particular) in the FIFO thread.
6105	*/
6106	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
6107	AssertLogRelRCReturn(rc, rc);
6108
6109	return VINF_SUCCESS;
6110	}
6111
6112	/**
6113	* Destructor for PVMSVGAR3STATE structure. The structure is not deallocated.
6114	*
6115	* @param pThis The shared VGA/VMSVGA instance data.
6116	* @param pThisCC The device context.
6117	*/
6118	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVGASTATECC pThisCC)
6119	{
6120	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6121
6122	# ifndef VMSVGA_USE_EMT_HALT_CODE
6123	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
6124	{
6125	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
6126	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
6127	}
6128	# endif
6129
6130	if (pSVGAState->Cursor.fActive)
6131	{
6132	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6133	pSVGAState->Cursor.pData = NULL;
6134	pSVGAState->Cursor.fActive = false;
6135	}
6136
6137	if (pSVGAState->paGMR)
6138	{
6139	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
6140	if (pSVGAState->paGMR[i].paDesc)
6141	RTMemFree(pSVGAState->paGMR[i].paDesc);
6142
6143	RTMemFree(pSVGAState->paGMR);
6144	pSVGAState->paGMR = NULL;
6145	}
6146
6147	if (RTCritSectIsInitialized(&pSVGAState->CritSectCmdBuf))
6148	{
6149	RTCritSectEnter(&pSVGAState->CritSectCmdBuf);
6150	for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->apCmdBufCtxs); ++i)
6151	{
6152	vmsvgaR3CmdBufCtxTerm(pSVGAState->apCmdBufCtxs[i]);
6153	pSVGAState->apCmdBufCtxs[i] = NULL;
6154	}
6155	vmsvgaR3CmdBufCtxTerm(&pSVGAState->CmdBufCtxDC);
6156	RTCritSectLeave(&pSVGAState->CritSectCmdBuf);
6157	RTCritSectDelete(&pSVGAState->CritSectCmdBuf);
6158	}
6159	}
6160
6161	/**
6162	* Constructor for PVMSVGAR3STATE structure.
6163	*
6164	* @returns VBox status code.
6165	* @param pDevIns The PDM device instance.
6166	* @param pThis The shared VGA/VMSVGA instance data.
6167	* @param pSVGAState Pointer to the structure. It is already allocated.
6168	*/
6169	static int vmsvgaR3StateInit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
6170	{
6171	int rc = VINF_SUCCESS;
6172
6173	pSVGAState->pDevIns = pDevIns;
6174
6175	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
6176	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
6177
6178	# ifndef VMSVGA_USE_EMT_HALT_CODE
6179	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
6180	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
6181	AssertRCReturn(rc, rc);
6182	# endif
6183
6184	rc = RTCritSectInit(&pSVGAState->CritSectCmdBuf);
6185	AssertRCReturn(rc, rc);
6186
6187	vmsvgaR3CmdBufCtxInit(&pSVGAState->CmdBufCtxDC);
6188
6189	RTListInit(&pSVGAState->MOBLRUList);
6190	# ifdef VBOX_WITH_VMSVGA3D
6191	# ifdef VMSVGA3D_DX
6192	pSVGAState->idDXContextCurrent = SVGA3D_INVALID_ID;
6193	# endif
6194	# endif
6195	return rc;
6196	}
6197
6198	# ifdef VBOX_WITH_VMSVGA3D
6199	static void vmsvga3dR3Free3dInterfaces(PVGASTATECC pThisCC)
6200	{
6201	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6202
6203	RTMemFree(pSVGAState->pFuncsMap);
6204	pSVGAState->pFuncsMap = NULL;
6205	RTMemFree(pSVGAState->pFuncsGBO);
6206	pSVGAState->pFuncsGBO = NULL;
6207	RTMemFree(pSVGAState->pFuncsDX);
6208	pSVGAState->pFuncsDX = NULL;
6209	RTMemFree(pSVGAState->pFuncsVGPU9);
6210	pSVGAState->pFuncsVGPU9 = NULL;
6211	RTMemFree(pSVGAState->pFuncs3D);
6212	pSVGAState->pFuncs3D = NULL;
6213	}
6214
6215	/* This structure is used only by vmsvgaR3Init3dInterfaces */
6216	typedef struct VMSVGA3DINTERFACE
6217	{
6218	char const *pcszName;
6219	uint32_t cbFuncs;
6220	void **ppvFuncs;
6221	} VMSVGA3DINTERFACE;
6222
6223	extern VMSVGA3DBACKENDDESC const g_BackendLegacy;
6224	#if defined(VMSVGA3D_DX_BACKEND)
6225	extern VMSVGA3DBACKENDDESC const g_BackendDX;
6226	#endif
6227
6228	/**
6229	* Initializes the optional host 3D backend interfaces.
6230	*
6231	* @returns VBox status code.
6232	* @param pThisCC The VGA/VMSVGA state for ring-3.
6233	*/
6234	static int vmsvgaR3Init3dInterfaces(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
6235	{
6236	#ifndef VMSVGA3D_DX
6237	RT_NOREF(pThis);
6238	#endif
6239
6240	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6241
6242	#define ENTRY_3D_INTERFACE(a_Name, a_Field) { VMSVGA3D_BACKEND_INTERFACE_NAME_##a_Name, sizeof(VMSVGA3DBACKENDFUNCS##a_Name), (void **)&pSVGAState->a_Field }
6243	VMSVGA3DINTERFACE a3dInterface[] =
6244	{
6245	ENTRY_3D_INTERFACE(3D, pFuncs3D),
6246	ENTRY_3D_INTERFACE(VGPU9, pFuncsVGPU9),
6247	ENTRY_3D_INTERFACE(DX, pFuncsDX),
6248	ENTRY_3D_INTERFACE(MAP, pFuncsMap),
6249	ENTRY_3D_INTERFACE(GBO, pFuncsGBO),
6250	};
6251	#undef ENTRY_3D_INTERFACE
6252
6253	VMSVGA3DBACKENDDESC const *pBackend = NULL;
6254	#if defined(VMSVGA3D_DX_BACKEND)
6255	if (pThis->fVMSVGA10)
6256	pBackend = &g_BackendDX;
6257	else
6258	#endif
6259	pBackend = &g_BackendLegacy;
6260
6261	int rc = VINF_SUCCESS;
6262	for (uint32_t i = 0; i < RT_ELEMENTS(a3dInterface); ++i)
6263	{
6264	VMSVGA3DINTERFACE *p = &a3dInterface[i];
6265
6266	int rc2 = pBackend->pfnQueryInterface(pThisCC, p->pcszName, NULL, p->cbFuncs);
6267	if (RT_SUCCESS(rc2))
6268	{
6269	*p->ppvFuncs = RTMemAllocZ(p->cbFuncs);
6270	AssertBreakStmt(*p->ppvFuncs, rc = VERR_NO_MEMORY);
6271
6272	pBackend->pfnQueryInterface(pThisCC, p->pcszName, *p->ppvFuncs, p->cbFuncs);
6273	}
6274	}
6275
6276	if (RT_SUCCESS(rc))
6277	{
6278	/* 3D interface is required. */
6279	if (pSVGAState->pFuncs3D)
6280	{
6281	rc = pSVGAState->pFuncs3D->pfnInit(pDevIns, pThis, pThisCC);
6282	if (RT_SUCCESS(rc))
6283	return VINF_SUCCESS;
6284	}
6285	else
6286	rc = VERR_NOT_SUPPORTED;
6287	}
6288
6289	vmsvga3dR3Free3dInterfaces(pThisCC);
6290	return rc;
6291	}
6292	# endif /* VBOX_WITH_VMSVGA3D */
6293
6294	/**
6295	* Compute the host capabilities: device and FIFO.
6296	* Depends on 3D backend initialization.
6297	*
6298	* @returns VBox status code.
6299	* @param pThis The shared VGA/VMSVGA instance data.
6300	* @param pThisCC The VGA/VMSVGA state for ring-3.
6301	* @param pu32DeviceCaps Device capabilities (SVGA_CAP_*).
6302	* @param pu32FIFOCaps FIFO capabilities (SVGA_FIFO_CAPS_*).
6303	*/
6304	static void vmsvgaR3GetCaps(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t pu32DeviceCaps, uint32_t pu32FIFOCaps)
6305	{
6306	#ifndef VBOX_WITH_VMSVGA3D
6307	RT_NOREF(pThisCC);
6308	#endif
6309
6310	/* Device caps. */
6311	*pu32DeviceCaps = SVGA_CAP_GMR
6312	\| SVGA_CAP_GMR2
6313	\| SVGA_CAP_CURSOR
6314	\| SVGA_CAP_CURSOR_BYPASS
6315	\| SVGA_CAP_CURSOR_BYPASS_2
6316	\| SVGA_CAP_EXTENDED_FIFO
6317	\| SVGA_CAP_IRQMASK
6318	\| SVGA_CAP_PITCHLOCK
6319	\| SVGA_CAP_RECT_COPY
6320	\| SVGA_CAP_TRACES
6321	\| SVGA_CAP_SCREEN_OBJECT_2
6322	\| SVGA_CAP_ALPHA_CURSOR;
6323
6324	pu32DeviceCaps \|= SVGA_CAP_COMMAND_BUFFERS / Enable register based command buffer submission. */
6325	// \| SVGA_CAP_CMD_BUFFERS_2 /* Support for SVGA_REG_CMD_PREPEND_LOW/HIGH */
6326	;
6327
6328	/* VGPU10 capabilities. */
6329	if (pThis->fVMSVGA10)
6330	{
6331	# ifdef VBOX_WITH_VMSVGA3D
6332	if (pThisCC->svga.pSvgaR3State->pFuncsGBO)
6333	pu32DeviceCaps \|= SVGA_CAP_GBOBJECTS; / Enable guest-backed objects and surfaces. */
6334	if (pThisCC->svga.pSvgaR3State->pFuncsDX)
6335	pu32DeviceCaps \|= SVGA_CAP_DX; / Enable support for DX commands, and command buffers in a mob. */
6336	# endif
6337	}
6338
6339	# ifdef VBOX_WITH_VMSVGA3D
6340	if (pThisCC->svga.pSvgaR3State->pFuncs3D)
6341	*pu32DeviceCaps \|= SVGA_CAP_3D;
6342	# endif
6343
6344	/* FIFO capabilities. */
6345	*pu32FIFOCaps = SVGA_FIFO_CAP_FENCE
6346	\| SVGA_FIFO_CAP_PITCHLOCK
6347	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
6348	\| SVGA_FIFO_CAP_RESERVE
6349	\| SVGA_FIFO_CAP_GMR2
6350	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
6351	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
6352	}
6353
6354	/** Initialize the FIFO on power on and reset.
6355	*
6356	* @param pThis The shared VGA/VMSVGA instance data.
6357	* @param pThisCC The VGA/VMSVGA state for ring-3.
6358	*/
6359	static void vmsvgaR3InitFIFO(PVGASTATE pThis, PVGASTATECC pThisCC)
6360	{
6361	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
6362
6363	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
6364	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
6365	}
6366
6367	# ifdef VBOX_WITH_VMSVGA3D
6368	/**
6369	* Initializes the host 3D capabilities and writes them to FIFO memory.
6370	*
6371	* @returns VBox status code.
6372	* @param pThis The shared VGA/VMSVGA instance data.
6373	* @param pThisCC The VGA/VMSVGA state for ring-3.
6374	*/
6375	static void vmsvgaR3InitFifo3DCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
6376	{
6377	/* Query the capabilities and store them in the pThis->svga.au32DevCaps array. */
6378	bool const fSavedBuffering = RTLogRelSetBuffering(true);
6379
6380	for (unsigned i = 0; i < RT_ELEMENTS(pThis->svga.au32DevCaps); ++i)
6381	{
6382	uint32_t val = 0;
6383	int rc = vmsvga3dQueryCaps(pThisCC, (SVGA3dDevCapIndex)i, &val);
6384	if (RT_SUCCESS(rc))
6385	pThis->svga.au32DevCaps[i] = val;
6386	else
6387	pThis->svga.au32DevCaps[i] = 0;
6388
6389	/* LogRel the capability value. */
6390	if (i < SVGA3D_DEVCAP_MAX)
6391	{
6392	char const *pszDevCapName = &vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)i)[sizeof("SVGA3D_DEVCAP")];
6393	if (RT_SUCCESS(rc))
6394	{
6395	if ( i == SVGA3D_DEVCAP_MAX_POINT_SIZE
6396	\|\| i == SVGA3D_DEVCAP_MAX_LINE_WIDTH
6397	\|\| i == SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH)
6398	{
6399	float const fval = (float )&val;
6400	LogRel(("VMSVGA3d: cap[%u]=" FLOAT_FMT_STR " {%s}\n", i, FLOAT_FMT_ARGS(fval), pszDevCapName));
6401	}
6402	else
6403	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, pszDevCapName));
6404	}
6405	else
6406	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc {%s}\n", i, rc, pszDevCapName));
6407	}
6408	else
6409	LogRel(("VMSVGA3d: new cap[%u]=%#010x rc=%Rrc\n", i, val, rc));
6410	}
6411
6412	RTLogRelSetBuffering(fSavedBuffering);
6413
6414	/* 3d hardware version; latest and greatest */
6415	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6416	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6417
6418	/* Fill out 3d capabilities up to SVGA3D_DEVCAP_SURFACEFMT_ATI2 in the FIFO memory.
6419	* SVGA3D_DEVCAP_SURFACEFMT_ATI2 is the last capabiltiy for pre-SVGA_CAP_GBOBJECTS hardware.
6420	* If the VMSVGA device supports SVGA_CAP_GBOBJECTS capability, then the guest has to use SVGA_REG_DEV_CAP
6421	* register to query the devcaps. Older guests will still try to read the devcaps from FIFO.
6422	*/
6423	SVGA3dCapsRecord *pCaps;
6424	SVGA3dCapPair *pData;
6425
6426	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
6427	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6428	pData = (SVGA3dCapPair *)&pCaps->data;
6429
6430	AssertCompile(SVGA3D_DEVCAP_DEAD1 == SVGA3D_DEVCAP_SURFACEFMT_ATI2 + 1);
6431	for (unsigned i = 0; i < SVGA3D_DEVCAP_DEAD1; ++i)
6432	{
6433	pData[i][0] = i;
6434	pData[i][1] = pThis->svga.au32DevCaps[i];
6435	}
6436	pCaps->header.length = (sizeof(pCaps->header) + SVGA3D_DEVCAP_DEAD1 * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6437	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6438
6439	/* Mark end of record array (a zero word). */
6440	pCaps->header.length = 0;
6441	}
6442
6443	# endif
6444
6445	/**
6446	* Resets the SVGA hardware state
6447	*
6448	* @returns VBox status code.
6449	* @param pDevIns The device instance.
6450	*/
6451	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6452	{
6453	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6454	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6455	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6456
6457	/* Reset before init? */
6458	if (!pSVGAState)
6459	return VINF_SUCCESS;
6460
6461	Log(("vmsvgaR3Reset\n"));
6462
6463	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6464	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6465	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6466
6467	/* Reset other stuff. */
6468	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6469	RT_ZERO(pThis->svga.au32ScratchRegion);
6470
6471	ASMAtomicWriteBool(&pThis->svga.fBadGuest, false);
6472
6473	vmsvgaR3StateTerm(pThis, pThisCC);
6474	vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
6475
6476	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6477
6478	vmsvgaR3InitFIFO(pThis, pThisCC);
6479
6480	/* Initialize FIFO and register capabilities. */
6481	vmsvgaR3GetCaps(pThis, pThisCC, &pThis->svga.u32DeviceCaps, &pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES]);
6482
6483	# ifdef VBOX_WITH_VMSVGA3D
6484	if (pThis->svga.f3DEnabled)
6485	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
6486	# endif
6487
6488	/* VRAM tracking is enabled by default during bootup. */
6489	pThis->svga.fVRAMTracking = true;
6490	pThis->svga.fEnabled = false;
6491
6492	/* Invalidate current settings. */
6493	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6494	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6495	pThis->svga.uBpp = pThis->svga.uHostBpp;
6496	pThis->svga.cbScanline = 0;
6497	pThis->svga.u32PitchLock = 0;
6498
6499	return rc;
6500	}
6501
6502	/**
6503	* Cleans up the SVGA hardware state
6504	*
6505	* @returns VBox status code.
6506	* @param pDevIns The device instance.
6507	*/
6508	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6509	{
6510	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6511	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6512
6513	/*
6514	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6515	*/
6516	if (pThisCC->svga.pFIFOIOThread)
6517	{
6518	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6519	NULL /pvParam/, 30000 /ms/);
6520	AssertLogRelRC(rc);
6521
6522	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6523	AssertLogRelRC(rc);
6524	pThisCC->svga.pFIFOIOThread = NULL;
6525	}
6526
6527	/*
6528	* Destroy the special SVGA state.
6529	*/
6530	if (pThisCC->svga.pSvgaR3State)
6531	{
6532	vmsvgaR3StateTerm(pThis, pThisCC);
6533
6534	# ifdef VBOX_WITH_VMSVGA3D
6535	vmsvga3dR3Free3dInterfaces(pThisCC);
6536	# endif
6537
6538	RTMemFree(pThisCC->svga.pSvgaR3State);
6539	pThisCC->svga.pSvgaR3State = NULL;
6540	}
6541
6542	/*
6543	* Free our resources residing in the VGA state.
6544	*/
6545	if (pThisCC->svga.pbVgaFrameBufferR3)
6546	{
6547	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6548	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6549	}
6550	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6551	{
6552	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6553	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6554	}
6555	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6556	{
6557	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6558	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6559	}
6560
6561	return VINF_SUCCESS;
6562	}
6563
6564	static DECLCALLBACK(size_t) vmsvga3dFloatFormat(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
6565	const char pszType, void const pvValue,
6566	int cchWidth, int cchPrecision, unsigned fFlags, void *pvUser)
6567	{
6568	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
6569	double const v = (double )&pvValue;
6570	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, FLOAT_FMT_STR, FLOAT_FMT_ARGS(v));
6571	}
6572
6573	/**
6574	* Initialize the SVGA hardware state
6575	*
6576	* @returns VBox status code.
6577	* @param pDevIns The device instance.
6578	*/
6579	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6580	{
6581	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6582	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6583	PVMSVGAR3STATE pSVGAState;
6584	int rc;
6585
6586	rc = RTStrFormatTypeRegister("float", vmsvga3dFloatFormat, NULL);
6587	AssertMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_ALREADY_EXISTS, ("%Rrc\n", rc), rc);
6588
6589	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6590	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6591
6592	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6593
6594	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6595	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6596	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6597
6598	/* Create event semaphore. */
6599	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6600	AssertRCReturn(rc, rc);
6601
6602	/* Create event semaphore. */
6603	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6604	AssertRCReturn(rc, rc);
6605
6606	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
6607	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6608
6609	rc = vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
6610	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6611
6612	pSVGAState = pThisCC->svga.pSvgaR3State;
6613
6614	/* Register the write-protected GBO access handler type (no ring-0 callbacks here). */
6615	rc = PDMDevHlpPGMHandlerPhysicalTypeRegister(pDevIns, PGMPHYSHANDLERKIND_WRITE, vmsvgaR3GboAccessHandler,
6616	"VMSVGA GBO", &pSVGAState->hGboAccessHandlerType);
6617	AssertRCReturn(rc, rc);
6618
6619	/* VRAM tracking is enabled by default during bootup. */
6620	pThis->svga.fVRAMTracking = true;
6621
6622	/* Set up the host bpp. This value is as a default for the programmable
6623	* bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
6624	* exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
6625	* separated as SVGA_REG_HOST_BITS_PER_PIXEL.
6626	*
6627	* NB: The driver cBits value is currently constant for the lifetime of the
6628	* VM. If that changes, the host bpp logic might need revisiting.
6629	*/
6630	pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
6631
6632	/* Invalidate current settings. */
6633	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6634	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6635	pThis->svga.uBpp = pThis->svga.uHostBpp;
6636	pThis->svga.cbScanline = 0;
6637
6638	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_XRES;
6639	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_YRES;
6640	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6641	{
6642	pThis->svga.u32MaxWidth -= 256;
6643	pThis->svga.u32MaxHeight -= 256;
6644	}
6645	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6646
6647	# ifdef DEBUG_GMR_ACCESS
6648	/* Register the GMR access handler type. */
6649	rc = PDMDevHlpPGMHandlerPhysicalTypeRegister(pDevIns, PGMPHYSHANDLERKIND_WRITE, vmsvgaR3GmrAccessHandler,
6650	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6651	AssertRCReturn(rc, rc);
6652	# endif
6653
6654	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6655	/* Register the FIFO access handler type. In addition to debugging FIFO
6656	access, this is also used to facilitate extended fifo thread sleeps. */
6657	rc = PDMDevHlpPGMHandlerPhysicalTypeRegister(pDevIns,
6658	# ifdef DEBUG_FIFO_ACCESS
6659	PGMPHYSHANDLERKIND_ALL,
6660	# else
6661	PGMPHYSHANDLERKIND_WRITE,
6662	# endif
6663	vmsvgaR3FifoAccessHandler,
6664	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6665	AssertRCReturn(rc, rc);
6666	# endif
6667
6668	/* Create the async IO thread. */
6669	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6670	RTTHREADTYPE_IO, "VMSVGA FIFO");
6671	if (RT_FAILURE(rc))
6672	{
6673	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6674	return rc;
6675	}
6676
6677	/*
6678	* Statistics.
6679	*/
6680	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6681	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6682	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6683	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6684	# ifdef VBOX_WITH_STATISTICS
6685	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6686	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6687	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6688	# endif
6689	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6690	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6691	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6692	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6693	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6694	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6695	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6696	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6697	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6698	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6699	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6700	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6701	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6702	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6703	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6704	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6705	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6706	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6707	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6708	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6709	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6710	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6711	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6712	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6713	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6714	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6715	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6716	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6717	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6718	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6719	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6720	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6721	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6722	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6723	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6724	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6725	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6726	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6727	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6728	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6729	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6730	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
6731	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
6732	REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
6733	REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
6734	REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
6735	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6736	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6737	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6738	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6739	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6740	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6741	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6742	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6743	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6744	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6745	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6746	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6747	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6748
6749	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6750	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6751	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6752	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6753	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6754	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6755	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
6756	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
6757	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) writes.");
6758	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
6759	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6760	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6761	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6762	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6763	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6764	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6765	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6766	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6767	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6768	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6769	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6770	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6771	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6772	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6773	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6774	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6775	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6776	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6777	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6778	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6779	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6780	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6781	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6782	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6783	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6784	REG_CNT(&pThis->svga.StatRegCommandLowWr, "VMSVGA/Reg/CommandLowWrite", "SVGA_REG_COMMAND_LOW writes.");
6785	REG_CNT(&pThis->svga.StatRegCommandHighWr, "VMSVGA/Reg/CommandHighWrite", "SVGA_REG_COMMAND_HIGH writes.");
6786	REG_CNT(&pThis->svga.StatRegDevCapWr, "VMSVGA/Reg/DevCapWrite", "SVGA_REG_DEV_CAP writes.");
6787	REG_CNT(&pThis->svga.StatRegCmdPrependLowWr, "VMSVGA/Reg/CmdPrependLowWrite", "SVGA_REG_CMD_PREPEND_LOW writes.");
6788	REG_CNT(&pThis->svga.StatRegCmdPrependHighWr, "VMSVGA/Reg/CmdPrependHighWrite", "SVGA_REG_CMD_PREPEND_HIGH writes.");
6789
6790	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6791	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6792	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6793	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6794	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6795	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6796	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
6797	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
6798	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) reads.");
6799	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
6800	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6801	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6802	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6803	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6804	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6805	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6806	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6807	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6808	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6809	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6810	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6811	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6812	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6813	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6814	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6815	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6816	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6817	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6818	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6819	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6820	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6821	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6822	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6823	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6824	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6825	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6826	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6827	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6828	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6829	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6830	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6831	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6832	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6833	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6834	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6835	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6836	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6837	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6838	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6839	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6840	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6841	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6842	REG_CNT(&pThis->svga.StatRegCommandLowRd, "VMSVGA/Reg/CommandLowRead", "SVGA_REG_COMMAND_LOW reads.");
6843	REG_CNT(&pThis->svga.StatRegCommandHighRd, "VMSVGA/Reg/CommandHighRead", "SVGA_REG_COMMAND_HIGH reads.");
6844	REG_CNT(&pThis->svga.StatRegMaxPrimBBMemRd, "VMSVGA/Reg/MaxPrimBBMemRead", "SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM reads.");
6845	REG_CNT(&pThis->svga.StatRegGBMemSizeRd, "VMSVGA/Reg/GBMemSizeRead", "SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB reads.");
6846	REG_CNT(&pThis->svga.StatRegDevCapRd, "VMSVGA/Reg/DevCapRead", "SVGA_REG_DEV_CAP reads.");
6847	REG_CNT(&pThis->svga.StatRegCmdPrependLowRd, "VMSVGA/Reg/CmdPrependLowRead", "SVGA_REG_CMD_PREPEND_LOW reads.");
6848	REG_CNT(&pThis->svga.StatRegCmdPrependHighRd, "VMSVGA/Reg/CmdPrependHighRead", "SVGA_REG_CMD_PREPEND_HIGH reads.");
6849	REG_CNT(&pThis->svga.StatRegScrnTgtMaxWidthRd, "VMSVGA/Reg/ScrnTgtMaxWidthRead", "SVGA_REG_SCREENTARGET_MAX_WIDTH reads.");
6850	REG_CNT(&pThis->svga.StatRegScrnTgtMaxHeightRd, "VMSVGA/Reg/ScrnTgtMaxHeightRead", "SVGA_REG_SCREENTARGET_MAX_HEIGHT reads.");
6851	REG_CNT(&pThis->svga.StatRegMobMaxSizeRd, "VMSVGA/Reg/MobMaxSizeRead", "SVGA_REG_MOB_MAX_SIZE reads.");
6852
6853	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6854	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6855	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6856	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6857	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6858	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6859	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6860	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6861	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6862	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6863	# endif
6864	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6865	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6866	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6867	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6868	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6869
6870	# undef REG_CNT
6871	# undef REG_PRF
6872
6873	/*
6874	* Info handlers.
6875	*/
6876	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6877	# ifdef VBOX_WITH_VMSVGA3D
6878	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6879	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6880	"VMSVGA 3d surface details. "
6881	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6882	vmsvgaR3Info3dSurface);
6883	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6884	"VMSVGA 3d surface details and bitmap: "
6885	"sid[>dir]",
6886	vmsvgaR3Info3dSurfaceBmp);
6887	# endif
6888
6889	return VINF_SUCCESS;
6890	}
6891
6892	/* Initialize 3D backend, set device capabilities and call pfnPowerOn callback of 3D backend.
6893	*
6894	* @param pDevIns The device instance.
6895	* @param pThis The shared VGA/VMSVGA instance data.
6896	* @param pThisCC The VGA/VMSVGA state for ring-3.
6897	* @param fLoadState Whether saved state is being loaded.
6898	*/
6899	static void vmsvgaR3PowerOnDevice(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, bool fLoadState)
6900	{
6901	# ifdef VBOX_WITH_VMSVGA3D
6902	if (pThis->svga.f3DEnabled)
6903	{
6904	/* Load a 3D backend. */
6905	int rc = vmsvgaR3Init3dInterfaces(pDevIns, pThis, pThisCC);
6906	if (RT_FAILURE(rc))
6907	{
6908	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6909	pThis->svga.f3DEnabled = false;
6910	}
6911	}
6912	# endif
6913
6914	# if defined(VBOX_WITH_VMSVGA3D) && defined(RT_OS_LINUX)
6915	if (pThis->svga.f3DEnabled)
6916	{
6917	/* The FIFO thread may use X API for accelerated screen output. */
6918	/* This must be done after backend initialization by vmsvgaR3Init3dInterfaces,
6919	* because it dynamically resolves XInitThreads.
6920	*/
6921	XInitThreads();
6922	}
6923	# endif
6924
6925	if (!fLoadState)
6926	{
6927	vmsvgaR3InitFIFO(pThis, pThisCC);
6928	vmsvgaR3GetCaps(pThis, pThisCC, &pThis->svga.u32DeviceCaps, &pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES]);
6929	}
6930	# ifdef DEBUG
6931	else
6932	{
6933	/* If saved state is being loaded then FIFO and caps are already restored. */
6934	uint32_t u32DeviceCaps = 0;
6935	uint32_t u32FIFOCaps = 0;
6936	vmsvgaR3GetCaps(pThis, pThisCC, &u32DeviceCaps, &u32FIFOCaps);
6937
6938	/* Capabilities should not change normally. */
6939	Assert( pThis->svga.u32DeviceCaps == u32DeviceCaps
6940	&& pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] == u32FIFOCaps);
6941	}
6942	#endif
6943
6944	# ifdef VBOX_WITH_VMSVGA3D
6945	if (pThis->svga.f3DEnabled)
6946	{
6947	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6948	int rc = pSVGAState->pFuncs3D->pfnPowerOn(pDevIns, pThis, pThisCC);
6949	if (RT_SUCCESS(rc))
6950	{
6951	/* Initialize FIFO 3D capabilities. */
6952	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
6953	}
6954	else
6955	{
6956	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dPowerOn -> %Rrc)\n", rc));
6957	pThis->svga.f3DEnabled = false;
6958	}
6959	}
6960	# else /* !VBOX_WITH_VMSVGA3D */
6961	RT_NOREF(pDevIns);
6962	# endif /* !VBOX_WITH_VMSVGA3D */
6963	}
6964
6965
6966	/**
6967	* Power On notification.
6968	*
6969	* @returns VBox status code.
6970	* @param pDevIns The device instance data.
6971	*
6972	* @remarks Caller enters the device critical section.
6973	*/
6974	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6975	{
6976	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6977	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6978
6979	vmsvgaR3PowerOnDevice(pDevIns, pThis, pThisCC, /fLoadState=/ false);
6980	}
6981
6982	/**
6983	* Power Off notification.
6984	*
6985	* @param pDevIns The device instance data.
6986	*
6987	* @remarks Caller enters the device critical section.
6988	*/
6989	DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns)
6990	{
6991	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6992	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6993
6994	/*
6995	* Notify the FIFO thread.
6996	*/
6997	if (pThisCC->svga.pFIFOIOThread)
6998	{
6999	/* Hack around a deadlock:
7000	* - the caller holds the device critsect;
7001	* - FIFO thread may attempt to enter the critsect too (when raising an IRQ).
7002	*/
7003	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
7004
7005	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_POWEROFF,
7006	NULL /pvParam/, 30000 /ms/);
7007	AssertLogRelRC(rc);
7008
7009	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
7010	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
7011	}
7012	}
7013
7014	#endif /* IN_RING3 */

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 96588

Download in other formats: