DevVGA-SVGA.cpp@ 94377

Last change on this file since 94377 was 94271, checked in by vboxsync, 3 years ago
Devices/Graphics: middes ifdefs: bugref:9830
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1	/* $Id: DevVGA-SVGA.cpp 94271 2022-03-16 14:39:27Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - Log6 for DX shaders.
13	* - Log7 for SVGA command dump.
14	* - LogRel for the usual important stuff.
15	* - LogRel2 for cursor.
16	* - LogRel3 for 3D performance data.
17	* - LogRel4 for HW accelerated graphics output.
18	*/
19
20	/*
21	* Copyright (C) 2013-2022 Oracle Corporation
22	*
23	* This file is part of VirtualBox Open Source Edition (OSE), as
24	* available from http://www.virtualbox.org. This file is free software;
25	* you can redistribute it and/or modify it under the terms of the GNU
26	* General Public License (GPL) as published by the Free Software
27	* Foundation, in version 2 as it comes in the "COPYING" file of the
28	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
29	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
30	*/
31
32
33	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
34	*
35	* This device emulation was contributed by trivirt AG. It offers an
36	* alternative to our Bochs based VGA graphics and 3d emulations. This is
37	* valuable for Xorg based guests, as there is driver support shipping with Xorg
38	* since it forked from XFree86.
39	*
40	*
41	* @section sec_dev_vmsvga_sdk The VMware SDK
42	*
43	* This is officially deprecated now, however it's still quite useful,
44	* especially for getting the old features working:
45	* http://vmware-svga.sourceforge.net/
46	*
47	* They currently point developers at the following resources.
48	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
49	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
50	* - http://cgit.freedesktop.org/mesa/vmwgfx/
51	*
52	* @subsection subsec_dev_vmsvga_sdk_results Test results
53	*
54	* Test results:
55	* - 2dmark.img:
56	* + todo
57	* - backdoor-tclo.img:
58	* + todo
59	* - blit-cube.img:
60	* + todo
61	* - bunnies.img:
62	* + todo
63	* - cube.img:
64	* + todo
65	* - cubemark.img:
66	* + todo
67	* - dynamic-vertex-stress.img:
68	* + todo
69	* - dynamic-vertex.img:
70	* + todo
71	* - fence-stress.img:
72	* + todo
73	* - gmr-test.img:
74	* + todo
75	* - half-float-test.img:
76	* + todo
77	* - noscreen-cursor.img:
78	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
79	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
80	* visible though.)
81	* - Cursor animation via the palette doesn't work.
82	* - During debugging, it turns out that the framebuffer content seems to
83	* be halfways ignore or something (memset(fb, 0xcc, lots)).
84	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
85	* grow it 0x10 fold (128KB -> 2MB like in WS10).
86	* - null.img:
87	* + todo
88	* - pong.img:
89	* + todo
90	* - presentReadback.img:
91	* + todo
92	* - resolution-set.img:
93	* + todo
94	* - rt-gamma-test.img:
95	* + todo
96	* - screen-annotation.img:
97	* + todo
98	* - screen-cursor.img:
99	* + todo
100	* - screen-dma-coalesce.img:
101	* + todo
102	* - screen-gmr-discontig.img:
103	* + todo
104	* - screen-gmr-remap.img:
105	* + todo
106	* - screen-multimon.img:
107	* + todo
108	* - screen-present-clip.img:
109	* + todo
110	* - screen-render-test.img:
111	* + todo
112	* - screen-simple.img:
113	* + todo
114	* - screen-text.img:
115	* + todo
116	* - simple-shaders.img:
117	* + todo
118	* - simple_blit.img:
119	* + todo
120	* - tiny-2d-updates.img:
121	* + todo
122	* - video-formats.img:
123	* + todo
124	* - video-sync.img:
125	* + todo
126	*
127	*/
128
129
130	/*********************************************************************************************************************************
131	* Header Files *
132	*********************************************************************************************************************************/
133	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
134	#include <VBox/vmm/pdmdev.h>
135	#include <VBox/version.h>
136	#include <VBox/err.h>
137	#include <VBox/log.h>
138	#include <VBox/vmm/pgm.h>
139	#include <VBox/sup.h>
140
141	#include <iprt/assert.h>
142	#include <iprt/semaphore.h>
143	#include <iprt/uuid.h>
144	#ifdef IN_RING3
145	# include <iprt/ctype.h>
146	# include <iprt/mem.h>
147	# ifdef VBOX_STRICT
148	# include <iprt/time.h>
149	# endif
150	#endif
151
152	#include <VBox/AssertGuest.h>
153	#include <VBox/VMMDev.h>
154	#include <VBoxVideo.h>
155	#include <VBox/bioslogo.h>
156
157	#ifdef LOG_ENABLED
158	#include "svgadump/svga_dump.h"
159	#endif
160
161	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
162	#include "DevVGA.h"
163
164	/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
165	#ifdef VBOX_WITH_VMSVGA3D
166	# include "DevVGA-SVGA3d.h"
167	# ifdef RT_OS_DARWIN
168	# include "DevVGA-SVGA3d-cocoa.h"
169	# endif
170	# ifdef RT_OS_LINUX
171	# ifdef IN_RING3
172	# include "DevVGA-SVGA3d-glLdr.h"
173	# endif
174	# endif
175	#endif
176	#ifdef IN_RING3
177	#include "DevVGA-SVGA-internal.h"
178	#endif
179
180
181	/*********************************************************************************************************************************
182	* Defined Constants And Macros *
183	*********************************************************************************************************************************/
184	/**
185	* Macro for checking if a fixed FIFO register is valid according to the
186	* current FIFO configuration.
187	*
188	* @returns true / false.
189	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
190	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
191	*/
192	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
193
194
195	/*********************************************************************************************************************************
196	* Structures and Typedefs *
197	*********************************************************************************************************************************/
198
199
200	/*********************************************************************************************************************************
201	* Internal Functions *
202	*********************************************************************************************************************************/
203	#ifdef IN_RING3
204	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
205	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
206	# endif
207	# ifdef DEBUG_GMR_ACCESS
208	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
209	# endif
210	#endif
211
212
213	/*********************************************************************************************************************************
214	* Global Variables *
215	*********************************************************************************************************************************/
216	#ifdef IN_RING3
217
218	/**
219	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
220	*/
221	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
222	{
223	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
224	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
225	SSMFIELD_ENTRY_TERM()
226	};
227
228	/**
229	* SSM descriptor table for the GMR structure.
230	*/
231	static SSMFIELD const g_aGMRFields[] =
232	{
233	SSMFIELD_ENTRY( GMR, cMaxPages),
234	SSMFIELD_ENTRY( GMR, cbTotal),
235	SSMFIELD_ENTRY( GMR, numDescriptors),
236	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
237	SSMFIELD_ENTRY_TERM()
238	};
239
240	/**
241	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
242	*/
243	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
244	{
245	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
246	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
247	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
248	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
249	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
250	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
251	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
252	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
253	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
254	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
255	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
256	SSMFIELD_ENTRY_VER( VMSVGASCREENOBJECT, cDpi, VGA_SAVEDSTATE_VERSION_VMSVGA_MIPLEVELS),
257	SSMFIELD_ENTRY_TERM()
258	};
259
260	/**
261	* SSM descriptor table for the VMSVGAR3STATE structure.
262	*/
263	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
264	{
265	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
266	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
267	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
268	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
269	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
270	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
271	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
272	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
273	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
274	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
275	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
276	#ifdef VMSVGA_USE_EMT_HALT_CODE
277	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
278	#else
279	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
280	#endif
281	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
282	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
283	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
284	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
285	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
286	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
287	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
288	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
289	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
290	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
291	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
292	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
293	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
294	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
295	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
296	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
297	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
298	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
299	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
300	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
301	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
302	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
303	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
304	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
305	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
306	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
307	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
308	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
309	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
310	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
311	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
312	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
313	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
314	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
315	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
316	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
317	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
318	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
319	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
320	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
321	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
322	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
323	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
324	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
325	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
326	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
327	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
328	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
329	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
330	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
331	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
332	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
333	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
334	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
335	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
336	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
337	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
338	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
339	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
340	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
341	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
342	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
343	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
344
345	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
346	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
347	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
348	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
349
350	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
351	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
352	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
353	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
354	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
355	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
356	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
357	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
358	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
359	# endif
360	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
361	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
362	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
363	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
364
365	SSMFIELD_ENTRY_TERM()
366	};
367
368	/**
369	* SSM descriptor table for the VGAState.svga structure.
370	*/
371	static SSMFIELD const g_aVGAStateSVGAFields[] =
372	{
373	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
374	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
375	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
376	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
377	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
378	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
379	SSMFIELD_ENTRY( VMSVGAState, fBusy),
380	SSMFIELD_ENTRY( VMSVGAState, fTraces),
381	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
382	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
383	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
384	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
385	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
386	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
387	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
388	SSMFIELD_ENTRY( VMSVGAState, u32DeviceCaps),
389	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
390	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
391	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
392	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
393	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
394	SSMFIELD_ENTRY( VMSVGAState, uWidth),
395	SSMFIELD_ENTRY( VMSVGAState, uHeight),
396	SSMFIELD_ENTRY( VMSVGAState, uBpp),
397	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
398	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
399	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
400	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
401	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
402	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
403	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
404	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
405	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
406	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
407	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
408	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
409	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
410	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
411	SSMFIELD_ENTRY_VER( VMSVGAState, au32DevCaps, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
412	SSMFIELD_ENTRY_VER( VMSVGAState, u32DevCapIndex, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
413	SSMFIELD_ENTRY_VER( VMSVGAState, u32RegCommandLow, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
414	SSMFIELD_ENTRY_VER( VMSVGAState, u32RegCommandHigh, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
415
416	SSMFIELD_ENTRY_TERM()
417	};
418	#endif /* IN_RING3 */
419
420
421	/*********************************************************************************************************************************
422	* Internal Functions *
423	*********************************************************************************************************************************/
424	#ifdef IN_RING3
425	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
426	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
427	uint32_t uVersion, uint32_t uPass);
428	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
429	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx);
430	#endif /* IN_RING3 */
431
432
433	#define SVGA_CASE_ID2STR(idx) case idx: return #idx
434	#if defined(LOG_ENABLED)
435	/**
436	* Index register string name lookup
437	*
438	* @returns Index register string or "UNKNOWN"
439	* @param pThis The shared VGA/VMSVGA state.
440	* @param idxReg The index register.
441	*/
442	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
443	{
444	AssertCompile(SVGA_REG_TOP == 77); /* Ensure that the correct headers are used. */
445	switch (idxReg)
446	{
447	SVGA_CASE_ID2STR(SVGA_REG_ID);
448	SVGA_CASE_ID2STR(SVGA_REG_ENABLE);
449	SVGA_CASE_ID2STR(SVGA_REG_WIDTH);
450	SVGA_CASE_ID2STR(SVGA_REG_HEIGHT);
451	SVGA_CASE_ID2STR(SVGA_REG_MAX_WIDTH);
452	SVGA_CASE_ID2STR(SVGA_REG_MAX_HEIGHT);
453	SVGA_CASE_ID2STR(SVGA_REG_DEPTH);
454	SVGA_CASE_ID2STR(SVGA_REG_BITS_PER_PIXEL); /* Current bpp in the guest */
455	SVGA_CASE_ID2STR(SVGA_REG_PSEUDOCOLOR);
456	SVGA_CASE_ID2STR(SVGA_REG_RED_MASK);
457	SVGA_CASE_ID2STR(SVGA_REG_GREEN_MASK);
458	SVGA_CASE_ID2STR(SVGA_REG_BLUE_MASK);
459	SVGA_CASE_ID2STR(SVGA_REG_BYTES_PER_LINE);
460	SVGA_CASE_ID2STR(SVGA_REG_FB_START); /* (Deprecated) */
461	SVGA_CASE_ID2STR(SVGA_REG_FB_OFFSET);
462	SVGA_CASE_ID2STR(SVGA_REG_VRAM_SIZE);
463	SVGA_CASE_ID2STR(SVGA_REG_FB_SIZE);
464
465	/* ID 0 implementation only had the above registers, then the palette */
466	SVGA_CASE_ID2STR(SVGA_REG_CAPABILITIES);
467	SVGA_CASE_ID2STR(SVGA_REG_MEM_START); /* (Deprecated) */
468	SVGA_CASE_ID2STR(SVGA_REG_MEM_SIZE);
469	SVGA_CASE_ID2STR(SVGA_REG_CONFIG_DONE); /* Set when memory area configured */
470	SVGA_CASE_ID2STR(SVGA_REG_SYNC); /* See "FIFO Synchronization Registers" */
471	SVGA_CASE_ID2STR(SVGA_REG_BUSY); /* See "FIFO Synchronization Registers" */
472	SVGA_CASE_ID2STR(SVGA_REG_GUEST_ID); /* Set guest OS identifier */
473	SVGA_CASE_ID2STR(SVGA_REG_DEAD); /* (Deprecated) SVGA_REG_CURSOR_ID. */
474	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_X); /* (Deprecated) */
475	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_Y); /* (Deprecated) */
476	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ON); /* (Deprecated) */
477	SVGA_CASE_ID2STR(SVGA_REG_HOST_BITS_PER_PIXEL); /* (Deprecated) */
478	SVGA_CASE_ID2STR(SVGA_REG_SCRATCH_SIZE); /* Number of scratch registers */
479	SVGA_CASE_ID2STR(SVGA_REG_MEM_REGS); /* Number of FIFO registers */
480	SVGA_CASE_ID2STR(SVGA_REG_NUM_DISPLAYS); /* (Deprecated) */
481	SVGA_CASE_ID2STR(SVGA_REG_PITCHLOCK); /* Fixed pitch for all modes */
482	SVGA_CASE_ID2STR(SVGA_REG_IRQMASK); /* Interrupt mask */
483
484	/* Legacy multi-monitor support */
485	SVGA_CASE_ID2STR(SVGA_REG_NUM_GUEST_DISPLAYS); /* Number of guest displays in X/Y direction */
486	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_ID); /* Display ID for the following display attributes */
487	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_IS_PRIMARY); /* Whether this is a primary display */
488	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_X); /* The display position x */
489	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_Y); /* The display position y */
490	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_WIDTH); /* The display's width */
491	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_HEIGHT); /* The display's height */
492
493	SVGA_CASE_ID2STR(SVGA_REG_GMR_ID);
494	SVGA_CASE_ID2STR(SVGA_REG_GMR_DESCRIPTOR);
495	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_IDS);
496	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
497
498	SVGA_CASE_ID2STR(SVGA_REG_TRACES); /* Enable trace-based updates even when FIFO is on */
499	SVGA_CASE_ID2STR(SVGA_REG_GMRS_MAX_PAGES); /* Maximum number of 4KB pages for all GMRs */
500	SVGA_CASE_ID2STR(SVGA_REG_MEMORY_SIZE); /* Total dedicated device memory excluding FIFO */
501	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_LOW); /* Lower 32 bits and submits commands */
502	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_HIGH); /* Upper 32 bits of command buffer PA */
503	SVGA_CASE_ID2STR(SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); /* Max primary memory */
504	SVGA_CASE_ID2STR(SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); /* Suggested limit on mob mem */
505	SVGA_CASE_ID2STR(SVGA_REG_DEV_CAP); /* Write dev cap index, read value */
506	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_LOW);
507	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_HIGH);
508	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_WIDTH);
509	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_HEIGHT);
510	SVGA_CASE_ID2STR(SVGA_REG_MOB_MAX_SIZE);
511	SVGA_CASE_ID2STR(SVGA_REG_BLANK_SCREEN_TARGETS);
512	SVGA_CASE_ID2STR(SVGA_REG_CAP2);
513	SVGA_CASE_ID2STR(SVGA_REG_DEVEL_CAP);
514	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_ID);
515	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION1);
516	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION2);
517	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION3);
518	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MOBID);
519	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_BYTE_SIZE);
520	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_DIMENSION);
521	SVGA_CASE_ID2STR(SVGA_REG_FIFO_CAPS);
522	SVGA_CASE_ID2STR(SVGA_REG_FENCE);
523	SVGA_CASE_ID2STR(SVGA_REG_RESERVED1);
524	SVGA_CASE_ID2STR(SVGA_REG_RESERVED2);
525	SVGA_CASE_ID2STR(SVGA_REG_RESERVED3);
526	SVGA_CASE_ID2STR(SVGA_REG_RESERVED4);
527	SVGA_CASE_ID2STR(SVGA_REG_RESERVED5);
528	SVGA_CASE_ID2STR(SVGA_REG_SCREENDMA);
529	SVGA_CASE_ID2STR(SVGA_REG_GBOBJECT_MEM_SIZE_KB);
530	SVGA_CASE_ID2STR(SVGA_REG_TOP); /* Must be 1 more than the last register */
531
532	default:
533	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
534	return "SVGA_SCRATCH_BASE reg";
535	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
536	return "SVGA_PALETTE_BASE reg";
537	return "UNKNOWN";
538	}
539	}
540	#endif /* LOG_ENABLED */
541
542	#if defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D))
543	static const char *vmsvgaDevCapIndexToString(SVGA3dDevCapIndex idxDevCap)
544	{
545	AssertCompile(SVGA3D_DEVCAP_MAX == 260);
546	switch (idxDevCap)
547	{
548	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_INVALID);
549	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_3D);
550	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LIGHTS);
551	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURES);
552	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CLIP_PLANES);
553	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER_VERSION);
554	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER);
555	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION);
556	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER);
557	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_RENDER_TARGETS);
558	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S23E8_TEXTURES);
559	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S10E5_TEXTURES);
560	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND);
561	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D16_BUFFER_FORMAT);
562	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT);
563	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT);
564	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_QUERY_TYPES);
565	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING);
566	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_POINT_SIZE);
567	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SHADER_TEXTURES);
568	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
569	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
570	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VOLUME_EXTENT);
571	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT);
572	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO);
573	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY);
574	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT);
575	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_INDEX);
576	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS);
577	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS);
578	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS);
579	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS);
580	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_OPS);
581	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);
582	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8);
583	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10);
584	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5);
585	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5);
586	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4);
587	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R5G6B5);
588	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16);
589	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8);
590	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ALPHA8);
591	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8);
592	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D16);
593	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8);
594	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8);
595	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT1);
596	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT2);
597	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT3);
598	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT4);
599	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT5);
600	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8);
601	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10);
602	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8);
603	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8);
604	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_CxV8U8);
605	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S10E5);
606	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S23E8);
607	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5);
608	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8);
609	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5);
610	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8);
611	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MISSING62);
612	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES);
613	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS);
614	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_V16U16);
615	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_G16R16);
616	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16);
617	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_UYVY);
618	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YUY2);
619	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD4); /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
620	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD5); /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
621	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD7); /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
622	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD6); /* SVGA3D_DEVCAP_SUPERSAMPLE */
623	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_AUTOGENMIPMAPS);
624	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_NV12);
625	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD10); /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
626	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CONTEXT_IDS);
627	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SURFACE_IDS);
628	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF16);
629	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF24);
630	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT);
631	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI1);
632	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI2);
633	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD1);
634	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD8); /* SVGA3D_DEVCAP_VIDEO_DECODE */
635	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD9); /* SVGA3D_DEVCAP_VIDEO_PROCESS */
636	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_AA);
637	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_STIPPLE);
638	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LINE_WIDTH);
639	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH);
640	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YV12);
641	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD3); /* Old SVGA3D_DEVCAP_LOGICOPS */
642	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TS_COLOR_KEY);
643	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD2);
644	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXCONTEXT);
645	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD11); /* SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE */
646	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS);
647	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS);
648	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_PROVOKING_VERTEX);
649	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8R8G8B8);
650	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8R8G8B8);
651	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R5G6B5);
652	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X1R5G5B5);
653	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A1R5G5B5);
654	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A4R4G4B4);
655	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D32);
656	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D16);
657	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8);
658	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D15S1);
659	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8);
660	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4);
661	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE16);
662	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8);
663	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT1);
664	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT2);
665	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT3);
666	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT4);
667	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT5);
668	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPU8V8);
669	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5);
670	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8);
671	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1);
672	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5);
673	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8);
674	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2R10G10B10);
675	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V8U8);
676	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8);
677	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_CxV8U8);
678	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8L8V8U8);
679	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2W10V10U10);
680	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ALPHA8);
681	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S10E5);
682	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S23E8);
683	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S10E5);
684	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S23E8);
685	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUFFER);
686	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24X8);
687	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V16U16);
688	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G16R16);
689	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A16B16G16R16);
690	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_UYVY);
691	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YUY2);
692	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_NV12);
693	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2); /* SVGA3D_DEVCAP_DXFMT_AYUV */
694	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS);
695	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT);
696	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT);
697	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS);
698	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT);
699	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT);
700	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT);
701	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS);
702	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT);
703	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM);
704	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT);
705	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS);
706	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_UINT);
707	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_SINT);
708	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS);
709	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT);
710	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24);
711	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT);
712	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS);
713	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT);
714	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT);
715	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS);
716	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM);
717	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB);
718	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT);
719	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT);
720	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS);
721	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UINT);
722	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SINT);
723	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS);
724	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT);
725	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_UINT);
726	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_SINT);
727	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS);
728	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT);
729	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8);
730	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X24_G8_UINT);
731	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS);
732	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM);
733	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UINT);
734	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SINT);
735	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS);
736	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UNORM);
737	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UINT);
738	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SNORM);
739	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SINT);
740	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS);
741	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UNORM);
742	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UINT);
743	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SNORM);
744	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SINT);
745	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_P8);
746	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP);
747	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM);
748	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM);
749	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS);
750	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB);
751	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS);
752	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB);
753	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS);
754	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB);
755	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS);
756	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI1);
757	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_SNORM);
758	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS);
759	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI2);
760	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_SNORM);
761	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM);
762	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS);
763	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB);
764	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS);
765	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB);
766	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF16);
767	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF24);
768	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT);
769	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YV12);
770	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT);
771	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT);
772	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM);
773	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT);
774	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM);
775	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM);
776	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT);
777	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM);
778	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM);
779	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT);
780	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM);
781	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_FLOAT);
782	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D16_UNORM);
783	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8_UNORM);
784	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM);
785	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM);
786	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM);
787	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM);
788	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM);
789	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM);
790	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM);
791	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_UNORM);
792	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_UNORM);
793	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM41);
794	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_2X);
795	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_4X);
796	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MS_FULL_QUALITY);
797	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGICOPS);
798	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGIC_BLENDOPS);
799	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_1);
800	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS);
801	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_UF16);
802	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_SF16);
803	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS);
804	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM);
805	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB);
806	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_2);
807	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM5);
808	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_8X);
809
810	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX);
811
812	default:
813	break;
814	}
815	return "UNKNOWN";
816	}
817	#endif /* defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D)) */
818	#undef SVGA_CASE_ID2STR
819
820
821	#ifdef IN_RING3
822
823	/**
824	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
825	*/
826	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
827	{
828	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
829	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
830
831	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
832	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
833
834	/** @todo Test how it interacts with multiple screen objects. */
835	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
836	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
837	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
838
839	if (x < uWidth)
840	{
841	pThis->svga.viewport.x = x;
842	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
843	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
844	}
845	else
846	{
847	pThis->svga.viewport.x = uWidth;
848	pThis->svga.viewport.cx = 0;
849	pThis->svga.viewport.xRight = uWidth;
850	}
851	if (y < uHeight)
852	{
853	pThis->svga.viewport.y = y;
854	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
855	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
856	pThis->svga.viewport.yHighWC = uHeight - y;
857	}
858	else
859	{
860	pThis->svga.viewport.y = uHeight;
861	pThis->svga.viewport.cy = 0;
862	pThis->svga.viewport.yLowWC = 0;
863	pThis->svga.viewport.yHighWC = 0;
864	}
865
866	# ifdef VBOX_WITH_VMSVGA3D
867	/*
868	* Now inform the 3D backend.
869	*/
870	if (pThis->svga.f3DEnabled)
871	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
872	# else
873	RT_NOREF(OldViewport);
874	# endif
875	}
876
877
878	/**
879	* Updating screen information in API
880	*
881	* @param pThis The The shared VGA/VMSVGA instance data.
882	* @param pThisCC The VGA/VMSVGA state for ring-3.
883	*/
884	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
885	{
886	int rc;
887
888	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
889
890	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
891	{
892	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
893	if (!pScreen->fModified)
894	continue;
895
896	pScreen->fModified = false;
897
898	VBVAINFOVIEW view;
899	RT_ZERO(view);
900	view.u32ViewIndex = pScreen->idScreen;
901	// view.u32ViewOffset = 0;
902	view.u32ViewSize = pThis->vram_size;
903	view.u32MaxScreenSize = pThis->vram_size;
904
905	VBVAINFOSCREEN screen;
906	RT_ZERO(screen);
907	screen.u32ViewIndex = pScreen->idScreen;
908
909	if (pScreen->fDefined)
910	{
911	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
912	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
913	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
914	{
915	Assert(pThis->svga.fGFBRegisters);
916	continue;
917	}
918
919	screen.i32OriginX = pScreen->xOrigin;
920	screen.i32OriginY = pScreen->yOrigin;
921	screen.u32StartOffset = pScreen->offVRAM;
922	screen.u32LineSize = pScreen->cbPitch;
923	screen.u32Width = pScreen->cWidth;
924	screen.u32Height = pScreen->cHeight;
925	screen.u16BitsPerPixel = pScreen->cBpp;
926	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
927	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
928	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
929	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
930	}
931	else
932	{
933	/* Screen is destroyed. */
934	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
935	}
936
937	void *pvVRAM = pScreen->pvScreenBitmap ? pScreen->pvScreenBitmap : pThisCC->pbVRam;
938	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pvVRAM, /fResetInputMapping=/ true);
939	AssertRC(rc);
940	}
941	}
942
943
944	/**
945	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
946	*
947	* Used to update screen offsets (positions) since appearently vmwgfx fails to
948	* pass correct offsets thru FIFO.
949	*/
950	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
951	{
952	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
953	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
954	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
955
956	AssertReturnVoid(pSVGAState);
957
958	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
959	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
960	for (uint32_t i = 0; i < cPositions; ++i)
961	{
962	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
963	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
964	continue;
965
966	if (paPositions[i].x == -1)
967	continue;
968	if (paPositions[i].y == -1)
969	continue;
970
971	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
972	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
973	pSVGAState->aScreens[i].fModified = true;
974	}
975
976	vmsvgaR3VBVAResize(pThis, pThisCC);
977	}
978
979	#endif /* IN_RING3 */
980
981	/**
982	* Read port register
983	*
984	* @returns VBox status code.
985	* @param pDevIns The device instance.
986	* @param pThis The shared VGA/VMSVGA state.
987	* @param pu32 Where to store the read value
988	*/
989	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
990	{
991	#ifdef IN_RING3
992	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
993	#endif
994	int rc = VINF_SUCCESS;
995	*pu32 = 0;
996
997	/* Rough index register validation. */
998	uint32_t idxReg = pThis->svga.u32IndexReg;
999	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1000	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1001	VINF_IOM_R3_IOPORT_READ);
1002	#else
1003	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1004	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
1005	VINF_SUCCESS);
1006	#endif
1007	RT_UNTRUSTED_VALIDATED_FENCE();
1008
1009	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1010	if ( idxReg >= SVGA_REG_ID_0_TOP
1011	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1012	{
1013	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1014	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1015	}
1016
1017	switch (idxReg)
1018	{
1019	case SVGA_REG_ID:
1020	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
1021	*pu32 = pThis->svga.u32SVGAId;
1022	break;
1023
1024	case SVGA_REG_ENABLE:
1025	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
1026	*pu32 = pThis->svga.fEnabled;
1027	break;
1028
1029	case SVGA_REG_WIDTH:
1030	{
1031	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
1032	if ( pThis->svga.fEnabled
1033	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
1034	*pu32 = pThis->svga.uWidth;
1035	else
1036	{
1037	#ifndef IN_RING3
1038	rc = VINF_IOM_R3_IOPORT_READ;
1039	#else
1040	*pu32 = pThisCC->pDrv->cx;
1041	#endif
1042	}
1043	break;
1044	}
1045
1046	case SVGA_REG_HEIGHT:
1047	{
1048	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
1049	if ( pThis->svga.fEnabled
1050	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1051	*pu32 = pThis->svga.uHeight;
1052	else
1053	{
1054	#ifndef IN_RING3
1055	rc = VINF_IOM_R3_IOPORT_READ;
1056	#else
1057	*pu32 = pThisCC->pDrv->cy;
1058	#endif
1059	}
1060	break;
1061	}
1062
1063	case SVGA_REG_MAX_WIDTH:
1064	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
1065	*pu32 = pThis->svga.u32MaxWidth;
1066	break;
1067
1068	case SVGA_REG_MAX_HEIGHT:
1069	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
1070	*pu32 = pThis->svga.u32MaxHeight;
1071	break;
1072
1073	case SVGA_REG_DEPTH:
1074	/* This returns the color depth of the current mode. */
1075	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
1076	switch (pThis->svga.uBpp)
1077	{
1078	case 15:
1079	case 16:
1080	case 24:
1081	*pu32 = pThis->svga.uBpp;
1082	break;
1083
1084	default:
1085	case 32:
1086	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
1087	break;
1088	}
1089	break;
1090
1091	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1092	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1093	*pu32 = pThis->svga.uHostBpp;
1094	break;
1095
1096	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1097	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1098	*pu32 = pThis->svga.uBpp;
1099	break;
1100
1101	case SVGA_REG_PSEUDOCOLOR:
1102	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1103	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1104	break;
1105
1106	case SVGA_REG_RED_MASK:
1107	case SVGA_REG_GREEN_MASK:
1108	case SVGA_REG_BLUE_MASK:
1109	{
1110	uint32_t uBpp;
1111
1112	if (pThis->svga.fEnabled)
1113	uBpp = pThis->svga.uBpp;
1114	else
1115	uBpp = pThis->svga.uHostBpp;
1116
1117	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1118	switch (uBpp)
1119	{
1120	case 8:
1121	u32RedMask = 0x07;
1122	u32GreenMask = 0x38;
1123	u32BlueMask = 0xc0;
1124	break;
1125
1126	case 15:
1127	u32RedMask = 0x0000001f;
1128	u32GreenMask = 0x000003e0;
1129	u32BlueMask = 0x00007c00;
1130	break;
1131
1132	case 16:
1133	u32RedMask = 0x0000001f;
1134	u32GreenMask = 0x000007e0;
1135	u32BlueMask = 0x0000f800;
1136	break;
1137
1138	case 24:
1139	case 32:
1140	default:
1141	u32RedMask = 0x00ff0000;
1142	u32GreenMask = 0x0000ff00;
1143	u32BlueMask = 0x000000ff;
1144	break;
1145	}
1146	switch (idxReg)
1147	{
1148	case SVGA_REG_RED_MASK:
1149	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1150	*pu32 = u32RedMask;
1151	break;
1152
1153	case SVGA_REG_GREEN_MASK:
1154	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1155	*pu32 = u32GreenMask;
1156	break;
1157
1158	case SVGA_REG_BLUE_MASK:
1159	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1160	*pu32 = u32BlueMask;
1161	break;
1162	}
1163	break;
1164	}
1165
1166	case SVGA_REG_BYTES_PER_LINE:
1167	{
1168	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1169	if ( pThis->svga.fEnabled
1170	&& pThis->svga.cbScanline)
1171	*pu32 = pThis->svga.cbScanline;
1172	else
1173	{
1174	#ifndef IN_RING3
1175	rc = VINF_IOM_R3_IOPORT_READ;
1176	#else
1177	*pu32 = pThisCC->pDrv->cbScanline;
1178	#endif
1179	}
1180	break;
1181	}
1182
1183	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1184	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1185	*pu32 = pThis->vram_size;
1186	break;
1187
1188	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1189	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1190	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1191	*pu32 = pThis->GCPhysVRAM;
1192	break;
1193
1194	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1195	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1196	/* Always zero in our case. */
1197	*pu32 = 0;
1198	break;
1199
1200	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1201	{
1202	#ifndef IN_RING3
1203	rc = VINF_IOM_R3_IOPORT_READ;
1204	#else
1205	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1206
1207	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1208	if ( pThis->svga.fEnabled
1209	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1210	{
1211	/* Hardware enabled; return real framebuffer size .*/
1212	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1213	}
1214	else
1215	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1216
1217	pu32 = RT_MIN(pThis->vram_size, pu32);
1218	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1219	#endif
1220	break;
1221	}
1222
1223	case SVGA_REG_CAPABILITIES:
1224	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1225	*pu32 = pThis->svga.u32DeviceCaps;
1226	break;
1227
1228	case SVGA_REG_MEM_START: /* FIFO start */
1229	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1230	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1231	*pu32 = pThis->svga.GCPhysFIFO;
1232	break;
1233
1234	case SVGA_REG_MEM_SIZE: /* FIFO size */
1235	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1236	*pu32 = pThis->svga.cbFIFO;
1237	break;
1238
1239	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1240	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1241	*pu32 = pThis->svga.fConfigured;
1242	break;
1243
1244	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1245	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1246	*pu32 = 0;
1247	break;
1248
1249	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1250	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1251	if (pThis->svga.fBusy)
1252	{
1253	#ifndef IN_RING3
1254	/* Go to ring-3 and halt the CPU. */
1255	rc = VINF_IOM_R3_IOPORT_READ;
1256	RT_NOREF(pDevIns);
1257	break;
1258	#else /* IN_RING3 */
1259	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1260	/* The guest is basically doing a HLT via the device here, but with
1261	a special wake up condition on FIFO completion. */
1262	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1263	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1264	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1265	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1266	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1267	if (pThis->svga.fBusy)
1268	{
1269	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1270	rc = PDMDevHlpVMWaitForDeviceReady(pDevIns, idCpu);
1271	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1272	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
1273	}
1274	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1275	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1276	# else
1277
1278	/* Delay the EMT a bit so the FIFO and others can get some work done.
1279	This used to be a crude 50 ms sleep. The current code tries to be
1280	more efficient, but the consept is still very crude. */
1281	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1282	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1283	RTThreadYield();
1284	if (pThis->svga.fBusy)
1285	{
1286	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1287
1288	if (pThis->svga.fBusy && cRefs == 1)
1289	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1290	if (pThis->svga.fBusy)
1291	{
1292	/** @todo If this code is going to stay, we need to call into the halt/wait
1293	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1294	* suffer when the guest is polling on a busy FIFO. */
1295	uint64_t uIgnored1, uIgnored2;
1296	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns), &uIgnored1, &uIgnored2);
1297	if (cNsMaxWait >= RT_NS_100US)
1298	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1299	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1300	RT_MIN(cNsMaxWait, RT_NS_10MS));
1301	}
1302
1303	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1304	}
1305	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1306	# endif
1307	*pu32 = pThis->svga.fBusy != 0;
1308	#endif /* IN_RING3 */
1309	}
1310	else
1311	*pu32 = false;
1312	break;
1313
1314	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1315	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1316	*pu32 = pThis->svga.u32GuestId;
1317	break;
1318
1319	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1320	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1321	*pu32 = pThis->svga.cScratchRegion;
1322	break;
1323
1324	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1325	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1326	*pu32 = SVGA_FIFO_NUM_REGS;
1327	break;
1328
1329	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1330	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1331	*pu32 = pThis->svga.u32PitchLock;
1332	break;
1333
1334	case SVGA_REG_IRQMASK: /* Interrupt mask */
1335	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1336	*pu32 = pThis->svga.u32IrqMask;
1337	break;
1338
1339	/* See "Guest memory regions" below. */
1340	case SVGA_REG_GMR_ID:
1341	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1342	*pu32 = pThis->svga.u32CurrentGMRId;
1343	break;
1344
1345	case SVGA_REG_GMR_DESCRIPTOR:
1346	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1347	/* Write only */
1348	*pu32 = 0;
1349	break;
1350
1351	case SVGA_REG_GMR_MAX_IDS:
1352	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1353	*pu32 = pThis->svga.cGMR;
1354	break;
1355
1356	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1357	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1358	*pu32 = VMSVGA_MAX_GMR_PAGES;
1359	break;
1360
1361	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1362	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1363	*pu32 = pThis->svga.fTraces;
1364	break;
1365
1366	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1367	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1368	*pu32 = VMSVGA_MAX_GMR_PAGES;
1369	break;
1370
1371	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1372	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1373	*pu32 = VMSVGA_SURFACE_SIZE;
1374	break;
1375
1376	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1377	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1378	break;
1379
1380	/* Mouse cursor support. */
1381	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
1382	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1383	*pu32 = pThis->svga.uCursorID;
1384	break;
1385
1386	case SVGA_REG_CURSOR_X:
1387	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1388	*pu32 = pThis->svga.uCursorX;
1389	break;
1390
1391	case SVGA_REG_CURSOR_Y:
1392	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1393	*pu32 = pThis->svga.uCursorY;
1394	break;
1395
1396	case SVGA_REG_CURSOR_ON:
1397	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1398	*pu32 = pThis->svga.uCursorOn;
1399	break;
1400
1401	/* Legacy multi-monitor support */
1402	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1403	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1404	*pu32 = 1;
1405	break;
1406
1407	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1408	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1409	*pu32 = 0;
1410	break;
1411
1412	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1413	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1414	*pu32 = 0;
1415	break;
1416
1417	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1418	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1419	*pu32 = 0;
1420	break;
1421
1422	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1423	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1424	*pu32 = 0;
1425	break;
1426
1427	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1428	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1429	*pu32 = pThis->svga.uWidth;
1430	break;
1431
1432	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1433	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1434	*pu32 = pThis->svga.uHeight;
1435	break;
1436
1437	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1438	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1439	/* We must return something sensible here otherwise the Linux driver
1440	will take a legacy code path without 3d support. This number also
1441	limits how many screens Linux guests will allow. */
1442	*pu32 = pThis->cMonitors;
1443	break;
1444
1445	/*
1446	* SVGA_CAP_GBOBJECTS+ registers.
1447	*/
1448	case SVGA_REG_COMMAND_LOW:
1449	/* Lower 32 bits of command buffer physical address. */
1450	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowRd);
1451	*pu32 = pThis->svga.u32RegCommandLow;
1452	break;
1453
1454	case SVGA_REG_COMMAND_HIGH:
1455	/* Upper 32 bits of command buffer PA. */
1456	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighRd);
1457	*pu32 = pThis->svga.u32RegCommandHigh;
1458	break;
1459
1460	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
1461	/* Max primary (screen) memory. */
1462	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxPrimBBMemRd);
1463	pu32 = pThis->vram_size; /* @todo Maybe half VRAM? */
1464	break;
1465
1466	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
1467	/* Suggested limit on mob mem (i.e. size of the guest mapped VRAM in KB) */
1468	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGBMemSizeRd);
1469	*pu32 = pThis->vram_size / 1024;
1470	break;
1471
1472	case SVGA_REG_DEV_CAP:
1473	/* Write dev cap index, read value */
1474	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapRd);
1475	if (pThis->svga.u32DevCapIndex < RT_ELEMENTS(pThis->svga.au32DevCaps))
1476	{
1477	RT_UNTRUSTED_VALIDATED_FENCE();
1478	*pu32 = pThis->svga.au32DevCaps[pThis->svga.u32DevCapIndex];
1479	}
1480	else
1481	*pu32 = 0;
1482	break;
1483
1484	case SVGA_REG_CMD_PREPEND_LOW:
1485	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowRd);
1486	pu32 = 0; / Not supported. */
1487	break;
1488
1489	case SVGA_REG_CMD_PREPEND_HIGH:
1490	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighRd);
1491	pu32 = 0; / Not supported. */
1492	break;
1493
1494	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
1495	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxWidthRd);
1496	*pu32 = pThis->svga.u32MaxWidth;
1497	break;
1498
1499	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
1500	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxHeightRd);
1501	*pu32 = pThis->svga.u32MaxHeight;
1502	break;
1503
1504	case SVGA_REG_MOB_MAX_SIZE:
1505	/* Essentially the max texture size */
1506	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMobMaxSizeRd);
1507	pu32 = _128M; /* @todo Some actual value. Probably the mapped VRAM size. */
1508	break;
1509
1510	default:
1511	{
1512	uint32_t offReg;
1513	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1514	{
1515	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1516	RT_UNTRUSTED_VALIDATED_FENCE();
1517	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1518	}
1519	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1520	{
1521	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1522	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1523	RT_UNTRUSTED_VALIDATED_FENCE();
1524	uint32_t u32 = pThis->last_palette[offReg / 3];
1525	switch (offReg % 3)
1526	{
1527	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1528	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1529	case 2: pu32 = u32 & 0xff; break; / blue */
1530	}
1531	}
1532	else
1533	{
1534	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1535	rc = VINF_IOM_R3_IOPORT_READ;
1536	#else
1537	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1538
1539	/* Do not assert. The guest might be reading all registers. */
1540	LogFunc(("Unknown reg=%#x\n", idxReg));
1541	#endif
1542	}
1543	break;
1544	}
1545	}
1546	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1547	return rc;
1548	}
1549
1550	#ifdef IN_RING3
1551	/**
1552	* Apply the current resolution settings to change the video mode.
1553	*
1554	* @returns VBox status code.
1555	* @param pThis The shared VGA state.
1556	* @param pThisCC The ring-3 VGA state.
1557	*/
1558	int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1559	{
1560	/* Always do changemode on FIFO thread. */
1561	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1562
1563	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1564
1565	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1566
1567	if (pThis->svga.fGFBRegisters)
1568	{
1569	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1570	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1571	* deletes all screens other than screen #0, and redefines screen
1572	* #0 according to the specified mode. Drivers that use
1573	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1574	*/
1575
1576	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1577	pScreen->fDefined = true;
1578	pScreen->fModified = true;
1579	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1580	pScreen->idScreen = 0;
1581	pScreen->xOrigin = 0;
1582	pScreen->yOrigin = 0;
1583	pScreen->offVRAM = 0;
1584	pScreen->cbPitch = pThis->svga.cbScanline;
1585	pScreen->cWidth = pThis->svga.uWidth;
1586	pScreen->cHeight = pThis->svga.uHeight;
1587	pScreen->cBpp = pThis->svga.uBpp;
1588
1589	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1590	{
1591	/* Delete screen. */
1592	pScreen = &pSVGAState->aScreens[iScreen];
1593	if (pScreen->fDefined)
1594	{
1595	pScreen->fModified = true;
1596	pScreen->fDefined = false;
1597	}
1598	}
1599	}
1600	else
1601	{
1602	/* "If Screen Objects are supported, they can be used to fully
1603	* replace the functionality provided by the framebuffer registers
1604	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1605	*/
1606	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1607	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1608	pThis->svga.uBpp = pThis->svga.uHostBpp;
1609	}
1610
1611	vmsvgaR3VBVAResize(pThis, pThisCC);
1612
1613	/* Last stuff. For the VGA device screenshot. */
1614	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1615	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1616	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1617	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1618	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1619
1620	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1621	if ( pThis->svga.viewport.cx == 0
1622	&& pThis->svga.viewport.cy == 0)
1623	{
1624	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1625	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1626	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1627	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1628	pThis->svga.viewport.yLowWC = 0;
1629	}
1630
1631	return VINF_SUCCESS;
1632	}
1633
1634	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1635	{
1636	VBVACMDHDR cmd;
1637	cmd.x = (int16_t)(pScreen->xOrigin + x);
1638	cmd.y = (int16_t)(pScreen->yOrigin + y);
1639	cmd.w = (uint16_t)w;
1640	cmd.h = (uint16_t)h;
1641
1642	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1643	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1644	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1645	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1646
1647	return VINF_SUCCESS;
1648	}
1649
1650	#endif /* IN_RING3 */
1651	#if defined(IN_RING0) \|\| defined(IN_RING3)
1652
1653	/**
1654	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1655	*
1656	* @param pThis The shared VGA/VMSVGA instance data.
1657	* @param pThisCC The VGA/VMSVGA state for the current context.
1658	* @param fState The busy state.
1659	*/
1660	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1661	{
1662	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1663
1664	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1665	{
1666	/* Race / unfortunately scheduling. Highly unlikly. */
1667	uint32_t cLoops = 64;
1668	do
1669	{
1670	ASMNopPause();
1671	fState = (pThis->svga.fBusy != 0);
1672	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1673	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1674	}
1675	}
1676
1677
1678	/**
1679	* Update the scanline pitch in response to the guest changing mode
1680	* width/bpp.
1681	*
1682	* @param pThis The shared VGA/VMSVGA state.
1683	* @param pThisCC The VGA/VMSVGA state for the current context.
1684	*/
1685	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1686	{
1687	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1688	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1689	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1690	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1691
1692	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1693	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1694	* location but it has a different meaning.
1695	*/
1696	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1697	uFifoPitchLock = 0;
1698
1699	/* Sanitize values. */
1700	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1701	uFifoPitchLock = 0;
1702	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1703	uRegPitchLock = 0;
1704
1705	/* Prefer the register value to the FIFO value.*/
1706	if (uRegPitchLock)
1707	pThis->svga.cbScanline = uRegPitchLock;
1708	else if (uFifoPitchLock)
1709	pThis->svga.cbScanline = uFifoPitchLock;
1710	else
1711	pThis->svga.cbScanline = (uint32_t)pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1712
1713	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1714	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1715	}
1716
1717	#endif /* IN_RING0 \|\| IN_RING3 */
1718
1719	#ifdef IN_RING3
1720
1721	/**
1722	* Sends cursor position and visibility information from legacy
1723	* SVGA registers to the front-end.
1724	*/
1725	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1726	{
1727	/*
1728	* Writing the X/Y/ID registers does not trigger changes; only writing the
1729	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1730	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1731	* register if they don't have to.
1732	*/
1733	uint32_t x, y, idScreen;
1734	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1735
1736	x = pThis->svga.uCursorX;
1737	y = pThis->svga.uCursorY;
1738	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1739
1740	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1741	* were extended as follows:
1742	*
1743	* SVGA_CURSOR_ON_HIDE 0
1744	* SVGA_CURSOR_ON_SHOW 1
1745	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1746	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1747	*
1748	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1749	* distinguish between the non-zero values but still remember them.
1750	*/
1751	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1752	{
1753	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1754	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1755	}
1756	pThis->svga.uCursorOn = uCursorOn;
1757	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1758	}
1759
1760	#endif /* IN_RING3 */
1761
1762
1763	/**
1764	* Write port register
1765	*
1766	* @returns Strict VBox status code.
1767	* @param pDevIns The device instance.
1768	* @param pThis The shared VGA/VMSVGA state.
1769	* @param pThisCC The VGA/VMSVGA state for the current context.
1770	* @param u32 Value to write
1771	*/
1772	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1773	{
1774	#ifdef IN_RING3
1775	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1776	#endif
1777	VBOXSTRICTRC rc = VINF_SUCCESS;
1778	RT_NOREF(pThisCC);
1779
1780	/* Rough index register validation. */
1781	uint32_t idxReg = pThis->svga.u32IndexReg;
1782	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1783	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1784	VINF_IOM_R3_IOPORT_WRITE);
1785	#else
1786	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1787	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1788	VINF_SUCCESS);
1789	#endif
1790	RT_UNTRUSTED_VALIDATED_FENCE();
1791
1792	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1793	if ( idxReg >= SVGA_REG_ID_0_TOP
1794	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1795	{
1796	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1797	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1798	}
1799	#ifdef LOG_ENABLED
1800	if (idxReg != SVGA_REG_DEV_CAP)
1801	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1802	else
1803	Log(("vmsvgaWritePort index=%s (%d) val=%s (%d)\n", vmsvgaIndexToString(pThis, idxReg), idxReg, vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)u32), u32));
1804	#endif
1805	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1806	switch (idxReg)
1807	{
1808	case SVGA_REG_WIDTH:
1809	case SVGA_REG_HEIGHT:
1810	case SVGA_REG_PITCHLOCK:
1811	case SVGA_REG_BITS_PER_PIXEL:
1812	pThis->svga.fGFBRegisters = true;
1813	break;
1814	default:
1815	break;
1816	}
1817
1818	switch (idxReg)
1819	{
1820	case SVGA_REG_ID:
1821	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1822	if ( u32 == SVGA_ID_0
1823	\|\| u32 == SVGA_ID_1
1824	\|\| u32 == SVGA_ID_2)
1825	pThis->svga.u32SVGAId = u32;
1826	else
1827	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1828	break;
1829
1830	case SVGA_REG_ENABLE:
1831	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1832	#ifdef IN_RING3
1833	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1834	&& pThis->svga.fEnabled == false)
1835	{
1836	/* Make a backup copy of the first 512kb in order to save font data etc. */
1837	/** @todo should probably swap here, rather than copy + zero */
1838	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1839	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1840	}
1841
1842	pThis->svga.fEnabled = u32;
1843	if (pThis->svga.fEnabled)
1844	{
1845	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1846	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1847	{
1848	/* Keep the current mode. */
1849	pThis->svga.uWidth = pThisCC->pDrv->cx;
1850	pThis->svga.uHeight = pThisCC->pDrv->cy;
1851	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1852	vmsvgaHCUpdatePitch(pThis, pThisCC);
1853	}
1854
1855	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1856	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1857	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1858	# ifdef LOG_ENABLED
1859	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1860	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1861	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1862	# endif
1863
1864	/* Disable or enable dirty page tracking according to the current fTraces value. */
1865	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1866
1867	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1868	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1869	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1870
1871	/* Make the cursor visible again as needed. */
1872	if (pSVGAState->Cursor.fActive)
1873	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, false, 0, 0, 0, 0, NULL);
1874	}
1875	else
1876	{
1877	/* Make sure the cursor is off. */
1878	if (pSVGAState->Cursor.fActive)
1879	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /fVisible/, false, 0, 0, 0, 0, NULL);
1880
1881	/* Restore the text mode backup. */
1882	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1883
1884	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1885
1886	/* Enable dirty page tracking again when going into legacy mode. */
1887	vmsvgaR3SetTraces(pDevIns, pThis, true);
1888
1889	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1890	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1891	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1892
1893	/* Clear the pitch lock. */
1894	pThis->svga.u32PitchLock = 0;
1895	}
1896	#else /* !IN_RING3 */
1897	rc = VINF_IOM_R3_IOPORT_WRITE;
1898	#endif /* !IN_RING3 */
1899	break;
1900
1901	case SVGA_REG_WIDTH:
1902	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1903	if (u32 != pThis->svga.uWidth)
1904	{
1905	if (u32 <= pThis->svga.u32MaxWidth)
1906	{
1907	#if defined(IN_RING3) \|\| defined(IN_RING0)
1908	pThis->svga.uWidth = u32;
1909	vmsvgaHCUpdatePitch(pThis, pThisCC);
1910	if (pThis->svga.fEnabled)
1911	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1912	#else
1913	rc = VINF_IOM_R3_IOPORT_WRITE;
1914	#endif
1915	}
1916	else
1917	Log(("SVGA_REG_WIDTH: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxWidth));
1918	}
1919	/* else: nop */
1920	break;
1921
1922	case SVGA_REG_HEIGHT:
1923	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1924	if (u32 != pThis->svga.uHeight)
1925	{
1926	if (u32 <= pThis->svga.u32MaxHeight)
1927	{
1928	pThis->svga.uHeight = u32;
1929	if (pThis->svga.fEnabled)
1930	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1931	}
1932	else
1933	Log(("SVGA_REG_HEIGHT: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxHeight));
1934	}
1935	/* else: nop */
1936	break;
1937
1938	case SVGA_REG_DEPTH:
1939	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1940	/** @todo read-only?? */
1941	break;
1942
1943	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1944	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1945	if (pThis->svga.uBpp != u32)
1946	{
1947	if (u32 <= 32)
1948	{
1949	#if defined(IN_RING3) \|\| defined(IN_RING0)
1950	pThis->svga.uBpp = u32;
1951	vmsvgaHCUpdatePitch(pThis, pThisCC);
1952	if (pThis->svga.fEnabled)
1953	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1954	#else
1955	rc = VINF_IOM_R3_IOPORT_WRITE;
1956	#endif
1957	}
1958	else
1959	Log(("SVGA_REG_BITS_PER_PIXEL: New value is out of bounds: %u, max 32\n", u32));
1960	}
1961	/* else: nop */
1962	break;
1963
1964	case SVGA_REG_PSEUDOCOLOR:
1965	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1966	break;
1967
1968	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1969	#ifdef IN_RING3
1970	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1971	pThis->svga.fConfigured = u32;
1972	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1973	if (!pThis->svga.fConfigured)
1974	pThis->svga.fTraces = true;
1975	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1976	#else
1977	rc = VINF_IOM_R3_IOPORT_WRITE;
1978	#endif
1979	break;
1980
1981	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1982	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1983	if ( pThis->svga.fEnabled
1984	&& pThis->svga.fConfigured)
1985	{
1986	#if defined(IN_RING3) \|\| defined(IN_RING0)
1987	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1988	/*
1989	* The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
1990	* at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
1991	*/
1992	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1993	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1994	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1995
1996	/* Kick the FIFO thread to start processing commands again. */
1997	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1998	#else
1999	rc = VINF_IOM_R3_IOPORT_WRITE;
2000	#endif
2001	}
2002	/* else nothing to do. */
2003	else
2004	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
2005
2006	break;
2007
2008	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
2009	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
2010	break;
2011
2012	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
2013	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
2014	pThis->svga.u32GuestId = u32;
2015	break;
2016
2017	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
2018	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
2019	pThis->svga.u32PitchLock = u32;
2020	/* Should this also update the FIFO pitch lock? Unclear. */
2021	break;
2022
2023	case SVGA_REG_IRQMASK: /* Interrupt mask */
2024	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
2025	pThis->svga.u32IrqMask = u32;
2026
2027	/* Irq pending after the above change? */
2028	if (pThis->svga.u32IrqStatus & u32)
2029	{
2030	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
2031	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
2032	}
2033	else
2034	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2035	break;
2036
2037	/* Mouse cursor support */
2038	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
2039	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
2040	pThis->svga.uCursorID = u32;
2041	break;
2042
2043	case SVGA_REG_CURSOR_X:
2044	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
2045	pThis->svga.uCursorX = u32;
2046	break;
2047
2048	case SVGA_REG_CURSOR_Y:
2049	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
2050	pThis->svga.uCursorY = u32;
2051	break;
2052
2053	case SVGA_REG_CURSOR_ON:
2054	#ifdef IN_RING3
2055	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
2056	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
2057	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
2058	#else
2059	rc = VINF_IOM_R3_IOPORT_WRITE;
2060	#endif
2061	break;
2062
2063	/* Legacy multi-monitor support */
2064	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
2065	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
2066	break;
2067	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
2068	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
2069	break;
2070	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
2071	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
2072	break;
2073	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
2074	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
2075	break;
2076	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
2077	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
2078	break;
2079	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
2080	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
2081	break;
2082	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
2083	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
2084	break;
2085	#ifdef VBOX_WITH_VMSVGA3D
2086	/* See "Guest memory regions" below. */
2087	case SVGA_REG_GMR_ID:
2088	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
2089	pThis->svga.u32CurrentGMRId = u32;
2090	break;
2091
2092	case SVGA_REG_GMR_DESCRIPTOR:
2093	# ifndef IN_RING3
2094	rc = VINF_IOM_R3_IOPORT_WRITE;
2095	break;
2096	# else /* IN_RING3 */
2097	{
2098	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
2099
2100	/* Validate current GMR id. */
2101	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
2102	AssertBreak(idGMR < pThis->svga.cGMR);
2103	RT_UNTRUSTED_VALIDATED_FENCE();
2104
2105	/* Free the old GMR if present. */
2106	vmsvgaR3GmrFree(pThisCC, idGMR);
2107
2108	/* Just undefine the GMR? */
2109	RTGCPHYS GCPhys = (RTGCPHYS)u32 << GUEST_PAGE_SHIFT;
2110	if (GCPhys == 0)
2111	{
2112	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
2113	break;
2114	}
2115
2116
2117	/* Never cross a page boundary automatically. */
2118	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
2119	uint32_t cPagesTotal = 0;
2120	uint32_t iDesc = 0;
2121	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2122	uint32_t cLoops = 0;
2123	RTGCPHYS GCPhysBase = GCPhys;
2124	while ((GCPhys >> GUEST_PAGE_SHIFT) == (GCPhysBase >> GUEST_PAGE_SHIFT))
2125	{
2126	/* Read descriptor. */
2127	SVGAGuestMemDescriptor desc;
2128	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2129	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2130
2131	if (desc.numPages != 0)
2132	{
2133	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2134	cPagesTotal += desc.numPages;
2135	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2136
2137	if ((iDesc & 15) == 0)
2138	{
2139	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
2140	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2141	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2142	}
2143
2144	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << GUEST_PAGE_SHIFT;
2145	paDescs[iDesc++].numPages = desc.numPages;
2146
2147	/* Continue with the next descriptor. */
2148	GCPhys += sizeof(desc);
2149	}
2150	else if (desc.ppn == 0)
2151	break; /* terminator */
2152	else /* Pointer to the next physical page of descriptors. */
2153	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << GUEST_PAGE_SHIFT;
2154
2155	cLoops++;
2156	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2157	}
2158
2159	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2160	if (RT_SUCCESS(rc))
2161	{
2162	/* Commit the GMR. */
2163	pSVGAState->paGMR[idGMR].paDesc = paDescs;
2164	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2165	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2166	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * GUEST_PAGE_SIZE;
2167	Assert((pSVGAState->paGMR[idGMR].cbTotal >> GUEST_PAGE_SHIFT) == cPagesTotal);
2168	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2169	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2170	}
2171	else
2172	{
2173	RTMemFree(paDescs);
2174	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2175	}
2176	break;
2177	}
2178	# endif /* IN_RING3 */
2179	#endif // VBOX_WITH_VMSVGA3D
2180
2181	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2182	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2183	if (pThis->svga.fTraces == u32)
2184	break; /* nothing to do */
2185
2186	#ifdef IN_RING3
2187	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2188	#else
2189	rc = VINF_IOM_R3_IOPORT_WRITE;
2190	#endif
2191	break;
2192
2193	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2194	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2195	break;
2196
2197	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2198	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2199	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2200	break;
2201
2202	/*
2203	* SVGA_CAP_GBOBJECTS+ registers.
2204	*/
2205	case SVGA_REG_COMMAND_LOW:
2206	{
2207	/* Lower 32 bits of command buffer physical address and submit the command buffer. */
2208	#ifdef IN_RING3
2209	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowWr);
2210	pThis->svga.u32RegCommandLow = u32;
2211
2212	/* "lower 6 bits are used for the SVGACBContext" */
2213	RTGCPHYS GCPhysCB = pThis->svga.u32RegCommandHigh;
2214	GCPhysCB <<= 32;
2215	GCPhysCB \|= pThis->svga.u32RegCommandLow & ~SVGA_CB_CONTEXT_MASK;
2216	SVGACBContext const CBCtx = (SVGACBContext)(pThis->svga.u32RegCommandLow & SVGA_CB_CONTEXT_MASK);
2217	vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, GCPhysCB, CBCtx);
2218	#else
2219	rc = VINF_IOM_R3_IOPORT_WRITE;
2220	#endif
2221	break;
2222	}
2223
2224	case SVGA_REG_COMMAND_HIGH:
2225	/* Upper 32 bits of command buffer PA. */
2226	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighWr);
2227	pThis->svga.u32RegCommandHigh = u32;
2228	break;
2229
2230	case SVGA_REG_DEV_CAP:
2231	/* Write dev cap index, read value */
2232	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapWr);
2233	pThis->svga.u32DevCapIndex = u32;
2234	break;
2235
2236	case SVGA_REG_CMD_PREPEND_LOW:
2237	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowWr);
2238	/* Not supported. */
2239	break;
2240
2241	case SVGA_REG_CMD_PREPEND_HIGH:
2242	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighWr);
2243	/* Not supported. */
2244	break;
2245
2246	case SVGA_REG_FB_START:
2247	case SVGA_REG_MEM_START:
2248	case SVGA_REG_HOST_BITS_PER_PIXEL:
2249	case SVGA_REG_MAX_WIDTH:
2250	case SVGA_REG_MAX_HEIGHT:
2251	case SVGA_REG_VRAM_SIZE:
2252	case SVGA_REG_FB_SIZE:
2253	case SVGA_REG_CAPABILITIES:
2254	case SVGA_REG_MEM_SIZE:
2255	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2256	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2257	case SVGA_REG_BYTES_PER_LINE:
2258	case SVGA_REG_FB_OFFSET:
2259	case SVGA_REG_RED_MASK:
2260	case SVGA_REG_GREEN_MASK:
2261	case SVGA_REG_BLUE_MASK:
2262	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2263	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2264	case SVGA_REG_GMR_MAX_IDS:
2265	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2266	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
2267	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
2268	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
2269	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
2270	case SVGA_REG_MOB_MAX_SIZE:
2271	/* Read only - ignore. */
2272	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2273	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2274	break;
2275
2276	default:
2277	{
2278	uint32_t offReg;
2279	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2280	{
2281	RT_UNTRUSTED_VALIDATED_FENCE();
2282	pThis->svga.au32ScratchRegion[offReg] = u32;
2283	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2284	}
2285	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2286	{
2287	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2288	Btw, see rgb_to_pixel32. */
2289	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2290	u32 &= 0xff;
2291	RT_UNTRUSTED_VALIDATED_FENCE();
2292	uint32_t uRgb = pThis->last_palette[offReg / 3];
2293	switch (offReg % 3)
2294	{
2295	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2296	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2297	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2298	}
2299	pThis->last_palette[offReg / 3] = uRgb;
2300	}
2301	else
2302	{
2303	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2304	rc = VINF_IOM_R3_IOPORT_WRITE;
2305	#else
2306	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2307	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2308	#endif
2309	}
2310	break;
2311	}
2312	}
2313	return rc;
2314	}
2315
2316	/**
2317	* @callback_method_impl{FNIOMIOPORTNEWIN}
2318	*/
2319	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2320	{
2321	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2322	RT_NOREF_PV(pvUser);
2323
2324	/* Only dword accesses. */
2325	if (cb == 4)
2326	{
2327	switch (offPort)
2328	{
2329	case SVGA_INDEX_PORT:
2330	*pu32 = pThis->svga.u32IndexReg;
2331	break;
2332
2333	case SVGA_VALUE_PORT:
2334	return vmsvgaReadPort(pDevIns, pThis, pu32);
2335
2336	case SVGA_BIOS_PORT:
2337	Log(("Ignoring BIOS port read\n"));
2338	*pu32 = 0;
2339	break;
2340
2341	case SVGA_IRQSTATUS_PORT:
2342	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2343	*pu32 = pThis->svga.u32IrqStatus;
2344	break;
2345
2346	default:
2347	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2348	*pu32 = UINT32_MAX;
2349	break;
2350	}
2351	}
2352	else
2353	{
2354	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2355	*pu32 = UINT32_MAX;
2356	}
2357	return VINF_SUCCESS;
2358	}
2359
2360	/**
2361	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2362	*/
2363	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2364	{
2365	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2366	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2367	RT_NOREF_PV(pvUser);
2368
2369	/* Only dword accesses. */
2370	if (cb == 4)
2371	switch (offPort)
2372	{
2373	case SVGA_INDEX_PORT:
2374	pThis->svga.u32IndexReg = u32;
2375	break;
2376
2377	case SVGA_VALUE_PORT:
2378	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2379
2380	case SVGA_BIOS_PORT:
2381	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2382	break;
2383
2384	case SVGA_IRQSTATUS_PORT:
2385	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2386	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2387	/* Clear the irq in case all events have been cleared. */
2388	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2389	{
2390	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2391	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2392	}
2393	break;
2394
2395	default:
2396	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2397	break;
2398	}
2399	else
2400	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2401
2402	return VINF_SUCCESS;
2403	}
2404
2405	#ifdef IN_RING3
2406
2407	# ifdef DEBUG_FIFO_ACCESS
2408	/**
2409	* Handle FIFO memory access.
2410	* @returns VBox status code.
2411	* @param pVM VM handle.
2412	* @param pThis The shared VGA/VMSVGA instance data.
2413	* @param GCPhys The access physical address.
2414	* @param fWriteAccess Read or write access
2415	*/
2416	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2417	{
2418	RT_NOREF(pVM);
2419	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2420	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2421
2422	switch (GCPhysOffset >> 2)
2423	{
2424	case SVGA_FIFO_MIN:
2425	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2426	break;
2427	case SVGA_FIFO_MAX:
2428	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2429	break;
2430	case SVGA_FIFO_NEXT_CMD:
2431	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2432	break;
2433	case SVGA_FIFO_STOP:
2434	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2435	break;
2436	case SVGA_FIFO_CAPABILITIES:
2437	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2438	break;
2439	case SVGA_FIFO_FLAGS:
2440	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2441	break;
2442	case SVGA_FIFO_FENCE:
2443	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2444	break;
2445	case SVGA_FIFO_3D_HWVERSION:
2446	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2447	break;
2448	case SVGA_FIFO_PITCHLOCK:
2449	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2450	break;
2451	case SVGA_FIFO_CURSOR_ON:
2452	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2453	break;
2454	case SVGA_FIFO_CURSOR_X:
2455	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2456	break;
2457	case SVGA_FIFO_CURSOR_Y:
2458	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2459	break;
2460	case SVGA_FIFO_CURSOR_COUNT:
2461	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2462	break;
2463	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2464	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2465	break;
2466	case SVGA_FIFO_RESERVED:
2467	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2468	break;
2469	case SVGA_FIFO_CURSOR_SCREEN_ID:
2470	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2471	break;
2472	case SVGA_FIFO_DEAD:
2473	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2474	break;
2475	case SVGA_FIFO_3D_HWVERSION_REVISED:
2476	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2477	break;
2478	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2479	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2480	break;
2481	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2482	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2483	break;
2484	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2485	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2486	break;
2487	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2488	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2489	break;
2490	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2491	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2492	break;
2493	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2494	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2495	break;
2496	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2497	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2498	break;
2499	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2500	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2501	break;
2502	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2503	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2504	break;
2505	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2506	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2507	break;
2508	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2509	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2510	break;
2511	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2512	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2513	break;
2514	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2515	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2516	break;
2517	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2518	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2519	break;
2520	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2521	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2522	break;
2523	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2524	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2525	break;
2526	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2527	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2528	break;
2529	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2530	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2531	break;
2532	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2533	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2534	break;
2535	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2536	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2537	break;
2538	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2539	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2540	break;
2541	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2542	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2543	break;
2544	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2545	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2546	break;
2547	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2548	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2549	break;
2550	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2551	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2552	break;
2553	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2554	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2555	break;
2556	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2557	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2558	break;
2559	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2560	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2561	break;
2562	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2563	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2564	break;
2565	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2566	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2567	break;
2568	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2569	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2570	break;
2571	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2572	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2573	break;
2574	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2575	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2576	break;
2577	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2578	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2579	break;
2580	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2581	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2582	break;
2583	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2584	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2585	break;
2586	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2587	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2588	break;
2589	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2590	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2591	break;
2592	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2593	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2594	break;
2595	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2596	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2597	break;
2598	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2599	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2600	break;
2601	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2602	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2603	break;
2604	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2605	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2606	break;
2607	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2608	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2609	break;
2610	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2611	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2612	break;
2613	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2614	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2615	break;
2616	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2617	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2618	break;
2619	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2620	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2621	break;
2622	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2623	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2624	break;
2625	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2626	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2627	break;
2628	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2629	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2630	break;
2631	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2632	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2633	break;
2634	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2635	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2636	break;
2637	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2638	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2639	break;
2640	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2641	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2642	break;
2643	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2644	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2645	break;
2646	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2647	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2648	break;
2649	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2650	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2651	break;
2652	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2653	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2654	break;
2655	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2656	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2657	break;
2658	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2659	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2660	break;
2661	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2662	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2663	break;
2664	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2665	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2666	break;
2667	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2668	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2669	break;
2670	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2671	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2672	break;
2673	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2674	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2675	break;
2676	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2677	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2678	break;
2679	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2680	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2681	break;
2682	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2683	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2684	break;
2685	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD4: /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
2686	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD4 (SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2687	break;
2688	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD5: /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
2689	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD5 (SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2690	break;
2691	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD7: /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
2692	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD7 (SVGA3D_DEVCAP_ALPHATOCOVERAGE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2693	break;
2694	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD6: /* SVGA3D_DEVCAP_SUPERSAMPLE */
2695	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD6 (SVGA3D_DEVCAP_SUPERSAMPLE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2696	break;
2697	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2698	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2699	break;
2700	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2701	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2702	break;
2703	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
2704	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD10 (SVGA3D_DEVCAP_SURFACEFMT_AYUV) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2705	break;
2706	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2707	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2708	break;
2709	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2710	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2711	break;
2712	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2713	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2714	break;
2715	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2716	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2717	break;
2718	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2719	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2720	break;
2721	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI1:
2722	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2723	break;
2724	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI2:
2725	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2726	break;
2727	case SVGA_FIFO_3D_CAPS_LAST:
2728	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2729	break;
2730	case SVGA_FIFO_GUEST_3D_HWVERSION:
2731	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2732	break;
2733	case SVGA_FIFO_FENCE_GOAL:
2734	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2735	break;
2736	case SVGA_FIFO_BUSY:
2737	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2738	break;
2739	default:
2740	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2741	break;
2742	}
2743
2744	return VINF_EM_RAW_EMULATE_INSTR;
2745	}
2746	# endif /* DEBUG_FIFO_ACCESS */
2747
2748	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2749	/**
2750	* HC access handler for the FIFO.
2751	*
2752	* @returns VINF_SUCCESS if the handler have carried out the operation.
2753	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2754	* @param pVM VM Handle.
2755	* @param pVCpu The cross context CPU structure for the calling EMT.
2756	* @param GCPhys The physical address the guest is writing to.
2757	* @param pvPhys The HC mapping of that address.
2758	* @param pvBuf What the guest is reading/writing.
2759	* @param cbBuf How much it's reading/writing.
2760	* @param enmAccessType The access type.
2761	* @param enmOrigin Who is making the access.
2762	* @param pvUser User argument.
2763	*/
2764	static DECLCALLBACK(VBOXSTRICTRC)
2765	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2766	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2767	{
2768	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2769	PVGASTATE pThis = (PVGASTATE)pvUser;
2770	AssertPtr(pThis);
2771
2772	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2773	/*
2774	* Wake up the FIFO thread as it might have work to do now.
2775	*/
2776	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2777	AssertLogRelRC(rc);
2778	# endif
2779
2780	# ifdef DEBUG_FIFO_ACCESS
2781	/*
2782	* When in debug-fifo-access mode, we do not disable the access handler,
2783	* but leave it on as we wish to catch all access.
2784	*/
2785	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2786	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2787	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2788	/*
2789	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2790	*/
2791	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2792	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2793	# endif
2794	if (RT_SUCCESS(rc))
2795	return VINF_PGM_HANDLER_DO_DEFAULT;
2796	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2797	return rc;
2798	}
2799	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2800
2801	#endif /* IN_RING3 */
2802
2803	#ifdef DEBUG_GMR_ACCESS
2804	# ifdef IN_RING3
2805
2806	/**
2807	* HC access handler for GMRs.
2808	*
2809	* @returns VINF_SUCCESS if the handler have carried out the operation.
2810	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2811	* @param pVM VM Handle.
2812	* @param pVCpu The cross context CPU structure for the calling EMT.
2813	* @param GCPhys The physical address the guest is writing to.
2814	* @param pvPhys The HC mapping of that address.
2815	* @param pvBuf What the guest is reading/writing.
2816	* @param cbBuf How much it's reading/writing.
2817	* @param enmAccessType The access type.
2818	* @param enmOrigin Who is making the access.
2819	* @param pvUser User argument.
2820	*/
2821	static DECLCALLBACK(VBOXSTRICTRC)
2822	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2823	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2824	{
2825	PVGASTATE pThis = (PVGASTATE)pvUser;
2826	Assert(pThis);
2827	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2828	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2829
2830	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2831
2832	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2833	{
2834	PGMR pGMR = &pSVGAState->paGMR[i];
2835
2836	if (pGMR->numDescriptors)
2837	{
2838	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2839	{
2840	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2841	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * GUEST_PAGE_SIZE)
2842	{
2843	/*
2844	* Turn off the write handler for this particular page and make it R/W.
2845	* Then return telling the caller to restart the guest instruction.
2846	*/
2847	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2848	AssertRC(rc);
2849	return VINF_PGM_HANDLER_DO_DEFAULT;
2850	}
2851	}
2852	}
2853	}
2854
2855	return VINF_PGM_HANDLER_DO_DEFAULT;
2856	}
2857
2858	/** Callback handler for VMR3ReqCallWaitU */
2859	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2860	{
2861	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2862	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2863	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2864	int rc;
2865
2866	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2867	{
2868	rc = PDMDevHlpPGMHandlerPhysicalRegister(pDevIns, pGMR->paDesc[i].GCPhys,
2869	pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * GUEST_PAGE_SIZE - 1,
2870	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2871	AssertRC(rc);
2872	}
2873	return VINF_SUCCESS;
2874	}
2875
2876	/** Callback handler for VMR3ReqCallWaitU */
2877	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2878	{
2879	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2880	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2881	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2882
2883	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2884	{
2885	int rc = PDMDevHlpPGMHandlerPhysicalDeregister(pDevIns, pGMR->paDesc[i].GCPhys);
2886	AssertRC(rc);
2887	}
2888	return VINF_SUCCESS;
2889	}
2890
2891	/** Callback handler for VMR3ReqCallWaitU */
2892	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2893	{
2894	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2895
2896	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2897	{
2898	PGMR pGMR = &pSVGAState->paGMR[i];
2899
2900	if (pGMR->numDescriptors)
2901	{
2902	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2903	{
2904	int rc = PDMDevHlpPGMHandlerPhysicalReset(pDevIns, pGMR->paDesc[j].GCPhys);
2905	AssertRC(rc);
2906	}
2907	}
2908	}
2909	return VINF_SUCCESS;
2910	}
2911
2912	# endif /* IN_RING3 */
2913	#endif /* DEBUG_GMR_ACCESS */
2914
2915	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2916
2917	#ifdef IN_RING3
2918
2919
2920	/*
2921	*
2922	* Command buffer submission.
2923	*
2924	* Guest submits a buffer by writing to SVGA_REG_COMMAND_LOW register.
2925	*
2926	* EMT thread appends a command buffer to the context queue (VMSVGACMDBUFCTX::listSubmitted)
2927	* and wakes up the FIFO thread.
2928	*
2929	* FIFO thread fetches the command buffer from the queue, processes the commands and writes
2930	* the buffer header back to the guest memory.
2931	*
2932	* If buffers are preempted, then the EMT thread removes all buffers from the context queue.
2933	*
2934	*/
2935
2936
2937	/** Update a command buffer header 'status' and 'errorOffset' fields in the guest memory.
2938	*
2939	* @param pDevIns The device instance.
2940	* @param GCPhysCB Guest physical address of the command buffer header.
2941	* @param status Command buffer status (SVGA_CB_STATUS_*).
2942	* @param errorOffset Offset to the first byte of the failing command for SVGA_CB_STATUS_COMMAND_ERROR.
2943	* errorOffset is ignored if the status is not SVGA_CB_STATUS_COMMAND_ERROR.
2944	* @thread FIFO or EMT.
2945	*/
2946	static void vmsvgaR3CmdBufWriteStatus(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCB, SVGACBStatus status, uint32_t errorOffset)
2947	{
2948	SVGACBHeader hdr;
2949	hdr.status = status;
2950	hdr.errorOffset = errorOffset;
2951	AssertCompile( RT_OFFSETOF(SVGACBHeader, status) == 0
2952	&& RT_OFFSETOF(SVGACBHeader, errorOffset) == 4
2953	&& RT_OFFSETOF(SVGACBHeader, id) == 8);
2954	size_t const cbWrite = status == SVGA_CB_STATUS_COMMAND_ERROR
2955	? RT_UOFFSET_AFTER(SVGACBHeader, errorOffset) /* Both 'status' and 'errorOffset' fields. */
2956	: RT_UOFFSET_AFTER(SVGACBHeader, status); /* Only 'status' field. */
2957	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysCB, &hdr, cbWrite);
2958	}
2959
2960
2961	/** Raise an IRQ.
2962	*
2963	* @param pDevIns The device instance.
2964	* @param pThis The shared VGA/VMSVGA state.
2965	* @param u32IrqStatus SVGA_IRQFLAG_* bits.
2966	* @thread FIFO or EMT.
2967	*/
2968	static void vmsvgaR3CmdBufRaiseIRQ(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t u32IrqStatus)
2969	{
2970	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
2971	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
2972
2973	if (pThis->svga.u32IrqMask & u32IrqStatus)
2974	{
2975	LogFunc(("Trigger interrupt with status %#x\n", u32IrqStatus));
2976	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
2977	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
2978	}
2979
2980	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
2981	}
2982
2983
2984	/** Allocate a command buffer structure.
2985	*
2986	* @param pCmdBufCtx The command buffer context which must allocate the buffer.
2987	* @return Pointer to the allocated command buffer structure.
2988	*/
2989	static PVMSVGACMDBUF vmsvgaR3CmdBufAlloc(PVMSVGACMDBUFCTX pCmdBufCtx)
2990	{
2991	if (!pCmdBufCtx)
2992	return NULL;
2993
2994	PVMSVGACMDBUF pCmdBuf = (PVMSVGACMDBUF)RTMemAllocZ(sizeof(*pCmdBuf));
2995	if (pCmdBuf)
2996	{
2997	// RT_ZERO(pCmdBuf->nodeBuffer);
2998	pCmdBuf->pCmdBufCtx = pCmdBufCtx;
2999	// pCmdBuf->GCPhysCB = 0;
3000	// RT_ZERO(pCmdBuf->hdr);
3001	// pCmdBuf->pvCommands = NULL;
3002	}
3003
3004	return pCmdBuf;
3005	}
3006
3007
3008	/** Free a command buffer structure.
3009	*
3010	* @param pCmdBuf The command buffer pointer.
3011	*/
3012	static void vmsvgaR3CmdBufFree(PVMSVGACMDBUF pCmdBuf)
3013	{
3014	if (pCmdBuf)
3015	RTMemFree(pCmdBuf->pvCommands);
3016	RTMemFree(pCmdBuf);
3017	}
3018
3019
3020	/** Initialize a command buffer context.
3021	*
3022	* @param pCmdBufCtx The command buffer context.
3023	*/
3024	static void vmsvgaR3CmdBufCtxInit(PVMSVGACMDBUFCTX pCmdBufCtx)
3025	{
3026	RTListInit(&pCmdBufCtx->listSubmitted);
3027	pCmdBufCtx->cSubmitted = 0;
3028	}
3029
3030
3031	/** Destroy a command buffer context.
3032	*
3033	* @param pCmdBufCtx The command buffer context pointer.
3034	*/
3035	static void vmsvgaR3CmdBufCtxTerm(PVMSVGACMDBUFCTX pCmdBufCtx)
3036	{
3037	if (!pCmdBufCtx)
3038	return;
3039
3040	if (pCmdBufCtx->listSubmitted.pNext)
3041	{
3042	/* If the list has been initialized. */
3043	PVMSVGACMDBUF pIter, pNext;
3044	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3045	{
3046	RTListNodeRemove(&pIter->nodeBuffer);
3047	--pCmdBufCtx->cSubmitted;
3048	vmsvgaR3CmdBufFree(pIter);
3049	}
3050	}
3051	Assert(pCmdBufCtx->cSubmitted == 0);
3052	pCmdBufCtx->cSubmitted = 0;
3053	}
3054
3055
3056	/** Handles SVGA_DC_CMD_START_STOP_CONTEXT command.
3057	*
3058	* @param pSvgaR3State VMSVGA R3 state.
3059	* @param pCmd The command data.
3060	* @return SVGACBStatus code.
3061	* @thread EMT
3062	*/
3063	static SVGACBStatus vmsvgaR3CmdBufDCStartStop(PVMSVGAR3STATE pSvgaR3State, SVGADCCmdStartStop const *pCmd)
3064	{
3065	/* Create or destroy a regular command buffer context. */
3066	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3067	return SVGA_CB_STATUS_COMMAND_ERROR;
3068	RT_UNTRUSTED_VALIDATED_FENCE();
3069
3070	SVGACBStatus CBStatus = SVGA_CB_STATUS_COMPLETED;
3071
3072	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3073	AssertRC(rc);
3074	if (pCmd->enable)
3075	{
3076	pSvgaR3State->apCmdBufCtxs[pCmd->context] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
3077	if (pSvgaR3State->apCmdBufCtxs[pCmd->context])
3078	vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3079	else
3080	CBStatus = SVGA_CB_STATUS_QUEUE_FULL;
3081	}
3082	else
3083	{
3084	vmsvgaR3CmdBufCtxTerm(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3085	pSvgaR3State->apCmdBufCtxs[pCmd->context] = NULL;
3086	}
3087	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3088
3089	return CBStatus;
3090	}
3091
3092
3093	/** Handles SVGA_DC_CMD_PREEMPT command.
3094	*
3095	* @param pDevIns The device instance.
3096	* @param pSvgaR3State VMSVGA R3 state.
3097	* @param pCmd The command data.
3098	* @return SVGACBStatus code.
3099	* @thread EMT
3100	*/
3101	static SVGACBStatus vmsvgaR3CmdBufDCPreempt(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, SVGADCCmdPreempt const *pCmd)
3102	{
3103	/* Remove buffers from the processing queue of the specified context. */
3104	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3105	return SVGA_CB_STATUS_COMMAND_ERROR;
3106	RT_UNTRUSTED_VALIDATED_FENCE();
3107
3108	PVMSVGACMDBUFCTX const pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[pCmd->context];
3109	RTLISTANCHOR listPreempted;
3110
3111	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3112	AssertRC(rc);
3113	if (pCmd->ignoreIDZero)
3114	{
3115	RTListInit(&listPreempted);
3116
3117	PVMSVGACMDBUF pIter, pNext;
3118	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3119	{
3120	if (pIter->hdr.id == 0)
3121	continue;
3122
3123	RTListNodeRemove(&pIter->nodeBuffer);
3124	--pCmdBufCtx->cSubmitted;
3125	RTListAppend(&listPreempted, &pIter->nodeBuffer);
3126	}
3127	}
3128	else
3129	{
3130	RTListMove(&listPreempted, &pCmdBufCtx->listSubmitted);
3131	}
3132	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3133
3134	PVMSVGACMDBUF pIter, pNext;
3135	RTListForEachSafe(&listPreempted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3136	{
3137	RTListNodeRemove(&pIter->nodeBuffer);
3138	vmsvgaR3CmdBufWriteStatus(pDevIns, pIter->GCPhysCB, SVGA_CB_STATUS_PREEMPTED, 0);
3139	vmsvgaR3CmdBufFree(pIter);
3140	}
3141
3142	return SVGA_CB_STATUS_COMPLETED;
3143	}
3144
3145
3146	/** @def VMSVGA_INC_CMD_SIZE_BREAK
3147	* Increments the size of the command cbCmd by a_cbMore.
3148	* Checks that the command buffer has at least cbCmd bytes. Will break out of the switch if it doesn't.
3149	* Used by vmsvgaR3CmdBufProcessDC and vmsvgaR3CmdBufProcessCommands.
3150	*/
3151	#define VMSVGA_INC_CMD_SIZE_BREAK(a_cbMore) \
3152	if (1) { \
3153	cbCmd += (a_cbMore); \
3154	ASSERT_GUEST_MSG_STMT_BREAK(cbRemain >= cbCmd, ("size=%#x remain=%#zx\n", cbCmd, (size_t)cbRemain), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR); \
3155	RT_UNTRUSTED_VALIDATED_FENCE(); \
3156	} else do {} while (0)
3157
3158
3159	/** Processes Device Context command buffer.
3160	*
3161	* @param pDevIns The device instance.
3162	* @param pSvgaR3State VMSVGA R3 state.
3163	* @param pvCommands Pointer to the command buffer.
3164	* @param cbCommands Size of the command buffer.
3165	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3166	* @return SVGACBStatus code.
3167	* @thread EMT
3168	*/
3169	static SVGACBStatus vmsvgaR3CmdBufProcessDC(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd)
3170	{
3171	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3172
3173	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3174	uint32_t cbRemain = cbCommands;
3175	while (cbRemain)
3176	{
3177	/* Command identifier is a 32 bit value. */
3178	if (cbRemain < sizeof(uint32_t))
3179	{
3180	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3181	break;
3182	}
3183
3184	/* Fetch the command id. */
3185	uint32_t const cmdId = (uint32_t )pu8Cmd;
3186	uint32_t cbCmd = sizeof(uint32_t);
3187	switch (cmdId)
3188	{
3189	case SVGA_DC_CMD_NOP:
3190	{
3191	/* NOP */
3192	break;
3193	}
3194
3195	case SVGA_DC_CMD_START_STOP_CONTEXT:
3196	{
3197	SVGADCCmdStartStop pCmd = (SVGADCCmdStartStop )&pu8Cmd[cbCmd];
3198	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3199	CBstatus = vmsvgaR3CmdBufDCStartStop(pSvgaR3State, pCmd);
3200	break;
3201	}
3202
3203	case SVGA_DC_CMD_PREEMPT:
3204	{
3205	SVGADCCmdPreempt pCmd = (SVGADCCmdPreempt )&pu8Cmd[cbCmd];
3206	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3207	CBstatus = vmsvgaR3CmdBufDCPreempt(pDevIns, pSvgaR3State, pCmd);
3208	break;
3209	}
3210
3211	default:
3212	{
3213	/* Unsupported command. */
3214	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3215	break;
3216	}
3217	}
3218
3219	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3220	break;
3221
3222	pu8Cmd += cbCmd;
3223	cbRemain -= cbCmd;
3224	}
3225
3226	Assert(cbRemain <= cbCommands);
3227	*poffNextCmd = cbCommands - cbRemain;
3228	return CBstatus;
3229	}
3230
3231
3232	/** Submits a device context command buffer for synchronous processing.
3233	*
3234	* @param pDevIns The device instance.
3235	* @param pThisCC The VGA/VMSVGA state for the current context.
3236	* @param ppCmdBuf Pointer to the command buffer pointer.
3237	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3238	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3239	* @return SVGACBStatus code.
3240	* @thread EMT
3241	*/
3242	static SVGACBStatus vmsvgaR3CmdBufSubmitDC(PPDMDEVINS pDevIns, PVGASTATECC pThisCC, PVMSVGACMDBUF ppCmdBuf, uint32_t poffNextCmd)
3243	{
3244	/* Synchronously process the device context commands. */
3245	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3246	return vmsvgaR3CmdBufProcessDC(pDevIns, pSvgaR3State, (ppCmdBuf)->pvCommands, (ppCmdBuf)->hdr.length, poffNextCmd);
3247	}
3248
3249	/** Submits a command buffer for asynchronous processing by the FIFO thread.
3250	*
3251	* @param pDevIns The device instance.
3252	* @param pThis The shared VGA/VMSVGA state.
3253	* @param pThisCC The VGA/VMSVGA state for the current context.
3254	* @param ppCmdBuf Pointer to the command buffer pointer.
3255	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3256	* @return SVGACBStatus code.
3257	* @thread EMT
3258	*/
3259	static SVGACBStatus vmsvgaR3CmdBufSubmitCtx(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf)
3260	{
3261	/* Command buffer submission. */
3262	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3263
3264	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3265
3266	PVMSVGACMDBUF const pCmdBuf = *ppCmdBuf;
3267	PVMSVGACMDBUFCTX const pCmdBufCtx = pCmdBuf->pCmdBufCtx;
3268
3269	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3270	AssertRC(rc);
3271
3272	if (RT_LIKELY(pCmdBufCtx->cSubmitted < SVGA_CB_MAX_QUEUED_PER_CONTEXT))
3273	{
3274	RTListAppend(&pCmdBufCtx->listSubmitted, &pCmdBuf->nodeBuffer);
3275	++pCmdBufCtx->cSubmitted;
3276	ppCmdBuf = NULL; / Consume the buffer. */
3277	ASMAtomicWriteU32(&pThisCC->svga.pSvgaR3State->fCmdBuf, 1);
3278	}
3279	else
3280	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3281
3282	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3283
3284	/* Inform the FIFO thread. */
3285	if (*ppCmdBuf == NULL)
3286	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3287
3288	return CBstatus;
3289	}
3290
3291
3292	/** SVGA_REG_COMMAND_LOW write handler.
3293	* Submits a command buffer to the FIFO thread or processes a device context command.
3294	*
3295	* @param pDevIns The device instance.
3296	* @param pThis The shared VGA/VMSVGA state.
3297	* @param pThisCC The VGA/VMSVGA state for the current context.
3298	* @param GCPhysCB Guest physical address of the command buffer header.
3299	* @param CBCtx Context the command buffer is submitted to.
3300	* @thread EMT
3301	*/
3302	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx)
3303	{
3304	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3305
3306	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3307	uint32_t offNextCmd = 0;
3308	uint32_t fIRQ = 0;
3309
3310	/* Get the context if the device has the capability. */
3311	PVMSVGACMDBUFCTX pCmdBufCtx = NULL;
3312	if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
3313	{
3314	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3315	pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[CBCtx];
3316	else if (CBCtx == SVGA_CB_CONTEXT_DEVICE)
3317	pCmdBufCtx = &pSvgaR3State->CmdBufCtxDC;
3318	RT_UNTRUSTED_VALIDATED_FENCE();
3319	}
3320
3321	/* Allocate a new command buffer. */
3322	PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pCmdBufCtx);
3323	if (RT_LIKELY(pCmdBuf))
3324	{
3325	pCmdBuf->GCPhysCB = GCPhysCB;
3326
3327	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCB, &pCmdBuf->hdr, sizeof(pCmdBuf->hdr));
3328	if (RT_SUCCESS(rc))
3329	{
3330	LogFunc(("status %RX32 errorOffset %RX32 id %RX64 flags %RX32 length %RX32 ptr %RX64 offset %RX32 dxContext %RX32 (%RX32 %RX32 %RX32 %RX32 %RX32 %RX32)\n",
3331	pCmdBuf->hdr.status,
3332	pCmdBuf->hdr.errorOffset,
3333	pCmdBuf->hdr.id,
3334	pCmdBuf->hdr.flags,
3335	pCmdBuf->hdr.length,
3336	pCmdBuf->hdr.ptr.pa,
3337	pCmdBuf->hdr.offset,
3338	pCmdBuf->hdr.dxContext,
3339	pCmdBuf->hdr.mustBeZero[0],
3340	pCmdBuf->hdr.mustBeZero[1],
3341	pCmdBuf->hdr.mustBeZero[2],
3342	pCmdBuf->hdr.mustBeZero[3],
3343	pCmdBuf->hdr.mustBeZero[4],
3344	pCmdBuf->hdr.mustBeZero[5]));
3345
3346	/* Verify the command buffer header. */
3347	if (RT_LIKELY( pCmdBuf->hdr.status == SVGA_CB_STATUS_NONE
3348	&& (pCmdBuf->hdr.flags & ~(SVGA_CB_FLAG_NO_IRQ \| SVGA_CB_FLAG_DX_CONTEXT)) == 0 /* No unexpected flags. */
3349	&& pCmdBuf->hdr.length <= SVGA_CB_MAX_SIZE))
3350	{
3351	RT_UNTRUSTED_VALIDATED_FENCE();
3352
3353	/* Read the command buffer content. */
3354	pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
3355	if (pCmdBuf->pvCommands)
3356	{
3357	RTGCPHYS const GCPhysCmd = (RTGCPHYS)pCmdBuf->hdr.ptr.pa;
3358	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
3359	if (RT_SUCCESS(rc))
3360	{
3361	/* Submit the buffer. Device context buffers will be processed synchronously. */
3362	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3363	/* This usually processes the CB async and sets pCmbBuf to NULL. */
3364	CBstatus = vmsvgaR3CmdBufSubmitCtx(pDevIns, pThis, pThisCC, &pCmdBuf);
3365	else
3366	CBstatus = vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
3367	}
3368	else
3369	{
3370	ASSERT_GUEST_MSG_FAILED(("Failed to read commands at %RGp\n", GCPhysCmd));
3371	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3372	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3373	}
3374	}
3375	else
3376	{
3377	/* No memory for commands. */
3378	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3379	}
3380	}
3381	else
3382	{
3383	ASSERT_GUEST_MSG_FAILED(("Invalid buffer header\n"));
3384	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3385	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3386	}
3387	}
3388	else
3389	{
3390	LogFunc(("Failed to read buffer header at %RGp\n", GCPhysCB));
3391	ASSERT_GUEST_FAILED();
3392	/* Do not attempt to write the status. */
3393	}
3394
3395	/* Free the buffer if pfnCmdBufSubmit did not consume it. */
3396	vmsvgaR3CmdBufFree(pCmdBuf);
3397	}
3398	else
3399	{
3400	LogFunc(("Can't allocate buffer for context id %#x\n", CBCtx));
3401	ASSERT_GUEST_FAILED();
3402	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3403	}
3404
3405	if (CBstatus != SVGA_CB_STATUS_NONE)
3406	{
3407	LogFunc(("Write status %#x, offNextCmd %#x (of %#x), fIRQ %#x\n", CBstatus, offNextCmd, pCmdBuf ? pCmdBuf->hdr.length : 0, fIRQ));
3408	vmsvgaR3CmdBufWriteStatus(pDevIns, GCPhysCB, CBstatus, offNextCmd);
3409	if (fIRQ)
3410	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, fIRQ);
3411	}
3412	}
3413
3414
3415	/** Checks if there are some buffers to be processed.
3416	*
3417	* @param pThisCC The VGA/VMSVGA state for the current context.
3418	* @return true if buffers must be processed.
3419	* @thread FIFO
3420	*/
3421	static bool vmsvgaR3CmdBufHasWork(PVGASTATECC pThisCC)
3422	{
3423	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3424	return RT_BOOL(ASMAtomicReadU32(&pSvgaR3State->fCmdBuf));
3425	}
3426
3427
3428	/** Processes a command buffer.
3429	*
3430	* @param pDevIns The device instance.
3431	* @param pThis The shared VGA/VMSVGA state.
3432	* @param pThisCC The VGA/VMSVGA state for the current context.
3433	* @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
3434	* @param pvCommands Pointer to the command buffer.
3435	* @param cbCommands Size of the command buffer.
3436	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3437	* @param pu32IrqStatus Where to store SVGA_IRQFLAG_ if the IRQ is generated by the last command in the buffer.
3438	* @return SVGACBStatus code.
3439	* @thread FIFO
3440	*/
3441	static SVGACBStatus vmsvgaR3CmdBufProcessCommands(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd, uint32_t *pu32IrqStatus)
3442	{
3443	# ifndef VBOX_WITH_VMSVGA3D
3444	RT_NOREF(idDXContext);
3445	# endif
3446	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3447	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3448
3449	# ifdef VBOX_WITH_VMSVGA3D
3450	# ifdef VMSVGA3D_DX
3451	/* Commands submitted for the SVGA3D_INVALID_ID context do not affect pipeline. So ignore them. */
3452	if (idDXContext != SVGA3D_INVALID_ID)
3453	{
3454	if (pSvgaR3State->idDXContextCurrent != idDXContext)
3455	{
3456	LogFlow(("DXCTX: buffer %d->%d\n", pSvgaR3State->idDXContextCurrent, idDXContext));
3457	vmsvga3dDXSwitchContext(pThisCC, idDXContext);
3458	pSvgaR3State->idDXContextCurrent = idDXContext;
3459	}
3460	}
3461	# endif
3462	# endif
3463
3464	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3465
3466	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3467	uint32_t cbRemain = cbCommands;
3468	while (cbRemain)
3469	{
3470	/* Command identifier is a 32 bit value. */
3471	if (cbRemain < sizeof(uint32_t))
3472	{
3473	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3474	break;
3475	}
3476
3477	/* Fetch the command id.
3478	* 'cmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
3479	* warning. Because we support some obsolete and deprecated commands, which are not included in
3480	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
3481	*/
3482	uint32_t const cmdId = (uint32_t )pu8Cmd;
3483	uint32_t cbCmd = sizeof(uint32_t);
3484
3485	LogFlowFunc(("[cid=%d] %s %d\n", (int32_t)idDXContext, vmsvgaR3FifoCmdToString(cmdId), cmdId));
3486	# ifdef LOG_ENABLED
3487	# ifdef VBOX_WITH_VMSVGA3D
3488	if (SVGA_3D_CMD_BASE <= cmdId && cmdId < SVGA_3D_CMD_MAX)
3489	{
3490	SVGA3dCmdHeader const header = (SVGA3dCmdHeader )pu8Cmd;
3491	svga_dump_command(cmdId, (uint8_t *)&header[1], header->size);
3492	}
3493	else if (cmdId == SVGA_CMD_FENCE)
3494	{
3495	Log7(("\tSVGA_CMD_FENCE\n"));
3496	Log7(("\t\t0x%08x\n", ((uint32_t *)pu8Cmd)[1]));
3497	}
3498	# endif
3499	# endif
3500
3501	/* At the end of the switch cbCmd is equal to the total length of the command including the cmdId.
3502	* I.e. pu8Cmd + cbCmd must point to the next command.
3503	* However if CBstatus is set to anything but SVGA_CB_STATUS_COMPLETED in the switch, then
3504	* the cbCmd value is ignored (and pu8Cmd still points to the failed command).
3505	*/
3506	/** @todo This code is very similar to the FIFO loop command processing. Think about merging. */
3507	switch (cmdId)
3508	{
3509	case SVGA_CMD_INVALID_CMD:
3510	{
3511	/* Nothing to do. */
3512	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdInvalidCmd);
3513	break;
3514	}
3515
3516	case SVGA_CMD_FENCE:
3517	{
3518	SVGAFifoCmdFence pCmd = (SVGAFifoCmdFence )&pu8Cmd[cbCmd];
3519	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3520	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdFence);
3521	Log(("SVGA_CMD_FENCE %#x\n", pCmd->fence));
3522
3523	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3524	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3525	{
3526	pFIFO[SVGA_FIFO_FENCE] = pCmd->fence;
3527
3528	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3529	{
3530	Log(("any fence irq\n"));
3531	*pu32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3532	}
3533	else if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3534	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3535	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmd->fence)
3536	{
3537	Log(("fence goal reached irq (fence=%#x)\n", pCmd->fence));
3538	*pu32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3539	}
3540	}
3541	else
3542	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3543	break;
3544	}
3545
3546	case SVGA_CMD_UPDATE:
3547	{
3548	SVGAFifoCmdUpdate pCmd = (SVGAFifoCmdUpdate )&pu8Cmd[cbCmd];
3549	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3550	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
3551	break;
3552	}
3553
3554	case SVGA_CMD_UPDATE_VERBOSE:
3555	{
3556	SVGAFifoCmdUpdateVerbose pCmd = (SVGAFifoCmdUpdateVerbose )&pu8Cmd[cbCmd];
3557	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3558	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
3559	break;
3560	}
3561
3562	case SVGA_CMD_DEFINE_CURSOR:
3563	{
3564	/* Followed by bitmap data. */
3565	SVGAFifoCmdDefineCursor pCmd = (SVGAFifoCmdDefineCursor )&pu8Cmd[cbCmd];
3566	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3567
3568	/* Figure out the size of the bitmap data. */
3569	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3570	ASSERT_GUEST_STMT_BREAK(pCmd->andMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3571	ASSERT_GUEST_STMT_BREAK(pCmd->xorMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3572	RT_UNTRUSTED_VALIDATED_FENCE();
3573
3574	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
3575	uint32_t const cbAndMask = cbAndLine * pCmd->height;
3576	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
3577	uint32_t const cbXorMask = cbXorLine * pCmd->height;
3578
3579	VMSVGA_INC_CMD_SIZE_BREAK(cbAndMask + cbXorMask);
3580	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
3581	break;
3582	}
3583
3584	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3585	{
3586	/* Followed by bitmap data. */
3587	SVGAFifoCmdDefineAlphaCursor pCmd = (SVGAFifoCmdDefineAlphaCursor )&pu8Cmd[cbCmd];
3588	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3589
3590	/* Figure out the size of the bitmap data. */
3591	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3592
3593	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->width * pCmd->height * sizeof(uint32_t)); /* 32-bit BRGA format */
3594	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
3595	break;
3596	}
3597
3598	case SVGA_CMD_MOVE_CURSOR:
3599	{
3600	/* Deprecated; there should be no driver which requires this command. However, if
3601	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3602	* alignment.
3603	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3604	*/
3605	SVGAFifoCmdMoveCursor pCmd = (SVGAFifoCmdMoveCursor )&pu8Cmd[cbCmd];
3606	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3607	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
3608	break;
3609	}
3610
3611	case SVGA_CMD_DISPLAY_CURSOR:
3612	{
3613	/* Deprecated; there should be no driver which requires this command. However, if
3614	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3615	* alignment.
3616	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3617	*/
3618	SVGAFifoCmdDisplayCursor pCmd = (SVGAFifoCmdDisplayCursor )&pu8Cmd[cbCmd];
3619	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3620	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
3621	break;
3622	}
3623
3624	case SVGA_CMD_RECT_FILL:
3625	{
3626	SVGAFifoCmdRectFill pCmd = (SVGAFifoCmdRectFill )&pu8Cmd[cbCmd];
3627	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3628	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
3629	break;
3630	}
3631
3632	case SVGA_CMD_RECT_COPY:
3633	{
3634	SVGAFifoCmdRectCopy pCmd = (SVGAFifoCmdRectCopy )&pu8Cmd[cbCmd];
3635	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3636	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
3637	break;
3638	}
3639
3640	case SVGA_CMD_RECT_ROP_COPY:
3641	{
3642	SVGAFifoCmdRectRopCopy pCmd = (SVGAFifoCmdRectRopCopy )&pu8Cmd[cbCmd];
3643	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3644	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
3645	break;
3646	}
3647
3648	case SVGA_CMD_ESCAPE:
3649	{
3650	/* Followed by 'size' bytes of data. */
3651	SVGAFifoCmdEscape pCmd = (SVGAFifoCmdEscape )&pu8Cmd[cbCmd];
3652	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3653
3654	ASSERT_GUEST_STMT_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3655	RT_UNTRUSTED_VALIDATED_FENCE();
3656
3657	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->size);
3658	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
3659	break;
3660	}
3661	# ifdef VBOX_WITH_VMSVGA3D
3662	case SVGA_CMD_DEFINE_GMR2:
3663	{
3664	SVGAFifoCmdDefineGMR2 pCmd = (SVGAFifoCmdDefineGMR2 )&pu8Cmd[cbCmd];
3665	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3666	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
3667	break;
3668	}
3669
3670	case SVGA_CMD_REMAP_GMR2:
3671	{
3672	/* Followed by page descriptors or guest ptr. */
3673	SVGAFifoCmdRemapGMR2 pCmd = (SVGAFifoCmdRemapGMR2 )&pu8Cmd[cbCmd];
3674	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3675
3676	/* Calculate the size of what comes after next and fetch it. */
3677	uint32_t cbMore = 0;
3678	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3679	cbMore = sizeof(SVGAGuestPtr);
3680	else
3681	{
3682	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3683	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3684	{
3685	cbMore = cbPageDesc;
3686	pCmd->numPages = 1;
3687	}
3688	else
3689	{
3690	ASSERT_GUEST_STMT_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3691	cbMore = cbPageDesc * pCmd->numPages;
3692	}
3693	}
3694	VMSVGA_INC_CMD_SIZE_BREAK(cbMore);
3695	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
3696	# ifdef DEBUG_GMR_ACCESS
3697	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
3698	# endif
3699	break;
3700	}
3701	# endif /* VBOX_WITH_VMSVGA3D */
3702	case SVGA_CMD_DEFINE_SCREEN:
3703	{
3704	/* The size of this command is specified by the guest and depends on capabilities. */
3705	SVGAFifoCmdDefineScreen pCmd = (SVGAFifoCmdDefineScreen )&pu8Cmd[cbCmd];
3706	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(pCmd->screen.structSize));
3707	ASSERT_GUEST_STMT_BREAK(pCmd->screen.structSize < pThis->svga.cbFIFO, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3708	RT_UNTRUSTED_VALIDATED_FENCE();
3709
3710	VMSVGA_INC_CMD_SIZE_BREAK(RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize) - sizeof(pCmd->screen.structSize));
3711	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
3712	break;
3713	}
3714
3715	case SVGA_CMD_DESTROY_SCREEN:
3716	{
3717	SVGAFifoCmdDestroyScreen pCmd = (SVGAFifoCmdDestroyScreen )&pu8Cmd[cbCmd];
3718	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3719	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
3720	break;
3721	}
3722
3723	case SVGA_CMD_DEFINE_GMRFB:
3724	{
3725	SVGAFifoCmdDefineGMRFB pCmd = (SVGAFifoCmdDefineGMRFB )&pu8Cmd[cbCmd];
3726	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3727	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
3728	break;
3729	}
3730
3731	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3732	{
3733	SVGAFifoCmdBlitGMRFBToScreen pCmd = (SVGAFifoCmdBlitGMRFBToScreen )&pu8Cmd[cbCmd];
3734	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3735	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
3736	break;
3737	}
3738
3739	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3740	{
3741	SVGAFifoCmdBlitScreenToGMRFB pCmd = (SVGAFifoCmdBlitScreenToGMRFB )&pu8Cmd[cbCmd];
3742	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3743	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
3744	break;
3745	}
3746
3747	case SVGA_CMD_ANNOTATION_FILL:
3748	{
3749	SVGAFifoCmdAnnotationFill pCmd = (SVGAFifoCmdAnnotationFill )&pu8Cmd[cbCmd];
3750	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3751	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
3752	break;
3753	}
3754
3755	case SVGA_CMD_ANNOTATION_COPY:
3756	{
3757	SVGAFifoCmdAnnotationCopy pCmd = (SVGAFifoCmdAnnotationCopy )&pu8Cmd[cbCmd];
3758	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3759	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
3760	break;
3761	}
3762
3763	default:
3764	{
3765	# ifdef VBOX_WITH_VMSVGA3D
3766	if ( cmdId >= SVGA_3D_CMD_BASE
3767	&& cmdId < SVGA_3D_CMD_MAX)
3768	{
3769	RT_UNTRUSTED_VALIDATED_FENCE();
3770
3771	/* All 3d commands start with a common header, which defines the identifier and the size
3772	* of the command. The identifier has been already read. Fetch the size.
3773	*/
3774	uint32_t const pcbMore = (uint32_t const )&pu8Cmd[cbCmd];
3775	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pcbMore));
3776	VMSVGA_INC_CMD_SIZE_BREAK(*pcbMore);
3777	if (RT_LIKELY(pThis->svga.f3DEnabled))
3778	{ /* likely */ }
3779	else
3780	{
3781	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", cmdId));
3782	break;
3783	}
3784
3785	/* Command data begins after the 32 bit command length. */
3786	int rc = vmsvgaR3Process3dCmd(pThis, pThisCC, idDXContext, (SVGAFifo3dCmdId)cmdId, *pcbMore, pcbMore + 1);
3787	if (RT_SUCCESS(rc))
3788	{ /* likely */ }
3789	else
3790	{
3791	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3792	break;
3793	}
3794	}
3795	else
3796	# endif /* VBOX_WITH_VMSVGA3D */
3797	{
3798	/* Unsupported command. */
3799	STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
3800	ASSERT_GUEST_MSG_FAILED(("cmdId=%d\n", cmdId));
3801	LogRelMax(16, ("VMSVGA: unsupported command %d\n", cmdId));
3802	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3803	break;
3804	}
3805	}
3806	}
3807
3808	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3809	break;
3810
3811	pu8Cmd += cbCmd;
3812	cbRemain -= cbCmd;
3813
3814	/* If this is not the last command in the buffer, then generate IRQ, if required.
3815	* This avoids a double call to vmsvgaR3CmdBufRaiseIRQ if FENCE is the last command
3816	* in the buffer (usually the case).
3817	*/
3818	if (RT_LIKELY(!(cbRemain && *pu32IrqStatus)))
3819	{ /* likely */ }
3820	else
3821	{
3822	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, *pu32IrqStatus);
3823	*pu32IrqStatus = 0;
3824	}
3825	}
3826
3827	Assert(cbRemain <= cbCommands);
3828	*poffNextCmd = cbCommands - cbRemain;
3829	return CBstatus;
3830	}
3831
3832
3833	/** Process command buffers.
3834	*
3835	* @param pDevIns The device instance.
3836	* @param pThis The shared VGA/VMSVGA state.
3837	* @param pThisCC The VGA/VMSVGA state for the current context.
3838	* @param pThread Handle of the FIFO thread.
3839	* @thread FIFO
3840	*/
3841	static void vmsvgaR3CmdBufProcessBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PPDMTHREAD pThread)
3842	{
3843	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3844
3845	for (;;)
3846	{
3847	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3848	break;
3849
3850	/* See if there is a submitted buffer. */
3851	PVMSVGACMDBUF pCmdBuf = NULL;
3852
3853	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3854	AssertRC(rc);
3855
3856	/* It seems that a higher queue index has a higher priority.
3857	* See SVGACBContext in svga_reg.h from latest vmwgfx Linux driver.
3858	*/
3859	for (unsigned i = RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs); i > 0; --i)
3860	{
3861	PVMSVGACMDBUFCTX pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[i - 1];
3862	if (pCmdBufCtx)
3863	{
3864	pCmdBuf = RTListRemoveFirst(&pCmdBufCtx->listSubmitted, VMSVGACMDBUF, nodeBuffer);
3865	if (pCmdBuf)
3866	{
3867	Assert(pCmdBufCtx->cSubmitted > 0);
3868	--pCmdBufCtx->cSubmitted;
3869	break;
3870	}
3871	}
3872	}
3873
3874	if (!pCmdBuf)
3875	{
3876	ASMAtomicWriteU32(&pSvgaR3State->fCmdBuf, 0);
3877	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3878	break;
3879	}
3880
3881	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3882
3883	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3884	uint32_t offNextCmd = 0;
3885	uint32_t u32IrqStatus = 0;
3886	uint32_t const idDXContext = RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_DX_CONTEXT)
3887	? pCmdBuf->hdr.dxContext
3888	: SVGA3D_INVALID_ID;
3889	/* Process one buffer. */
3890	CBstatus = vmsvgaR3CmdBufProcessCommands(pDevIns, pThis, pThisCC, idDXContext, pCmdBuf->pvCommands, pCmdBuf->hdr.length, &offNextCmd, &u32IrqStatus);
3891
3892	if (!RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_NO_IRQ))
3893	u32IrqStatus \|= SVGA_IRQFLAG_COMMAND_BUFFER;
3894	if (CBstatus == SVGA_CB_STATUS_COMMAND_ERROR)
3895	u32IrqStatus \|= SVGA_IRQFLAG_ERROR;
3896
3897	vmsvgaR3CmdBufWriteStatus(pDevIns, pCmdBuf->GCPhysCB, CBstatus, offNextCmd);
3898	if (u32IrqStatus)
3899	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, u32IrqStatus);
3900
3901	vmsvgaR3CmdBufFree(pCmdBuf);
3902	}
3903	}
3904
3905
3906	/**
3907	* Worker for vmsvgaR3FifoThread that handles an external command.
3908	*
3909	* @param pDevIns The device instance.
3910	* @param pThis The shared VGA/VMSVGA instance data.
3911	* @param pThisCC The VGA/VMSVGA state for ring-3.
3912	*/
3913	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3914	{
3915	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
3916	switch (pThis->svga.u8FIFOExtCommand)
3917	{
3918	case VMSVGA_FIFO_EXTCMD_RESET:
3919	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
3920	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3921
3922	vmsvgaR3ResetScreens(pThis, pThisCC);
3923	# ifdef VBOX_WITH_VMSVGA3D
3924	if (pThis->svga.f3DEnabled)
3925	{
3926	/* The 3d subsystem must be reset from the fifo thread. */
3927	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3928	pSVGAState->pFuncs3D->pfnReset(pThisCC);
3929	}
3930	# endif
3931	break;
3932
3933	case VMSVGA_FIFO_EXTCMD_POWEROFF:
3934	Log(("vmsvgaR3FifoLoop: power off.\n"));
3935	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3936
3937	/* The screens must be reset on the FIFO thread, because they may use 3D resources. */
3938	vmsvgaR3ResetScreens(pThis, pThisCC);
3939	break;
3940
3941	case VMSVGA_FIFO_EXTCMD_TERMINATE:
3942	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
3943	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3944	# ifdef VBOX_WITH_VMSVGA3D
3945	if (pThis->svga.f3DEnabled)
3946	{
3947	/* The 3d subsystem must be shut down from the fifo thread. */
3948	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3949	pSVGAState->pFuncs3D->pfnTerminate(pThisCC);
3950	}
3951	# endif
3952	break;
3953
3954	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
3955	{
3956	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
3957	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
3958	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
3959	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
3960	# ifdef VBOX_WITH_VMSVGA3D
3961	if (pThis->svga.f3DEnabled)
3962	{
3963	if (vmsvga3dIsLegacyBackend(pThisCC))
3964	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
3965	# ifdef VMSVGA3D_DX
3966	else
3967	vmsvga3dDXSaveExec(pDevIns, pThisCC, pSSM);
3968	# endif
3969	}
3970	# endif
3971	break;
3972	}
3973
3974	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
3975	{
3976	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
3977	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
3978	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
3979	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3980	# ifdef VBOX_WITH_VMSVGA3D
3981	if (pThis->svga.f3DEnabled)
3982	{
3983	/* The following RT_OS_DARWIN code was in vmsvga3dLoadExec and therefore must be executed before each vmsvga3dLoadExec invocation. */
3984	# ifndef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA.cpp */
3985	/* Must initialize now as the recreation calls below rely on an initialized 3d subsystem. */
3986	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3987	pSVGAState->pFuncs3D->pfnPowerOn(pDevIns, pThis, pThisCC);
3988	# endif
3989
3990	if (vmsvga3dIsLegacyBackend(pThisCC))
3991	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3992	# ifdef VMSVGA3D_DX
3993	else
3994	vmsvga3dDXLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3995	# endif
3996	}
3997	# endif
3998	break;
3999	}
4000
4001	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
4002	{
4003	# ifdef VBOX_WITH_VMSVGA3D
4004	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
4005	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
4006	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
4007	# endif
4008	break;
4009	}
4010
4011
4012	default:
4013	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
4014	break;
4015	}
4016
4017	/*
4018	* Signal the end of the external command.
4019	*/
4020	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4021	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
4022	ASMMemoryFence(); /* paranoia^2 */
4023	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
4024	AssertLogRelRC(rc);
4025	}
4026
4027	/**
4028	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
4029	* doing a job on the FIFO thread (even when it's officially suspended).
4030	*
4031	* @returns VBox status code (fully asserted).
4032	* @param pDevIns The device instance.
4033	* @param pThis The shared VGA/VMSVGA instance data.
4034	* @param pThisCC The VGA/VMSVGA state for ring-3.
4035	* @param uExtCmd The command to execute on the FIFO thread.
4036	* @param pvParam Pointer to command parameters.
4037	* @param cMsWait The time to wait for the command, given in
4038	* milliseconds.
4039	*/
4040	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
4041	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
4042	{
4043	Assert(cMsWait >= RT_MS_1SEC * 5);
4044	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
4045	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
4046
4047	int rc;
4048	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
4049	PDMTHREADSTATE enmState = pThread->enmState;
4050	if (enmState == PDMTHREADSTATE_SUSPENDED)
4051	{
4052	/*
4053	* The thread is suspended, we have to temporarily wake it up so it can
4054	* perform the task.
4055	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
4056	*/
4057	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
4058	/* Post the request. */
4059	pThis->svga.fFifoExtCommandWakeup = true;
4060	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4061	pThis->svga.u8FIFOExtCommand = uExtCmd;
4062	ASMMemoryFence(); /* paranoia^3 */
4063
4064	/* Resume the thread. */
4065	rc = PDMDevHlpThreadResume(pDevIns, pThread);
4066	AssertLogRelRC(rc);
4067	if (RT_SUCCESS(rc))
4068	{
4069	/* Wait. Take care in case the semaphore was already posted (same as below). */
4070	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4071	if ( rc == VINF_SUCCESS
4072	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4073	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4074	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4075	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4076
4077	/* suspend the thread */
4078	pThis->svga.fFifoExtCommandWakeup = false;
4079	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
4080	AssertLogRelRC(rc2);
4081	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
4082	rc = rc2;
4083	}
4084	pThis->svga.fFifoExtCommandWakeup = false;
4085	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4086	}
4087	else if (enmState == PDMTHREADSTATE_RUNNING)
4088	{
4089	/*
4090	* The thread is running, should only happen during reset and vmsvga3dsfc.
4091	* We ASSUME not racing code here, both wrt thread state and ext commands.
4092	*/
4093	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
4094	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_POWEROFF);
4095
4096	/* Post the request. */
4097	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4098	pThis->svga.u8FIFOExtCommand = uExtCmd;
4099	ASMMemoryFence(); /* paranoia^2 */
4100	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4101	AssertLogRelRC(rc);
4102
4103	/* Wait. Take care in case the semaphore was already posted (same as above). */
4104	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4105	if ( rc == VINF_SUCCESS
4106	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4107	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
4108	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4109	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4110
4111	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4112	}
4113	else
4114	{
4115	/*
4116	* Something is wrong with the thread!
4117	*/
4118	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
4119	rc = VERR_INVALID_STATE;
4120	}
4121	return rc;
4122	}
4123
4124
4125	/**
4126	* Marks the FIFO non-busy, notifying any waiting EMTs.
4127	*
4128	* @param pDevIns The device instance.
4129	* @param pThis The shared VGA/VMSVGA instance data.
4130	* @param pThisCC The VGA/VMSVGA state for ring-3.
4131	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
4132	* @param offFifoMin The start byte offset of the command FIFO.
4133	*/
4134	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
4135	{
4136	ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO \| VMSVGA_BUSY_F_EMT_FORCE));
4137	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4138	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
4139
4140	/* Wake up any waiting EMTs. */
4141	if (pSVGAState->cBusyDelayedEmts > 0)
4142	{
4143	# ifdef VMSVGA_USE_EMT_HALT_CODE
4144	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
4145	if (idCpu != NIL_VMCPUID)
4146	{
4147	PDMDevHlpVMNotifyCpuDeviceReady(pDevIns, idCpu);
4148	while (idCpu-- > 0)
4149	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
4150	PDMDevHlpVMNotifyCpuDeviceReady(pDevIns, idCpu);
4151	}
4152	# else
4153	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
4154	AssertRC(rc2);
4155	# endif
4156	}
4157	}
4158
4159	/**
4160	* Reads (more) payload into the command buffer.
4161	*
4162	* @returns pbBounceBuf on success
4163	* @retval (void *)1 if the thread was requested to stop.
4164	* @retval NULL on FIFO error.
4165	*
4166	* @param cbPayloadReq The number of bytes of payload requested.
4167	* @param pFIFO The FIFO.
4168	* @param offCurrentCmd The FIFO byte offset of the current command.
4169	* @param offFifoMin The start byte offset of the command FIFO.
4170	* @param offFifoMax The end byte offset of the command FIFO.
4171	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
4172	* always sufficient size.
4173	* @param pcbAlreadyRead How much payload we've already read into the bounce
4174	* buffer. (We will NEVER re-read anything.)
4175	* @param pThread The calling PDM thread handle.
4176	* @param pThis The shared VGA/VMSVGA instance data.
4177	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
4178	* statistics collection.
4179	* @param pDevIns The device instance.
4180	*/
4181	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
4182	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
4183	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
4184	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
4185	{
4186	Assert(pbBounceBuf);
4187	Assert(pcbAlreadyRead);
4188	Assert(offFifoMin < offFifoMax);
4189	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
4190	Assert(offFifoMax <= pThis->svga.cbFIFO);
4191
4192	/*
4193	* Check if the requested payload size has already been satisfied .
4194	* .
4195	* When called to read more, the caller is responsible for making sure the .
4196	* new command size (cbRequsted) never is smaller than what has already .
4197	* been read.
4198	*/
4199	uint32_t cbAlreadyRead = *pcbAlreadyRead;
4200	if (cbPayloadReq <= cbAlreadyRead)
4201	{
4202	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
4203	return pbBounceBuf;
4204	}
4205
4206	/*
4207	* Commands bigger than the fifo buffer are invalid.
4208	*/
4209	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
4210	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
4211	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
4212	NULL);
4213
4214	/*
4215	* Move offCurrentCmd past the command dword.
4216	*/
4217	offCurrentCmd += sizeof(uint32_t);
4218	if (offCurrentCmd >= offFifoMax)
4219	offCurrentCmd = offFifoMin;
4220
4221	/*
4222	* Do we have sufficient payload data available already?
4223	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
4224	*/
4225	uint32_t cbAfter, cbBefore;
4226	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4227	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4228	if (offNextCmd >= offCurrentCmd)
4229	{
4230	if (RT_LIKELY(offNextCmd < offFifoMax))
4231	cbAfter = offNextCmd - offCurrentCmd;
4232	else
4233	{
4234	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4235	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4236	offNextCmd, offFifoMin, offFifoMax));
4237	cbAfter = offFifoMax - offCurrentCmd;
4238	}
4239	cbBefore = 0;
4240	}
4241	else
4242	{
4243	cbAfter = offFifoMax - offCurrentCmd;
4244	if (offNextCmd >= offFifoMin)
4245	cbBefore = offNextCmd - offFifoMin;
4246	else
4247	{
4248	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4249	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4250	offNextCmd, offFifoMin, offFifoMax));
4251	cbBefore = 0;
4252	}
4253	}
4254	if (cbAfter + cbBefore < cbPayloadReq)
4255	{
4256	/*
4257	* Insufficient, must wait for it to arrive.
4258	*/
4259	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
4260	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
4261	for (uint32_t i = 0;; i++)
4262	{
4263	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4264	{
4265	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4266	return (void *)(uintptr_t)1;
4267	}
4268	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
4269	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
4270
4271	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
4272
4273	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4274	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4275	if (offNextCmd >= offCurrentCmd)
4276	{
4277	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
4278	cbBefore = 0;
4279	}
4280	else
4281	{
4282	cbAfter = offFifoMax - offCurrentCmd;
4283	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
4284	}
4285
4286	if (cbAfter + cbBefore >= cbPayloadReq)
4287	break;
4288	}
4289	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4290	}
4291
4292	/*
4293	* Copy out the memory and update what pcbAlreadyRead points to.
4294	*/
4295	if (cbAfter >= cbPayloadReq)
4296	memcpy(pbBounceBuf + cbAlreadyRead,
4297	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4298	cbPayloadReq - cbAlreadyRead);
4299	else
4300	{
4301	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
4302	if (cbAlreadyRead < cbAfter)
4303	{
4304	memcpy(pbBounceBuf + cbAlreadyRead,
4305	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4306	cbAfter - cbAlreadyRead);
4307	cbAlreadyRead = cbAfter;
4308	}
4309	memcpy(pbBounceBuf + cbAlreadyRead,
4310	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
4311	cbPayloadReq - cbAlreadyRead);
4312	}
4313	*pcbAlreadyRead = cbPayloadReq;
4314	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4315	return pbBounceBuf;
4316	}
4317
4318
4319	/**
4320	* Sends cursor position and visibility information from the FIFO to the front-end.
4321	* @returns SVGA_FIFO_CURSOR_COUNT value used.
4322	*/
4323	static uint32_t
4324	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
4325	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
4326	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
4327	{
4328	/*
4329	* Check if the cursor update counter has changed and try get a stable
4330	* set of values if it has. This is race-prone, especially consindering
4331	* the screen ID, but little we can do about that.
4332	*/
4333	uint32_t x, y, fVisible, idScreen;
4334	for (uint32_t i = 0; ; i++)
4335	{
4336	x = pFIFO[SVGA_FIFO_CURSOR_X];
4337	y = pFIFO[SVGA_FIFO_CURSOR_Y];
4338	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
4339	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
4340	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
4341	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
4342	\|\| i > 3)
4343	break;
4344	if (i == 0)
4345	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
4346	ASMNopPause();
4347	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4348	}
4349
4350	/*
4351	* Check if anything has changed, as calling into pDrv is not light-weight.
4352	*/
4353	if ( *pxLast == x
4354	&& *pyLast == y
4355	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
4356	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
4357	else
4358	{
4359	/*
4360	* Detected changes.
4361	*
4362	* We handle global, not per-screen visibility information by sending
4363	* pfnVBVAMousePointerShape without shape data.
4364	*/
4365	*pxLast = x;
4366	*pyLast = y;
4367	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
4368	if (idScreen != SVGA_ID_INVALID)
4369	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
4370	else if (*pfLastVisible != fVisible)
4371	{
4372	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
4373	*pfLastVisible = fVisible;
4374	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
4375	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
4376	}
4377	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
4378	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
4379	}
4380
4381	/*
4382	* Update done. Signal this to the guest.
4383	*/
4384	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
4385
4386	return uCursorUpdateCount;
4387	}
4388
4389
4390	/**
4391	* Checks if there is work to be done, either cursor updating or FIFO commands.
4392	*
4393	* @returns true if pending work, false if not.
4394	* @param pThisCC The VGA/VMSVGA state for ring-3.
4395	* @param uLastCursorCount The last cursor update counter value.
4396	*/
4397	DECLINLINE(bool) vmsvgaR3FifoHasWork(PVGASTATECC pThisCC, uint32_t uLastCursorCount)
4398	{
4399	/* If FIFO does not exist than there is nothing to do. Command buffers also require the enabled FIFO. */
4400	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4401	AssertReturn(pFIFO, false);
4402
4403	if (vmsvgaR3CmdBufHasWork(pThisCC))
4404	return true;
4405
4406	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
4407	return true;
4408
4409	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
4410	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
4411	return true;
4412
4413	return false;
4414	}
4415
4416
4417	/**
4418	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
4419	*
4420	* @param pDevIns The device instance.
4421	* @param pThis The shared VGA/VMSVGA instance data.
4422	* @param pThisCC The VGA/VMSVGA state for ring-3.
4423	*/
4424	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4425	{
4426	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
4427	to recheck it before doing the signalling. */
4428	if ( vmsvgaR3FifoHasWork(pThisCC, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
4429	&& pThis->svga.fFIFOThreadSleeping
4430	&& !ASMAtomicReadBool(&pThis->svga.fBadGuest))
4431	{
4432	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4433	AssertRC(rc);
4434	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
4435	}
4436	}
4437
4438
4439	/**
4440	* Called by the FIFO thread to process pending actions.
4441	*
4442	* @param pDevIns The device instance.
4443	* @param pThis The shared VGA/VMSVGA instance data.
4444	* @param pThisCC The VGA/VMSVGA state for ring-3.
4445	*/
4446	void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4447	{
4448	RT_NOREF(pDevIns);
4449
4450	/* Currently just mode changes. */
4451	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
4452	{
4453	vmsvgaR3ChangeMode(pThis, pThisCC);
4454	# ifdef VBOX_WITH_VMSVGA3D
4455	if (pThisCC->svga.p3dState != NULL)
4456	vmsvga3dChangeMode(pThisCC);
4457	# endif
4458	}
4459	}
4460
4461
4462	/*
4463	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
4464	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
4465	*/
4466	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4467	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
4468	*
4469	* Will break out of the switch on failure.
4470	* Will restart and quit the loop if the thread was requested to stop.
4471	*
4472	* @param a_PtrVar Request variable pointer.
4473	* @param a_Type Request typedef (not pointer) for casting.
4474	* @param a_cbPayloadReq How much payload to fetch.
4475	* @remarks Accesses a bunch of variables in the current scope!
4476	*/
4477	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4478	if (1) { \
4479	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
4480	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
4481	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
4482	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
4483	} else do {} while (0)
4484	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4485	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
4486	* buffer after figuring out the actual command size.
4487	*
4488	* Will break out of the switch on failure.
4489	*
4490	* @param a_PtrVar Request variable pointer.
4491	* @param a_Type Request typedef (not pointer) for casting.
4492	* @param a_cbPayloadReq How much payload to fetch.
4493	* @remarks Accesses a bunch of variables in the current scope!
4494	*/
4495	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4496	if (1) { \
4497	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
4498	} else do {} while (0)
4499
4500	/**
4501	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
4502	*/
4503	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4504	{
4505	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4506	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4507	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4508	int rc;
4509
4510	# if defined(VBOX_WITH_VMSVGA3D) && defined(RT_OS_LINUX)
4511	if (pThis->svga.f3DEnabled)
4512	{
4513	/* The FIFO thread may use X API for accelerated screen output. */
4514	XInitThreads();
4515	}
4516	# endif
4517
4518	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4519	return VINF_SUCCESS;
4520
4521	/*
4522	* Special mode where we only execute an external command and the go back
4523	* to being suspended. Currently, all ext cmds ends up here, with the reset
4524	* one also being eligble for runtime execution further down as well.
4525	*/
4526	if (pThis->svga.fFifoExtCommandWakeup)
4527	{
4528	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4529	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4530	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
4531	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
4532	else
4533	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4534	return VINF_SUCCESS;
4535	}
4536
4537
4538	/*
4539	* Signal the semaphore to make sure we don't wait for 250ms after a
4540	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
4541	*/
4542	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4543
4544	/*
4545	* Allocate a bounce buffer for command we get from the FIFO.
4546	* (All code must return via the end of the function to free this buffer.)
4547	*/
4548	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
4549	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
4550
4551	/*
4552	* Polling/sleep interval config.
4553	*
4554	* We wait for an a short interval if the guest has recently given us work
4555	* to do, but the interval increases the longer we're kept idle. Once we've
4556	* reached the refresh timer interval, we'll switch to extended waits,
4557	* depending on it or the guest to kick us into action when needed.
4558	*
4559	* Should the refresh time go fishing, we'll just continue increasing the
4560	* sleep length till we reaches the 250 ms max after about 16 seconds.
4561	*/
4562	RTMSINTERVAL const cMsMinSleep = 16;
4563	RTMSINTERVAL const cMsIncSleep = 2;
4564	RTMSINTERVAL const cMsMaxSleep = 250;
4565	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
4566	RTMSINTERVAL cMsSleep = cMsMaxSleep;
4567
4568	/*
4569	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
4570	*
4571	* Initialize with values that will detect an update from the guest.
4572	* Make sure that if the guest never updates the cursor position, then the device does not report it.
4573	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
4574	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
4575	*/
4576	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4577	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4578	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
4579	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
4580	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
4581
4582	/*
4583	* The FIFO loop.
4584	*/
4585	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
4586	bool fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4587	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4588	{
4589	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
4590	/*
4591	* Should service the run loop every so often.
4592	*/
4593	if (pThis->svga.f3DEnabled)
4594	vmsvga3dCocoaServiceRunLoop();
4595	# endif
4596
4597	/* First check any pending actions. */
4598	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4599
4600	/*
4601	* Unless there's already work pending, go to sleep for a short while.
4602	* (See polling/sleep interval config above.)
4603	*/
4604	if ( fBadOrDisabledFifo
4605	\|\| !vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4606	{
4607	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
4608	Assert(pThis->cMilliesRefreshInterval > 0);
4609	if (cMsSleep < pThis->cMilliesRefreshInterval)
4610	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
4611	else
4612	{
4613	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
4614	int rc2 = PDMDevHlpPGMHandlerPhysicalReset(pDevIns, pThis->svga.GCPhysFIFO);
4615	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
4616	# endif
4617	if ( !fBadOrDisabledFifo
4618	&& vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4619	rc = VINF_SUCCESS;
4620	else
4621	{
4622	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
4623	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
4624	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
4625	}
4626	}
4627	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
4628	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
4629	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4630	{
4631	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
4632	break;
4633	}
4634	}
4635	else
4636	rc = VINF_SUCCESS;
4637	fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4638	if (rc == VERR_TIMEOUT)
4639	{
4640	if (!vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4641	{
4642	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
4643	continue;
4644	}
4645	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
4646
4647	Log(("vmsvgaR3FifoLoop: timeout\n"));
4648	}
4649	else if (vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4650	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
4651	cMsSleep = cMsMinSleep;
4652
4653	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
4654	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
4655	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
4656
4657	/*
4658	* Handle external commands (currently only reset).
4659	*/
4660	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4661	{
4662	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4663	continue;
4664	}
4665
4666	/*
4667	* If guest misbehaves, then do nothing.
4668	*/
4669	if (ASMAtomicReadBool(&pThis->svga.fBadGuest))
4670	{
4671	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4672	cMsSleep = cMsExtendedSleep;
4673	LogRelMax(1, ("VMSVGA: FIFO processing stopped because of the guest misbehavior\n"));
4674	continue;
4675	}
4676
4677	/*
4678	* The device must be enabled and configured.
4679	*/
4680	if ( !pThis->svga.fEnabled
4681	\|\| !pThis->svga.fConfigured)
4682	{
4683	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4684	fBadOrDisabledFifo = true;
4685	cMsSleep = cMsMaxSleep; /* cheat */
4686	continue;
4687	}
4688
4689	/*
4690	* Get and check the min/max values. We ASSUME that they will remain
4691	* unchanged while we process requests. A further ASSUMPTION is that
4692	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
4693	* we don't read it back while in the loop.
4694	*/
4695	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
4696	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
4697	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
4698	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4699	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
4700	\|\| offFifoMax <= offFifoMin
4701	\|\| offFifoMax > pThis->svga.cbFIFO
4702	\|\| (offFifoMax & 3) != 0
4703	\|\| (offFifoMin & 3) != 0
4704	\|\| offCurrentCmd < offFifoMin
4705	\|\| offCurrentCmd > offFifoMax))
4706	{
4707	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4708	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
4709	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4710	fBadOrDisabledFifo = true;
4711	continue;
4712	}
4713	RT_UNTRUSTED_VALIDATED_FENCE();
4714	if (RT_UNLIKELY(offCurrentCmd & 3))
4715	{
4716	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4717	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
4718	offCurrentCmd &= ~UINT32_C(3);
4719	}
4720
4721	/*
4722	* Update the cursor position before we start on the FIFO commands.
4723	*/
4724	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
4725	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
4726	{
4727	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4728	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
4729	{ /* halfways likely */ }
4730	else
4731	{
4732	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
4733	&xLastCursor, &yLastCursor, &fLastCursorVisible);
4734	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
4735	}
4736	}
4737
4738	/*
4739	* Mark the FIFO as busy.
4740	*/
4741	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
4742	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4743	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
4744
4745	/*
4746	* Process all submitted command buffers.
4747	*/
4748	vmsvgaR3CmdBufProcessBuffers(pDevIns, pThis, pThisCC, pThread);
4749
4750	/*
4751	* Execute all queued FIFO commands.
4752	* Quit if pending external command or changes in the thread state.
4753	*/
4754	bool fDone = false;
4755	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
4756	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
4757	{
4758	uint32_t cbPayload = 0;
4759	uint32_t u32IrqStatus = 0;
4760
4761	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
4762
4763	/* First check any pending actions. */
4764	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4765
4766	/* Check for pending external commands (reset). */
4767	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4768	break;
4769
4770	/*
4771	* Process the command.
4772	*/
4773	/* 'enmCmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
4774	* warning. Because we implement some obsolete and deprecated commands, which are not included in
4775	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
4776	*/
4777	uint32_t const enmCmdId = pFIFO[offCurrentCmd / sizeof(uint32_t)];
4778	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4779	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s %d\n",
4780	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
4781	switch (enmCmdId)
4782	{
4783	case SVGA_CMD_INVALID_CMD:
4784	/* Nothing to do. */
4785	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
4786	break;
4787
4788	case SVGA_CMD_FENCE:
4789	{
4790	SVGAFifoCmdFence *pCmdFence;
4791	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
4792	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
4793	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
4794	{
4795	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %#x\n", pCmdFence->fence));
4796	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
4797
4798	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
4799	{
4800	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
4801	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
4802	}
4803	else
4804	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
4805	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
4806	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
4807	{
4808	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%#x)\n", pCmdFence->fence));
4809	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
4810	}
4811	}
4812	else
4813	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
4814	break;
4815	}
4816
4817	case SVGA_CMD_UPDATE:
4818	{
4819	SVGAFifoCmdUpdate *pCmd;
4820	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdate, sizeof(*pCmd));
4821	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
4822	break;
4823	}
4824
4825	case SVGA_CMD_UPDATE_VERBOSE:
4826	{
4827	SVGAFifoCmdUpdateVerbose *pCmd;
4828	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdateVerbose, sizeof(*pCmd));
4829	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
4830	break;
4831	}
4832
4833	case SVGA_CMD_DEFINE_CURSOR:
4834	{
4835	/* Followed by bitmap data. */
4836	SVGAFifoCmdDefineCursor *pCmd;
4837	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, sizeof(*pCmd));
4838
4839	/* Figure out the size of the bitmap data. */
4840	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4841	ASSERT_GUEST_BREAK(pCmd->andMaskDepth <= 32);
4842	ASSERT_GUEST_BREAK(pCmd->xorMaskDepth <= 32);
4843	RT_UNTRUSTED_VALIDATED_FENCE();
4844
4845	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
4846	uint32_t const cbAndMask = cbAndLine * pCmd->height;
4847	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
4848	uint32_t const cbXorMask = cbXorLine * pCmd->height;
4849
4850	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineCursor) + cbAndMask + cbXorMask;
4851	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, cbCmd);
4852	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
4853	break;
4854	}
4855
4856	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
4857	{
4858	/* Followed by bitmap data. */
4859	SVGAFifoCmdDefineAlphaCursor *pCmd;
4860	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCmd));
4861
4862	/* Figure out the size of the bitmap data. */
4863	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4864
4865	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCmd->width * pCmd->height * sizeof(uint32_t) /* 32-bit BRGA format */;
4866	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, cbCmd);
4867	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
4868	break;
4869	}
4870
4871	case SVGA_CMD_MOVE_CURSOR:
4872	{
4873	/* Deprecated; there should be no driver which requires this command. However, if
4874	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4875	* alignment.
4876	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4877	*/
4878	SVGAFifoCmdMoveCursor *pCmd;
4879	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdMoveCursor, sizeof(*pCmd));
4880	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
4881	break;
4882	}
4883
4884	case SVGA_CMD_DISPLAY_CURSOR:
4885	{
4886	/* Deprecated; there should be no driver which requires this command. However, if
4887	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4888	* alignment.
4889	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4890	*/
4891	SVGAFifoCmdDisplayCursor *pCmd;
4892	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDisplayCursor, sizeof(*pCmd));
4893	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
4894	break;
4895	}
4896
4897	case SVGA_CMD_RECT_FILL:
4898	{
4899	SVGAFifoCmdRectFill *pCmd;
4900	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectFill, sizeof(*pCmd));
4901	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
4902	break;
4903	}
4904
4905	case SVGA_CMD_RECT_COPY:
4906	{
4907	SVGAFifoCmdRectCopy *pCmd;
4908	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectCopy, sizeof(*pCmd));
4909	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
4910	break;
4911	}
4912
4913	case SVGA_CMD_RECT_ROP_COPY:
4914	{
4915	SVGAFifoCmdRectRopCopy *pCmd;
4916	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectRopCopy, sizeof(*pCmd));
4917	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
4918	break;
4919	}
4920
4921	case SVGA_CMD_ESCAPE:
4922	{
4923	/* Followed by 'size' bytes of data. */
4924	SVGAFifoCmdEscape *pCmd;
4925	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, sizeof(*pCmd));
4926
4927	ASSERT_GUEST_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape));
4928	RT_UNTRUSTED_VALIDATED_FENCE();
4929
4930	uint32_t const cbCmd = sizeof(SVGAFifoCmdEscape) + pCmd->size;
4931	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, cbCmd);
4932	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
4933	break;
4934	}
4935	# ifdef VBOX_WITH_VMSVGA3D
4936	case SVGA_CMD_DEFINE_GMR2:
4937	{
4938	SVGAFifoCmdDefineGMR2 *pCmd;
4939	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
4940	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
4941	break;
4942	}
4943
4944	case SVGA_CMD_REMAP_GMR2:
4945	{
4946	/* Followed by page descriptors or guest ptr. */
4947	SVGAFifoCmdRemapGMR2 *pCmd;
4948	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
4949
4950	/* Calculate the size of what comes after next and fetch it. */
4951	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
4952	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4953	cbCmd += sizeof(SVGAGuestPtr);
4954	else
4955	{
4956	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
4957	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
4958	{
4959	cbCmd += cbPageDesc;
4960	pCmd->numPages = 1;
4961	}
4962	else
4963	{
4964	ASSERT_GUEST_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
4965	cbCmd += cbPageDesc * pCmd->numPages;
4966	}
4967	}
4968	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
4969	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
4970	# ifdef DEBUG_GMR_ACCESS
4971	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4972	# endif
4973	break;
4974	}
4975	# endif // VBOX_WITH_VMSVGA3D
4976	case SVGA_CMD_DEFINE_SCREEN:
4977	{
4978	/* The size of this command is specified by the guest and depends on capabilities. */
4979	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4980
4981	SVGAFifoCmdDefineScreen *pCmd;
4982	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4983	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4984	RT_UNTRUSTED_VALIDATED_FENCE();
4985
4986	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4987	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4988	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
4989	break;
4990	}
4991
4992	case SVGA_CMD_DESTROY_SCREEN:
4993	{
4994	SVGAFifoCmdDestroyScreen *pCmd;
4995	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4996	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
4997	break;
4998	}
4999
5000	case SVGA_CMD_DEFINE_GMRFB:
5001	{
5002	SVGAFifoCmdDefineGMRFB *pCmd;
5003	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
5004	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
5005	break;
5006	}
5007
5008	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
5009	{
5010	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
5011	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
5012	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
5013	break;
5014	}
5015
5016	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
5017	{
5018	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
5019	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
5020	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
5021	break;
5022	}
5023
5024	case SVGA_CMD_ANNOTATION_FILL:
5025	{
5026	SVGAFifoCmdAnnotationFill *pCmd;
5027	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
5028	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
5029	break;
5030	}
5031
5032	case SVGA_CMD_ANNOTATION_COPY:
5033	{
5034	SVGAFifoCmdAnnotationCopy *pCmd;
5035	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
5036	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
5037	break;
5038	}
5039
5040	default:
5041	# ifdef VBOX_WITH_VMSVGA3D
5042	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
5043	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
5044	{
5045	RT_UNTRUSTED_VALIDATED_FENCE();
5046
5047	/* All 3d commands start with a common header, which defines the identifier and the size
5048	* of the command. The identifier has been already read from FIFO. Fetch the size.
5049	*/
5050	uint32_t *pcbCmd;
5051	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pcbCmd, uint32_t, sizeof(*pcbCmd));
5052	uint32_t const cbCmd = *pcbCmd;
5053	AssertBreak(cbCmd < pThis->svga.cbFIFO);
5054	uint32_t *pu32Cmd;
5055	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pu32Cmd, uint32_t, sizeof(*pcbCmd) + cbCmd);
5056	pu32Cmd++; /* Skip the command size. */
5057
5058	if (RT_LIKELY(pThis->svga.f3DEnabled))
5059	{ /* likely */ }
5060	else
5061	{
5062	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", enmCmdId));
5063	break;
5064	}
5065
5066	vmsvgaR3Process3dCmd(pThis, pThisCC, SVGA3D_INVALID_ID, (SVGAFifo3dCmdId)enmCmdId, cbCmd, pu32Cmd);
5067	}
5068	else
5069	# endif // VBOX_WITH_VMSVGA3D
5070	{
5071	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
5072	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
5073	LogRelMax(16, ("VMSVGA: unsupported command %d\n", enmCmdId));
5074	}
5075	}
5076
5077	/* Go to the next slot */
5078	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
5079	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
5080	if (offCurrentCmd >= offFifoMax)
5081	{
5082	offCurrentCmd -= offFifoMax - offFifoMin;
5083	Assert(offCurrentCmd >= offFifoMin);
5084	Assert(offCurrentCmd < offFifoMax);
5085	}
5086	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
5087	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
5088
5089	/*
5090	* Raise IRQ if required. Must enter the critical section here
5091	* before making final decisions here, otherwise cubebench and
5092	* others may end up waiting forever.
5093	*/
5094	if ( u32IrqStatus
5095	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
5096	{
5097	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
5098	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
5099
5100	/* FIFO progress might trigger an interrupt. */
5101	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
5102	{
5103	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
5104	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
5105	}
5106
5107	/* Unmasked IRQ pending? */
5108	if (pThis->svga.u32IrqMask & u32IrqStatus)
5109	{
5110	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
5111	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
5112	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
5113	}
5114
5115	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5116	}
5117	}
5118
5119	/* If really done, clear the busy flag. */
5120	if (fDone)
5121	{
5122	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
5123	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
5124	}
5125	}
5126
5127	/*
5128	* Free the bounce buffer. (There are no returns above!)
5129	*/
5130	RTMemFree(pbBounceBuf);
5131
5132	return VINF_SUCCESS;
5133	}
5134
5135	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
5136	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
5137
5138	/**
5139	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5140	* Unblock the FIFO I/O thread so it can respond to a state change.}
5141	*/
5142	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5143	{
5144	RT_NOREF(pDevIns);
5145	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5146	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5147	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5148	}
5149
5150	/**
5151	* Enables or disables dirty page tracking for the framebuffer
5152	*
5153	* @param pDevIns The device instance.
5154	* @param pThis The shared VGA/VMSVGA instance data.
5155	* @param fTraces Enable/disable traces
5156	*/
5157	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5158	{
5159	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5160	&& !fTraces)
5161	{
5162	//Assert(pThis->svga.fTraces);
5163	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5164	return;
5165	}
5166
5167	pThis->svga.fTraces = fTraces;
5168	if (pThis->svga.fTraces)
5169	{
5170	unsigned cbFrameBuffer = pThis->vram_size;
5171
5172	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5173	/** @todo How does this work with screens? */
5174	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5175	{
5176	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5177	Assert(pThis->svga.cbScanline);
5178	# endif
5179	/* Hardware enabled; return real framebuffer size .*/
5180	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5181	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, GUEST_PAGE_SIZE);
5182	}
5183
5184	if (!pThis->svga.fVRAMTracking)
5185	{
5186	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5187	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5188	pThis->svga.fVRAMTracking = true;
5189	}
5190	}
5191	else
5192	{
5193	if (pThis->svga.fVRAMTracking)
5194	{
5195	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5196	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5197	pThis->svga.fVRAMTracking = false;
5198	}
5199	}
5200	}
5201
5202	/**
5203	* @callback_method_impl{FNPCIIOREGIONMAP}
5204	*/
5205	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5206	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5207	{
5208	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5209	int rc;
5210	RT_NOREF(pPciDev);
5211	Assert(pPciDev == pDevIns->apPciDevs[0]);
5212
5213	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5214	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5215	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5216	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5217	, VERR_INTERNAL_ERROR);
5218	if (GCPhysAddress != NIL_RTGCPHYS)
5219	{
5220	/*
5221	* Mapping the FIFO RAM.
5222	*/
5223	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5224	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5225	AssertRC(rc);
5226
5227	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5228	if (RT_SUCCESS(rc))
5229	{
5230	rc = PDMDevHlpPGMHandlerPhysicalRegister(pDevIns, GCPhysAddress,
5231	# ifdef DEBUG_FIFO_ACCESS
5232	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5233	# else
5234	GCPhysAddress + GUEST_PAGE_SIZE - 1,
5235	# endif
5236	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5237	"VMSVGA FIFO");
5238	AssertRC(rc);
5239	}
5240	# endif
5241	if (RT_SUCCESS(rc))
5242	{
5243	pThis->svga.GCPhysFIFO = GCPhysAddress;
5244	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5245	}
5246	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite errors here. */
5247	}
5248	else
5249	{
5250	Assert(pThis->svga.GCPhysFIFO);
5251	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5252	rc = PDMDevHlpPGMHandlerPhysicalDeregister(pDevIns, pThis->svga.GCPhysFIFO);
5253	AssertRC(rc);
5254	# else
5255	rc = VINF_SUCCESS;
5256	# endif
5257	pThis->svga.GCPhysFIFO = 0;
5258	}
5259	return rc;
5260	}
5261
5262	# ifdef VBOX_WITH_VMSVGA3D
5263
5264	/**
5265	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5266	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5267	*
5268	* @param pDevIns The device instance.
5269	* @param pThis The The shared VGA/VMSVGA instance data.
5270	* @param pThisCC The VGA/VMSVGA state for ring-3.
5271	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5272	* UINT32_MAX is used, all surfaces are processed.
5273	*/
5274	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5275	{
5276	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5277	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5278	}
5279
5280
5281	/**
5282	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5283	*/
5284	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5285	{
5286	/* There might be a specific surface ID at the start of the
5287	arguments, if not show all surfaces. */
5288	uint32_t sid = UINT32_MAX;
5289	if (pszArgs)
5290	pszArgs = RTStrStripL(pszArgs);
5291	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5292	sid = RTStrToUInt32(pszArgs);
5293
5294	/* Verbose or terse display, we default to verbose. */
5295	bool fVerbose = true;
5296	if (RTStrIStr(pszArgs, "terse"))
5297	fVerbose = false;
5298
5299	/* The size of the ascii art (x direction, y is 3/4 of x). */
5300	uint32_t cxAscii = 80;
5301	if (RTStrIStr(pszArgs, "gigantic"))
5302	cxAscii = 300;
5303	else if (RTStrIStr(pszArgs, "huge"))
5304	cxAscii = 180;
5305	else if (RTStrIStr(pszArgs, "big"))
5306	cxAscii = 132;
5307	else if (RTStrIStr(pszArgs, "normal"))
5308	cxAscii = 80;
5309	else if (RTStrIStr(pszArgs, "medium"))
5310	cxAscii = 64;
5311	else if (RTStrIStr(pszArgs, "small"))
5312	cxAscii = 48;
5313	else if (RTStrIStr(pszArgs, "tiny"))
5314	cxAscii = 24;
5315
5316	/* Y invert the image when producing the ASCII art. */
5317	bool fInvY = false;
5318	if (RTStrIStr(pszArgs, "invy"))
5319	fInvY = true;
5320
5321	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5322	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5323	}
5324
5325
5326	/**
5327	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5328	*/
5329	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5330	{
5331	/* pszArg = "sid[>dir]"
5332	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5333	*/
5334	char *pszBitmapPath = NULL;
5335	uint32_t sid = UINT32_MAX;
5336	if (pszArgs)
5337	pszArgs = RTStrStripL(pszArgs);
5338	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5339	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5340	if ( pszBitmapPath
5341	&& *pszBitmapPath == '>')
5342	++pszBitmapPath;
5343
5344	const bool fVerbose = true;
5345	const uint32_t cxAscii = 0; /* No ASCII */
5346	const bool fInvY = false; /* Do not invert. */
5347	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5348	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5349	}
5350
5351	/**
5352	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5353	*/
5354	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5355	{
5356	/* There might be a specific surface ID at the start of the
5357	arguments, if not show all contexts. */
5358	uint32_t sid = UINT32_MAX;
5359	if (pszArgs)
5360	pszArgs = RTStrStripL(pszArgs);
5361	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5362	sid = RTStrToUInt32(pszArgs);
5363
5364	/* Verbose or terse display, we default to verbose. */
5365	bool fVerbose = true;
5366	if (RTStrIStr(pszArgs, "terse"))
5367	fVerbose = false;
5368
5369	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5370	}
5371	# endif /* VBOX_WITH_VMSVGA3D */
5372
5373	/**
5374	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5375	*/
5376	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5377	{
5378	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5379	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5380	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5381	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5382	RT_NOREF(pszArgs);
5383
5384	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5385	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5386	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5387	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5388	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5389	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5390	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5391	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5392	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5393	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5394	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5395	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5396	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5397	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5398	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5399	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5400	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5401	pHlp->pfnPrintf(pHlp, "Device Capabilites: %#x\n", pThis->svga.u32DeviceCaps);
5402	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5403	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5404	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5405	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5406	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5407	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5408	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5409
5410	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5411	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5412	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5413	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5414
5415	pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
5416	pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
5417
5418	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
5419	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
5420
5421	# ifdef VBOX_WITH_VMSVGA3D
5422	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5423	# endif
5424	if (pThisCC->pDrv)
5425	{
5426	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5427	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5428	}
5429
5430	/* Dump screen information. */
5431	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5432	{
5433	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5434	if (pScreen)
5435	{
5436	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5437	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5438	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5439	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5440	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5441	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5442	{
5443	pHlp->pfnPrintf(pHlp, " (");
5444	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5445	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5446	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5447	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5448	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5449	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5450	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5451	pHlp->pfnPrintf(pHlp, " BLANKING");
5452	pHlp->pfnPrintf(pHlp, " )");
5453	}
5454	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5455	}
5456	}
5457
5458	}
5459
5460	static int vmsvgaR3LoadBufCtx(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM, PVMSVGACMDBUFCTX pBufCtx, SVGACBContext CBCtx)
5461	{
5462	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5463	PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
5464
5465	uint32_t cSubmitted;
5466	int rc = pHlp->pfnSSMGetU32(pSSM, &cSubmitted);
5467	AssertLogRelRCReturn(rc, rc);
5468
5469	for (uint32_t i = 0; i < cSubmitted; ++i)
5470	{
5471	PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pBufCtx);
5472	AssertPtrReturn(pCmdBuf, VERR_NO_MEMORY);
5473
5474	pHlp->pfnSSMGetGCPhys(pSSM, &pCmdBuf->GCPhysCB);
5475
5476	uint32_t u32;
5477	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
5478	AssertRCReturn(rc, rc);
5479	AssertReturn(u32 == sizeof(SVGACBHeader), VERR_INVALID_STATE);
5480	pHlp->pfnSSMGetMem(pSSM, &pCmdBuf->hdr, sizeof(SVGACBHeader));
5481
5482	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
5483	AssertRCReturn(rc, rc);
5484	AssertReturn(u32 == pCmdBuf->hdr.length, VERR_INVALID_STATE);
5485
5486	if (pCmdBuf->hdr.length)
5487	{
5488	pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
5489	AssertPtrReturn(pCmdBuf->pvCommands, VERR_NO_MEMORY);
5490
5491	rc = pHlp->pfnSSMGetMem(pSSM, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
5492	AssertRCReturn(rc, rc);
5493	}
5494
5495	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
5496	{
5497	vmsvgaR3CmdBufSubmitCtx(pDevIns, pThis, pThisCC, &pCmdBuf);
5498	}
5499	else
5500	{
5501	uint32_t offNextCmd = 0;
5502	vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
5503	}
5504
5505	/* Free the buffer if CmdBufSubmit* did not consume it. */
5506	vmsvgaR3CmdBufFree(pCmdBuf);
5507	}
5508	return rc;
5509	}
5510
5511	static int vmsvgaR3LoadGbo(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, VMSVGAGBO *pGbo)
5512	{
5513	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5514
5515	int rc;
5516	pHlp->pfnSSMGetU32(pSSM, &pGbo->fGboFlags);
5517	pHlp->pfnSSMGetU32(pSSM, &pGbo->cTotalPages);
5518	pHlp->pfnSSMGetU32(pSSM, &pGbo->cbTotal);
5519	rc = pHlp->pfnSSMGetU32(pSSM, &pGbo->cDescriptors);
5520	AssertRCReturn(rc, rc);
5521
5522	if (pGbo->cDescriptors)
5523	{
5524	pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAllocZ(pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
5525	AssertPtrReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
5526	}
5527
5528	for (uint32_t iDesc = 0; iDesc < pGbo->cDescriptors; ++iDesc)
5529	{
5530	PVMSVGAGBODESCRIPTOR pDesc = &pGbo->paDescriptors[iDesc];
5531	pHlp->pfnSSMGetGCPhys(pSSM, &pDesc->GCPhys);
5532	rc = pHlp->pfnSSMGetU64(pSSM, &pDesc->cPages);
5533	}
5534
5535	if (pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED)
5536	{
5537	pGbo->pvHost = RTMemAlloc(pGbo->cbTotal);
5538	AssertPtrReturn(pGbo->pvHost, VERR_NO_MEMORY);
5539	rc = pHlp->pfnSSMGetMem(pSSM, pGbo->pvHost, pGbo->cbTotal);
5540	}
5541
5542	return rc;
5543	}
5544
5545	/**
5546	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5547	*/
5548	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5549	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5550	{
5551	RT_NOREF(uPass);
5552
5553	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5554	int rc;
5555
5556	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5557	{
5558	uint32_t cScreens = 0;
5559	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5560	AssertRCReturn(rc, rc);
5561	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5562	("cScreens=%#x\n", cScreens),
5563	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5564
5565	for (uint32_t i = 0; i < cScreens; ++i)
5566	{
5567	VMSVGASCREENOBJECT screen;
5568	RT_ZERO(screen);
5569
5570	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5571	AssertLogRelRCReturn(rc, rc);
5572
5573	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5574	{
5575	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5576	*pScreen = screen;
5577	pScreen->fModified = true;
5578
5579	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_DX)
5580	{
5581	uint32_t u32;
5582	pHlp->pfnSSMGetU32(pSSM, &u32); /* Size of screen bitmap. */
5583	AssertLogRelRCReturn(rc, rc);
5584	if (u32)
5585	{
5586	pScreen->pvScreenBitmap = RTMemAlloc(u32);
5587	AssertPtrReturn(pScreen->pvScreenBitmap, VERR_NO_MEMORY);
5588
5589	pHlp->pfnSSMGetMem(pSSM, pScreen->pvScreenBitmap, u32);
5590	}
5591	}
5592	}
5593	else
5594	{
5595	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5596	}
5597	}
5598	}
5599	else
5600	{
5601	/* Try to setup at least the first screen. */
5602	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5603	pScreen->fDefined = true;
5604	pScreen->fModified = true;
5605	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5606	pScreen->idScreen = 0;
5607	pScreen->xOrigin = 0;
5608	pScreen->yOrigin = 0;
5609	pScreen->offVRAM = pThis->svga.uScreenOffset;
5610	pScreen->cbPitch = pThis->svga.cbScanline;
5611	pScreen->cWidth = pThis->svga.uWidth;
5612	pScreen->cHeight = pThis->svga.uHeight;
5613	pScreen->cBpp = pThis->svga.uBpp;
5614	}
5615
5616	return VINF_SUCCESS;
5617	}
5618
5619	/**
5620	* @copydoc FNSSMDEVLOADEXEC
5621	*/
5622	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5623	{
5624	RT_NOREF(uPass);
5625	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5626	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5627	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5628	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5629	int rc;
5630
5631	/* Load our part of the VGAState */
5632	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5633	AssertRCReturn(rc, rc);
5634
5635	/* Load the VGA framebuffer. */
5636	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5637	uint32_t cbVgaFramebuffer = _32K;
5638	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5639	{
5640	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5641	AssertRCReturn(rc, rc);
5642	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5643	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5644	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5645	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5646	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5647	}
5648	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5649	AssertRCReturn(rc, rc);
5650	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5651	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5652	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5653	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5654
5655	/* Load the VMSVGA state. */
5656	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5657	AssertRCReturn(rc, rc);
5658
5659	/* Load the active cursor bitmaps. */
5660	if (pSVGAState->Cursor.fActive)
5661	{
5662	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5663	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5664
5665	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5666	AssertRCReturn(rc, rc);
5667	}
5668
5669	/* Load the GMR state. */
5670	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5671	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5672	{
5673	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5674	AssertRCReturn(rc, rc);
5675	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5676	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5677	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5678	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5679	}
5680
5681	if (pThis->svga.cGMR != cGMR)
5682	{
5683	/* Reallocate GMR array. */
5684	Assert(pSVGAState->paGMR != NULL);
5685	RTMemFree(pSVGAState->paGMR);
5686	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5687	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5688	pThis->svga.cGMR = cGMR;
5689	}
5690
5691	for (uint32_t i = 0; i < cGMR; ++i)
5692	{
5693	PGMR pGMR = &pSVGAState->paGMR[i];
5694
5695	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5696	AssertRCReturn(rc, rc);
5697
5698	if (pGMR->numDescriptors)
5699	{
5700	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5701	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5702	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5703
5704	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5705	{
5706	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5707	AssertRCReturn(rc, rc);
5708	}
5709	}
5710	}
5711
5712	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_DX)
5713	{
5714	bool f;
5715	uint32_t u32;
5716
5717	rc = pHlp->pfnSSMGetBool(pSSM, &f);
5718	AssertLogRelRCReturn(rc, rc);
5719	AssertReturn(f == pThis->fVMSVGA10, VERR_INVALID_STATE);
5720
5721	if (pThis->fVMSVGA10)
5722	{
5723	/* Device context command buffers. */
5724	rc = vmsvgaR3LoadBufCtx(pDevIns, pThis, pThisCC, pSSM, &pSVGAState->CmdBufCtxDC, SVGA_CB_CONTEXT_MAX);
5725	AssertLogRelRCReturn(rc, rc);
5726
5727	/* DX contexts command buffers. */
5728	uint32_t cBufCtx;
5729	rc = pHlp->pfnSSMGetU32(pSSM, &cBufCtx);
5730	AssertLogRelRCReturn(rc, rc);
5731	AssertReturn(cBufCtx == RT_ELEMENTS(pSVGAState->apCmdBufCtxs), VERR_INVALID_STATE);
5732	for (uint32_t j = 0; j < cBufCtx; ++j)
5733	{
5734	rc = pHlp->pfnSSMGetBool(pSSM, &f);
5735	AssertLogRelRCReturn(rc, rc);
5736	if (f)
5737	{
5738	pSVGAState->apCmdBufCtxs[j] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
5739	AssertPtrReturn(pSVGAState->apCmdBufCtxs[j], VERR_NO_MEMORY);
5740	vmsvgaR3CmdBufCtxInit(pSVGAState->apCmdBufCtxs[j]);
5741
5742	rc = vmsvgaR3LoadBufCtx(pDevIns, pThis, pThisCC, pSSM, pSVGAState->apCmdBufCtxs[j], (SVGACBContext)j);
5743	AssertLogRelRCReturn(rc, rc);
5744	}
5745	}
5746
5747	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
5748	pSVGAState->fCmdBuf = u32;
5749
5750	/*
5751	* OTables GBOs.
5752	*/
5753	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
5754	AssertLogRelRCReturn(rc, rc);
5755	AssertReturn(u32 == SVGA_OTABLE_MAX, VERR_INVALID_STATE);
5756	for (int i = 0; i < SVGA_OTABLE_MAX; ++i)
5757	{
5758	VMSVGAGBO *pGbo = &pSVGAState->aGboOTables[i];
5759	rc = vmsvgaR3LoadGbo(pDevIns, pSSM, pGbo);
5760	AssertRCReturn(rc, rc);
5761	}
5762
5763	/*
5764	* MOBs.
5765	*/
5766	for (;;)
5767	{
5768	rc = pHlp->pfnSSMGetU32(pSSM, &u32); /* MOB id. */
5769	AssertRCReturn(rc, rc);
5770	if (u32 == SVGA_ID_INVALID)
5771	break;
5772
5773	PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
5774	AssertPtrReturn(pMob, VERR_NO_MEMORY);
5775
5776	rc = vmsvgaR3LoadGbo(pDevIns, pSSM, &pMob->Gbo);
5777	AssertRCReturn(rc, rc);
5778
5779	pMob->Core.Key = u32;
5780	if (RTAvlU32Insert(&pSVGAState->MOBTree, &pMob->Core))
5781	RTListPrepend(&pSVGAState->MOBLRUList, &pMob->nodeLRU);
5782	else
5783	AssertFailedReturn(VERR_NO_MEMORY);
5784	}
5785
5786	# ifdef VMSVGA3D_DX
5787	if (pThis->svga.f3DEnabled)
5788	{
5789	pHlp->pfnSSMGetU32(pSSM, &pSVGAState->idDXContextCurrent);
5790	}
5791	# endif
5792	}
5793	}
5794
5795	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5796	if (pThis->svga.f3DEnabled)
5797	pSVGAState->pFuncs3D->pfnPowerOn(pDevIns, pThis, pThisCC);
5798	# endif
5799
5800	VMSVGA_STATE_LOAD LoadState;
5801	LoadState.pSSM = pSSM;
5802	LoadState.uVersion = uVersion;
5803	LoadState.uPass = uPass;
5804	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5805	AssertLogRelRCReturn(rc, rc);
5806
5807	return VINF_SUCCESS;
5808	}
5809
5810	/**
5811	* Reinit the video mode after the state has been loaded.
5812	*/
5813	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5814	{
5815	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5816	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5817	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5818
5819	/* VMSVGA is working via VBVA interface, therefore it needs to be
5820	* enabled on saved state restore. See @bugref{10071#c7}. */
5821	if (pThis->svga.fEnabled)
5822	{
5823	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
5824	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
5825	}
5826
5827	/* Set the active cursor. */
5828	if (pSVGAState->Cursor.fActive)
5829	{
5830	/* We don't store the alpha flag, but we can take a guess that if
5831	* the old register interface was used, the cursor was B&W.
5832	*/
5833	bool fAlpha = pThis->svga.uCursorOn ? false : true;
5834
5835	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
5836	true /fVisible/,
5837	fAlpha,
5838	pSVGAState->Cursor.xHotspot,
5839	pSVGAState->Cursor.yHotspot,
5840	pSVGAState->Cursor.width,
5841	pSVGAState->Cursor.height,
5842	pSVGAState->Cursor.pData);
5843	AssertRC(rc);
5844
5845	if (pThis->svga.uCursorOn)
5846	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
5847	}
5848
5849	/* If the VRAM handler should not be registered, we have to explicitly
5850	* unregister it here!
5851	*/
5852	if (!pThis->svga.fVRAMTracking)
5853	{
5854	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5855	}
5856
5857	/* Let the FIFO thread deal with changing the mode. */
5858	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5859
5860	return VINF_SUCCESS;
5861	}
5862
5863	static int vmsvgaR3SaveBufCtx(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PVMSVGACMDBUFCTX pBufCtx)
5864	{
5865	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5866
5867	int rc = pHlp->pfnSSMPutU32(pSSM, pBufCtx->cSubmitted);
5868	AssertLogRelRCReturn(rc, rc);
5869	if (pBufCtx->cSubmitted)
5870	{
5871	PVMSVGACMDBUF pIter;
5872	RTListForEach(&pBufCtx->listSubmitted, pIter, VMSVGACMDBUF, nodeBuffer)
5873	{
5874	pHlp->pfnSSMPutGCPhys(pSSM, pIter->GCPhysCB);
5875	pHlp->pfnSSMPutU32(pSSM, sizeof(SVGACBHeader));
5876	pHlp->pfnSSMPutMem(pSSM, &pIter->hdr, sizeof(SVGACBHeader));
5877	pHlp->pfnSSMPutU32(pSSM, pIter->hdr.length);
5878	if (pIter->hdr.length)
5879	rc = pHlp->pfnSSMPutMem(pSSM, pIter->pvCommands, pIter->hdr.length);
5880	AssertLogRelRCReturn(rc, rc);
5881	}
5882	}
5883	return rc;
5884	}
5885
5886	static int vmsvgaR3SaveGbo(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, VMSVGAGBO *pGbo)
5887	{
5888	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5889
5890	int rc;
5891	pHlp->pfnSSMPutU32(pSSM, pGbo->fGboFlags);
5892	pHlp->pfnSSMPutU32(pSSM, pGbo->cTotalPages);
5893	pHlp->pfnSSMPutU32(pSSM, pGbo->cbTotal);
5894	rc = pHlp->pfnSSMPutU32(pSSM, pGbo->cDescriptors);
5895	for (uint32_t iDesc = 0; iDesc < pGbo->cDescriptors; ++iDesc)
5896	{
5897	PVMSVGAGBODESCRIPTOR pDesc = &pGbo->paDescriptors[iDesc];
5898	pHlp->pfnSSMPutGCPhys(pSSM, pDesc->GCPhys);
5899	rc = pHlp->pfnSSMPutU64(pSSM, pDesc->cPages);
5900	}
5901	if (pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED)
5902	rc = pHlp->pfnSSMPutMem(pSSM, pGbo->pvHost, pGbo->cbTotal);
5903	return rc;
5904	}
5905
5906	/**
5907	* Portion of SVGA state which must be saved in the FIFO thread.
5908	*/
5909	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5910	{
5911	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5912	int rc;
5913
5914	/* Save the screen objects. */
5915	/* Count defined screen object. */
5916	uint32_t cScreens = 0;
5917	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5918	{
5919	if (pSVGAState->aScreens[i].fDefined)
5920	++cScreens;
5921	}
5922
5923	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5924	AssertLogRelRCReturn(rc, rc);
5925
5926	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5927	{
5928	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5929	if (!pScreen->fDefined)
5930	continue;
5931
5932	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5933	AssertLogRelRCReturn(rc, rc);
5934
5935	/*
5936	* VGA_SAVEDSTATE_VERSION_VMSVGA_DX
5937	*/
5938	if (pScreen->pvScreenBitmap)
5939	{
5940	uint32_t const cbScreenBitmap = pScreen->cHeight * pScreen->cbPitch;
5941	pHlp->pfnSSMPutU32(pSSM, cbScreenBitmap);
5942	pHlp->pfnSSMPutMem(pSSM, pScreen->pvScreenBitmap, cbScreenBitmap);
5943	}
5944	else
5945	pHlp->pfnSSMPutU32(pSSM, 0);
5946	}
5947	return VINF_SUCCESS;
5948	}
5949
5950	/**
5951	* @copydoc FNSSMDEVSAVEEXEC
5952	*/
5953	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5954	{
5955	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5956	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5957	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5958	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5959	int rc;
5960
5961	/* Save our part of the VGAState */
5962	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5963	AssertLogRelRCReturn(rc, rc);
5964
5965	/* Save the framebuffer backup. */
5966	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5967	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5968	AssertLogRelRCReturn(rc, rc);
5969
5970	/* Save the VMSVGA state. */
5971	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5972	AssertLogRelRCReturn(rc, rc);
5973
5974	/* Save the active cursor bitmaps. */
5975	if (pSVGAState->Cursor.fActive)
5976	{
5977	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5978	AssertLogRelRCReturn(rc, rc);
5979	}
5980
5981	/* Save the GMR state */
5982	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5983	AssertLogRelRCReturn(rc, rc);
5984	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5985	{
5986	PGMR pGMR = &pSVGAState->paGMR[i];
5987
5988	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5989	AssertLogRelRCReturn(rc, rc);
5990
5991	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5992	{
5993	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5994	AssertLogRelRCReturn(rc, rc);
5995	}
5996	}
5997
5998	/*
5999	* VGA_SAVEDSTATE_VERSION_VMSVGA_DX
6000	*/
6001
6002	rc = pHlp->pfnSSMPutBool(pSSM, pThis->fVMSVGA10);
6003	AssertLogRelRCReturn(rc, rc);
6004
6005	if (pThis->fVMSVGA10)
6006	{
6007	/* Device context command buffers. */
6008	rc = vmsvgaR3SaveBufCtx(pDevIns, pSSM, &pSVGAState->CmdBufCtxDC);
6009	AssertRCReturn(rc, rc);
6010
6011	/* DX contexts command buffers. */
6012	rc = pHlp->pfnSSMPutU32(pSSM, RT_ELEMENTS(pSVGAState->apCmdBufCtxs));
6013	AssertLogRelRCReturn(rc, rc);
6014	for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->apCmdBufCtxs); ++i)
6015	{
6016	if (pSVGAState->apCmdBufCtxs[i])
6017	{
6018	pHlp->pfnSSMPutBool(pSSM, true);
6019	rc = vmsvgaR3SaveBufCtx(pDevIns, pSSM, pSVGAState->apCmdBufCtxs[i]);
6020	AssertRCReturn(rc, rc);
6021	}
6022	else
6023	pHlp->pfnSSMPutBool(pSSM, false);
6024	}
6025
6026	rc = pHlp->pfnSSMPutU32(pSSM, pSVGAState->fCmdBuf);
6027	AssertRCReturn(rc, rc);
6028
6029	/*
6030	* OTables GBOs.
6031	*/
6032	pHlp->pfnSSMPutU32(pSSM, SVGA_OTABLE_MAX);
6033	for (int i = 0; i < SVGA_OTABLE_MAX; ++i)
6034	{
6035	VMSVGAGBO *pGbo = &pSVGAState->aGboOTables[i];
6036	rc = vmsvgaR3SaveGbo(pDevIns, pSSM, pGbo);
6037	AssertRCReturn(rc, rc);
6038	}
6039
6040	/*
6041	* MOBs.
6042	*/
6043	PVMSVGAMOB pIter;
6044	RTListForEach(&pSVGAState->MOBLRUList, pIter, VMSVGAMOB, nodeLRU)
6045	{
6046	pHlp->pfnSSMPutU32(pSSM, pIter->Core.Key); /* MOB id. */
6047	rc = vmsvgaR3SaveGbo(pDevIns, pSSM, &pIter->Gbo);
6048	AssertRCReturn(rc, rc);
6049	}
6050
6051	pHlp->pfnSSMPutU32(pSSM, SVGA_ID_INVALID); /* End marker. */
6052
6053	# ifdef VMSVGA3D_DX
6054	if (pThis->svga.f3DEnabled)
6055	{
6056	pHlp->pfnSSMPutU32(pSSM, pSVGAState->idDXContextCurrent);
6057	}
6058	# endif
6059	}
6060
6061	/*
6062	* Must save some state (3D in particular) in the FIFO thread.
6063	*/
6064	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
6065	AssertLogRelRCReturn(rc, rc);
6066
6067	return VINF_SUCCESS;
6068	}
6069
6070	/**
6071	* Destructor for PVMSVGAR3STATE structure. The structure is not deallocated.
6072	*
6073	* @param pThis The shared VGA/VMSVGA instance data.
6074	* @param pThisCC The device context.
6075	*/
6076	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVGASTATECC pThisCC)
6077	{
6078	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6079
6080	# ifndef VMSVGA_USE_EMT_HALT_CODE
6081	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
6082	{
6083	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
6084	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
6085	}
6086	# endif
6087
6088	if (pSVGAState->Cursor.fActive)
6089	{
6090	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6091	pSVGAState->Cursor.pData = NULL;
6092	pSVGAState->Cursor.fActive = false;
6093	}
6094
6095	if (pSVGAState->paGMR)
6096	{
6097	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
6098	if (pSVGAState->paGMR[i].paDesc)
6099	RTMemFree(pSVGAState->paGMR[i].paDesc);
6100
6101	RTMemFree(pSVGAState->paGMR);
6102	pSVGAState->paGMR = NULL;
6103	}
6104
6105	if (RTCritSectIsInitialized(&pSVGAState->CritSectCmdBuf))
6106	{
6107	RTCritSectEnter(&pSVGAState->CritSectCmdBuf);
6108	for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->apCmdBufCtxs); ++i)
6109	{
6110	vmsvgaR3CmdBufCtxTerm(pSVGAState->apCmdBufCtxs[i]);
6111	pSVGAState->apCmdBufCtxs[i] = NULL;
6112	}
6113	vmsvgaR3CmdBufCtxTerm(&pSVGAState->CmdBufCtxDC);
6114	RTCritSectLeave(&pSVGAState->CritSectCmdBuf);
6115	RTCritSectDelete(&pSVGAState->CritSectCmdBuf);
6116	}
6117	}
6118
6119	/**
6120	* Constructor for PVMSVGAR3STATE structure.
6121	*
6122	* @returns VBox status code.
6123	* @param pDevIns The PDM device instance.
6124	* @param pThis The shared VGA/VMSVGA instance data.
6125	* @param pSVGAState Pointer to the structure. It is already allocated.
6126	*/
6127	static int vmsvgaR3StateInit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
6128	{
6129	int rc = VINF_SUCCESS;
6130
6131	pSVGAState->pDevIns = pDevIns;
6132
6133	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
6134	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
6135
6136	# ifndef VMSVGA_USE_EMT_HALT_CODE
6137	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
6138	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
6139	AssertRCReturn(rc, rc);
6140	# endif
6141
6142	rc = RTCritSectInit(&pSVGAState->CritSectCmdBuf);
6143	AssertRCReturn(rc, rc);
6144
6145	vmsvgaR3CmdBufCtxInit(&pSVGAState->CmdBufCtxDC);
6146
6147	RTListInit(&pSVGAState->MOBLRUList);
6148	# ifdef VBOX_WITH_VMSVGA3D
6149	# ifdef VMSVGA3D_DX
6150	pSVGAState->idDXContextCurrent = SVGA3D_INVALID_ID;
6151	# endif
6152	# endif
6153	return rc;
6154	}
6155
6156	# ifdef VBOX_WITH_VMSVGA3D
6157	static void vmsvga3dR3Free3dInterfaces(PVGASTATECC pThisCC)
6158	{
6159	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6160
6161	RTMemFree(pSVGAState->pFuncsMap);
6162	pSVGAState->pFuncsMap = NULL;
6163	RTMemFree(pSVGAState->pFuncsGBO);
6164	pSVGAState->pFuncsGBO = NULL;
6165	RTMemFree(pSVGAState->pFuncsDX);
6166	pSVGAState->pFuncsDX = NULL;
6167	RTMemFree(pSVGAState->pFuncsVGPU9);
6168	pSVGAState->pFuncsVGPU9 = NULL;
6169	RTMemFree(pSVGAState->pFuncs3D);
6170	pSVGAState->pFuncs3D = NULL;
6171	}
6172
6173	/* This structure is used only by vmsvgaR3Init3dInterfaces */
6174	typedef struct VMSVGA3DINTERFACE
6175	{
6176	char const *pcszName;
6177	uint32_t cbFuncs;
6178	void **ppvFuncs;
6179	} VMSVGA3DINTERFACE;
6180
6181	extern VMSVGA3DBACKENDDESC const g_BackendLegacy;
6182	#if defined(VMSVGA3D_DX_BACKEND)
6183	extern VMSVGA3DBACKENDDESC const g_BackendDX;
6184	#endif
6185
6186	/**
6187	* Initializes the optional host 3D backend interfaces.
6188	*
6189	* @returns VBox status code.
6190	* @param pThisCC The VGA/VMSVGA state for ring-3.
6191	*/
6192	static int vmsvgaR3Init3dInterfaces(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
6193	{
6194	#ifndef VMSVGA3D_DX
6195	RT_NOREF(pThis);
6196	#endif
6197
6198	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6199
6200	#define ENTRY_3D_INTERFACE(a_Name, a_Field) { VMSVGA3D_BACKEND_INTERFACE_NAME_##a_Name, sizeof(VMSVGA3DBACKENDFUNCS##a_Name), (void **)&pSVGAState->a_Field }
6201	VMSVGA3DINTERFACE a3dInterface[] =
6202	{
6203	ENTRY_3D_INTERFACE(3D, pFuncs3D),
6204	ENTRY_3D_INTERFACE(VGPU9, pFuncsVGPU9),
6205	ENTRY_3D_INTERFACE(DX, pFuncsDX),
6206	ENTRY_3D_INTERFACE(MAP, pFuncsMap),
6207	ENTRY_3D_INTERFACE(GBO, pFuncsGBO),
6208	};
6209	#undef ENTRY_3D_INTERFACE
6210
6211	VMSVGA3DBACKENDDESC const *pBackend = NULL;
6212	#if defined(VMSVGA3D_DX_BACKEND)
6213	if (pThis->fVMSVGA10)
6214	pBackend = &g_BackendDX;
6215	else
6216	#endif
6217	pBackend = &g_BackendLegacy;
6218
6219	int rc = VINF_SUCCESS;
6220	for (uint32_t i = 0; i < RT_ELEMENTS(a3dInterface); ++i)
6221	{
6222	VMSVGA3DINTERFACE *p = &a3dInterface[i];
6223
6224	int rc2 = pBackend->pfnQueryInterface(pThisCC, p->pcszName, NULL, p->cbFuncs);
6225	if (RT_SUCCESS(rc2))
6226	{
6227	*p->ppvFuncs = RTMemAllocZ(p->cbFuncs);
6228	AssertBreakStmt(*p->ppvFuncs, rc = VERR_NO_MEMORY);
6229
6230	pBackend->pfnQueryInterface(pThisCC, p->pcszName, *p->ppvFuncs, p->cbFuncs);
6231	}
6232	}
6233
6234	if (RT_SUCCESS(rc))
6235	{
6236	/* 3D interface is required. */
6237	if (pSVGAState->pFuncs3D)
6238	{
6239	rc = pSVGAState->pFuncs3D->pfnInit(pDevIns, pThis, pThisCC);
6240	if (RT_SUCCESS(rc))
6241	return VINF_SUCCESS;
6242	}
6243	else
6244	rc = VERR_NOT_SUPPORTED;
6245	}
6246
6247	vmsvga3dR3Free3dInterfaces(pThisCC);
6248	return rc;
6249	}
6250	# endif /* VBOX_WITH_VMSVGA3D */
6251
6252	/**
6253	* Initializes the host capabilities: device and FIFO.
6254	*
6255	* @returns VBox status code.
6256	* @param pThis The shared VGA/VMSVGA instance data.
6257	* @param pThisCC The VGA/VMSVGA state for ring-3.
6258	*/
6259	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
6260	{
6261	# ifdef VBOX_WITH_VMSVGA3D
6262	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6263	# endif
6264
6265	/* Device caps. */
6266	pThis->svga.u32DeviceCaps = SVGA_CAP_GMR
6267	\| SVGA_CAP_GMR2
6268	\| SVGA_CAP_CURSOR
6269	\| SVGA_CAP_CURSOR_BYPASS
6270	\| SVGA_CAP_CURSOR_BYPASS_2
6271	\| SVGA_CAP_EXTENDED_FIFO
6272	\| SVGA_CAP_IRQMASK
6273	\| SVGA_CAP_PITCHLOCK
6274	\| SVGA_CAP_RECT_COPY
6275	\| SVGA_CAP_TRACES
6276	\| SVGA_CAP_SCREEN_OBJECT_2
6277	\| SVGA_CAP_ALPHA_CURSOR;
6278
6279	/* VGPU10 capabilities. */
6280	if (pThis->fVMSVGA10)
6281	{
6282	pThis->svga.u32DeviceCaps \|= SVGA_CAP_COMMAND_BUFFERS /* Enable register based command buffer submission. */
6283	// \| SVGA_CAP_CMD_BUFFERS_2 /* Support for SVGA_REG_CMD_PREPEND_LOW/HIGH */
6284	;
6285
6286	# ifdef VBOX_WITH_VMSVGA3D
6287	if (pSVGAState->pFuncsGBO)
6288	pThis->svga.u32DeviceCaps \|= SVGA_CAP_GBOBJECTS; /* Enable guest-backed objects and surfaces. */
6289	if (pSVGAState->pFuncsDX)
6290	pThis->svga.u32DeviceCaps \|= SVGA_CAP_DX; /* Enable support for DX commands, and command buffers in a mob. */
6291	# endif
6292	}
6293
6294	# ifdef VBOX_WITH_VMSVGA3D
6295	if (pSVGAState->pFuncs3D)
6296	pThis->svga.u32DeviceCaps \|= SVGA_CAP_3D;
6297	# endif
6298
6299	/* Clear the FIFO. */
6300	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
6301
6302	/* Setup FIFO capabilities. */
6303	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
6304	\| SVGA_FIFO_CAP_PITCHLOCK
6305	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
6306	\| SVGA_FIFO_CAP_RESERVE
6307	\| SVGA_FIFO_CAP_GMR2
6308	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
6309	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
6310
6311	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
6312	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
6313	}
6314
6315	# ifdef VBOX_WITH_VMSVGA3D
6316	/**
6317	* Initializes the host 3D capabilities and writes them to FIFO memory.
6318	*
6319	* @returns VBox status code.
6320	* @param pThis The shared VGA/VMSVGA instance data.
6321	* @param pThisCC The VGA/VMSVGA state for ring-3.
6322	*/
6323	static void vmsvgaR3InitFifo3DCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
6324	{
6325	/* Query the capabilities and store them in the pThis->svga.au32DevCaps array. */
6326	bool const fSavedBuffering = RTLogRelSetBuffering(true);
6327
6328	for (unsigned i = 0; i < RT_ELEMENTS(pThis->svga.au32DevCaps); ++i)
6329	{
6330	uint32_t val = 0;
6331	int rc = vmsvga3dQueryCaps(pThisCC, (SVGA3dDevCapIndex)i, &val);
6332	if (RT_SUCCESS(rc))
6333	pThis->svga.au32DevCaps[i] = val;
6334	else
6335	pThis->svga.au32DevCaps[i] = 0;
6336
6337	/* LogRel the capability value. */
6338	if (i < SVGA3D_DEVCAP_MAX)
6339	{
6340	char const *pszDevCapName = &vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)i)[sizeof("SVGA3D_DEVCAP")];
6341	if (RT_SUCCESS(rc))
6342	{
6343	if ( i == SVGA3D_DEVCAP_MAX_POINT_SIZE
6344	\|\| i == SVGA3D_DEVCAP_MAX_LINE_WIDTH
6345	\|\| i == SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH)
6346	{
6347	float const fval = (float )&val;
6348	LogRel(("VMSVGA3d: cap[%u]=" FLOAT_FMT_STR " {%s}\n", i, FLOAT_FMT_ARGS(fval), pszDevCapName));
6349	}
6350	else
6351	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, pszDevCapName));
6352	}
6353	else
6354	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc {%s}\n", i, rc, pszDevCapName));
6355	}
6356	else
6357	LogRel(("VMSVGA3d: new cap[%u]=%#010x rc=%Rrc\n", i, val, rc));
6358	}
6359
6360	RTLogRelSetBuffering(fSavedBuffering);
6361
6362	/* 3d hardware version; latest and greatest */
6363	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6364	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6365
6366	/* Fill out 3d capabilities up to SVGA3D_DEVCAP_SURFACEFMT_ATI2 in the FIFO memory.
6367	* SVGA3D_DEVCAP_SURFACEFMT_ATI2 is the last capabiltiy for pre-SVGA_CAP_GBOBJECTS hardware.
6368	* If the VMSVGA device supports SVGA_CAP_GBOBJECTS capability, then the guest has to use SVGA_REG_DEV_CAP
6369	* register to query the devcaps. Older guests will still try to read the devcaps from FIFO.
6370	*/
6371	SVGA3dCapsRecord *pCaps;
6372	SVGA3dCapPair *pData;
6373
6374	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
6375	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6376	pData = (SVGA3dCapPair *)&pCaps->data;
6377
6378	AssertCompile(SVGA3D_DEVCAP_DEAD1 == SVGA3D_DEVCAP_SURFACEFMT_ATI2 + 1);
6379	for (unsigned i = 0; i < SVGA3D_DEVCAP_DEAD1; ++i)
6380	{
6381	pData[i][0] = i;
6382	pData[i][1] = pThis->svga.au32DevCaps[i];
6383	}
6384	pCaps->header.length = (sizeof(pCaps->header) + SVGA3D_DEVCAP_DEAD1 * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6385	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6386
6387	/* Mark end of record array (a zero word). */
6388	pCaps->header.length = 0;
6389	}
6390
6391	# endif
6392
6393	/**
6394	* Resets the SVGA hardware state
6395	*
6396	* @returns VBox status code.
6397	* @param pDevIns The device instance.
6398	*/
6399	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6400	{
6401	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6402	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6403	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6404
6405	/* Reset before init? */
6406	if (!pSVGAState)
6407	return VINF_SUCCESS;
6408
6409	Log(("vmsvgaR3Reset\n"));
6410
6411	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6412	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6413	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6414
6415	/* Reset other stuff. */
6416	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6417	RT_ZERO(pThis->svga.au32ScratchRegion);
6418
6419	ASMAtomicWriteBool(&pThis->svga.fBadGuest, false);
6420
6421	vmsvgaR3StateTerm(pThis, pThisCC);
6422	vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
6423
6424	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6425
6426	/* Initialize FIFO and register capabilities. */
6427	vmsvgaR3InitCaps(pThis, pThisCC);
6428
6429	# ifdef VBOX_WITH_VMSVGA3D
6430	if (pThis->svga.f3DEnabled)
6431	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
6432	# endif
6433
6434	/* VRAM tracking is enabled by default during bootup. */
6435	pThis->svga.fVRAMTracking = true;
6436	pThis->svga.fEnabled = false;
6437
6438	/* Invalidate current settings. */
6439	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6440	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6441	pThis->svga.uBpp = pThis->svga.uHostBpp;
6442	pThis->svga.cbScanline = 0;
6443	pThis->svga.u32PitchLock = 0;
6444
6445	return rc;
6446	}
6447
6448	/**
6449	* Cleans up the SVGA hardware state
6450	*
6451	* @returns VBox status code.
6452	* @param pDevIns The device instance.
6453	*/
6454	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6455	{
6456	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6457	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6458
6459	/*
6460	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6461	*/
6462	if (pThisCC->svga.pFIFOIOThread)
6463	{
6464	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6465	NULL /pvParam/, 30000 /ms/);
6466	AssertLogRelRC(rc);
6467
6468	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6469	AssertLogRelRC(rc);
6470	pThisCC->svga.pFIFOIOThread = NULL;
6471	}
6472
6473	/*
6474	* Destroy the special SVGA state.
6475	*/
6476	if (pThisCC->svga.pSvgaR3State)
6477	{
6478	vmsvgaR3StateTerm(pThis, pThisCC);
6479
6480	# ifdef VBOX_WITH_VMSVGA3D
6481	vmsvga3dR3Free3dInterfaces(pThisCC);
6482	# endif
6483
6484	RTMemFree(pThisCC->svga.pSvgaR3State);
6485	pThisCC->svga.pSvgaR3State = NULL;
6486	}
6487
6488	/*
6489	* Free our resources residing in the VGA state.
6490	*/
6491	if (pThisCC->svga.pbVgaFrameBufferR3)
6492	{
6493	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6494	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6495	}
6496	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6497	{
6498	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6499	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6500	}
6501	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6502	{
6503	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6504	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6505	}
6506
6507	return VINF_SUCCESS;
6508	}
6509
6510	static DECLCALLBACK(size_t) vmsvga3dFloatFormat(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
6511	const char pszType, void const pvValue,
6512	int cchWidth, int cchPrecision, unsigned fFlags, void *pvUser)
6513	{
6514	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
6515	double const v = (double )&pvValue;
6516	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, FLOAT_FMT_STR, FLOAT_FMT_ARGS(v));
6517	}
6518
6519	/**
6520	* Initialize the SVGA hardware state
6521	*
6522	* @returns VBox status code.
6523	* @param pDevIns The device instance.
6524	*/
6525	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6526	{
6527	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6528	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6529	PVMSVGAR3STATE pSVGAState;
6530	int rc;
6531
6532	rc = RTStrFormatTypeRegister("float", vmsvga3dFloatFormat, NULL);
6533	AssertMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_ALREADY_EXISTS, ("%Rrc\n", rc), rc);
6534
6535	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6536	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6537
6538	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6539
6540	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6541	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6542	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6543
6544	/* Create event semaphore. */
6545	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6546	AssertRCReturn(rc, rc);
6547
6548	/* Create event semaphore. */
6549	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6550	AssertRCReturn(rc, rc);
6551
6552	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
6553	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6554
6555	rc = vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
6556	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6557
6558	pSVGAState = pThisCC->svga.pSvgaR3State;
6559
6560	/* Register the write-protected GBO access handler type (no ring-0 callbacks here). */
6561	rc = PDMDevHlpPGMHandlerPhysicalTypeRegister(pDevIns, PGMPHYSHANDLERKIND_WRITE, vmsvgaR3GboAccessHandler,
6562	"VMSVGA GBO", &pSVGAState->hGboAccessHandlerType);
6563	AssertRCReturn(rc, rc);
6564
6565	# ifdef VBOX_WITH_VMSVGA3D
6566	if (pThis->svga.f3DEnabled)
6567	{
6568	/* Load a 3D backend. */
6569	rc = vmsvgaR3Init3dInterfaces(pDevIns, pThis, pThisCC);
6570	if (RT_FAILURE(rc))
6571	{
6572	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6573	pThis->svga.f3DEnabled = false;
6574	}
6575	}
6576	# endif
6577
6578	/* Initialize FIFO and register capabilities. */
6579	vmsvgaR3InitCaps(pThis, pThisCC);
6580
6581	/* VRAM tracking is enabled by default during bootup. */
6582	pThis->svga.fVRAMTracking = true;
6583
6584	/* Set up the host bpp. This value is as a default for the programmable
6585	* bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
6586	* exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
6587	* separated as SVGA_REG_HOST_BITS_PER_PIXEL.
6588	*
6589	* NB: The driver cBits value is currently constant for the lifetime of the
6590	* VM. If that changes, the host bpp logic might need revisiting.
6591	*/
6592	pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
6593
6594	/* Invalidate current settings. */
6595	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6596	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6597	pThis->svga.uBpp = pThis->svga.uHostBpp;
6598	pThis->svga.cbScanline = 0;
6599
6600	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_XRES;
6601	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_YRES;
6602	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6603	{
6604	pThis->svga.u32MaxWidth -= 256;
6605	pThis->svga.u32MaxHeight -= 256;
6606	}
6607	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6608
6609	# ifdef DEBUG_GMR_ACCESS
6610	/* Register the GMR access handler type. */
6611	rc = PDMDevHlpPGMHandlerPhysicalTypeRegister(pDevIns, PGMPHYSHANDLERKIND_WRITE, vmsvgaR3GmrAccessHandler,
6612	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6613	AssertRCReturn(rc, rc);
6614	# endif
6615
6616	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6617	/* Register the FIFO access handler type. In addition to debugging FIFO
6618	access, this is also used to facilitate extended fifo thread sleeps. */
6619	rc = PDMDevHlpPGMHandlerPhysicalTypeRegister(pDevIns,
6620	# ifdef DEBUG_FIFO_ACCESS
6621	PGMPHYSHANDLERKIND_ALL,
6622	# else
6623	PGMPHYSHANDLERKIND_WRITE,
6624	# endif
6625	vmsvgaR3FifoAccessHandler,
6626	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6627	AssertRCReturn(rc, rc);
6628	# endif
6629
6630	/* Create the async IO thread. */
6631	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6632	RTTHREADTYPE_IO, "VMSVGA FIFO");
6633	if (RT_FAILURE(rc))
6634	{
6635	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6636	return rc;
6637	}
6638
6639	/*
6640	* Statistics.
6641	*/
6642	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6643	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6644	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6645	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6646	# ifdef VBOX_WITH_STATISTICS
6647	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6648	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6649	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6650	# endif
6651	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6652	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6653	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6654	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6655	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6656	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6657	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6658	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6659	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6660	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6661	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6662	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6663	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6664	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6665	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6666	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6667	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6668	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6669	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6670	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6671	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6672	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6673	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6674	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6675	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6676	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6677	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6678	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6679	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6680	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6681	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6682	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6683	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6684	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6685	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6686	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6687	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6688	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6689	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6690	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6691	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6692	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
6693	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
6694	REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
6695	REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
6696	REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
6697	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6698	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6699	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6700	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6701	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6702	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6703	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6704	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6705	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6706	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6707	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6708	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6709	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6710
6711	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6712	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6713	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6714	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6715	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6716	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6717	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
6718	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
6719	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) writes.");
6720	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
6721	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6722	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6723	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6724	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6725	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6726	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6727	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6728	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6729	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6730	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6731	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6732	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6733	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6734	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6735	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6736	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6737	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6738	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6739	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6740	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6741	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6742	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6743	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6744	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6745	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6746	REG_CNT(&pThis->svga.StatRegCommandLowWr, "VMSVGA/Reg/CommandLowWrite", "SVGA_REG_COMMAND_LOW writes.");
6747	REG_CNT(&pThis->svga.StatRegCommandHighWr, "VMSVGA/Reg/CommandHighWrite", "SVGA_REG_COMMAND_HIGH writes.");
6748	REG_CNT(&pThis->svga.StatRegDevCapWr, "VMSVGA/Reg/DevCapWrite", "SVGA_REG_DEV_CAP writes.");
6749	REG_CNT(&pThis->svga.StatRegCmdPrependLowWr, "VMSVGA/Reg/CmdPrependLowWrite", "SVGA_REG_CMD_PREPEND_LOW writes.");
6750	REG_CNT(&pThis->svga.StatRegCmdPrependHighWr, "VMSVGA/Reg/CmdPrependHighWrite", "SVGA_REG_CMD_PREPEND_HIGH writes.");
6751
6752	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6753	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6754	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6755	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6756	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6757	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6758	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
6759	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
6760	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) reads.");
6761	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
6762	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6763	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6764	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6765	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6766	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6767	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6768	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6769	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6770	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6771	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6772	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6773	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6774	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6775	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6776	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6777	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6778	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6779	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6780	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6781	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6782	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6783	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6784	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6785	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6786	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6787	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6788	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6789	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6790	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6791	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6792	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6793	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6794	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6795	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6796	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6797	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6798	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6799	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6800	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6801	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6802	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6803	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6804	REG_CNT(&pThis->svga.StatRegCommandLowRd, "VMSVGA/Reg/CommandLowRead", "SVGA_REG_COMMAND_LOW reads.");
6805	REG_CNT(&pThis->svga.StatRegCommandHighRd, "VMSVGA/Reg/CommandHighRead", "SVGA_REG_COMMAND_HIGH reads.");
6806	REG_CNT(&pThis->svga.StatRegMaxPrimBBMemRd, "VMSVGA/Reg/MaxPrimBBMemRead", "SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM reads.");
6807	REG_CNT(&pThis->svga.StatRegGBMemSizeRd, "VMSVGA/Reg/GBMemSizeRead", "SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB reads.");
6808	REG_CNT(&pThis->svga.StatRegDevCapRd, "VMSVGA/Reg/DevCapRead", "SVGA_REG_DEV_CAP reads.");
6809	REG_CNT(&pThis->svga.StatRegCmdPrependLowRd, "VMSVGA/Reg/CmdPrependLowRead", "SVGA_REG_CMD_PREPEND_LOW reads.");
6810	REG_CNT(&pThis->svga.StatRegCmdPrependHighRd, "VMSVGA/Reg/CmdPrependHighRead", "SVGA_REG_CMD_PREPEND_HIGH reads.");
6811	REG_CNT(&pThis->svga.StatRegScrnTgtMaxWidthRd, "VMSVGA/Reg/ScrnTgtMaxWidthRead", "SVGA_REG_SCREENTARGET_MAX_WIDTH reads.");
6812	REG_CNT(&pThis->svga.StatRegScrnTgtMaxHeightRd, "VMSVGA/Reg/ScrnTgtMaxHeightRead", "SVGA_REG_SCREENTARGET_MAX_HEIGHT reads.");
6813	REG_CNT(&pThis->svga.StatRegMobMaxSizeRd, "VMSVGA/Reg/MobMaxSizeRead", "SVGA_REG_MOB_MAX_SIZE reads.");
6814
6815	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6816	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6817	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6818	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6819	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6820	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6821	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6822	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6823	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6824	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6825	# endif
6826	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6827	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6828	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6829	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6830	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6831
6832	# undef REG_CNT
6833	# undef REG_PRF
6834
6835	/*
6836	* Info handlers.
6837	*/
6838	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6839	# ifdef VBOX_WITH_VMSVGA3D
6840	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6841	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6842	"VMSVGA 3d surface details. "
6843	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6844	vmsvgaR3Info3dSurface);
6845	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6846	"VMSVGA 3d surface details and bitmap: "
6847	"sid[>dir]",
6848	vmsvgaR3Info3dSurfaceBmp);
6849	# endif
6850
6851	return VINF_SUCCESS;
6852	}
6853
6854	/**
6855	* Power On notification.
6856	*
6857	* @returns VBox status code.
6858	* @param pDevIns The device instance data.
6859	*
6860	* @remarks Caller enters the device critical section.
6861	*/
6862	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6863	{
6864	# ifdef VBOX_WITH_VMSVGA3D
6865	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6866	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6867	if (pThis->svga.f3DEnabled)
6868	{
6869	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6870	int rc = pSVGAState->pFuncs3D->pfnPowerOn(pDevIns, pThis, pThisCC);
6871	if (RT_SUCCESS(rc))
6872	{
6873	/* Initialize FIFO 3D capabilities. */
6874	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
6875	}
6876	else
6877	{
6878	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dPowerOn -> %Rrc)\n", rc));
6879	pThis->svga.f3DEnabled = false;
6880	}
6881	}
6882	# else /* !VBOX_WITH_VMSVGA3D */
6883	RT_NOREF(pDevIns);
6884	# endif /* !VBOX_WITH_VMSVGA3D */
6885	}
6886
6887	/**
6888	* Power Off notification.
6889	*
6890	* @param pDevIns The device instance data.
6891	*
6892	* @remarks Caller enters the device critical section.
6893	*/
6894	DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns)
6895	{
6896	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6897	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6898
6899	/*
6900	* Notify the FIFO thread.
6901	*/
6902	if (pThisCC->svga.pFIFOIOThread)
6903	{
6904	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_POWEROFF,
6905	NULL /pvParam/, 30000 /ms/);
6906	AssertLogRelRC(rc);
6907	}
6908	}
6909
6910	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 94377

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