DevVGA-SVGA.cpp@ 92162

Last change on this file since 92162 was 91928, checked in by vboxsync, 3 years ago
VMM,Devices: Eliminate direct calls to PGMHandlerPhysical* APIs and introduce callbacks in the device helper callback table, bugref:10074
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1	/* $Id: DevVGA-SVGA.cpp 91928 2021-10-21 09:09:51Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - Log6 for DX shaders.
13	* - Log7 for SVGA command dump.
14	* - LogRel for the usual important stuff.
15	* - LogRel2 for cursor.
16	* - LogRel3 for 3D performance data.
17	* - LogRel4 for HW accelerated graphics output.
18	*/
19
20	/*
21	* Copyright (C) 2013-2020 Oracle Corporation
22	*
23	* This file is part of VirtualBox Open Source Edition (OSE), as
24	* available from http://www.virtualbox.org. This file is free software;
25	* you can redistribute it and/or modify it under the terms of the GNU
26	* General Public License (GPL) as published by the Free Software
27	* Foundation, in version 2 as it comes in the "COPYING" file of the
28	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
29	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
30	*/
31
32
33	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
34	*
35	* This device emulation was contributed by trivirt AG. It offers an
36	* alternative to our Bochs based VGA graphics and 3d emulations. This is
37	* valuable for Xorg based guests, as there is driver support shipping with Xorg
38	* since it forked from XFree86.
39	*
40	*
41	* @section sec_dev_vmsvga_sdk The VMware SDK
42	*
43	* This is officially deprecated now, however it's still quite useful,
44	* especially for getting the old features working:
45	* http://vmware-svga.sourceforge.net/
46	*
47	* They currently point developers at the following resources.
48	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
49	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
50	* - http://cgit.freedesktop.org/mesa/vmwgfx/
51	*
52	* @subsection subsec_dev_vmsvga_sdk_results Test results
53	*
54	* Test results:
55	* - 2dmark.img:
56	* + todo
57	* - backdoor-tclo.img:
58	* + todo
59	* - blit-cube.img:
60	* + todo
61	* - bunnies.img:
62	* + todo
63	* - cube.img:
64	* + todo
65	* - cubemark.img:
66	* + todo
67	* - dynamic-vertex-stress.img:
68	* + todo
69	* - dynamic-vertex.img:
70	* + todo
71	* - fence-stress.img:
72	* + todo
73	* - gmr-test.img:
74	* + todo
75	* - half-float-test.img:
76	* + todo
77	* - noscreen-cursor.img:
78	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
79	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
80	* visible though.)
81	* - Cursor animation via the palette doesn't work.
82	* - During debugging, it turns out that the framebuffer content seems to
83	* be halfways ignore or something (memset(fb, 0xcc, lots)).
84	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
85	* grow it 0x10 fold (128KB -> 2MB like in WS10).
86	* - null.img:
87	* + todo
88	* - pong.img:
89	* + todo
90	* - presentReadback.img:
91	* + todo
92	* - resolution-set.img:
93	* + todo
94	* - rt-gamma-test.img:
95	* + todo
96	* - screen-annotation.img:
97	* + todo
98	* - screen-cursor.img:
99	* + todo
100	* - screen-dma-coalesce.img:
101	* + todo
102	* - screen-gmr-discontig.img:
103	* + todo
104	* - screen-gmr-remap.img:
105	* + todo
106	* - screen-multimon.img:
107	* + todo
108	* - screen-present-clip.img:
109	* + todo
110	* - screen-render-test.img:
111	* + todo
112	* - screen-simple.img:
113	* + todo
114	* - screen-text.img:
115	* + todo
116	* - simple-shaders.img:
117	* + todo
118	* - simple_blit.img:
119	* + todo
120	* - tiny-2d-updates.img:
121	* + todo
122	* - video-formats.img:
123	* + todo
124	* - video-sync.img:
125	* + todo
126	*
127	*/
128
129
130	/*********************************************************************************************************************************
131	* Header Files *
132	*********************************************************************************************************************************/
133	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
134	#include <VBox/vmm/pdmdev.h>
135	#include <VBox/version.h>
136	#include <VBox/err.h>
137	#include <VBox/log.h>
138	#include <VBox/vmm/pgm.h>
139	#include <VBox/sup.h>
140
141	#include <iprt/assert.h>
142	#include <iprt/semaphore.h>
143	#include <iprt/uuid.h>
144	#ifdef IN_RING3
145	# include <iprt/ctype.h>
146	# include <iprt/mem.h>
147	# ifdef VBOX_STRICT
148	# include <iprt/time.h>
149	# endif
150	#endif
151
152	#include <VBox/AssertGuest.h>
153	#include <VBox/VMMDev.h>
154	#include <VBoxVideo.h>
155	#include <VBox/bioslogo.h>
156
157	#ifdef LOG_ENABLED
158	#include "svgadump/svga_dump.h"
159	#endif
160
161	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
162	#include "DevVGA.h"
163
164	/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
165	#ifdef VBOX_WITH_VMSVGA3D
166	# include "DevVGA-SVGA3d.h"
167	# ifdef RT_OS_DARWIN
168	# include "DevVGA-SVGA3d-cocoa.h"
169	# endif
170	# ifdef RT_OS_LINUX
171	# ifdef IN_RING3
172	# include "DevVGA-SVGA3d-glLdr.h"
173	# endif
174	# endif
175	#endif
176	#ifdef IN_RING3
177	#include "DevVGA-SVGA-internal.h"
178	#endif
179
180
181	/*********************************************************************************************************************************
182	* Defined Constants And Macros *
183	*********************************************************************************************************************************/
184	/**
185	* Macro for checking if a fixed FIFO register is valid according to the
186	* current FIFO configuration.
187	*
188	* @returns true / false.
189	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
190	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
191	*/
192	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
193
194
195	/*********************************************************************************************************************************
196	* Structures and Typedefs *
197	*********************************************************************************************************************************/
198
199
200	/*********************************************************************************************************************************
201	* Internal Functions *
202	*********************************************************************************************************************************/
203	#ifdef IN_RING3
204	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
205	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
206	# endif
207	# ifdef DEBUG_GMR_ACCESS
208	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
209	# endif
210	#endif
211
212
213	/*********************************************************************************************************************************
214	* Global Variables *
215	*********************************************************************************************************************************/
216	#ifdef IN_RING3
217
218	/**
219	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
220	*/
221	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
222	{
223	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
224	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
225	SSMFIELD_ENTRY_TERM()
226	};
227
228	/**
229	* SSM descriptor table for the GMR structure.
230	*/
231	static SSMFIELD const g_aGMRFields[] =
232	{
233	SSMFIELD_ENTRY( GMR, cMaxPages),
234	SSMFIELD_ENTRY( GMR, cbTotal),
235	SSMFIELD_ENTRY( GMR, numDescriptors),
236	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
237	SSMFIELD_ENTRY_TERM()
238	};
239
240	/**
241	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
242	*/
243	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
244	{
245	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
246	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
247	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
248	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
249	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
250	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
251	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
252	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
253	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
254	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
255	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
256	SSMFIELD_ENTRY_VER( VMSVGASCREENOBJECT, cDpi, VGA_SAVEDSTATE_VERSION_VMSVGA_MIPLEVELS),
257	SSMFIELD_ENTRY_TERM()
258	};
259
260	/**
261	* SSM descriptor table for the VMSVGAR3STATE structure.
262	*/
263	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
264	{
265	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
266	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
267	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
268	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
269	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
270	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
271	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
272	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
273	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
274	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
275	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
276	#ifdef VMSVGA_USE_EMT_HALT_CODE
277	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
278	#else
279	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
280	#endif
281	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
282	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
283	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
284	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
285	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
286	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
287	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
288	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
289	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
290	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
291	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
292	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
293	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
294	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
295	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
296	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
297	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
298	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
299	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
300	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
301	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
302	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
303	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
304	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
305	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
306	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
307	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
308	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
309	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
310	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
311	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
312	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
313	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
314	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
315	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
316	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
317	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
318	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
319	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
320	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
321	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
322	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
323	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
324	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
325	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
326	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
327	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
328	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
329	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
330	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
331	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
332	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
333	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
334	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
335	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
336	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
337	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
338	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
339	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
340	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
341	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
342	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
343	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
344
345	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
346	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
347	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
348	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
349
350	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
351	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
352	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
353	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
354	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
355	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
356	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
357	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
358	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
359	# endif
360	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
361	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
362	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
363	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
364
365	SSMFIELD_ENTRY_TERM()
366	};
367
368	/**
369	* SSM descriptor table for the VGAState.svga structure.
370	*/
371	static SSMFIELD const g_aVGAStateSVGAFields[] =
372	{
373	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
374	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
375	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
376	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
377	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
378	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
379	SSMFIELD_ENTRY( VMSVGAState, fBusy),
380	SSMFIELD_ENTRY( VMSVGAState, fTraces),
381	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
382	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
383	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
384	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
385	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
386	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
387	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
388	SSMFIELD_ENTRY( VMSVGAState, u32DeviceCaps),
389	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
390	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
391	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
392	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
393	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
394	SSMFIELD_ENTRY( VMSVGAState, uWidth),
395	SSMFIELD_ENTRY( VMSVGAState, uHeight),
396	SSMFIELD_ENTRY( VMSVGAState, uBpp),
397	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
398	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
399	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
400	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
401	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
402	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
403	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
404	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
405	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
406	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
407	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
408	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
409	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
410	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
411	SSMFIELD_ENTRY_TERM()
412	};
413	#endif /* IN_RING3 */
414
415
416	/*********************************************************************************************************************************
417	* Internal Functions *
418	*********************************************************************************************************************************/
419	#ifdef IN_RING3
420	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
421	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
422	uint32_t uVersion, uint32_t uPass);
423	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
424	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx);
425	#endif /* IN_RING3 */
426
427
428	#define SVGA_CASE_ID2STR(idx) case idx: return #idx
429	#if defined(LOG_ENABLED)
430	/**
431	* Index register string name lookup
432	*
433	* @returns Index register string or "UNKNOWN"
434	* @param pThis The shared VGA/VMSVGA state.
435	* @param idxReg The index register.
436	*/
437	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
438	{
439	AssertCompile(SVGA_REG_TOP == 77); /* Ensure that the correct headers are used. */
440	switch (idxReg)
441	{
442	SVGA_CASE_ID2STR(SVGA_REG_ID);
443	SVGA_CASE_ID2STR(SVGA_REG_ENABLE);
444	SVGA_CASE_ID2STR(SVGA_REG_WIDTH);
445	SVGA_CASE_ID2STR(SVGA_REG_HEIGHT);
446	SVGA_CASE_ID2STR(SVGA_REG_MAX_WIDTH);
447	SVGA_CASE_ID2STR(SVGA_REG_MAX_HEIGHT);
448	SVGA_CASE_ID2STR(SVGA_REG_DEPTH);
449	SVGA_CASE_ID2STR(SVGA_REG_BITS_PER_PIXEL); /* Current bpp in the guest */
450	SVGA_CASE_ID2STR(SVGA_REG_PSEUDOCOLOR);
451	SVGA_CASE_ID2STR(SVGA_REG_RED_MASK);
452	SVGA_CASE_ID2STR(SVGA_REG_GREEN_MASK);
453	SVGA_CASE_ID2STR(SVGA_REG_BLUE_MASK);
454	SVGA_CASE_ID2STR(SVGA_REG_BYTES_PER_LINE);
455	SVGA_CASE_ID2STR(SVGA_REG_FB_START); /* (Deprecated) */
456	SVGA_CASE_ID2STR(SVGA_REG_FB_OFFSET);
457	SVGA_CASE_ID2STR(SVGA_REG_VRAM_SIZE);
458	SVGA_CASE_ID2STR(SVGA_REG_FB_SIZE);
459
460	/* ID 0 implementation only had the above registers, then the palette */
461	SVGA_CASE_ID2STR(SVGA_REG_CAPABILITIES);
462	SVGA_CASE_ID2STR(SVGA_REG_MEM_START); /* (Deprecated) */
463	SVGA_CASE_ID2STR(SVGA_REG_MEM_SIZE);
464	SVGA_CASE_ID2STR(SVGA_REG_CONFIG_DONE); /* Set when memory area configured */
465	SVGA_CASE_ID2STR(SVGA_REG_SYNC); /* See "FIFO Synchronization Registers" */
466	SVGA_CASE_ID2STR(SVGA_REG_BUSY); /* See "FIFO Synchronization Registers" */
467	SVGA_CASE_ID2STR(SVGA_REG_GUEST_ID); /* Set guest OS identifier */
468	SVGA_CASE_ID2STR(SVGA_REG_DEAD); /* (Deprecated) SVGA_REG_CURSOR_ID. */
469	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_X); /* (Deprecated) */
470	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_Y); /* (Deprecated) */
471	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ON); /* (Deprecated) */
472	SVGA_CASE_ID2STR(SVGA_REG_HOST_BITS_PER_PIXEL); /* (Deprecated) */
473	SVGA_CASE_ID2STR(SVGA_REG_SCRATCH_SIZE); /* Number of scratch registers */
474	SVGA_CASE_ID2STR(SVGA_REG_MEM_REGS); /* Number of FIFO registers */
475	SVGA_CASE_ID2STR(SVGA_REG_NUM_DISPLAYS); /* (Deprecated) */
476	SVGA_CASE_ID2STR(SVGA_REG_PITCHLOCK); /* Fixed pitch for all modes */
477	SVGA_CASE_ID2STR(SVGA_REG_IRQMASK); /* Interrupt mask */
478
479	/* Legacy multi-monitor support */
480	SVGA_CASE_ID2STR(SVGA_REG_NUM_GUEST_DISPLAYS); /* Number of guest displays in X/Y direction */
481	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_ID); /* Display ID for the following display attributes */
482	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_IS_PRIMARY); /* Whether this is a primary display */
483	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_X); /* The display position x */
484	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_Y); /* The display position y */
485	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_WIDTH); /* The display's width */
486	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_HEIGHT); /* The display's height */
487
488	SVGA_CASE_ID2STR(SVGA_REG_GMR_ID);
489	SVGA_CASE_ID2STR(SVGA_REG_GMR_DESCRIPTOR);
490	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_IDS);
491	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
492
493	SVGA_CASE_ID2STR(SVGA_REG_TRACES); /* Enable trace-based updates even when FIFO is on */
494	SVGA_CASE_ID2STR(SVGA_REG_GMRS_MAX_PAGES); /* Maximum number of 4KB pages for all GMRs */
495	SVGA_CASE_ID2STR(SVGA_REG_MEMORY_SIZE); /* Total dedicated device memory excluding FIFO */
496	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_LOW); /* Lower 32 bits and submits commands */
497	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_HIGH); /* Upper 32 bits of command buffer PA */
498	SVGA_CASE_ID2STR(SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); /* Max primary memory */
499	SVGA_CASE_ID2STR(SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); /* Suggested limit on mob mem */
500	SVGA_CASE_ID2STR(SVGA_REG_DEV_CAP); /* Write dev cap index, read value */
501	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_LOW);
502	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_HIGH);
503	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_WIDTH);
504	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_HEIGHT);
505	SVGA_CASE_ID2STR(SVGA_REG_MOB_MAX_SIZE);
506	SVGA_CASE_ID2STR(SVGA_REG_BLANK_SCREEN_TARGETS);
507	SVGA_CASE_ID2STR(SVGA_REG_CAP2);
508	SVGA_CASE_ID2STR(SVGA_REG_DEVEL_CAP);
509	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_ID);
510	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION1);
511	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION2);
512	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION3);
513	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MOBID);
514	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_BYTE_SIZE);
515	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_DIMENSION);
516	SVGA_CASE_ID2STR(SVGA_REG_FIFO_CAPS);
517	SVGA_CASE_ID2STR(SVGA_REG_FENCE);
518	SVGA_CASE_ID2STR(SVGA_REG_RESERVED1);
519	SVGA_CASE_ID2STR(SVGA_REG_RESERVED2);
520	SVGA_CASE_ID2STR(SVGA_REG_RESERVED3);
521	SVGA_CASE_ID2STR(SVGA_REG_RESERVED4);
522	SVGA_CASE_ID2STR(SVGA_REG_RESERVED5);
523	SVGA_CASE_ID2STR(SVGA_REG_SCREENDMA);
524	SVGA_CASE_ID2STR(SVGA_REG_GBOBJECT_MEM_SIZE_KB);
525	SVGA_CASE_ID2STR(SVGA_REG_TOP); /* Must be 1 more than the last register */
526
527	default:
528	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
529	return "SVGA_SCRATCH_BASE reg";
530	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
531	return "SVGA_PALETTE_BASE reg";
532	return "UNKNOWN";
533	}
534	}
535	#endif /* LOG_ENABLED */
536
537	#if defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D))
538	static const char *vmsvgaDevCapIndexToString(SVGA3dDevCapIndex idxDevCap)
539	{
540	AssertCompile(SVGA3D_DEVCAP_MAX == 260);
541	switch (idxDevCap)
542	{
543	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_INVALID);
544	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_3D);
545	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LIGHTS);
546	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURES);
547	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CLIP_PLANES);
548	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER_VERSION);
549	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER);
550	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION);
551	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER);
552	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_RENDER_TARGETS);
553	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S23E8_TEXTURES);
554	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S10E5_TEXTURES);
555	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND);
556	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D16_BUFFER_FORMAT);
557	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT);
558	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT);
559	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_QUERY_TYPES);
560	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING);
561	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_POINT_SIZE);
562	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SHADER_TEXTURES);
563	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
564	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
565	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VOLUME_EXTENT);
566	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT);
567	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO);
568	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY);
569	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT);
570	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_INDEX);
571	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS);
572	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS);
573	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS);
574	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS);
575	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_OPS);
576	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);
577	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8);
578	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10);
579	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5);
580	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5);
581	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4);
582	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R5G6B5);
583	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16);
584	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8);
585	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ALPHA8);
586	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8);
587	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D16);
588	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8);
589	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8);
590	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT1);
591	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT2);
592	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT3);
593	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT4);
594	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT5);
595	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8);
596	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10);
597	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8);
598	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8);
599	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_CxV8U8);
600	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S10E5);
601	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S23E8);
602	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5);
603	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8);
604	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5);
605	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8);
606	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MISSING62);
607	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES);
608	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS);
609	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_V16U16);
610	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_G16R16);
611	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16);
612	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_UYVY);
613	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YUY2);
614	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD4); /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
615	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD5); /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
616	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD7); /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
617	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD6); /* SVGA3D_DEVCAP_SUPERSAMPLE */
618	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_AUTOGENMIPMAPS);
619	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_NV12);
620	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD10); /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
621	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CONTEXT_IDS);
622	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SURFACE_IDS);
623	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF16);
624	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF24);
625	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT);
626	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI1);
627	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI2);
628	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD1);
629	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD8); /* SVGA3D_DEVCAP_VIDEO_DECODE */
630	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD9); /* SVGA3D_DEVCAP_VIDEO_PROCESS */
631	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_AA);
632	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_STIPPLE);
633	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LINE_WIDTH);
634	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH);
635	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YV12);
636	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD3); /* Old SVGA3D_DEVCAP_LOGICOPS */
637	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TS_COLOR_KEY);
638	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD2);
639	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXCONTEXT);
640	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD11); /* SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE */
641	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS);
642	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS);
643	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_PROVOKING_VERTEX);
644	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8R8G8B8);
645	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8R8G8B8);
646	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R5G6B5);
647	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X1R5G5B5);
648	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A1R5G5B5);
649	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A4R4G4B4);
650	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D32);
651	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D16);
652	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8);
653	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D15S1);
654	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8);
655	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4);
656	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE16);
657	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8);
658	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT1);
659	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT2);
660	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT3);
661	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT4);
662	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT5);
663	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPU8V8);
664	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5);
665	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8);
666	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1);
667	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5);
668	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8);
669	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2R10G10B10);
670	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V8U8);
671	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8);
672	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_CxV8U8);
673	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8L8V8U8);
674	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2W10V10U10);
675	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ALPHA8);
676	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S10E5);
677	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S23E8);
678	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S10E5);
679	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S23E8);
680	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUFFER);
681	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24X8);
682	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V16U16);
683	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G16R16);
684	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A16B16G16R16);
685	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_UYVY);
686	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YUY2);
687	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_NV12);
688	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2); /* SVGA3D_DEVCAP_DXFMT_AYUV */
689	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS);
690	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT);
691	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT);
692	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS);
693	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT);
694	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT);
695	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT);
696	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS);
697	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT);
698	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM);
699	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT);
700	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS);
701	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_UINT);
702	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_SINT);
703	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS);
704	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT);
705	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24);
706	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT);
707	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS);
708	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT);
709	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT);
710	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS);
711	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM);
712	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB);
713	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT);
714	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT);
715	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS);
716	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UINT);
717	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SINT);
718	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS);
719	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT);
720	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_UINT);
721	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_SINT);
722	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS);
723	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT);
724	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8);
725	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X24_G8_UINT);
726	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS);
727	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM);
728	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UINT);
729	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SINT);
730	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS);
731	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UNORM);
732	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UINT);
733	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SNORM);
734	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SINT);
735	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS);
736	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UNORM);
737	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UINT);
738	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SNORM);
739	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SINT);
740	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_P8);
741	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP);
742	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM);
743	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM);
744	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS);
745	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB);
746	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS);
747	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB);
748	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS);
749	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB);
750	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS);
751	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI1);
752	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_SNORM);
753	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS);
754	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI2);
755	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_SNORM);
756	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM);
757	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS);
758	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB);
759	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS);
760	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB);
761	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF16);
762	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF24);
763	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT);
764	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YV12);
765	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT);
766	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT);
767	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM);
768	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT);
769	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM);
770	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM);
771	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT);
772	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM);
773	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM);
774	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT);
775	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM);
776	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_FLOAT);
777	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D16_UNORM);
778	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8_UNORM);
779	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM);
780	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM);
781	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM);
782	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM);
783	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM);
784	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM);
785	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM);
786	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_UNORM);
787	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_UNORM);
788	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM41);
789	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_2X);
790	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_4X);
791	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MS_FULL_QUALITY);
792	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGICOPS);
793	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGIC_BLENDOPS);
794	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_1);
795	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS);
796	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_UF16);
797	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_SF16);
798	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS);
799	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM);
800	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB);
801	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_2);
802	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM5);
803	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_8X);
804
805	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX);
806
807	default:
808	break;
809	}
810	return "UNKNOWN";
811	}
812	#endif /* defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D)) */
813	#undef SVGA_CASE_ID2STR
814
815
816	#ifdef IN_RING3
817
818	/**
819	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
820	*/
821	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
822	{
823	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
824	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
825
826	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
827	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
828
829	/** @todo Test how it interacts with multiple screen objects. */
830	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
831	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
832	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
833
834	if (x < uWidth)
835	{
836	pThis->svga.viewport.x = x;
837	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
838	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
839	}
840	else
841	{
842	pThis->svga.viewport.x = uWidth;
843	pThis->svga.viewport.cx = 0;
844	pThis->svga.viewport.xRight = uWidth;
845	}
846	if (y < uHeight)
847	{
848	pThis->svga.viewport.y = y;
849	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
850	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
851	pThis->svga.viewport.yHighWC = uHeight - y;
852	}
853	else
854	{
855	pThis->svga.viewport.y = uHeight;
856	pThis->svga.viewport.cy = 0;
857	pThis->svga.viewport.yLowWC = 0;
858	pThis->svga.viewport.yHighWC = 0;
859	}
860
861	# ifdef VBOX_WITH_VMSVGA3D
862	/*
863	* Now inform the 3D backend.
864	*/
865	if (pThis->svga.f3DEnabled)
866	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
867	# else
868	RT_NOREF(OldViewport);
869	# endif
870	}
871
872
873	/**
874	* Updating screen information in API
875	*
876	* @param pThis The The shared VGA/VMSVGA instance data.
877	* @param pThisCC The VGA/VMSVGA state for ring-3.
878	*/
879	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
880	{
881	int rc;
882
883	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
884
885	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
886	{
887	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
888	if (!pScreen->fModified)
889	continue;
890
891	pScreen->fModified = false;
892
893	VBVAINFOVIEW view;
894	RT_ZERO(view);
895	view.u32ViewIndex = pScreen->idScreen;
896	// view.u32ViewOffset = 0;
897	view.u32ViewSize = pThis->vram_size;
898	view.u32MaxScreenSize = pThis->vram_size;
899
900	VBVAINFOSCREEN screen;
901	RT_ZERO(screen);
902	screen.u32ViewIndex = pScreen->idScreen;
903
904	if (pScreen->fDefined)
905	{
906	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
907	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
908	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
909	{
910	Assert(pThis->svga.fGFBRegisters);
911	continue;
912	}
913
914	screen.i32OriginX = pScreen->xOrigin;
915	screen.i32OriginY = pScreen->yOrigin;
916	screen.u32StartOffset = pScreen->offVRAM;
917	screen.u32LineSize = pScreen->cbPitch;
918	screen.u32Width = pScreen->cWidth;
919	screen.u32Height = pScreen->cHeight;
920	screen.u16BitsPerPixel = pScreen->cBpp;
921	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
922	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
923	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
924	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
925	}
926	else
927	{
928	/* Screen is destroyed. */
929	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
930	}
931
932	void *pvVRAM = pScreen->pvScreenBitmap ? pScreen->pvScreenBitmap : pThisCC->pbVRam;
933	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pvVRAM, /fResetInputMapping=/ true);
934	AssertRC(rc);
935	}
936	}
937
938
939	/**
940	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
941	*
942	* Used to update screen offsets (positions) since appearently vmwgfx fails to
943	* pass correct offsets thru FIFO.
944	*/
945	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
946	{
947	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
948	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
949	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
950
951	AssertReturnVoid(pSVGAState);
952
953	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
954	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
955	for (uint32_t i = 0; i < cPositions; ++i)
956	{
957	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
958	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
959	continue;
960
961	if (paPositions[i].x == -1)
962	continue;
963	if (paPositions[i].y == -1)
964	continue;
965
966	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
967	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
968	pSVGAState->aScreens[i].fModified = true;
969	}
970
971	vmsvgaR3VBVAResize(pThis, pThisCC);
972	}
973
974	#endif /* IN_RING3 */
975
976	/**
977	* Read port register
978	*
979	* @returns VBox status code.
980	* @param pDevIns The device instance.
981	* @param pThis The shared VGA/VMSVGA state.
982	* @param pu32 Where to store the read value
983	*/
984	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
985	{
986	#ifdef IN_RING3
987	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
988	#endif
989	int rc = VINF_SUCCESS;
990	*pu32 = 0;
991
992	/* Rough index register validation. */
993	uint32_t idxReg = pThis->svga.u32IndexReg;
994	#if !defined(IN_RING3) && defined(VBOX_STRICT)
995	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
996	VINF_IOM_R3_IOPORT_READ);
997	#else
998	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
999	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
1000	VINF_SUCCESS);
1001	#endif
1002	RT_UNTRUSTED_VALIDATED_FENCE();
1003
1004	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1005	if ( idxReg >= SVGA_REG_ID_0_TOP
1006	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1007	{
1008	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1009	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1010	}
1011
1012	switch (idxReg)
1013	{
1014	case SVGA_REG_ID:
1015	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
1016	*pu32 = pThis->svga.u32SVGAId;
1017	break;
1018
1019	case SVGA_REG_ENABLE:
1020	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
1021	*pu32 = pThis->svga.fEnabled;
1022	break;
1023
1024	case SVGA_REG_WIDTH:
1025	{
1026	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
1027	if ( pThis->svga.fEnabled
1028	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
1029	*pu32 = pThis->svga.uWidth;
1030	else
1031	{
1032	#ifndef IN_RING3
1033	rc = VINF_IOM_R3_IOPORT_READ;
1034	#else
1035	*pu32 = pThisCC->pDrv->cx;
1036	#endif
1037	}
1038	break;
1039	}
1040
1041	case SVGA_REG_HEIGHT:
1042	{
1043	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
1044	if ( pThis->svga.fEnabled
1045	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1046	*pu32 = pThis->svga.uHeight;
1047	else
1048	{
1049	#ifndef IN_RING3
1050	rc = VINF_IOM_R3_IOPORT_READ;
1051	#else
1052	*pu32 = pThisCC->pDrv->cy;
1053	#endif
1054	}
1055	break;
1056	}
1057
1058	case SVGA_REG_MAX_WIDTH:
1059	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
1060	*pu32 = pThis->svga.u32MaxWidth;
1061	break;
1062
1063	case SVGA_REG_MAX_HEIGHT:
1064	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
1065	*pu32 = pThis->svga.u32MaxHeight;
1066	break;
1067
1068	case SVGA_REG_DEPTH:
1069	/* This returns the color depth of the current mode. */
1070	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
1071	switch (pThis->svga.uBpp)
1072	{
1073	case 15:
1074	case 16:
1075	case 24:
1076	*pu32 = pThis->svga.uBpp;
1077	break;
1078
1079	default:
1080	case 32:
1081	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
1082	break;
1083	}
1084	break;
1085
1086	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1087	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1088	*pu32 = pThis->svga.uHostBpp;
1089	break;
1090
1091	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1092	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1093	*pu32 = pThis->svga.uBpp;
1094	break;
1095
1096	case SVGA_REG_PSEUDOCOLOR:
1097	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1098	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1099	break;
1100
1101	case SVGA_REG_RED_MASK:
1102	case SVGA_REG_GREEN_MASK:
1103	case SVGA_REG_BLUE_MASK:
1104	{
1105	uint32_t uBpp;
1106
1107	if (pThis->svga.fEnabled)
1108	uBpp = pThis->svga.uBpp;
1109	else
1110	uBpp = pThis->svga.uHostBpp;
1111
1112	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1113	switch (uBpp)
1114	{
1115	case 8:
1116	u32RedMask = 0x07;
1117	u32GreenMask = 0x38;
1118	u32BlueMask = 0xc0;
1119	break;
1120
1121	case 15:
1122	u32RedMask = 0x0000001f;
1123	u32GreenMask = 0x000003e0;
1124	u32BlueMask = 0x00007c00;
1125	break;
1126
1127	case 16:
1128	u32RedMask = 0x0000001f;
1129	u32GreenMask = 0x000007e0;
1130	u32BlueMask = 0x0000f800;
1131	break;
1132
1133	case 24:
1134	case 32:
1135	default:
1136	u32RedMask = 0x00ff0000;
1137	u32GreenMask = 0x0000ff00;
1138	u32BlueMask = 0x000000ff;
1139	break;
1140	}
1141	switch (idxReg)
1142	{
1143	case SVGA_REG_RED_MASK:
1144	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1145	*pu32 = u32RedMask;
1146	break;
1147
1148	case SVGA_REG_GREEN_MASK:
1149	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1150	*pu32 = u32GreenMask;
1151	break;
1152
1153	case SVGA_REG_BLUE_MASK:
1154	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1155	*pu32 = u32BlueMask;
1156	break;
1157	}
1158	break;
1159	}
1160
1161	case SVGA_REG_BYTES_PER_LINE:
1162	{
1163	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1164	if ( pThis->svga.fEnabled
1165	&& pThis->svga.cbScanline)
1166	*pu32 = pThis->svga.cbScanline;
1167	else
1168	{
1169	#ifndef IN_RING3
1170	rc = VINF_IOM_R3_IOPORT_READ;
1171	#else
1172	*pu32 = pThisCC->pDrv->cbScanline;
1173	#endif
1174	}
1175	break;
1176	}
1177
1178	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1179	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1180	*pu32 = pThis->vram_size;
1181	break;
1182
1183	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1184	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1185	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1186	*pu32 = pThis->GCPhysVRAM;
1187	break;
1188
1189	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1190	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1191	/* Always zero in our case. */
1192	*pu32 = 0;
1193	break;
1194
1195	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1196	{
1197	#ifndef IN_RING3
1198	rc = VINF_IOM_R3_IOPORT_READ;
1199	#else
1200	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1201
1202	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1203	if ( pThis->svga.fEnabled
1204	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1205	{
1206	/* Hardware enabled; return real framebuffer size .*/
1207	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1208	}
1209	else
1210	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1211
1212	pu32 = RT_MIN(pThis->vram_size, pu32);
1213	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1214	#endif
1215	break;
1216	}
1217
1218	case SVGA_REG_CAPABILITIES:
1219	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1220	*pu32 = pThis->svga.u32DeviceCaps;
1221	break;
1222
1223	case SVGA_REG_MEM_START: /* FIFO start */
1224	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1225	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1226	*pu32 = pThis->svga.GCPhysFIFO;
1227	break;
1228
1229	case SVGA_REG_MEM_SIZE: /* FIFO size */
1230	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1231	*pu32 = pThis->svga.cbFIFO;
1232	break;
1233
1234	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1235	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1236	*pu32 = pThis->svga.fConfigured;
1237	break;
1238
1239	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1240	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1241	*pu32 = 0;
1242	break;
1243
1244	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1245	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1246	if (pThis->svga.fBusy)
1247	{
1248	#ifndef IN_RING3
1249	/* Go to ring-3 and halt the CPU. */
1250	rc = VINF_IOM_R3_IOPORT_READ;
1251	RT_NOREF(pDevIns);
1252	break;
1253	#else /* IN_RING3 */
1254	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1255	/* The guest is basically doing a HLT via the device here, but with
1256	a special wake up condition on FIFO completion. */
1257	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1258	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1259	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1260	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1261	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1262	if (pThis->svga.fBusy)
1263	{
1264	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1265	rc = PDMDevHlpVMWaitForDeviceReady(pDevIns, idCpu);
1266	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1267	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
1268	}
1269	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1270	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1271	# else
1272
1273	/* Delay the EMT a bit so the FIFO and others can get some work done.
1274	This used to be a crude 50 ms sleep. The current code tries to be
1275	more efficient, but the consept is still very crude. */
1276	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1277	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1278	RTThreadYield();
1279	if (pThis->svga.fBusy)
1280	{
1281	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1282
1283	if (pThis->svga.fBusy && cRefs == 1)
1284	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1285	if (pThis->svga.fBusy)
1286	{
1287	/** @todo If this code is going to stay, we need to call into the halt/wait
1288	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1289	* suffer when the guest is polling on a busy FIFO. */
1290	uint64_t uIgnored1, uIgnored2;
1291	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns), &uIgnored1, &uIgnored2);
1292	if (cNsMaxWait >= RT_NS_100US)
1293	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1294	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1295	RT_MIN(cNsMaxWait, RT_NS_10MS));
1296	}
1297
1298	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1299	}
1300	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1301	# endif
1302	*pu32 = pThis->svga.fBusy != 0;
1303	#endif /* IN_RING3 */
1304	}
1305	else
1306	*pu32 = false;
1307	break;
1308
1309	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1310	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1311	*pu32 = pThis->svga.u32GuestId;
1312	break;
1313
1314	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1315	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1316	*pu32 = pThis->svga.cScratchRegion;
1317	break;
1318
1319	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1320	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1321	*pu32 = SVGA_FIFO_NUM_REGS;
1322	break;
1323
1324	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1325	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1326	*pu32 = pThis->svga.u32PitchLock;
1327	break;
1328
1329	case SVGA_REG_IRQMASK: /* Interrupt mask */
1330	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1331	*pu32 = pThis->svga.u32IrqMask;
1332	break;
1333
1334	/* See "Guest memory regions" below. */
1335	case SVGA_REG_GMR_ID:
1336	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1337	*pu32 = pThis->svga.u32CurrentGMRId;
1338	break;
1339
1340	case SVGA_REG_GMR_DESCRIPTOR:
1341	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1342	/* Write only */
1343	*pu32 = 0;
1344	break;
1345
1346	case SVGA_REG_GMR_MAX_IDS:
1347	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1348	*pu32 = pThis->svga.cGMR;
1349	break;
1350
1351	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1352	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1353	*pu32 = VMSVGA_MAX_GMR_PAGES;
1354	break;
1355
1356	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1357	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1358	*pu32 = pThis->svga.fTraces;
1359	break;
1360
1361	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1362	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1363	*pu32 = VMSVGA_MAX_GMR_PAGES;
1364	break;
1365
1366	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1367	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1368	*pu32 = VMSVGA_SURFACE_SIZE;
1369	break;
1370
1371	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1372	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1373	break;
1374
1375	/* Mouse cursor support. */
1376	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
1377	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1378	*pu32 = pThis->svga.uCursorID;
1379	break;
1380
1381	case SVGA_REG_CURSOR_X:
1382	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1383	*pu32 = pThis->svga.uCursorX;
1384	break;
1385
1386	case SVGA_REG_CURSOR_Y:
1387	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1388	*pu32 = pThis->svga.uCursorY;
1389	break;
1390
1391	case SVGA_REG_CURSOR_ON:
1392	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1393	*pu32 = pThis->svga.uCursorOn;
1394	break;
1395
1396	/* Legacy multi-monitor support */
1397	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1398	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1399	*pu32 = 1;
1400	break;
1401
1402	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1403	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1404	*pu32 = 0;
1405	break;
1406
1407	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1408	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1409	*pu32 = 0;
1410	break;
1411
1412	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1413	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1414	*pu32 = 0;
1415	break;
1416
1417	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1418	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1419	*pu32 = 0;
1420	break;
1421
1422	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1423	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1424	*pu32 = pThis->svga.uWidth;
1425	break;
1426
1427	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1428	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1429	*pu32 = pThis->svga.uHeight;
1430	break;
1431
1432	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1433	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1434	/* We must return something sensible here otherwise the Linux driver
1435	will take a legacy code path without 3d support. This number also
1436	limits how many screens Linux guests will allow. */
1437	*pu32 = pThis->cMonitors;
1438	break;
1439
1440	/*
1441	* SVGA_CAP_GBOBJECTS+ registers.
1442	*/
1443	case SVGA_REG_COMMAND_LOW:
1444	/* Lower 32 bits of command buffer physical address. */
1445	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowRd);
1446	*pu32 = pThis->svga.u32RegCommandLow;
1447	break;
1448
1449	case SVGA_REG_COMMAND_HIGH:
1450	/* Upper 32 bits of command buffer PA. */
1451	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighRd);
1452	*pu32 = pThis->svga.u32RegCommandHigh;
1453	break;
1454
1455	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
1456	/* Max primary (screen) memory. */
1457	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxPrimBBMemRd);
1458	pu32 = pThis->vram_size; /* @todo Maybe half VRAM? */
1459	break;
1460
1461	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
1462	/* Suggested limit on mob mem (i.e. size of the guest mapped VRAM in KB) */
1463	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGBMemSizeRd);
1464	*pu32 = pThis->vram_size / 1024;
1465	break;
1466
1467	case SVGA_REG_DEV_CAP:
1468	/* Write dev cap index, read value */
1469	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapRd);
1470	if (pThis->svga.u32DevCapIndex < RT_ELEMENTS(pThis->svga.au32DevCaps))
1471	{
1472	RT_UNTRUSTED_VALIDATED_FENCE();
1473	*pu32 = pThis->svga.au32DevCaps[pThis->svga.u32DevCapIndex];
1474	}
1475	else
1476	*pu32 = 0;
1477	break;
1478
1479	case SVGA_REG_CMD_PREPEND_LOW:
1480	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowRd);
1481	pu32 = 0; / Not supported. */
1482	break;
1483
1484	case SVGA_REG_CMD_PREPEND_HIGH:
1485	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighRd);
1486	pu32 = 0; / Not supported. */
1487	break;
1488
1489	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
1490	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxWidthRd);
1491	*pu32 = pThis->svga.u32MaxWidth;
1492	break;
1493
1494	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
1495	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxHeightRd);
1496	*pu32 = pThis->svga.u32MaxHeight;
1497	break;
1498
1499	case SVGA_REG_MOB_MAX_SIZE:
1500	/* Essentially the max texture size */
1501	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMobMaxSizeRd);
1502	pu32 = _128M; /* @todo Some actual value. Probably the mapped VRAM size. */
1503	break;
1504
1505	default:
1506	{
1507	uint32_t offReg;
1508	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1509	{
1510	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1511	RT_UNTRUSTED_VALIDATED_FENCE();
1512	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1513	}
1514	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1515	{
1516	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1517	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1518	RT_UNTRUSTED_VALIDATED_FENCE();
1519	uint32_t u32 = pThis->last_palette[offReg / 3];
1520	switch (offReg % 3)
1521	{
1522	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1523	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1524	case 2: pu32 = u32 & 0xff; break; / blue */
1525	}
1526	}
1527	else
1528	{
1529	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1530	rc = VINF_IOM_R3_IOPORT_READ;
1531	#else
1532	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1533
1534	/* Do not assert. The guest might be reading all registers. */
1535	LogFunc(("Unknown reg=%#x\n", idxReg));
1536	#endif
1537	}
1538	break;
1539	}
1540	}
1541	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1542	return rc;
1543	}
1544
1545	#ifdef IN_RING3
1546	/**
1547	* Apply the current resolution settings to change the video mode.
1548	*
1549	* @returns VBox status code.
1550	* @param pThis The shared VGA state.
1551	* @param pThisCC The ring-3 VGA state.
1552	*/
1553	int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1554	{
1555	/* Always do changemode on FIFO thread. */
1556	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1557
1558	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1559
1560	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1561
1562	if (pThis->svga.fGFBRegisters)
1563	{
1564	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1565	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1566	* deletes all screens other than screen #0, and redefines screen
1567	* #0 according to the specified mode. Drivers that use
1568	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1569	*/
1570
1571	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1572	pScreen->fDefined = true;
1573	pScreen->fModified = true;
1574	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1575	pScreen->idScreen = 0;
1576	pScreen->xOrigin = 0;
1577	pScreen->yOrigin = 0;
1578	pScreen->offVRAM = 0;
1579	pScreen->cbPitch = pThis->svga.cbScanline;
1580	pScreen->cWidth = pThis->svga.uWidth;
1581	pScreen->cHeight = pThis->svga.uHeight;
1582	pScreen->cBpp = pThis->svga.uBpp;
1583
1584	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1585	{
1586	/* Delete screen. */
1587	pScreen = &pSVGAState->aScreens[iScreen];
1588	if (pScreen->fDefined)
1589	{
1590	pScreen->fModified = true;
1591	pScreen->fDefined = false;
1592	}
1593	}
1594	}
1595	else
1596	{
1597	/* "If Screen Objects are supported, they can be used to fully
1598	* replace the functionality provided by the framebuffer registers
1599	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1600	*/
1601	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1602	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1603	pThis->svga.uBpp = pThis->svga.uHostBpp;
1604	}
1605
1606	vmsvgaR3VBVAResize(pThis, pThisCC);
1607
1608	/* Last stuff. For the VGA device screenshot. */
1609	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1610	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1611	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1612	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1613	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1614
1615	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1616	if ( pThis->svga.viewport.cx == 0
1617	&& pThis->svga.viewport.cy == 0)
1618	{
1619	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1620	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1621	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1622	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1623	pThis->svga.viewport.yLowWC = 0;
1624	}
1625
1626	return VINF_SUCCESS;
1627	}
1628
1629	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1630	{
1631	VBVACMDHDR cmd;
1632	cmd.x = (int16_t)(pScreen->xOrigin + x);
1633	cmd.y = (int16_t)(pScreen->yOrigin + y);
1634	cmd.w = (uint16_t)w;
1635	cmd.h = (uint16_t)h;
1636
1637	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1638	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1639	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1640	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1641
1642	return VINF_SUCCESS;
1643	}
1644
1645	#endif /* IN_RING3 */
1646	#if defined(IN_RING0) \|\| defined(IN_RING3)
1647
1648	/**
1649	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1650	*
1651	* @param pThis The shared VGA/VMSVGA instance data.
1652	* @param pThisCC The VGA/VMSVGA state for the current context.
1653	* @param fState The busy state.
1654	*/
1655	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1656	{
1657	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1658
1659	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1660	{
1661	/* Race / unfortunately scheduling. Highly unlikly. */
1662	uint32_t cLoops = 64;
1663	do
1664	{
1665	ASMNopPause();
1666	fState = (pThis->svga.fBusy != 0);
1667	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1668	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1669	}
1670	}
1671
1672
1673	/**
1674	* Update the scanline pitch in response to the guest changing mode
1675	* width/bpp.
1676	*
1677	* @param pThis The shared VGA/VMSVGA state.
1678	* @param pThisCC The VGA/VMSVGA state for the current context.
1679	*/
1680	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1681	{
1682	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1683	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1684	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1685	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1686
1687	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1688	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1689	* location but it has a different meaning.
1690	*/
1691	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1692	uFifoPitchLock = 0;
1693
1694	/* Sanitize values. */
1695	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1696	uFifoPitchLock = 0;
1697	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1698	uRegPitchLock = 0;
1699
1700	/* Prefer the register value to the FIFO value.*/
1701	if (uRegPitchLock)
1702	pThis->svga.cbScanline = uRegPitchLock;
1703	else if (uFifoPitchLock)
1704	pThis->svga.cbScanline = uFifoPitchLock;
1705	else
1706	pThis->svga.cbScanline = (uint32_t)pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1707
1708	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1709	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1710	}
1711
1712	#endif /* IN_RING0 \|\| IN_RING3 */
1713
1714	#ifdef IN_RING3
1715
1716	/**
1717	* Sends cursor position and visibility information from legacy
1718	* SVGA registers to the front-end.
1719	*/
1720	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1721	{
1722	/*
1723	* Writing the X/Y/ID registers does not trigger changes; only writing the
1724	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1725	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1726	* register if they don't have to.
1727	*/
1728	uint32_t x, y, idScreen;
1729	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1730
1731	x = pThis->svga.uCursorX;
1732	y = pThis->svga.uCursorY;
1733	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1734
1735	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1736	* were extended as follows:
1737	*
1738	* SVGA_CURSOR_ON_HIDE 0
1739	* SVGA_CURSOR_ON_SHOW 1
1740	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1741	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1742	*
1743	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1744	* distinguish between the non-zero values but still remember them.
1745	*/
1746	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1747	{
1748	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1749	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1750	}
1751	pThis->svga.uCursorOn = uCursorOn;
1752	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1753	}
1754
1755	#endif /* IN_RING3 */
1756
1757
1758	/**
1759	* Write port register
1760	*
1761	* @returns Strict VBox status code.
1762	* @param pDevIns The device instance.
1763	* @param pThis The shared VGA/VMSVGA state.
1764	* @param pThisCC The VGA/VMSVGA state for the current context.
1765	* @param u32 Value to write
1766	*/
1767	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1768	{
1769	#ifdef IN_RING3
1770	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1771	#endif
1772	VBOXSTRICTRC rc = VINF_SUCCESS;
1773	RT_NOREF(pThisCC);
1774
1775	/* Rough index register validation. */
1776	uint32_t idxReg = pThis->svga.u32IndexReg;
1777	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1778	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1779	VINF_IOM_R3_IOPORT_WRITE);
1780	#else
1781	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1782	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1783	VINF_SUCCESS);
1784	#endif
1785	RT_UNTRUSTED_VALIDATED_FENCE();
1786
1787	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1788	if ( idxReg >= SVGA_REG_ID_0_TOP
1789	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1790	{
1791	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1792	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1793	}
1794	#ifdef LOG_ENABLED
1795	if (idxReg != SVGA_REG_DEV_CAP)
1796	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1797	else
1798	Log(("vmsvgaWritePort index=%s (%d) val=%s (%d)\n", vmsvgaIndexToString(pThis, idxReg), idxReg, vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)u32), u32));
1799	#endif
1800	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1801	switch (idxReg)
1802	{
1803	case SVGA_REG_WIDTH:
1804	case SVGA_REG_HEIGHT:
1805	case SVGA_REG_PITCHLOCK:
1806	case SVGA_REG_BITS_PER_PIXEL:
1807	pThis->svga.fGFBRegisters = true;
1808	break;
1809	default:
1810	break;
1811	}
1812
1813	switch (idxReg)
1814	{
1815	case SVGA_REG_ID:
1816	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1817	if ( u32 == SVGA_ID_0
1818	\|\| u32 == SVGA_ID_1
1819	\|\| u32 == SVGA_ID_2)
1820	pThis->svga.u32SVGAId = u32;
1821	else
1822	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1823	break;
1824
1825	case SVGA_REG_ENABLE:
1826	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1827	#ifdef IN_RING3
1828	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1829	&& pThis->svga.fEnabled == false)
1830	{
1831	/* Make a backup copy of the first 512kb in order to save font data etc. */
1832	/** @todo should probably swap here, rather than copy + zero */
1833	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1834	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1835	}
1836
1837	pThis->svga.fEnabled = u32;
1838	if (pThis->svga.fEnabled)
1839	{
1840	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1841	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1842	{
1843	/* Keep the current mode. */
1844	pThis->svga.uWidth = pThisCC->pDrv->cx;
1845	pThis->svga.uHeight = pThisCC->pDrv->cy;
1846	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1847	vmsvgaHCUpdatePitch(pThis, pThisCC);
1848	}
1849
1850	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1851	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1852	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1853	# ifdef LOG_ENABLED
1854	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1855	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1856	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1857	# endif
1858
1859	/* Disable or enable dirty page tracking according to the current fTraces value. */
1860	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1861
1862	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1863	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1864	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1865
1866	/* Make the cursor visible again as needed. */
1867	if (pSVGAState->Cursor.fActive)
1868	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, false, 0, 0, 0, 0, NULL);
1869	}
1870	else
1871	{
1872	/* Make sure the cursor is off. */
1873	if (pSVGAState->Cursor.fActive)
1874	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /fVisible/, false, 0, 0, 0, 0, NULL);
1875
1876	/* Restore the text mode backup. */
1877	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1878
1879	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1880
1881	/* Enable dirty page tracking again when going into legacy mode. */
1882	vmsvgaR3SetTraces(pDevIns, pThis, true);
1883
1884	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1885	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1886	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1887
1888	/* Clear the pitch lock. */
1889	pThis->svga.u32PitchLock = 0;
1890	}
1891	#else /* !IN_RING3 */
1892	rc = VINF_IOM_R3_IOPORT_WRITE;
1893	#endif /* !IN_RING3 */
1894	break;
1895
1896	case SVGA_REG_WIDTH:
1897	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1898	if (u32 != pThis->svga.uWidth)
1899	{
1900	if (u32 <= pThis->svga.u32MaxWidth)
1901	{
1902	#if defined(IN_RING3) \|\| defined(IN_RING0)
1903	pThis->svga.uWidth = u32;
1904	vmsvgaHCUpdatePitch(pThis, pThisCC);
1905	if (pThis->svga.fEnabled)
1906	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1907	#else
1908	rc = VINF_IOM_R3_IOPORT_WRITE;
1909	#endif
1910	}
1911	else
1912	Log(("SVGA_REG_WIDTH: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxWidth));
1913	}
1914	/* else: nop */
1915	break;
1916
1917	case SVGA_REG_HEIGHT:
1918	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1919	if (u32 != pThis->svga.uHeight)
1920	{
1921	if (u32 <= pThis->svga.u32MaxHeight)
1922	{
1923	pThis->svga.uHeight = u32;
1924	if (pThis->svga.fEnabled)
1925	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1926	}
1927	else
1928	Log(("SVGA_REG_HEIGHT: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxHeight));
1929	}
1930	/* else: nop */
1931	break;
1932
1933	case SVGA_REG_DEPTH:
1934	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1935	/** @todo read-only?? */
1936	break;
1937
1938	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1939	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1940	if (pThis->svga.uBpp != u32)
1941	{
1942	if (u32 <= 32)
1943	{
1944	#if defined(IN_RING3) \|\| defined(IN_RING0)
1945	pThis->svga.uBpp = u32;
1946	vmsvgaHCUpdatePitch(pThis, pThisCC);
1947	if (pThis->svga.fEnabled)
1948	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1949	#else
1950	rc = VINF_IOM_R3_IOPORT_WRITE;
1951	#endif
1952	}
1953	else
1954	Log(("SVGA_REG_BITS_PER_PIXEL: New value is out of bounds: %u, max 32\n", u32));
1955	}
1956	/* else: nop */
1957	break;
1958
1959	case SVGA_REG_PSEUDOCOLOR:
1960	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1961	break;
1962
1963	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1964	#ifdef IN_RING3
1965	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1966	pThis->svga.fConfigured = u32;
1967	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1968	if (!pThis->svga.fConfigured)
1969	pThis->svga.fTraces = true;
1970	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1971	#else
1972	rc = VINF_IOM_R3_IOPORT_WRITE;
1973	#endif
1974	break;
1975
1976	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1977	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1978	if ( pThis->svga.fEnabled
1979	&& pThis->svga.fConfigured)
1980	{
1981	#if defined(IN_RING3) \|\| defined(IN_RING0)
1982	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1983	/*
1984	* The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
1985	* at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
1986	*/
1987	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1988	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1989	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1990
1991	/* Kick the FIFO thread to start processing commands again. */
1992	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1993	#else
1994	rc = VINF_IOM_R3_IOPORT_WRITE;
1995	#endif
1996	}
1997	/* else nothing to do. */
1998	else
1999	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
2000
2001	break;
2002
2003	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
2004	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
2005	break;
2006
2007	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
2008	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
2009	pThis->svga.u32GuestId = u32;
2010	break;
2011
2012	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
2013	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
2014	pThis->svga.u32PitchLock = u32;
2015	/* Should this also update the FIFO pitch lock? Unclear. */
2016	break;
2017
2018	case SVGA_REG_IRQMASK: /* Interrupt mask */
2019	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
2020	pThis->svga.u32IrqMask = u32;
2021
2022	/* Irq pending after the above change? */
2023	if (pThis->svga.u32IrqStatus & u32)
2024	{
2025	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
2026	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
2027	}
2028	else
2029	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2030	break;
2031
2032	/* Mouse cursor support */
2033	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
2034	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
2035	pThis->svga.uCursorID = u32;
2036	break;
2037
2038	case SVGA_REG_CURSOR_X:
2039	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
2040	pThis->svga.uCursorX = u32;
2041	break;
2042
2043	case SVGA_REG_CURSOR_Y:
2044	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
2045	pThis->svga.uCursorY = u32;
2046	break;
2047
2048	case SVGA_REG_CURSOR_ON:
2049	#ifdef IN_RING3
2050	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
2051	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
2052	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
2053	#else
2054	rc = VINF_IOM_R3_IOPORT_WRITE;
2055	#endif
2056	break;
2057
2058	/* Legacy multi-monitor support */
2059	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
2060	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
2061	break;
2062	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
2063	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
2064	break;
2065	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
2066	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
2067	break;
2068	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
2069	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
2070	break;
2071	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
2072	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
2073	break;
2074	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
2075	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
2076	break;
2077	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
2078	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
2079	break;
2080	#ifdef VBOX_WITH_VMSVGA3D
2081	/* See "Guest memory regions" below. */
2082	case SVGA_REG_GMR_ID:
2083	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
2084	pThis->svga.u32CurrentGMRId = u32;
2085	break;
2086
2087	case SVGA_REG_GMR_DESCRIPTOR:
2088	# ifndef IN_RING3
2089	rc = VINF_IOM_R3_IOPORT_WRITE;
2090	break;
2091	# else /* IN_RING3 */
2092	{
2093	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
2094
2095	/* Validate current GMR id. */
2096	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
2097	AssertBreak(idGMR < pThis->svga.cGMR);
2098	RT_UNTRUSTED_VALIDATED_FENCE();
2099
2100	/* Free the old GMR if present. */
2101	vmsvgaR3GmrFree(pThisCC, idGMR);
2102
2103	/* Just undefine the GMR? */
2104	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
2105	if (GCPhys == 0)
2106	{
2107	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
2108	break;
2109	}
2110
2111
2112	/* Never cross a page boundary automatically. */
2113	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
2114	uint32_t cPagesTotal = 0;
2115	uint32_t iDesc = 0;
2116	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2117	uint32_t cLoops = 0;
2118	RTGCPHYS GCPhysBase = GCPhys;
2119	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
2120	{
2121	/* Read descriptor. */
2122	SVGAGuestMemDescriptor desc;
2123	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2124	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2125
2126	if (desc.numPages != 0)
2127	{
2128	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2129	cPagesTotal += desc.numPages;
2130	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2131
2132	if ((iDesc & 15) == 0)
2133	{
2134	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
2135	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2136	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2137	}
2138
2139	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2140	paDescs[iDesc++].numPages = desc.numPages;
2141
2142	/* Continue with the next descriptor. */
2143	GCPhys += sizeof(desc);
2144	}
2145	else if (desc.ppn == 0)
2146	break; /* terminator */
2147	else /* Pointer to the next physical page of descriptors. */
2148	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2149
2150	cLoops++;
2151	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2152	}
2153
2154	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2155	if (RT_SUCCESS(rc))
2156	{
2157	/* Commit the GMR. */
2158	pSVGAState->paGMR[idGMR].paDesc = paDescs;
2159	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2160	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2161	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
2162	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
2163	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2164	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2165	}
2166	else
2167	{
2168	RTMemFree(paDescs);
2169	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2170	}
2171	break;
2172	}
2173	# endif /* IN_RING3 */
2174	#endif // VBOX_WITH_VMSVGA3D
2175
2176	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2177	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2178	if (pThis->svga.fTraces == u32)
2179	break; /* nothing to do */
2180
2181	#ifdef IN_RING3
2182	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2183	#else
2184	rc = VINF_IOM_R3_IOPORT_WRITE;
2185	#endif
2186	break;
2187
2188	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2189	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2190	break;
2191
2192	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2193	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2194	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2195	break;
2196
2197	/*
2198	* SVGA_CAP_GBOBJECTS+ registers.
2199	*/
2200	case SVGA_REG_COMMAND_LOW:
2201	{
2202	/* Lower 32 bits of command buffer physical address and submit the command buffer. */
2203	#ifdef IN_RING3
2204	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowWr);
2205	pThis->svga.u32RegCommandLow = u32;
2206
2207	/* "lower 6 bits are used for the SVGACBContext" */
2208	RTGCPHYS GCPhysCB = pThis->svga.u32RegCommandHigh;
2209	GCPhysCB <<= 32;
2210	GCPhysCB \|= pThis->svga.u32RegCommandLow & ~SVGA_CB_CONTEXT_MASK;
2211	SVGACBContext const CBCtx = (SVGACBContext)(pThis->svga.u32RegCommandLow & SVGA_CB_CONTEXT_MASK);
2212	vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, GCPhysCB, CBCtx);
2213	#else
2214	rc = VINF_IOM_R3_IOPORT_WRITE;
2215	#endif
2216	break;
2217	}
2218
2219	case SVGA_REG_COMMAND_HIGH:
2220	/* Upper 32 bits of command buffer PA. */
2221	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighWr);
2222	pThis->svga.u32RegCommandHigh = u32;
2223	break;
2224
2225	case SVGA_REG_DEV_CAP:
2226	/* Write dev cap index, read value */
2227	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapWr);
2228	pThis->svga.u32DevCapIndex = u32;
2229	break;
2230
2231	case SVGA_REG_CMD_PREPEND_LOW:
2232	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowWr);
2233	/* Not supported. */
2234	break;
2235
2236	case SVGA_REG_CMD_PREPEND_HIGH:
2237	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighWr);
2238	/* Not supported. */
2239	break;
2240
2241	case SVGA_REG_FB_START:
2242	case SVGA_REG_MEM_START:
2243	case SVGA_REG_HOST_BITS_PER_PIXEL:
2244	case SVGA_REG_MAX_WIDTH:
2245	case SVGA_REG_MAX_HEIGHT:
2246	case SVGA_REG_VRAM_SIZE:
2247	case SVGA_REG_FB_SIZE:
2248	case SVGA_REG_CAPABILITIES:
2249	case SVGA_REG_MEM_SIZE:
2250	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2251	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2252	case SVGA_REG_BYTES_PER_LINE:
2253	case SVGA_REG_FB_OFFSET:
2254	case SVGA_REG_RED_MASK:
2255	case SVGA_REG_GREEN_MASK:
2256	case SVGA_REG_BLUE_MASK:
2257	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2258	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2259	case SVGA_REG_GMR_MAX_IDS:
2260	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2261	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
2262	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
2263	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
2264	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
2265	case SVGA_REG_MOB_MAX_SIZE:
2266	/* Read only - ignore. */
2267	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2268	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2269	break;
2270
2271	default:
2272	{
2273	uint32_t offReg;
2274	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2275	{
2276	RT_UNTRUSTED_VALIDATED_FENCE();
2277	pThis->svga.au32ScratchRegion[offReg] = u32;
2278	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2279	}
2280	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2281	{
2282	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2283	Btw, see rgb_to_pixel32. */
2284	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2285	u32 &= 0xff;
2286	RT_UNTRUSTED_VALIDATED_FENCE();
2287	uint32_t uRgb = pThis->last_palette[offReg / 3];
2288	switch (offReg % 3)
2289	{
2290	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2291	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2292	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2293	}
2294	pThis->last_palette[offReg / 3] = uRgb;
2295	}
2296	else
2297	{
2298	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2299	rc = VINF_IOM_R3_IOPORT_WRITE;
2300	#else
2301	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2302	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2303	#endif
2304	}
2305	break;
2306	}
2307	}
2308	return rc;
2309	}
2310
2311	/**
2312	* @callback_method_impl{FNIOMIOPORTNEWIN}
2313	*/
2314	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2315	{
2316	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2317	RT_NOREF_PV(pvUser);
2318
2319	/* Only dword accesses. */
2320	if (cb == 4)
2321	{
2322	switch (offPort)
2323	{
2324	case SVGA_INDEX_PORT:
2325	*pu32 = pThis->svga.u32IndexReg;
2326	break;
2327
2328	case SVGA_VALUE_PORT:
2329	return vmsvgaReadPort(pDevIns, pThis, pu32);
2330
2331	case SVGA_BIOS_PORT:
2332	Log(("Ignoring BIOS port read\n"));
2333	*pu32 = 0;
2334	break;
2335
2336	case SVGA_IRQSTATUS_PORT:
2337	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2338	*pu32 = pThis->svga.u32IrqStatus;
2339	break;
2340
2341	default:
2342	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2343	*pu32 = UINT32_MAX;
2344	break;
2345	}
2346	}
2347	else
2348	{
2349	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2350	*pu32 = UINT32_MAX;
2351	}
2352	return VINF_SUCCESS;
2353	}
2354
2355	/**
2356	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2357	*/
2358	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2359	{
2360	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2361	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2362	RT_NOREF_PV(pvUser);
2363
2364	/* Only dword accesses. */
2365	if (cb == 4)
2366	switch (offPort)
2367	{
2368	case SVGA_INDEX_PORT:
2369	pThis->svga.u32IndexReg = u32;
2370	break;
2371
2372	case SVGA_VALUE_PORT:
2373	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2374
2375	case SVGA_BIOS_PORT:
2376	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2377	break;
2378
2379	case SVGA_IRQSTATUS_PORT:
2380	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2381	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2382	/* Clear the irq in case all events have been cleared. */
2383	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2384	{
2385	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2386	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2387	}
2388	break;
2389
2390	default:
2391	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2392	break;
2393	}
2394	else
2395	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2396
2397	return VINF_SUCCESS;
2398	}
2399
2400	#ifdef IN_RING3
2401
2402	# ifdef DEBUG_FIFO_ACCESS
2403	/**
2404	* Handle FIFO memory access.
2405	* @returns VBox status code.
2406	* @param pVM VM handle.
2407	* @param pThis The shared VGA/VMSVGA instance data.
2408	* @param GCPhys The access physical address.
2409	* @param fWriteAccess Read or write access
2410	*/
2411	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2412	{
2413	RT_NOREF(pVM);
2414	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2415	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2416
2417	switch (GCPhysOffset >> 2)
2418	{
2419	case SVGA_FIFO_MIN:
2420	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2421	break;
2422	case SVGA_FIFO_MAX:
2423	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2424	break;
2425	case SVGA_FIFO_NEXT_CMD:
2426	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2427	break;
2428	case SVGA_FIFO_STOP:
2429	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2430	break;
2431	case SVGA_FIFO_CAPABILITIES:
2432	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2433	break;
2434	case SVGA_FIFO_FLAGS:
2435	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2436	break;
2437	case SVGA_FIFO_FENCE:
2438	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2439	break;
2440	case SVGA_FIFO_3D_HWVERSION:
2441	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2442	break;
2443	case SVGA_FIFO_PITCHLOCK:
2444	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2445	break;
2446	case SVGA_FIFO_CURSOR_ON:
2447	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2448	break;
2449	case SVGA_FIFO_CURSOR_X:
2450	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2451	break;
2452	case SVGA_FIFO_CURSOR_Y:
2453	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2454	break;
2455	case SVGA_FIFO_CURSOR_COUNT:
2456	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2457	break;
2458	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2459	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2460	break;
2461	case SVGA_FIFO_RESERVED:
2462	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2463	break;
2464	case SVGA_FIFO_CURSOR_SCREEN_ID:
2465	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2466	break;
2467	case SVGA_FIFO_DEAD:
2468	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2469	break;
2470	case SVGA_FIFO_3D_HWVERSION_REVISED:
2471	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2472	break;
2473	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2474	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2475	break;
2476	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2477	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2478	break;
2479	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2480	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2481	break;
2482	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2483	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2484	break;
2485	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2486	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2487	break;
2488	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2489	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2490	break;
2491	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2492	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2493	break;
2494	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2495	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2496	break;
2497	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2498	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2499	break;
2500	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2501	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2502	break;
2503	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2504	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2505	break;
2506	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2507	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2508	break;
2509	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2510	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2511	break;
2512	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2513	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2514	break;
2515	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2516	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2517	break;
2518	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2519	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2520	break;
2521	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2522	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2523	break;
2524	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2525	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2526	break;
2527	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2528	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2529	break;
2530	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2531	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2532	break;
2533	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2534	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2535	break;
2536	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2537	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2538	break;
2539	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2540	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2541	break;
2542	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2543	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2544	break;
2545	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2546	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2547	break;
2548	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2549	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2550	break;
2551	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2552	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2553	break;
2554	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2555	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2556	break;
2557	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2558	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2559	break;
2560	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2561	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2562	break;
2563	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2564	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2565	break;
2566	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2567	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2568	break;
2569	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2570	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2571	break;
2572	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2573	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2574	break;
2575	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2576	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2577	break;
2578	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2579	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2580	break;
2581	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2582	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2583	break;
2584	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2585	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2586	break;
2587	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2588	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2589	break;
2590	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2591	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2592	break;
2593	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2594	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2595	break;
2596	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2597	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2598	break;
2599	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2600	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2601	break;
2602	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2603	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2604	break;
2605	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2606	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2607	break;
2608	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2609	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2610	break;
2611	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2612	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2613	break;
2614	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2615	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2616	break;
2617	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2618	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2619	break;
2620	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2621	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2622	break;
2623	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2624	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2625	break;
2626	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2627	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2628	break;
2629	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2630	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2631	break;
2632	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2633	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2634	break;
2635	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2636	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2637	break;
2638	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2639	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2640	break;
2641	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2642	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2643	break;
2644	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2645	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2646	break;
2647	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2648	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2649	break;
2650	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2651	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2652	break;
2653	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2654	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2655	break;
2656	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2657	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2658	break;
2659	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2660	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2661	break;
2662	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2663	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2664	break;
2665	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2666	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2667	break;
2668	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2669	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2670	break;
2671	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2672	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2673	break;
2674	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2675	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2676	break;
2677	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2678	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2679	break;
2680	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD4: /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
2681	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD4 (SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2682	break;
2683	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD5: /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
2684	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD5 (SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2685	break;
2686	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD7: /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
2687	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD7 (SVGA3D_DEVCAP_ALPHATOCOVERAGE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2688	break;
2689	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD6: /* SVGA3D_DEVCAP_SUPERSAMPLE */
2690	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD6 (SVGA3D_DEVCAP_SUPERSAMPLE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2691	break;
2692	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2693	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2694	break;
2695	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2696	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2697	break;
2698	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
2699	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD10 (SVGA3D_DEVCAP_SURFACEFMT_AYUV) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2700	break;
2701	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2702	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2703	break;
2704	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2705	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2706	break;
2707	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2708	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2709	break;
2710	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2711	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2712	break;
2713	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2714	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2715	break;
2716	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI1:
2717	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2718	break;
2719	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI2:
2720	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2721	break;
2722	case SVGA_FIFO_3D_CAPS_LAST:
2723	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2724	break;
2725	case SVGA_FIFO_GUEST_3D_HWVERSION:
2726	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2727	break;
2728	case SVGA_FIFO_FENCE_GOAL:
2729	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2730	break;
2731	case SVGA_FIFO_BUSY:
2732	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2733	break;
2734	default:
2735	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2736	break;
2737	}
2738
2739	return VINF_EM_RAW_EMULATE_INSTR;
2740	}
2741	# endif /* DEBUG_FIFO_ACCESS */
2742
2743	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2744	/**
2745	* HC access handler for the FIFO.
2746	*
2747	* @returns VINF_SUCCESS if the handler have carried out the operation.
2748	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2749	* @param pVM VM Handle.
2750	* @param pVCpu The cross context CPU structure for the calling EMT.
2751	* @param GCPhys The physical address the guest is writing to.
2752	* @param pvPhys The HC mapping of that address.
2753	* @param pvBuf What the guest is reading/writing.
2754	* @param cbBuf How much it's reading/writing.
2755	* @param enmAccessType The access type.
2756	* @param enmOrigin Who is making the access.
2757	* @param pvUser User argument.
2758	*/
2759	static DECLCALLBACK(VBOXSTRICTRC)
2760	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2761	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2762	{
2763	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2764	PVGASTATE pThis = (PVGASTATE)pvUser;
2765	AssertPtr(pThis);
2766
2767	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2768	/*
2769	* Wake up the FIFO thread as it might have work to do now.
2770	*/
2771	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2772	AssertLogRelRC(rc);
2773	# endif
2774
2775	# ifdef DEBUG_FIFO_ACCESS
2776	/*
2777	* When in debug-fifo-access mode, we do not disable the access handler,
2778	* but leave it on as we wish to catch all access.
2779	*/
2780	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2781	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2782	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2783	/*
2784	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2785	*/
2786	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2787	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2788	# endif
2789	if (RT_SUCCESS(rc))
2790	return VINF_PGM_HANDLER_DO_DEFAULT;
2791	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2792	return rc;
2793	}
2794	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2795
2796	#endif /* IN_RING3 */
2797
2798	#ifdef DEBUG_GMR_ACCESS
2799	# ifdef IN_RING3
2800
2801	/**
2802	* HC access handler for GMRs.
2803	*
2804	* @returns VINF_SUCCESS if the handler have carried out the operation.
2805	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2806	* @param pVM VM Handle.
2807	* @param pVCpu The cross context CPU structure for the calling EMT.
2808	* @param GCPhys The physical address the guest is writing to.
2809	* @param pvPhys The HC mapping of that address.
2810	* @param pvBuf What the guest is reading/writing.
2811	* @param cbBuf How much it's reading/writing.
2812	* @param enmAccessType The access type.
2813	* @param enmOrigin Who is making the access.
2814	* @param pvUser User argument.
2815	*/
2816	static DECLCALLBACK(VBOXSTRICTRC)
2817	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2818	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2819	{
2820	PVGASTATE pThis = (PVGASTATE)pvUser;
2821	Assert(pThis);
2822	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2823	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2824
2825	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2826
2827	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2828	{
2829	PGMR pGMR = &pSVGAState->paGMR[i];
2830
2831	if (pGMR->numDescriptors)
2832	{
2833	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2834	{
2835	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2836	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2837	{
2838	/*
2839	* Turn off the write handler for this particular page and make it R/W.
2840	* Then return telling the caller to restart the guest instruction.
2841	*/
2842	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2843	AssertRC(rc);
2844	return VINF_PGM_HANDLER_DO_DEFAULT;
2845	}
2846	}
2847	}
2848	}
2849
2850	return VINF_PGM_HANDLER_DO_DEFAULT;
2851	}
2852
2853	/** Callback handler for VMR3ReqCallWaitU */
2854	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2855	{
2856	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2857	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2858	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2859	int rc;
2860
2861	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2862	{
2863	rc = PDMDevHlpPGMHandlerPhysicalRegister(pDevIns,
2864	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2865	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2866	AssertRC(rc);
2867	}
2868	return VINF_SUCCESS;
2869	}
2870
2871	/** Callback handler for VMR3ReqCallWaitU */
2872	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2873	{
2874	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2875	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2876	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2877
2878	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2879	{
2880	int rc = PDMDevHlpPGMHandlerPhysicalDeregister(pDevIns, pGMR->paDesc[i].GCPhys);
2881	AssertRC(rc);
2882	}
2883	return VINF_SUCCESS;
2884	}
2885
2886	/** Callback handler for VMR3ReqCallWaitU */
2887	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2888	{
2889	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2890
2891	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2892	{
2893	PGMR pGMR = &pSVGAState->paGMR[i];
2894
2895	if (pGMR->numDescriptors)
2896	{
2897	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2898	{
2899	int rc = PDMDevHlpPGMHandlerPhysicalReset(pDevIns, pGMR->paDesc[j].GCPhys);
2900	AssertRC(rc);
2901	}
2902	}
2903	}
2904	return VINF_SUCCESS;
2905	}
2906
2907	# endif /* IN_RING3 */
2908	#endif /* DEBUG_GMR_ACCESS */
2909
2910	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2911
2912	#ifdef IN_RING3
2913
2914
2915	/*
2916	*
2917	* Command buffer submission.
2918	*
2919	* Guest submits a buffer by writing to SVGA_REG_COMMAND_LOW register.
2920	*
2921	* EMT thread appends a command buffer to the context queue (VMSVGACMDBUFCTX::listSubmitted)
2922	* and wakes up the FIFO thread.
2923	*
2924	* FIFO thread fetches the command buffer from the queue, processes the commands and writes
2925	* the buffer header back to the guest memory.
2926	*
2927	* If buffers are preempted, then the EMT thread removes all buffers from the context queue.
2928	*
2929	*/
2930
2931
2932	/** Update a command buffer header 'status' and 'errorOffset' fields in the guest memory.
2933	*
2934	* @param pDevIns The device instance.
2935	* @param GCPhysCB Guest physical address of the command buffer header.
2936	* @param status Command buffer status (SVGA_CB_STATUS_*).
2937	* @param errorOffset Offset to the first byte of the failing command for SVGA_CB_STATUS_COMMAND_ERROR.
2938	* errorOffset is ignored if the status is not SVGA_CB_STATUS_COMMAND_ERROR.
2939	* @thread FIFO or EMT.
2940	*/
2941	static void vmsvgaR3CmdBufWriteStatus(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCB, SVGACBStatus status, uint32_t errorOffset)
2942	{
2943	SVGACBHeader hdr;
2944	hdr.status = status;
2945	hdr.errorOffset = errorOffset;
2946	AssertCompile( RT_OFFSETOF(SVGACBHeader, status) == 0
2947	&& RT_OFFSETOF(SVGACBHeader, errorOffset) == 4
2948	&& RT_OFFSETOF(SVGACBHeader, id) == 8);
2949	size_t const cbWrite = status == SVGA_CB_STATUS_COMMAND_ERROR
2950	? RT_UOFFSET_AFTER(SVGACBHeader, errorOffset) /* Both 'status' and 'errorOffset' fields. */
2951	: RT_UOFFSET_AFTER(SVGACBHeader, status); /* Only 'status' field. */
2952	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysCB, &hdr, cbWrite);
2953	}
2954
2955
2956	/** Raise an IRQ.
2957	*
2958	* @param pDevIns The device instance.
2959	* @param pThis The shared VGA/VMSVGA state.
2960	* @param u32IrqStatus SVGA_IRQFLAG_* bits.
2961	* @thread FIFO or EMT.
2962	*/
2963	static void vmsvgaR3CmdBufRaiseIRQ(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t u32IrqStatus)
2964	{
2965	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
2966	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
2967
2968	if (pThis->svga.u32IrqMask & u32IrqStatus)
2969	{
2970	LogFunc(("Trigger interrupt with status %#x\n", u32IrqStatus));
2971	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
2972	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
2973	}
2974
2975	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
2976	}
2977
2978
2979	/** Allocate a command buffer structure.
2980	*
2981	* @param pCmdBufCtx The command buffer context which must allocate the buffer.
2982	* @return Pointer to the allocated command buffer structure.
2983	*/
2984	static PVMSVGACMDBUF vmsvgaR3CmdBufAlloc(PVMSVGACMDBUFCTX pCmdBufCtx)
2985	{
2986	if (!pCmdBufCtx)
2987	return NULL;
2988
2989	PVMSVGACMDBUF pCmdBuf = (PVMSVGACMDBUF)RTMemAllocZ(sizeof(*pCmdBuf));
2990	if (pCmdBuf)
2991	{
2992	// RT_ZERO(pCmdBuf->nodeBuffer);
2993	pCmdBuf->pCmdBufCtx = pCmdBufCtx;
2994	// pCmdBuf->GCPhysCB = 0;
2995	// RT_ZERO(pCmdBuf->hdr);
2996	// pCmdBuf->pvCommands = NULL;
2997	}
2998
2999	return pCmdBuf;
3000	}
3001
3002
3003	/** Free a command buffer structure.
3004	*
3005	* @param pCmdBuf The command buffer pointer.
3006	*/
3007	static void vmsvgaR3CmdBufFree(PVMSVGACMDBUF pCmdBuf)
3008	{
3009	if (pCmdBuf)
3010	RTMemFree(pCmdBuf->pvCommands);
3011	RTMemFree(pCmdBuf);
3012	}
3013
3014
3015	/** Initialize a command buffer context.
3016	*
3017	* @param pCmdBufCtx The command buffer context.
3018	*/
3019	static void vmsvgaR3CmdBufCtxInit(PVMSVGACMDBUFCTX pCmdBufCtx)
3020	{
3021	RTListInit(&pCmdBufCtx->listSubmitted);
3022	pCmdBufCtx->cSubmitted = 0;
3023	}
3024
3025
3026	/** Destroy a command buffer context.
3027	*
3028	* @param pCmdBufCtx The command buffer context pointer.
3029	*/
3030	static void vmsvgaR3CmdBufCtxTerm(PVMSVGACMDBUFCTX pCmdBufCtx)
3031	{
3032	if (!pCmdBufCtx)
3033	return;
3034
3035	if (pCmdBufCtx->listSubmitted.pNext)
3036	{
3037	/* If the list has been initialized. */
3038	PVMSVGACMDBUF pIter, pNext;
3039	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3040	{
3041	RTListNodeRemove(&pIter->nodeBuffer);
3042	--pCmdBufCtx->cSubmitted;
3043	vmsvgaR3CmdBufFree(pIter);
3044	}
3045	}
3046	Assert(pCmdBufCtx->cSubmitted == 0);
3047	pCmdBufCtx->cSubmitted = 0;
3048	}
3049
3050
3051	/** Handles SVGA_DC_CMD_START_STOP_CONTEXT command.
3052	*
3053	* @param pSvgaR3State VMSVGA R3 state.
3054	* @param pCmd The command data.
3055	* @return SVGACBStatus code.
3056	* @thread EMT
3057	*/
3058	static SVGACBStatus vmsvgaR3CmdBufDCStartStop(PVMSVGAR3STATE pSvgaR3State, SVGADCCmdStartStop const *pCmd)
3059	{
3060	/* Create or destroy a regular command buffer context. */
3061	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3062	return SVGA_CB_STATUS_COMMAND_ERROR;
3063	RT_UNTRUSTED_VALIDATED_FENCE();
3064
3065	SVGACBStatus CBStatus = SVGA_CB_STATUS_COMPLETED;
3066
3067	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3068	AssertRC(rc);
3069	if (pCmd->enable)
3070	{
3071	pSvgaR3State->apCmdBufCtxs[pCmd->context] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
3072	if (pSvgaR3State->apCmdBufCtxs[pCmd->context])
3073	vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3074	else
3075	CBStatus = SVGA_CB_STATUS_QUEUE_FULL;
3076	}
3077	else
3078	{
3079	vmsvgaR3CmdBufCtxTerm(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3080	pSvgaR3State->apCmdBufCtxs[pCmd->context] = NULL;
3081	}
3082	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3083
3084	return CBStatus;
3085	}
3086
3087
3088	/** Handles SVGA_DC_CMD_PREEMPT command.
3089	*
3090	* @param pDevIns The device instance.
3091	* @param pSvgaR3State VMSVGA R3 state.
3092	* @param pCmd The command data.
3093	* @return SVGACBStatus code.
3094	* @thread EMT
3095	*/
3096	static SVGACBStatus vmsvgaR3CmdBufDCPreempt(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, SVGADCCmdPreempt const *pCmd)
3097	{
3098	/* Remove buffers from the processing queue of the specified context. */
3099	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3100	return SVGA_CB_STATUS_COMMAND_ERROR;
3101	RT_UNTRUSTED_VALIDATED_FENCE();
3102
3103	PVMSVGACMDBUFCTX const pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[pCmd->context];
3104	RTLISTANCHOR listPreempted;
3105
3106	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3107	AssertRC(rc);
3108	if (pCmd->ignoreIDZero)
3109	{
3110	RTListInit(&listPreempted);
3111
3112	PVMSVGACMDBUF pIter, pNext;
3113	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3114	{
3115	if (pIter->hdr.id == 0)
3116	continue;
3117
3118	RTListNodeRemove(&pIter->nodeBuffer);
3119	--pCmdBufCtx->cSubmitted;
3120	RTListAppend(&listPreempted, &pIter->nodeBuffer);
3121	}
3122	}
3123	else
3124	{
3125	RTListMove(&listPreempted, &pCmdBufCtx->listSubmitted);
3126	}
3127	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3128
3129	PVMSVGACMDBUF pIter, pNext;
3130	RTListForEachSafe(&listPreempted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3131	{
3132	RTListNodeRemove(&pIter->nodeBuffer);
3133	vmsvgaR3CmdBufWriteStatus(pDevIns, pIter->GCPhysCB, SVGA_CB_STATUS_PREEMPTED, 0);
3134	vmsvgaR3CmdBufFree(pIter);
3135	}
3136
3137	return SVGA_CB_STATUS_COMPLETED;
3138	}
3139
3140
3141	/** @def VMSVGA_INC_CMD_SIZE_BREAK
3142	* Increments the size of the command cbCmd by a_cbMore.
3143	* Checks that the command buffer has at least cbCmd bytes. Will break out of the switch if it doesn't.
3144	* Used by vmsvgaR3CmdBufProcessDC and vmsvgaR3CmdBufProcessCommands.
3145	*/
3146	#define VMSVGA_INC_CMD_SIZE_BREAK(a_cbMore) \
3147	if (1) { \
3148	cbCmd += (a_cbMore); \
3149	ASSERT_GUEST_MSG_STMT_BREAK(cbRemain >= cbCmd, ("size=%#x remain=%#zx\n", cbCmd, (size_t)cbRemain), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR); \
3150	RT_UNTRUSTED_VALIDATED_FENCE(); \
3151	} else do {} while (0)
3152
3153
3154	/** Processes Device Context command buffer.
3155	*
3156	* @param pDevIns The device instance.
3157	* @param pSvgaR3State VMSVGA R3 state.
3158	* @param pvCommands Pointer to the command buffer.
3159	* @param cbCommands Size of the command buffer.
3160	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3161	* @return SVGACBStatus code.
3162	* @thread EMT
3163	*/
3164	static SVGACBStatus vmsvgaR3CmdBufProcessDC(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd)
3165	{
3166	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3167
3168	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3169	uint32_t cbRemain = cbCommands;
3170	while (cbRemain)
3171	{
3172	/* Command identifier is a 32 bit value. */
3173	if (cbRemain < sizeof(uint32_t))
3174	{
3175	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3176	break;
3177	}
3178
3179	/* Fetch the command id. */
3180	uint32_t const cmdId = (uint32_t )pu8Cmd;
3181	uint32_t cbCmd = sizeof(uint32_t);
3182	switch (cmdId)
3183	{
3184	case SVGA_DC_CMD_NOP:
3185	{
3186	/* NOP */
3187	break;
3188	}
3189
3190	case SVGA_DC_CMD_START_STOP_CONTEXT:
3191	{
3192	SVGADCCmdStartStop pCmd = (SVGADCCmdStartStop )&pu8Cmd[cbCmd];
3193	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3194	CBstatus = vmsvgaR3CmdBufDCStartStop(pSvgaR3State, pCmd);
3195	break;
3196	}
3197
3198	case SVGA_DC_CMD_PREEMPT:
3199	{
3200	SVGADCCmdPreempt pCmd = (SVGADCCmdPreempt )&pu8Cmd[cbCmd];
3201	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3202	CBstatus = vmsvgaR3CmdBufDCPreempt(pDevIns, pSvgaR3State, pCmd);
3203	break;
3204	}
3205
3206	default:
3207	{
3208	/* Unsupported command. */
3209	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3210	break;
3211	}
3212	}
3213
3214	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3215	break;
3216
3217	pu8Cmd += cbCmd;
3218	cbRemain -= cbCmd;
3219	}
3220
3221	Assert(cbRemain <= cbCommands);
3222	*poffNextCmd = cbCommands - cbRemain;
3223	return CBstatus;
3224	}
3225
3226
3227	/** Submits a device context command buffer for synchronous processing.
3228	*
3229	* @param pDevIns The device instance.
3230	* @param pThisCC The VGA/VMSVGA state for the current context.
3231	* @param ppCmdBuf Pointer to the command buffer pointer.
3232	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3233	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3234	* @return SVGACBStatus code.
3235	* @thread EMT
3236	*/
3237	static SVGACBStatus vmsvgaR3CmdBufSubmitDC(PPDMDEVINS pDevIns, PVGASTATECC pThisCC, PVMSVGACMDBUF ppCmdBuf, uint32_t poffNextCmd)
3238	{
3239	/* Synchronously process the device context commands. */
3240	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3241	return vmsvgaR3CmdBufProcessDC(pDevIns, pSvgaR3State, (ppCmdBuf)->pvCommands, (ppCmdBuf)->hdr.length, poffNextCmd);
3242	}
3243
3244	/** Submits a command buffer for asynchronous processing by the FIFO thread.
3245	*
3246	* @param pDevIns The device instance.
3247	* @param pThis The shared VGA/VMSVGA state.
3248	* @param pThisCC The VGA/VMSVGA state for the current context.
3249	* @param ppCmdBuf Pointer to the command buffer pointer.
3250	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3251	* @return SVGACBStatus code.
3252	* @thread EMT
3253	*/
3254	static SVGACBStatus vmsvgaR3CmdBufSubmitCtx(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf)
3255	{
3256	/* Command buffer submission. */
3257	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3258
3259	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3260
3261	PVMSVGACMDBUF const pCmdBuf = *ppCmdBuf;
3262	PVMSVGACMDBUFCTX const pCmdBufCtx = pCmdBuf->pCmdBufCtx;
3263
3264	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3265	AssertRC(rc);
3266
3267	if (RT_LIKELY(pCmdBufCtx->cSubmitted < SVGA_CB_MAX_QUEUED_PER_CONTEXT))
3268	{
3269	RTListAppend(&pCmdBufCtx->listSubmitted, &pCmdBuf->nodeBuffer);
3270	++pCmdBufCtx->cSubmitted;
3271	ppCmdBuf = NULL; / Consume the buffer. */
3272	ASMAtomicWriteU32(&pThisCC->svga.pSvgaR3State->fCmdBuf, 1);
3273	}
3274	else
3275	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3276
3277	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3278
3279	/* Inform the FIFO thread. */
3280	if (*ppCmdBuf == NULL)
3281	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3282
3283	return CBstatus;
3284	}
3285
3286
3287	/** SVGA_REG_COMMAND_LOW write handler.
3288	* Submits a command buffer to the FIFO thread or processes a device context command.
3289	*
3290	* @param pDevIns The device instance.
3291	* @param pThis The shared VGA/VMSVGA state.
3292	* @param pThisCC The VGA/VMSVGA state for the current context.
3293	* @param GCPhysCB Guest physical address of the command buffer header.
3294	* @param CBCtx Context the command buffer is submitted to.
3295	* @thread EMT
3296	*/
3297	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx)
3298	{
3299	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3300
3301	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3302	uint32_t offNextCmd = 0;
3303	uint32_t fIRQ = 0;
3304
3305	/* Get the context if the device has the capability. */
3306	PVMSVGACMDBUFCTX pCmdBufCtx = NULL;
3307	if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
3308	{
3309	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3310	pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[CBCtx];
3311	else if (CBCtx == SVGA_CB_CONTEXT_DEVICE)
3312	pCmdBufCtx = &pSvgaR3State->CmdBufCtxDC;
3313	RT_UNTRUSTED_VALIDATED_FENCE();
3314	}
3315
3316	/* Allocate a new command buffer. */
3317	PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pCmdBufCtx);
3318	if (RT_LIKELY(pCmdBuf))
3319	{
3320	pCmdBuf->GCPhysCB = GCPhysCB;
3321
3322	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCB, &pCmdBuf->hdr, sizeof(pCmdBuf->hdr));
3323	if (RT_SUCCESS(rc))
3324	{
3325	LogFunc(("status %RX32 errorOffset %RX32 id %RX64 flags %RX32 length %RX32 ptr %RX64 offset %RX32 dxContext %RX32 (%RX32 %RX32 %RX32 %RX32 %RX32 %RX32)\n",
3326	pCmdBuf->hdr.status,
3327	pCmdBuf->hdr.errorOffset,
3328	pCmdBuf->hdr.id,
3329	pCmdBuf->hdr.flags,
3330	pCmdBuf->hdr.length,
3331	pCmdBuf->hdr.ptr.pa,
3332	pCmdBuf->hdr.offset,
3333	pCmdBuf->hdr.dxContext,
3334	pCmdBuf->hdr.mustBeZero[0],
3335	pCmdBuf->hdr.mustBeZero[1],
3336	pCmdBuf->hdr.mustBeZero[2],
3337	pCmdBuf->hdr.mustBeZero[3],
3338	pCmdBuf->hdr.mustBeZero[4],
3339	pCmdBuf->hdr.mustBeZero[5]));
3340
3341	/* Verify the command buffer header. */
3342	if (RT_LIKELY( pCmdBuf->hdr.status == SVGA_CB_STATUS_NONE
3343	&& (pCmdBuf->hdr.flags & ~(SVGA_CB_FLAG_NO_IRQ \| SVGA_CB_FLAG_DX_CONTEXT)) == 0 /* No unexpected flags. */
3344	&& pCmdBuf->hdr.length <= SVGA_CB_MAX_SIZE))
3345	{
3346	RT_UNTRUSTED_VALIDATED_FENCE();
3347
3348	/* Read the command buffer content. */
3349	pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
3350	if (pCmdBuf->pvCommands)
3351	{
3352	RTGCPHYS const GCPhysCmd = (RTGCPHYS)pCmdBuf->hdr.ptr.pa;
3353	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
3354	if (RT_SUCCESS(rc))
3355	{
3356	/* Submit the buffer. Device context buffers will be processed synchronously. */
3357	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3358	/* This usually processes the CB async and sets pCmbBuf to NULL. */
3359	CBstatus = vmsvgaR3CmdBufSubmitCtx(pDevIns, pThis, pThisCC, &pCmdBuf);
3360	else
3361	CBstatus = vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
3362	}
3363	else
3364	{
3365	ASSERT_GUEST_MSG_FAILED(("Failed to read commands at %RGp\n", GCPhysCmd));
3366	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3367	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3368	}
3369	}
3370	else
3371	{
3372	/* No memory for commands. */
3373	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3374	}
3375	}
3376	else
3377	{
3378	ASSERT_GUEST_MSG_FAILED(("Invalid buffer header\n"));
3379	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3380	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3381	}
3382	}
3383	else
3384	{
3385	LogFunc(("Failed to read buffer header at %RGp\n", GCPhysCB));
3386	ASSERT_GUEST_FAILED();
3387	/* Do not attempt to write the status. */
3388	}
3389
3390	/* Free the buffer if pfnCmdBufSubmit did not consume it. */
3391	vmsvgaR3CmdBufFree(pCmdBuf);
3392	}
3393	else
3394	{
3395	LogFunc(("Can't allocate buffer for context id %#x\n", CBCtx));
3396	ASSERT_GUEST_FAILED();
3397	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3398	}
3399
3400	if (CBstatus != SVGA_CB_STATUS_NONE)
3401	{
3402	LogFunc(("Write status %#x, offNextCmd %#x (of %#x), fIRQ %#x\n", CBstatus, offNextCmd, pCmdBuf ? pCmdBuf->hdr.length : 0, fIRQ));
3403	vmsvgaR3CmdBufWriteStatus(pDevIns, GCPhysCB, CBstatus, offNextCmd);
3404	if (fIRQ)
3405	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, fIRQ);
3406	}
3407	}
3408
3409
3410	/** Checks if there are some buffers to be processed.
3411	*
3412	* @param pThisCC The VGA/VMSVGA state for the current context.
3413	* @return true if buffers must be processed.
3414	* @thread FIFO
3415	*/
3416	static bool vmsvgaR3CmdBufHasWork(PVGASTATECC pThisCC)
3417	{
3418	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3419	return RT_BOOL(ASMAtomicReadU32(&pSvgaR3State->fCmdBuf));
3420	}
3421
3422
3423	/** Processes a command buffer.
3424	*
3425	* @param pDevIns The device instance.
3426	* @param pThis The shared VGA/VMSVGA state.
3427	* @param pThisCC The VGA/VMSVGA state for the current context.
3428	* @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
3429	* @param pvCommands Pointer to the command buffer.
3430	* @param cbCommands Size of the command buffer.
3431	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3432	* @param pu32IrqStatus Where to store SVGA_IRQFLAG_ if the IRQ is generated by the last command in the buffer.
3433	* @return SVGACBStatus code.
3434	* @thread FIFO
3435	*/
3436	static SVGACBStatus vmsvgaR3CmdBufProcessCommands(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd, uint32_t *pu32IrqStatus)
3437	{
3438	# ifndef VBOX_WITH_VMSVGA3D
3439	RT_NOREF(idDXContext);
3440	# endif
3441	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3442	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3443
3444	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3445
3446	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3447	uint32_t cbRemain = cbCommands;
3448	while (cbRemain)
3449	{
3450	/* Command identifier is a 32 bit value. */
3451	if (cbRemain < sizeof(uint32_t))
3452	{
3453	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3454	break;
3455	}
3456
3457	/* Fetch the command id.
3458	* 'cmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
3459	* warning. Because we support some obsolete and deprecated commands, which are not included in
3460	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
3461	*/
3462	uint32_t const cmdId = (uint32_t )pu8Cmd;
3463	uint32_t cbCmd = sizeof(uint32_t);
3464
3465	LogFlowFunc(("[cid=%d] %s %d\n", (int32_t)idDXContext, vmsvgaR3FifoCmdToString(cmdId), cmdId));
3466	# ifdef LOG_ENABLED
3467	# ifdef VBOX_WITH_VMSVGA3D
3468	if (SVGA_3D_CMD_BASE <= cmdId && cmdId < SVGA_3D_CMD_MAX)
3469	{
3470	SVGA3dCmdHeader const header = (SVGA3dCmdHeader )pu8Cmd;
3471	svga_dump_command(cmdId, (uint8_t *)&header[1], header->size);
3472	}
3473	else if (cmdId == SVGA_CMD_FENCE)
3474	{
3475	Log7(("\tSVGA_CMD_FENCE\n"));
3476	Log7(("\t\t0x%08x\n", ((uint32_t *)pu8Cmd)[1]));
3477	}
3478	# endif
3479	# endif
3480
3481	/* At the end of the switch cbCmd is equal to the total length of the command including the cmdId.
3482	* I.e. pu8Cmd + cbCmd must point to the next command.
3483	* However if CBstatus is set to anything but SVGA_CB_STATUS_COMPLETED in the switch, then
3484	* the cbCmd value is ignored (and pu8Cmd still points to the failed command).
3485	*/
3486	/** @todo This code is very similar to the FIFO loop command processing. Think about merging. */
3487	switch (cmdId)
3488	{
3489	case SVGA_CMD_INVALID_CMD:
3490	{
3491	/* Nothing to do. */
3492	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdInvalidCmd);
3493	break;
3494	}
3495
3496	case SVGA_CMD_FENCE:
3497	{
3498	SVGAFifoCmdFence pCmd = (SVGAFifoCmdFence )&pu8Cmd[cbCmd];
3499	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3500	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdFence);
3501	Log(("SVGA_CMD_FENCE %#x\n", pCmd->fence));
3502
3503	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3504	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3505	{
3506	pFIFO[SVGA_FIFO_FENCE] = pCmd->fence;
3507
3508	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3509	{
3510	Log(("any fence irq\n"));
3511	*pu32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3512	}
3513	else if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3514	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3515	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmd->fence)
3516	{
3517	Log(("fence goal reached irq (fence=%#x)\n", pCmd->fence));
3518	*pu32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3519	}
3520	}
3521	else
3522	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3523	break;
3524	}
3525
3526	case SVGA_CMD_UPDATE:
3527	{
3528	SVGAFifoCmdUpdate pCmd = (SVGAFifoCmdUpdate )&pu8Cmd[cbCmd];
3529	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3530	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
3531	break;
3532	}
3533
3534	case SVGA_CMD_UPDATE_VERBOSE:
3535	{
3536	SVGAFifoCmdUpdateVerbose pCmd = (SVGAFifoCmdUpdateVerbose )&pu8Cmd[cbCmd];
3537	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3538	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
3539	break;
3540	}
3541
3542	case SVGA_CMD_DEFINE_CURSOR:
3543	{
3544	/* Followed by bitmap data. */
3545	SVGAFifoCmdDefineCursor pCmd = (SVGAFifoCmdDefineCursor )&pu8Cmd[cbCmd];
3546	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3547
3548	/* Figure out the size of the bitmap data. */
3549	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3550	ASSERT_GUEST_STMT_BREAK(pCmd->andMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3551	ASSERT_GUEST_STMT_BREAK(pCmd->xorMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3552	RT_UNTRUSTED_VALIDATED_FENCE();
3553
3554	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
3555	uint32_t const cbAndMask = cbAndLine * pCmd->height;
3556	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
3557	uint32_t const cbXorMask = cbXorLine * pCmd->height;
3558
3559	VMSVGA_INC_CMD_SIZE_BREAK(cbAndMask + cbXorMask);
3560	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
3561	break;
3562	}
3563
3564	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3565	{
3566	/* Followed by bitmap data. */
3567	SVGAFifoCmdDefineAlphaCursor pCmd = (SVGAFifoCmdDefineAlphaCursor )&pu8Cmd[cbCmd];
3568	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3569
3570	/* Figure out the size of the bitmap data. */
3571	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3572
3573	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->width * pCmd->height * sizeof(uint32_t)); /* 32-bit BRGA format */
3574	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
3575	break;
3576	}
3577
3578	case SVGA_CMD_MOVE_CURSOR:
3579	{
3580	/* Deprecated; there should be no driver which requires this command. However, if
3581	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3582	* alignment.
3583	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3584	*/
3585	SVGAFifoCmdMoveCursor pCmd = (SVGAFifoCmdMoveCursor )&pu8Cmd[cbCmd];
3586	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3587	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
3588	break;
3589	}
3590
3591	case SVGA_CMD_DISPLAY_CURSOR:
3592	{
3593	/* Deprecated; there should be no driver which requires this command. However, if
3594	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3595	* alignment.
3596	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3597	*/
3598	SVGAFifoCmdDisplayCursor pCmd = (SVGAFifoCmdDisplayCursor )&pu8Cmd[cbCmd];
3599	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3600	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
3601	break;
3602	}
3603
3604	case SVGA_CMD_RECT_FILL:
3605	{
3606	SVGAFifoCmdRectFill pCmd = (SVGAFifoCmdRectFill )&pu8Cmd[cbCmd];
3607	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3608	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
3609	break;
3610	}
3611
3612	case SVGA_CMD_RECT_COPY:
3613	{
3614	SVGAFifoCmdRectCopy pCmd = (SVGAFifoCmdRectCopy )&pu8Cmd[cbCmd];
3615	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3616	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
3617	break;
3618	}
3619
3620	case SVGA_CMD_RECT_ROP_COPY:
3621	{
3622	SVGAFifoCmdRectRopCopy pCmd = (SVGAFifoCmdRectRopCopy )&pu8Cmd[cbCmd];
3623	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3624	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
3625	break;
3626	}
3627
3628	case SVGA_CMD_ESCAPE:
3629	{
3630	/* Followed by 'size' bytes of data. */
3631	SVGAFifoCmdEscape pCmd = (SVGAFifoCmdEscape )&pu8Cmd[cbCmd];
3632	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3633
3634	ASSERT_GUEST_STMT_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3635	RT_UNTRUSTED_VALIDATED_FENCE();
3636
3637	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->size);
3638	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
3639	break;
3640	}
3641	# ifdef VBOX_WITH_VMSVGA3D
3642	case SVGA_CMD_DEFINE_GMR2:
3643	{
3644	SVGAFifoCmdDefineGMR2 pCmd = (SVGAFifoCmdDefineGMR2 )&pu8Cmd[cbCmd];
3645	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3646	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
3647	break;
3648	}
3649
3650	case SVGA_CMD_REMAP_GMR2:
3651	{
3652	/* Followed by page descriptors or guest ptr. */
3653	SVGAFifoCmdRemapGMR2 pCmd = (SVGAFifoCmdRemapGMR2 )&pu8Cmd[cbCmd];
3654	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3655
3656	/* Calculate the size of what comes after next and fetch it. */
3657	uint32_t cbMore = 0;
3658	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3659	cbMore = sizeof(SVGAGuestPtr);
3660	else
3661	{
3662	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3663	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3664	{
3665	cbMore = cbPageDesc;
3666	pCmd->numPages = 1;
3667	}
3668	else
3669	{
3670	ASSERT_GUEST_STMT_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3671	cbMore = cbPageDesc * pCmd->numPages;
3672	}
3673	}
3674	VMSVGA_INC_CMD_SIZE_BREAK(cbMore);
3675	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
3676	# ifdef DEBUG_GMR_ACCESS
3677	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
3678	# endif
3679	break;
3680	}
3681	# endif /* VBOX_WITH_VMSVGA3D */
3682	case SVGA_CMD_DEFINE_SCREEN:
3683	{
3684	/* The size of this command is specified by the guest and depends on capabilities. */
3685	SVGAFifoCmdDefineScreen pCmd = (SVGAFifoCmdDefineScreen )&pu8Cmd[cbCmd];
3686	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(pCmd->screen.structSize));
3687	ASSERT_GUEST_STMT_BREAK(pCmd->screen.structSize < pThis->svga.cbFIFO, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3688	RT_UNTRUSTED_VALIDATED_FENCE();
3689
3690	VMSVGA_INC_CMD_SIZE_BREAK(RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize) - sizeof(pCmd->screen.structSize));
3691	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
3692	break;
3693	}
3694
3695	case SVGA_CMD_DESTROY_SCREEN:
3696	{
3697	SVGAFifoCmdDestroyScreen pCmd = (SVGAFifoCmdDestroyScreen )&pu8Cmd[cbCmd];
3698	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3699	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
3700	break;
3701	}
3702
3703	case SVGA_CMD_DEFINE_GMRFB:
3704	{
3705	SVGAFifoCmdDefineGMRFB pCmd = (SVGAFifoCmdDefineGMRFB )&pu8Cmd[cbCmd];
3706	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3707	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
3708	break;
3709	}
3710
3711	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3712	{
3713	SVGAFifoCmdBlitGMRFBToScreen pCmd = (SVGAFifoCmdBlitGMRFBToScreen )&pu8Cmd[cbCmd];
3714	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3715	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
3716	break;
3717	}
3718
3719	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3720	{
3721	SVGAFifoCmdBlitScreenToGMRFB pCmd = (SVGAFifoCmdBlitScreenToGMRFB )&pu8Cmd[cbCmd];
3722	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3723	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
3724	break;
3725	}
3726
3727	case SVGA_CMD_ANNOTATION_FILL:
3728	{
3729	SVGAFifoCmdAnnotationFill pCmd = (SVGAFifoCmdAnnotationFill )&pu8Cmd[cbCmd];
3730	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3731	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
3732	break;
3733	}
3734
3735	case SVGA_CMD_ANNOTATION_COPY:
3736	{
3737	SVGAFifoCmdAnnotationCopy pCmd = (SVGAFifoCmdAnnotationCopy )&pu8Cmd[cbCmd];
3738	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3739	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
3740	break;
3741	}
3742
3743	default:
3744	{
3745	# ifdef VBOX_WITH_VMSVGA3D
3746	if ( cmdId >= SVGA_3D_CMD_BASE
3747	&& cmdId < SVGA_3D_CMD_MAX)
3748	{
3749	RT_UNTRUSTED_VALIDATED_FENCE();
3750
3751	/* All 3d commands start with a common header, which defines the identifier and the size
3752	* of the command. The identifier has been already read. Fetch the size.
3753	*/
3754	uint32_t const pcbMore = (uint32_t const )&pu8Cmd[cbCmd];
3755	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pcbMore));
3756	VMSVGA_INC_CMD_SIZE_BREAK(*pcbMore);
3757	if (RT_LIKELY(pThis->svga.f3DEnabled))
3758	{ /* likely */ }
3759	else
3760	{
3761	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", cmdId));
3762	break;
3763	}
3764
3765	/* Command data begins after the 32 bit command length. */
3766	int rc = vmsvgaR3Process3dCmd(pThis, pThisCC, idDXContext, (SVGAFifo3dCmdId)cmdId, *pcbMore, pcbMore + 1);
3767	if (RT_SUCCESS(rc))
3768	{ /* likely */ }
3769	else
3770	{
3771	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3772	break;
3773	}
3774	}
3775	else
3776	# endif /* VBOX_WITH_VMSVGA3D */
3777	{
3778	/* Unsupported command. */
3779	STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
3780	ASSERT_GUEST_MSG_FAILED(("cmdId=%d\n", cmdId));
3781	LogRelMax(16, ("VMSVGA: unsupported command %d\n", cmdId));
3782	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3783	break;
3784	}
3785	}
3786	}
3787
3788	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3789	break;
3790
3791	pu8Cmd += cbCmd;
3792	cbRemain -= cbCmd;
3793
3794	/* If this is not the last command in the buffer, then generate IRQ, if required.
3795	* This avoids a double call to vmsvgaR3CmdBufRaiseIRQ if FENCE is the last command
3796	* in the buffer (usually the case).
3797	*/
3798	if (RT_LIKELY(!(cbRemain && *pu32IrqStatus)))
3799	{ /* likely */ }
3800	else
3801	{
3802	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, *pu32IrqStatus);
3803	*pu32IrqStatus = 0;
3804	}
3805	}
3806
3807	Assert(cbRemain <= cbCommands);
3808	*poffNextCmd = cbCommands - cbRemain;
3809	return CBstatus;
3810	}
3811
3812
3813	/** Process command buffers.
3814	*
3815	* @param pDevIns The device instance.
3816	* @param pThis The shared VGA/VMSVGA state.
3817	* @param pThisCC The VGA/VMSVGA state for the current context.
3818	* @param pThread Handle of the FIFO thread.
3819	* @thread FIFO
3820	*/
3821	static void vmsvgaR3CmdBufProcessBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PPDMTHREAD pThread)
3822	{
3823	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3824
3825	for (;;)
3826	{
3827	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3828	break;
3829
3830	/* See if there is a submitted buffer. */
3831	PVMSVGACMDBUF pCmdBuf = NULL;
3832
3833	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3834	AssertRC(rc);
3835
3836	/* It seems that a higher queue index has a higher priority.
3837	* See SVGACBContext in svga_reg.h from latest vmwgfx Linux driver.
3838	*/
3839	for (unsigned i = RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs); i > 0; --i)
3840	{
3841	PVMSVGACMDBUFCTX pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[i - 1];
3842	if (pCmdBufCtx)
3843	{
3844	pCmdBuf = RTListRemoveFirst(&pCmdBufCtx->listSubmitted, VMSVGACMDBUF, nodeBuffer);
3845	if (pCmdBuf)
3846	{
3847	Assert(pCmdBufCtx->cSubmitted > 0);
3848	--pCmdBufCtx->cSubmitted;
3849	break;
3850	}
3851	}
3852	}
3853
3854	if (!pCmdBuf)
3855	{
3856	ASMAtomicWriteU32(&pSvgaR3State->fCmdBuf, 0);
3857	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3858	break;
3859	}
3860
3861	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3862
3863	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3864	uint32_t offNextCmd = 0;
3865	uint32_t u32IrqStatus = 0;
3866	uint32_t const idDXContext = RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_DX_CONTEXT)
3867	? pCmdBuf->hdr.dxContext
3868	: SVGA3D_INVALID_ID;
3869	/* Process one buffer. */
3870	CBstatus = vmsvgaR3CmdBufProcessCommands(pDevIns, pThis, pThisCC, idDXContext, pCmdBuf->pvCommands, pCmdBuf->hdr.length, &offNextCmd, &u32IrqStatus);
3871
3872	if (!RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_NO_IRQ))
3873	u32IrqStatus \|= SVGA_IRQFLAG_COMMAND_BUFFER;
3874	if (CBstatus == SVGA_CB_STATUS_COMMAND_ERROR)
3875	u32IrqStatus \|= SVGA_IRQFLAG_ERROR;
3876
3877	vmsvgaR3CmdBufWriteStatus(pDevIns, pCmdBuf->GCPhysCB, CBstatus, offNextCmd);
3878	if (u32IrqStatus)
3879	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, u32IrqStatus);
3880
3881	vmsvgaR3CmdBufFree(pCmdBuf);
3882	}
3883	}
3884
3885
3886	/**
3887	* Worker for vmsvgaR3FifoThread that handles an external command.
3888	*
3889	* @param pDevIns The device instance.
3890	* @param pThis The shared VGA/VMSVGA instance data.
3891	* @param pThisCC The VGA/VMSVGA state for ring-3.
3892	*/
3893	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3894	{
3895	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
3896	switch (pThis->svga.u8FIFOExtCommand)
3897	{
3898	case VMSVGA_FIFO_EXTCMD_RESET:
3899	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
3900	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3901
3902	vmsvgaR3ResetScreens(pThis, pThisCC);
3903	# ifdef VBOX_WITH_VMSVGA3D
3904	if (pThis->svga.f3DEnabled)
3905	{
3906	/* The 3d subsystem must be reset from the fifo thread. */
3907	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3908	pSVGAState->pFuncs3D->pfnReset(pThisCC);
3909	}
3910	# endif
3911	break;
3912
3913	case VMSVGA_FIFO_EXTCMD_POWEROFF:
3914	Log(("vmsvgaR3FifoLoop: power off.\n"));
3915	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3916
3917	/* The screens must be reset on the FIFO thread, because they may use 3D resources. */
3918	vmsvgaR3ResetScreens(pThis, pThisCC);
3919	break;
3920
3921	case VMSVGA_FIFO_EXTCMD_TERMINATE:
3922	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
3923	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3924	# ifdef VBOX_WITH_VMSVGA3D
3925	if (pThis->svga.f3DEnabled)
3926	{
3927	/* The 3d subsystem must be shut down from the fifo thread. */
3928	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3929	pSVGAState->pFuncs3D->pfnTerminate(pThisCC);
3930	}
3931	# endif
3932	break;
3933
3934	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
3935	{
3936	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
3937	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
3938	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
3939	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
3940	# ifdef VBOX_WITH_VMSVGA3D
3941	if (pThis->svga.f3DEnabled)
3942	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
3943	# endif
3944	break;
3945	}
3946
3947	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
3948	{
3949	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
3950	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
3951	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
3952	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3953	# ifdef VBOX_WITH_VMSVGA3D
3954	if (pThis->svga.f3DEnabled)
3955	{
3956	/* The following RT_OS_DARWIN code was in vmsvga3dLoadExec and therefore must be executed before each vmsvga3dLoadExec invocation. */
3957	# ifndef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA.cpp */
3958	/* Must initialize now as the recreation calls below rely on an initialized 3d subsystem. */
3959	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3960	pSVGAState->pFuncs3D->pfnPowerOn(pDevIns, pThis, pThisCC);
3961	# endif
3962
3963	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3964	}
3965	# endif
3966	break;
3967	}
3968
3969	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
3970	{
3971	# ifdef VBOX_WITH_VMSVGA3D
3972	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
3973	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
3974	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
3975	# endif
3976	break;
3977	}
3978
3979
3980	default:
3981	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
3982	break;
3983	}
3984
3985	/*
3986	* Signal the end of the external command.
3987	*/
3988	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3989	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
3990	ASMMemoryFence(); /* paranoia^2 */
3991	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
3992	AssertLogRelRC(rc);
3993	}
3994
3995	/**
3996	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
3997	* doing a job on the FIFO thread (even when it's officially suspended).
3998	*
3999	* @returns VBox status code (fully asserted).
4000	* @param pDevIns The device instance.
4001	* @param pThis The shared VGA/VMSVGA instance data.
4002	* @param pThisCC The VGA/VMSVGA state for ring-3.
4003	* @param uExtCmd The command to execute on the FIFO thread.
4004	* @param pvParam Pointer to command parameters.
4005	* @param cMsWait The time to wait for the command, given in
4006	* milliseconds.
4007	*/
4008	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
4009	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
4010	{
4011	Assert(cMsWait >= RT_MS_1SEC * 5);
4012	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
4013	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
4014
4015	int rc;
4016	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
4017	PDMTHREADSTATE enmState = pThread->enmState;
4018	if (enmState == PDMTHREADSTATE_SUSPENDED)
4019	{
4020	/*
4021	* The thread is suspended, we have to temporarily wake it up so it can
4022	* perform the task.
4023	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
4024	*/
4025	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
4026	/* Post the request. */
4027	pThis->svga.fFifoExtCommandWakeup = true;
4028	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4029	pThis->svga.u8FIFOExtCommand = uExtCmd;
4030	ASMMemoryFence(); /* paranoia^3 */
4031
4032	/* Resume the thread. */
4033	rc = PDMDevHlpThreadResume(pDevIns, pThread);
4034	AssertLogRelRC(rc);
4035	if (RT_SUCCESS(rc))
4036	{
4037	/* Wait. Take care in case the semaphore was already posted (same as below). */
4038	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4039	if ( rc == VINF_SUCCESS
4040	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4041	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4042	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4043	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4044
4045	/* suspend the thread */
4046	pThis->svga.fFifoExtCommandWakeup = false;
4047	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
4048	AssertLogRelRC(rc2);
4049	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
4050	rc = rc2;
4051	}
4052	pThis->svga.fFifoExtCommandWakeup = false;
4053	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4054	}
4055	else if (enmState == PDMTHREADSTATE_RUNNING)
4056	{
4057	/*
4058	* The thread is running, should only happen during reset and vmsvga3dsfc.
4059	* We ASSUME not racing code here, both wrt thread state and ext commands.
4060	*/
4061	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
4062	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_POWEROFF);
4063
4064	/* Post the request. */
4065	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4066	pThis->svga.u8FIFOExtCommand = uExtCmd;
4067	ASMMemoryFence(); /* paranoia^2 */
4068	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4069	AssertLogRelRC(rc);
4070
4071	/* Wait. Take care in case the semaphore was already posted (same as above). */
4072	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4073	if ( rc == VINF_SUCCESS
4074	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4075	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
4076	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4077	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4078
4079	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4080	}
4081	else
4082	{
4083	/*
4084	* Something is wrong with the thread!
4085	*/
4086	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
4087	rc = VERR_INVALID_STATE;
4088	}
4089	return rc;
4090	}
4091
4092
4093	/**
4094	* Marks the FIFO non-busy, notifying any waiting EMTs.
4095	*
4096	* @param pDevIns The device instance.
4097	* @param pThis The shared VGA/VMSVGA instance data.
4098	* @param pThisCC The VGA/VMSVGA state for ring-3.
4099	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
4100	* @param offFifoMin The start byte offset of the command FIFO.
4101	*/
4102	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
4103	{
4104	ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO \| VMSVGA_BUSY_F_EMT_FORCE));
4105	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4106	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
4107
4108	/* Wake up any waiting EMTs. */
4109	if (pSVGAState->cBusyDelayedEmts > 0)
4110	{
4111	# ifdef VMSVGA_USE_EMT_HALT_CODE
4112	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
4113	if (idCpu != NIL_VMCPUID)
4114	{
4115	PDMDevHlpVMNotifyCpuDeviceReady(pDevIns, idCpu);
4116	while (idCpu-- > 0)
4117	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
4118	PDMDevHlpVMNotifyCpuDeviceReady(pDevIns, idCpu);
4119	}
4120	# else
4121	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
4122	AssertRC(rc2);
4123	# endif
4124	}
4125	}
4126
4127	/**
4128	* Reads (more) payload into the command buffer.
4129	*
4130	* @returns pbBounceBuf on success
4131	* @retval (void *)1 if the thread was requested to stop.
4132	* @retval NULL on FIFO error.
4133	*
4134	* @param cbPayloadReq The number of bytes of payload requested.
4135	* @param pFIFO The FIFO.
4136	* @param offCurrentCmd The FIFO byte offset of the current command.
4137	* @param offFifoMin The start byte offset of the command FIFO.
4138	* @param offFifoMax The end byte offset of the command FIFO.
4139	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
4140	* always sufficient size.
4141	* @param pcbAlreadyRead How much payload we've already read into the bounce
4142	* buffer. (We will NEVER re-read anything.)
4143	* @param pThread The calling PDM thread handle.
4144	* @param pThis The shared VGA/VMSVGA instance data.
4145	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
4146	* statistics collection.
4147	* @param pDevIns The device instance.
4148	*/
4149	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
4150	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
4151	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
4152	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
4153	{
4154	Assert(pbBounceBuf);
4155	Assert(pcbAlreadyRead);
4156	Assert(offFifoMin < offFifoMax);
4157	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
4158	Assert(offFifoMax <= pThis->svga.cbFIFO);
4159
4160	/*
4161	* Check if the requested payload size has already been satisfied .
4162	* .
4163	* When called to read more, the caller is responsible for making sure the .
4164	* new command size (cbRequsted) never is smaller than what has already .
4165	* been read.
4166	*/
4167	uint32_t cbAlreadyRead = *pcbAlreadyRead;
4168	if (cbPayloadReq <= cbAlreadyRead)
4169	{
4170	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
4171	return pbBounceBuf;
4172	}
4173
4174	/*
4175	* Commands bigger than the fifo buffer are invalid.
4176	*/
4177	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
4178	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
4179	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
4180	NULL);
4181
4182	/*
4183	* Move offCurrentCmd past the command dword.
4184	*/
4185	offCurrentCmd += sizeof(uint32_t);
4186	if (offCurrentCmd >= offFifoMax)
4187	offCurrentCmd = offFifoMin;
4188
4189	/*
4190	* Do we have sufficient payload data available already?
4191	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
4192	*/
4193	uint32_t cbAfter, cbBefore;
4194	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4195	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4196	if (offNextCmd >= offCurrentCmd)
4197	{
4198	if (RT_LIKELY(offNextCmd < offFifoMax))
4199	cbAfter = offNextCmd - offCurrentCmd;
4200	else
4201	{
4202	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4203	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4204	offNextCmd, offFifoMin, offFifoMax));
4205	cbAfter = offFifoMax - offCurrentCmd;
4206	}
4207	cbBefore = 0;
4208	}
4209	else
4210	{
4211	cbAfter = offFifoMax - offCurrentCmd;
4212	if (offNextCmd >= offFifoMin)
4213	cbBefore = offNextCmd - offFifoMin;
4214	else
4215	{
4216	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4217	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4218	offNextCmd, offFifoMin, offFifoMax));
4219	cbBefore = 0;
4220	}
4221	}
4222	if (cbAfter + cbBefore < cbPayloadReq)
4223	{
4224	/*
4225	* Insufficient, must wait for it to arrive.
4226	*/
4227	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
4228	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
4229	for (uint32_t i = 0;; i++)
4230	{
4231	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4232	{
4233	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4234	return (void *)(uintptr_t)1;
4235	}
4236	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
4237	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
4238
4239	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
4240
4241	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4242	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4243	if (offNextCmd >= offCurrentCmd)
4244	{
4245	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
4246	cbBefore = 0;
4247	}
4248	else
4249	{
4250	cbAfter = offFifoMax - offCurrentCmd;
4251	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
4252	}
4253
4254	if (cbAfter + cbBefore >= cbPayloadReq)
4255	break;
4256	}
4257	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4258	}
4259
4260	/*
4261	* Copy out the memory and update what pcbAlreadyRead points to.
4262	*/
4263	if (cbAfter >= cbPayloadReq)
4264	memcpy(pbBounceBuf + cbAlreadyRead,
4265	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4266	cbPayloadReq - cbAlreadyRead);
4267	else
4268	{
4269	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
4270	if (cbAlreadyRead < cbAfter)
4271	{
4272	memcpy(pbBounceBuf + cbAlreadyRead,
4273	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4274	cbAfter - cbAlreadyRead);
4275	cbAlreadyRead = cbAfter;
4276	}
4277	memcpy(pbBounceBuf + cbAlreadyRead,
4278	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
4279	cbPayloadReq - cbAlreadyRead);
4280	}
4281	*pcbAlreadyRead = cbPayloadReq;
4282	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4283	return pbBounceBuf;
4284	}
4285
4286
4287	/**
4288	* Sends cursor position and visibility information from the FIFO to the front-end.
4289	* @returns SVGA_FIFO_CURSOR_COUNT value used.
4290	*/
4291	static uint32_t
4292	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
4293	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
4294	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
4295	{
4296	/*
4297	* Check if the cursor update counter has changed and try get a stable
4298	* set of values if it has. This is race-prone, especially consindering
4299	* the screen ID, but little we can do about that.
4300	*/
4301	uint32_t x, y, fVisible, idScreen;
4302	for (uint32_t i = 0; ; i++)
4303	{
4304	x = pFIFO[SVGA_FIFO_CURSOR_X];
4305	y = pFIFO[SVGA_FIFO_CURSOR_Y];
4306	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
4307	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
4308	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
4309	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
4310	\|\| i > 3)
4311	break;
4312	if (i == 0)
4313	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
4314	ASMNopPause();
4315	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4316	}
4317
4318	/*
4319	* Check if anything has changed, as calling into pDrv is not light-weight.
4320	*/
4321	if ( *pxLast == x
4322	&& *pyLast == y
4323	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
4324	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
4325	else
4326	{
4327	/*
4328	* Detected changes.
4329	*
4330	* We handle global, not per-screen visibility information by sending
4331	* pfnVBVAMousePointerShape without shape data.
4332	*/
4333	*pxLast = x;
4334	*pyLast = y;
4335	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
4336	if (idScreen != SVGA_ID_INVALID)
4337	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
4338	else if (*pfLastVisible != fVisible)
4339	{
4340	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
4341	*pfLastVisible = fVisible;
4342	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
4343	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
4344	}
4345	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
4346	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
4347	}
4348
4349	/*
4350	* Update done. Signal this to the guest.
4351	*/
4352	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
4353
4354	return uCursorUpdateCount;
4355	}
4356
4357
4358	/**
4359	* Checks if there is work to be done, either cursor updating or FIFO commands.
4360	*
4361	* @returns true if pending work, false if not.
4362	* @param pThisCC The VGA/VMSVGA state for ring-3.
4363	* @param uLastCursorCount The last cursor update counter value.
4364	*/
4365	DECLINLINE(bool) vmsvgaR3FifoHasWork(PVGASTATECC pThisCC, uint32_t uLastCursorCount)
4366	{
4367	/* If FIFO does not exist than there is nothing to do. Command buffers also require the enabled FIFO. */
4368	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4369	AssertReturn(pFIFO, false);
4370
4371	if (vmsvgaR3CmdBufHasWork(pThisCC))
4372	return true;
4373
4374	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
4375	return true;
4376
4377	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
4378	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
4379	return true;
4380
4381	return false;
4382	}
4383
4384
4385	/**
4386	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
4387	*
4388	* @param pDevIns The device instance.
4389	* @param pThis The shared VGA/VMSVGA instance data.
4390	* @param pThisCC The VGA/VMSVGA state for ring-3.
4391	*/
4392	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4393	{
4394	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
4395	to recheck it before doing the signalling. */
4396	if ( vmsvgaR3FifoHasWork(pThisCC, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
4397	&& pThis->svga.fFIFOThreadSleeping
4398	&& !ASMAtomicReadBool(&pThis->svga.fBadGuest))
4399	{
4400	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4401	AssertRC(rc);
4402	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
4403	}
4404	}
4405
4406
4407	/**
4408	* Called by the FIFO thread to process pending actions.
4409	*
4410	* @param pDevIns The device instance.
4411	* @param pThis The shared VGA/VMSVGA instance data.
4412	* @param pThisCC The VGA/VMSVGA state for ring-3.
4413	*/
4414	void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4415	{
4416	RT_NOREF(pDevIns);
4417
4418	/* Currently just mode changes. */
4419	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
4420	{
4421	vmsvgaR3ChangeMode(pThis, pThisCC);
4422	# ifdef VBOX_WITH_VMSVGA3D
4423	if (pThisCC->svga.p3dState != NULL)
4424	vmsvga3dChangeMode(pThisCC);
4425	# endif
4426	}
4427	}
4428
4429
4430	/*
4431	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
4432	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
4433	*/
4434	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4435	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
4436	*
4437	* Will break out of the switch on failure.
4438	* Will restart and quit the loop if the thread was requested to stop.
4439	*
4440	* @param a_PtrVar Request variable pointer.
4441	* @param a_Type Request typedef (not pointer) for casting.
4442	* @param a_cbPayloadReq How much payload to fetch.
4443	* @remarks Accesses a bunch of variables in the current scope!
4444	*/
4445	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4446	if (1) { \
4447	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
4448	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
4449	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
4450	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
4451	} else do {} while (0)
4452	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4453	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
4454	* buffer after figuring out the actual command size.
4455	*
4456	* Will break out of the switch on failure.
4457	*
4458	* @param a_PtrVar Request variable pointer.
4459	* @param a_Type Request typedef (not pointer) for casting.
4460	* @param a_cbPayloadReq How much payload to fetch.
4461	* @remarks Accesses a bunch of variables in the current scope!
4462	*/
4463	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4464	if (1) { \
4465	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
4466	} else do {} while (0)
4467
4468	/**
4469	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
4470	*/
4471	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4472	{
4473	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4474	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4475	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4476	int rc;
4477
4478	# if defined(VBOX_WITH_VMSVGA3D) && defined(RT_OS_LINUX)
4479	if (pThis->svga.f3DEnabled)
4480	{
4481	/* The FIFO thread may use X API for accelerated screen output. */
4482	XInitThreads();
4483	}
4484	# endif
4485
4486	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4487	return VINF_SUCCESS;
4488
4489	/*
4490	* Special mode where we only execute an external command and the go back
4491	* to being suspended. Currently, all ext cmds ends up here, with the reset
4492	* one also being eligble for runtime execution further down as well.
4493	*/
4494	if (pThis->svga.fFifoExtCommandWakeup)
4495	{
4496	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4497	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4498	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
4499	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
4500	else
4501	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4502	return VINF_SUCCESS;
4503	}
4504
4505
4506	/*
4507	* Signal the semaphore to make sure we don't wait for 250ms after a
4508	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
4509	*/
4510	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4511
4512	/*
4513	* Allocate a bounce buffer for command we get from the FIFO.
4514	* (All code must return via the end of the function to free this buffer.)
4515	*/
4516	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
4517	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
4518
4519	/*
4520	* Polling/sleep interval config.
4521	*
4522	* We wait for an a short interval if the guest has recently given us work
4523	* to do, but the interval increases the longer we're kept idle. Once we've
4524	* reached the refresh timer interval, we'll switch to extended waits,
4525	* depending on it or the guest to kick us into action when needed.
4526	*
4527	* Should the refresh time go fishing, we'll just continue increasing the
4528	* sleep length till we reaches the 250 ms max after about 16 seconds.
4529	*/
4530	RTMSINTERVAL const cMsMinSleep = 16;
4531	RTMSINTERVAL const cMsIncSleep = 2;
4532	RTMSINTERVAL const cMsMaxSleep = 250;
4533	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
4534	RTMSINTERVAL cMsSleep = cMsMaxSleep;
4535
4536	/*
4537	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
4538	*
4539	* Initialize with values that will detect an update from the guest.
4540	* Make sure that if the guest never updates the cursor position, then the device does not report it.
4541	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
4542	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
4543	*/
4544	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4545	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4546	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
4547	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
4548	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
4549
4550	/*
4551	* The FIFO loop.
4552	*/
4553	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
4554	bool fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4555	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4556	{
4557	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
4558	/*
4559	* Should service the run loop every so often.
4560	*/
4561	if (pThis->svga.f3DEnabled)
4562	vmsvga3dCocoaServiceRunLoop();
4563	# endif
4564
4565	/* First check any pending actions. */
4566	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4567
4568	/*
4569	* Unless there's already work pending, go to sleep for a short while.
4570	* (See polling/sleep interval config above.)
4571	*/
4572	if ( fBadOrDisabledFifo
4573	\|\| !vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4574	{
4575	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
4576	Assert(pThis->cMilliesRefreshInterval > 0);
4577	if (cMsSleep < pThis->cMilliesRefreshInterval)
4578	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
4579	else
4580	{
4581	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
4582	int rc2 = PDMDevHlpPGMHandlerPhysicalReset(pDevIns, pThis->svga.GCPhysFIFO);
4583	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
4584	# endif
4585	if ( !fBadOrDisabledFifo
4586	&& vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4587	rc = VINF_SUCCESS;
4588	else
4589	{
4590	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
4591	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
4592	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
4593	}
4594	}
4595	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
4596	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
4597	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4598	{
4599	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
4600	break;
4601	}
4602	}
4603	else
4604	rc = VINF_SUCCESS;
4605	fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4606	if (rc == VERR_TIMEOUT)
4607	{
4608	if (!vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4609	{
4610	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
4611	continue;
4612	}
4613	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
4614
4615	Log(("vmsvgaR3FifoLoop: timeout\n"));
4616	}
4617	else if (vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4618	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
4619	cMsSleep = cMsMinSleep;
4620
4621	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
4622	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
4623	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
4624
4625	/*
4626	* Handle external commands (currently only reset).
4627	*/
4628	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4629	{
4630	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4631	continue;
4632	}
4633
4634	/*
4635	* If guest misbehaves, then do nothing.
4636	*/
4637	if (ASMAtomicReadBool(&pThis->svga.fBadGuest))
4638	{
4639	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4640	cMsSleep = cMsExtendedSleep;
4641	LogRelMax(1, ("VMSVGA: FIFO processing stopped because of the guest misbehavior\n"));
4642	continue;
4643	}
4644
4645	/*
4646	* The device must be enabled and configured.
4647	*/
4648	if ( !pThis->svga.fEnabled
4649	\|\| !pThis->svga.fConfigured)
4650	{
4651	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4652	fBadOrDisabledFifo = true;
4653	cMsSleep = cMsMaxSleep; /* cheat */
4654	continue;
4655	}
4656
4657	/*
4658	* Get and check the min/max values. We ASSUME that they will remain
4659	* unchanged while we process requests. A further ASSUMPTION is that
4660	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
4661	* we don't read it back while in the loop.
4662	*/
4663	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
4664	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
4665	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
4666	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4667	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
4668	\|\| offFifoMax <= offFifoMin
4669	\|\| offFifoMax > pThis->svga.cbFIFO
4670	\|\| (offFifoMax & 3) != 0
4671	\|\| (offFifoMin & 3) != 0
4672	\|\| offCurrentCmd < offFifoMin
4673	\|\| offCurrentCmd > offFifoMax))
4674	{
4675	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4676	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
4677	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4678	fBadOrDisabledFifo = true;
4679	continue;
4680	}
4681	RT_UNTRUSTED_VALIDATED_FENCE();
4682	if (RT_UNLIKELY(offCurrentCmd & 3))
4683	{
4684	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4685	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
4686	offCurrentCmd &= ~UINT32_C(3);
4687	}
4688
4689	/*
4690	* Update the cursor position before we start on the FIFO commands.
4691	*/
4692	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
4693	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
4694	{
4695	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4696	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
4697	{ /* halfways likely */ }
4698	else
4699	{
4700	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
4701	&xLastCursor, &yLastCursor, &fLastCursorVisible);
4702	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
4703	}
4704	}
4705
4706	/*
4707	* Mark the FIFO as busy.
4708	*/
4709	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
4710	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4711	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
4712
4713	/*
4714	* Process all submitted command buffers.
4715	*/
4716	vmsvgaR3CmdBufProcessBuffers(pDevIns, pThis, pThisCC, pThread);
4717
4718	/*
4719	* Execute all queued FIFO commands.
4720	* Quit if pending external command or changes in the thread state.
4721	*/
4722	bool fDone = false;
4723	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
4724	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
4725	{
4726	uint32_t cbPayload = 0;
4727	uint32_t u32IrqStatus = 0;
4728
4729	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
4730
4731	/* First check any pending actions. */
4732	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4733
4734	/* Check for pending external commands (reset). */
4735	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4736	break;
4737
4738	/*
4739	* Process the command.
4740	*/
4741	/* 'enmCmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
4742	* warning. Because we implement some obsolete and deprecated commands, which are not included in
4743	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
4744	*/
4745	uint32_t const enmCmdId = pFIFO[offCurrentCmd / sizeof(uint32_t)];
4746	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4747	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s %d\n",
4748	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
4749	switch (enmCmdId)
4750	{
4751	case SVGA_CMD_INVALID_CMD:
4752	/* Nothing to do. */
4753	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
4754	break;
4755
4756	case SVGA_CMD_FENCE:
4757	{
4758	SVGAFifoCmdFence *pCmdFence;
4759	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
4760	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
4761	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
4762	{
4763	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %#x\n", pCmdFence->fence));
4764	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
4765
4766	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
4767	{
4768	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
4769	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
4770	}
4771	else
4772	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
4773	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
4774	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
4775	{
4776	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%#x)\n", pCmdFence->fence));
4777	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
4778	}
4779	}
4780	else
4781	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
4782	break;
4783	}
4784
4785	case SVGA_CMD_UPDATE:
4786	{
4787	SVGAFifoCmdUpdate *pCmd;
4788	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdate, sizeof(*pCmd));
4789	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
4790	break;
4791	}
4792
4793	case SVGA_CMD_UPDATE_VERBOSE:
4794	{
4795	SVGAFifoCmdUpdateVerbose *pCmd;
4796	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdateVerbose, sizeof(*pCmd));
4797	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
4798	break;
4799	}
4800
4801	case SVGA_CMD_DEFINE_CURSOR:
4802	{
4803	/* Followed by bitmap data. */
4804	SVGAFifoCmdDefineCursor *pCmd;
4805	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, sizeof(*pCmd));
4806
4807	/* Figure out the size of the bitmap data. */
4808	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4809	ASSERT_GUEST_BREAK(pCmd->andMaskDepth <= 32);
4810	ASSERT_GUEST_BREAK(pCmd->xorMaskDepth <= 32);
4811	RT_UNTRUSTED_VALIDATED_FENCE();
4812
4813	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
4814	uint32_t const cbAndMask = cbAndLine * pCmd->height;
4815	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
4816	uint32_t const cbXorMask = cbXorLine * pCmd->height;
4817
4818	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineCursor) + cbAndMask + cbXorMask;
4819	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, cbCmd);
4820	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
4821	break;
4822	}
4823
4824	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
4825	{
4826	/* Followed by bitmap data. */
4827	SVGAFifoCmdDefineAlphaCursor *pCmd;
4828	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCmd));
4829
4830	/* Figure out the size of the bitmap data. */
4831	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4832
4833	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCmd->width * pCmd->height * sizeof(uint32_t) /* 32-bit BRGA format */;
4834	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, cbCmd);
4835	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
4836	break;
4837	}
4838
4839	case SVGA_CMD_MOVE_CURSOR:
4840	{
4841	/* Deprecated; there should be no driver which requires this command. However, if
4842	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4843	* alignment.
4844	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4845	*/
4846	SVGAFifoCmdMoveCursor *pCmd;
4847	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdMoveCursor, sizeof(*pCmd));
4848	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
4849	break;
4850	}
4851
4852	case SVGA_CMD_DISPLAY_CURSOR:
4853	{
4854	/* Deprecated; there should be no driver which requires this command. However, if
4855	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4856	* alignment.
4857	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4858	*/
4859	SVGAFifoCmdDisplayCursor *pCmd;
4860	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDisplayCursor, sizeof(*pCmd));
4861	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
4862	break;
4863	}
4864
4865	case SVGA_CMD_RECT_FILL:
4866	{
4867	SVGAFifoCmdRectFill *pCmd;
4868	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectFill, sizeof(*pCmd));
4869	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
4870	break;
4871	}
4872
4873	case SVGA_CMD_RECT_COPY:
4874	{
4875	SVGAFifoCmdRectCopy *pCmd;
4876	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectCopy, sizeof(*pCmd));
4877	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
4878	break;
4879	}
4880
4881	case SVGA_CMD_RECT_ROP_COPY:
4882	{
4883	SVGAFifoCmdRectRopCopy *pCmd;
4884	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectRopCopy, sizeof(*pCmd));
4885	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
4886	break;
4887	}
4888
4889	case SVGA_CMD_ESCAPE:
4890	{
4891	/* Followed by 'size' bytes of data. */
4892	SVGAFifoCmdEscape *pCmd;
4893	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, sizeof(*pCmd));
4894
4895	ASSERT_GUEST_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape));
4896	RT_UNTRUSTED_VALIDATED_FENCE();
4897
4898	uint32_t const cbCmd = sizeof(SVGAFifoCmdEscape) + pCmd->size;
4899	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, cbCmd);
4900	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
4901	break;
4902	}
4903	# ifdef VBOX_WITH_VMSVGA3D
4904	case SVGA_CMD_DEFINE_GMR2:
4905	{
4906	SVGAFifoCmdDefineGMR2 *pCmd;
4907	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
4908	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
4909	break;
4910	}
4911
4912	case SVGA_CMD_REMAP_GMR2:
4913	{
4914	/* Followed by page descriptors or guest ptr. */
4915	SVGAFifoCmdRemapGMR2 *pCmd;
4916	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
4917
4918	/* Calculate the size of what comes after next and fetch it. */
4919	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
4920	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4921	cbCmd += sizeof(SVGAGuestPtr);
4922	else
4923	{
4924	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
4925	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
4926	{
4927	cbCmd += cbPageDesc;
4928	pCmd->numPages = 1;
4929	}
4930	else
4931	{
4932	ASSERT_GUEST_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
4933	cbCmd += cbPageDesc * pCmd->numPages;
4934	}
4935	}
4936	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
4937	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
4938	# ifdef DEBUG_GMR_ACCESS
4939	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4940	# endif
4941	break;
4942	}
4943	# endif // VBOX_WITH_VMSVGA3D
4944	case SVGA_CMD_DEFINE_SCREEN:
4945	{
4946	/* The size of this command is specified by the guest and depends on capabilities. */
4947	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4948
4949	SVGAFifoCmdDefineScreen *pCmd;
4950	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4951	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4952	RT_UNTRUSTED_VALIDATED_FENCE();
4953
4954	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4955	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4956	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
4957	break;
4958	}
4959
4960	case SVGA_CMD_DESTROY_SCREEN:
4961	{
4962	SVGAFifoCmdDestroyScreen *pCmd;
4963	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4964	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
4965	break;
4966	}
4967
4968	case SVGA_CMD_DEFINE_GMRFB:
4969	{
4970	SVGAFifoCmdDefineGMRFB *pCmd;
4971	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4972	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
4973	break;
4974	}
4975
4976	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4977	{
4978	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4979	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4980	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
4981	break;
4982	}
4983
4984	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4985	{
4986	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4987	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4988	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
4989	break;
4990	}
4991
4992	case SVGA_CMD_ANNOTATION_FILL:
4993	{
4994	SVGAFifoCmdAnnotationFill *pCmd;
4995	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4996	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
4997	break;
4998	}
4999
5000	case SVGA_CMD_ANNOTATION_COPY:
5001	{
5002	SVGAFifoCmdAnnotationCopy *pCmd;
5003	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
5004	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
5005	break;
5006	}
5007
5008	default:
5009	# ifdef VBOX_WITH_VMSVGA3D
5010	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
5011	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
5012	{
5013	RT_UNTRUSTED_VALIDATED_FENCE();
5014
5015	/* All 3d commands start with a common header, which defines the identifier and the size
5016	* of the command. The identifier has been already read from FIFO. Fetch the size.
5017	*/
5018	uint32_t *pcbCmd;
5019	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pcbCmd, uint32_t, sizeof(*pcbCmd));
5020	uint32_t const cbCmd = *pcbCmd;
5021	AssertBreak(cbCmd < pThis->svga.cbFIFO);
5022	uint32_t *pu32Cmd;
5023	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pu32Cmd, uint32_t, sizeof(*pcbCmd) + cbCmd);
5024	pu32Cmd++; /* Skip the command size. */
5025
5026	if (RT_LIKELY(pThis->svga.f3DEnabled))
5027	{ /* likely */ }
5028	else
5029	{
5030	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", enmCmdId));
5031	break;
5032	}
5033
5034	vmsvgaR3Process3dCmd(pThis, pThisCC, SVGA3D_INVALID_ID, (SVGAFifo3dCmdId)enmCmdId, cbCmd, pu32Cmd);
5035	}
5036	else
5037	# endif // VBOX_WITH_VMSVGA3D
5038	{
5039	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
5040	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
5041	LogRelMax(16, ("VMSVGA: unsupported command %d\n", enmCmdId));
5042	}
5043	}
5044
5045	/* Go to the next slot */
5046	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
5047	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
5048	if (offCurrentCmd >= offFifoMax)
5049	{
5050	offCurrentCmd -= offFifoMax - offFifoMin;
5051	Assert(offCurrentCmd >= offFifoMin);
5052	Assert(offCurrentCmd < offFifoMax);
5053	}
5054	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
5055	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
5056
5057	/*
5058	* Raise IRQ if required. Must enter the critical section here
5059	* before making final decisions here, otherwise cubebench and
5060	* others may end up waiting forever.
5061	*/
5062	if ( u32IrqStatus
5063	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
5064	{
5065	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
5066	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
5067
5068	/* FIFO progress might trigger an interrupt. */
5069	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
5070	{
5071	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
5072	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
5073	}
5074
5075	/* Unmasked IRQ pending? */
5076	if (pThis->svga.u32IrqMask & u32IrqStatus)
5077	{
5078	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
5079	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
5080	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
5081	}
5082
5083	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5084	}
5085	}
5086
5087	/* If really done, clear the busy flag. */
5088	if (fDone)
5089	{
5090	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
5091	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
5092	}
5093	}
5094
5095	/*
5096	* Free the bounce buffer. (There are no returns above!)
5097	*/
5098	RTMemFree(pbBounceBuf);
5099
5100	return VINF_SUCCESS;
5101	}
5102
5103	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
5104	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
5105
5106	/**
5107	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5108	* Unblock the FIFO I/O thread so it can respond to a state change.}
5109	*/
5110	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5111	{
5112	RT_NOREF(pDevIns);
5113	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5114	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5115	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5116	}
5117
5118	/**
5119	* Enables or disables dirty page tracking for the framebuffer
5120	*
5121	* @param pDevIns The device instance.
5122	* @param pThis The shared VGA/VMSVGA instance data.
5123	* @param fTraces Enable/disable traces
5124	*/
5125	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5126	{
5127	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5128	&& !fTraces)
5129	{
5130	//Assert(pThis->svga.fTraces);
5131	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5132	return;
5133	}
5134
5135	pThis->svga.fTraces = fTraces;
5136	if (pThis->svga.fTraces)
5137	{
5138	unsigned cbFrameBuffer = pThis->vram_size;
5139
5140	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5141	/** @todo How does this work with screens? */
5142	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5143	{
5144	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5145	Assert(pThis->svga.cbScanline);
5146	# endif
5147	/* Hardware enabled; return real framebuffer size .*/
5148	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5149	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5150	}
5151
5152	if (!pThis->svga.fVRAMTracking)
5153	{
5154	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5155	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5156	pThis->svga.fVRAMTracking = true;
5157	}
5158	}
5159	else
5160	{
5161	if (pThis->svga.fVRAMTracking)
5162	{
5163	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5164	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5165	pThis->svga.fVRAMTracking = false;
5166	}
5167	}
5168	}
5169
5170	/**
5171	* @callback_method_impl{FNPCIIOREGIONMAP}
5172	*/
5173	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5174	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5175	{
5176	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5177	int rc;
5178	RT_NOREF(pPciDev);
5179	Assert(pPciDev == pDevIns->apPciDevs[0]);
5180
5181	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5182	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5183	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5184	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5185	, VERR_INTERNAL_ERROR);
5186	if (GCPhysAddress != NIL_RTGCPHYS)
5187	{
5188	/*
5189	* Mapping the FIFO RAM.
5190	*/
5191	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5192	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5193	AssertRC(rc);
5194
5195	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5196	if (RT_SUCCESS(rc))
5197	{
5198	rc = PDMDevHlpPGMHandlerPhysicalRegister(pDevIns, GCPhysAddress,
5199	# ifdef DEBUG_FIFO_ACCESS
5200	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5201	# else
5202	GCPhysAddress + PAGE_SIZE - 1,
5203	# endif
5204	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5205	"VMSVGA FIFO");
5206	AssertRC(rc);
5207	}
5208	# endif
5209	if (RT_SUCCESS(rc))
5210	{
5211	pThis->svga.GCPhysFIFO = GCPhysAddress;
5212	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5213	}
5214	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite errors here. */
5215	}
5216	else
5217	{
5218	Assert(pThis->svga.GCPhysFIFO);
5219	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5220	rc = PDMDevHlpPGMHandlerPhysicalDeregister(pDevIns, pThis->svga.GCPhysFIFO);
5221	AssertRC(rc);
5222	# else
5223	rc = VINF_SUCCESS;
5224	# endif
5225	pThis->svga.GCPhysFIFO = 0;
5226	}
5227	return rc;
5228	}
5229
5230	# ifdef VBOX_WITH_VMSVGA3D
5231
5232	/**
5233	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5234	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5235	*
5236	* @param pDevIns The device instance.
5237	* @param pThis The The shared VGA/VMSVGA instance data.
5238	* @param pThisCC The VGA/VMSVGA state for ring-3.
5239	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5240	* UINT32_MAX is used, all surfaces are processed.
5241	*/
5242	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5243	{
5244	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5245	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5246	}
5247
5248
5249	/**
5250	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5251	*/
5252	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5253	{
5254	/* There might be a specific surface ID at the start of the
5255	arguments, if not show all surfaces. */
5256	uint32_t sid = UINT32_MAX;
5257	if (pszArgs)
5258	pszArgs = RTStrStripL(pszArgs);
5259	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5260	sid = RTStrToUInt32(pszArgs);
5261
5262	/* Verbose or terse display, we default to verbose. */
5263	bool fVerbose = true;
5264	if (RTStrIStr(pszArgs, "terse"))
5265	fVerbose = false;
5266
5267	/* The size of the ascii art (x direction, y is 3/4 of x). */
5268	uint32_t cxAscii = 80;
5269	if (RTStrIStr(pszArgs, "gigantic"))
5270	cxAscii = 300;
5271	else if (RTStrIStr(pszArgs, "huge"))
5272	cxAscii = 180;
5273	else if (RTStrIStr(pszArgs, "big"))
5274	cxAscii = 132;
5275	else if (RTStrIStr(pszArgs, "normal"))
5276	cxAscii = 80;
5277	else if (RTStrIStr(pszArgs, "medium"))
5278	cxAscii = 64;
5279	else if (RTStrIStr(pszArgs, "small"))
5280	cxAscii = 48;
5281	else if (RTStrIStr(pszArgs, "tiny"))
5282	cxAscii = 24;
5283
5284	/* Y invert the image when producing the ASCII art. */
5285	bool fInvY = false;
5286	if (RTStrIStr(pszArgs, "invy"))
5287	fInvY = true;
5288
5289	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5290	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5291	}
5292
5293
5294	/**
5295	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5296	*/
5297	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5298	{
5299	/* pszArg = "sid[>dir]"
5300	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5301	*/
5302	char *pszBitmapPath = NULL;
5303	uint32_t sid = UINT32_MAX;
5304	if (pszArgs)
5305	pszArgs = RTStrStripL(pszArgs);
5306	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5307	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5308	if ( pszBitmapPath
5309	&& *pszBitmapPath == '>')
5310	++pszBitmapPath;
5311
5312	const bool fVerbose = true;
5313	const uint32_t cxAscii = 0; /* No ASCII */
5314	const bool fInvY = false; /* Do not invert. */
5315	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5316	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5317	}
5318
5319	/**
5320	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5321	*/
5322	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5323	{
5324	/* There might be a specific surface ID at the start of the
5325	arguments, if not show all contexts. */
5326	uint32_t sid = UINT32_MAX;
5327	if (pszArgs)
5328	pszArgs = RTStrStripL(pszArgs);
5329	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5330	sid = RTStrToUInt32(pszArgs);
5331
5332	/* Verbose or terse display, we default to verbose. */
5333	bool fVerbose = true;
5334	if (RTStrIStr(pszArgs, "terse"))
5335	fVerbose = false;
5336
5337	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5338	}
5339	# endif /* VBOX_WITH_VMSVGA3D */
5340
5341	/**
5342	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5343	*/
5344	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5345	{
5346	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5347	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5348	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5349	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5350	RT_NOREF(pszArgs);
5351
5352	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5353	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5354	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5355	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5356	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5357	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5358	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5359	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5360	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5361	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5362	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5363	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5364	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5365	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5366	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5367	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5368	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5369	pHlp->pfnPrintf(pHlp, "Device Capabilites: %#x\n", pThis->svga.u32DeviceCaps);
5370	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5371	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5372	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5373	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5374	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5375	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5376	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5377
5378	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5379	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5380	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5381	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5382
5383	pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
5384	pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
5385
5386	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
5387	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
5388
5389	# ifdef VBOX_WITH_VMSVGA3D
5390	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5391	# endif
5392	if (pThisCC->pDrv)
5393	{
5394	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5395	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5396	}
5397
5398	/* Dump screen information. */
5399	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5400	{
5401	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5402	if (pScreen)
5403	{
5404	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5405	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5406	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5407	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5408	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5409	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5410	{
5411	pHlp->pfnPrintf(pHlp, " (");
5412	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5413	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5414	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5415	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5416	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5417	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5418	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5419	pHlp->pfnPrintf(pHlp, " BLANKING");
5420	pHlp->pfnPrintf(pHlp, " )");
5421	}
5422	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5423	}
5424	}
5425
5426	}
5427
5428	/**
5429	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5430	*/
5431	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5432	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5433	{
5434	RT_NOREF(uPass);
5435
5436	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5437	int rc;
5438
5439	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5440	{
5441	uint32_t cScreens = 0;
5442	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5443	AssertRCReturn(rc, rc);
5444	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5445	("cScreens=%#x\n", cScreens),
5446	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5447
5448	for (uint32_t i = 0; i < cScreens; ++i)
5449	{
5450	VMSVGASCREENOBJECT screen;
5451	RT_ZERO(screen);
5452
5453	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5454	AssertLogRelRCReturn(rc, rc);
5455
5456	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5457	{
5458	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5459	*pScreen = screen;
5460	pScreen->fModified = true;
5461	}
5462	else
5463	{
5464	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5465	}
5466	}
5467	}
5468	else
5469	{
5470	/* Try to setup at least the first screen. */
5471	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5472	pScreen->fDefined = true;
5473	pScreen->fModified = true;
5474	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5475	pScreen->idScreen = 0;
5476	pScreen->xOrigin = 0;
5477	pScreen->yOrigin = 0;
5478	pScreen->offVRAM = pThis->svga.uScreenOffset;
5479	pScreen->cbPitch = pThis->svga.cbScanline;
5480	pScreen->cWidth = pThis->svga.uWidth;
5481	pScreen->cHeight = pThis->svga.uHeight;
5482	pScreen->cBpp = pThis->svga.uBpp;
5483	}
5484
5485	return VINF_SUCCESS;
5486	}
5487
5488	/**
5489	* @copydoc FNSSMDEVLOADEXEC
5490	*/
5491	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5492	{
5493	RT_NOREF(uPass);
5494	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5495	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5496	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5497	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5498	int rc;
5499
5500	/* Load our part of the VGAState */
5501	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5502	AssertRCReturn(rc, rc);
5503
5504	/* Load the VGA framebuffer. */
5505	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5506	uint32_t cbVgaFramebuffer = _32K;
5507	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5508	{
5509	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5510	AssertRCReturn(rc, rc);
5511	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5512	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5513	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5514	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5515	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5516	}
5517	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5518	AssertRCReturn(rc, rc);
5519	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5520	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5521	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5522	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5523
5524	/* Load the VMSVGA state. */
5525	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5526	AssertRCReturn(rc, rc);
5527
5528	/* Load the active cursor bitmaps. */
5529	if (pSVGAState->Cursor.fActive)
5530	{
5531	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5532	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5533
5534	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5535	AssertRCReturn(rc, rc);
5536	}
5537
5538	/* Load the GMR state. */
5539	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5540	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5541	{
5542	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5543	AssertRCReturn(rc, rc);
5544	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5545	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5546	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5547	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5548	}
5549
5550	if (pThis->svga.cGMR != cGMR)
5551	{
5552	/* Reallocate GMR array. */
5553	Assert(pSVGAState->paGMR != NULL);
5554	RTMemFree(pSVGAState->paGMR);
5555	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5556	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5557	pThis->svga.cGMR = cGMR;
5558	}
5559
5560	for (uint32_t i = 0; i < cGMR; ++i)
5561	{
5562	PGMR pGMR = &pSVGAState->paGMR[i];
5563
5564	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5565	AssertRCReturn(rc, rc);
5566
5567	if (pGMR->numDescriptors)
5568	{
5569	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5570	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5571	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5572
5573	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5574	{
5575	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5576	AssertRCReturn(rc, rc);
5577	}
5578	}
5579	}
5580
5581	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5582	if (pThis->svga.f3DEnabled)
5583	pSVGAState->pFuncs3D->pfnPowerOn(pDevIns, pThis, pThisCC);
5584	# endif
5585
5586	VMSVGA_STATE_LOAD LoadState;
5587	LoadState.pSSM = pSSM;
5588	LoadState.uVersion = uVersion;
5589	LoadState.uPass = uPass;
5590	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5591	AssertLogRelRCReturn(rc, rc);
5592
5593	return VINF_SUCCESS;
5594	}
5595
5596	/**
5597	* Reinit the video mode after the state has been loaded.
5598	*/
5599	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5600	{
5601	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5602	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5603	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5604
5605	/* VMSVGA is working via VBVA interface, therefore it needs to be
5606	* enabled on saved state restore. See @bugref{10071#c7}. */
5607	if (pThis->svga.fEnabled)
5608	{
5609	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
5610	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
5611	}
5612
5613	/* Set the active cursor. */
5614	if (pSVGAState->Cursor.fActive)
5615	{
5616	/* We don't store the alpha flag, but we can take a guess that if
5617	* the old register interface was used, the cursor was B&W.
5618	*/
5619	bool fAlpha = pThis->svga.uCursorOn ? false : true;
5620
5621	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
5622	true /fVisible/,
5623	fAlpha,
5624	pSVGAState->Cursor.xHotspot,
5625	pSVGAState->Cursor.yHotspot,
5626	pSVGAState->Cursor.width,
5627	pSVGAState->Cursor.height,
5628	pSVGAState->Cursor.pData);
5629	AssertRC(rc);
5630
5631	if (pThis->svga.uCursorOn)
5632	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
5633	}
5634
5635	/* If the VRAM handler should not be registered, we have to explicitly
5636	* unregister it here!
5637	*/
5638	if (!pThis->svga.fVRAMTracking)
5639	{
5640	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5641	}
5642
5643	/* Let the FIFO thread deal with changing the mode. */
5644	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5645
5646	return VINF_SUCCESS;
5647	}
5648
5649	/**
5650	* Portion of SVGA state which must be saved in the FIFO thread.
5651	*/
5652	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5653	{
5654	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5655	int rc;
5656
5657	/* Save the screen objects. */
5658	/* Count defined screen object. */
5659	uint32_t cScreens = 0;
5660	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5661	{
5662	if (pSVGAState->aScreens[i].fDefined)
5663	++cScreens;
5664	}
5665
5666	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5667	AssertLogRelRCReturn(rc, rc);
5668
5669	for (uint32_t i = 0; i < cScreens; ++i)
5670	{
5671	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5672
5673	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5674	AssertLogRelRCReturn(rc, rc);
5675	}
5676	return VINF_SUCCESS;
5677	}
5678
5679	/**
5680	* @copydoc FNSSMDEVSAVEEXEC
5681	*/
5682	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5683	{
5684	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5685	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5686	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5687	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5688	int rc;
5689
5690	/* Save our part of the VGAState */
5691	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5692	AssertLogRelRCReturn(rc, rc);
5693
5694	/* Save the framebuffer backup. */
5695	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5696	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5697	AssertLogRelRCReturn(rc, rc);
5698
5699	/* Save the VMSVGA state. */
5700	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5701	AssertLogRelRCReturn(rc, rc);
5702
5703	/* Save the active cursor bitmaps. */
5704	if (pSVGAState->Cursor.fActive)
5705	{
5706	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5707	AssertLogRelRCReturn(rc, rc);
5708	}
5709
5710	/* Save the GMR state */
5711	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5712	AssertLogRelRCReturn(rc, rc);
5713	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5714	{
5715	PGMR pGMR = &pSVGAState->paGMR[i];
5716
5717	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5718	AssertLogRelRCReturn(rc, rc);
5719
5720	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5721	{
5722	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5723	AssertLogRelRCReturn(rc, rc);
5724	}
5725	}
5726
5727	/*
5728	* Must save some state (3D in particular) in the FIFO thread.
5729	*/
5730	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5731	AssertLogRelRCReturn(rc, rc);
5732
5733	return VINF_SUCCESS;
5734	}
5735
5736	/**
5737	* Destructor for PVMSVGAR3STATE structure. The structure is not deallocated.
5738	*
5739	* @param pThis The shared VGA/VMSVGA instance data.
5740	* @param pThisCC The device context.
5741	*/
5742	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVGASTATECC pThisCC)
5743	{
5744	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5745
5746	# ifndef VMSVGA_USE_EMT_HALT_CODE
5747	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5748	{
5749	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5750	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5751	}
5752	# endif
5753
5754	if (pSVGAState->Cursor.fActive)
5755	{
5756	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5757	pSVGAState->Cursor.pData = NULL;
5758	pSVGAState->Cursor.fActive = false;
5759	}
5760
5761	if (pSVGAState->paGMR)
5762	{
5763	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5764	if (pSVGAState->paGMR[i].paDesc)
5765	RTMemFree(pSVGAState->paGMR[i].paDesc);
5766
5767	RTMemFree(pSVGAState->paGMR);
5768	pSVGAState->paGMR = NULL;
5769	}
5770
5771	if (RTCritSectIsInitialized(&pSVGAState->CritSectCmdBuf))
5772	{
5773	RTCritSectEnter(&pSVGAState->CritSectCmdBuf);
5774	for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->apCmdBufCtxs); ++i)
5775	{
5776	vmsvgaR3CmdBufCtxTerm(pSVGAState->apCmdBufCtxs[i]);
5777	pSVGAState->apCmdBufCtxs[i] = NULL;
5778	}
5779	vmsvgaR3CmdBufCtxTerm(&pSVGAState->CmdBufCtxDC);
5780	RTCritSectLeave(&pSVGAState->CritSectCmdBuf);
5781	RTCritSectDelete(&pSVGAState->CritSectCmdBuf);
5782	}
5783	}
5784
5785	/**
5786	* Constructor for PVMSVGAR3STATE structure.
5787	*
5788	* @returns VBox status code.
5789	* @param pDevIns The PDM device instance.
5790	* @param pThis The shared VGA/VMSVGA instance data.
5791	* @param pSVGAState Pointer to the structure. It is already allocated.
5792	*/
5793	static int vmsvgaR3StateInit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5794	{
5795	int rc = VINF_SUCCESS;
5796
5797	pSVGAState->pDevIns = pDevIns;
5798
5799	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5800	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5801
5802	# ifndef VMSVGA_USE_EMT_HALT_CODE
5803	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5804	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5805	AssertRCReturn(rc, rc);
5806	# endif
5807
5808	rc = RTCritSectInit(&pSVGAState->CritSectCmdBuf);
5809	AssertRCReturn(rc, rc);
5810
5811	vmsvgaR3CmdBufCtxInit(&pSVGAState->CmdBufCtxDC);
5812
5813	RTListInit(&pSVGAState->MOBLRUList);
5814	return rc;
5815	}
5816
5817	# ifdef VBOX_WITH_VMSVGA3D
5818	static void vmsvga3dR3Free3dInterfaces(PVGASTATECC pThisCC)
5819	{
5820	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5821
5822	RTMemFree(pSVGAState->pFuncsMap);
5823	pSVGAState->pFuncsMap = NULL;
5824	RTMemFree(pSVGAState->pFuncsGBO);
5825	pSVGAState->pFuncsGBO = NULL;
5826	RTMemFree(pSVGAState->pFuncsDX);
5827	pSVGAState->pFuncsDX = NULL;
5828	RTMemFree(pSVGAState->pFuncsVGPU9);
5829	pSVGAState->pFuncsVGPU9 = NULL;
5830	RTMemFree(pSVGAState->pFuncs3D);
5831	pSVGAState->pFuncs3D = NULL;
5832	}
5833
5834	/* This structure is used only by vmsvgaR3Init3dInterfaces */
5835	typedef struct VMSVGA3DINTERFACE
5836	{
5837	char const *pcszName;
5838	uint32_t cbFuncs;
5839	void **ppvFuncs;
5840	} VMSVGA3DINTERFACE;
5841
5842	extern VMSVGA3DBACKENDDESC const g_BackendLegacy;
5843	#if defined(VMSVGA3D_DX_BACKEND)
5844	extern VMSVGA3DBACKENDDESC const g_BackendDX;
5845	#endif
5846
5847	/**
5848	* Initializes the optional host 3D backend interfaces.
5849	*
5850	* @returns VBox status code.
5851	* @param pThisCC The VGA/VMSVGA state for ring-3.
5852	*/
5853	static int vmsvgaR3Init3dInterfaces(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
5854	{
5855	#ifndef VMSVGA3D_DX
5856	RT_NOREF(pThis);
5857	#endif
5858
5859	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5860
5861	#define ENTRY_3D_INTERFACE(a_Name, a_Field) { VMSVGA3D_BACKEND_INTERFACE_NAME_##a_Name, sizeof(VMSVGA3DBACKENDFUNCS##a_Name), (void **)&pSVGAState->a_Field }
5862	VMSVGA3DINTERFACE a3dInterface[] =
5863	{
5864	ENTRY_3D_INTERFACE(3D, pFuncs3D),
5865	ENTRY_3D_INTERFACE(VGPU9, pFuncsVGPU9),
5866	ENTRY_3D_INTERFACE(DX, pFuncsDX),
5867	ENTRY_3D_INTERFACE(MAP, pFuncsMap),
5868	ENTRY_3D_INTERFACE(GBO, pFuncsGBO),
5869	};
5870	#undef ENTRY_3D_INTERFACE
5871
5872	VMSVGA3DBACKENDDESC const *pBackend = NULL;
5873	#if defined(VMSVGA3D_DX_BACKEND)
5874	if (pThis->fVMSVGA10)
5875	pBackend = &g_BackendDX;
5876	else
5877	#endif
5878	pBackend = &g_BackendLegacy;
5879
5880	int rc = VINF_SUCCESS;
5881	for (uint32_t i = 0; i < RT_ELEMENTS(a3dInterface); ++i)
5882	{
5883	VMSVGA3DINTERFACE *p = &a3dInterface[i];
5884
5885	int rc2 = pBackend->pfnQueryInterface(pThisCC, p->pcszName, NULL, p->cbFuncs);
5886	if (RT_SUCCESS(rc2))
5887	{
5888	*p->ppvFuncs = RTMemAllocZ(p->cbFuncs);
5889	AssertBreakStmt(*p->ppvFuncs, rc = VERR_NO_MEMORY);
5890
5891	pBackend->pfnQueryInterface(pThisCC, p->pcszName, *p->ppvFuncs, p->cbFuncs);
5892	}
5893	}
5894
5895	if (RT_SUCCESS(rc))
5896	{
5897	/* 3D interface is required. */
5898	if (pSVGAState->pFuncs3D)
5899	{
5900	rc = pSVGAState->pFuncs3D->pfnInit(pDevIns, pThis, pThisCC);
5901	if (RT_SUCCESS(rc))
5902	return VINF_SUCCESS;
5903	}
5904	else
5905	rc = VERR_NOT_SUPPORTED;
5906	}
5907
5908	vmsvga3dR3Free3dInterfaces(pThisCC);
5909	return rc;
5910	}
5911	# endif /* VBOX_WITH_VMSVGA3D */
5912
5913	/**
5914	* Initializes the host capabilities: device and FIFO.
5915	*
5916	* @returns VBox status code.
5917	* @param pThis The shared VGA/VMSVGA instance data.
5918	* @param pThisCC The VGA/VMSVGA state for ring-3.
5919	*/
5920	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5921	{
5922	# ifdef VBOX_WITH_VMSVGA3D
5923	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5924	# endif
5925
5926	/* Device caps. */
5927	pThis->svga.u32DeviceCaps = SVGA_CAP_GMR
5928	\| SVGA_CAP_GMR2
5929	\| SVGA_CAP_CURSOR
5930	\| SVGA_CAP_CURSOR_BYPASS
5931	\| SVGA_CAP_CURSOR_BYPASS_2
5932	\| SVGA_CAP_EXTENDED_FIFO
5933	\| SVGA_CAP_IRQMASK
5934	\| SVGA_CAP_PITCHLOCK
5935	\| SVGA_CAP_RECT_COPY
5936	\| SVGA_CAP_TRACES
5937	\| SVGA_CAP_SCREEN_OBJECT_2
5938	\| SVGA_CAP_ALPHA_CURSOR;
5939
5940	/* VGPU10 capabilities. */
5941	if (pThis->fVMSVGA10)
5942	{
5943	pThis->svga.u32DeviceCaps \|= SVGA_CAP_COMMAND_BUFFERS /* Enable register based command buffer submission. */
5944	// \| SVGA_CAP_CMD_BUFFERS_2 /* Support for SVGA_REG_CMD_PREPEND_LOW/HIGH */
5945	;
5946
5947	# ifdef VBOX_WITH_VMSVGA3D
5948	if (pSVGAState->pFuncsGBO)
5949	pThis->svga.u32DeviceCaps \|= SVGA_CAP_GBOBJECTS; /* Enable guest-backed objects and surfaces. */
5950	if (pSVGAState->pFuncsDX)
5951	pThis->svga.u32DeviceCaps \|= SVGA_CAP_DX; /* Enable support for DX commands, and command buffers in a mob. */
5952	# endif
5953	}
5954
5955	# ifdef VBOX_WITH_VMSVGA3D
5956	if (pSVGAState->pFuncs3D)
5957	pThis->svga.u32DeviceCaps \|= SVGA_CAP_3D;
5958	# endif
5959
5960	/* Clear the FIFO. */
5961	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
5962
5963	/* Setup FIFO capabilities. */
5964	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5965	\| SVGA_FIFO_CAP_PITCHLOCK
5966	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5967	\| SVGA_FIFO_CAP_RESERVE
5968	\| SVGA_FIFO_CAP_GMR2
5969	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5970	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5971
5972	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5973	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5974	}
5975
5976	# ifdef VBOX_WITH_VMSVGA3D
5977	/**
5978	* Initializes the host 3D capabilities and writes them to FIFO memory.
5979	*
5980	* @returns VBox status code.
5981	* @param pThis The shared VGA/VMSVGA instance data.
5982	* @param pThisCC The VGA/VMSVGA state for ring-3.
5983	*/
5984	static void vmsvgaR3InitFifo3DCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5985	{
5986	/* Query the capabilities and store them in the pThis->svga.au32DevCaps array. */
5987	bool const fSavedBuffering = RTLogRelSetBuffering(true);
5988
5989	for (unsigned i = 0; i < RT_ELEMENTS(pThis->svga.au32DevCaps); ++i)
5990	{
5991	uint32_t val = 0;
5992	int rc = vmsvga3dQueryCaps(pThisCC, (SVGA3dDevCapIndex)i, &val);
5993	if (RT_SUCCESS(rc))
5994	pThis->svga.au32DevCaps[i] = val;
5995	else
5996	pThis->svga.au32DevCaps[i] = 0;
5997
5998	/* LogRel the capability value. */
5999	if (i < SVGA3D_DEVCAP_MAX)
6000	{
6001	char const *pszDevCapName = &vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)i)[sizeof("SVGA3D_DEVCAP")];
6002	if (RT_SUCCESS(rc))
6003	{
6004	if ( i == SVGA3D_DEVCAP_MAX_POINT_SIZE
6005	\|\| i == SVGA3D_DEVCAP_MAX_LINE_WIDTH
6006	\|\| i == SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH)
6007	{
6008	float const fval = (float )&val;
6009	LogRel(("VMSVGA3d: cap[%u]=" FLOAT_FMT_STR " {%s}\n", i, FLOAT_FMT_ARGS(fval), pszDevCapName));
6010	}
6011	else
6012	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, pszDevCapName));
6013	}
6014	else
6015	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc {%s}\n", i, rc, pszDevCapName));
6016	}
6017	else
6018	LogRel(("VMSVGA3d: new cap[%u]=%#010x rc=%Rrc\n", i, val, rc));
6019	}
6020
6021	RTLogRelSetBuffering(fSavedBuffering);
6022
6023	/* 3d hardware version; latest and greatest */
6024	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6025	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6026
6027	/* Fill out 3d capabilities up to SVGA3D_DEVCAP_SURFACEFMT_ATI2 in the FIFO memory.
6028	* SVGA3D_DEVCAP_SURFACEFMT_ATI2 is the last capabiltiy for pre-SVGA_CAP_GBOBJECTS hardware.
6029	* If the VMSVGA device supports SVGA_CAP_GBOBJECTS capability, then the guest has to use SVGA_REG_DEV_CAP
6030	* register to query the devcaps. Older guests will still try to read the devcaps from FIFO.
6031	*/
6032	SVGA3dCapsRecord *pCaps;
6033	SVGA3dCapPair *pData;
6034
6035	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
6036	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6037	pData = (SVGA3dCapPair *)&pCaps->data;
6038
6039	AssertCompile(SVGA3D_DEVCAP_DEAD1 == SVGA3D_DEVCAP_SURFACEFMT_ATI2 + 1);
6040	for (unsigned i = 0; i < SVGA3D_DEVCAP_DEAD1; ++i)
6041	{
6042	pData[i][0] = i;
6043	pData[i][1] = pThis->svga.au32DevCaps[i];
6044	}
6045	pCaps->header.length = (sizeof(pCaps->header) + SVGA3D_DEVCAP_DEAD1 * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6046	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6047
6048	/* Mark end of record array (a zero word). */
6049	pCaps->header.length = 0;
6050	}
6051
6052	# endif
6053
6054	/**
6055	* Resets the SVGA hardware state
6056	*
6057	* @returns VBox status code.
6058	* @param pDevIns The device instance.
6059	*/
6060	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6061	{
6062	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6063	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6064	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6065
6066	/* Reset before init? */
6067	if (!pSVGAState)
6068	return VINF_SUCCESS;
6069
6070	Log(("vmsvgaR3Reset\n"));
6071
6072	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6073	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6074	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6075
6076	/* Reset other stuff. */
6077	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6078	RT_ZERO(pThis->svga.au32ScratchRegion);
6079
6080	ASMAtomicWriteBool(&pThis->svga.fBadGuest, false);
6081
6082	vmsvgaR3StateTerm(pThis, pThisCC);
6083	vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
6084
6085	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6086
6087	/* Initialize FIFO and register capabilities. */
6088	vmsvgaR3InitCaps(pThis, pThisCC);
6089
6090	# ifdef VBOX_WITH_VMSVGA3D
6091	if (pThis->svga.f3DEnabled)
6092	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
6093	# endif
6094
6095	/* VRAM tracking is enabled by default during bootup. */
6096	pThis->svga.fVRAMTracking = true;
6097	pThis->svga.fEnabled = false;
6098
6099	/* Invalidate current settings. */
6100	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6101	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6102	pThis->svga.uBpp = pThis->svga.uHostBpp;
6103	pThis->svga.cbScanline = 0;
6104	pThis->svga.u32PitchLock = 0;
6105
6106	return rc;
6107	}
6108
6109	/**
6110	* Cleans up the SVGA hardware state
6111	*
6112	* @returns VBox status code.
6113	* @param pDevIns The device instance.
6114	*/
6115	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6116	{
6117	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6118	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6119
6120	/*
6121	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6122	*/
6123	if (pThisCC->svga.pFIFOIOThread)
6124	{
6125	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6126	NULL /pvParam/, 30000 /ms/);
6127	AssertLogRelRC(rc);
6128
6129	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6130	AssertLogRelRC(rc);
6131	pThisCC->svga.pFIFOIOThread = NULL;
6132	}
6133
6134	/*
6135	* Destroy the special SVGA state.
6136	*/
6137	if (pThisCC->svga.pSvgaR3State)
6138	{
6139	vmsvgaR3StateTerm(pThis, pThisCC);
6140
6141	# ifdef VBOX_WITH_VMSVGA3D
6142	vmsvga3dR3Free3dInterfaces(pThisCC);
6143	# endif
6144
6145	RTMemFree(pThisCC->svga.pSvgaR3State);
6146	pThisCC->svga.pSvgaR3State = NULL;
6147	}
6148
6149	/*
6150	* Free our resources residing in the VGA state.
6151	*/
6152	if (pThisCC->svga.pbVgaFrameBufferR3)
6153	{
6154	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6155	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6156	}
6157	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6158	{
6159	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6160	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6161	}
6162	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6163	{
6164	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6165	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6166	}
6167
6168	return VINF_SUCCESS;
6169	}
6170
6171	static DECLCALLBACK(size_t) vmsvga3dFloatFormat(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
6172	const char pszType, void const pvValue,
6173	int cchWidth, int cchPrecision, unsigned fFlags, void *pvUser)
6174	{
6175	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
6176	double const v = (double )&pvValue;
6177	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, FLOAT_FMT_STR, FLOAT_FMT_ARGS(v));
6178	}
6179
6180	/**
6181	* Initialize the SVGA hardware state
6182	*
6183	* @returns VBox status code.
6184	* @param pDevIns The device instance.
6185	*/
6186	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6187	{
6188	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6189	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6190	PVMSVGAR3STATE pSVGAState;
6191	int rc;
6192
6193	rc = RTStrFormatTypeRegister("float", vmsvga3dFloatFormat, NULL);
6194	AssertMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_ALREADY_EXISTS, ("%Rrc\n", rc), rc);
6195
6196	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6197	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6198
6199	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6200
6201	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6202	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6203	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6204
6205	/* Create event semaphore. */
6206	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6207	AssertRCReturn(rc, rc);
6208
6209	/* Create event semaphore. */
6210	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6211	AssertRCReturn(rc, rc);
6212
6213	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
6214	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6215
6216	rc = vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
6217	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6218
6219	pSVGAState = pThisCC->svga.pSvgaR3State;
6220
6221	/* Register the write-protected GBO access handler type. */
6222	rc = PDMDevHlpPGMHandlerPhysicalTypeRegister(pDevIns, PGMPHYSHANDLERKIND_WRITE,
6223	vmsvgaR3GboAccessHandler,
6224	NULL, NULL,
6225	NULL, NULL,
6226	"VMSVGA GBO", &pSVGAState->hGboAccessHandlerType);
6227	AssertRCReturn(rc, rc);
6228
6229	# ifdef VBOX_WITH_VMSVGA3D
6230	if (pThis->svga.f3DEnabled)
6231	{
6232	/* Load a 3D backend. */
6233	rc = vmsvgaR3Init3dInterfaces(pDevIns, pThis, pThisCC);
6234	if (RT_FAILURE(rc))
6235	{
6236	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6237	pThis->svga.f3DEnabled = false;
6238	}
6239	}
6240	# endif
6241
6242	/* Initialize FIFO and register capabilities. */
6243	vmsvgaR3InitCaps(pThis, pThisCC);
6244
6245	/* VRAM tracking is enabled by default during bootup. */
6246	pThis->svga.fVRAMTracking = true;
6247
6248	/* Set up the host bpp. This value is as a default for the programmable
6249	* bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
6250	* exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
6251	* separated as SVGA_REG_HOST_BITS_PER_PIXEL.
6252	*
6253	* NB: The driver cBits value is currently constant for the lifetime of the
6254	* VM. If that changes, the host bpp logic might need revisiting.
6255	*/
6256	pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
6257
6258	/* Invalidate current settings. */
6259	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6260	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6261	pThis->svga.uBpp = pThis->svga.uHostBpp;
6262	pThis->svga.cbScanline = 0;
6263
6264	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_XRES;
6265	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_YRES;
6266	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6267	{
6268	pThis->svga.u32MaxWidth -= 256;
6269	pThis->svga.u32MaxHeight -= 256;
6270	}
6271	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6272
6273	# ifdef DEBUG_GMR_ACCESS
6274	/* Register the GMR access handler type. */
6275	rc = PDMDevHlpPGMHandlerPhysicalTypeRegister(pDevIns, PGMPHYSHANDLERKIND_WRITE,
6276	vmsvgaR3GmrAccessHandler,
6277	NULL, NULL,
6278	NULL, NULL,
6279	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6280	AssertRCReturn(rc, rc);
6281	# endif
6282
6283	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6284	/* Register the FIFO access handler type. In addition to
6285	debugging FIFO access, this is also used to facilitate
6286	extended fifo thread sleeps. */
6287	rc = PDMDevHlpPGMHandlerPhysicalTypeRegister(pDevIns,
6288	# ifdef DEBUG_FIFO_ACCESS
6289	PGMPHYSHANDLERKIND_ALL,
6290	# else
6291	PGMPHYSHANDLERKIND_WRITE,
6292	# endif
6293	vmsvgaR3FifoAccessHandler,
6294	NULL, NULL,
6295	NULL, NULL,
6296	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6297	AssertRCReturn(rc, rc);
6298	# endif
6299
6300	/* Create the async IO thread. */
6301	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6302	RTTHREADTYPE_IO, "VMSVGA FIFO");
6303	if (RT_FAILURE(rc))
6304	{
6305	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6306	return rc;
6307	}
6308
6309	/*
6310	* Statistics.
6311	*/
6312	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6313	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6314	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6315	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6316	# ifdef VBOX_WITH_STATISTICS
6317	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6318	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6319	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6320	# endif
6321	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6322	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6323	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6324	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6325	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6326	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6327	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6328	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6329	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6330	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6331	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6332	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6333	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6334	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6335	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6336	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6337	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6338	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6339	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6340	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6341	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6342	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6343	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6344	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6345	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6346	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6347	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6348	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6349	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6350	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6351	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6352	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6353	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6354	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6355	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6356	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6357	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6358	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6359	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6360	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6361	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6362	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
6363	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
6364	REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
6365	REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
6366	REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
6367	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6368	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6369	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6370	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6371	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6372	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6373	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6374	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6375	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6376	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6377	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6378	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6379	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6380
6381	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6382	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6383	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6384	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6385	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6386	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6387	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
6388	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
6389	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) writes.");
6390	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
6391	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6392	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6393	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6394	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6395	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6396	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6397	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6398	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6399	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6400	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6401	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6402	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6403	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6404	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6405	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6406	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6407	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6408	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6409	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6410	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6411	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6412	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6413	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6414	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6415	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6416	REG_CNT(&pThis->svga.StatRegCommandLowWr, "VMSVGA/Reg/CommandLowWrite", "SVGA_REG_COMMAND_LOW writes.");
6417	REG_CNT(&pThis->svga.StatRegCommandHighWr, "VMSVGA/Reg/CommandHighWrite", "SVGA_REG_COMMAND_HIGH writes.");
6418	REG_CNT(&pThis->svga.StatRegDevCapWr, "VMSVGA/Reg/DevCapWrite", "SVGA_REG_DEV_CAP writes.");
6419	REG_CNT(&pThis->svga.StatRegCmdPrependLowWr, "VMSVGA/Reg/CmdPrependLowWrite", "SVGA_REG_CMD_PREPEND_LOW writes.");
6420	REG_CNT(&pThis->svga.StatRegCmdPrependHighWr, "VMSVGA/Reg/CmdPrependHighWrite", "SVGA_REG_CMD_PREPEND_HIGH writes.");
6421
6422	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6423	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6424	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6425	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6426	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6427	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6428	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
6429	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
6430	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) reads.");
6431	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
6432	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6433	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6434	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6435	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6436	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6437	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6438	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6439	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6440	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6441	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6442	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6443	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6444	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6445	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6446	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6447	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6448	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6449	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6450	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6451	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6452	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6453	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6454	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6455	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6456	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6457	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6458	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6459	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6460	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6461	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6462	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6463	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6464	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6465	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6466	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6467	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6468	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6469	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6470	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6471	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6472	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6473	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6474	REG_CNT(&pThis->svga.StatRegCommandLowRd, "VMSVGA/Reg/CommandLowRead", "SVGA_REG_COMMAND_LOW reads.");
6475	REG_CNT(&pThis->svga.StatRegCommandHighRd, "VMSVGA/Reg/CommandHighRead", "SVGA_REG_COMMAND_HIGH reads.");
6476	REG_CNT(&pThis->svga.StatRegMaxPrimBBMemRd, "VMSVGA/Reg/MaxPrimBBMemRead", "SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM reads.");
6477	REG_CNT(&pThis->svga.StatRegGBMemSizeRd, "VMSVGA/Reg/GBMemSizeRead", "SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB reads.");
6478	REG_CNT(&pThis->svga.StatRegDevCapRd, "VMSVGA/Reg/DevCapRead", "SVGA_REG_DEV_CAP reads.");
6479	REG_CNT(&pThis->svga.StatRegCmdPrependLowRd, "VMSVGA/Reg/CmdPrependLowRead", "SVGA_REG_CMD_PREPEND_LOW reads.");
6480	REG_CNT(&pThis->svga.StatRegCmdPrependHighRd, "VMSVGA/Reg/CmdPrependHighRead", "SVGA_REG_CMD_PREPEND_HIGH reads.");
6481	REG_CNT(&pThis->svga.StatRegScrnTgtMaxWidthRd, "VMSVGA/Reg/ScrnTgtMaxWidthRead", "SVGA_REG_SCREENTARGET_MAX_WIDTH reads.");
6482	REG_CNT(&pThis->svga.StatRegScrnTgtMaxHeightRd, "VMSVGA/Reg/ScrnTgtMaxHeightRead", "SVGA_REG_SCREENTARGET_MAX_HEIGHT reads.");
6483	REG_CNT(&pThis->svga.StatRegMobMaxSizeRd, "VMSVGA/Reg/MobMaxSizeRead", "SVGA_REG_MOB_MAX_SIZE reads.");
6484
6485	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6486	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6487	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6488	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6489	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6490	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6491	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6492	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6493	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6494	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6495	# endif
6496	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6497	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6498	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6499	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6500	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6501
6502	# undef REG_CNT
6503	# undef REG_PRF
6504
6505	/*
6506	* Info handlers.
6507	*/
6508	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6509	# ifdef VBOX_WITH_VMSVGA3D
6510	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6511	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6512	"VMSVGA 3d surface details. "
6513	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6514	vmsvgaR3Info3dSurface);
6515	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6516	"VMSVGA 3d surface details and bitmap: "
6517	"sid[>dir]",
6518	vmsvgaR3Info3dSurfaceBmp);
6519	# endif
6520
6521	return VINF_SUCCESS;
6522	}
6523
6524	/**
6525	* Power On notification.
6526	*
6527	* @returns VBox status code.
6528	* @param pDevIns The device instance data.
6529	*
6530	* @remarks Caller enters the device critical section.
6531	*/
6532	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6533	{
6534	# ifdef VBOX_WITH_VMSVGA3D
6535	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6536	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6537	if (pThis->svga.f3DEnabled)
6538	{
6539	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6540	int rc = pSVGAState->pFuncs3D->pfnPowerOn(pDevIns, pThis, pThisCC);
6541	if (RT_SUCCESS(rc))
6542	{
6543	/* Initialize FIFO 3D capabilities. */
6544	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
6545	}
6546	else
6547	{
6548	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dPowerOn -> %Rrc)\n", rc));
6549	pThis->svga.f3DEnabled = false;
6550	}
6551	}
6552	# else /* !VBOX_WITH_VMSVGA3D */
6553	RT_NOREF(pDevIns);
6554	# endif /* !VBOX_WITH_VMSVGA3D */
6555	}
6556
6557	/**
6558	* Power Off notification.
6559	*
6560	* @param pDevIns The device instance data.
6561	*
6562	* @remarks Caller enters the device critical section.
6563	*/
6564	DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns)
6565	{
6566	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6567	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6568
6569	/*
6570	* Notify the FIFO thread.
6571	*/
6572	if (pThisCC->svga.pFIFOIOThread)
6573	{
6574	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_POWEROFF,
6575	NULL /pvParam/, 30000 /ms/);
6576	AssertLogRelRC(rc);
6577	}
6578	}
6579
6580	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 92162

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