VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 86195

Last change on this file since 86195 was 86195, checked in by vboxsync, 4 years ago

Devices/Graphics: build fix.
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1/* $Id: DevVGA-SVGA.cpp 86195 2020-09-21 12:51:48Z vboxsync $ */
2/** @file
3 * VMware SVGA device.
4 *
5 * Logging levels guidelines for this and related files:
6 * - Log() for normal bits.
7 * - LogFlow() for more info.
8 * - Log2 for hex dump of cursor data.
9 * - Log3 for hex dump of shader code.
10 * - Log4 for hex dumps of 3D data.
11 * - Log5 for info about GMR pages.
12 * - LogRel for the usual important stuff.
13 * - LogRel2 for cursor.
14 * - LogRel3 for 3D performance data.
15 * - LogRel4 for HW accelerated graphics output.
16 */
17
18/*
19 * Copyright (C) 2013-2020 Oracle Corporation
20 *
21 * This file is part of VirtualBox Open Source Edition (OSE), as
22 * available from http://www.virtualbox.org. This file is free software;
23 * you can redistribute it and/or modify it under the terms of the GNU
24 * General Public License (GPL) as published by the Free Software
25 * Foundation, in version 2 as it comes in the "COPYING" file of the
26 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
27 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
28 */
29
30
31/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
32 *
33 * This device emulation was contributed by trivirt AG. It offers an
34 * alternative to our Bochs based VGA graphics and 3d emulations. This is
35 * valuable for Xorg based guests, as there is driver support shipping with Xorg
36 * since it forked from XFree86.
37 *
38 *
39 * @section sec_dev_vmsvga_sdk The VMware SDK
40 *
41 * This is officially deprecated now, however it's still quite useful,
42 * especially for getting the old features working:
43 * http://vmware-svga.sourceforge.net/
44 *
45 * They currently point developers at the following resources.
46 * - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
47 * - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
48 * - http://cgit.freedesktop.org/mesa/vmwgfx/
49 *
50 * @subsection subsec_dev_vmsvga_sdk_results Test results
51 *
52 * Test results:
53 * - 2dmark.img:
54 * + todo
55 * - backdoor-tclo.img:
56 * + todo
57 * - blit-cube.img:
58 * + todo
59 * - bunnies.img:
60 * + todo
61 * - cube.img:
62 * + todo
63 * - cubemark.img:
64 * + todo
65 * - dynamic-vertex-stress.img:
66 * + todo
67 * - dynamic-vertex.img:
68 * + todo
69 * - fence-stress.img:
70 * + todo
71 * - gmr-test.img:
72 * + todo
73 * - half-float-test.img:
74 * + todo
75 * - noscreen-cursor.img:
76 * - The CURSOR I/O and FIFO registers are not implemented, so the mouse
77 * cursor doesn't show. (Hacking the GUI a little, would make the cursor
78 * visible though.)
79 * - Cursor animation via the palette doesn't work.
80 * - During debugging, it turns out that the framebuffer content seems to
81 * be halfways ignore or something (memset(fb, 0xcc, lots)).
82 * - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
83 * grow it 0x10 fold (128KB -> 2MB like in WS10).
84 * - null.img:
85 * + todo
86 * - pong.img:
87 * + todo
88 * - presentReadback.img:
89 * + todo
90 * - resolution-set.img:
91 * + todo
92 * - rt-gamma-test.img:
93 * + todo
94 * - screen-annotation.img:
95 * + todo
96 * - screen-cursor.img:
97 * + todo
98 * - screen-dma-coalesce.img:
99 * + todo
100 * - screen-gmr-discontig.img:
101 * + todo
102 * - screen-gmr-remap.img:
103 * + todo
104 * - screen-multimon.img:
105 * + todo
106 * - screen-present-clip.img:
107 * + todo
108 * - screen-render-test.img:
109 * + todo
110 * - screen-simple.img:
111 * + todo
112 * - screen-text.img:
113 * + todo
114 * - simple-shaders.img:
115 * + todo
116 * - simple_blit.img:
117 * + todo
118 * - tiny-2d-updates.img:
119 * + todo
120 * - video-formats.img:
121 * + todo
122 * - video-sync.img:
123 * + todo
124 *
125 */
126
127
128/*********************************************************************************************************************************
129* Header Files *
130*********************************************************************************************************************************/
131#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
132#define VMSVGA_USE_EMT_HALT_CODE
133#include <VBox/vmm/pdmdev.h>
134#include <VBox/version.h>
135#include <VBox/err.h>
136#include <VBox/log.h>
137#include <VBox/vmm/pgm.h>
138#ifdef VMSVGA_USE_EMT_HALT_CODE
139# include <VBox/vmm/vmapi.h>
140# include <VBox/vmm/vmcpuset.h>
141#endif
142#include <VBox/sup.h>
143
144#include <iprt/assert.h>
145#include <iprt/semaphore.h>
146#include <iprt/uuid.h>
147#ifdef IN_RING3
148# include <iprt/ctype.h>
149# include <iprt/mem.h>
150# ifdef VBOX_STRICT
151# include <iprt/time.h>
152# endif
153#endif
154
155#include <VBox/AssertGuest.h>
156#include <VBox/VMMDev.h>
157#include <VBoxVideo.h>
158#include <VBox/bioslogo.h>
159
160/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
161#include "DevVGA.h"
162
163#include "DevVGA-SVGA.h"
164#ifdef VBOX_WITH_VMSVGA3D
165# include "DevVGA-SVGA3d.h"
166# ifdef RT_OS_DARWIN
167# include "DevVGA-SVGA3d-cocoa.h"
168# endif
169# ifdef RT_OS_LINUX
170# ifdef IN_RING3
171#include "DevVGA-SVGA3d-glLdr.h"
172# endif
173# endif
174#endif
175
176
177/*********************************************************************************************************************************
178* Defined Constants And Macros *
179*********************************************************************************************************************************/
180/**
181 * Macro for checking if a fixed FIFO register is valid according to the
182 * current FIFO configuration.
183 *
184 * @returns true / false.
185 * @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
186 * @param a_offFifoMin A valid SVGA_FIFO_MIN value.
187 */
188#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
189
190
191/*********************************************************************************************************************************
192* Structures and Typedefs *
193*********************************************************************************************************************************/
194/**
195 * 64-bit GMR descriptor.
196 */
197typedef struct
198{
199 RTGCPHYS GCPhys;
200 uint64_t numPages;
201} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
202
203/**
204 * GMR slot
205 */
206typedef struct
207{
208 uint32_t cMaxPages;
209 uint32_t cbTotal;
210 uint32_t numDescriptors;
211 PVMSVGAGMRDESCRIPTOR paDesc;
212} GMR, *PGMR;
213
214#ifdef IN_RING3
215typedef struct VMSVGACMDBUF *PVMSVGACMDBUF;
216typedef struct VMSVGACMDBUFCTX *PVMSVGACMDBUFCTX;
217
218/* Command buffer. */
219typedef struct VMSVGACMDBUF
220{
221 RTLISTNODE nodeBuffer;
222 /* Context of the buffer. */
223 PVMSVGACMDBUFCTX pCmdBufCtx;
224 /* PA of the buffer. */
225 RTGCPHYS GCPhysCB;
226 /* A copy of the buffer header. */
227 SVGACBHeader hdr;
228 /* A copy of the commands. Size of the memory buffer is hdr.length */
229 void *pvCommands;
230} VMSVGACMDBUF;
231
232/* Command buffer context. */
233typedef struct VMSVGACMDBUFCTX
234{
235 /* Buffers submitted to processing for the FIFO thread. */
236 RTLISTANCHOR listSubmitted;
237 /* How many buffers in the queue. */
238 uint32_t cSubmitted;
239} VMSVGACMDBUFCTX;
240
241/**
242 * Internal SVGA ring-3 only state.
243 */
244typedef struct VMSVGAR3STATE
245{
246 GMR *paGMR; // [VMSVGAState::cGMR]
247 struct
248 {
249 SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
250 uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
251 SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
252 } GMRFB;
253 struct
254 {
255 bool fActive;
256 uint32_t xHotspot;
257 uint32_t yHotspot;
258 uint32_t width;
259 uint32_t height;
260 uint32_t cbData;
261 void *pData;
262 } Cursor;
263 SVGAColorBGRX colorAnnotation;
264
265# ifdef VMSVGA_USE_EMT_HALT_CODE
266 /** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
267 uint32_t volatile cBusyDelayedEmts;
268 /** Set of EMTs that are */
269 VMCPUSET BusyDelayedEmts;
270# else
271 /** Number of EMTs waiting on hBusyDelayedEmts. */
272 uint32_t volatile cBusyDelayedEmts;
273 /** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
274 * busy (ugly). */
275 RTSEMEVENTMULTI hBusyDelayedEmts;
276# endif
277
278 /** Information about screens. */
279 VMSVGASCREENOBJECT aScreens[64];
280
281 /** Command buffer contexts. */
282 PVMSVGACMDBUFCTX apCmdBufCtxs[SVGA_CB_CONTEXT_MAX];
283 /** The special Device Context for synchronous commands. */
284 VMSVGACMDBUFCTX CmdBufCtxDC;
285 /** Flag which indicates that there are buffers to be processed. */
286 uint32_t volatile fCmdBuf;
287 /** Critical section for accessing the command buffer data. */
288 RTCRITSECT CritSectCmdBuf;
289
290 /** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
291 STAMPROFILE StatBusyDelayEmts;
292
293 STAMPROFILE StatR3Cmd3dPresentProf;
294 STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
295 STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
296 STAMPROFILE StatR3Cmd3dBlitSurfaceToScreenProf;
297 STAMCOUNTER StatR3CmdDefineGmr2;
298 STAMCOUNTER StatR3CmdDefineGmr2Free;
299 STAMCOUNTER StatR3CmdDefineGmr2Modify;
300 STAMCOUNTER StatR3CmdRemapGmr2;
301 STAMCOUNTER StatR3CmdRemapGmr2Modify;
302 STAMCOUNTER StatR3CmdInvalidCmd;
303 STAMCOUNTER StatR3CmdFence;
304 STAMCOUNTER StatR3CmdUpdate;
305 STAMCOUNTER StatR3CmdUpdateVerbose;
306 STAMCOUNTER StatR3CmdDefineCursor;
307 STAMCOUNTER StatR3CmdDefineAlphaCursor;
308 STAMCOUNTER StatR3CmdMoveCursor;
309 STAMCOUNTER StatR3CmdDisplayCursor;
310 STAMCOUNTER StatR3CmdRectFill;
311 STAMCOUNTER StatR3CmdRectCopy;
312 STAMCOUNTER StatR3CmdRectRopCopy;
313 STAMCOUNTER StatR3CmdEscape;
314 STAMCOUNTER StatR3CmdDefineScreen;
315 STAMCOUNTER StatR3CmdDestroyScreen;
316 STAMCOUNTER StatR3CmdDefineGmrFb;
317 STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
318 STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
319 STAMCOUNTER StatR3CmdAnnotationFill;
320 STAMCOUNTER StatR3CmdAnnotationCopy;
321 STAMCOUNTER StatR3Cmd3dSurfaceDefine;
322 STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
323 STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
324 STAMCOUNTER StatR3Cmd3dSurfaceCopy;
325 STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
326 STAMCOUNTER StatR3Cmd3dSurfaceDma;
327 STAMCOUNTER StatR3Cmd3dSurfaceScreen;
328 STAMCOUNTER StatR3Cmd3dContextDefine;
329 STAMCOUNTER StatR3Cmd3dContextDestroy;
330 STAMCOUNTER StatR3Cmd3dSetTransform;
331 STAMCOUNTER StatR3Cmd3dSetZRange;
332 STAMCOUNTER StatR3Cmd3dSetRenderState;
333 STAMCOUNTER StatR3Cmd3dSetRenderTarget;
334 STAMCOUNTER StatR3Cmd3dSetTextureState;
335 STAMCOUNTER StatR3Cmd3dSetMaterial;
336 STAMCOUNTER StatR3Cmd3dSetLightData;
337 STAMCOUNTER StatR3Cmd3dSetLightEnable;
338 STAMCOUNTER StatR3Cmd3dSetViewPort;
339 STAMCOUNTER StatR3Cmd3dSetClipPlane;
340 STAMCOUNTER StatR3Cmd3dClear;
341 STAMCOUNTER StatR3Cmd3dPresent;
342 STAMCOUNTER StatR3Cmd3dPresentReadBack;
343 STAMCOUNTER StatR3Cmd3dShaderDefine;
344 STAMCOUNTER StatR3Cmd3dShaderDestroy;
345 STAMCOUNTER StatR3Cmd3dSetShader;
346 STAMCOUNTER StatR3Cmd3dSetShaderConst;
347 STAMCOUNTER StatR3Cmd3dDrawPrimitives;
348 STAMCOUNTER StatR3Cmd3dSetScissorRect;
349 STAMCOUNTER StatR3Cmd3dBeginQuery;
350 STAMCOUNTER StatR3Cmd3dEndQuery;
351 STAMCOUNTER StatR3Cmd3dWaitForQuery;
352 STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
353 STAMCOUNTER StatR3Cmd3dActivateSurface;
354 STAMCOUNTER StatR3Cmd3dDeactivateSurface;
355
356 STAMCOUNTER StatR3RegConfigDoneWr;
357 STAMCOUNTER StatR3RegGmrDescriptorWr;
358 STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
359 STAMCOUNTER StatR3RegGmrDescriptorWrFree;
360
361 STAMCOUNTER StatFifoCommands;
362 STAMCOUNTER StatFifoErrors;
363 STAMCOUNTER StatFifoUnkCmds;
364 STAMCOUNTER StatFifoTodoTimeout;
365 STAMCOUNTER StatFifoTodoWoken;
366 STAMPROFILE StatFifoStalls;
367 STAMPROFILE StatFifoExtendedSleep;
368# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
369 STAMCOUNTER StatFifoAccessHandler;
370# endif
371 STAMCOUNTER StatFifoCursorFetchAgain;
372 STAMCOUNTER StatFifoCursorNoChange;
373 STAMCOUNTER StatFifoCursorPosition;
374 STAMCOUNTER StatFifoCursorVisiblity;
375 STAMCOUNTER StatFifoWatchdogWakeUps;
376} VMSVGAR3STATE, *PVMSVGAR3STATE;
377#endif /* IN_RING3 */
378
379
380/*********************************************************************************************************************************
381* Internal Functions *
382*********************************************************************************************************************************/
383#ifdef IN_RING3
384# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
385static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
386# endif
387# ifdef DEBUG_GMR_ACCESS
388static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
389# endif
390#endif
391
392
393/*********************************************************************************************************************************
394* Global Variables *
395*********************************************************************************************************************************/
396#ifdef IN_RING3
397
398/**
399 * SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
400 */
401static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
402{
403 SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
404 SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
405 SSMFIELD_ENTRY_TERM()
406};
407
408/**
409 * SSM descriptor table for the GMR structure.
410 */
411static SSMFIELD const g_aGMRFields[] =
412{
413 SSMFIELD_ENTRY( GMR, cMaxPages),
414 SSMFIELD_ENTRY( GMR, cbTotal),
415 SSMFIELD_ENTRY( GMR, numDescriptors),
416 SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
417 SSMFIELD_ENTRY_TERM()
418};
419
420/**
421 * SSM descriptor table for the VMSVGASCREENOBJECT structure.
422 */
423static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
424{
425 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
426 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
427 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
428 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
429 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
430 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
431 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
432 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
433 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
434 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
435 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
436 SSMFIELD_ENTRY_TERM()
437};
438
439/**
440 * SSM descriptor table for the VMSVGAR3STATE structure.
441 */
442static SSMFIELD const g_aVMSVGAR3STATEFields[] =
443{
444 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
445 SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
446 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
447 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
448 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
449 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
450 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
451 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
452 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
453 SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
454 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
455#ifdef VMSVGA_USE_EMT_HALT_CODE
456 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
457#else
458 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
459#endif
460 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
461 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
462 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
463 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
464 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
465 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
466 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
467 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
468 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
469 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
470 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
471 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
472 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
473 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
474 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
475 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
476 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
477 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
478 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
479 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
480 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
481 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
482 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
483 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
484 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
485 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
486 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
487 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
488 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
489 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
490 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
491 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
492 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
493 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
494 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
495 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
496 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
497 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
498 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
499 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
500 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
501 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
502 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
503 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
504 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
505 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
506 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
507 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
508 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
509 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
510 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
511 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
512 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
513 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
514 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
515 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
516 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
517 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
518 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
519 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
520 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
521 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
522 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
523
524 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
525 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
526 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
527 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
528
529 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
530 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
531 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
532 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
533 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
534 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
535 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
536# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
537 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
538# endif
539 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
540 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
541 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
542 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
543
544 SSMFIELD_ENTRY_TERM()
545};
546
547/**
548 * SSM descriptor table for the VGAState.svga structure.
549 */
550static SSMFIELD const g_aVGAStateSVGAFields[] =
551{
552 SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
553 SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
554 SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
555 SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
556 SSMFIELD_ENTRY( VMSVGAState, fEnabled),
557 SSMFIELD_ENTRY( VMSVGAState, fConfigured),
558 SSMFIELD_ENTRY( VMSVGAState, fBusy),
559 SSMFIELD_ENTRY( VMSVGAState, fTraces),
560 SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
561 SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
562 SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
563 SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
564 SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
565 SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
566 SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
567 SSMFIELD_ENTRY( VMSVGAState, u32DeviceCaps),
568 SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
569 SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
570 SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
571 SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
572 SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
573 SSMFIELD_ENTRY( VMSVGAState, uWidth),
574 SSMFIELD_ENTRY( VMSVGAState, uHeight),
575 SSMFIELD_ENTRY( VMSVGAState, uBpp),
576 SSMFIELD_ENTRY( VMSVGAState, cbScanline),
577 SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
578 SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
579 SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
580 SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
581 SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
582 SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
583 SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
584 SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
585 SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
586 SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
587 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
588 SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
589 SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
590 SSMFIELD_ENTRY_TERM()
591};
592#endif /* IN_RING3 */
593
594
595/*********************************************************************************************************************************
596* Internal Functions *
597*********************************************************************************************************************************/
598#ifdef IN_RING3
599static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
600static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
601 uint32_t uVersion, uint32_t uPass);
602static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
603static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx);
604# ifdef VBOX_WITH_VMSVGA3D
605static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR);
606# endif /* VBOX_WITH_VMSVGA3D */
607#endif /* IN_RING3 */
608
609
610
611#ifdef IN_RING3
612VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
613{
614 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
615 if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
616 && pSVGAState
617 && pSVGAState->aScreens[idScreen].fDefined)
618 {
619 return &pSVGAState->aScreens[idScreen];
620 }
621 return NULL;
622}
623
624void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
625{
626# ifdef VBOX_WITH_VMSVGA3D
627 if (pThis->svga.f3DEnabled)
628 {
629 for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
630 {
631 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
632 if (pScreen)
633 vmsvga3dDestroyScreen(pThisCC, pScreen);
634 }
635 }
636# else
637 RT_NOREF(pThis, pThisCC);
638# endif
639}
640#endif /* IN_RING3 */
641
642#define SVGA_CASE_ID2STR(idx) case idx: return #idx
643
644#ifdef LOG_ENABLED
645
646/**
647 * Index register string name lookup
648 *
649 * @returns Index register string or "UNKNOWN"
650 * @param pThis The shared VGA/VMSVGA state.
651 * @param idxReg The index register.
652 */
653static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
654{
655 switch (idxReg)
656 {
657 SVGA_CASE_ID2STR(SVGA_REG_ID);
658 SVGA_CASE_ID2STR(SVGA_REG_ENABLE);
659 SVGA_CASE_ID2STR(SVGA_REG_WIDTH);
660 SVGA_CASE_ID2STR(SVGA_REG_HEIGHT);
661 SVGA_CASE_ID2STR(SVGA_REG_MAX_WIDTH);
662 SVGA_CASE_ID2STR(SVGA_REG_MAX_HEIGHT);
663 SVGA_CASE_ID2STR(SVGA_REG_DEPTH);
664 SVGA_CASE_ID2STR(SVGA_REG_BITS_PER_PIXEL); /* Current bpp in the guest */
665 SVGA_CASE_ID2STR(SVGA_REG_PSEUDOCOLOR);
666 SVGA_CASE_ID2STR(SVGA_REG_RED_MASK);
667 SVGA_CASE_ID2STR(SVGA_REG_GREEN_MASK);
668 SVGA_CASE_ID2STR(SVGA_REG_BLUE_MASK);
669 SVGA_CASE_ID2STR(SVGA_REG_BYTES_PER_LINE);
670 SVGA_CASE_ID2STR(SVGA_REG_FB_START); /* (Deprecated) */
671 SVGA_CASE_ID2STR(SVGA_REG_FB_OFFSET);
672 SVGA_CASE_ID2STR(SVGA_REG_VRAM_SIZE);
673 SVGA_CASE_ID2STR(SVGA_REG_FB_SIZE);
674
675 /* ID 0 implementation only had the above registers, then the palette */
676 SVGA_CASE_ID2STR(SVGA_REG_CAPABILITIES);
677 SVGA_CASE_ID2STR(SVGA_REG_MEM_START); /* (Deprecated) */
678 SVGA_CASE_ID2STR(SVGA_REG_MEM_SIZE);
679 SVGA_CASE_ID2STR(SVGA_REG_CONFIG_DONE); /* Set when memory area configured */
680 SVGA_CASE_ID2STR(SVGA_REG_SYNC); /* See "FIFO Synchronization Registers" */
681 SVGA_CASE_ID2STR(SVGA_REG_BUSY); /* See "FIFO Synchronization Registers" */
682 SVGA_CASE_ID2STR(SVGA_REG_GUEST_ID); /* Set guest OS identifier */
683 SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ID); /* (Deprecated) */
684 SVGA_CASE_ID2STR(SVGA_REG_CURSOR_X); /* (Deprecated) */
685 SVGA_CASE_ID2STR(SVGA_REG_CURSOR_Y); /* (Deprecated) */
686 SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ON); /* (Deprecated) */
687 SVGA_CASE_ID2STR(SVGA_REG_HOST_BITS_PER_PIXEL); /* (Deprecated) */
688 SVGA_CASE_ID2STR(SVGA_REG_SCRATCH_SIZE); /* Number of scratch registers */
689 SVGA_CASE_ID2STR(SVGA_REG_MEM_REGS); /* Number of FIFO registers */
690 SVGA_CASE_ID2STR(SVGA_REG_NUM_DISPLAYS); /* (Deprecated) */
691 SVGA_CASE_ID2STR(SVGA_REG_PITCHLOCK); /* Fixed pitch for all modes */
692 SVGA_CASE_ID2STR(SVGA_REG_IRQMASK); /* Interrupt mask */
693
694 /* Legacy multi-monitor support */
695 SVGA_CASE_ID2STR(SVGA_REG_NUM_GUEST_DISPLAYS); /* Number of guest displays in X/Y direction */
696 SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_ID); /* Display ID for the following display attributes */
697 SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_IS_PRIMARY); /* Whether this is a primary display */
698 SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_X); /* The display position x */
699 SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_Y); /* The display position y */
700 SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_WIDTH); /* The display's width */
701 SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_HEIGHT); /* The display's height */
702
703 SVGA_CASE_ID2STR(SVGA_REG_GMR_ID);
704 SVGA_CASE_ID2STR(SVGA_REG_GMR_DESCRIPTOR);
705 SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_IDS);
706 SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
707
708 SVGA_CASE_ID2STR(SVGA_REG_TRACES); /* Enable trace-based updates even when FIFO is on */
709 SVGA_CASE_ID2STR(SVGA_REG_GMRS_MAX_PAGES); /* Maximum number of 4KB pages for all GMRs */
710 SVGA_CASE_ID2STR(SVGA_REG_MEMORY_SIZE); /* Total dedicated device memory excluding FIFO */
711 SVGA_CASE_ID2STR(SVGA_REG_COMMAND_LOW); /* Lower 32 bits and submits commands */
712 SVGA_CASE_ID2STR(SVGA_REG_COMMAND_HIGH); /* Upper 32 bits of command buffer PA */
713 SVGA_CASE_ID2STR(SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); /* Max primary memory */
714 SVGA_CASE_ID2STR(SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); /* Suggested limit on mob mem */
715 SVGA_CASE_ID2STR(SVGA_REG_DEV_CAP); /* Write dev cap index, read value */
716 SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_LOW);
717 SVGA_CASE_ID2STR(SVGA_REG_iCMD_PREPEND_HIGH);
718 SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_WIDTH);
719 SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_HEIGHT);
720 SVGA_CASE_ID2STR(SVGA_REG_MOB_MAX_SIZE);
721 SVGA_CASE_ID2STR(SVGA_REG_TOP); /* Must be 1 more than the last register */
722
723 default:
724 if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
725 return "SVGA_SCRATCH_BASE reg";
726 if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
727 return "SVGA_PALETTE_BASE reg";
728 return "UNKNOWN";
729 }
730}
731
732#ifdef IN_RING3
733/**
734 * FIFO command name lookup
735 *
736 * @returns FIFO command string or "UNKNOWN"
737 * @param u32Cmd FIFO command
738 */
739static const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
740{
741 switch (u32Cmd)
742 {
743 SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
744 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
745 SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
746 SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
747 SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
748 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
749 SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
750 SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
751 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
752 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
753 SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
754 SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
755 SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
756 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
757 SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
758 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
759 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
760 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
761 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
762 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
763 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
764 SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
765 SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
766 SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
767 SVGA_CASE_ID2STR(SVGA_CMD_NOP);
768 SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
769 SVGA_CASE_ID2STR(SVGA_CMD_MAX);
770 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
771 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
772 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
773 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
774 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
775 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
776 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
777 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
778 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
779 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
780 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
781 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
782 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
783 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
784 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
785 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
786 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
787 SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
788 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
789 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
790 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
791 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
792 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
793 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
794 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
795 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
796 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
797 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
798 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
799 SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
800 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
801 SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
802 SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_CREATE_DECODER);
803 SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_DESTROY_DECODER);
804 SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR);
805 SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR);
806 SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_DECODE_START_FRAME);
807 SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_DECODE_RENDER);
808 SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_DECODE_END_FRAME);
809 SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_PROCESS_FRAME);
810 SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
811 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
812 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
813 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD1);
814 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
815 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
816 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
817 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
818 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
819 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
820 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
821 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
822 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
823 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
824 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
825 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
826 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
827 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
828 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
829 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
830 SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
831 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
832 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
833 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
834 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
835 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
836 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
837 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
838 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
839 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
840 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
841 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
842 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
843 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
844 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
845 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
846 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
847 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
848 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
849 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
850 SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
851 SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
852 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
853 SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
854 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
855 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
856 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
857 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
858 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
859 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
860 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
861 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
862 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
863 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
864 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
865 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
866 SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
867 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
868 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
869 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
870 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
871 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
872 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
873 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
874 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
875 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
876 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
877 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
878 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
879 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
880 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
881 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
882 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
883 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
884 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
885 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
886 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
887 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
888 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
889 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
890 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
891 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
892 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
893 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
894 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
895 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
896 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
897 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
898 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
899 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
900 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
901 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
902 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
903 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
904 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
905 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
906 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
907 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
908 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
909 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
910 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_STRETCHBLT);
911 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
912 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
913 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
914 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
915 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
916 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
917 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
918 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
919 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
920 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
921 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
922 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
923 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
924 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
925 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
926 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
927 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
928 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
929 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
930 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
931 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
932 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
933 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
934 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
935 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
936 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
937 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
938 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
939 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
940 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
941 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
942 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
943 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
944 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
945 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
946 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
947 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
948 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
949 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
950 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
951 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
952 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
953 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESERVED1);
954 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESERVED2);
955 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESERVED3);
956 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
957 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MAX);
958 default: return "UNKNOWN";
959 }
960}
961# endif /* IN_RING3 */
962
963#endif /* LOG_ENABLED */
964#ifdef IN_RING3
965
966/**
967 * @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
968 */
969DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
970{
971 PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
972 PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
973
974 Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
975 VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
976
977 /** @todo Test how it interacts with multiple screen objects. */
978 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
979 uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
980 uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
981
982 if (x < uWidth)
983 {
984 pThis->svga.viewport.x = x;
985 pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
986 pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
987 }
988 else
989 {
990 pThis->svga.viewport.x = uWidth;
991 pThis->svga.viewport.cx = 0;
992 pThis->svga.viewport.xRight = uWidth;
993 }
994 if (y < uHeight)
995 {
996 pThis->svga.viewport.y = y;
997 pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
998 pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
999 pThis->svga.viewport.yHighWC = uHeight - y;
1000 }
1001 else
1002 {
1003 pThis->svga.viewport.y = uHeight;
1004 pThis->svga.viewport.cy = 0;
1005 pThis->svga.viewport.yLowWC = 0;
1006 pThis->svga.viewport.yHighWC = 0;
1007 }
1008
1009# ifdef VBOX_WITH_VMSVGA3D
1010 /*
1011 * Now inform the 3D backend.
1012 */
1013 if (pThis->svga.f3DEnabled)
1014 vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
1015# else
1016 RT_NOREF(OldViewport);
1017# endif
1018}
1019
1020
1021/**
1022 * Updating screen information in API
1023 *
1024 * @param pThis The The shared VGA/VMSVGA instance data.
1025 * @param pThisCC The VGA/VMSVGA state for ring-3.
1026 */
1027void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
1028{
1029 int rc;
1030
1031 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1032
1033 for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1034 {
1035 VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1036 if (!pScreen->fModified)
1037 continue;
1038
1039 pScreen->fModified = false;
1040
1041 VBVAINFOVIEW view;
1042 RT_ZERO(view);
1043 view.u32ViewIndex = pScreen->idScreen;
1044 // view.u32ViewOffset = 0;
1045 view.u32ViewSize = pThis->vram_size;
1046 view.u32MaxScreenSize = pThis->vram_size;
1047
1048 VBVAINFOSCREEN screen;
1049 RT_ZERO(screen);
1050 screen.u32ViewIndex = pScreen->idScreen;
1051
1052 if (pScreen->fDefined)
1053 {
1054 if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1055 || pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1056 || pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1057 {
1058 Assert(pThis->svga.fGFBRegisters);
1059 continue;
1060 }
1061
1062 screen.i32OriginX = pScreen->xOrigin;
1063 screen.i32OriginY = pScreen->yOrigin;
1064 screen.u32StartOffset = pScreen->offVRAM;
1065 screen.u32LineSize = pScreen->cbPitch;
1066 screen.u32Width = pScreen->cWidth;
1067 screen.u32Height = pScreen->cHeight;
1068 screen.u16BitsPerPixel = pScreen->cBpp;
1069 if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1070 screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1071 if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1072 screen.u16Flags |= VBVA_SCREEN_F_BLANK2;
1073 }
1074 else
1075 {
1076 /* Screen is destroyed. */
1077 screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1078 }
1079
1080 rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pThisCC->pbVRam, /*fResetInputMapping=*/ true);
1081 AssertRC(rc);
1082 }
1083}
1084
1085
1086/**
1087 * @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
1088 *
1089 * Used to update screen offsets (positions) since appearently vmwgfx fails to
1090 * pass correct offsets thru FIFO.
1091 */
1092DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
1093{
1094 PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
1095 PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
1096 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1097
1098 AssertReturnVoid(pSVGAState);
1099
1100 /* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
1101 cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
1102 for (uint32_t i = 0; i < cPositions; ++i)
1103 {
1104 if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
1105 && pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
1106 continue;
1107
1108 if (pSVGAState->aScreens[i].xOrigin == -1)
1109 continue;
1110 if (pSVGAState->aScreens[i].yOrigin == -1)
1111 continue;
1112
1113 pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
1114 pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
1115 pSVGAState->aScreens[i].fModified = true;
1116 }
1117
1118 vmsvgaR3VBVAResize(pThis, pThisCC);
1119}
1120
1121#endif /* IN_RING3 */
1122
1123/**
1124 * Read port register
1125 *
1126 * @returns VBox status code.
1127 * @param pDevIns The device instance.
1128 * @param pThis The shared VGA/VMSVGA state.
1129 * @param pu32 Where to store the read value
1130 */
1131static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
1132{
1133#ifdef IN_RING3
1134 PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
1135#endif
1136 int rc = VINF_SUCCESS;
1137 *pu32 = 0;
1138
1139 /* Rough index register validation. */
1140 uint32_t idxReg = pThis->svga.u32IndexReg;
1141#if !defined(IN_RING3) && defined(VBOX_STRICT)
1142 ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1143 VINF_IOM_R3_IOPORT_READ);
1144#else
1145 ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1146 STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
1147 VINF_SUCCESS);
1148#endif
1149 RT_UNTRUSTED_VALIDATED_FENCE();
1150
1151 /* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1152 if ( idxReg >= SVGA_REG_ID_0_TOP
1153 && pThis->svga.u32SVGAId == SVGA_ID_0)
1154 {
1155 idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1156 Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1157 }
1158
1159 switch (idxReg)
1160 {
1161 case SVGA_REG_ID:
1162 STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
1163 *pu32 = pThis->svga.u32SVGAId;
1164 break;
1165
1166 case SVGA_REG_ENABLE:
1167 STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
1168 *pu32 = pThis->svga.fEnabled;
1169 break;
1170
1171 case SVGA_REG_WIDTH:
1172 {
1173 STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
1174 if ( pThis->svga.fEnabled
1175 && pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
1176 *pu32 = pThis->svga.uWidth;
1177 else
1178 {
1179#ifndef IN_RING3
1180 rc = VINF_IOM_R3_IOPORT_READ;
1181#else
1182 *pu32 = pThisCC->pDrv->cx;
1183#endif
1184 }
1185 break;
1186 }
1187
1188 case SVGA_REG_HEIGHT:
1189 {
1190 STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
1191 if ( pThis->svga.fEnabled
1192 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1193 *pu32 = pThis->svga.uHeight;
1194 else
1195 {
1196#ifndef IN_RING3
1197 rc = VINF_IOM_R3_IOPORT_READ;
1198#else
1199 *pu32 = pThisCC->pDrv->cy;
1200#endif
1201 }
1202 break;
1203 }
1204
1205 case SVGA_REG_MAX_WIDTH:
1206 STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
1207 *pu32 = pThis->svga.u32MaxWidth;
1208 break;
1209
1210 case SVGA_REG_MAX_HEIGHT:
1211 STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
1212 *pu32 = pThis->svga.u32MaxHeight;
1213 break;
1214
1215 case SVGA_REG_DEPTH:
1216 /* This returns the color depth of the current mode. */
1217 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
1218 switch (pThis->svga.uBpp)
1219 {
1220 case 15:
1221 case 16:
1222 case 24:
1223 *pu32 = pThis->svga.uBpp;
1224 break;
1225
1226 default:
1227 case 32:
1228 *pu32 = 24; /* The upper 8 bits are either alpha bits or not used. */
1229 break;
1230 }
1231 break;
1232
1233 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1234 STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1235 *pu32 = pThis->svga.uHostBpp;
1236 break;
1237
1238 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1239 STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1240 *pu32 = pThis->svga.uBpp;
1241 break;
1242
1243 case SVGA_REG_PSEUDOCOLOR:
1244 STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1245 *pu32 = pThis->svga.uBpp == 8; /* See section 6 "Pseudocolor" in svga_interface.txt. */
1246 break;
1247
1248 case SVGA_REG_RED_MASK:
1249 case SVGA_REG_GREEN_MASK:
1250 case SVGA_REG_BLUE_MASK:
1251 {
1252 uint32_t uBpp;
1253
1254 if (pThis->svga.fEnabled)
1255 uBpp = pThis->svga.uBpp;
1256 else
1257 uBpp = pThis->svga.uHostBpp;
1258
1259 uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1260 switch (uBpp)
1261 {
1262 case 8:
1263 u32RedMask = 0x07;
1264 u32GreenMask = 0x38;
1265 u32BlueMask = 0xc0;
1266 break;
1267
1268 case 15:
1269 u32RedMask = 0x0000001f;
1270 u32GreenMask = 0x000003e0;
1271 u32BlueMask = 0x00007c00;
1272 break;
1273
1274 case 16:
1275 u32RedMask = 0x0000001f;
1276 u32GreenMask = 0x000007e0;
1277 u32BlueMask = 0x0000f800;
1278 break;
1279
1280 case 24:
1281 case 32:
1282 default:
1283 u32RedMask = 0x00ff0000;
1284 u32GreenMask = 0x0000ff00;
1285 u32BlueMask = 0x000000ff;
1286 break;
1287 }
1288 switch (idxReg)
1289 {
1290 case SVGA_REG_RED_MASK:
1291 STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1292 *pu32 = u32RedMask;
1293 break;
1294
1295 case SVGA_REG_GREEN_MASK:
1296 STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1297 *pu32 = u32GreenMask;
1298 break;
1299
1300 case SVGA_REG_BLUE_MASK:
1301 STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1302 *pu32 = u32BlueMask;
1303 break;
1304 }
1305 break;
1306 }
1307
1308 case SVGA_REG_BYTES_PER_LINE:
1309 {
1310 STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1311 if ( pThis->svga.fEnabled
1312 && pThis->svga.cbScanline)
1313 *pu32 = pThis->svga.cbScanline;
1314 else
1315 {
1316#ifndef IN_RING3
1317 rc = VINF_IOM_R3_IOPORT_READ;
1318#else
1319 *pu32 = pThisCC->pDrv->cbScanline;
1320#endif
1321 }
1322 break;
1323 }
1324
1325 case SVGA_REG_VRAM_SIZE: /* VRAM size */
1326 STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1327 *pu32 = pThis->vram_size;
1328 break;
1329
1330 case SVGA_REG_FB_START: /* Frame buffer physical address. */
1331 STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1332 Assert(pThis->GCPhysVRAM <= 0xffffffff);
1333 *pu32 = pThis->GCPhysVRAM;
1334 break;
1335
1336 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1337 STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1338 /* Always zero in our case. */
1339 *pu32 = 0;
1340 break;
1341
1342 case SVGA_REG_FB_SIZE: /* Frame buffer size */
1343 {
1344#ifndef IN_RING3
1345 rc = VINF_IOM_R3_IOPORT_READ;
1346#else
1347 STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1348
1349 /* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1350 if ( pThis->svga.fEnabled
1351 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1352 {
1353 /* Hardware enabled; return real framebuffer size .*/
1354 *pu32 = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
1355 }
1356 else
1357 *pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy * pThisCC->pDrv->cbScanline);
1358
1359 *pu32 = RT_MIN(pThis->vram_size, *pu32);
1360 Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1361#endif
1362 break;
1363 }
1364
1365 case SVGA_REG_CAPABILITIES:
1366 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1367 *pu32 = pThis->svga.u32DeviceCaps;
1368 break;
1369
1370 case SVGA_REG_MEM_START: /* FIFO start */
1371 STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1372 Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1373 *pu32 = pThis->svga.GCPhysFIFO;
1374 break;
1375
1376 case SVGA_REG_MEM_SIZE: /* FIFO size */
1377 STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1378 *pu32 = pThis->svga.cbFIFO;
1379 break;
1380
1381 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1382 STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1383 *pu32 = pThis->svga.fConfigured;
1384 break;
1385
1386 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1387 STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1388 *pu32 = 0;
1389 break;
1390
1391 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1392 STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1393 if (pThis->svga.fBusy)
1394 {
1395#ifndef IN_RING3
1396 /* Go to ring-3 and halt the CPU. */
1397 rc = VINF_IOM_R3_IOPORT_READ;
1398 RT_NOREF(pDevIns);
1399 break;
1400#else
1401# if defined(VMSVGA_USE_EMT_HALT_CODE)
1402 /* The guest is basically doing a HLT via the device here, but with
1403 a special wake up condition on FIFO completion. */
1404 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1405 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1406 PVM pVM = PDMDevHlpGetVM(pDevIns);
1407 VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1408 VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1409 ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1410 if (pThis->svga.fBusy)
1411 {
1412 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1413 rc = VMR3WaitForDeviceReady(pVM, idCpu);
1414 PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1415 }
1416 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1417 VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1418# else
1419
1420 /* Delay the EMT a bit so the FIFO and others can get some work done.
1421 This used to be a crude 50 ms sleep. The current code tries to be
1422 more efficient, but the consept is still very crude. */
1423 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1424 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1425 RTThreadYield();
1426 if (pThis->svga.fBusy)
1427 {
1428 uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1429
1430 if (pThis->svga.fBusy && cRefs == 1)
1431 RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1432 if (pThis->svga.fBusy)
1433 {
1434 /** @todo If this code is going to stay, we need to call into the halt/wait
1435 * code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1436 * suffer when the guest is polling on a busy FIFO. */
1437 uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns));
1438 if (cNsMaxWait >= RT_NS_100US)
1439 RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1440 RTSEMWAIT_FLAGS_NANOSECS | RTSEMWAIT_FLAGS_RELATIVE | RTSEMWAIT_FLAGS_NORESUME,
1441 RT_MIN(cNsMaxWait, RT_NS_10MS));
1442 }
1443
1444 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1445 }
1446 STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1447# endif
1448 *pu32 = pThis->svga.fBusy != 0;
1449#endif
1450 }
1451 else
1452 *pu32 = false;
1453 break;
1454
1455 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1456 STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1457 *pu32 = pThis->svga.u32GuestId;
1458 break;
1459
1460 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1461 STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1462 *pu32 = pThis->svga.cScratchRegion;
1463 break;
1464
1465 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1466 STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1467 *pu32 = SVGA_FIFO_NUM_REGS;
1468 break;
1469
1470 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1471 STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1472 *pu32 = pThis->svga.u32PitchLock;
1473 break;
1474
1475 case SVGA_REG_IRQMASK: /* Interrupt mask */
1476 STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1477 *pu32 = pThis->svga.u32IrqMask;
1478 break;
1479
1480 /* See "Guest memory regions" below. */
1481 case SVGA_REG_GMR_ID:
1482 STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1483 *pu32 = pThis->svga.u32CurrentGMRId;
1484 break;
1485
1486 case SVGA_REG_GMR_DESCRIPTOR:
1487 STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1488 /* Write only */
1489 *pu32 = 0;
1490 break;
1491
1492 case SVGA_REG_GMR_MAX_IDS:
1493 STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1494 *pu32 = pThis->svga.cGMR;
1495 break;
1496
1497 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1498 STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1499 *pu32 = VMSVGA_MAX_GMR_PAGES;
1500 break;
1501
1502 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1503 STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1504 *pu32 = pThis->svga.fTraces;
1505 break;
1506
1507 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1508 STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1509 *pu32 = VMSVGA_MAX_GMR_PAGES;
1510 break;
1511
1512 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1513 STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1514 *pu32 = VMSVGA_SURFACE_SIZE;
1515 break;
1516
1517 case SVGA_REG_TOP: /* Must be 1 more than the last register */
1518 STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1519 break;
1520
1521 /* Mouse cursor support. */
1522 case SVGA_REG_CURSOR_ID:
1523 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1524 *pu32 = pThis->svga.uCursorID;
1525 break;
1526
1527 case SVGA_REG_CURSOR_X:
1528 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1529 *pu32 = pThis->svga.uCursorX;
1530 break;
1531
1532 case SVGA_REG_CURSOR_Y:
1533 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1534 *pu32 = pThis->svga.uCursorY;
1535 break;
1536
1537 case SVGA_REG_CURSOR_ON:
1538 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1539 *pu32 = pThis->svga.uCursorOn;
1540 break;
1541
1542 /* Legacy multi-monitor support */
1543 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1544 STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1545 *pu32 = 1;
1546 break;
1547
1548 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1549 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1550 *pu32 = 0;
1551 break;
1552
1553 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1554 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1555 *pu32 = 0;
1556 break;
1557
1558 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1559 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1560 *pu32 = 0;
1561 break;
1562
1563 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1564 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1565 *pu32 = 0;
1566 break;
1567
1568 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1569 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1570 *pu32 = pThis->svga.uWidth;
1571 break;
1572
1573 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1574 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1575 *pu32 = pThis->svga.uHeight;
1576 break;
1577
1578 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1579 STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1580 /* We must return something sensible here otherwise the Linux driver
1581 will take a legacy code path without 3d support. This number also
1582 limits how many screens Linux guests will allow. */
1583 *pu32 = pThis->cMonitors;
1584 break;
1585
1586 /*
1587 * SVGA_CAP_GBOBJECTS+ registers.
1588 */
1589 case SVGA_REG_COMMAND_LOW:
1590 /* Lower 32 bits of command buffer physical address. */
1591 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowRd);
1592 *pu32 = pThis->svga.u32RegCommandLow;
1593 break;
1594
1595 case SVGA_REG_COMMAND_HIGH:
1596 /* Upper 32 bits of command buffer PA. */
1597 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighRd);
1598 *pu32 = pThis->svga.u32RegCommandHigh;
1599 break;
1600
1601 case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
1602 /* Max primary (screen) memory. */
1603 STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxPrimBBMemRd);
1604 *pu32 = pThis->vram_size; /** @todo Maybe half VRAM? */
1605 break;
1606
1607 case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
1608 /* Suggested limit on mob mem (i.e. size of the guest mapped VRAM in KB) */
1609 STAM_REL_COUNTER_INC(&pThis->svga.StatRegGBMemSizeRd);
1610 *pu32 = pThis->vram_size / 1024;
1611 break;
1612
1613 case SVGA_REG_DEV_CAP:
1614 /* Write dev cap index, read value */
1615 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapRd);
1616 if (pThis->svga.u32DevCapIndex < RT_ELEMENTS(pThis->svga.au32DevCaps))
1617 {
1618 RT_UNTRUSTED_VALIDATED_FENCE();
1619 *pu32 = pThis->svga.au32DevCaps[pThis->svga.u32DevCapIndex];
1620 }
1621 else
1622 *pu32 = 0;
1623 break;
1624
1625 case SVGA_REG_CMD_PREPEND_LOW:
1626 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowRd);
1627 *pu32 = 0; /* Not supported. */
1628 break;
1629
1630 case SVGA_REG_iCMD_PREPEND_HIGH:
1631 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighRd);
1632 *pu32 = 0; /* Not supported. */
1633 break;
1634
1635 case SVGA_REG_SCREENTARGET_MAX_WIDTH:
1636 STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxWidthRd);
1637 *pu32 = pThis->svga.u32MaxWidth;
1638 break;
1639
1640 case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
1641 STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxHeightRd);
1642 *pu32 = pThis->svga.u32MaxHeight;
1643 break;
1644
1645 case SVGA_REG_MOB_MAX_SIZE:
1646 /* Essentially the max texture size */
1647 STAM_REL_COUNTER_INC(&pThis->svga.StatRegMobMaxSizeRd);
1648 *pu32 = _128M; /** @todo Some actual value. Probably the mapped VRAM size. */
1649 break;
1650
1651 default:
1652 {
1653 uint32_t offReg;
1654 if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1655 {
1656 STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1657 RT_UNTRUSTED_VALIDATED_FENCE();
1658 *pu32 = pThis->svga.au32ScratchRegion[offReg];
1659 }
1660 else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1661 {
1662 /* Note! Using last_palette rather than palette here to preserve the VGA one. */
1663 STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1664 RT_UNTRUSTED_VALIDATED_FENCE();
1665 uint32_t u32 = pThis->last_palette[offReg / 3];
1666 switch (offReg % 3)
1667 {
1668 case 0: *pu32 = (u32 >> 16) & 0xff; break; /* red */
1669 case 1: *pu32 = (u32 >> 8) & 0xff; break; /* green */
1670 case 2: *pu32 = u32 & 0xff; break; /* blue */
1671 }
1672 }
1673 else
1674 {
1675#if !defined(IN_RING3) && defined(VBOX_STRICT)
1676 rc = VINF_IOM_R3_IOPORT_READ;
1677#else
1678 STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1679
1680 /* Do not assert. The guest might be reading all registers. */
1681 LogFunc(("Unknown reg=%#x\n", idxReg));
1682#endif
1683 }
1684 break;
1685 }
1686 }
1687 Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1688 return rc;
1689}
1690
1691#ifdef IN_RING3
1692/**
1693 * Apply the current resolution settings to change the video mode.
1694 *
1695 * @returns VBox status code.
1696 * @param pThis The shared VGA state.
1697 * @param pThisCC The ring-3 VGA state.
1698 */
1699static int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1700{
1701 /* Always do changemode on FIFO thread. */
1702 Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1703
1704 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1705
1706 pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1707
1708 if (pThis->svga.fGFBRegisters)
1709 {
1710 /* "For backwards compatibility, when the GFB mode registers (WIDTH,
1711 * HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1712 * deletes all screens other than screen #0, and redefines screen
1713 * #0 according to the specified mode. Drivers that use
1714 * SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1715 */
1716
1717 VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1718 pScreen->fDefined = true;
1719 pScreen->fModified = true;
1720 pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET | SVGA_SCREEN_IS_PRIMARY;
1721 pScreen->idScreen = 0;
1722 pScreen->xOrigin = 0;
1723 pScreen->yOrigin = 0;
1724 pScreen->offVRAM = 0;
1725 pScreen->cbPitch = pThis->svga.cbScanline;
1726 pScreen->cWidth = pThis->svga.uWidth;
1727 pScreen->cHeight = pThis->svga.uHeight;
1728 pScreen->cBpp = pThis->svga.uBpp;
1729
1730 for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1731 {
1732 /* Delete screen. */
1733 pScreen = &pSVGAState->aScreens[iScreen];
1734 if (pScreen->fDefined)
1735 {
1736 pScreen->fModified = true;
1737 pScreen->fDefined = false;
1738 }
1739 }
1740 }
1741 else
1742 {
1743 /* "If Screen Objects are supported, they can be used to fully
1744 * replace the functionality provided by the framebuffer registers
1745 * (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1746 */
1747 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1748 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1749 pThis->svga.uBpp = pThis->svga.uHostBpp;
1750 }
1751
1752 vmsvgaR3VBVAResize(pThis, pThisCC);
1753
1754 /* Last stuff. For the VGA device screenshot. */
1755 pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1756 pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1757 pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1758 pThis->last_width = pSVGAState->aScreens[0].cWidth;
1759 pThis->last_height = pSVGAState->aScreens[0].cHeight;
1760
1761 /* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1762 if ( pThis->svga.viewport.cx == 0
1763 && pThis->svga.viewport.cy == 0)
1764 {
1765 pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1766 pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1767 pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1768 pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1769 pThis->svga.viewport.yLowWC = 0;
1770 }
1771
1772 return VINF_SUCCESS;
1773}
1774
1775int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1776{
1777 VBVACMDHDR cmd;
1778 cmd.x = (int16_t)(pScreen->xOrigin + x);
1779 cmd.y = (int16_t)(pScreen->yOrigin + y);
1780 cmd.w = (uint16_t)w;
1781 cmd.h = (uint16_t)h;
1782
1783 pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1784 pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1785 pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1786 pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1787
1788 return VINF_SUCCESS;
1789}
1790
1791#endif /* IN_RING3 */
1792#if defined(IN_RING0) || defined(IN_RING3)
1793
1794/**
1795 * Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1796 *
1797 * @param pThis The shared VGA/VMSVGA instance data.
1798 * @param pThisCC The VGA/VMSVGA state for the current context.
1799 * @param fState The busy state.
1800 */
1801DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1802{
1803 ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1804
1805 if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1806 {
1807 /* Race / unfortunately scheduling. Highly unlikly. */
1808 uint32_t cLoops = 64;
1809 do
1810 {
1811 ASMNopPause();
1812 fState = (pThis->svga.fBusy != 0);
1813 ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1814 } while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1815 }
1816}
1817
1818
1819/**
1820 * Update the scanline pitch in response to the guest changing mode
1821 * width/bpp.
1822 *
1823 * @param pThis The shared VGA/VMSVGA state.
1824 * @param pThisCC The VGA/VMSVGA state for the current context.
1825 */
1826DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1827{
1828 uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1829 uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1830 uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1831 uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1832
1833 /* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1834 * it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1835 * location but it has a different meaning.
1836 */
1837 if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1838 uFifoPitchLock = 0;
1839
1840 /* Sanitize values. */
1841 if ((uFifoPitchLock < 200) || (uFifoPitchLock > 32768))
1842 uFifoPitchLock = 0;
1843 if ((uRegPitchLock < 200) || (uRegPitchLock > 32768))
1844 uRegPitchLock = 0;
1845
1846 /* Prefer the register value to the FIFO value.*/
1847 if (uRegPitchLock)
1848 pThis->svga.cbScanline = uRegPitchLock;
1849 else if (uFifoPitchLock)
1850 pThis->svga.cbScanline = uFifoPitchLock;
1851 else
1852 pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1853
1854 if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1855 pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1856}
1857
1858#endif /* IN_RING0 || IN_RING3 */
1859
1860#ifdef IN_RING3
1861
1862/**
1863 * Sends cursor position and visibility information from legacy
1864 * SVGA registers to the front-end.
1865 */
1866static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1867{
1868 /*
1869 * Writing the X/Y/ID registers does not trigger changes; only writing the
1870 * SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1871 * We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1872 * register if they don't have to.
1873 */
1874 uint32_t x, y, idScreen;
1875 uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1876
1877 x = pThis->svga.uCursorX;
1878 y = pThis->svga.uCursorY;
1879 idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1880
1881 /* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1882 * were extended as follows:
1883 *
1884 * SVGA_CURSOR_ON_HIDE 0
1885 * SVGA_CURSOR_ON_SHOW 1
1886 * SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1887 * SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1888 *
1889 * Since we never draw the cursor into the guest's framebuffer, we do not need to
1890 * distinguish between the non-zero values but still remember them.
1891 */
1892 if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1893 {
1894 LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1895 pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1896 }
1897 pThis->svga.uCursorOn = uCursorOn;
1898 pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1899}
1900
1901
1902/**
1903 * Copy a rectangle of pixels within guest VRAM.
1904 */
1905static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1906 uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1907{
1908 if (!width || !height)
1909 return; /* Nothing to do, don't even bother. */
1910
1911 /*
1912 * The guest VRAM (aka GFB) is considered to be a bitmap in the format
1913 * corresponding to the current display mode.
1914 */
1915 uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1916 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1917 uint8_t const *pSrc;
1918 uint8_t *pDst;
1919 unsigned const cbRectWidth = width * cbPixel;
1920 unsigned uMaxOffset;
1921
1922 uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1923 if (uMaxOffset >= cbFrameBuffer)
1924 {
1925 Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1926 return; /* Just don't listen to a bad guest. */
1927 }
1928
1929 pSrc = pDst = pThisCC->pbVRam;
1930 pSrc += srcY * cbScanline + srcX * cbPixel;
1931 pDst += dstY * cbScanline + dstX * cbPixel;
1932
1933 if (srcY >= dstY)
1934 {
1935 /* Source below destination, copy top to bottom. */
1936 for (; height > 0; height--)
1937 {
1938 memmove(pDst, pSrc, cbRectWidth);
1939 pSrc += cbScanline;
1940 pDst += cbScanline;
1941 }
1942 }
1943 else
1944 {
1945 /* Source above destination, copy bottom to top. */
1946 pSrc += cbScanline * (height - 1);
1947 pDst += cbScanline * (height - 1);
1948 for (; height > 0; height--)
1949 {
1950 memmove(pDst, pSrc, cbRectWidth);
1951 pSrc -= cbScanline;
1952 pDst -= cbScanline;
1953 }
1954 }
1955}
1956
1957#endif /* IN_RING3 */
1958
1959
1960/**
1961 * Write port register
1962 *
1963 * @returns Strict VBox status code.
1964 * @param pDevIns The device instance.
1965 * @param pThis The shared VGA/VMSVGA state.
1966 * @param pThisCC The VGA/VMSVGA state for the current context.
1967 * @param u32 Value to write
1968 */
1969static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1970{
1971#ifdef IN_RING3
1972 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1973#endif
1974 VBOXSTRICTRC rc = VINF_SUCCESS;
1975 RT_NOREF(pThisCC);
1976
1977 /* Rough index register validation. */
1978 uint32_t idxReg = pThis->svga.u32IndexReg;
1979#if !defined(IN_RING3) && defined(VBOX_STRICT)
1980 ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1981 VINF_IOM_R3_IOPORT_WRITE);
1982#else
1983 ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1984 STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1985 VINF_SUCCESS);
1986#endif
1987 RT_UNTRUSTED_VALIDATED_FENCE();
1988
1989 /* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1990 if ( idxReg >= SVGA_REG_ID_0_TOP
1991 && pThis->svga.u32SVGAId == SVGA_ID_0)
1992 {
1993 idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1994 Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1995 }
1996 Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1997 /* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1998 switch (idxReg)
1999 {
2000 case SVGA_REG_WIDTH:
2001 case SVGA_REG_HEIGHT:
2002 case SVGA_REG_PITCHLOCK:
2003 case SVGA_REG_BITS_PER_PIXEL:
2004 pThis->svga.fGFBRegisters = true;
2005 break;
2006 default:
2007 break;
2008 }
2009
2010 switch (idxReg)
2011 {
2012 case SVGA_REG_ID:
2013 STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
2014 if ( u32 == SVGA_ID_0
2015 || u32 == SVGA_ID_1
2016 || u32 == SVGA_ID_2)
2017 pThis->svga.u32SVGAId = u32;
2018 else
2019 PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
2020 break;
2021
2022 case SVGA_REG_ENABLE:
2023 STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
2024#ifdef IN_RING3
2025 if ( (u32 & SVGA_REG_ENABLE_ENABLE)
2026 && pThis->svga.fEnabled == false)
2027 {
2028 /* Make a backup copy of the first 512kb in order to save font data etc. */
2029 /** @todo should probably swap here, rather than copy + zero */
2030 memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
2031 memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
2032 }
2033
2034 pThis->svga.fEnabled = u32;
2035 if (pThis->svga.fEnabled)
2036 {
2037 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
2038 && pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
2039 {
2040 /* Keep the current mode. */
2041 pThis->svga.uWidth = pThisCC->pDrv->cx;
2042 pThis->svga.uHeight = pThisCC->pDrv->cy;
2043 pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
2044 }
2045
2046 if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
2047 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
2048 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2049# ifdef LOG_ENABLED
2050 uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2051 Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
2052 Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
2053# endif
2054
2055 /* Disable or enable dirty page tracking according to the current fTraces value. */
2056 vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
2057
2058 /* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
2059 for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
2060 pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /*pHostFlags*/);
2061
2062 /* Make the cursor visible again as needed. */
2063 if (pSVGAState->Cursor.fActive)
2064 pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, false, 0, 0, 0, 0, NULL);
2065 }
2066 else
2067 {
2068 /* Make sure the cursor is off. */
2069 if (pSVGAState->Cursor.fActive)
2070 pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /*fVisible*/, false, 0, 0, 0, 0, NULL);
2071
2072 /* Restore the text mode backup. */
2073 memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
2074
2075 pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
2076
2077 /* Enable dirty page tracking again when going into legacy mode. */
2078 vmsvgaR3SetTraces(pDevIns, pThis, true);
2079
2080 /* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
2081 for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
2082 pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
2083
2084 /* Clear the pitch lock. */
2085 pThis->svga.u32PitchLock = 0;
2086 }
2087#else /* !IN_RING3 */
2088 rc = VINF_IOM_R3_IOPORT_WRITE;
2089#endif /* !IN_RING3 */
2090 break;
2091
2092 case SVGA_REG_WIDTH:
2093 STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
2094 if (pThis->svga.uWidth != u32)
2095 {
2096#if defined(IN_RING3) || defined(IN_RING0)
2097 pThis->svga.uWidth = u32;
2098 vmsvgaHCUpdatePitch(pThis, pThisCC);
2099 if (pThis->svga.fEnabled)
2100 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2101#else
2102 rc = VINF_IOM_R3_IOPORT_WRITE;
2103#endif
2104 }
2105 /* else: nop */
2106 break;
2107
2108 case SVGA_REG_HEIGHT:
2109 STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
2110 if (pThis->svga.uHeight != u32)
2111 {
2112 pThis->svga.uHeight = u32;
2113 if (pThis->svga.fEnabled)
2114 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2115 }
2116 /* else: nop */
2117 break;
2118
2119 case SVGA_REG_DEPTH:
2120 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
2121 /** @todo read-only?? */
2122 break;
2123
2124 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
2125 STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
2126 if (pThis->svga.uBpp != u32)
2127 {
2128#if defined(IN_RING3) || defined(IN_RING0)
2129 pThis->svga.uBpp = u32;
2130 vmsvgaHCUpdatePitch(pThis, pThisCC);
2131 if (pThis->svga.fEnabled)
2132 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2133#else
2134 rc = VINF_IOM_R3_IOPORT_WRITE;
2135#endif
2136 }
2137 /* else: nop */
2138 break;
2139
2140 case SVGA_REG_PSEUDOCOLOR:
2141 STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
2142 break;
2143
2144 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
2145#ifdef IN_RING3
2146 STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
2147 pThis->svga.fConfigured = u32;
2148 /* Disabling the FIFO enables tracing (dirty page detection) by default. */
2149 if (!pThis->svga.fConfigured)
2150 pThis->svga.fTraces = true;
2151 vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
2152#else
2153 rc = VINF_IOM_R3_IOPORT_WRITE;
2154#endif
2155 break;
2156
2157 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
2158 STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
2159 if ( pThis->svga.fEnabled
2160 && pThis->svga.fConfigured)
2161 {
2162#if defined(IN_RING3) || defined(IN_RING0)
2163 Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
2164 /*
2165 * The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
2166 * at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
2167 */
2168 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE | VMSVGA_BUSY_F_FIFO);
2169 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
2170 vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
2171
2172 /* Kick the FIFO thread to start processing commands again. */
2173 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2174#else
2175 rc = VINF_IOM_R3_IOPORT_WRITE;
2176#endif
2177 }
2178 /* else nothing to do. */
2179 else
2180 Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
2181
2182 break;
2183
2184 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
2185 STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
2186 break;
2187
2188 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
2189 STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
2190 pThis->svga.u32GuestId = u32;
2191 break;
2192
2193 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
2194 STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
2195 pThis->svga.u32PitchLock = u32;
2196 /* Should this also update the FIFO pitch lock? Unclear. */
2197 break;
2198
2199 case SVGA_REG_IRQMASK: /* Interrupt mask */
2200 STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
2201 pThis->svga.u32IrqMask = u32;
2202
2203 /* Irq pending after the above change? */
2204 if (pThis->svga.u32IrqStatus & u32)
2205 {
2206 Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
2207 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
2208 }
2209 else
2210 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2211 break;
2212
2213 /* Mouse cursor support */
2214 case SVGA_REG_CURSOR_ID:
2215 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
2216 pThis->svga.uCursorID = u32;
2217 break;
2218
2219 case SVGA_REG_CURSOR_X:
2220 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
2221 pThis->svga.uCursorX = u32;
2222 break;
2223
2224 case SVGA_REG_CURSOR_Y:
2225 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
2226 pThis->svga.uCursorY = u32;
2227 break;
2228
2229 case SVGA_REG_CURSOR_ON:
2230#ifdef IN_RING3
2231 /* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
2232 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
2233 vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
2234#else
2235 rc = VINF_IOM_R3_IOPORT_WRITE;
2236#endif
2237 break;
2238
2239 /* Legacy multi-monitor support */
2240 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
2241 STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
2242 break;
2243 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
2244 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
2245 break;
2246 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
2247 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
2248 break;
2249 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
2250 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
2251 break;
2252 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
2253 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
2254 break;
2255 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
2256 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
2257 break;
2258 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
2259 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
2260 break;
2261#ifdef VBOX_WITH_VMSVGA3D
2262 /* See "Guest memory regions" below. */
2263 case SVGA_REG_GMR_ID:
2264 STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
2265 pThis->svga.u32CurrentGMRId = u32;
2266 break;
2267
2268 case SVGA_REG_GMR_DESCRIPTOR:
2269# ifndef IN_RING3
2270 rc = VINF_IOM_R3_IOPORT_WRITE;
2271 break;
2272# else /* IN_RING3 */
2273 {
2274 STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
2275
2276 /* Validate current GMR id. */
2277 uint32_t idGMR = pThis->svga.u32CurrentGMRId;
2278 AssertBreak(idGMR < pThis->svga.cGMR);
2279 RT_UNTRUSTED_VALIDATED_FENCE();
2280
2281 /* Free the old GMR if present. */
2282 vmsvgaR3GmrFree(pThisCC, idGMR);
2283
2284 /* Just undefine the GMR? */
2285 RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
2286 if (GCPhys == 0)
2287 {
2288 STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
2289 break;
2290 }
2291
2292
2293 /* Never cross a page boundary automatically. */
2294 const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
2295 uint32_t cPagesTotal = 0;
2296 uint32_t iDesc = 0;
2297 PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2298 uint32_t cLoops = 0;
2299 RTGCPHYS GCPhysBase = GCPhys;
2300 while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
2301 {
2302 /* Read descriptor. */
2303 SVGAGuestMemDescriptor desc;
2304 rc = PDMDevHlpPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2305 AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2306
2307 if (desc.numPages != 0)
2308 {
2309 AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2310 cPagesTotal += desc.numPages;
2311 AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2312
2313 if ((iDesc & 15) == 0)
2314 {
2315 void *pvNew = RTMemRealloc(paDescs, (iDesc + 16) * sizeof(VMSVGAGMRDESCRIPTOR));
2316 AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2317 paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2318 }
2319
2320 paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2321 paDescs[iDesc++].numPages = desc.numPages;
2322
2323 /* Continue with the next descriptor. */
2324 GCPhys += sizeof(desc);
2325 }
2326 else if (desc.ppn == 0)
2327 break; /* terminator */
2328 else /* Pointer to the next physical page of descriptors. */
2329 GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2330
2331 cLoops++;
2332 AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2333 }
2334
2335 AssertStmt(iDesc > 0 || RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2336 if (RT_SUCCESS(rc))
2337 {
2338 /* Commit the GMR. */
2339 pSVGAState->paGMR[idGMR].paDesc = paDescs;
2340 pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2341 pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2342 pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
2343 Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
2344 Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2345 idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2346 }
2347 else
2348 {
2349 RTMemFree(paDescs);
2350 STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2351 }
2352 break;
2353 }
2354# endif /* IN_RING3 */
2355#endif // VBOX_WITH_VMSVGA3D
2356
2357 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2358 STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2359 if (pThis->svga.fTraces == u32)
2360 break; /* nothing to do */
2361
2362#ifdef IN_RING3
2363 vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2364#else
2365 rc = VINF_IOM_R3_IOPORT_WRITE;
2366#endif
2367 break;
2368
2369 case SVGA_REG_TOP: /* Must be 1 more than the last register */
2370 STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2371 break;
2372
2373 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2374 STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2375 Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2376 break;
2377
2378 /*
2379 * SVGA_CAP_GBOBJECTS+ registers.
2380 */
2381 case SVGA_REG_COMMAND_LOW:
2382 {
2383 /* Lower 32 bits of command buffer physical address and submit the command buffer. */
2384#ifdef IN_RING3
2385 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowWr);
2386 pThis->svga.u32RegCommandLow = u32;
2387
2388 /* "lower 6 bits are used for the SVGACBContext" */
2389 RTGCPHYS GCPhysCB = pThis->svga.u32RegCommandHigh;
2390 GCPhysCB <<= 32;
2391 GCPhysCB |= pThis->svga.u32RegCommandLow & ~SVGA_CB_CONTEXT_MASK;
2392 SVGACBContext const CBCtx = (SVGACBContext)(pThis->svga.u32RegCommandLow & SVGA_CB_CONTEXT_MASK);
2393 vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, GCPhysCB, CBCtx);
2394#else
2395 rc = VINF_IOM_R3_IOPORT_WRITE;
2396#endif
2397 break;
2398 }
2399
2400 case SVGA_REG_COMMAND_HIGH:
2401 /* Upper 32 bits of command buffer PA. */
2402 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighWr);
2403 pThis->svga.u32RegCommandHigh = u32;
2404 break;
2405
2406 case SVGA_REG_DEV_CAP:
2407 /* Write dev cap index, read value */
2408 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapWr);
2409 pThis->svga.u32DevCapIndex = u32;
2410 break;
2411
2412 case SVGA_REG_CMD_PREPEND_LOW:
2413 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowWr);
2414 /* Not supported. */
2415 break;
2416
2417 case SVGA_REG_iCMD_PREPEND_HIGH:
2418 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighWr);
2419 /* Not supported. */
2420 break;
2421
2422 case SVGA_REG_FB_START:
2423 case SVGA_REG_MEM_START:
2424 case SVGA_REG_HOST_BITS_PER_PIXEL:
2425 case SVGA_REG_MAX_WIDTH:
2426 case SVGA_REG_MAX_HEIGHT:
2427 case SVGA_REG_VRAM_SIZE:
2428 case SVGA_REG_FB_SIZE:
2429 case SVGA_REG_CAPABILITIES:
2430 case SVGA_REG_MEM_SIZE:
2431 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2432 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2433 case SVGA_REG_BYTES_PER_LINE:
2434 case SVGA_REG_FB_OFFSET:
2435 case SVGA_REG_RED_MASK:
2436 case SVGA_REG_GREEN_MASK:
2437 case SVGA_REG_BLUE_MASK:
2438 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2439 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2440 case SVGA_REG_GMR_MAX_IDS:
2441 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2442 case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
2443 case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
2444 case SVGA_REG_SCREENTARGET_MAX_WIDTH:
2445 case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
2446 case SVGA_REG_MOB_MAX_SIZE:
2447 /* Read only - ignore. */
2448 Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2449 STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2450 break;
2451
2452 default:
2453 {
2454 uint32_t offReg;
2455 if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2456 {
2457 RT_UNTRUSTED_VALIDATED_FENCE();
2458 pThis->svga.au32ScratchRegion[offReg] = u32;
2459 STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2460 }
2461 else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2462 {
2463 /* Note! Using last_palette rather than palette here to preserve the VGA one.
2464 Btw, see rgb_to_pixel32. */
2465 STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2466 u32 &= 0xff;
2467 RT_UNTRUSTED_VALIDATED_FENCE();
2468 uint32_t uRgb = pThis->last_palette[offReg / 3];
2469 switch (offReg % 3)
2470 {
2471 case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) | (u32 << 16); break; /* red */
2472 case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) | (u32 << 8); break; /* green */
2473 case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) | u32 ; break; /* blue */
2474 }
2475 pThis->last_palette[offReg / 3] = uRgb;
2476 }
2477 else
2478 {
2479#if !defined(IN_RING3) && defined(VBOX_STRICT)
2480 rc = VINF_IOM_R3_IOPORT_WRITE;
2481#else
2482 STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2483 AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2484#endif
2485 }
2486 break;
2487 }
2488 }
2489 return rc;
2490}
2491
2492/**
2493 * @callback_method_impl{FNIOMIOPORTNEWIN}
2494 */
2495DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2496{
2497 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2498 RT_NOREF_PV(pvUser);
2499
2500 /* Only dword accesses. */
2501 if (cb == 4)
2502 {
2503 switch (offPort)
2504 {
2505 case SVGA_INDEX_PORT:
2506 *pu32 = pThis->svga.u32IndexReg;
2507 break;
2508
2509 case SVGA_VALUE_PORT:
2510 return vmsvgaReadPort(pDevIns, pThis, pu32);
2511
2512 case SVGA_BIOS_PORT:
2513 Log(("Ignoring BIOS port read\n"));
2514 *pu32 = 0;
2515 break;
2516
2517 case SVGA_IRQSTATUS_PORT:
2518 LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2519 *pu32 = pThis->svga.u32IrqStatus;
2520 break;
2521
2522 default:
2523 ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2524 *pu32 = UINT32_MAX;
2525 break;
2526 }
2527 }
2528 else
2529 {
2530 Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2531 *pu32 = UINT32_MAX;
2532 }
2533 return VINF_SUCCESS;
2534}
2535
2536/**
2537 * @callback_method_impl{FNIOMIOPORTNEWOUT}
2538 */
2539DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2540{
2541 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2542 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2543 RT_NOREF_PV(pvUser);
2544
2545 /* Only dword accesses. */
2546 if (cb == 4)
2547 switch (offPort)
2548 {
2549 case SVGA_INDEX_PORT:
2550 pThis->svga.u32IndexReg = u32;
2551 break;
2552
2553 case SVGA_VALUE_PORT:
2554 return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2555
2556 case SVGA_BIOS_PORT:
2557 Log(("Ignoring BIOS port write (val=%x)\n", u32));
2558 break;
2559
2560 case SVGA_IRQSTATUS_PORT:
2561 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2562 ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2563 /* Clear the irq in case all events have been cleared. */
2564 if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2565 {
2566 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2567 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2568 }
2569 break;
2570
2571 default:
2572 ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2573 break;
2574 }
2575 else
2576 Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2577
2578 return VINF_SUCCESS;
2579}
2580
2581#ifdef IN_RING3
2582
2583# ifdef DEBUG_FIFO_ACCESS
2584/**
2585 * Handle FIFO memory access.
2586 * @returns VBox status code.
2587 * @param pVM VM handle.
2588 * @param pThis The shared VGA/VMSVGA instance data.
2589 * @param GCPhys The access physical address.
2590 * @param fWriteAccess Read or write access
2591 */
2592static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2593{
2594 RT_NOREF(pVM);
2595 RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2596 uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2597
2598 switch (GCPhysOffset >> 2)
2599 {
2600 case SVGA_FIFO_MIN:
2601 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2602 break;
2603 case SVGA_FIFO_MAX:
2604 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2605 break;
2606 case SVGA_FIFO_NEXT_CMD:
2607 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2608 break;
2609 case SVGA_FIFO_STOP:
2610 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2611 break;
2612 case SVGA_FIFO_CAPABILITIES:
2613 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2614 break;
2615 case SVGA_FIFO_FLAGS:
2616 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2617 break;
2618 case SVGA_FIFO_FENCE:
2619 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2620 break;
2621 case SVGA_FIFO_3D_HWVERSION:
2622 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2623 break;
2624 case SVGA_FIFO_PITCHLOCK:
2625 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2626 break;
2627 case SVGA_FIFO_CURSOR_ON:
2628 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2629 break;
2630 case SVGA_FIFO_CURSOR_X:
2631 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2632 break;
2633 case SVGA_FIFO_CURSOR_Y:
2634 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2635 break;
2636 case SVGA_FIFO_CURSOR_COUNT:
2637 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2638 break;
2639 case SVGA_FIFO_CURSOR_LAST_UPDATED:
2640 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2641 break;
2642 case SVGA_FIFO_RESERVED:
2643 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2644 break;
2645 case SVGA_FIFO_CURSOR_SCREEN_ID:
2646 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2647 break;
2648 case SVGA_FIFO_DEAD:
2649 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2650 break;
2651 case SVGA_FIFO_3D_HWVERSION_REVISED:
2652 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2653 break;
2654 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2655 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2656 break;
2657 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2658 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2659 break;
2660 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2661 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2662 break;
2663 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2664 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2665 break;
2666 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2667 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2668 break;
2669 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2670 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2671 break;
2672 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2673 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2674 break;
2675 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2676 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2677 break;
2678 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2679 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2680 break;
2681 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2682 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2683 break;
2684 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2685 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2686 break;
2687 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2688 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2689 break;
2690 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2691 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2692 break;
2693 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2694 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2695 break;
2696 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2697 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2698 break;
2699 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2700 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2701 break;
2702 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2703 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2704 break;
2705 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2706 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2707 break;
2708 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2709 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2710 break;
2711 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2712 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2713 break;
2714 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2715 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2716 break;
2717 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2718 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2719 break;
2720 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2721 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2722 break;
2723 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2724 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2725 break;
2726 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2727 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2728 break;
2729 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2730 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2731 break;
2732 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2733 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2734 break;
2735 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2736 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2737 break;
2738 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2739 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2740 break;
2741 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2742 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2743 break;
2744 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2745 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2746 break;
2747 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2748 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2749 break;
2750 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2751 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2752 break;
2753 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2754 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2755 break;
2756 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2757 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2758 break;
2759 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2760 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2761 break;
2762 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2763 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2764 break;
2765 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2766 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2767 break;
2768 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2769 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2770 break;
2771 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2772 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2773 break;
2774 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2775 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2776 break;
2777 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2778 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2779 break;
2780 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2781 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2782 break;
2783 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2784 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2785 break;
2786 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2787 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2788 break;
2789 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2790 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2791 break;
2792 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2793 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2794 break;
2795 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2796 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2797 break;
2798 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2799 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2800 break;
2801 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2802 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2803 break;
2804 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2805 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2806 break;
2807 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2808 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2809 break;
2810 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2811 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2812 break;
2813 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2814 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2815 break;
2816 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2817 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2818 break;
2819 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2820 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2821 break;
2822 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2823 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2824 break;
2825 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2826 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2827 break;
2828 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2829 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2830 break;
2831 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2832 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2833 break;
2834 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2835 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2836 break;
2837 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2838 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2839 break;
2840 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2841 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2842 break;
2843 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2844 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2845 break;
2846 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2847 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2848 break;
2849 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2850 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2851 break;
2852 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2853 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2854 break;
2855 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2856 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2857 break;
2858 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2859 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2860 break;
2861 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2862 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2863 break;
2864 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2865 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2866 break;
2867 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2868 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2869 break;
2870 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2871 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2872 break;
2873 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2874 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2875 break;
2876 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2877 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2878 break;
2879 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2880 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2881 break;
2882 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2883 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2884 break;
2885 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2886 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2887 break;
2888 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2889 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2890 break;
2891 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2892 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2893 break;
2894 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2895 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2896 break;
2897 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI1:
2898 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2899 break;
2900 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI2:
2901 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2902 break;
2903 case SVGA_FIFO_3D_CAPS_LAST:
2904 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2905 break;
2906 case SVGA_FIFO_GUEST_3D_HWVERSION:
2907 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2908 break;
2909 case SVGA_FIFO_FENCE_GOAL:
2910 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2911 break;
2912 case SVGA_FIFO_BUSY:
2913 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2914 break;
2915 default:
2916 Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2917 break;
2918 }
2919
2920 return VINF_EM_RAW_EMULATE_INSTR;
2921}
2922# endif /* DEBUG_FIFO_ACCESS */
2923
2924# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
2925/**
2926 * HC access handler for the FIFO.
2927 *
2928 * @returns VINF_SUCCESS if the handler have carried out the operation.
2929 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2930 * @param pVM VM Handle.
2931 * @param pVCpu The cross context CPU structure for the calling EMT.
2932 * @param GCPhys The physical address the guest is writing to.
2933 * @param pvPhys The HC mapping of that address.
2934 * @param pvBuf What the guest is reading/writing.
2935 * @param cbBuf How much it's reading/writing.
2936 * @param enmAccessType The access type.
2937 * @param enmOrigin Who is making the access.
2938 * @param pvUser User argument.
2939 */
2940static DECLCALLBACK(VBOXSTRICTRC)
2941vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
2942 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2943{
2944 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2945 PVGASTATE pThis = (PVGASTATE)pvUser;
2946 AssertPtr(pThis);
2947
2948# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2949 /*
2950 * Wake up the FIFO thread as it might have work to do now.
2951 */
2952 int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2953 AssertLogRelRC(rc);
2954# endif
2955
2956# ifdef DEBUG_FIFO_ACCESS
2957 /*
2958 * When in debug-fifo-access mode, we do not disable the access handler,
2959 * but leave it on as we wish to catch all access.
2960 */
2961 Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2962 rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2963# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2964 /*
2965 * Temporarily disable the access handler now that we've kicked the FIFO thread.
2966 */
2967 STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2968 rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2969# endif
2970 if (RT_SUCCESS(rc))
2971 return VINF_PGM_HANDLER_DO_DEFAULT;
2972 AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2973 return rc;
2974}
2975# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER || DEBUG_FIFO_ACCESS */
2976
2977#endif /* IN_RING3 */
2978
2979#ifdef DEBUG_GMR_ACCESS
2980# ifdef IN_RING3
2981
2982/**
2983 * HC access handler for the FIFO.
2984 *
2985 * @returns VINF_SUCCESS if the handler have carried out the operation.
2986 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2987 * @param pVM VM Handle.
2988 * @param pVCpu The cross context CPU structure for the calling EMT.
2989 * @param GCPhys The physical address the guest is writing to.
2990 * @param pvPhys The HC mapping of that address.
2991 * @param pvBuf What the guest is reading/writing.
2992 * @param cbBuf How much it's reading/writing.
2993 * @param enmAccessType The access type.
2994 * @param enmOrigin Who is making the access.
2995 * @param pvUser User argument.
2996 */
2997static DECLCALLBACK(VBOXSTRICTRC)
2998vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
2999 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
3000{
3001 PVGASTATE pThis = (PVGASTATE)pvUser;
3002 Assert(pThis);
3003 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3004 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
3005
3006 Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
3007
3008 for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
3009 {
3010 PGMR pGMR = &pSVGAState->paGMR[i];
3011
3012 if (pGMR->numDescriptors)
3013 {
3014 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
3015 {
3016 if ( GCPhys >= pGMR->paDesc[j].GCPhys
3017 && GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
3018 {
3019 /*
3020 * Turn off the write handler for this particular page and make it R/W.
3021 * Then return telling the caller to restart the guest instruction.
3022 */
3023 int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
3024 AssertRC(rc);
3025 return VINF_PGM_HANDLER_DO_DEFAULT;
3026 }
3027 }
3028 }
3029 }
3030
3031 return VINF_PGM_HANDLER_DO_DEFAULT;
3032}
3033
3034/** Callback handler for VMR3ReqCallWaitU */
3035static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
3036{
3037 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3038 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3039 PGMR pGMR = &pSVGAState->paGMR[gmrId];
3040 int rc;
3041
3042 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3043 {
3044 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
3045 pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
3046 pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
3047 AssertRC(rc);
3048 }
3049 return VINF_SUCCESS;
3050}
3051
3052/** Callback handler for VMR3ReqCallWaitU */
3053static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
3054{
3055 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3056 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3057 PGMR pGMR = &pSVGAState->paGMR[gmrId];
3058
3059 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3060 {
3061 int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
3062 AssertRC(rc);
3063 }
3064 return VINF_SUCCESS;
3065}
3066
3067/** Callback handler for VMR3ReqCallWaitU */
3068static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
3069{
3070 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3071
3072 for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
3073 {
3074 PGMR pGMR = &pSVGAState->paGMR[i];
3075
3076 if (pGMR->numDescriptors)
3077 {
3078 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
3079 {
3080 int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
3081 AssertRC(rc);
3082 }
3083 }
3084 }
3085 return VINF_SUCCESS;
3086}
3087
3088# endif /* IN_RING3 */
3089#endif /* DEBUG_GMR_ACCESS */
3090
3091/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
3092
3093#ifdef IN_RING3
3094
3095
3096/**
3097 * Common worker for changing the pointer shape.
3098 *
3099 * @param pThisCC The VGA/VMSVGA state for ring-3.
3100 * @param pSVGAState The VMSVGA ring-3 instance data.
3101 * @param fAlpha Whether there is alpha or not.
3102 * @param xHot Hotspot x coordinate.
3103 * @param yHot Hotspot y coordinate.
3104 * @param cx Width.
3105 * @param cy Height.
3106 * @param pbData Heap copy of the cursor data. Consumed.
3107 * @param cbData The size of the data.
3108 */
3109static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
3110 uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
3111{
3112 LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
3113# ifdef LOG_ENABLED
3114 if (LogIs2Enabled())
3115 {
3116 uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
3117 if (!fAlpha)
3118 {
3119 Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
3120 for (uint32_t y = 0; y < cy; y++)
3121 {
3122 Log2(("%3u:", y));
3123 uint8_t const *pbLine = &pbData[y * cbAndLine];
3124 for (uint32_t x = 0; x < cx; x += 8)
3125 {
3126 uint8_t b = pbLine[x / 8];
3127 char szByte[12];
3128 szByte[0] = b & 0x80 ? '*' : ' '; /* most significant bit first */
3129 szByte[1] = b & 0x40 ? '*' : ' ';
3130 szByte[2] = b & 0x20 ? '*' : ' ';
3131 szByte[3] = b & 0x10 ? '*' : ' ';
3132 szByte[4] = b & 0x08 ? '*' : ' ';
3133 szByte[5] = b & 0x04 ? '*' : ' ';
3134 szByte[6] = b & 0x02 ? '*' : ' ';
3135 szByte[7] = b & 0x01 ? '*' : ' ';
3136 szByte[8] = '\0';
3137 Log2(("%s", szByte));
3138 }
3139 Log2(("\n"));
3140 }
3141 }
3142
3143 Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
3144 uint32_t const *pu32Xor = (uint32_t const *)&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
3145 for (uint32_t y = 0; y < cy; y++)
3146 {
3147 Log2(("%3u:", y));
3148 uint32_t const *pu32Line = &pu32Xor[y * cx];
3149 for (uint32_t x = 0; x < cx; x++)
3150 Log2((" %08x", pu32Line[x]));
3151 Log2(("\n"));
3152 }
3153 }
3154# endif
3155
3156 int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, fAlpha, xHot, yHot, cx, cy, pbData);
3157 AssertRC(rc);
3158
3159 if (pSVGAState->Cursor.fActive)
3160 RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
3161
3162 pSVGAState->Cursor.fActive = true;
3163 pSVGAState->Cursor.xHotspot = xHot;
3164 pSVGAState->Cursor.yHotspot = yHot;
3165 pSVGAState->Cursor.width = cx;
3166 pSVGAState->Cursor.height = cy;
3167 pSVGAState->Cursor.cbData = cbData;
3168 pSVGAState->Cursor.pData = pbData;
3169}
3170
3171
3172# ifdef VBOX_WITH_VMSVGA3D
3173/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
3174 * Check that the 3D command has at least a_cbMin of payload bytes after the
3175 * header. Will break out of the switch if it doesn't.
3176 */
3177# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3178 if (1) { \
3179 AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
3180 RT_UNTRUSTED_VALIDATED_FENCE(); \
3181 } else do {} while (0)
3182
3183/** SVGA_3D_CMD_* handler.
3184 *
3185 * @param pThis The shared VGA/VMSVGA state.
3186 * @param pThisCC The VGA/VMSVGA state for the current context.
3187 * @param cmdId SVGA_3D_CMD_* command identifier.
3188 * @param cbCmd Size of the command in bytes.
3189 * @param pvCmd Pointer to the command.
3190 */
3191static int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t cmdId, uint32_t cbCmd, void const *pvCmd)
3192{
3193 int rc = VINF_SUCCESS;
3194 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3195
3196 switch (cmdId)
3197 {
3198 case SVGA_3D_CMD_SURFACE_DEFINE:
3199 {
3200 uint32_t cMipLevels;
3201 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)pvCmd;
3202 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3203 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
3204
3205 cMipLevels = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3206 rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
3207 SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
3208# ifdef DEBUG_GMR_ACCESS
3209 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
3210# endif
3211 break;
3212 }
3213
3214 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3215 {
3216 uint32_t cMipLevels;
3217 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)pvCmd;
3218 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3219 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
3220
3221 cMipLevels = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3222 rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
3223 pCmd->multisampleCount, pCmd->autogenFilter,
3224 cMipLevels, (SVGA3dSize *)(pCmd + 1));
3225 break;
3226 }
3227
3228 case SVGA_3D_CMD_SURFACE_DESTROY:
3229 {
3230 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)pvCmd;
3231 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3232 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
3233 rc = vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
3234 break;
3235 }
3236
3237 case SVGA_3D_CMD_SURFACE_COPY:
3238 {
3239 uint32_t cCopyBoxes;
3240 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)pvCmd;
3241 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3242 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
3243
3244 cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3245 rc = vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3246 break;
3247 }
3248
3249 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3250 {
3251 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)pvCmd;
3252 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3253 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
3254
3255 rc = vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
3256 &pCmd->src, &pCmd->boxSrc, pCmd->mode);
3257 break;
3258 }
3259
3260 case SVGA_3D_CMD_SURFACE_DMA:
3261 {
3262 uint32_t cCopyBoxes;
3263 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)pvCmd;
3264 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3265 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
3266
3267 uint64_t u64NanoTS = 0;
3268 if (LogRelIs3Enabled())
3269 u64NanoTS = RTTimeNanoTS();
3270 cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3271 STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
3272 rc = vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
3273 cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3274 STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
3275 if (LogRelIs3Enabled())
3276 {
3277 if (cCopyBoxes)
3278 {
3279 SVGA3dCopyBox *pFirstBox = (SVGA3dCopyBox *)(pCmd + 1);
3280 LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
3281 (RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
3282 pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
3283 pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
3284 }
3285 }
3286 break;
3287 }
3288
3289 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3290 {
3291 uint32_t cRects;
3292 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)pvCmd;
3293 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3294 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
3295
3296 static uint64_t u64FrameStartNanoTS = 0;
3297 static uint64_t u64ElapsedPerSecNano = 0;
3298 static int cFrames = 0;
3299 uint64_t u64NanoTS = 0;
3300 if (LogRelIs3Enabled())
3301 u64NanoTS = RTTimeNanoTS();
3302 cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3303 STAM_REL_PROFILE_START(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
3304 rc = vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
3305 pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3306 STAM_REL_PROFILE_STOP(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
3307 if (LogRelIs3Enabled())
3308 {
3309 uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
3310 u64ElapsedPerSecNano += u64ElapsedNano;
3311
3312 SVGASignedRect *pFirstRect = cRects ? (SVGASignedRect *)(pCmd + 1) : &pCmd->destRect;
3313 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
3314 (u64ElapsedNano) / 1000ULL, cRects,
3315 pFirstRect->left, pFirstRect->top,
3316 pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
3317
3318 ++cFrames;
3319 if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
3320 {
3321 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
3322 cFrames, u64ElapsedPerSecNano / 1000ULL));
3323 u64FrameStartNanoTS = u64NanoTS;
3324 cFrames = 0;
3325 u64ElapsedPerSecNano = 0;
3326 }
3327 }
3328 break;
3329 }
3330
3331 case SVGA_3D_CMD_CONTEXT_DEFINE:
3332 {
3333 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)pvCmd;
3334 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3335 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
3336
3337 rc = vmsvga3dContextDefine(pThisCC, pCmd->cid);
3338 break;
3339 }
3340
3341 case SVGA_3D_CMD_CONTEXT_DESTROY:
3342 {
3343 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)pvCmd;
3344 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3345 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
3346
3347 rc = vmsvga3dContextDestroy(pThisCC, pCmd->cid);
3348 break;
3349 }
3350
3351 case SVGA_3D_CMD_SETTRANSFORM:
3352 {
3353 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)pvCmd;
3354 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3355 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
3356
3357 rc = vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
3358 break;
3359 }
3360
3361 case SVGA_3D_CMD_SETZRANGE:
3362 {
3363 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)pvCmd;
3364 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3365 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
3366
3367 rc = vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
3368 break;
3369 }
3370
3371 case SVGA_3D_CMD_SETRENDERSTATE:
3372 {
3373 uint32_t cRenderStates;
3374 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)pvCmd;
3375 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3376 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
3377
3378 cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3379 rc = vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3380 break;
3381 }
3382
3383 case SVGA_3D_CMD_SETRENDERTARGET:
3384 {
3385 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)pvCmd;
3386 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3387 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
3388
3389 rc = vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
3390 break;
3391 }
3392
3393 case SVGA_3D_CMD_SETTEXTURESTATE:
3394 {
3395 uint32_t cTextureStates;
3396 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)pvCmd;
3397 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3398 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
3399
3400 cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3401 rc = vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3402 break;
3403 }
3404
3405 case SVGA_3D_CMD_SETMATERIAL:
3406 {
3407 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)pvCmd;
3408 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3409 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
3410
3411 rc = vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
3412 break;
3413 }
3414
3415 case SVGA_3D_CMD_SETLIGHTDATA:
3416 {
3417 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)pvCmd;
3418 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3419 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
3420
3421 rc = vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
3422 break;
3423 }
3424
3425 case SVGA_3D_CMD_SETLIGHTENABLED:
3426 {
3427 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)pvCmd;
3428 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3429 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
3430
3431 rc = vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
3432 break;
3433 }
3434
3435 case SVGA_3D_CMD_SETVIEWPORT:
3436 {
3437 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)pvCmd;
3438 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3439 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
3440
3441 rc = vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
3442 break;
3443 }
3444
3445 case SVGA_3D_CMD_SETCLIPPLANE:
3446 {
3447 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)pvCmd;
3448 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3449 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
3450
3451 rc = vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
3452 break;
3453 }
3454
3455 case SVGA_3D_CMD_CLEAR:
3456 {
3457 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)pvCmd;
3458 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3459 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
3460
3461 uint32_t cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
3462 rc = vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
3463 break;
3464 }
3465
3466 case SVGA_3D_CMD_PRESENT:
3467 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
3468 {
3469 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)pvCmd;
3470 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3471 if (cmdId == SVGA_3D_CMD_PRESENT)
3472 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
3473 else
3474 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
3475
3476 uint32_t cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
3477
3478 STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
3479 rc = vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
3480 STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
3481 break;
3482 }
3483
3484 case SVGA_3D_CMD_SHADER_DEFINE:
3485 {
3486 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)pvCmd;
3487 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3488 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
3489
3490 uint32_t cbData = (cbCmd - sizeof(*pCmd));
3491 rc = vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
3492 break;
3493 }
3494
3495 case SVGA_3D_CMD_SHADER_DESTROY:
3496 {
3497 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)pvCmd;
3498 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3499 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
3500
3501 rc = vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
3502 break;
3503 }
3504
3505 case SVGA_3D_CMD_SET_SHADER:
3506 {
3507 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)pvCmd;
3508 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3509 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
3510
3511 rc = vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
3512 break;
3513 }
3514
3515 case SVGA_3D_CMD_SET_SHADER_CONST:
3516 {
3517 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)pvCmd;
3518 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3519 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
3520
3521 uint32_t cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
3522 rc = vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
3523 break;
3524 }
3525
3526 case SVGA_3D_CMD_DRAW_PRIMITIVES:
3527 {
3528 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)pvCmd;
3529 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3530 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
3531
3532 AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
3533 AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
3534 uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
3535 + pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
3536 ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd));
3537
3538 uint32_t cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
3539 AssertBreak(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls);
3540
3541 RT_UNTRUSTED_VALIDATED_FENCE();
3542
3543 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
3544 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *)&pVertexDecl[pCmd->numVertexDecls];
3545 SVGA3dVertexDivisor *pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor *)&pNumRange[pCmd->numRanges] : NULL;
3546
3547 STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
3548 rc = vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
3549 pNumRange, cVertexDivisor, pVertexDivisor);
3550 STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
3551 break;
3552 }
3553
3554 case SVGA_3D_CMD_SETSCISSORRECT:
3555 {
3556 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)pvCmd;
3557 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3558 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
3559
3560 rc = vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
3561 break;
3562 }
3563
3564 case SVGA_3D_CMD_BEGIN_QUERY:
3565 {
3566 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)pvCmd;
3567 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3568 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
3569
3570 rc = vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
3571 break;
3572 }
3573
3574 case SVGA_3D_CMD_END_QUERY:
3575 {
3576 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)pvCmd;
3577 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3578 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
3579
3580 rc = vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
3581 break;
3582 }
3583
3584 case SVGA_3D_CMD_WAIT_FOR_QUERY:
3585 {
3586 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)pvCmd;
3587 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3588 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
3589
3590 rc = vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
3591 break;
3592 }
3593
3594 case SVGA_3D_CMD_GENERATE_MIPMAPS:
3595 {
3596 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)pvCmd;
3597 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3598 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
3599
3600 rc = vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
3601 break;
3602 }
3603
3604 case SVGA_3D_CMD_ACTIVATE_SURFACE:
3605 /* context id + surface id? */
3606 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
3607 break;
3608 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
3609 /* context id + surface id? */
3610 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
3611 break;
3612
3613 default:
3614 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3615 AssertMsgFailed(("cmdId=%d\n", cmdId));
3616 break;
3617 }
3618
3619 return rc;
3620}
3621# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
3622# endif // VBOX_WITH_VMSVGA3D
3623
3624
3625/*
3626 *
3627 * Handlers for FIFO commands.
3628 *
3629 * Every handler takes the following parameters:
3630 *
3631 * pThis The shared VGA/VMSVGA state.
3632 * pThisCC The VGA/VMSVGA state for ring-3.
3633 * pCmd The command data.
3634 */
3635
3636
3637/* SVGA_CMD_UPDATE */
3638static void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
3639{
3640 RT_NOREF(pThis);
3641 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3642
3643 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
3644 Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
3645
3646 /** @todo Multiple screens? */
3647 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
3648 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
3649 return;
3650
3651 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
3652}
3653
3654
3655/* SVGA_CMD_UPDATE_VERBOSE */
3656static void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
3657{
3658 RT_NOREF(pThis);
3659 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3660
3661 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
3662 Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
3663
3664 /** @todo Multiple screens? */
3665 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
3666 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
3667 return;
3668
3669 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
3670}
3671
3672
3673/* SVGA_CMD_RECT_FILL */
3674static void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
3675{
3676 RT_NOREF(pThis, pCmd);
3677 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3678
3679 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
3680 Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
3681 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
3682}
3683
3684
3685/* SVGA_CMD_RECT_COPY */
3686static void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
3687{
3688 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3689
3690 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
3691 Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
3692
3693 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
3694 AssertPtrReturnVoid(pScreen);
3695
3696 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
3697 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
3698 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
3699 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
3700 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
3701 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
3702 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
3703
3704 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
3705 pCmd->width, pCmd->height, pThis->vram_size);
3706 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
3707}
3708
3709
3710/* SVGA_CMD_RECT_ROP_COPY */
3711static void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
3712{
3713 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3714
3715 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
3716 Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
3717
3718 if (pCmd->rop != SVGA_ROP_COPY)
3719 {
3720 /* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
3721 * as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
3722 * respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
3723 * SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
3724 */
3725 LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
3726 pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
3727 return;
3728 }
3729
3730 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
3731 AssertPtrReturnVoid(pScreen);
3732
3733 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
3734 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
3735 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
3736 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
3737 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
3738 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
3739 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
3740
3741 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
3742 pCmd->width, pCmd->height, pThis->vram_size);
3743 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
3744}
3745
3746
3747/* SVGA_CMD_DISPLAY_CURSOR */
3748static void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
3749{
3750 RT_NOREF(pThis, pCmd);
3751 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3752
3753 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
3754 Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
3755 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
3756}
3757
3758
3759/* SVGA_CMD_MOVE_CURSOR */
3760static void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
3761{
3762 RT_NOREF(pThis, pCmd);
3763 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3764
3765 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
3766 Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
3767 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
3768}
3769
3770
3771/* SVGA_CMD_DEFINE_CURSOR */
3772static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
3773{
3774 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3775
3776 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
3777 Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3778 pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
3779
3780 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
3781 ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
3782 ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
3783 RT_UNTRUSTED_VALIDATED_FENCE();
3784
3785 uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
3786 uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
3787 uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
3788
3789 uint8_t const *pbSrcAndMask = (uint8_t const *)(pCmd + 1);
3790 uint8_t const *pbSrcXorMask = (uint8_t const *)(pCmd + 1) + cbSrcAndMask;
3791
3792 uint32_t const cx = pCmd->width;
3793 uint32_t const cy = pCmd->height;
3794
3795 /*
3796 * Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
3797 * The AND data uses 8-bit aligned scanlines.
3798 * The XOR data must be starting on a 32-bit boundrary.
3799 */
3800 uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
3801 uint32_t cbDstAndMask = cbDstAndLine * cy;
3802 uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
3803 uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
3804
3805 uint8_t *pbCopy = (uint8_t *)RTMemAlloc(cbCopy);
3806 AssertReturnVoid(pbCopy);
3807
3808 /* Convert the AND mask. */
3809 uint8_t *pbDst = pbCopy;
3810 uint8_t const *pbSrc = pbSrcAndMask;
3811 switch (pCmd->andMaskDepth)
3812 {
3813 case 1:
3814 if (cbSrcAndLine == cbDstAndLine)
3815 memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
3816 else
3817 {
3818 Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
3819 for (uint32_t y = 0; y < cy; y++)
3820 {
3821 memcpy(pbDst, pbSrc, cbDstAndLine);
3822 pbDst += cbDstAndLine;
3823 pbSrc += cbSrcAndLine;
3824 }
3825 }
3826 break;
3827 /* Should take the XOR mask into account for the multi-bit AND mask. */
3828 case 8:
3829 for (uint32_t y = 0; y < cy; y++)
3830 {
3831 for (uint32_t x = 0; x < cx; )
3832 {
3833 uint8_t bDst = 0;
3834 uint8_t fBit = 0x80;
3835 do
3836 {
3837 uintptr_t const idxPal = pbSrc[x] * 3;
3838 if ((( pThis->last_palette[idxPal]
3839 | (pThis->last_palette[idxPal] >> 8)
3840 | (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
3841 bDst |= fBit;
3842 fBit >>= 1;
3843 x++;
3844 } while (x < cx && (x & 7));
3845 pbDst[(x - 1) / 8] = bDst;
3846 }
3847 pbDst += cbDstAndLine;
3848 pbSrc += cbSrcAndLine;
3849 }
3850 break;
3851 case 15:
3852 for (uint32_t y = 0; y < cy; y++)
3853 {
3854 for (uint32_t x = 0; x < cx; )
3855 {
3856 uint8_t bDst = 0;
3857 uint8_t fBit = 0x80;
3858 do
3859 {
3860 if ((pbSrc[x * 2] | (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
3861 bDst |= fBit;
3862 fBit >>= 1;
3863 x++;
3864 } while (x < cx && (x & 7));
3865 pbDst[(x - 1) / 8] = bDst;
3866 }
3867 pbDst += cbDstAndLine;
3868 pbSrc += cbSrcAndLine;
3869 }
3870 break;
3871 case 16:
3872 for (uint32_t y = 0; y < cy; y++)
3873 {
3874 for (uint32_t x = 0; x < cx; )
3875 {
3876 uint8_t bDst = 0;
3877 uint8_t fBit = 0x80;
3878 do
3879 {
3880 if ((pbSrc[x * 2] | pbSrc[x * 2 + 1]) >= 0xfc)
3881 bDst |= fBit;
3882 fBit >>= 1;
3883 x++;
3884 } while (x < cx && (x & 7));
3885 pbDst[(x - 1) / 8] = bDst;
3886 }
3887 pbDst += cbDstAndLine;
3888 pbSrc += cbSrcAndLine;
3889 }
3890 break;
3891 case 24:
3892 for (uint32_t y = 0; y < cy; y++)
3893 {
3894 for (uint32_t x = 0; x < cx; )
3895 {
3896 uint8_t bDst = 0;
3897 uint8_t fBit = 0x80;
3898 do
3899 {
3900 if ((pbSrc[x * 3] | pbSrc[x * 3 + 1] | pbSrc[x * 3 + 2]) >= 0xfc)
3901 bDst |= fBit;
3902 fBit >>= 1;
3903 x++;
3904 } while (x < cx && (x & 7));
3905 pbDst[(x - 1) / 8] = bDst;
3906 }
3907 pbDst += cbDstAndLine;
3908 pbSrc += cbSrcAndLine;
3909 }
3910 break;
3911 case 32:
3912 for (uint32_t y = 0; y < cy; y++)
3913 {
3914 for (uint32_t x = 0; x < cx; )
3915 {
3916 uint8_t bDst = 0;
3917 uint8_t fBit = 0x80;
3918 do
3919 {
3920 if ((pbSrc[x * 4] | pbSrc[x * 4 + 1] | pbSrc[x * 4 + 2] | pbSrc[x * 4 + 3]) >= 0xfc)
3921 bDst |= fBit;
3922 fBit >>= 1;
3923 x++;
3924 } while (x < cx && (x & 7));
3925 pbDst[(x - 1) / 8] = bDst;
3926 }
3927 pbDst += cbDstAndLine;
3928 pbSrc += cbSrcAndLine;
3929 }
3930 break;
3931 default:
3932 RTMemFreeZ(pbCopy, cbCopy);
3933 AssertFailedReturnVoid();
3934 }
3935
3936 /* Convert the XOR mask. */
3937 uint32_t *pu32Dst = (uint32_t *)(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
3938 pbSrc = pbSrcXorMask;
3939 switch (pCmd->xorMaskDepth)
3940 {
3941 case 1:
3942 for (uint32_t y = 0; y < cy; y++)
3943 {
3944 for (uint32_t x = 0; x < cx; )
3945 {
3946 /* most significant bit is the left most one. */
3947 uint8_t bSrc = pbSrc[x / 8];
3948 do
3949 {
3950 *pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
3951 bSrc <<= 1;
3952 x++;
3953 } while ((x & 7) && x < cx);
3954 }
3955 pbSrc += cbSrcXorLine;
3956 }
3957 break;
3958 case 8:
3959 for (uint32_t y = 0; y < cy; y++)
3960 {
3961 for (uint32_t x = 0; x < cx; x++)
3962 {
3963 uint32_t u = pThis->last_palette[pbSrc[x]];
3964 *pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
3965 }
3966 pbSrc += cbSrcXorLine;
3967 }
3968 break;
3969 case 15: /* Src: RGB-5-5-5 */
3970 for (uint32_t y = 0; y < cy; y++)
3971 {
3972 for (uint32_t x = 0; x < cx; x++)
3973 {
3974 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
3975 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
3976 ((uValue >> 5) & 0x1f) << 3,
3977 ((uValue >> 10) & 0x1f) << 3, 0);
3978 }
3979 pbSrc += cbSrcXorLine;
3980 }
3981 break;
3982 case 16: /* Src: RGB-5-6-5 */
3983 for (uint32_t y = 0; y < cy; y++)
3984 {
3985 for (uint32_t x = 0; x < cx; x++)
3986 {
3987 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
3988 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
3989 ((uValue >> 5) & 0x3f) << 2,
3990 ((uValue >> 11) & 0x1f) << 3, 0);
3991 }
3992 pbSrc += cbSrcXorLine;
3993 }
3994 break;
3995 case 24:
3996 for (uint32_t y = 0; y < cy; y++)
3997 {
3998 for (uint32_t x = 0; x < cx; x++)
3999 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*3], pbSrc[x*3 + 1], pbSrc[x*3 + 2], 0);
4000 pbSrc += cbSrcXorLine;
4001 }
4002 break;
4003 case 32:
4004 for (uint32_t y = 0; y < cy; y++)
4005 {
4006 for (uint32_t x = 0; x < cx; x++)
4007 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*4], pbSrc[x*4 + 1], pbSrc[x*4 + 2], 0);
4008 pbSrc += cbSrcXorLine;
4009 }
4010 break;
4011 default:
4012 RTMemFreeZ(pbCopy, cbCopy);
4013 AssertFailedReturnVoid();
4014 }
4015
4016 /*
4017 * Pass it to the frontend/whatever.
4018 */
4019 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
4020 cx, cy, pbCopy, cbCopy);
4021}
4022
4023
4024/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
4025static void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
4026{
4027 RT_NOREF(pThis);
4028 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4029
4030 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
4031 Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
4032
4033 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
4034 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
4035 RT_UNTRUSTED_VALIDATED_FENCE();
4036
4037 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
4038 uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
4039 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
4040 uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
4041 uint32_t cbCursorShape = cbAndMask + cbXorMask;
4042
4043 uint8_t *pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
4044 AssertPtrReturnVoid(pCursorCopy);
4045
4046 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
4047 memset(pCursorCopy, 0xff, cbAndMask);
4048 /* Colour data */
4049 memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
4050
4051 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
4052 pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
4053}
4054
4055
4056/* SVGA_CMD_ESCAPE */
4057static void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
4058{
4059 RT_NOREF(pThis);
4060 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4061
4062 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
4063
4064 if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
4065 {
4066 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
4067 RT_UNTRUSTED_VALIDATED_FENCE();
4068
4069 uint32_t const cmd = *(uint32_t *)(pCmd + 1);
4070 Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
4071
4072 switch (cmd)
4073 {
4074 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
4075 {
4076 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pCmd + 1);
4077 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
4078 RT_UNTRUSTED_VALIDATED_FENCE();
4079
4080 uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
4081
4082 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
4083 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
4084 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
4085 RT_NOREF_PV(pVideoCmd);
4086 break;
4087 }
4088
4089 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
4090 {
4091 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pCmd + 1);
4092 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
4093 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
4094 RT_NOREF_PV(pVideoCmd);
4095 break;
4096 }
4097
4098 default:
4099 Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
4100 break;
4101 }
4102 }
4103 else
4104 Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
4105}
4106
4107
4108/* SVGA_CMD_DEFINE_SCREEN */
4109static void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
4110{
4111 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4112
4113 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
4114 Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4115 pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4116 pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4117
4118 uint32_t const idScreen = pCmd->screen.id;
4119 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
4120
4121 uint32_t const uWidth = pCmd->screen.size.width;
4122 ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
4123
4124 uint32_t const uHeight = pCmd->screen.size.height;
4125 ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
4126
4127 uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4128 uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4129 ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
4130
4131 uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4132 ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
4133
4134 uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4135 /* If we have a not zero pitch, then height can't exceed the available VRAM. */
4136 ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
4137 || (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4138 RT_UNTRUSTED_VALIDATED_FENCE();
4139
4140 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
4141 pScreen->fDefined = true;
4142 pScreen->fModified = true;
4143 pScreen->fuScreen = pCmd->screen.flags;
4144 pScreen->idScreen = idScreen;
4145 if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE | SVGA_SCREEN_BLANKING)))
4146 {
4147 /* Not blanked. */
4148 ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
4149 RT_UNTRUSTED_VALIDATED_FENCE();
4150
4151 pScreen->xOrigin = pCmd->screen.root.x;
4152 pScreen->yOrigin = pCmd->screen.root.y;
4153 pScreen->cWidth = uWidth;
4154 pScreen->cHeight = uHeight;
4155 pScreen->offVRAM = uScreenOffset;
4156 pScreen->cbPitch = cbPitch;
4157 pScreen->cBpp = 32;
4158 }
4159 else
4160 {
4161 /* Screen blanked. Keep old values. */
4162 }
4163
4164 pThis->svga.fGFBRegisters = false;
4165 vmsvgaR3ChangeMode(pThis, pThisCC);
4166
4167# ifdef VBOX_WITH_VMSVGA3D
4168 if (RT_LIKELY(pThis->svga.f3DEnabled))
4169 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
4170# endif
4171}
4172
4173
4174/* SVGA_CMD_DESTROY_SCREEN */
4175static void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
4176{
4177 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4178
4179 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
4180 Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4181
4182 uint32_t const idScreen = pCmd->screenId;
4183 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
4184 RT_UNTRUSTED_VALIDATED_FENCE();
4185
4186 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
4187 pScreen->fModified = true;
4188 pScreen->fDefined = false;
4189 pScreen->idScreen = idScreen;
4190
4191# ifdef VBOX_WITH_VMSVGA3D
4192 if (RT_LIKELY(pThis->svga.f3DEnabled))
4193 vmsvga3dDestroyScreen(pThisCC, pScreen);
4194# endif
4195 vmsvgaR3ChangeMode(pThis, pThisCC);
4196}
4197
4198
4199/* SVGA_CMD_DEFINE_GMRFB */
4200static void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
4201{
4202 RT_NOREF(pThis);
4203 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4204
4205 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
4206 Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
4207 pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
4208
4209 pSvgaR3State->GMRFB.ptr = pCmd->ptr;
4210 pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4211 pSvgaR3State->GMRFB.format = pCmd->format;
4212}
4213
4214
4215/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
4216static void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
4217{
4218 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4219
4220 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
4221 Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4222 pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4223
4224 ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
4225 RT_UNTRUSTED_VALIDATED_FENCE();
4226
4227 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
4228 AssertPtrReturnVoid(pScreen);
4229
4230 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
4231 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
4232
4233 /* Clip destRect to the screen dimensions. */
4234 SVGASignedRect screenRect;
4235 screenRect.left = 0;
4236 screenRect.top = 0;
4237 screenRect.right = pScreen->cWidth;
4238 screenRect.bottom = pScreen->cHeight;
4239 SVGASignedRect clipRect = pCmd->destRect;
4240 vmsvgaR3ClipRect(&screenRect, &clipRect);
4241 RT_UNTRUSTED_VALIDATED_FENCE();
4242
4243 uint32_t const width = clipRect.right - clipRect.left;
4244 uint32_t const height = clipRect.bottom - clipRect.top;
4245
4246 if ( width == 0
4247 || height == 0)
4248 return; /* Nothing to do. */
4249
4250 int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4251 int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4252
4253 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
4254 * Prepare parameters for vmsvgaR3GmrTransfer.
4255 */
4256 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4257
4258 /* Destination: host buffer which describes the screen 0 VRAM.
4259 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4260 */
4261 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4262 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4263 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4264 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4265 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4266 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4267 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4268 + cbScanline * clipRect.top;
4269 int32_t const cbHstPitch = cbScanline;
4270
4271 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4272 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
4273 uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
4274 + pSvgaR3State->GMRFB.bytesPerLine * srcy;
4275 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
4276
4277 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
4278 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4279 gstPtr, offGst, cbGstPitch,
4280 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4281 AssertRC(rc);
4282 vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
4283}
4284
4285
4286/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
4287static void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
4288{
4289 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4290
4291 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
4292 /* Note! This can fetch 3d render results as well!! */
4293 Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4294 pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4295
4296 ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
4297 RT_UNTRUSTED_VALIDATED_FENCE();
4298
4299 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
4300 AssertPtrReturnVoid(pScreen);
4301
4302 /** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
4303 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
4304
4305 /* Clip destRect to the screen dimensions. */
4306 SVGASignedRect screenRect;
4307 screenRect.left = 0;
4308 screenRect.top = 0;
4309 screenRect.right = pScreen->cWidth;
4310 screenRect.bottom = pScreen->cHeight;
4311 SVGASignedRect clipRect = pCmd->srcRect;
4312 vmsvgaR3ClipRect(&screenRect, &clipRect);
4313 RT_UNTRUSTED_VALIDATED_FENCE();
4314
4315 uint32_t const width = clipRect.right - clipRect.left;
4316 uint32_t const height = clipRect.bottom - clipRect.top;
4317
4318 if ( width == 0
4319 || height == 0)
4320 return; /* Nothing to do. */
4321
4322 int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4323 int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4324
4325 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
4326 * Prepare parameters for vmsvgaR3GmrTransfer.
4327 */
4328 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4329
4330 /* Source: host buffer which describes the screen 0 VRAM.
4331 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4332 */
4333 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4334 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4335 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4336 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4337 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4338 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4339 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4340 + cbScanline * clipRect.top;
4341 int32_t const cbHstPitch = cbScanline;
4342
4343 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4344 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
4345 uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
4346 + pSvgaR3State->GMRFB.bytesPerLine * dsty;
4347 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
4348
4349 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
4350 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4351 gstPtr, offGst, cbGstPitch,
4352 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4353 AssertRC(rc);
4354}
4355
4356
4357/* SVGA_CMD_ANNOTATION_FILL */
4358static void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
4359{
4360 RT_NOREF(pThis);
4361 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4362
4363 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
4364 Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
4365
4366 pSvgaR3State->colorAnnotation = pCmd->color;
4367}
4368
4369
4370/* SVGA_CMD_ANNOTATION_COPY */
4371static void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
4372{
4373 RT_NOREF(pThis, pCmd);
4374 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4375
4376 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
4377 Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
4378
4379 AssertFailed();
4380}
4381
4382
4383# ifdef VBOX_WITH_VMSVGA3D
4384/* SVGA_CMD_DEFINE_GMR2 */
4385static void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
4386{
4387 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4388
4389 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
4390 Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
4391
4392 /* Validate current GMR id. */
4393 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
4394 ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
4395 RT_UNTRUSTED_VALIDATED_FENCE();
4396
4397 if (!pCmd->numPages)
4398 {
4399 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
4400 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
4401 }
4402 else
4403 {
4404 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
4405 if (pGMR->cMaxPages)
4406 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
4407
4408 /* Not sure if we should always free the descriptor, but for simplicity
4409 we do so if the new size is smaller than the current. */
4410 /** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
4411 if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
4412 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
4413
4414 pGMR->cMaxPages = pCmd->numPages;
4415 /* The rest is done by the REMAP_GMR2 command. */
4416 }
4417}
4418
4419
4420/* SVGA_CMD_REMAP_GMR2 */
4421static void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
4422{
4423 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4424
4425 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
4426 Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
4427
4428 /* Validate current GMR id and size. */
4429 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
4430 RT_UNTRUSTED_VALIDATED_FENCE();
4431 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
4432 ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
4433 <= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
4434 ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
4435
4436 if (pCmd->numPages == 0)
4437 return;
4438 RT_UNTRUSTED_VALIDATED_FENCE();
4439
4440 /* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
4441 uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
4442
4443 /*
4444 * We flatten the existing descriptors into a page array, overwrite the
4445 * pages specified in this command and then recompress the descriptor.
4446 */
4447 /** @todo Optimize the GMR remap algorithm! */
4448
4449 /* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
4450 uint64_t *paNewPage64 = NULL;
4451 if (pGMR->paDesc)
4452 {
4453 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
4454
4455 paNewPage64 = (uint64_t *)RTMemAllocZ(cNewTotalPages * sizeof(uint64_t));
4456 AssertPtrReturnVoid(paNewPage64);
4457
4458 uint32_t idxPage = 0;
4459 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
4460 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
4461 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
4462 AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
4463 RT_UNTRUSTED_VALIDATED_FENCE();
4464 }
4465
4466 /* Free the old GMR if present. */
4467 if (pGMR->paDesc)
4468 RTMemFree(pGMR->paDesc);
4469
4470 /* Allocate the maximum amount possible (everything non-continuous) */
4471 PVMSVGAGMRDESCRIPTOR paDescs;
4472 pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
4473 AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
4474
4475 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4476 {
4477 /** @todo */
4478 AssertFailed();
4479 pGMR->numDescriptors = 0;
4480 }
4481 else
4482 {
4483 uint32_t *paPages32 = (uint32_t *)(pCmd + 1);
4484 uint64_t *paPages64 = (uint64_t *)(pCmd + 1);
4485 bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
4486
4487 uint32_t cPages;
4488 if (paNewPage64)
4489 {
4490 /* Overwrite the old page array with the new page values. */
4491 if (fGCPhys64)
4492 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4493 paNewPage64[i] = paPages64[i - pCmd->offsetPages];
4494 else
4495 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4496 paNewPage64[i] = paPages32[i - pCmd->offsetPages];
4497
4498 /* Use the updated page array instead of the command data. */
4499 fGCPhys64 = true;
4500 paPages64 = paNewPage64;
4501 cPages = cNewTotalPages;
4502 }
4503 else
4504 cPages = pCmd->numPages;
4505
4506 /* The first page. */
4507 /** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
4508 * applied to paNewPage64. */
4509 RTGCPHYS GCPhys;
4510 if (fGCPhys64)
4511 GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4512 else
4513 GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4514 paDescs[0].GCPhys = GCPhys;
4515 paDescs[0].numPages = 1;
4516
4517 /* Subsequent pages. */
4518 uint32_t iDescriptor = 0;
4519 for (uint32_t i = 1; i < cPages; i++)
4520 {
4521 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4522 GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4523 else
4524 GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4525
4526 /* Continuous physical memory? */
4527 if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4528 {
4529 Assert(paDescs[iDescriptor].numPages);
4530 paDescs[iDescriptor].numPages++;
4531 Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4532 }
4533 else
4534 {
4535 iDescriptor++;
4536 paDescs[iDescriptor].GCPhys = GCPhys;
4537 paDescs[iDescriptor].numPages = 1;
4538 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4539 }
4540 }
4541
4542 pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4543 Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4544 pGMR->numDescriptors = iDescriptor + 1;
4545 }
4546
4547 if (paNewPage64)
4548 RTMemFree(paNewPage64);
4549}
4550# endif // VBOX_WITH_VMSVGA3D
4551
4552
4553/*
4554 *
4555 * Command buffer submission.
4556 *
4557 * Guest submits a buffer by writing to SVGA_REG_COMMAND_LOW register.
4558 *
4559 * EMT thread appends a command buffer to the context queue (VMSVGACMDBUFCTX::listSubmitted)
4560 * and wakes up the FIFO thread.
4561 *
4562 * FIFO thread fetches the command buffer from the queue, processes the commands and writes
4563 * the buffer header back to the guest memory.
4564 *
4565 * If buffers are preempted, then the EMT thread removes all buffers from the context queue.
4566 *
4567 */
4568
4569
4570/** Update a command buffer header 'status' and 'errorOffset' fields in the guest memory.
4571 *
4572 * @param pDevIns The device instance.
4573 * @param GCPhysCB Guest physical address of the command buffer header.
4574 * @param status Command buffer status (SVGA_CB_STATUS_*).
4575 * @param errorOffset Offset to the first byte of the failing command for SVGA_CB_STATUS_COMMAND_ERROR.
4576 * errorOffset is ignored if the status is not SVGA_CB_STATUS_COMMAND_ERROR.
4577 * @thread FIFO or EMT.
4578 */
4579static void vmsvgaR3CmdBufWriteStatus(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCB, SVGACBStatus status, uint32_t errorOffset)
4580{
4581 SVGACBHeader hdr;
4582 hdr.status = status;
4583 hdr.errorOffset = errorOffset;
4584 AssertCompile( RT_OFFSETOF(SVGACBHeader, status) == 0
4585 && RT_OFFSETOF(SVGACBHeader, errorOffset) == 4
4586 && RT_OFFSETOF(SVGACBHeader, id) == 8);
4587 size_t const cbWrite = status == SVGA_CB_STATUS_COMMAND_ERROR
4588 ? RT_UOFFSET_AFTER(SVGACBHeader, errorOffset) /* Both 'status' and 'errorOffset' fields. */
4589 : RT_UOFFSET_AFTER(SVGACBHeader, status); /* Only 'status' field. */
4590 PDMDevHlpPhysWrite(pDevIns, GCPhysCB, &hdr, cbWrite);
4591}
4592
4593
4594/** Raise an IRQ.
4595 *
4596 * @param pDevIns The device instance.
4597 * @param pThis The shared VGA/VMSVGA state.
4598 * @param fIRQ SVGA_IRQFLAG_* bits.
4599 * @thread FIFO or EMT.
4600 */
4601static void vmsvgaR3CmdBufRaiseIRQ(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t fIRQ)
4602{
4603 int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4604 AssertRC(rc);
4605
4606 if (pThis->svga.u32IrqMask & fIRQ)
4607 {
4608 LogFunc(("Trigger interrupt with status %#x\n", fIRQ));
4609 ASMAtomicOrU32(&pThis->svga.u32IrqStatus, fIRQ);
4610 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4611 }
4612
4613 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4614}
4615
4616
4617/** Allocate a command buffer structure.
4618 *
4619 * @param pCmdBufCtx The command buffer context which must allocate the buffer.
4620 * @return Pointer to the allocated command buffer structure.
4621 */
4622static PVMSVGACMDBUF vmsvgaR3CmdBufAlloc(PVMSVGACMDBUFCTX pCmdBufCtx)
4623{
4624 if (!pCmdBufCtx)
4625 return NULL;
4626
4627 PVMSVGACMDBUF pCmdBuf = (PVMSVGACMDBUF)RTMemAllocZ(sizeof(*pCmdBuf));
4628 if (pCmdBuf)
4629 {
4630 // RT_ZERO(pCmdBuf->nodeBuffer);
4631 pCmdBuf->pCmdBufCtx = pCmdBufCtx;
4632 // pCmdBuf->GCPhysCB = 0;
4633 // RT_ZERO(pCmdBuf->hdr);
4634 // pCmdBuf->pvCommands = NULL;
4635 }
4636
4637 return pCmdBuf;
4638}
4639
4640
4641/** Free a command buffer structure.
4642 *
4643 * @param pCmdBuf The command buffer pointer.
4644 */
4645static void vmsvgaR3CmdBufFree(PVMSVGACMDBUF pCmdBuf)
4646{
4647 if (pCmdBuf)
4648 RTMemFree(pCmdBuf->pvCommands);
4649 RTMemFree(pCmdBuf);
4650}
4651
4652
4653/** Initialize a command buffer context.
4654 *
4655 * @param pCmdBufCtx The command buffer context.
4656 */
4657static void vmsvgaR3CmdBufCtxInit(PVMSVGACMDBUFCTX pCmdBufCtx)
4658{
4659 RTListInit(&pCmdBufCtx->listSubmitted);
4660 pCmdBufCtx->cSubmitted = 0;
4661}
4662
4663
4664/** Destroy a command buffer context.
4665 *
4666 * @param pCmdBufCtx The command buffer context pointer.
4667 */
4668static void vmsvgaR3CmdBufCtxTerm(PVMSVGACMDBUFCTX pCmdBufCtx)
4669{
4670 if (!pCmdBufCtx)
4671 return;
4672
4673 if (pCmdBufCtx->listSubmitted.pNext)
4674 {
4675 /* If the list has been initialized. */
4676 PVMSVGACMDBUF pIter, pNext;
4677 RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
4678 {
4679 RTListNodeRemove(&pIter->nodeBuffer);
4680 --pCmdBufCtx->cSubmitted;
4681 vmsvgaR3CmdBufFree(pIter);
4682 }
4683 }
4684 Assert(pCmdBufCtx->cSubmitted == 0);
4685 pCmdBufCtx->cSubmitted = 0;
4686}
4687
4688
4689/** Handles SVGA_DC_CMD_START_STOP_CONTEXT command.
4690 *
4691 * @param pSvgaR3State VMSVGA R3 state.
4692 * @param pCmd The command data.
4693 * @return SVGACBStatus code.
4694 * @thread EMT
4695 */
4696static SVGACBStatus vmsvgaR3CmdBufDCStartStop(PVMSVGAR3STATE pSvgaR3State, SVGADCCmdStartStop const *pCmd)
4697{
4698 /* Create or destroy a regular command buffer context. */
4699 if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
4700 return SVGA_CB_STATUS_COMMAND_ERROR;
4701 RT_UNTRUSTED_VALIDATED_FENCE();
4702
4703 SVGACBStatus CBStatus = SVGA_CB_STATUS_COMPLETED;
4704
4705 int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
4706 AssertRC(rc);
4707 if (pCmd->enable)
4708 {
4709 pSvgaR3State->apCmdBufCtxs[pCmd->context] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
4710 if (pSvgaR3State->apCmdBufCtxs[pCmd->context])
4711 vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
4712 else
4713 CBStatus = SVGA_CB_STATUS_QUEUE_FULL;
4714 }
4715 else
4716 {
4717 vmsvgaR3CmdBufCtxTerm(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
4718 pSvgaR3State->apCmdBufCtxs[pCmd->context] = NULL;
4719 }
4720 RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
4721
4722 return CBStatus;
4723}
4724
4725
4726/** Handles SVGA_DC_CMD_PREEMPT command.
4727 *
4728 * @param pDevIns The device instance.
4729 * @param pSvgaR3State VMSVGA R3 state.
4730 * @param pCmd The command data.
4731 * @return SVGACBStatus code.
4732 * @thread EMT
4733 */
4734static SVGACBStatus vmsvgaR3CmdBufDCPreempt(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, SVGADCCmdPreempt const *pCmd)
4735{
4736 /* Remove buffers from the processing queue of the specified context. */
4737 if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
4738 return SVGA_CB_STATUS_COMMAND_ERROR;
4739 RT_UNTRUSTED_VALIDATED_FENCE();
4740
4741 PVMSVGACMDBUFCTX const pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[pCmd->context];
4742 RTLISTANCHOR listPreempted;
4743
4744 int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
4745 AssertRC(rc);
4746 if (pCmd->ignoreIDZero)
4747 {
4748 RTListInit(&listPreempted);
4749
4750 PVMSVGACMDBUF pIter, pNext;
4751 RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
4752 {
4753 if (pIter->hdr.id == 0)
4754 continue;
4755
4756 RTListNodeRemove(&pIter->nodeBuffer);
4757 --pCmdBufCtx->cSubmitted;
4758 RTListAppend(&listPreempted, &pIter->nodeBuffer);
4759 }
4760 }
4761 else
4762 {
4763 RTListMove(&listPreempted, &pCmdBufCtx->listSubmitted);
4764 }
4765 RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
4766
4767 PVMSVGACMDBUF pIter, pNext;
4768 RTListForEachSafe(&listPreempted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
4769 {
4770 RTListNodeRemove(&pIter->nodeBuffer);
4771 vmsvgaR3CmdBufWriteStatus(pDevIns, pIter->GCPhysCB, SVGA_CB_STATUS_PREEMPTED, 0);
4772 vmsvgaR3CmdBufFree(pIter);
4773 }
4774
4775 return SVGA_CB_STATUS_COMPLETED;
4776}
4777
4778
4779/** @def VMSVGA_INC_CMD_SIZE_BREAK
4780 * Increments the size of the command cbCmd by a_cbMore.
4781 * Checks that the command buffer has at least cbCmd bytes. Will break out of the switch if it doesn't.
4782 * Used by vmsvgaR3CmdBufProcessDC and vmsvgaR3CmdBufProcessCommands.
4783 */
4784#define VMSVGA_INC_CMD_SIZE_BREAK(a_cbMore) \
4785 if (1) { \
4786 cbCmd += (a_cbMore); \
4787 ASSERT_GUEST_MSG_STMT_BREAK(cbRemain >= cbCmd, ("size=%#x remain=%#zx\n", cbCmd, (size_t)cbRemain), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR); \
4788 RT_UNTRUSTED_VALIDATED_FENCE(); \
4789 } else do {} while (0)
4790
4791
4792/** Processes Device Context command buffer.
4793 *
4794 * @param pDevIns The device instance.
4795 * @param pSvgaR3State VMSVGA R3 state.
4796 * @param pvCommands Pointer to the command buffer.
4797 * @param cbCommands Size of the command buffer.
4798 * @param poffNextCmd Where to store the offset of the first unprocessed command.
4799 * @return SVGACBStatus code.
4800 * @thread EMT
4801 */
4802static SVGACBStatus vmsvgaR3CmdBufProcessDC(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, void const *pvCommands, uint32_t cbCommands, uint32_t *poffNextCmd)
4803{
4804 SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
4805
4806 uint8_t const *pu8Cmd = (uint8_t *)pvCommands;
4807 uint32_t cbRemain = cbCommands;
4808 while (cbRemain)
4809 {
4810 /* Command identifier is a 32 bit value. */
4811 if (cbRemain < sizeof(uint32_t))
4812 {
4813 CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
4814 break;
4815 }
4816
4817 /* Fetch the command id. */
4818 uint32_t const cmdId = *(uint32_t *)pu8Cmd;
4819 uint32_t cbCmd = sizeof(uint32_t);
4820 switch (cmdId)
4821 {
4822 case SVGA_DC_CMD_NOP:
4823 {
4824 /* NOP */
4825 break;
4826 }
4827
4828 case SVGA_DC_CMD_START_STOP_CONTEXT:
4829 {
4830 SVGADCCmdStartStop *pCmd = (SVGADCCmdStartStop *)&pu8Cmd[cbCmd];
4831 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
4832 CBstatus = vmsvgaR3CmdBufDCStartStop(pSvgaR3State, pCmd);
4833 break;
4834 }
4835
4836 case SVGA_DC_CMD_PREEMPT:
4837 {
4838 SVGADCCmdPreempt *pCmd = (SVGADCCmdPreempt *)&pu8Cmd[cbCmd];
4839 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
4840 CBstatus = vmsvgaR3CmdBufDCPreempt(pDevIns, pSvgaR3State, pCmd);
4841 break;
4842 }
4843
4844 default:
4845 {
4846 /* Unsupported command. */
4847 CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
4848 break;
4849 }
4850 }
4851
4852 if (CBstatus != SVGA_CB_STATUS_COMPLETED)
4853 break;
4854
4855 pu8Cmd += cbCmd;
4856 cbRemain -= cbCmd;
4857 }
4858
4859 Assert(cbRemain <= cbCommands);
4860 *poffNextCmd = cbCommands - cbRemain;
4861 return CBstatus;
4862}
4863
4864
4865/** Submits a device context command buffer for synchronous processing.
4866 *
4867 * @param pDevIns The device instance.
4868 * @param pThisCC The VGA/VMSVGA state for the current context.
4869 * @param ppCmdBuf Pointer to the command buffer pointer.
4870 * The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
4871 * @param poffNextCmd Where to store the offset of the first unprocessed command.
4872 * @return SVGACBStatus code.
4873 * @thread EMT
4874 */
4875static SVGACBStatus vmsvgaR3CmdBufSubmitDC(PPDMDEVINS pDevIns, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf, uint32_t *poffNextCmd)
4876{
4877 /* Synchronously process the device context commands. */
4878 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4879 return vmsvgaR3CmdBufProcessDC(pDevIns, pSvgaR3State, (*ppCmdBuf)->pvCommands, (*ppCmdBuf)->hdr.length, poffNextCmd);
4880}
4881
4882/** Submits a command buffer for asynchronous processing by the FIFO thread.
4883 *
4884 * @param pDevIns The device instance.
4885 * @param pThis The shared VGA/VMSVGA state.
4886 * @param pThisCC The VGA/VMSVGA state for the current context.
4887 * @param ppCmdBuf Pointer to the command buffer pointer.
4888 * The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
4889 * @return SVGACBStatus code.
4890 * @thread EMT
4891 */
4892static SVGACBStatus vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf)
4893{
4894 /* Command buffer submission. */
4895 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4896
4897 SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
4898
4899 PVMSVGACMDBUF const pCmdBuf = *ppCmdBuf;
4900 PVMSVGACMDBUFCTX const pCmdBufCtx = pCmdBuf->pCmdBufCtx;
4901
4902 int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
4903 AssertRC(rc);
4904
4905 if (RT_LIKELY(pCmdBufCtx->cSubmitted < SVGA_CB_MAX_QUEUED_PER_CONTEXT))
4906 {
4907 RTListAppend(&pCmdBufCtx->listSubmitted, &pCmdBuf->nodeBuffer);
4908 ++pCmdBufCtx->cSubmitted;
4909 *ppCmdBuf = NULL; /* Consume the buffer. */
4910 ASMAtomicWriteU32(&pThisCC->svga.pSvgaR3State->fCmdBuf, 1);
4911 }
4912 else
4913 CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
4914
4915 RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
4916
4917 /* Inform the FIFO thread. */
4918 if (*ppCmdBuf == NULL)
4919 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4920
4921 return CBstatus;
4922}
4923
4924
4925/** SVGA_REG_COMMAND_LOW write handler.
4926 * Submits a command buffer to the FIFO thread or processes a device context command.
4927 *
4928 * @param pDevIns The device instance.
4929 * @param pThis The shared VGA/VMSVGA state.
4930 * @param pThisCC The VGA/VMSVGA state for the current context.
4931 * @param GCPhysCB Guest physical address of the command buffer header.
4932 * @param CBCtx Context the command buffer is submitted to.
4933 * @thread EMT
4934 */
4935static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx)
4936{
4937 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4938
4939 SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
4940 uint32_t offNextCmd = 0;
4941 uint32_t fIRQ = 0;
4942
4943 /* Get the context if the device has the capability. */
4944 PVMSVGACMDBUFCTX pCmdBufCtx = NULL;
4945 if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
4946 {
4947 if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
4948 pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[CBCtx];
4949 else if (CBCtx == SVGA_CB_CONTEXT_DEVICE)
4950 pCmdBufCtx = &pSvgaR3State->CmdBufCtxDC;
4951 RT_UNTRUSTED_VALIDATED_FENCE();
4952 }
4953
4954 /* Allocate a new command buffer. */
4955 PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pCmdBufCtx);
4956 if (RT_LIKELY(pCmdBuf))
4957 {
4958 pCmdBuf->GCPhysCB = GCPhysCB;
4959
4960 int rc = PDMDevHlpPhysRead(pDevIns, GCPhysCB, &pCmdBuf->hdr, sizeof(pCmdBuf->hdr));
4961 if (RT_SUCCESS(rc))
4962 {
4963 /* Verify the command buffer header. */
4964 if (RT_LIKELY( pCmdBuf->hdr.status == SVGA_CB_STATUS_NONE
4965 && (pCmdBuf->hdr.flags & ~(SVGA_CB_FLAG_NO_IRQ)) == 0 /* No unexpected flags. */
4966 && pCmdBuf->hdr.length <= SVGA_CB_MAX_SIZE))
4967 {
4968 RT_UNTRUSTED_VALIDATED_FENCE();
4969
4970 /* Read the command buffer content. */
4971 pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
4972 if (pCmdBuf->pvCommands)
4973 {
4974 RTGCPHYS const GCPhysCmd = (RTGCPHYS)pCmdBuf->hdr.ptr.pa;
4975 rc = PDMDevHlpPhysRead(pDevIns, GCPhysCmd, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
4976 if (RT_SUCCESS(rc))
4977 {
4978 /* Submit the buffer. Device context buffers will be processed synchronously. */
4979 if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
4980 /* This usually processes the CB async and sets pCmbBuf to NULL. */
4981 CBstatus = vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, &pCmdBuf);
4982 else
4983 CBstatus = vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
4984 }
4985 else
4986 {
4987 ASSERT_GUEST_MSG_FAILED(("Failed to read commands at %RGp\n", GCPhysCmd));
4988 CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
4989 fIRQ = SVGA_IRQFLAG_ERROR | SVGA_IRQFLAG_COMMAND_BUFFER;
4990 }
4991 }
4992 else
4993 {
4994 /* No memory for commands. */
4995 CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
4996 }
4997 }
4998 else
4999 {
5000 ASSERT_GUEST_MSG_FAILED(("Invalid buffer header\n"));
5001 CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
5002 fIRQ = SVGA_IRQFLAG_ERROR | SVGA_IRQFLAG_COMMAND_BUFFER;
5003 }
5004 }
5005 else
5006 {
5007 LogFunc(("Failed to read buffer header at %RGp\n", GCPhysCB));
5008 ASSERT_GUEST_FAILED();
5009 /* Do not attempt to write the status. */
5010 }
5011
5012 /* Free the buffer if pfnCmdBufSubmit did not consume it. */
5013 vmsvgaR3CmdBufFree(pCmdBuf);
5014 }
5015 else
5016 {
5017 LogFunc(("Can't allocate buffer for context id %#x\n", CBCtx));
5018 ASSERT_GUEST_FAILED();
5019 CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
5020 }
5021
5022 if (CBstatus != SVGA_CB_STATUS_NONE)
5023 {
5024 LogFunc(("Write status %#x, offNextCmd %#x (of %#x), fIRQ %#x\n", CBstatus, offNextCmd, pCmdBuf->hdr.length, fIRQ));
5025 vmsvgaR3CmdBufWriteStatus(pDevIns, GCPhysCB, CBstatus, offNextCmd);
5026 if (fIRQ)
5027 vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, fIRQ);
5028 }
5029}
5030
5031
5032/** Checks if there are some buffers to be processed.
5033 *
5034 * @param pThisCC The VGA/VMSVGA state for the current context.
5035 * @return true if buffers must be processed.
5036 * @thread FIFO
5037 */
5038static bool vmsvgaR3CmdBufHasWork(PVGASTATECC pThisCC)
5039{
5040 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5041 return RT_BOOL(ASMAtomicReadU32(&pSvgaR3State->fCmdBuf));
5042}
5043
5044
5045/** Processes a command buffer.
5046 *
5047 * @param pDevIns The device instance.
5048 * @param pThis The shared VGA/VMSVGA state.
5049 * @param pThisCC The VGA/VMSVGA state for the current context.
5050 * @param pvCommands Pointer to the command buffer.
5051 * @param cbCommands Size of the command buffer.
5052 * @param poffNextCmd Where to store the offset of the first unprocessed command.
5053 * @return SVGACBStatus code.
5054 * @thread FIFO
5055 */
5056static SVGACBStatus vmsvgaR3CmdBufProcessCommands(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, void const *pvCommands, uint32_t cbCommands, uint32_t *poffNextCmd)
5057{
5058 SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
5059 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5060
5061 uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
5062
5063 uint8_t const *pu8Cmd = (uint8_t *)pvCommands;
5064 uint32_t cbRemain = cbCommands;
5065 while (cbRemain)
5066 {
5067 /* Command identifier is a 32 bit value. */
5068 if (cbRemain < sizeof(uint32_t))
5069 {
5070 CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
5071 break;
5072 }
5073
5074 /* Fetch the command id.
5075 * 'cmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
5076 * warning. Because we support some obsolete and deprecated commands, which are not included in
5077 * the SVGAFifoCmdId enum in the VMSVGA headers anymore.
5078 */
5079 uint32_t const cmdId = *(uint32_t *)pu8Cmd;
5080 uint32_t cbCmd = sizeof(uint32_t);
5081
5082 LogFlowFunc(("%s %d\n", vmsvgaR3FifoCmdToString(cmdId), cmdId));
5083
5084 /* At the end of the switch cbCmd is equal to the total length of the command including the cmdId.
5085 * I.e. pu8Cmd + cbCmd must point to the next command.
5086 * However if CBstatus is set to anything but SVGA_CB_STATUS_COMPLETED in the switch, then
5087 * the cbCmd value is ignored (and pu8Cmd still points to the failed command).
5088 */
5089 /** @todo This code is very similar to the FIFO loop command processing. Think about merging. */
5090 switch (cmdId)
5091 {
5092 case SVGA_CMD_INVALID_CMD:
5093 {
5094 /* Nothing to do. */
5095 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdInvalidCmd);
5096 break;
5097 }
5098
5099 case SVGA_CMD_FENCE:
5100 {
5101 SVGAFifoCmdFence *pCmd = (SVGAFifoCmdFence *)&pu8Cmd[cbCmd];
5102 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5103 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdFence);
5104 Log(("SVGA_CMD_FENCE %#x\n", pCmd->fence));
5105
5106 uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
5107 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
5108 {
5109 pFIFO[SVGA_FIFO_FENCE] = pCmd->fence;
5110
5111 uint32_t u32IrqStatus = 0;
5112 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
5113 {
5114 Log(("any fence irq\n"));
5115 u32IrqStatus |= SVGA_IRQFLAG_ANY_FENCE;
5116 }
5117 else if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
5118 && (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
5119 && pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmd->fence)
5120 {
5121 Log(("fence goal reached irq (fence=%x)\n", pCmd->fence));
5122 u32IrqStatus |= SVGA_IRQFLAG_FENCE_GOAL;
5123 }
5124
5125 if (u32IrqStatus)
5126 vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, u32IrqStatus);
5127 }
5128 else
5129 Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
5130 break;
5131 }
5132
5133 case SVGA_CMD_UPDATE:
5134 {
5135 SVGAFifoCmdUpdate *pCmd = (SVGAFifoCmdUpdate *)&pu8Cmd[cbCmd];
5136 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5137 vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
5138 break;
5139 }
5140
5141 case SVGA_CMD_UPDATE_VERBOSE:
5142 {
5143 SVGAFifoCmdUpdateVerbose *pCmd = (SVGAFifoCmdUpdateVerbose *)&pu8Cmd[cbCmd];
5144 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5145 vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
5146 break;
5147 }
5148
5149 case SVGA_CMD_DEFINE_CURSOR:
5150 {
5151 /* Followed by bitmap data. */
5152 SVGAFifoCmdDefineCursor *pCmd = (SVGAFifoCmdDefineCursor *)&pu8Cmd[cbCmd];
5153 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5154
5155 /* Figure out the size of the bitmap data. */
5156 ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
5157 ASSERT_GUEST_STMT_BREAK(pCmd->andMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
5158 ASSERT_GUEST_STMT_BREAK(pCmd->xorMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
5159 RT_UNTRUSTED_VALIDATED_FENCE();
5160
5161 uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
5162 uint32_t const cbAndMask = cbAndLine * pCmd->height;
5163 uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
5164 uint32_t const cbXorMask = cbXorLine * pCmd->height;
5165
5166 VMSVGA_INC_CMD_SIZE_BREAK(cbAndMask + cbXorMask);
5167 vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
5168 break;
5169 }
5170
5171 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
5172 {
5173 /* Followed by bitmap data. */
5174 SVGAFifoCmdDefineAlphaCursor *pCmd = (SVGAFifoCmdDefineAlphaCursor *)&pu8Cmd[cbCmd];
5175 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5176
5177 /* Figure out the size of the bitmap data. */
5178 ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
5179
5180 VMSVGA_INC_CMD_SIZE_BREAK(pCmd->width * pCmd->height * sizeof(uint32_t)); /* 32-bit BRGA format */
5181 vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
5182 break;
5183 }
5184
5185 case SVGA_CMD_MOVE_CURSOR:
5186 {
5187 /* Deprecated; there should be no driver which *requires* this command. However, if
5188 * we do ecncounter this command, it might be useful to not get the FIFO completely out of
5189 * alignment.
5190 * May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
5191 */
5192 SVGAFifoCmdMoveCursor *pCmd = (SVGAFifoCmdMoveCursor *)&pu8Cmd[cbCmd];
5193 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5194 vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
5195 break;
5196 }
5197
5198 case SVGA_CMD_DISPLAY_CURSOR:
5199 {
5200 /* Deprecated; there should be no driver which *requires* this command. However, if
5201 * we do ecncounter this command, it might be useful to not get the FIFO completely out of
5202 * alignment.
5203 * May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
5204 */
5205 SVGAFifoCmdDisplayCursor *pCmd = (SVGAFifoCmdDisplayCursor *)&pu8Cmd[cbCmd];
5206 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5207 vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
5208 break;
5209 }
5210
5211 case SVGA_CMD_RECT_FILL:
5212 {
5213 SVGAFifoCmdRectFill *pCmd = (SVGAFifoCmdRectFill *)&pu8Cmd[cbCmd];
5214 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5215 vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
5216 break;
5217 }
5218
5219 case SVGA_CMD_RECT_COPY:
5220 {
5221 SVGAFifoCmdRectCopy *pCmd = (SVGAFifoCmdRectCopy *)&pu8Cmd[cbCmd];
5222 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5223 vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
5224 break;
5225 }
5226
5227 case SVGA_CMD_RECT_ROP_COPY:
5228 {
5229 SVGAFifoCmdRectRopCopy *pCmd = (SVGAFifoCmdRectRopCopy *)&pu8Cmd[cbCmd];
5230 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5231 vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
5232 break;
5233 }
5234
5235 case SVGA_CMD_ESCAPE:
5236 {
5237 /* Followed by 'size' bytes of data. */
5238 SVGAFifoCmdEscape *pCmd = (SVGAFifoCmdEscape *)&pu8Cmd[cbCmd];
5239 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5240
5241 ASSERT_GUEST_STMT_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
5242 RT_UNTRUSTED_VALIDATED_FENCE();
5243
5244 VMSVGA_INC_CMD_SIZE_BREAK(pCmd->size);
5245 vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
5246 break;
5247 }
5248# ifdef VBOX_WITH_VMSVGA3D
5249 case SVGA_CMD_DEFINE_GMR2:
5250 {
5251 SVGAFifoCmdDefineGMR2 *pCmd = (SVGAFifoCmdDefineGMR2 *)&pu8Cmd[cbCmd];
5252 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5253 vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
5254 break;
5255 }
5256
5257 case SVGA_CMD_REMAP_GMR2:
5258 {
5259 /* Followed by page descriptors or guest ptr. */
5260 SVGAFifoCmdRemapGMR2 *pCmd = (SVGAFifoCmdRemapGMR2 *)&pu8Cmd[cbCmd];
5261 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5262
5263 /* Calculate the size of what comes after next and fetch it. */
5264 uint32_t cbMore = 0;
5265 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
5266 cbMore = sizeof(SVGAGuestPtr);
5267 else
5268 {
5269 uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
5270 if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
5271 {
5272 cbMore = cbPageDesc;
5273 pCmd->numPages = 1;
5274 }
5275 else
5276 {
5277 ASSERT_GUEST_STMT_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
5278 cbMore = cbPageDesc * pCmd->numPages;
5279 }
5280 }
5281 VMSVGA_INC_CMD_SIZE_BREAK(cbMore);
5282 vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
5283# ifdef DEBUG_GMR_ACCESS
5284 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
5285# endif
5286 break;
5287 }
5288# endif // VBOX_WITH_VMSVGA3D
5289 case SVGA_CMD_DEFINE_SCREEN:
5290 {
5291 /* The size of this command is specified by the guest and depends on capabilities. */
5292 SVGAFifoCmdDefineScreen *pCmd = (SVGAFifoCmdDefineScreen *)&pu8Cmd[cbCmd];
5293 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(pCmd->screen.structSize));
5294 ASSERT_GUEST_STMT_BREAK(pCmd->screen.structSize < pThis->svga.cbFIFO, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
5295 RT_UNTRUSTED_VALIDATED_FENCE();
5296
5297 VMSVGA_INC_CMD_SIZE_BREAK(RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize) - sizeof(pCmd->screen.structSize));
5298 vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
5299 break;
5300 }
5301
5302 case SVGA_CMD_DESTROY_SCREEN:
5303 {
5304 SVGAFifoCmdDestroyScreen *pCmd = (SVGAFifoCmdDestroyScreen *)&pu8Cmd[cbCmd];
5305 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5306 vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
5307 break;
5308 }
5309
5310 case SVGA_CMD_DEFINE_GMRFB:
5311 {
5312 SVGAFifoCmdDefineGMRFB *pCmd = (SVGAFifoCmdDefineGMRFB *)&pu8Cmd[cbCmd];
5313 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5314 vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
5315 break;
5316 }
5317
5318 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
5319 {
5320 SVGAFifoCmdBlitGMRFBToScreen *pCmd = (SVGAFifoCmdBlitGMRFBToScreen *)&pu8Cmd[cbCmd];
5321 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5322 vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
5323 break;
5324 }
5325
5326 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
5327 {
5328 SVGAFifoCmdBlitScreenToGMRFB *pCmd = (SVGAFifoCmdBlitScreenToGMRFB *)&pu8Cmd[cbCmd];
5329 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5330 vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
5331 break;
5332 }
5333
5334 case SVGA_CMD_ANNOTATION_FILL:
5335 {
5336 SVGAFifoCmdAnnotationFill *pCmd = (SVGAFifoCmdAnnotationFill *)&pu8Cmd[cbCmd];
5337 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5338 vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
5339 break;
5340 }
5341
5342 case SVGA_CMD_ANNOTATION_COPY:
5343 {
5344 SVGAFifoCmdAnnotationCopy *pCmd = (SVGAFifoCmdAnnotationCopy *)&pu8Cmd[cbCmd];
5345 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
5346 vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
5347 break;
5348 }
5349
5350 default:
5351 {
5352# ifdef VBOX_WITH_VMSVGA3D
5353 if ( cmdId >= SVGA_3D_CMD_BASE
5354 && cmdId < SVGA_3D_CMD_MAX)
5355 {
5356 RT_UNTRUSTED_VALIDATED_FENCE();
5357
5358 /* All 3d commands start with a common header, which defines the identifier and the size
5359 * of the command. The identifier has been already read. Fetch the size.
5360 */
5361 uint32_t const *pcbMore = (uint32_t const *)&pu8Cmd[cbCmd];
5362 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pcbMore));
5363 VMSVGA_INC_CMD_SIZE_BREAK(*pcbMore);
5364 if (RT_LIKELY(pThis->svga.f3DEnabled))
5365 { /* likely */ }
5366 else
5367 {
5368 LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", cmdId));
5369 break;
5370 }
5371
5372 /* Command data begins after the 32 bit command length. */
5373 vmsvgaR3Process3dCmd(pThis, pThisCC, cmdId, *pcbMore, pcbMore + 1);
5374 }
5375 else
5376# endif // VBOX_WITH_VMSVGA3D
5377 {
5378 /* Unsupported command. */
5379 STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
5380 ASSERT_GUEST_MSG_FAILED(("cmdId=%d\n", cmdId));
5381 CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
5382 break;
5383 }
5384 }
5385 }
5386
5387 if (CBstatus != SVGA_CB_STATUS_COMPLETED)
5388 break;
5389
5390 pu8Cmd += cbCmd;
5391 cbRemain -= cbCmd;
5392 }
5393
5394 Assert(cbRemain <= cbCommands);
5395 *poffNextCmd = cbCommands - cbRemain;
5396 return CBstatus;
5397}
5398
5399
5400/** Process command buffers.
5401 *
5402 * @param pDevIns The device instance.
5403 * @param pThis The shared VGA/VMSVGA state.
5404 * @param pThisCC The VGA/VMSVGA state for the current context.
5405 * @param pThread Handle of the FIFO thread.
5406 * @thread FIFO
5407 */
5408static void vmsvgaR3CmdBufProcessBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PPDMTHREAD pThread)
5409{
5410 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5411
5412 for (;;)
5413 {
5414 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
5415 break;
5416
5417 /* See if there is a submitted buffer. */
5418 PVMSVGACMDBUF pCmdBuf = NULL;
5419
5420 int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
5421 AssertRC(rc);
5422
5423 /* It seems that a higher queue index has a higher priority.
5424 * See SVGACBContext in svga_reg.h from latest vmwgfx Linux driver.
5425 */
5426 for (unsigned i = RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs); i > 0; --i)
5427 {
5428 PVMSVGACMDBUFCTX pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[i - 1];
5429 if (pCmdBufCtx)
5430 {
5431 pCmdBuf = RTListRemoveFirst(&pCmdBufCtx->listSubmitted, VMSVGACMDBUF, nodeBuffer);
5432 if (pCmdBuf)
5433 {
5434 Assert(pCmdBufCtx->cSubmitted > 0);
5435 --pCmdBufCtx->cSubmitted;
5436 break;
5437 }
5438 }
5439 }
5440
5441 if (!pCmdBuf)
5442 {
5443 ASMAtomicWriteU32(&pSvgaR3State->fCmdBuf, 0);
5444 RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
5445 break;
5446 }
5447
5448 RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
5449
5450 SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
5451 uint32_t offNextCmd = 0;
5452
5453 /* Process one buffer. */
5454 CBstatus = vmsvgaR3CmdBufProcessCommands(pDevIns, pThis, pThisCC, pCmdBuf->pvCommands, pCmdBuf->hdr.length, &offNextCmd);
5455
5456 uint32_t fIRQ = 0;
5457 if (!RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_NO_IRQ))
5458 fIRQ |= SVGA_IRQFLAG_COMMAND_BUFFER;
5459 if (CBstatus == SVGA_CB_STATUS_COMMAND_ERROR)
5460 fIRQ |= SVGA_IRQFLAG_ERROR;
5461
5462 vmsvgaR3CmdBufWriteStatus(pDevIns, pCmdBuf->GCPhysCB, CBstatus, offNextCmd);
5463 if (fIRQ)
5464 vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, fIRQ);
5465
5466 vmsvgaR3CmdBufFree(pCmdBuf);
5467 }
5468}
5469
5470
5471/**
5472 * Worker for vmsvgaR3FifoThread that handles an external command.
5473 *
5474 * @param pDevIns The device instance.
5475 * @param pThis The shared VGA/VMSVGA instance data.
5476 * @param pThisCC The VGA/VMSVGA state for ring-3.
5477 */
5478static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
5479{
5480 uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
5481 switch (pThis->svga.u8FIFOExtCommand)
5482 {
5483 case VMSVGA_FIFO_EXTCMD_RESET:
5484 Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
5485 Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
5486
5487 vmsvgaR3ResetScreens(pThis, pThisCC);
5488# ifdef VBOX_WITH_VMSVGA3D
5489 if (pThis->svga.f3DEnabled)
5490 {
5491 /* The 3d subsystem must be reset from the fifo thread. */
5492 vmsvga3dReset(pThisCC);
5493 }
5494# endif
5495 break;
5496
5497 case VMSVGA_FIFO_EXTCMD_POWEROFF:
5498 Log(("vmsvgaR3FifoLoop: power off.\n"));
5499 Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
5500
5501 /* The screens must be reset on the FIFO thread, because they may use 3D resources. */
5502 vmsvgaR3ResetScreens(pThis, pThisCC);
5503 break;
5504
5505 case VMSVGA_FIFO_EXTCMD_TERMINATE:
5506 Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
5507 Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
5508# ifdef VBOX_WITH_VMSVGA3D
5509 if (pThis->svga.f3DEnabled)
5510 {
5511 /* The 3d subsystem must be shut down from the fifo thread. */
5512 vmsvga3dTerminate(pThisCC);
5513 }
5514# endif
5515 break;
5516
5517 case VMSVGA_FIFO_EXTCMD_SAVESTATE:
5518 {
5519 Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
5520 PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
5521 AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
5522 vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
5523# ifdef VBOX_WITH_VMSVGA3D
5524 if (pThis->svga.f3DEnabled)
5525 vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
5526# endif
5527 break;
5528 }
5529
5530 case VMSVGA_FIFO_EXTCMD_LOADSTATE:
5531 {
5532 Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
5533 PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
5534 AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
5535 vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
5536# ifdef VBOX_WITH_VMSVGA3D
5537 if (pThis->svga.f3DEnabled)
5538 vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
5539# endif
5540 break;
5541 }
5542
5543 case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
5544 {
5545# ifdef VBOX_WITH_VMSVGA3D
5546 uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
5547 Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
5548 vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
5549# endif
5550 break;
5551 }
5552
5553
5554 default:
5555 AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
5556 break;
5557 }
5558
5559 /*
5560 * Signal the end of the external command.
5561 */
5562 pThisCC->svga.pvFIFOExtCmdParam = NULL;
5563 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
5564 ASMMemoryFence(); /* paranoia^2 */
5565 int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
5566 AssertLogRelRC(rc);
5567}
5568
5569/**
5570 * Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
5571 * doing a job on the FIFO thread (even when it's officially suspended).
5572 *
5573 * @returns VBox status code (fully asserted).
5574 * @param pDevIns The device instance.
5575 * @param pThis The shared VGA/VMSVGA instance data.
5576 * @param pThisCC The VGA/VMSVGA state for ring-3.
5577 * @param uExtCmd The command to execute on the FIFO thread.
5578 * @param pvParam Pointer to command parameters.
5579 * @param cMsWait The time to wait for the command, given in
5580 * milliseconds.
5581 */
5582static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
5583 uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
5584{
5585 Assert(cMsWait >= RT_MS_1SEC * 5);
5586 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
5587 ("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
5588
5589 int rc;
5590 PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
5591 PDMTHREADSTATE enmState = pThread->enmState;
5592 if (enmState == PDMTHREADSTATE_SUSPENDED)
5593 {
5594 /*
5595 * The thread is suspended, we have to temporarily wake it up so it can
5596 * perform the task.
5597 * (We ASSUME not racing code here, both wrt thread state and ext commands.)
5598 */
5599 Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
5600 /* Post the request. */
5601 pThis->svga.fFifoExtCommandWakeup = true;
5602 pThisCC->svga.pvFIFOExtCmdParam = pvParam;
5603 pThis->svga.u8FIFOExtCommand = uExtCmd;
5604 ASMMemoryFence(); /* paranoia^3 */
5605
5606 /* Resume the thread. */
5607 rc = PDMDevHlpThreadResume(pDevIns, pThread);
5608 AssertLogRelRC(rc);
5609 if (RT_SUCCESS(rc))
5610 {
5611 /* Wait. Take care in case the semaphore was already posted (same as below). */
5612 rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
5613 if ( rc == VINF_SUCCESS
5614 && pThis->svga.u8FIFOExtCommand == uExtCmd)
5615 rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
5616 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
5617 ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
5618
5619 /* suspend the thread */
5620 pThis->svga.fFifoExtCommandWakeup = false;
5621 int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
5622 AssertLogRelRC(rc2);
5623 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
5624 rc = rc2;
5625 }
5626 pThis->svga.fFifoExtCommandWakeup = false;
5627 pThisCC->svga.pvFIFOExtCmdParam = NULL;
5628 }
5629 else if (enmState == PDMTHREADSTATE_RUNNING)
5630 {
5631 /*
5632 * The thread is running, should only happen during reset and vmsvga3dsfc.
5633 * We ASSUME not racing code here, both wrt thread state and ext commands.
5634 */
5635 Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
5636 Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET || uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS || uExtCmd == VMSVGA_FIFO_EXTCMD_POWEROFF);
5637
5638 /* Post the request. */
5639 pThisCC->svga.pvFIFOExtCmdParam = pvParam;
5640 pThis->svga.u8FIFOExtCommand = uExtCmd;
5641 ASMMemoryFence(); /* paranoia^2 */
5642 rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5643 AssertLogRelRC(rc);
5644
5645 /* Wait. Take care in case the semaphore was already posted (same as above). */
5646 rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
5647 if ( rc == VINF_SUCCESS
5648 && pThis->svga.u8FIFOExtCommand == uExtCmd)
5649 rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
5650 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
5651 ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
5652
5653 pThisCC->svga.pvFIFOExtCmdParam = NULL;
5654 }
5655 else
5656 {
5657 /*
5658 * Something is wrong with the thread!
5659 */
5660 AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
5661 rc = VERR_INVALID_STATE;
5662 }
5663 return rc;
5664}
5665
5666
5667/**
5668 * Marks the FIFO non-busy, notifying any waiting EMTs.
5669 *
5670 * @param pDevIns The device instance.
5671 * @param pThis The shared VGA/VMSVGA instance data.
5672 * @param pThisCC The VGA/VMSVGA state for ring-3.
5673 * @param pSVGAState Pointer to the ring-3 only SVGA state data.
5674 * @param offFifoMin The start byte offset of the command FIFO.
5675 */
5676static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
5677{
5678 ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO | VMSVGA_BUSY_F_EMT_FORCE));
5679 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
5680 vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
5681
5682 /* Wake up any waiting EMTs. */
5683 if (pSVGAState->cBusyDelayedEmts > 0)
5684 {
5685# ifdef VMSVGA_USE_EMT_HALT_CODE
5686 PVM pVM = PDMDevHlpGetVM(pDevIns);
5687 VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
5688 if (idCpu != NIL_VMCPUID)
5689 {
5690 VMR3NotifyCpuDeviceReady(pVM, idCpu);
5691 while (idCpu-- > 0)
5692 if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
5693 VMR3NotifyCpuDeviceReady(pVM, idCpu);
5694 }
5695# else
5696 int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
5697 AssertRC(rc2);
5698# endif
5699 }
5700}
5701
5702/**
5703 * Reads (more) payload into the command buffer.
5704 *
5705 * @returns pbBounceBuf on success
5706 * @retval (void *)1 if the thread was requested to stop.
5707 * @retval NULL on FIFO error.
5708 *
5709 * @param cbPayloadReq The number of bytes of payload requested.
5710 * @param pFIFO The FIFO.
5711 * @param offCurrentCmd The FIFO byte offset of the current command.
5712 * @param offFifoMin The start byte offset of the command FIFO.
5713 * @param offFifoMax The end byte offset of the command FIFO.
5714 * @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
5715 * always sufficient size.
5716 * @param pcbAlreadyRead How much payload we've already read into the bounce
5717 * buffer. (We will NEVER re-read anything.)
5718 * @param pThread The calling PDM thread handle.
5719 * @param pThis The shared VGA/VMSVGA instance data.
5720 * @param pSVGAState Pointer to the ring-3 only SVGA state data. For
5721 * statistics collection.
5722 * @param pDevIns The device instance.
5723 */
5724static void *vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
5725 uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
5726 uint8_t *pbBounceBuf, uint32_t *pcbAlreadyRead,
5727 PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
5728{
5729 Assert(pbBounceBuf);
5730 Assert(pcbAlreadyRead);
5731 Assert(offFifoMin < offFifoMax);
5732 Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
5733 Assert(offFifoMax <= pThis->svga.cbFIFO);
5734
5735 /*
5736 * Check if the requested payload size has already been satisfied .
5737 * .
5738 * When called to read more, the caller is responsible for making sure the .
5739 * new command size (cbRequsted) never is smaller than what has already .
5740 * been read.
5741 */
5742 uint32_t cbAlreadyRead = *pcbAlreadyRead;
5743 if (cbPayloadReq <= cbAlreadyRead)
5744 {
5745 AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
5746 return pbBounceBuf;
5747 }
5748
5749 /*
5750 * Commands bigger than the fifo buffer are invalid.
5751 */
5752 uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
5753 AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
5754 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
5755 NULL);
5756
5757 /*
5758 * Move offCurrentCmd past the command dword.
5759 */
5760 offCurrentCmd += sizeof(uint32_t);
5761 if (offCurrentCmd >= offFifoMax)
5762 offCurrentCmd = offFifoMin;
5763
5764 /*
5765 * Do we have sufficient payload data available already?
5766 * The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
5767 */
5768 uint32_t cbAfter, cbBefore;
5769 uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
5770 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
5771 if (offNextCmd >= offCurrentCmd)
5772 {
5773 if (RT_LIKELY(offNextCmd < offFifoMax))
5774 cbAfter = offNextCmd - offCurrentCmd;
5775 else
5776 {
5777 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
5778 LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
5779 offNextCmd, offFifoMin, offFifoMax));
5780 cbAfter = offFifoMax - offCurrentCmd;
5781 }
5782 cbBefore = 0;
5783 }
5784 else
5785 {
5786 cbAfter = offFifoMax - offCurrentCmd;
5787 if (offNextCmd >= offFifoMin)
5788 cbBefore = offNextCmd - offFifoMin;
5789 else
5790 {
5791 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
5792 LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
5793 offNextCmd, offFifoMin, offFifoMax));
5794 cbBefore = 0;
5795 }
5796 }
5797 if (cbAfter + cbBefore < cbPayloadReq)
5798 {
5799 /*
5800 * Insufficient, must wait for it to arrive.
5801 */
5802/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
5803 STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
5804 for (uint32_t i = 0;; i++)
5805 {
5806 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
5807 {
5808 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
5809 return (void *)(uintptr_t)1;
5810 }
5811 Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
5812 cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
5813
5814 PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
5815
5816 offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
5817 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
5818 if (offNextCmd >= offCurrentCmd)
5819 {
5820 cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
5821 cbBefore = 0;
5822 }
5823 else
5824 {
5825 cbAfter = offFifoMax - offCurrentCmd;
5826 cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
5827 }
5828
5829 if (cbAfter + cbBefore >= cbPayloadReq)
5830 break;
5831 }
5832 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
5833 }
5834
5835 /*
5836 * Copy out the memory and update what pcbAlreadyRead points to.
5837 */
5838 if (cbAfter >= cbPayloadReq)
5839 memcpy(pbBounceBuf + cbAlreadyRead,
5840 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
5841 cbPayloadReq - cbAlreadyRead);
5842 else
5843 {
5844 LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
5845 if (cbAlreadyRead < cbAfter)
5846 {
5847 memcpy(pbBounceBuf + cbAlreadyRead,
5848 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
5849 cbAfter - cbAlreadyRead);
5850 cbAlreadyRead = cbAfter;
5851 }
5852 memcpy(pbBounceBuf + cbAlreadyRead,
5853 (uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
5854 cbPayloadReq - cbAlreadyRead);
5855 }
5856 *pcbAlreadyRead = cbPayloadReq;
5857 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
5858 return pbBounceBuf;
5859}
5860
5861
5862/**
5863 * Sends cursor position and visibility information from the FIFO to the front-end.
5864 * @returns SVGA_FIFO_CURSOR_COUNT value used.
5865 */
5866static uint32_t
5867vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
5868 uint32_t offFifoMin, uint32_t uCursorUpdateCount,
5869 uint32_t *pxLast, uint32_t *pyLast, uint32_t *pfLastVisible)
5870{
5871 /*
5872 * Check if the cursor update counter has changed and try get a stable
5873 * set of values if it has. This is race-prone, especially consindering
5874 * the screen ID, but little we can do about that.
5875 */
5876 uint32_t x, y, fVisible, idScreen;
5877 for (uint32_t i = 0; ; i++)
5878 {
5879 x = pFIFO[SVGA_FIFO_CURSOR_X];
5880 y = pFIFO[SVGA_FIFO_CURSOR_Y];
5881 fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
5882 idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
5883 ? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
5884 if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
5885 || i > 3)
5886 break;
5887 if (i == 0)
5888 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
5889 ASMNopPause();
5890 uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
5891 }
5892
5893 /*
5894 * Check if anything has changed, as calling into pDrv is not light-weight.
5895 */
5896 if ( *pxLast == x
5897 && *pyLast == y
5898 && (idScreen != SVGA_ID_INVALID || *pfLastVisible == fVisible))
5899 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
5900 else
5901 {
5902 /*
5903 * Detected changes.
5904 *
5905 * We handle global, not per-screen visibility information by sending
5906 * pfnVBVAMousePointerShape without shape data.
5907 */
5908 *pxLast = x;
5909 *pyLast = y;
5910 uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
5911 if (idScreen != SVGA_ID_INVALID)
5912 fFlags |= VBVA_CURSOR_SCREEN_RELATIVE;
5913 else if (*pfLastVisible != fVisible)
5914 {
5915 LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
5916 *pfLastVisible = fVisible;
5917 pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
5918 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
5919 }
5920 pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
5921 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
5922 }
5923
5924 /*
5925 * Update done. Signal this to the guest.
5926 */
5927 pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
5928
5929 return uCursorUpdateCount;
5930}
5931
5932
5933/**
5934 * Checks if there is work to be done, either cursor updating or FIFO commands.
5935 *
5936 * @returns true if pending work, false if not.
5937 * @param pThisCC The VGA/VMSVGA state for ring-3.
5938 * @param uLastCursorCount The last cursor update counter value.
5939 */
5940DECLINLINE(bool) vmsvgaR3FifoHasWork(PVGASTATECC pThisCC, uint32_t uLastCursorCount)
5941{
5942 /* If FIFO does not exist than there is nothing to do. Command buffers also require the enabled FIFO. */
5943 uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
5944 AssertReturn(pFIFO, false);
5945
5946 if (vmsvgaR3CmdBufHasWork(pThisCC))
5947 return true;
5948
5949 if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
5950 return true;
5951
5952 if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
5953 && VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
5954 return true;
5955
5956 return false;
5957}
5958
5959
5960/**
5961 * Called by the VGA refresh timer to wake up the FIFO thread when needed.
5962 *
5963 * @param pDevIns The device instance.
5964 * @param pThis The shared VGA/VMSVGA instance data.
5965 * @param pThisCC The VGA/VMSVGA state for ring-3.
5966 */
5967void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
5968{
5969 /* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
5970 to recheck it before doing the signalling. */
5971 if ( vmsvgaR3FifoHasWork(pThisCC, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
5972 && pThis->svga.fFIFOThreadSleeping)
5973 {
5974 int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5975 AssertRC(rc);
5976 STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
5977 }
5978}
5979
5980
5981/**
5982 * Called by the FIFO thread to process pending actions.
5983 *
5984 * @param pDevIns The device instance.
5985 * @param pThis The shared VGA/VMSVGA instance data.
5986 * @param pThisCC The VGA/VMSVGA state for ring-3.
5987 */
5988void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
5989{
5990 RT_NOREF(pDevIns);
5991
5992 /* Currently just mode changes. */
5993 if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
5994 {
5995 vmsvgaR3ChangeMode(pThis, pThisCC);
5996# ifdef VBOX_WITH_VMSVGA3D
5997 if (pThisCC->svga.p3dState != NULL)
5998 vmsvga3dChangeMode(pThisCC);
5999# endif
6000 }
6001}
6002
6003
6004/*
6005 * These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
6006 * even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
6007 */
6008/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
6009 * Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
6010 *
6011 * Will break out of the switch on failure.
6012 * Will restart and quit the loop if the thread was requested to stop.
6013 *
6014 * @param a_PtrVar Request variable pointer.
6015 * @param a_Type Request typedef (not pointer) for casting.
6016 * @param a_cbPayloadReq How much payload to fetch.
6017 * @remarks Accesses a bunch of variables in the current scope!
6018 */
6019# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
6020 if (1) { \
6021 (a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
6022 pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
6023 if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
6024 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
6025 } else do {} while (0)
6026/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
6027 * Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
6028 * buffer after figuring out the actual command size.
6029 *
6030 * Will break out of the switch on failure.
6031 *
6032 * @param a_PtrVar Request variable pointer.
6033 * @param a_Type Request typedef (not pointer) for casting.
6034 * @param a_cbPayloadReq How much payload to fetch.
6035 * @remarks Accesses a bunch of variables in the current scope!
6036 */
6037# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
6038 if (1) { \
6039 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
6040 } else do {} while (0)
6041
6042/**
6043 * @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
6044 */
6045static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
6046{
6047 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6048 PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6049 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6050 int rc;
6051
6052# if defined(VBOX_WITH_VMSVGA3D) && defined(RT_OS_LINUX)
6053 if (pThis->svga.f3DEnabled)
6054 {
6055 /* The FIFO thread may use X API for accelerated screen output. */
6056 XInitThreads();
6057 }
6058# endif
6059
6060 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
6061 return VINF_SUCCESS;
6062
6063 /*
6064 * Special mode where we only execute an external command and the go back
6065 * to being suspended. Currently, all ext cmds ends up here, with the reset
6066 * one also being eligble for runtime execution further down as well.
6067 */
6068 if (pThis->svga.fFifoExtCommandWakeup)
6069 {
6070 vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
6071 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
6072 if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
6073 PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
6074 else
6075 vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
6076 return VINF_SUCCESS;
6077 }
6078
6079
6080 /*
6081 * Signal the semaphore to make sure we don't wait for 250ms after a
6082 * suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
6083 */
6084 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
6085
6086 /*
6087 * Allocate a bounce buffer for command we get from the FIFO.
6088 * (All code must return via the end of the function to free this buffer.)
6089 */
6090 uint8_t *pbBounceBuf = (uint8_t *)RTMemAllocZ(pThis->svga.cbFIFO);
6091 AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
6092
6093 /*
6094 * Polling/sleep interval config.
6095 *
6096 * We wait for an a short interval if the guest has recently given us work
6097 * to do, but the interval increases the longer we're kept idle. Once we've
6098 * reached the refresh timer interval, we'll switch to extended waits,
6099 * depending on it or the guest to kick us into action when needed.
6100 *
6101 * Should the refresh time go fishing, we'll just continue increasing the
6102 * sleep length till we reaches the 250 ms max after about 16 seconds.
6103 */
6104 RTMSINTERVAL const cMsMinSleep = 16;
6105 RTMSINTERVAL const cMsIncSleep = 2;
6106 RTMSINTERVAL const cMsMaxSleep = 250;
6107 RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
6108 RTMSINTERVAL cMsSleep = cMsMaxSleep;
6109
6110 /*
6111 * Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
6112 *
6113 * Initialize with values that will detect an update from the guest.
6114 * Make sure that if the guest never updates the cursor position, then the device does not report it.
6115 * The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
6116 * xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
6117 */
6118 uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
6119 pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
6120 uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
6121 uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
6122 uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
6123
6124 /*
6125 * The FIFO loop.
6126 */
6127 LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
6128 bool fBadOrDisabledFifo = false;
6129 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
6130 {
6131# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
6132 /*
6133 * Should service the run loop every so often.
6134 */
6135 if (pThis->svga.f3DEnabled)
6136 vmsvga3dCocoaServiceRunLoop();
6137# endif
6138
6139 /* First check any pending actions. */
6140 vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
6141
6142 /*
6143 * Unless there's already work pending, go to sleep for a short while.
6144 * (See polling/sleep interval config above.)
6145 */
6146 if ( fBadOrDisabledFifo
6147 || !vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
6148 {
6149 ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
6150 Assert(pThis->cMilliesRefreshInterval > 0);
6151 if (cMsSleep < pThis->cMilliesRefreshInterval)
6152 rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
6153 else
6154 {
6155# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
6156 int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
6157 AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
6158# endif
6159 if ( !fBadOrDisabledFifo
6160 && vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
6161 rc = VINF_SUCCESS;
6162 else
6163 {
6164 STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
6165 rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
6166 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
6167 }
6168 }
6169 ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
6170 AssertBreak(RT_SUCCESS(rc) || rc == VERR_TIMEOUT || rc == VERR_INTERRUPTED);
6171 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
6172 {
6173 LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
6174 break;
6175 }
6176 }
6177 else
6178 rc = VINF_SUCCESS;
6179 fBadOrDisabledFifo = false;
6180 if (rc == VERR_TIMEOUT)
6181 {
6182 if (!vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
6183 {
6184 cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
6185 continue;
6186 }
6187 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
6188
6189 Log(("vmsvgaR3FifoLoop: timeout\n"));
6190 }
6191 else if (vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
6192 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
6193 cMsSleep = cMsMinSleep;
6194
6195 Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
6196 Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
6197 Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
6198
6199 /*
6200 * Handle external commands (currently only reset).
6201 */
6202 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
6203 {
6204 vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
6205 continue;
6206 }
6207
6208 /*
6209 * The device must be enabled and configured.
6210 */
6211 if ( !pThis->svga.fEnabled
6212 || !pThis->svga.fConfigured)
6213 {
6214 vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
6215 fBadOrDisabledFifo = true;
6216 cMsSleep = cMsMaxSleep; /* cheat */
6217 continue;
6218 }
6219
6220 /*
6221 * Get and check the min/max values. We ASSUME that they will remain
6222 * unchanged while we process requests. A further ASSUMPTION is that
6223 * the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
6224 * we don't read it back while in the loop.
6225 */
6226 uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
6227 uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
6228 uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
6229 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
6230 if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
6231 || offFifoMax <= offFifoMin
6232 || offFifoMax > pThis->svga.cbFIFO
6233 || (offFifoMax & 3) != 0
6234 || (offFifoMin & 3) != 0
6235 || offCurrentCmd < offFifoMin
6236 || offCurrentCmd > offFifoMax))
6237 {
6238 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
6239 LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
6240 vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
6241 fBadOrDisabledFifo = true;
6242 continue;
6243 }
6244 RT_UNTRUSTED_VALIDATED_FENCE();
6245 if (RT_UNLIKELY(offCurrentCmd & 3))
6246 {
6247 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
6248 LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
6249 offCurrentCmd &= ~UINT32_C(3);
6250 }
6251
6252 /*
6253 * Update the cursor position before we start on the FIFO commands.
6254 */
6255 /** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
6256 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
6257 {
6258 uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
6259 if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
6260 { /* halfways likely */ }
6261 else
6262 {
6263 uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
6264 &xLastCursor, &yLastCursor, &fLastCursorVisible);
6265 ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
6266 }
6267 }
6268
6269 /*
6270 * Mark the FIFO as busy.
6271 */
6272 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
6273 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
6274 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
6275
6276 /*
6277 * Process all submitted command buffers.
6278 */
6279 vmsvgaR3CmdBufProcessBuffers(pDevIns, pThis, pThisCC, pThread);
6280
6281 /*
6282 * Execute all queued FIFO commands.
6283 * Quit if pending external command or changes in the thread state.
6284 */
6285 bool fDone = false;
6286 while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
6287 && pThread->enmState == PDMTHREADSTATE_RUNNING)
6288 {
6289 uint32_t cbPayload = 0;
6290 uint32_t u32IrqStatus = 0;
6291
6292 Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
6293
6294 /* First check any pending actions. */
6295 vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
6296
6297 /* Check for pending external commands (reset). */
6298 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
6299 break;
6300
6301 /*
6302 * Process the command.
6303 */
6304 /* 'enmCmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
6305 * warning. Because we implement some obsolete and deprecated commands, which are not included in
6306 * the SVGAFifoCmdId enum in the VMSVGA headers anymore.
6307 */
6308 uint32_t const enmCmdId = pFIFO[offCurrentCmd / sizeof(uint32_t)];
6309 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
6310 LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s %d\n",
6311 offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
6312 switch (enmCmdId)
6313 {
6314 case SVGA_CMD_INVALID_CMD:
6315 /* Nothing to do. */
6316 STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
6317 break;
6318
6319 case SVGA_CMD_FENCE:
6320 {
6321 SVGAFifoCmdFence *pCmdFence;
6322 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
6323 STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
6324 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
6325 {
6326 Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %#x\n", pCmdFence->fence));
6327 pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
6328
6329 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
6330 {
6331 Log(("vmsvgaR3FifoLoop: any fence irq\n"));
6332 u32IrqStatus |= SVGA_IRQFLAG_ANY_FENCE;
6333 }
6334 else
6335 if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
6336 && (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
6337 && pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
6338 {
6339 Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%#x)\n", pCmdFence->fence));
6340 u32IrqStatus |= SVGA_IRQFLAG_FENCE_GOAL;
6341 }
6342 }
6343 else
6344 Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
6345 break;
6346 }
6347
6348 case SVGA_CMD_UPDATE:
6349 {
6350 SVGAFifoCmdUpdate *pCmd;
6351 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdate, sizeof(*pCmd));
6352 vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
6353 break;
6354 }
6355
6356 case SVGA_CMD_UPDATE_VERBOSE:
6357 {
6358 SVGAFifoCmdUpdateVerbose *pCmd;
6359 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdateVerbose, sizeof(*pCmd));
6360 vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
6361 break;
6362 }
6363
6364 case SVGA_CMD_DEFINE_CURSOR:
6365 {
6366 /* Followed by bitmap data. */
6367 SVGAFifoCmdDefineCursor *pCmd;
6368 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, sizeof(*pCmd));
6369
6370 /* Figure out the size of the bitmap data. */
6371 ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
6372 ASSERT_GUEST_BREAK(pCmd->andMaskDepth <= 32);
6373 ASSERT_GUEST_BREAK(pCmd->xorMaskDepth <= 32);
6374 RT_UNTRUSTED_VALIDATED_FENCE();
6375
6376 uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
6377 uint32_t const cbAndMask = cbAndLine * pCmd->height;
6378 uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
6379 uint32_t const cbXorMask = cbXorLine * pCmd->height;
6380
6381 uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineCursor) + cbAndMask + cbXorMask;
6382 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, cbCmd);
6383 vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
6384 break;
6385 }
6386
6387 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
6388 {
6389 /* Followed by bitmap data. */
6390 SVGAFifoCmdDefineAlphaCursor *pCmd;
6391 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCmd));
6392
6393 /* Figure out the size of the bitmap data. */
6394 ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
6395
6396 uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCmd->width * pCmd->height * sizeof(uint32_t) /* 32-bit BRGA format */;
6397 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, cbCmd);
6398 vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
6399 break;
6400 }
6401
6402 case SVGA_CMD_MOVE_CURSOR:
6403 {
6404 /* Deprecated; there should be no driver which *requires* this command. However, if
6405 * we do ecncounter this command, it might be useful to not get the FIFO completely out of
6406 * alignment.
6407 * May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
6408 */
6409 SVGAFifoCmdMoveCursor *pCmd;
6410 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdMoveCursor, sizeof(*pCmd));
6411 vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
6412 break;
6413 }
6414
6415 case SVGA_CMD_DISPLAY_CURSOR:
6416 {
6417 /* Deprecated; there should be no driver which *requires* this command. However, if
6418 * we do ecncounter this command, it might be useful to not get the FIFO completely out of
6419 * alignment.
6420 * May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
6421 */
6422 SVGAFifoCmdDisplayCursor *pCmd;
6423 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDisplayCursor, sizeof(*pCmd));
6424 vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
6425 break;
6426 }
6427
6428 case SVGA_CMD_RECT_FILL:
6429 {
6430 SVGAFifoCmdRectFill *pCmd;
6431 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectFill, sizeof(*pCmd));
6432 vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
6433 break;
6434 }
6435
6436 case SVGA_CMD_RECT_COPY:
6437 {
6438 SVGAFifoCmdRectCopy *pCmd;
6439 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectCopy, sizeof(*pCmd));
6440 vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
6441 break;
6442 }
6443
6444 case SVGA_CMD_RECT_ROP_COPY:
6445 {
6446 SVGAFifoCmdRectRopCopy *pCmd;
6447 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectRopCopy, sizeof(*pCmd));
6448 vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
6449 break;
6450 }
6451
6452 case SVGA_CMD_ESCAPE:
6453 {
6454 /* Followed by 'size' bytes of data. */
6455 SVGAFifoCmdEscape *pCmd;
6456 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, sizeof(*pCmd));
6457
6458 ASSERT_GUEST_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape));
6459 RT_UNTRUSTED_VALIDATED_FENCE();
6460
6461 uint32_t const cbCmd = sizeof(SVGAFifoCmdEscape) + pCmd->size;
6462 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, cbCmd);
6463 vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
6464 break;
6465 }
6466# ifdef VBOX_WITH_VMSVGA3D
6467 case SVGA_CMD_DEFINE_GMR2:
6468 {
6469 SVGAFifoCmdDefineGMR2 *pCmd;
6470 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
6471 vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
6472 break;
6473 }
6474
6475 case SVGA_CMD_REMAP_GMR2:
6476 {
6477 /* Followed by page descriptors or guest ptr. */
6478 SVGAFifoCmdRemapGMR2 *pCmd;
6479 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
6480
6481 /* Calculate the size of what comes after next and fetch it. */
6482 uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
6483 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
6484 cbCmd += sizeof(SVGAGuestPtr);
6485 else
6486 {
6487 uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
6488 if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
6489 {
6490 cbCmd += cbPageDesc;
6491 pCmd->numPages = 1;
6492 }
6493 else
6494 {
6495 ASSERT_GUEST_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
6496 cbCmd += cbPageDesc * pCmd->numPages;
6497 }
6498 }
6499 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
6500 vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
6501# ifdef DEBUG_GMR_ACCESS
6502 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
6503# endif
6504 break;
6505 }
6506# endif // VBOX_WITH_VMSVGA3D
6507 case SVGA_CMD_DEFINE_SCREEN:
6508 {
6509 /* The size of this command is specified by the guest and depends on capabilities. */
6510 Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
6511
6512 SVGAFifoCmdDefineScreen *pCmd;
6513 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
6514 AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
6515 RT_UNTRUSTED_VALIDATED_FENCE();
6516
6517 RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
6518 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
6519 vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
6520 break;
6521 }
6522
6523 case SVGA_CMD_DESTROY_SCREEN:
6524 {
6525 SVGAFifoCmdDestroyScreen *pCmd;
6526 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
6527 vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
6528 break;
6529 }
6530
6531 case SVGA_CMD_DEFINE_GMRFB:
6532 {
6533 SVGAFifoCmdDefineGMRFB *pCmd;
6534 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
6535 vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
6536 break;
6537 }
6538
6539 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
6540 {
6541 SVGAFifoCmdBlitGMRFBToScreen *pCmd;
6542 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
6543 vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
6544 break;
6545 }
6546
6547 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
6548 {
6549 SVGAFifoCmdBlitScreenToGMRFB *pCmd;
6550 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
6551 vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
6552 break;
6553 }
6554
6555 case SVGA_CMD_ANNOTATION_FILL:
6556 {
6557 SVGAFifoCmdAnnotationFill *pCmd;
6558 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
6559 vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
6560 break;
6561 }
6562
6563 case SVGA_CMD_ANNOTATION_COPY:
6564 {
6565 SVGAFifoCmdAnnotationCopy *pCmd;
6566 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
6567 vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
6568 break;
6569 }
6570
6571 default:
6572# ifdef VBOX_WITH_VMSVGA3D
6573 if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
6574 && (int)enmCmdId < SVGA_3D_CMD_MAX)
6575 {
6576 RT_UNTRUSTED_VALIDATED_FENCE();
6577
6578 /* All 3d commands start with a common header, which defines the identifier and the size
6579 * of the command. The identifier has been already read from FIFO. Fetch the size.
6580 */
6581 uint32_t *pcbCmd;
6582 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pcbCmd, uint32_t, sizeof(*pcbCmd));
6583 uint32_t const cbCmd = *pcbCmd;
6584 AssertBreak(cbCmd < pThis->svga.cbFIFO);
6585 uint32_t *pu32Cmd;
6586 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pu32Cmd, uint32_t, sizeof(*pcbCmd) + cbCmd);
6587 pu32Cmd++; /* Skip the command size. */
6588
6589 if (RT_LIKELY(pThis->svga.f3DEnabled))
6590 { /* likely */ }
6591 else
6592 {
6593 LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", enmCmdId));
6594 break;
6595 }
6596
6597 vmsvgaR3Process3dCmd(pThis, pThisCC, enmCmdId, cbCmd, pu32Cmd);
6598 }
6599 else
6600# endif // VBOX_WITH_VMSVGA3D
6601 {
6602 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
6603 AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
6604 }
6605 }
6606
6607 /* Go to the next slot */
6608 Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
6609 offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
6610 if (offCurrentCmd >= offFifoMax)
6611 {
6612 offCurrentCmd -= offFifoMax - offFifoMin;
6613 Assert(offCurrentCmd >= offFifoMin);
6614 Assert(offCurrentCmd < offFifoMax);
6615 }
6616 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
6617 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
6618
6619 /*
6620 * Raise IRQ if required. Must enter the critical section here
6621 * before making final decisions here, otherwise cubebench and
6622 * others may end up waiting forever.
6623 */
6624 if ( u32IrqStatus
6625 || (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
6626 {
6627 int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
6628 AssertRC(rc2);
6629
6630 /* FIFO progress might trigger an interrupt. */
6631 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
6632 {
6633 Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
6634 u32IrqStatus |= SVGA_IRQFLAG_FIFO_PROGRESS;
6635 }
6636
6637 /* Unmasked IRQ pending? */
6638 if (pThis->svga.u32IrqMask & u32IrqStatus)
6639 {
6640 Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
6641 ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
6642 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
6643 }
6644
6645 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
6646 }
6647 }
6648
6649 /* If really done, clear the busy flag. */
6650 if (fDone)
6651 {
6652 Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
6653 vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
6654 }
6655 }
6656
6657 /*
6658 * Free the bounce buffer. (There are no returns above!)
6659 */
6660 RTMemFree(pbBounceBuf);
6661
6662 return VINF_SUCCESS;
6663}
6664
6665#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
6666#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
6667
6668#ifdef VBOX_WITH_VMSVGA3D
6669/**
6670 * Free the specified GMR
6671 *
6672 * @param pThisCC The VGA/VMSVGA state for ring-3.
6673 * @param idGMR GMR id
6674 */
6675static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
6676{
6677 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6678
6679 /* Free the old descriptor if present. */
6680 PGMR pGMR = &pSVGAState->paGMR[idGMR];
6681 if ( pGMR->numDescriptors
6682 || pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
6683 {
6684# ifdef DEBUG_GMR_ACCESS
6685 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
6686# endif
6687
6688 Assert(pGMR->paDesc);
6689 RTMemFree(pGMR->paDesc);
6690 pGMR->paDesc = NULL;
6691 pGMR->numDescriptors = 0;
6692 pGMR->cbTotal = 0;
6693 pGMR->cMaxPages = 0;
6694 }
6695 Assert(!pGMR->cMaxPages);
6696 Assert(!pGMR->cbTotal);
6697}
6698#endif /* VBOX_WITH_VMSVGA3D */
6699
6700/**
6701 * Copy between a GMR and a host memory buffer.
6702 *
6703 * @returns VBox status code.
6704 * @param pThis The shared VGA/VMSVGA instance data.
6705 * @param pThisCC The VGA/VMSVGA state for ring-3.
6706 * @param enmTransferType Transfer type (read/write)
6707 * @param pbHstBuf Host buffer pointer (valid)
6708 * @param cbHstBuf Size of host buffer (valid)
6709 * @param offHst Host buffer offset of the first scanline
6710 * @param cbHstPitch Destination buffer pitch
6711 * @param gstPtr GMR description
6712 * @param offGst Guest buffer offset of the first scanline
6713 * @param cbGstPitch Guest buffer pitch
6714 * @param cbWidth Width in bytes to copy
6715 * @param cHeight Number of scanllines to copy
6716 */
6717int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
6718 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
6719 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
6720 uint32_t cbWidth, uint32_t cHeight)
6721{
6722 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6723 PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
6724 int rc;
6725
6726 LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
6727 enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
6728 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6729 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
6730 AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
6731
6732 PGMR pGMR;
6733 uint32_t cbGmr; /* The GMR size in bytes. */
6734 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
6735 {
6736 pGMR = NULL;
6737 cbGmr = pThis->vram_size;
6738 }
6739 else
6740 {
6741 AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
6742 RT_UNTRUSTED_VALIDATED_FENCE();
6743 pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
6744 cbGmr = pGMR->cbTotal;
6745 }
6746
6747 /*
6748 * GMR
6749 */
6750 /* Calculate GMR offset of the data to be copied. */
6751 AssertMsgReturn(gstPtr.offset < cbGmr,
6752 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6753 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6754 VERR_INVALID_PARAMETER);
6755 RT_UNTRUSTED_VALIDATED_FENCE();
6756 AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
6757 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6758 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6759 VERR_INVALID_PARAMETER);
6760 RT_UNTRUSTED_VALIDATED_FENCE();
6761 uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
6762
6763 /* Verify that cbWidth is less than scanline and fits into the GMR. */
6764 uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
6765 AssertMsgReturn(cbGmrScanline != 0,
6766 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6767 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6768 VERR_INVALID_PARAMETER);
6769 RT_UNTRUSTED_VALIDATED_FENCE();
6770 AssertMsgReturn(cbWidth <= cbGmrScanline,
6771 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6772 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6773 VERR_INVALID_PARAMETER);
6774 AssertMsgReturn(cbWidth <= cbGmr - offGmr,
6775 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6776 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6777 VERR_INVALID_PARAMETER);
6778 RT_UNTRUSTED_VALIDATED_FENCE();
6779
6780 /* How many bytes are available for the data in the GMR. */
6781 uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
6782
6783 /* How many scanlines would fit into the available data. */
6784 uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
6785 uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
6786 if (cbWidth <= cbGmrLastScanline)
6787 ++cGmrScanlines;
6788
6789 if (cHeight > cGmrScanlines)
6790 cHeight = cGmrScanlines;
6791
6792 AssertMsgReturn(cHeight > 0,
6793 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6794 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6795 VERR_INVALID_PARAMETER);
6796 RT_UNTRUSTED_VALIDATED_FENCE();
6797
6798 /*
6799 * Host buffer.
6800 */
6801 AssertMsgReturn(offHst < cbHstBuf,
6802 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6803 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6804 VERR_INVALID_PARAMETER);
6805
6806 /* Verify that cbWidth is less than scanline and fits into the buffer. */
6807 uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
6808 AssertMsgReturn(cbHstScanline != 0,
6809 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6810 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6811 VERR_INVALID_PARAMETER);
6812 AssertMsgReturn(cbWidth <= cbHstScanline,
6813 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6814 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6815 VERR_INVALID_PARAMETER);
6816 AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
6817 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6818 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6819 VERR_INVALID_PARAMETER);
6820
6821 /* How many bytes are available for the data in the buffer. */
6822 uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
6823
6824 /* How many scanlines would fit into the available data. */
6825 uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
6826 uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
6827 if (cbWidth <= cbHstLastScanline)
6828 ++cHstScanlines;
6829
6830 if (cHeight > cHstScanlines)
6831 cHeight = cHstScanlines;
6832
6833 AssertMsgReturn(cHeight > 0,
6834 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6835 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6836 VERR_INVALID_PARAMETER);
6837
6838 uint8_t *pbHst = pbHstBuf + offHst;
6839
6840 /* Shortcut for the framebuffer. */
6841 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
6842 {
6843 uint8_t *pbGst = pThisCC->pbVRam + offGmr;
6844
6845 uint8_t const *pbSrc;
6846 int32_t cbSrcPitch;
6847 uint8_t *pbDst;
6848 int32_t cbDstPitch;
6849
6850 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
6851 {
6852 pbSrc = pbHst;
6853 cbSrcPitch = cbHstPitch;
6854 pbDst = pbGst;
6855 cbDstPitch = cbGstPitch;
6856 }
6857 else
6858 {
6859 pbSrc = pbGst;
6860 cbSrcPitch = cbGstPitch;
6861 pbDst = pbHst;
6862 cbDstPitch = cbHstPitch;
6863 }
6864
6865 if ( cbWidth == (uint32_t)cbGstPitch
6866 && cbGstPitch == cbHstPitch)
6867 {
6868 /* Entire scanlines, positive pitch. */
6869 memcpy(pbDst, pbSrc, cbWidth * cHeight);
6870 }
6871 else
6872 {
6873 for (uint32_t i = 0; i < cHeight; ++i)
6874 {
6875 memcpy(pbDst, pbSrc, cbWidth);
6876
6877 pbDst += cbDstPitch;
6878 pbSrc += cbSrcPitch;
6879 }
6880 }
6881 return VINF_SUCCESS;
6882 }
6883
6884 AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
6885 AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
6886
6887 PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
6888 uint32_t iDesc = 0; /* Index in the descriptor array. */
6889 uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
6890 uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
6891 uint8_t *pbHstScanline = pbHst; /* Host address of the scanline which is being copied. */
6892 for (uint32_t i = 0; i < cHeight; ++i)
6893 {
6894 uint32_t cbCurrentWidth = cbWidth;
6895 uint32_t offGmrCurrent = offGmrScanline;
6896 uint8_t *pbCurrentHost = pbHstScanline;
6897
6898 /* Find the right descriptor */
6899 while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
6900 {
6901 offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
6902 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
6903 ++iDesc;
6904 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
6905 }
6906
6907 while (cbCurrentWidth)
6908 {
6909 uint32_t cbToCopy;
6910
6911 if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
6912 {
6913 cbToCopy = cbCurrentWidth;
6914 }
6915 else
6916 {
6917 cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
6918 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
6919 }
6920
6921 RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
6922
6923 Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
6924
6925 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
6926 rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
6927 else
6928 rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
6929 AssertRCBreak(rc);
6930
6931 cbCurrentWidth -= cbToCopy;
6932 offGmrCurrent += cbToCopy;
6933 pbCurrentHost += cbToCopy;
6934
6935 /* Go to the next descriptor if there's anything left. */
6936 if (cbCurrentWidth)
6937 {
6938 offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
6939 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
6940 ++iDesc;
6941 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
6942 }
6943 }
6944
6945 offGmrScanline += cbGstPitch;
6946 pbHstScanline += cbHstPitch;
6947 }
6948
6949 return VINF_SUCCESS;
6950}
6951
6952
6953/**
6954 * Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
6955 *
6956 * @param pSizeSrc Source surface dimensions.
6957 * @param pSizeDest Destination surface dimensions.
6958 * @param pBox Coordinates to be clipped.
6959 */
6960void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox)
6961{
6962 /* Src x, w */
6963 if (pBox->srcx > pSizeSrc->width)
6964 pBox->srcx = pSizeSrc->width;
6965 if (pBox->w > pSizeSrc->width - pBox->srcx)
6966 pBox->w = pSizeSrc->width - pBox->srcx;
6967
6968 /* Src y, h */
6969 if (pBox->srcy > pSizeSrc->height)
6970 pBox->srcy = pSizeSrc->height;
6971 if (pBox->h > pSizeSrc->height - pBox->srcy)
6972 pBox->h = pSizeSrc->height - pBox->srcy;
6973
6974 /* Src z, d */
6975 if (pBox->srcz > pSizeSrc->depth)
6976 pBox->srcz = pSizeSrc->depth;
6977 if (pBox->d > pSizeSrc->depth - pBox->srcz)
6978 pBox->d = pSizeSrc->depth - pBox->srcz;
6979
6980 /* Dest x, w */
6981 if (pBox->x > pSizeDest->width)
6982 pBox->x = pSizeDest->width;
6983 if (pBox->w > pSizeDest->width - pBox->x)
6984 pBox->w = pSizeDest->width - pBox->x;
6985
6986 /* Dest y, h */
6987 if (pBox->y > pSizeDest->height)
6988 pBox->y = pSizeDest->height;
6989 if (pBox->h > pSizeDest->height - pBox->y)
6990 pBox->h = pSizeDest->height - pBox->y;
6991
6992 /* Dest z, d */
6993 if (pBox->z > pSizeDest->depth)
6994 pBox->z = pSizeDest->depth;
6995 if (pBox->d > pSizeDest->depth - pBox->z)
6996 pBox->d = pSizeDest->depth - pBox->z;
6997}
6998
6999/**
7000 * Unsigned coordinates in pBox. Clip to [0; pSize).
7001 *
7002 * @param pSize Source surface dimensions.
7003 * @param pBox Coordinates to be clipped.
7004 */
7005void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox)
7006{
7007 /* x, w */
7008 if (pBox->x > pSize->width)
7009 pBox->x = pSize->width;
7010 if (pBox->w > pSize->width - pBox->x)
7011 pBox->w = pSize->width - pBox->x;
7012
7013 /* y, h */
7014 if (pBox->y > pSize->height)
7015 pBox->y = pSize->height;
7016 if (pBox->h > pSize->height - pBox->y)
7017 pBox->h = pSize->height - pBox->y;
7018
7019 /* z, d */
7020 if (pBox->z > pSize->depth)
7021 pBox->z = pSize->depth;
7022 if (pBox->d > pSize->depth - pBox->z)
7023 pBox->d = pSize->depth - pBox->z;
7024}
7025
7026/**
7027 * Clip.
7028 *
7029 * @param pBound Bounding rectangle.
7030 * @param pRect Rectangle to be clipped.
7031 */
7032void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect)
7033{
7034 int32_t left;
7035 int32_t top;
7036 int32_t right;
7037 int32_t bottom;
7038
7039 /* Right order. */
7040 Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
7041 if (pRect->left < pRect->right)
7042 {
7043 left = pRect->left;
7044 right = pRect->right;
7045 }
7046 else
7047 {
7048 left = pRect->right;
7049 right = pRect->left;
7050 }
7051 if (pRect->top < pRect->bottom)
7052 {
7053 top = pRect->top;
7054 bottom = pRect->bottom;
7055 }
7056 else
7057 {
7058 top = pRect->bottom;
7059 bottom = pRect->top;
7060 }
7061
7062 if (left < pBound->left)
7063 left = pBound->left;
7064 if (right < pBound->left)
7065 right = pBound->left;
7066
7067 if (left > pBound->right)
7068 left = pBound->right;
7069 if (right > pBound->right)
7070 right = pBound->right;
7071
7072 if (top < pBound->top)
7073 top = pBound->top;
7074 if (bottom < pBound->top)
7075 bottom = pBound->top;
7076
7077 if (top > pBound->bottom)
7078 top = pBound->bottom;
7079 if (bottom > pBound->bottom)
7080 bottom = pBound->bottom;
7081
7082 pRect->left = left;
7083 pRect->right = right;
7084 pRect->top = top;
7085 pRect->bottom = bottom;
7086}
7087
7088/**
7089 * @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
7090 * Unblock the FIFO I/O thread so it can respond to a state change.}
7091 */
7092static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7093{
7094 RT_NOREF(pDevIns);
7095 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
7096 Log(("vmsvgaR3FifoLoopWakeUp\n"));
7097 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
7098}
7099
7100/**
7101 * Enables or disables dirty page tracking for the framebuffer
7102 *
7103 * @param pDevIns The device instance.
7104 * @param pThis The shared VGA/VMSVGA instance data.
7105 * @param fTraces Enable/disable traces
7106 */
7107static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
7108{
7109 if ( (!pThis->svga.fConfigured || !pThis->svga.fEnabled)
7110 && !fTraces)
7111 {
7112 //Assert(pThis->svga.fTraces);
7113 Log(("vmsvgaR3SetTraces: *not* allowed to disable dirty page tracking when the device is in legacy mode.\n"));
7114 return;
7115 }
7116
7117 pThis->svga.fTraces = fTraces;
7118 if (pThis->svga.fTraces)
7119 {
7120 unsigned cbFrameBuffer = pThis->vram_size;
7121
7122 Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
7123 /** @todo How does this work with screens? */
7124 if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
7125 {
7126# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
7127 Assert(pThis->svga.cbScanline);
7128# endif
7129 /* Hardware enabled; return real framebuffer size .*/
7130 cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
7131 cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
7132 }
7133
7134 if (!pThis->svga.fVRAMTracking)
7135 {
7136 Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
7137 vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
7138 pThis->svga.fVRAMTracking = true;
7139 }
7140 }
7141 else
7142 {
7143 if (pThis->svga.fVRAMTracking)
7144 {
7145 Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
7146 vgaR3UnregisterVRAMHandler(pDevIns, pThis);
7147 pThis->svga.fVRAMTracking = false;
7148 }
7149 }
7150}
7151
7152/**
7153 * @callback_method_impl{FNPCIIOREGIONMAP}
7154 */
7155DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
7156 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
7157{
7158 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
7159 int rc;
7160 RT_NOREF(pPciDev);
7161 Assert(pPciDev == pDevIns->apPciDevs[0]);
7162
7163 Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
7164 AssertReturn( iRegion == pThis->pciRegions.iFIFO
7165 && ( enmType == PCI_ADDRESS_SPACE_MEM
7166 || (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
7167 , VERR_INTERNAL_ERROR);
7168 if (GCPhysAddress != NIL_RTGCPHYS)
7169 {
7170 /*
7171 * Mapping the FIFO RAM.
7172 */
7173 AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
7174 rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
7175 AssertRC(rc);
7176
7177# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
7178 if (RT_SUCCESS(rc))
7179 {
7180 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
7181# ifdef DEBUG_FIFO_ACCESS
7182 GCPhysAddress + (pThis->svga.cbFIFO - 1),
7183# else
7184 GCPhysAddress + PAGE_SIZE - 1,
7185# endif
7186 pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
7187 "VMSVGA FIFO");
7188 AssertRC(rc);
7189 }
7190# endif
7191 if (RT_SUCCESS(rc))
7192 {
7193 pThis->svga.GCPhysFIFO = GCPhysAddress;
7194 Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
7195 }
7196 rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite errors here. */
7197 }
7198 else
7199 {
7200 Assert(pThis->svga.GCPhysFIFO);
7201# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
7202 rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
7203 AssertRC(rc);
7204# else
7205 rc = VINF_SUCCESS;
7206# endif
7207 pThis->svga.GCPhysFIFO = 0;
7208 }
7209 return rc;
7210}
7211
7212# ifdef VBOX_WITH_VMSVGA3D
7213
7214/**
7215 * Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
7216 * surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
7217 *
7218 * @param pDevIns The device instance.
7219 * @param pThis The The shared VGA/VMSVGA instance data.
7220 * @param pThisCC The VGA/VMSVGA state for ring-3.
7221 * @param sid Either UINT32_MAX or the ID of a specific surface. If
7222 * UINT32_MAX is used, all surfaces are processed.
7223 */
7224void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
7225{
7226 vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
7227 sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
7228}
7229
7230
7231/**
7232 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
7233 */
7234DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
7235{
7236 /* There might be a specific surface ID at the start of the
7237 arguments, if not show all surfaces. */
7238 uint32_t sid = UINT32_MAX;
7239 if (pszArgs)
7240 pszArgs = RTStrStripL(pszArgs);
7241 if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
7242 sid = RTStrToUInt32(pszArgs);
7243
7244 /* Verbose or terse display, we default to verbose. */
7245 bool fVerbose = true;
7246 if (RTStrIStr(pszArgs, "terse"))
7247 fVerbose = false;
7248
7249 /* The size of the ascii art (x direction, y is 3/4 of x). */
7250 uint32_t cxAscii = 80;
7251 if (RTStrIStr(pszArgs, "gigantic"))
7252 cxAscii = 300;
7253 else if (RTStrIStr(pszArgs, "huge"))
7254 cxAscii = 180;
7255 else if (RTStrIStr(pszArgs, "big"))
7256 cxAscii = 132;
7257 else if (RTStrIStr(pszArgs, "normal"))
7258 cxAscii = 80;
7259 else if (RTStrIStr(pszArgs, "medium"))
7260 cxAscii = 64;
7261 else if (RTStrIStr(pszArgs, "small"))
7262 cxAscii = 48;
7263 else if (RTStrIStr(pszArgs, "tiny"))
7264 cxAscii = 24;
7265
7266 /* Y invert the image when producing the ASCII art. */
7267 bool fInvY = false;
7268 if (RTStrIStr(pszArgs, "invy"))
7269 fInvY = true;
7270
7271 vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
7272 pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
7273}
7274
7275
7276/**
7277 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
7278 */
7279DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
7280{
7281 /* pszArg = "sid[>dir]"
7282 * Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
7283 */
7284 char *pszBitmapPath = NULL;
7285 uint32_t sid = UINT32_MAX;
7286 if (pszArgs)
7287 pszArgs = RTStrStripL(pszArgs);
7288 if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
7289 RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
7290 if ( pszBitmapPath
7291 && *pszBitmapPath == '>')
7292 ++pszBitmapPath;
7293
7294 const bool fVerbose = true;
7295 const uint32_t cxAscii = 0; /* No ASCII */
7296 const bool fInvY = false; /* Do not invert. */
7297 vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
7298 pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
7299}
7300
7301/**
7302 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
7303 */
7304DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
7305{
7306 /* There might be a specific surface ID at the start of the
7307 arguments, if not show all contexts. */
7308 uint32_t sid = UINT32_MAX;
7309 if (pszArgs)
7310 pszArgs = RTStrStripL(pszArgs);
7311 if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
7312 sid = RTStrToUInt32(pszArgs);
7313
7314 /* Verbose or terse display, we default to verbose. */
7315 bool fVerbose = true;
7316 if (RTStrIStr(pszArgs, "terse"))
7317 fVerbose = false;
7318
7319 vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
7320}
7321# endif /* VBOX_WITH_VMSVGA3D */
7322
7323/**
7324 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
7325 */
7326static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
7327{
7328 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
7329 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
7330 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7331 uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
7332 RT_NOREF(pszArgs);
7333
7334 pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
7335 pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
7336 pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
7337 pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
7338 ? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
7339 pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
7340 pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
7341 pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
7342 pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
7343 pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
7344 pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
7345 pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
7346 pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
7347 pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
7348 pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
7349 pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
7350 pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
7351 pHlp->pfnPrintf(pHlp, "Device Capabilites: %#x\n", pThis->svga.u32DeviceCaps);
7352 pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
7353 pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
7354 pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
7355 pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
7356 pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
7357 pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
7358 pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
7359
7360 pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
7361 pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
7362 pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
7363 pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
7364
7365 pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
7366 pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
7367
7368 pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
7369 pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
7370
7371# ifdef VBOX_WITH_VMSVGA3D
7372 pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
7373# endif
7374 if (pThisCC->pDrv)
7375 {
7376 pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
7377 pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
7378 }
7379
7380 /* Dump screen information. */
7381 for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
7382 {
7383 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
7384 if (pScreen)
7385 {
7386 pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
7387 pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
7388 pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
7389 pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
7390 pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
7391 if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
7392 {
7393 pHlp->pfnPrintf(pHlp, " (");
7394 if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
7395 pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
7396 if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
7397 pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
7398 if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
7399 pHlp->pfnPrintf(pHlp, " DEACTIVATE");
7400 if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
7401 pHlp->pfnPrintf(pHlp, " BLANKING");
7402 pHlp->pfnPrintf(pHlp, " )");
7403 }
7404 pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
7405 }
7406 }
7407
7408}
7409
7410/**
7411 * Portion of VMSVGA state which must be loaded oin the FIFO thread.
7412 */
7413static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
7414 PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
7415{
7416 RT_NOREF(uPass);
7417
7418 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7419 int rc;
7420
7421 if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
7422 {
7423 uint32_t cScreens = 0;
7424 rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
7425 AssertRCReturn(rc, rc);
7426 AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
7427 ("cScreens=%#x\n", cScreens),
7428 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
7429
7430 for (uint32_t i = 0; i < cScreens; ++i)
7431 {
7432 VMSVGASCREENOBJECT screen;
7433 RT_ZERO(screen);
7434
7435 rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
7436 AssertLogRelRCReturn(rc, rc);
7437
7438 if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
7439 {
7440 VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
7441 *pScreen = screen;
7442 pScreen->fModified = true;
7443 }
7444 else
7445 {
7446 LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
7447 }
7448 }
7449 }
7450 else
7451 {
7452 /* Try to setup at least the first screen. */
7453 VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
7454 pScreen->fDefined = true;
7455 pScreen->fModified = true;
7456 pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET | SVGA_SCREEN_IS_PRIMARY;
7457 pScreen->idScreen = 0;
7458 pScreen->xOrigin = 0;
7459 pScreen->yOrigin = 0;
7460 pScreen->offVRAM = pThis->svga.uScreenOffset;
7461 pScreen->cbPitch = pThis->svga.cbScanline;
7462 pScreen->cWidth = pThis->svga.uWidth;
7463 pScreen->cHeight = pThis->svga.uHeight;
7464 pScreen->cBpp = pThis->svga.uBpp;
7465 }
7466
7467 return VINF_SUCCESS;
7468}
7469
7470/**
7471 * @copydoc FNSSMDEVLOADEXEC
7472 */
7473int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
7474{
7475 RT_NOREF(uPass);
7476 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
7477 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
7478 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7479 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7480 int rc;
7481
7482 /* Load our part of the VGAState */
7483 rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
7484 AssertRCReturn(rc, rc);
7485
7486 /* Load the VGA framebuffer. */
7487 AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
7488 uint32_t cbVgaFramebuffer = _32K;
7489 if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
7490 {
7491 rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
7492 AssertRCReturn(rc, rc);
7493 AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
7494 ("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
7495 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
7496 AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
7497 AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
7498 }
7499 rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
7500 AssertRCReturn(rc, rc);
7501 if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
7502 pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
7503 else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
7504 RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
7505
7506 /* Load the VMSVGA state. */
7507 rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
7508 AssertRCReturn(rc, rc);
7509
7510 /* Load the active cursor bitmaps. */
7511 if (pSVGAState->Cursor.fActive)
7512 {
7513 pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
7514 AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
7515
7516 rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
7517 AssertRCReturn(rc, rc);
7518 }
7519
7520 /* Load the GMR state. */
7521 uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
7522 if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
7523 {
7524 rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
7525 AssertRCReturn(rc, rc);
7526 /* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
7527 AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
7528 ("cGMR=%#x - expected 256B..1MB\n", cGMR),
7529 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
7530 }
7531
7532 if (pThis->svga.cGMR != cGMR)
7533 {
7534 /* Reallocate GMR array. */
7535 Assert(pSVGAState->paGMR != NULL);
7536 RTMemFree(pSVGAState->paGMR);
7537 pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
7538 AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
7539 pThis->svga.cGMR = cGMR;
7540 }
7541
7542 for (uint32_t i = 0; i < cGMR; ++i)
7543 {
7544 PGMR pGMR = &pSVGAState->paGMR[i];
7545
7546 rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
7547 AssertRCReturn(rc, rc);
7548
7549 if (pGMR->numDescriptors)
7550 {
7551 Assert(pGMR->cMaxPages || pGMR->cbTotal);
7552 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
7553 AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
7554
7555 for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
7556 {
7557 rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
7558 AssertRCReturn(rc, rc);
7559 }
7560 }
7561 }
7562
7563# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
7564 vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
7565# endif
7566
7567 VMSVGA_STATE_LOAD LoadState;
7568 LoadState.pSSM = pSSM;
7569 LoadState.uVersion = uVersion;
7570 LoadState.uPass = uPass;
7571 rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
7572 AssertLogRelRCReturn(rc, rc);
7573
7574 return VINF_SUCCESS;
7575}
7576
7577/**
7578 * Reinit the video mode after the state has been loaded.
7579 */
7580int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
7581{
7582 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
7583 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
7584 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7585
7586 /* Set the active cursor. */
7587 if (pSVGAState->Cursor.fActive)
7588 {
7589 /* We don't store the alpha flag, but we can take a guess that if
7590 * the old register interface was used, the cursor was B&W.
7591 */
7592 bool fAlpha = pThis->svga.uCursorOn ? false : true;
7593
7594 int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
7595 true /*fVisible*/,
7596 fAlpha,
7597 pSVGAState->Cursor.xHotspot,
7598 pSVGAState->Cursor.yHotspot,
7599 pSVGAState->Cursor.width,
7600 pSVGAState->Cursor.height,
7601 pSVGAState->Cursor.pData);
7602 AssertRC(rc);
7603
7604 if (pThis->svga.uCursorOn)
7605 pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
7606 }
7607
7608 /* If the VRAM handler should not be registered, we have to explicitly
7609 * unregister it here!
7610 */
7611 if (!pThis->svga.fVRAMTracking)
7612 {
7613 vgaR3UnregisterVRAMHandler(pDevIns, pThis);
7614 }
7615
7616 /* Let the FIFO thread deal with changing the mode. */
7617 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
7618
7619 return VINF_SUCCESS;
7620}
7621
7622/**
7623 * Portion of SVGA state which must be saved in the FIFO thread.
7624 */
7625static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
7626{
7627 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7628 int rc;
7629
7630 /* Save the screen objects. */
7631 /* Count defined screen object. */
7632 uint32_t cScreens = 0;
7633 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
7634 {
7635 if (pSVGAState->aScreens[i].fDefined)
7636 ++cScreens;
7637 }
7638
7639 rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
7640 AssertLogRelRCReturn(rc, rc);
7641
7642 for (uint32_t i = 0; i < cScreens; ++i)
7643 {
7644 VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
7645
7646 rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
7647 AssertLogRelRCReturn(rc, rc);
7648 }
7649 return VINF_SUCCESS;
7650}
7651
7652/**
7653 * @copydoc FNSSMDEVSAVEEXEC
7654 */
7655int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7656{
7657 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
7658 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
7659 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7660 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7661 int rc;
7662
7663 /* Save our part of the VGAState */
7664 rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
7665 AssertLogRelRCReturn(rc, rc);
7666
7667 /* Save the framebuffer backup. */
7668 rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
7669 rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
7670 AssertLogRelRCReturn(rc, rc);
7671
7672 /* Save the VMSVGA state. */
7673 rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
7674 AssertLogRelRCReturn(rc, rc);
7675
7676 /* Save the active cursor bitmaps. */
7677 if (pSVGAState->Cursor.fActive)
7678 {
7679 rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
7680 AssertLogRelRCReturn(rc, rc);
7681 }
7682
7683 /* Save the GMR state */
7684 rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
7685 AssertLogRelRCReturn(rc, rc);
7686 for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
7687 {
7688 PGMR pGMR = &pSVGAState->paGMR[i];
7689
7690 rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
7691 AssertLogRelRCReturn(rc, rc);
7692
7693 for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
7694 {
7695 rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
7696 AssertLogRelRCReturn(rc, rc);
7697 }
7698 }
7699
7700 /*
7701 * Must save some state (3D in particular) in the FIFO thread.
7702 */
7703 rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
7704 AssertLogRelRCReturn(rc, rc);
7705
7706 return VINF_SUCCESS;
7707}
7708
7709/**
7710 * Destructor for PVMSVGAR3STATE structure.
7711 *
7712 * @param pThis The shared VGA/VMSVGA instance data.
7713 * @param pSVGAState Pointer to the structure. It is not deallocated.
7714 */
7715static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
7716{
7717# ifndef VMSVGA_USE_EMT_HALT_CODE
7718 if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
7719 {
7720 RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
7721 pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
7722 }
7723# endif
7724
7725 if (pSVGAState->Cursor.fActive)
7726 {
7727 RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
7728 pSVGAState->Cursor.pData = NULL;
7729 pSVGAState->Cursor.fActive = false;
7730 }
7731
7732 if (pSVGAState->paGMR)
7733 {
7734 for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
7735 if (pSVGAState->paGMR[i].paDesc)
7736 RTMemFree(pSVGAState->paGMR[i].paDesc);
7737
7738 RTMemFree(pSVGAState->paGMR);
7739 pSVGAState->paGMR = NULL;
7740 }
7741
7742 if (RTCritSectIsInitialized(&pSVGAState->CritSectCmdBuf))
7743 {
7744 RTCritSectEnter(&pSVGAState->CritSectCmdBuf);
7745 for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->apCmdBufCtxs); ++i)
7746 {
7747 vmsvgaR3CmdBufCtxTerm(pSVGAState->apCmdBufCtxs[i]);
7748 pSVGAState->apCmdBufCtxs[i] = NULL;
7749 }
7750 vmsvgaR3CmdBufCtxTerm(&pSVGAState->CmdBufCtxDC);
7751 RTCritSectLeave(&pSVGAState->CritSectCmdBuf);
7752 RTCritSectDelete(&pSVGAState->CritSectCmdBuf);
7753 }
7754}
7755
7756/**
7757 * Constructor for PVMSVGAR3STATE structure.
7758 *
7759 * @returns VBox status code.
7760 * @param pThis The shared VGA/VMSVGA instance data.
7761 * @param pSVGAState Pointer to the structure. It is already allocated.
7762 */
7763static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
7764{
7765 int rc = VINF_SUCCESS;
7766 RT_ZERO(*pSVGAState);
7767
7768 pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
7769 AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
7770
7771# ifndef VMSVGA_USE_EMT_HALT_CODE
7772 /* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
7773 rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
7774 AssertRCReturn(rc, rc);
7775# endif
7776
7777 rc = RTCritSectInit(&pSVGAState->CritSectCmdBuf);
7778 AssertRCReturn(rc, rc);
7779
7780 vmsvgaR3CmdBufCtxInit(&pSVGAState->CmdBufCtxDC);
7781 return rc;
7782}
7783
7784/**
7785 * Initializes the host capabilities: device and FIFO.
7786 *
7787 * @returns VBox status code.
7788 * @param pThis The shared VGA/VMSVGA instance data.
7789 * @param pThisCC The VGA/VMSVGA state for ring-3.
7790 */
7791static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
7792{
7793 /* Device caps. */
7794 pThis->svga.u32DeviceCaps = SVGA_CAP_GMR
7795 | SVGA_CAP_GMR2
7796 | SVGA_CAP_CURSOR
7797 | SVGA_CAP_CURSOR_BYPASS
7798 | SVGA_CAP_CURSOR_BYPASS_2
7799 | SVGA_CAP_EXTENDED_FIFO
7800 | SVGA_CAP_IRQMASK
7801 | SVGA_CAP_PITCHLOCK
7802 | SVGA_CAP_RECT_COPY
7803 | SVGA_CAP_TRACES
7804 | SVGA_CAP_SCREEN_OBJECT_2
7805 | SVGA_CAP_ALPHA_CURSOR;
7806
7807 /* VGPU10 capabilities. */
7808// pThis->svga.u32DeviceCaps |= SVGA_CAP_COMMAND_BUFFERS /* Enable register based command buffer submission. */
7809// | SVGA_CAP_CMD_BUFFERS_2 /* Support for SVGA_REG_CMD_PREPEND_LOW/HIGH */
7810// | SVGA_CAP_GBOBJECTS /* Enable guest-backed objects and surfaces. */
7811// | SVGA_CAP_CMD_BUFFERS_3 /* AKA SVGA_CAP_DX. Enable support for DX commands, and command buffers in a mob. */
7812// ;
7813
7814# ifdef VBOX_WITH_VMSVGA3D
7815 pThis->svga.u32DeviceCaps |= SVGA_CAP_3D;
7816# endif
7817
7818 /* Clear the FIFO. */
7819 RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
7820
7821 /* Setup FIFO capabilities. */
7822 pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
7823 | SVGA_FIFO_CAP_PITCHLOCK
7824 | SVGA_FIFO_CAP_CURSOR_BYPASS_3
7825 | SVGA_FIFO_CAP_RESERVE
7826 | SVGA_FIFO_CAP_GMR2
7827 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED
7828 | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
7829
7830 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
7831 pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
7832}
7833
7834# ifdef VBOX_WITH_VMSVGA3D
7835/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
7836static const char * const g_apszVmSvgaDevCapNames[] =
7837{
7838 "x3D", /* = 0 */
7839 "xMAX_LIGHTS",
7840 "xMAX_TEXTURES",
7841 "xMAX_CLIP_PLANES",
7842 "xVERTEX_SHADER_VERSION",
7843 "xVERTEX_SHADER",
7844 "xFRAGMENT_SHADER_VERSION",
7845 "xFRAGMENT_SHADER",
7846 "xMAX_RENDER_TARGETS",
7847 "xS23E8_TEXTURES",
7848 "xS10E5_TEXTURES",
7849 "xMAX_FIXED_VERTEXBLEND",
7850 "xD16_BUFFER_FORMAT",
7851 "xD24S8_BUFFER_FORMAT",
7852 "xD24X8_BUFFER_FORMAT",
7853 "xQUERY_TYPES",
7854 "xTEXTURE_GRADIENT_SAMPLING",
7855 "rMAX_POINT_SIZE",
7856 "xMAX_SHADER_TEXTURES",
7857 "xMAX_TEXTURE_WIDTH",
7858 "xMAX_TEXTURE_HEIGHT",
7859 "xMAX_VOLUME_EXTENT",
7860 "xMAX_TEXTURE_REPEAT",
7861 "xMAX_TEXTURE_ASPECT_RATIO",
7862 "xMAX_TEXTURE_ANISOTROPY",
7863 "xMAX_PRIMITIVE_COUNT",
7864 "xMAX_VERTEX_INDEX",
7865 "xMAX_VERTEX_SHADER_INSTRUCTIONS",
7866 "xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
7867 "xMAX_VERTEX_SHADER_TEMPS",
7868 "xMAX_FRAGMENT_SHADER_TEMPS",
7869 "xTEXTURE_OPS",
7870 "xSURFACEFMT_X8R8G8B8",
7871 "xSURFACEFMT_A8R8G8B8",
7872 "xSURFACEFMT_A2R10G10B10",
7873 "xSURFACEFMT_X1R5G5B5",
7874 "xSURFACEFMT_A1R5G5B5",
7875 "xSURFACEFMT_A4R4G4B4",
7876 "xSURFACEFMT_R5G6B5",
7877 "xSURFACEFMT_LUMINANCE16",
7878 "xSURFACEFMT_LUMINANCE8_ALPHA8",
7879 "xSURFACEFMT_ALPHA8",
7880 "xSURFACEFMT_LUMINANCE8",
7881 "xSURFACEFMT_Z_D16",
7882 "xSURFACEFMT_Z_D24S8",
7883 "xSURFACEFMT_Z_D24X8",
7884 "xSURFACEFMT_DXT1",
7885 "xSURFACEFMT_DXT2",
7886 "xSURFACEFMT_DXT3",
7887 "xSURFACEFMT_DXT4",
7888 "xSURFACEFMT_DXT5",
7889 "xSURFACEFMT_BUMPX8L8V8U8",
7890 "xSURFACEFMT_A2W10V10U10",
7891 "xSURFACEFMT_BUMPU8V8",
7892 "xSURFACEFMT_Q8W8V8U8",
7893 "xSURFACEFMT_CxV8U8",
7894 "xSURFACEFMT_R_S10E5",
7895 "xSURFACEFMT_R_S23E8",
7896 "xSURFACEFMT_RG_S10E5",
7897 "xSURFACEFMT_RG_S23E8",
7898 "xSURFACEFMT_ARGB_S10E5",
7899 "xSURFACEFMT_ARGB_S23E8",
7900 "xMISSING62",
7901 "xMAX_VERTEX_SHADER_TEXTURES",
7902 "xMAX_SIMULTANEOUS_RENDER_TARGETS",
7903 "xSURFACEFMT_V16U16",
7904 "xSURFACEFMT_G16R16",
7905 "xSURFACEFMT_A16B16G16R16",
7906 "xSURFACEFMT_UYVY",
7907 "xSURFACEFMT_YUY2",
7908 "xMULTISAMPLE_NONMASKABLESAMPLES",
7909 "xMULTISAMPLE_MASKABLESAMPLES",
7910 "xALPHATOCOVERAGE",
7911 "xSUPERSAMPLE",
7912 "xAUTOGENMIPMAPS",
7913 "xSURFACEFMT_NV12",
7914 "xSURFACEFMT_AYUV",
7915 "xMAX_CONTEXT_IDS",
7916 "xMAX_SURFACE_IDS",
7917 "xSURFACEFMT_Z_DF16",
7918 "xSURFACEFMT_Z_DF24",
7919 "xSURFACEFMT_Z_D24S8_INT",
7920 "xSURFACEFMT_ATI1",
7921 "xSURFACEFMT_ATI2", /* 83 */
7922 "xDEAD1",
7923 "xVIDEO_DECODE",
7924 "xVIDEO_PROCESS",
7925 "xLINE_AA",
7926 "xLINE_STIPPLE",
7927 "rMAX_LINE_WIDTH",
7928 "rMAX_AA_LINE_WIDTH",
7929 "xSURFACEFMT_YV12",
7930 "xLOGICOPS",
7931 "xTS_COLOR_KEY",
7932 "xDEAD2",
7933 "xDX",
7934 "xMAX_TEXTURE_ARRAY_SIZE",
7935 "xDX_MAX_VERTEXBUFFERS",
7936 "xDX_MAX_CONSTANT_BUFFERS",
7937 "xDX_PROVOKING_VERTEX",
7938 "xDXFMT_X8R8G8B8",
7939 "xDXFMT_A8R8G8B8",
7940 "xDXFMT_R5G6B5",
7941 "xDXFMT_X1R5G5B5",
7942 "xDXFMT_A1R5G5B5",
7943 "xDXFMT_A4R4G4B4",
7944 "xDXFMT_Z_D32",
7945 "xDXFMT_Z_D16",
7946 "xDXFMT_Z_D24S8",
7947 "xDXFMT_Z_D15S1",
7948 "xDXFMT_LUMINANCE8",
7949 "xDXFMT_LUMINANCE4_ALPHA4",
7950 "xDXFMT_LUMINANCE16",
7951 "xDXFMT_LUMINANCE8_ALPHA8",
7952 "xDXFMT_DXT1",
7953 "xDXFMT_DXT2",
7954 "xDXFMT_DXT3",
7955 "xDXFMT_DXT4",
7956 "xDXFMT_DXT5",
7957 "xDXFMT_BUMPU8V8",
7958 "xDXFMT_BUMPL6V5U5",
7959 "xDXFMT_BUMPX8L8V8U8",
7960 "xDXFMT_FORMAT_DEAD1",
7961 "xDXFMT_ARGB_S10E5",
7962 "xDXFMT_ARGB_S23E8",
7963 "xDXFMT_A2R10G10B10",
7964 "xDXFMT_V8U8",
7965 "xDXFMT_Q8W8V8U8",
7966 "xDXFMT_CxV8U8",
7967 "xDXFMT_X8L8V8U8",
7968 "xDXFMT_A2W10V10U10",
7969 "xDXFMT_ALPHA8",
7970 "xDXFMT_R_S10E5",
7971 "xDXFMT_R_S23E8",
7972 "xDXFMT_RG_S10E5",
7973 "xDXFMT_RG_S23E8",
7974 "xDXFMT_BUFFER",
7975 "xDXFMT_Z_D24X8",
7976 "xDXFMT_V16U16",
7977 "xDXFMT_G16R16",
7978 "xDXFMT_A16B16G16R16",
7979 "xDXFMT_UYVY",
7980 "xDXFMT_YUY2",
7981 "xDXFMT_NV12",
7982 "xDXFMT_AYUV",
7983 "xDXFMT_R32G32B32A32_TYPELESS",
7984 "xDXFMT_R32G32B32A32_UINT",
7985 "xDXFMT_R32G32B32A32_SINT",
7986 "xDXFMT_R32G32B32_TYPELESS",
7987 "xDXFMT_R32G32B32_FLOAT",
7988 "xDXFMT_R32G32B32_UINT",
7989 "xDXFMT_R32G32B32_SINT",
7990 "xDXFMT_R16G16B16A16_TYPELESS",
7991 "xDXFMT_R16G16B16A16_UINT",
7992 "xDXFMT_R16G16B16A16_SNORM",
7993 "xDXFMT_R16G16B16A16_SINT",
7994 "xDXFMT_R32G32_TYPELESS",
7995 "xDXFMT_R32G32_UINT",
7996 "xDXFMT_R32G32_SINT",
7997 "xDXFMT_R32G8X24_TYPELESS",
7998 "xDXFMT_D32_FLOAT_S8X24_UINT",
7999 "xDXFMT_R32_FLOAT_X8X24_TYPELESS",
8000 "xDXFMT_X32_TYPELESS_G8X24_UINT",
8001 "xDXFMT_R10G10B10A2_TYPELESS",
8002 "xDXFMT_R10G10B10A2_UINT",
8003 "xDXFMT_R11G11B10_FLOAT",
8004 "xDXFMT_R8G8B8A8_TYPELESS",
8005 "xDXFMT_R8G8B8A8_UNORM",
8006 "xDXFMT_R8G8B8A8_UNORM_SRGB",
8007 "xDXFMT_R8G8B8A8_UINT",
8008 "xDXFMT_R8G8B8A8_SINT",
8009 "xDXFMT_R16G16_TYPELESS",
8010 "xDXFMT_R16G16_UINT",
8011 "xDXFMT_R16G16_SINT",
8012 "xDXFMT_R32_TYPELESS",
8013 "xDXFMT_D32_FLOAT",
8014 "xDXFMT_R32_UINT",
8015 "xDXFMT_R32_SINT",
8016 "xDXFMT_R24G8_TYPELESS",
8017 "xDXFMT_D24_UNORM_S8_UINT",
8018 "xDXFMT_R24_UNORM_X8_TYPELESS",
8019 "xDXFMT_X24_TYPELESS_G8_UINT",
8020 "xDXFMT_R8G8_TYPELESS",
8021 "xDXFMT_R8G8_UNORM",
8022 "xDXFMT_R8G8_UINT",
8023 "xDXFMT_R8G8_SINT",
8024 "xDXFMT_R16_TYPELESS",
8025 "xDXFMT_R16_UNORM",
8026 "xDXFMT_R16_UINT",
8027 "xDXFMT_R16_SNORM",
8028 "xDXFMT_R16_SINT",
8029 "xDXFMT_R8_TYPELESS",
8030 "xDXFMT_R8_UNORM",
8031 "xDXFMT_R8_UINT",
8032 "xDXFMT_R8_SNORM",
8033 "xDXFMT_R8_SINT",
8034 "xDXFMT_P8",
8035 "xDXFMT_R9G9B9E5_SHAREDEXP",
8036 "xDXFMT_R8G8_B8G8_UNORM",
8037 "xDXFMT_G8R8_G8B8_UNORM",
8038 "xDXFMT_BC1_TYPELESS",
8039 "xDXFMT_BC1_UNORM_SRGB",
8040 "xDXFMT_BC2_TYPELESS",
8041 "xDXFMT_BC2_UNORM_SRGB",
8042 "xDXFMT_BC3_TYPELESS",
8043 "xDXFMT_BC3_UNORM_SRGB",
8044 "xDXFMT_BC4_TYPELESS",
8045 "xDXFMT_ATI1",
8046 "xDXFMT_BC4_SNORM",
8047 "xDXFMT_BC5_TYPELESS",
8048 "xDXFMT_ATI2",
8049 "xDXFMT_BC5_SNORM",
8050 "xDXFMT_R10G10B10_XR_BIAS_A2_UNORM",
8051 "xDXFMT_B8G8R8A8_TYPELESS",
8052 "xDXFMT_B8G8R8A8_UNORM_SRGB",
8053 "xDXFMT_B8G8R8X8_TYPELESS",
8054 "xDXFMT_B8G8R8X8_UNORM_SRGB",
8055 "xDXFMT_Z_DF16",
8056 "xDXFMT_Z_DF24",
8057 "xDXFMT_Z_D24S8_INT",
8058 "xDXFMT_YV12",
8059 "xDXFMT_R32G32B32A32_FLOAT",
8060 "xDXFMT_R16G16B16A16_FLOAT",
8061 "xDXFMT_R16G16B16A16_UNORM",
8062 "xDXFMT_R32G32_FLOAT",
8063 "xDXFMT_R10G10B10A2_UNORM",
8064 "xDXFMT_R8G8B8A8_SNORM",
8065 "xDXFMT_R16G16_FLOAT",
8066 "xDXFMT_R16G16_UNORM",
8067 "xDXFMT_R16G16_SNORM",
8068 "xDXFMT_R32_FLOAT",
8069 "xDXFMT_R8G8_SNORM",
8070 "xDXFMT_R16_FLOAT",
8071 "xDXFMT_D16_UNORM",
8072 "xDXFMT_A8_UNORM",
8073 "xDXFMT_BC1_UNORM",
8074 "xDXFMT_BC2_UNORM",
8075 "xDXFMT_BC3_UNORM",
8076 "xDXFMT_B5G6R5_UNORM",
8077 "xDXFMT_B5G5R5A1_UNORM",
8078 "xDXFMT_B8G8R8A8_UNORM",
8079 "xDXFMT_B8G8R8X8_UNORM",
8080 "xDXFMT_BC4_UNORM",
8081 "xDXFMT_BC5_UNORM",
8082};
8083
8084/**
8085 * Initializes the host 3D capabilities and writes them to FIFO memory.
8086 *
8087 * @returns VBox status code.
8088 * @param pThis The shared VGA/VMSVGA instance data.
8089 * @param pThisCC The VGA/VMSVGA state for ring-3.
8090 */
8091static void vmsvgaR3InitFifo3DCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
8092{
8093 /* Query the capabilities and store them in the pThis->svga.au32DevCaps array. */
8094 bool const fSavedBuffering = RTLogRelSetBuffering(true);
8095
8096 for (unsigned i = 0; i < RT_ELEMENTS(pThis->svga.au32DevCaps); ++i)
8097 {
8098 uint32_t val = 0;
8099 int rc = vmsvga3dQueryCaps(pThisCC, i, &val);
8100 if (RT_SUCCESS(rc))
8101 pThis->svga.au32DevCaps[i] = val;
8102 else
8103 pThis->svga.au32DevCaps[i] = 0;
8104
8105 /* LogRel the capability value. */
8106 if (i < RT_ELEMENTS(g_apszVmSvgaDevCapNames))
8107 {
8108 if (RT_SUCCESS(rc))
8109 {
8110 if (g_apszVmSvgaDevCapNames[i][0] == 'x')
8111 LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
8112 else
8113 {
8114 float const fval = *(float *)&val;
8115 LogRel(("VMSVGA3d: cap[%u]=" FLOAT_FMT_STR " {%s}\n", i, FLOAT_FMT_ARGS(fval), &g_apszVmSvgaDevCapNames[i][1]));
8116 }
8117 }
8118 else
8119 LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
8120 }
8121 else
8122 LogRel(("VMSVGA3d: new cap[%u]=%#010x rc=%Rrc\n", i, val, rc));
8123 }
8124
8125 RTLogRelSetBuffering(fSavedBuffering);
8126
8127 /* 3d hardware version; latest and greatest */
8128 pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
8129 pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
8130
8131 /* Fill out 3d capabilities up to SVGA3D_DEVCAP_SURFACEFMT_ATI2 in the FIFO memory.
8132 * SVGA3D_DEVCAP_SURFACEFMT_ATI2 is the last capabiltiy for pre-SVGA_CAP_GBOBJECTS hardware.
8133 * If the VMSVGA device supports SVGA_CAP_GBOBJECTS capability, then the guest has to use SVGA_REG_DEV_CAP
8134 * register to query the devcaps. Older guests will still try to read the devcaps from FIFO.
8135 */
8136 SVGA3dCapsRecord *pCaps;
8137 SVGA3dCapPair *pData;
8138
8139 pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
8140 pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
8141 pData = (SVGA3dCapPair *)&pCaps->data;
8142
8143 AssertCompile(SVGA3D_DEVCAP_DEAD1 == SVGA3D_DEVCAP_SURFACEFMT_ATI2 + 1);
8144 for (unsigned i = 0; i < SVGA3D_DEVCAP_DEAD1; ++i)
8145 {
8146 pData[i][0] = i;
8147 pData[i][1] = pThis->svga.au32DevCaps[i];
8148 }
8149 pCaps->header.length = (sizeof(pCaps->header) + SVGA3D_DEVCAP_DEAD1 * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
8150 pCaps = (SVGA3dCapsRecord *)((uint32_t *)pCaps + pCaps->header.length);
8151
8152 /* Mark end of record array (a zero word). */
8153 pCaps->header.length = 0;
8154}
8155
8156# endif
8157
8158/**
8159 * Resets the SVGA hardware state
8160 *
8161 * @returns VBox status code.
8162 * @param pDevIns The device instance.
8163 */
8164int vmsvgaR3Reset(PPDMDEVINS pDevIns)
8165{
8166 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
8167 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
8168 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
8169
8170 /* Reset before init? */
8171 if (!pSVGAState)
8172 return VINF_SUCCESS;
8173
8174 Log(("vmsvgaR3Reset\n"));
8175
8176 /* Reset the FIFO processing as well as the 3d state (if we have one). */
8177 pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
8178 int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /*pvParam*/, 10000 /*ms*/);
8179
8180 /* Reset other stuff. */
8181 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
8182 RT_ZERO(pThis->svga.au32ScratchRegion);
8183
8184 vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
8185 vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
8186
8187 RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
8188
8189 /* Initialize FIFO and register capabilities. */
8190 vmsvgaR3InitCaps(pThis, pThisCC);
8191
8192# ifdef VBOX_WITH_VMSVGA3D
8193 if (pThis->svga.f3DEnabled)
8194 vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
8195# endif
8196
8197 /* VRAM tracking is enabled by default during bootup. */
8198 pThis->svga.fVRAMTracking = true;
8199 pThis->svga.fEnabled = false;
8200
8201 /* Invalidate current settings. */
8202 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
8203 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
8204 pThis->svga.uBpp = pThis->svga.uHostBpp;
8205 pThis->svga.cbScanline = 0;
8206 pThis->svga.u32PitchLock = 0;
8207
8208 return rc;
8209}
8210
8211/**
8212 * Cleans up the SVGA hardware state
8213 *
8214 * @returns VBox status code.
8215 * @param pDevIns The device instance.
8216 */
8217int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
8218{
8219 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
8220 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
8221
8222 /*
8223 * Ask the FIFO thread to terminate the 3d state and then terminate it.
8224 */
8225 if (pThisCC->svga.pFIFOIOThread)
8226 {
8227 int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
8228 NULL /*pvParam*/, 30000 /*ms*/);
8229 AssertLogRelRC(rc);
8230
8231 rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
8232 AssertLogRelRC(rc);
8233 pThisCC->svga.pFIFOIOThread = NULL;
8234 }
8235
8236 /*
8237 * Destroy the special SVGA state.
8238 */
8239 if (pThisCC->svga.pSvgaR3State)
8240 {
8241 vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
8242
8243 RTMemFree(pThisCC->svga.pSvgaR3State);
8244 pThisCC->svga.pSvgaR3State = NULL;
8245 }
8246
8247 /*
8248 * Free our resources residing in the VGA state.
8249 */
8250 if (pThisCC->svga.pbVgaFrameBufferR3)
8251 {
8252 RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
8253 pThisCC->svga.pbVgaFrameBufferR3 = NULL;
8254 }
8255 if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
8256 {
8257 RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
8258 pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
8259 }
8260 if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
8261 {
8262 PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
8263 pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
8264 }
8265
8266 return VINF_SUCCESS;
8267}
8268
8269/**
8270 * Initialize the SVGA hardware state
8271 *
8272 * @returns VBox status code.
8273 * @param pDevIns The device instance.
8274 */
8275int vmsvgaR3Init(PPDMDEVINS pDevIns)
8276{
8277 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
8278 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
8279 PVMSVGAR3STATE pSVGAState;
8280 int rc;
8281
8282 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
8283 memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
8284
8285 pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
8286
8287 /* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
8288 pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
8289 AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
8290
8291 /* Create event semaphore. */
8292 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
8293 AssertRCReturn(rc, rc);
8294
8295 /* Create event semaphore. */
8296 rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
8297 AssertRCReturn(rc, rc);
8298
8299 pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
8300 AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
8301
8302 rc = vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
8303 AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
8304
8305 pSVGAState = pThisCC->svga.pSvgaR3State;
8306
8307 /* Initialize FIFO and register capabilities. */
8308 vmsvgaR3InitCaps(pThis, pThisCC);
8309
8310# ifdef VBOX_WITH_VMSVGA3D
8311 if (pThis->svga.f3DEnabled)
8312 {
8313 rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
8314 if (RT_FAILURE(rc))
8315 {
8316 LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
8317 pThis->svga.f3DEnabled = false;
8318 }
8319 }
8320# endif
8321 /* VRAM tracking is enabled by default during bootup. */
8322 pThis->svga.fVRAMTracking = true;
8323
8324 /* Set up the host bpp. This value is as a default for the programmable
8325 * bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
8326 * exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
8327 * separated as SVGA_REG_HOST_BITS_PER_PIXEL.
8328 *
8329 * NB: The driver cBits value is currently constant for the lifetime of the
8330 * VM. If that changes, the host bpp logic might need revisiting.
8331 */
8332 pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
8333
8334 /* Invalidate current settings. */
8335 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
8336 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
8337 pThis->svga.uBpp = pThis->svga.uHostBpp;
8338 pThis->svga.cbScanline = 0;
8339
8340 pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
8341 pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
8342 while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
8343 {
8344 pThis->svga.u32MaxWidth -= 256;
8345 pThis->svga.u32MaxHeight -= 256;
8346 }
8347 Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
8348
8349# ifdef DEBUG_GMR_ACCESS
8350 /* Register the GMR access handler type. */
8351 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
8352 vmsvgaR3GmrAccessHandler,
8353 NULL, NULL, NULL,
8354 NULL, NULL, NULL,
8355 "VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
8356 AssertRCReturn(rc, rc);
8357# endif
8358
8359# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
8360 /* Register the FIFO access handler type. In addition to
8361 debugging FIFO access, this is also used to facilitate
8362 extended fifo thread sleeps. */
8363 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
8364# ifdef DEBUG_FIFO_ACCESS
8365 PGMPHYSHANDLERKIND_ALL,
8366# else
8367 PGMPHYSHANDLERKIND_WRITE,
8368# endif
8369 vmsvgaR3FifoAccessHandler,
8370 NULL, NULL, NULL,
8371 NULL, NULL, NULL,
8372 "VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
8373 AssertRCReturn(rc, rc);
8374# endif
8375
8376 /* Create the async IO thread. */
8377 rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
8378 RTTHREADTYPE_IO, "VMSVGA FIFO");
8379 if (RT_FAILURE(rc))
8380 {
8381 AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
8382 return rc;
8383 }
8384
8385 /*
8386 * Statistics.
8387 */
8388# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
8389 PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
8390# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
8391 PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
8392# ifdef VBOX_WITH_STATISTICS
8393 REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
8394 REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
8395 REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
8396# endif
8397 REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
8398 REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
8399 REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
8400 REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
8401 REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
8402 REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
8403 REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
8404 REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
8405 REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
8406 REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
8407 REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
8408 REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
8409 REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
8410 REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
8411 REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
8412 REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
8413 REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
8414 REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
8415 REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
8416 REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
8417 REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
8418 REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
8419 REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
8420 REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
8421 REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
8422 REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
8423 REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
8424 REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
8425 REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
8426 REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
8427 REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
8428 REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
8429 REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
8430 REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
8431 REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
8432 REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
8433 REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
8434 REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
8435 REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
8436 REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
8437 REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
8438 REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
8439 REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
8440 REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
8441 REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
8442 REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
8443 REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
8444 REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
8445 REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
8446 REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
8447 REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
8448 REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
8449 REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
8450 REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
8451 REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
8452 REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
8453 REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
8454 REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
8455 REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
8456
8457 REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
8458 REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
8459 REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
8460 REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
8461 REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
8462 REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
8463 REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
8464 REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
8465 REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_CURSOR_ID writes.");
8466 REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
8467 REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
8468 REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
8469 REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
8470 REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
8471 REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
8472 REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
8473 REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
8474 REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
8475 REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
8476 REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
8477 REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
8478 REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
8479 REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
8480 REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
8481 REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
8482 REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
8483 REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
8484 REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
8485 REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
8486 REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
8487 REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
8488 REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
8489 REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
8490 REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
8491 REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
8492 REG_CNT(&pThis->svga.StatRegCommandLowWr, "VMSVGA/Reg/CommandLowWrite", "SVGA_REG_COMMAND_LOW writes.");
8493 REG_CNT(&pThis->svga.StatRegCommandHighWr, "VMSVGA/Reg/CommandHighWrite", "SVGA_REG_COMMAND_HIGH writes.");
8494 REG_CNT(&pThis->svga.StatRegDevCapWr, "VMSVGA/Reg/DevCapWrite", "SVGA_REG_DEV_CAP writes.");
8495 REG_CNT(&pThis->svga.StatRegCmdPrependLowWr, "VMSVGA/Reg/CmdPrependLowWrite", "SVGA_REG_CMD_PREPEND_LOW writes.");
8496 REG_CNT(&pThis->svga.StatRegCmdPrependHighWr, "VMSVGA/Reg/CmdPrependHighWrite", "SVGA_REG_iCMD_PREPEND_HIGH writes.");
8497
8498 REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
8499 REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
8500 REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
8501 REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
8502 REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
8503 REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
8504 REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
8505 REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
8506 REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_CURSOR_ID reads.");
8507 REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
8508 REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
8509 REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
8510 REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
8511 REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
8512 REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
8513 REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
8514 REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
8515 REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
8516 REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
8517 REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
8518 REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
8519 REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
8520 REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
8521 REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
8522 REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
8523 REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
8524 REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
8525 REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
8526 REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
8527 REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
8528 REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
8529 REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
8530 REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
8531 REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
8532 REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
8533 REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
8534 REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
8535 REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
8536 REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
8537 REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
8538 REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
8539 REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
8540 REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
8541 REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
8542 REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
8543 REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
8544 REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
8545 REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
8546 REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
8547 REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
8548 REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
8549 REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
8550 REG_CNT(&pThis->svga.StatRegCommandLowRd, "VMSVGA/Reg/CommandLowRead", "SVGA_REG_COMMAND_LOW reads.");
8551 REG_CNT(&pThis->svga.StatRegCommandHighRd, "VMSVGA/Reg/CommandHighRead", "SVGA_REG_COMMAND_HIGH reads.");
8552 REG_CNT(&pThis->svga.StatRegMaxPrimBBMemRd, "VMSVGA/Reg/MaxPrimBBMemRead", "SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM reads.");
8553 REG_CNT(&pThis->svga.StatRegGBMemSizeRd, "VMSVGA/Reg/GBMemSizeRead", "SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB reads.");
8554 REG_CNT(&pThis->svga.StatRegDevCapRd, "VMSVGA/Reg/DevCapRead", "SVGA_REG_DEV_CAP reads.");
8555 REG_CNT(&pThis->svga.StatRegCmdPrependLowRd, "VMSVGA/Reg/CmdPrependLowRead", "SVGA_REG_CMD_PREPEND_LOW reads.");
8556 REG_CNT(&pThis->svga.StatRegCmdPrependHighRd, "VMSVGA/Reg/CmdPrependHighRead", "SVGA_REG_iCMD_PREPEND_HIGH reads.");
8557 REG_CNT(&pThis->svga.StatRegScrnTgtMaxWidthRd, "VMSVGA/Reg/ScrnTgtMaxWidthRead", "SVGA_REG_SCREENTARGET_MAX_WIDTH reads.");
8558 REG_CNT(&pThis->svga.StatRegScrnTgtMaxHeightRd, "VMSVGA/Reg/ScrnTgtMaxHeightRead", "SVGA_REG_SCREENTARGET_MAX_HEIGHT reads.");
8559 REG_CNT(&pThis->svga.StatRegMobMaxSizeRd, "VMSVGA/Reg/MobMaxSizeRead", "SVGA_REG_MOB_MAX_SIZE reads.");
8560
8561 REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
8562 REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
8563 REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
8564 REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
8565 REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
8566 REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
8567 REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
8568 REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
8569# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
8570 REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
8571# endif
8572 REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
8573 REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
8574 REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
8575 REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
8576 REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
8577
8578# undef REG_CNT
8579# undef REG_PRF
8580
8581 /*
8582 * Info handlers.
8583 */
8584 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
8585# ifdef VBOX_WITH_VMSVGA3D
8586 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
8587 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
8588 "VMSVGA 3d surface details. "
8589 "Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
8590 vmsvgaR3Info3dSurface);
8591 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
8592 "VMSVGA 3d surface details and bitmap: "
8593 "sid[>dir]",
8594 vmsvgaR3Info3dSurfaceBmp);
8595# endif
8596
8597 return VINF_SUCCESS;
8598}
8599
8600/**
8601 * Power On notification.
8602 *
8603 * @returns VBox status code.
8604 * @param pDevIns The device instance data.
8605 *
8606 * @remarks Caller enters the device critical section.
8607 */
8608DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
8609{
8610# ifdef VBOX_WITH_VMSVGA3D
8611 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
8612 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
8613 if (pThis->svga.f3DEnabled)
8614 {
8615 int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
8616 if (RT_SUCCESS(rc))
8617 {
8618 /* Initialize FIFO 3D capabilities. */
8619 vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
8620 }
8621 }
8622# else /* !VBOX_WITH_VMSVGA3D */
8623 RT_NOREF(pDevIns);
8624# endif /* !VBOX_WITH_VMSVGA3D */
8625}
8626
8627/**
8628 * Power Off notification.
8629 *
8630 * @param pDevIns The device instance data.
8631 *
8632 * @remarks Caller enters the device critical section.
8633 */
8634DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns)
8635{
8636 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
8637 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
8638
8639 /*
8640 * Notify the FIFO thread.
8641 */
8642 if (pThisCC->svga.pFIFOIOThread)
8643 {
8644 int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_POWEROFF,
8645 NULL /*pvParam*/, 30000 /*ms*/);
8646 AssertLogRelRC(rc);
8647 }
8648}
8649
8650#endif /* IN_RING3 */
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