DevVGA-SVGA.cpp@ 82968

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1	/* $Id: DevVGA-SVGA.cpp 82968 2020-02-04 10:35:17Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - LogRel for the usual important stuff.
13	* - LogRel2 for cursor.
14	* - LogRel3 for 3D performance data.
15	*/
16
17	/*
18	* Copyright (C) 2013-2020 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29
30	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
31	*
32	* This device emulation was contributed by trivirt AG. It offers an
33	* alternative to our Bochs based VGA graphics and 3d emulations. This is
34	* valuable for Xorg based guests, as there is driver support shipping with Xorg
35	* since it forked from XFree86.
36	*
37	*
38	* @section sec_dev_vmsvga_sdk The VMware SDK
39	*
40	* This is officially deprecated now, however it's still quite useful,
41	* especially for getting the old features working:
42	* http://vmware-svga.sourceforge.net/
43	*
44	* They currently point developers at the following resources.
45	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
46	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
47	* - http://cgit.freedesktop.org/mesa/vmwgfx/
48	*
49	* @subsection subsec_dev_vmsvga_sdk_results Test results
50	*
51	* Test results:
52	* - 2dmark.img:
53	* + todo
54	* - backdoor-tclo.img:
55	* + todo
56	* - blit-cube.img:
57	* + todo
58	* - bunnies.img:
59	* + todo
60	* - cube.img:
61	* + todo
62	* - cubemark.img:
63	* + todo
64	* - dynamic-vertex-stress.img:
65	* + todo
66	* - dynamic-vertex.img:
67	* + todo
68	* - fence-stress.img:
69	* + todo
70	* - gmr-test.img:
71	* + todo
72	* - half-float-test.img:
73	* + todo
74	* - noscreen-cursor.img:
75	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
76	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
77	* visible though.)
78	* - Cursor animation via the palette doesn't work.
79	* - During debugging, it turns out that the framebuffer content seems to
80	* be halfways ignore or something (memset(fb, 0xcc, lots)).
81	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
82	* grow it 0x10 fold (128KB -> 2MB like in WS10).
83	* - null.img:
84	* + todo
85	* - pong.img:
86	* + todo
87	* - presentReadback.img:
88	* + todo
89	* - resolution-set.img:
90	* + todo
91	* - rt-gamma-test.img:
92	* + todo
93	* - screen-annotation.img:
94	* + todo
95	* - screen-cursor.img:
96	* + todo
97	* - screen-dma-coalesce.img:
98	* + todo
99	* - screen-gmr-discontig.img:
100	* + todo
101	* - screen-gmr-remap.img:
102	* + todo
103	* - screen-multimon.img:
104	* + todo
105	* - screen-present-clip.img:
106	* + todo
107	* - screen-render-test.img:
108	* + todo
109	* - screen-simple.img:
110	* + todo
111	* - screen-text.img:
112	* + todo
113	* - simple-shaders.img:
114	* + todo
115	* - simple_blit.img:
116	* + todo
117	* - tiny-2d-updates.img:
118	* + todo
119	* - video-formats.img:
120	* + todo
121	* - video-sync.img:
122	* + todo
123	*
124	*/
125
126
127	/*********************************************************************************************************************************
128	* Header Files *
129	*********************************************************************************************************************************/
130	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
131	#define VMSVGA_USE_EMT_HALT_CODE
132	#include <VBox/vmm/pdmdev.h>
133	#include <VBox/version.h>
134	#include <VBox/err.h>
135	#include <VBox/log.h>
136	#include <VBox/vmm/pgm.h>
137	#ifdef VMSVGA_USE_EMT_HALT_CODE
138	# include <VBox/vmm/vmapi.h>
139	# include <VBox/vmm/vmcpuset.h>
140	#endif
141	#include <VBox/sup.h>
142
143	#include <iprt/assert.h>
144	#include <iprt/semaphore.h>
145	#include <iprt/uuid.h>
146	#ifdef IN_RING3
147	# include <iprt/ctype.h>
148	# include <iprt/mem.h>
149	# ifdef VBOX_STRICT
150	# include <iprt/time.h>
151	# endif
152	#endif
153
154	#include <VBox/AssertGuest.h>
155	#include <VBox/VMMDev.h>
156	#include <VBoxVideo.h>
157	#include <VBox/bioslogo.h>
158
159	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
160	#include "DevVGA.h"
161
162	#include "DevVGA-SVGA.h"
163	#include "vmsvga/svga_escape.h"
164	#include "vmsvga/svga_overlay.h"
165	#include "vmsvga/svga3d_caps.h"
166	#ifdef VBOX_WITH_VMSVGA3D
167	# include "DevVGA-SVGA3d.h"
168	# ifdef RT_OS_DARWIN
169	# include "DevVGA-SVGA3d-cocoa.h"
170	# endif
171	#endif
172
173
174	/*********************************************************************************************************************************
175	* Defined Constants And Macros *
176	*********************************************************************************************************************************/
177	/**
178	* Macro for checking if a fixed FIFO register is valid according to the
179	* current FIFO configuration.
180	*
181	* @returns true / false.
182	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
183	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
184	*/
185	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
186
187
188	/*********************************************************************************************************************************
189	* Structures and Typedefs *
190	*********************************************************************************************************************************/
191	/**
192	* 64-bit GMR descriptor.
193	*/
194	typedef struct
195	{
196	RTGCPHYS GCPhys;
197	uint64_t numPages;
198	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
199
200	/**
201	* GMR slot
202	*/
203	typedef struct
204	{
205	uint32_t cMaxPages;
206	uint32_t cbTotal;
207	uint32_t numDescriptors;
208	PVMSVGAGMRDESCRIPTOR paDesc;
209	} GMR, *PGMR;
210
211	#ifdef IN_RING3
212	/**
213	* Internal SVGA ring-3 only state.
214	*/
215	typedef struct VMSVGAR3STATE
216	{
217	GMR *paGMR; // [VMSVGAState::cGMR]
218	struct
219	{
220	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
221	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
222	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
223	} GMRFB;
224	struct
225	{
226	bool fActive;
227	uint32_t xHotspot;
228	uint32_t yHotspot;
229	uint32_t width;
230	uint32_t height;
231	uint32_t cbData;
232	void *pData;
233	} Cursor;
234	SVGAColorBGRX colorAnnotation;
235
236	# ifdef VMSVGA_USE_EMT_HALT_CODE
237	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
238	uint32_t volatile cBusyDelayedEmts;
239	/** Set of EMTs that are */
240	VMCPUSET BusyDelayedEmts;
241	# else
242	/** Number of EMTs waiting on hBusyDelayedEmts. */
243	uint32_t volatile cBusyDelayedEmts;
244	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
245	* busy (ugly). */
246	RTSEMEVENTMULTI hBusyDelayedEmts;
247	# endif
248
249	/** Information obout screens. */
250	VMSVGASCREENOBJECT aScreens[64];
251
252	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
253	STAMPROFILE StatBusyDelayEmts;
254
255	STAMPROFILE StatR3Cmd3dPresentProf;
256	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
257	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
258	STAMPROFILE StatR3Cmd3dBlitSurfaceToScreenProf;
259	STAMCOUNTER StatR3CmdDefineGmr2;
260	STAMCOUNTER StatR3CmdDefineGmr2Free;
261	STAMCOUNTER StatR3CmdDefineGmr2Modify;
262	STAMCOUNTER StatR3CmdRemapGmr2;
263	STAMCOUNTER StatR3CmdRemapGmr2Modify;
264	STAMCOUNTER StatR3CmdInvalidCmd;
265	STAMCOUNTER StatR3CmdFence;
266	STAMCOUNTER StatR3CmdUpdate;
267	STAMCOUNTER StatR3CmdUpdateVerbose;
268	STAMCOUNTER StatR3CmdDefineCursor;
269	STAMCOUNTER StatR3CmdDefineAlphaCursor;
270	STAMCOUNTER StatR3CmdEscape;
271	STAMCOUNTER StatR3CmdDefineScreen;
272	STAMCOUNTER StatR3CmdDestroyScreen;
273	STAMCOUNTER StatR3CmdDefineGmrFb;
274	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
275	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
276	STAMCOUNTER StatR3CmdAnnotationFill;
277	STAMCOUNTER StatR3CmdAnnotationCopy;
278	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
279	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
280	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
281	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
282	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
283	STAMCOUNTER StatR3Cmd3dSurfaceDma;
284	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
285	STAMCOUNTER StatR3Cmd3dContextDefine;
286	STAMCOUNTER StatR3Cmd3dContextDestroy;
287	STAMCOUNTER StatR3Cmd3dSetTransform;
288	STAMCOUNTER StatR3Cmd3dSetZRange;
289	STAMCOUNTER StatR3Cmd3dSetRenderState;
290	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
291	STAMCOUNTER StatR3Cmd3dSetTextureState;
292	STAMCOUNTER StatR3Cmd3dSetMaterial;
293	STAMCOUNTER StatR3Cmd3dSetLightData;
294	STAMCOUNTER StatR3Cmd3dSetLightEnable;
295	STAMCOUNTER StatR3Cmd3dSetViewPort;
296	STAMCOUNTER StatR3Cmd3dSetClipPlane;
297	STAMCOUNTER StatR3Cmd3dClear;
298	STAMCOUNTER StatR3Cmd3dPresent;
299	STAMCOUNTER StatR3Cmd3dPresentReadBack;
300	STAMCOUNTER StatR3Cmd3dShaderDefine;
301	STAMCOUNTER StatR3Cmd3dShaderDestroy;
302	STAMCOUNTER StatR3Cmd3dSetShader;
303	STAMCOUNTER StatR3Cmd3dSetShaderConst;
304	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
305	STAMCOUNTER StatR3Cmd3dSetScissorRect;
306	STAMCOUNTER StatR3Cmd3dBeginQuery;
307	STAMCOUNTER StatR3Cmd3dEndQuery;
308	STAMCOUNTER StatR3Cmd3dWaitForQuery;
309	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
310	STAMCOUNTER StatR3Cmd3dActivateSurface;
311	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
312
313	STAMCOUNTER StatR3RegConfigDoneWr;
314	STAMCOUNTER StatR3RegGmrDescriptorWr;
315	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
316	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
317
318	STAMCOUNTER StatFifoCommands;
319	STAMCOUNTER StatFifoErrors;
320	STAMCOUNTER StatFifoUnkCmds;
321	STAMCOUNTER StatFifoTodoTimeout;
322	STAMCOUNTER StatFifoTodoWoken;
323	STAMPROFILE StatFifoStalls;
324	STAMPROFILE StatFifoExtendedSleep;
325	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
326	STAMCOUNTER StatFifoAccessHandler;
327	# endif
328	STAMCOUNTER StatFifoCursorFetchAgain;
329	STAMCOUNTER StatFifoCursorNoChange;
330	STAMCOUNTER StatFifoCursorPosition;
331	STAMCOUNTER StatFifoCursorVisiblity;
332	STAMCOUNTER StatFifoWatchdogWakeUps;
333	} VMSVGAR3STATE, *PVMSVGAR3STATE;
334	#endif /* IN_RING3 */
335
336
337	/*********************************************************************************************************************************
338	* Internal Functions *
339	*********************************************************************************************************************************/
340	#ifdef IN_RING3
341	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
342	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
343	# endif
344	# ifdef DEBUG_GMR_ACCESS
345	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
346	# endif
347	#endif
348
349
350	/*********************************************************************************************************************************
351	* Global Variables *
352	*********************************************************************************************************************************/
353	#ifdef IN_RING3
354
355	/**
356	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
357	*/
358	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
359	{
360	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
361	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
362	SSMFIELD_ENTRY_TERM()
363	};
364
365	/**
366	* SSM descriptor table for the GMR structure.
367	*/
368	static SSMFIELD const g_aGMRFields[] =
369	{
370	SSMFIELD_ENTRY( GMR, cMaxPages),
371	SSMFIELD_ENTRY( GMR, cbTotal),
372	SSMFIELD_ENTRY( GMR, numDescriptors),
373	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
374	SSMFIELD_ENTRY_TERM()
375	};
376
377	/**
378	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
379	*/
380	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
381	{
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
389	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
390	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
391	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
392	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
393	SSMFIELD_ENTRY_TERM()
394	};
395
396	/**
397	* SSM descriptor table for the VMSVGAR3STATE structure.
398	*/
399	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
400	{
401	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
404	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
405	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
406	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
407	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
408	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
409	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
410	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
412	#ifdef VMSVGA_USE_EMT_HALT_CODE
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
414	#else
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
416	#endif
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
475
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
480
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
485	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
488	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
490	# endif
491	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
492	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
493	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
494	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
495
496	SSMFIELD_ENTRY_TERM()
497	};
498
499	/**
500	* SSM descriptor table for the VGAState.svga structure.
501	*/
502	static SSMFIELD const g_aVGAStateSVGAFields[] =
503	{
504	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
505	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
507	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
508	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
509	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
510	SSMFIELD_ENTRY( VMSVGAState, fBusy),
511	SSMFIELD_ENTRY( VMSVGAState, fTraces),
512	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
513	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
514	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
515	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
516	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
517	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
518	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
519	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
520	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
521	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
523	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
524	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
525	SSMFIELD_ENTRY( VMSVGAState, uWidth),
526	SSMFIELD_ENTRY( VMSVGAState, uHeight),
527	SSMFIELD_ENTRY( VMSVGAState, uBpp),
528	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
529	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
530	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
531	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
532	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
533	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
534	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
535	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
536	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
537	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
538	SSMFIELD_ENTRY_TERM()
539	};
540	#endif /* IN_RING3 */
541
542
543	/*********************************************************************************************************************************
544	* Internal Functions *
545	*********************************************************************************************************************************/
546	#ifdef IN_RING3
547	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
548	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
549	uint32_t uVersion, uint32_t uPass);
550	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
551	# ifdef VBOX_WITH_VMSVGA3D
552	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR);
553	# endif /* VBOX_WITH_VMSVGA3D */
554	#endif /* IN_RING3 */
555
556
557
558	#ifdef IN_RING3
559	VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
560	{
561	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
562	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
563	&& pSVGAState
564	&& pSVGAState->aScreens[idScreen].fDefined)
565	{
566	return &pSVGAState->aScreens[idScreen];
567	}
568	return NULL;
569	}
570	#endif /* IN_RING3 */
571
572	#ifdef LOG_ENABLED
573
574	/**
575	* Index register string name lookup
576	*
577	* @returns Index register string or "UNKNOWN"
578	* @param pThis The shared VGA/VMSVGA state.
579	* @param idxReg The index register.
580	*/
581	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
582	{
583	switch (idxReg)
584	{
585	case SVGA_REG_ID: return "SVGA_REG_ID";
586	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
587	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
588	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
589	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
590	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
591	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
592	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
593	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
594	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
595	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
596	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
597	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
598	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
599	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
600	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
601	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
602	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
603	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
604	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
605	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
606	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
607	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
608	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
609	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
610	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
611	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
612	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
613	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
614	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
615	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
616	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
617	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
618	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
619	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
620	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
621	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
622	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
623	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
624	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
625	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
626	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
627	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
628	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
629	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
630	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
631	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
632	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
633	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
634	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
635
636	default:
637	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
638	return "SVGA_SCRATCH_BASE reg";
639	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
640	return "SVGA_PALETTE_BASE reg";
641	return "UNKNOWN";
642	}
643	}
644
645	#ifdef IN_RING3
646	/**
647	* FIFO command name lookup
648	*
649	* @returns FIFO command string or "UNKNOWN"
650	* @param u32Cmd FIFO command
651	*/
652	static const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
653	{
654	switch (u32Cmd)
655	{
656	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
657	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
658	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
659	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
660	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
661	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
662	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
663	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
664	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
665	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
666	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
667	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
668	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
669	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
670	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
671	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
672	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
673	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
674	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
675	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
676	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
677	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
678	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
679	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
680	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
681	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
682	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
683	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
684	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
685	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
686	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
687	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
688	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
689	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
690	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
691	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
692	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
693	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
694	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
695	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
696	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
697	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
698	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
699	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
700	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
701	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
702	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
703	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
704	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
705	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
706	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
707	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
708	default: return "UNKNOWN";
709	}
710	}
711	# endif /* IN_RING3 */
712
713	#endif /* LOG_ENABLED */
714
715	#ifdef IN_RING3
716	/**
717	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
718	*/
719	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
720	{
721	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
722	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
723
724	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
725	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
726
727	/** @todo Test how it interacts with multiple screen objects. */
728	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
729	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
730	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
731
732	if (x < uWidth)
733	{
734	pThis->svga.viewport.x = x;
735	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
736	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
737	}
738	else
739	{
740	pThis->svga.viewport.x = uWidth;
741	pThis->svga.viewport.cx = 0;
742	pThis->svga.viewport.xRight = uWidth;
743	}
744	if (y < uHeight)
745	{
746	pThis->svga.viewport.y = y;
747	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
748	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
749	pThis->svga.viewport.yHighWC = uHeight - y;
750	}
751	else
752	{
753	pThis->svga.viewport.y = uHeight;
754	pThis->svga.viewport.cy = 0;
755	pThis->svga.viewport.yLowWC = 0;
756	pThis->svga.viewport.yHighWC = 0;
757	}
758
759	# ifdef VBOX_WITH_VMSVGA3D
760	/*
761	* Now inform the 3D backend.
762	*/
763	if (pThis->svga.f3DEnabled)
764	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
765	# else
766	RT_NOREF(OldViewport);
767	# endif
768	}
769	#endif /* IN_RING3 */
770
771	/**
772	* Read port register
773	*
774	* @returns VBox status code.
775	* @param pDevIns The device instance.
776	* @param pThis The shared VGA/VMSVGA state.
777	* @param pu32 Where to store the read value
778	*/
779	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
780	{
781	#ifdef IN_RING3
782	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
783	#endif
784	int rc = VINF_SUCCESS;
785	*pu32 = 0;
786
787	/* Rough index register validation. */
788	uint32_t idxReg = pThis->svga.u32IndexReg;
789	#if !defined(IN_RING3) && defined(VBOX_STRICT)
790	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
791	VINF_IOM_R3_IOPORT_READ);
792	#else
793	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
794	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
795	VINF_SUCCESS);
796	#endif
797	RT_UNTRUSTED_VALIDATED_FENCE();
798
799	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
800	if ( idxReg >= SVGA_REG_CAPABILITIES
801	&& pThis->svga.u32SVGAId == SVGA_ID_0)
802	{
803	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
804	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
805	}
806
807	switch (idxReg)
808	{
809	case SVGA_REG_ID:
810	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
811	*pu32 = pThis->svga.u32SVGAId;
812	break;
813
814	case SVGA_REG_ENABLE:
815	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
816	*pu32 = pThis->svga.fEnabled;
817	break;
818
819	case SVGA_REG_WIDTH:
820	{
821	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
822	if ( pThis->svga.fEnabled
823	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
824	*pu32 = pThis->svga.uWidth;
825	else
826	{
827	#ifndef IN_RING3
828	rc = VINF_IOM_R3_IOPORT_READ;
829	#else
830	*pu32 = pThisCC->pDrv->cx;
831	#endif
832	}
833	break;
834	}
835
836	case SVGA_REG_HEIGHT:
837	{
838	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
839	if ( pThis->svga.fEnabled
840	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
841	*pu32 = pThis->svga.uHeight;
842	else
843	{
844	#ifndef IN_RING3
845	rc = VINF_IOM_R3_IOPORT_READ;
846	#else
847	*pu32 = pThisCC->pDrv->cy;
848	#endif
849	}
850	break;
851	}
852
853	case SVGA_REG_MAX_WIDTH:
854	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
855	*pu32 = pThis->svga.u32MaxWidth;
856	break;
857
858	case SVGA_REG_MAX_HEIGHT:
859	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
860	*pu32 = pThis->svga.u32MaxHeight;
861	break;
862
863	case SVGA_REG_DEPTH:
864	/* This returns the color depth of the current mode. */
865	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
866	switch (pThis->svga.uBpp)
867	{
868	case 15:
869	case 16:
870	case 24:
871	*pu32 = pThis->svga.uBpp;
872	break;
873
874	default:
875	case 32:
876	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
877	break;
878	}
879	break;
880
881	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
882	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
883	if ( pThis->svga.fEnabled
884	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
885	*pu32 = pThis->svga.uBpp;
886	else
887	{
888	#ifndef IN_RING3
889	rc = VINF_IOM_R3_IOPORT_READ;
890	#else
891	*pu32 = pThisCC->pDrv->cBits;
892	#endif
893	}
894	break;
895
896	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
897	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
898	if ( pThis->svga.fEnabled
899	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
900	*pu32 = (pThis->svga.uBpp + 7) & ~7;
901	else
902	{
903	#ifndef IN_RING3
904	rc = VINF_IOM_R3_IOPORT_READ;
905	#else
906	*pu32 = (pThisCC->pDrv->cBits + 7) & ~7;
907	#endif
908	}
909	break;
910
911	case SVGA_REG_PSEUDOCOLOR:
912	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
913	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
914	break;
915
916	case SVGA_REG_RED_MASK:
917	case SVGA_REG_GREEN_MASK:
918	case SVGA_REG_BLUE_MASK:
919	{
920	uint32_t uBpp;
921
922	if ( pThis->svga.fEnabled
923	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
924	{
925	uBpp = pThis->svga.uBpp;
926	}
927	else
928	{
929	#ifndef IN_RING3
930	rc = VINF_IOM_R3_IOPORT_READ;
931	break;
932	#else
933	uBpp = pThisCC->pDrv->cBits;
934	#endif
935	}
936	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
937	switch (uBpp)
938	{
939	case 8:
940	u32RedMask = 0x07;
941	u32GreenMask = 0x38;
942	u32BlueMask = 0xc0;
943	break;
944
945	case 15:
946	u32RedMask = 0x0000001f;
947	u32GreenMask = 0x000003e0;
948	u32BlueMask = 0x00007c00;
949	break;
950
951	case 16:
952	u32RedMask = 0x0000001f;
953	u32GreenMask = 0x000007e0;
954	u32BlueMask = 0x0000f800;
955	break;
956
957	case 24:
958	case 32:
959	default:
960	u32RedMask = 0x00ff0000;
961	u32GreenMask = 0x0000ff00;
962	u32BlueMask = 0x000000ff;
963	break;
964	}
965	switch (idxReg)
966	{
967	case SVGA_REG_RED_MASK:
968	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
969	*pu32 = u32RedMask;
970	break;
971
972	case SVGA_REG_GREEN_MASK:
973	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
974	*pu32 = u32GreenMask;
975	break;
976
977	case SVGA_REG_BLUE_MASK:
978	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
979	*pu32 = u32BlueMask;
980	break;
981	}
982	break;
983	}
984
985	case SVGA_REG_BYTES_PER_LINE:
986	{
987	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
988	if ( pThis->svga.fEnabled
989	&& pThis->svga.cbScanline)
990	*pu32 = pThis->svga.cbScanline;
991	else
992	{
993	#ifndef IN_RING3
994	rc = VINF_IOM_R3_IOPORT_READ;
995	#else
996	*pu32 = pThisCC->pDrv->cbScanline;
997	#endif
998	}
999	break;
1000	}
1001
1002	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1003	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1004	*pu32 = pThis->vram_size;
1005	break;
1006
1007	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1008	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1009	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1010	*pu32 = pThis->GCPhysVRAM;
1011	break;
1012
1013	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1014	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1015	/* Always zero in our case. */
1016	*pu32 = 0;
1017	break;
1018
1019	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1020	{
1021	#ifndef IN_RING3
1022	rc = VINF_IOM_R3_IOPORT_READ;
1023	#else
1024	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1025
1026	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1027	if ( pThis->svga.fEnabled
1028	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1029	{
1030	/* Hardware enabled; return real framebuffer size .*/
1031	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1032	}
1033	else
1034	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1035
1036	pu32 = RT_MIN(pThis->vram_size, pu32);
1037	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1038	#endif
1039	break;
1040	}
1041
1042	case SVGA_REG_CAPABILITIES:
1043	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1044	*pu32 = pThis->svga.u32RegCaps;
1045	break;
1046
1047	case SVGA_REG_MEM_START: /* FIFO start */
1048	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1049	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1050	*pu32 = pThis->svga.GCPhysFIFO;
1051	break;
1052
1053	case SVGA_REG_MEM_SIZE: /* FIFO size */
1054	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1055	*pu32 = pThis->svga.cbFIFO;
1056	break;
1057
1058	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1059	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1060	*pu32 = pThis->svga.fConfigured;
1061	break;
1062
1063	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1064	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1065	*pu32 = 0;
1066	break;
1067
1068	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1069	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1070	if (pThis->svga.fBusy)
1071	{
1072	#ifndef IN_RING3
1073	/* Go to ring-3 and halt the CPU. */
1074	rc = VINF_IOM_R3_IOPORT_READ;
1075	RT_NOREF(pDevIns);
1076	break;
1077	#else
1078	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1079	/* The guest is basically doing a HLT via the device here, but with
1080	a special wake up condition on FIFO completion. */
1081	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1082	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1083	PVM pVM = PDMDevHlpGetVM(pDevIns);
1084	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1085	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1086	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1087	if (pThis->svga.fBusy)
1088	{
1089	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1090	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1091	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1092	}
1093	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1094	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1095	# else
1096
1097	/* Delay the EMT a bit so the FIFO and others can get some work done.
1098	This used to be a crude 50 ms sleep. The current code tries to be
1099	more efficient, but the consept is still very crude. */
1100	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1101	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1102	RTThreadYield();
1103	if (pThis->svga.fBusy)
1104	{
1105	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1106
1107	if (pThis->svga.fBusy && cRefs == 1)
1108	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1109	if (pThis->svga.fBusy)
1110	{
1111	/** @todo If this code is going to stay, we need to call into the halt/wait
1112	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1113	* suffer when the guest is polling on a busy FIFO. */
1114	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns));
1115	if (cNsMaxWait >= RT_NS_100US)
1116	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1117	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1118	RT_MIN(cNsMaxWait, RT_NS_10MS));
1119	}
1120
1121	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1122	}
1123	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1124	# endif
1125	*pu32 = pThis->svga.fBusy != 0;
1126	#endif
1127	}
1128	else
1129	*pu32 = false;
1130	break;
1131
1132	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1133	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1134	*pu32 = pThis->svga.u32GuestId;
1135	break;
1136
1137	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1138	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1139	*pu32 = pThis->svga.cScratchRegion;
1140	break;
1141
1142	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1143	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1144	*pu32 = SVGA_FIFO_NUM_REGS;
1145	break;
1146
1147	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1148	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1149	*pu32 = pThis->svga.u32PitchLock;
1150	break;
1151
1152	case SVGA_REG_IRQMASK: /* Interrupt mask */
1153	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1154	*pu32 = pThis->svga.u32IrqMask;
1155	break;
1156
1157	/* See "Guest memory regions" below. */
1158	case SVGA_REG_GMR_ID:
1159	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1160	*pu32 = pThis->svga.u32CurrentGMRId;
1161	break;
1162
1163	case SVGA_REG_GMR_DESCRIPTOR:
1164	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1165	/* Write only */
1166	*pu32 = 0;
1167	break;
1168
1169	case SVGA_REG_GMR_MAX_IDS:
1170	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1171	*pu32 = pThis->svga.cGMR;
1172	break;
1173
1174	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1175	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1176	*pu32 = VMSVGA_MAX_GMR_PAGES;
1177	break;
1178
1179	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1180	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1181	*pu32 = pThis->svga.fTraces;
1182	break;
1183
1184	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1185	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1186	*pu32 = VMSVGA_MAX_GMR_PAGES;
1187	break;
1188
1189	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1190	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1191	*pu32 = VMSVGA_SURFACE_SIZE;
1192	break;
1193
1194	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1195	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1196	break;
1197
1198	/* Mouse cursor support. */
1199	case SVGA_REG_CURSOR_ID:
1200	case SVGA_REG_CURSOR_X:
1201	case SVGA_REG_CURSOR_Y:
1202	case SVGA_REG_CURSOR_ON:
1203	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1204	break;
1205
1206	/* Legacy multi-monitor support */
1207	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1208	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1209	*pu32 = 1;
1210	break;
1211
1212	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1213	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1214	*pu32 = 0;
1215	break;
1216
1217	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1218	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1219	*pu32 = 0;
1220	break;
1221
1222	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1223	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1224	*pu32 = 0;
1225	break;
1226
1227	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1228	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1229	*pu32 = 0;
1230	break;
1231
1232	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1233	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1234	*pu32 = pThis->svga.uWidth;
1235	break;
1236
1237	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1238	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1239	*pu32 = pThis->svga.uHeight;
1240	break;
1241
1242	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1243	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1244	/* We must return something sensible here otherwise the Linux driver
1245	will take a legacy code path without 3d support. This number also
1246	limits how many screens Linux guests will allow. */
1247	*pu32 = pThis->cMonitors;
1248	break;
1249
1250	default:
1251	{
1252	uint32_t offReg;
1253	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1254	{
1255	RT_UNTRUSTED_VALIDATED_FENCE();
1256	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1257	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1258	}
1259	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1260	{
1261	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1262	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1263	RT_UNTRUSTED_VALIDATED_FENCE();
1264	uint32_t u32 = pThis->last_palette[offReg / 3];
1265	switch (offReg % 3)
1266	{
1267	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1268	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1269	case 2: pu32 = u32 & 0xff; break; / blue */
1270	}
1271	}
1272	else
1273	{
1274	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1275	rc = VINF_IOM_R3_IOPORT_READ;
1276	#else
1277	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1278
1279	/* Do not assert. The guest might be reading all registers. */
1280	LogFunc(("Unknown reg=%#x\n", idxReg));
1281	#endif
1282	}
1283	break;
1284	}
1285	}
1286	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1287	return rc;
1288	}
1289
1290	#ifdef IN_RING3
1291	/**
1292	* Apply the current resolution settings to change the video mode.
1293	*
1294	* @returns VBox status code.
1295	* @param pThis The shared VGA state.
1296	* @param pThisCC The ring-3 VGA state.
1297	*/
1298	static int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1299	{
1300	int rc;
1301
1302	/* Always do changemode on FIFO thread. */
1303	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1304
1305	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1306
1307	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1308
1309	if (pThis->svga.fGFBRegisters)
1310	{
1311	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1312	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1313	* deletes all screens other than screen #0, and redefines screen
1314	* #0 according to the specified mode. Drivers that use
1315	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1316	*/
1317
1318	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1319	pScreen->fDefined = true;
1320	pScreen->fModified = true;
1321	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1322	pScreen->idScreen = 0;
1323	pScreen->xOrigin = 0;
1324	pScreen->yOrigin = 0;
1325	pScreen->offVRAM = 0;
1326	pScreen->cbPitch = pThis->svga.cbScanline;
1327	pScreen->cWidth = pThis->svga.uWidth;
1328	pScreen->cHeight = pThis->svga.uHeight;
1329	pScreen->cBpp = pThis->svga.uBpp;
1330
1331	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1332	{
1333	/* Delete screen. */
1334	pScreen = &pSVGAState->aScreens[iScreen];
1335	if (pScreen->fDefined)
1336	{
1337	pScreen->fModified = true;
1338	pScreen->fDefined = false;
1339	}
1340	}
1341	}
1342	else
1343	{
1344	/* "If Screen Objects are supported, they can be used to fully
1345	* replace the functionality provided by the framebuffer registers
1346	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1347	*/
1348	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1349	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1350	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1351	}
1352
1353	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1354	{
1355	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1356	if (!pScreen->fModified)
1357	continue;
1358
1359	pScreen->fModified = false;
1360
1361	VBVAINFOVIEW view;
1362	RT_ZERO(view);
1363	view.u32ViewIndex = pScreen->idScreen;
1364	// view.u32ViewOffset = 0;
1365	view.u32ViewSize = pThis->vram_size;
1366	view.u32MaxScreenSize = pThis->vram_size;
1367
1368	VBVAINFOSCREEN screen;
1369	RT_ZERO(screen);
1370	screen.u32ViewIndex = pScreen->idScreen;
1371
1372	if (pScreen->fDefined)
1373	{
1374	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1375	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1376	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1377	{
1378	Assert(pThis->svga.fGFBRegisters);
1379	continue;
1380	}
1381
1382	screen.i32OriginX = pScreen->xOrigin;
1383	screen.i32OriginY = pScreen->yOrigin;
1384	screen.u32StartOffset = pScreen->offVRAM;
1385	screen.u32LineSize = pScreen->cbPitch;
1386	screen.u32Width = pScreen->cWidth;
1387	screen.u32Height = pScreen->cHeight;
1388	screen.u16BitsPerPixel = pScreen->cBpp;
1389	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1390	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1391	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1392	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1393	}
1394	else
1395	{
1396	/* Screen is destroyed. */
1397	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1398	}
1399
1400	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pThisCC->pbVRam, /fResetInputMapping=/ true);
1401	AssertRC(rc);
1402	}
1403
1404	/* Last stuff. For the VGA device screenshot. */
1405	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1406	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1407	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1408	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1409	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1410
1411	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1412	if ( pThis->svga.viewport.cx == 0
1413	&& pThis->svga.viewport.cy == 0)
1414	{
1415	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1416	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1417	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1418	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1419	pThis->svga.viewport.yLowWC = 0;
1420	}
1421
1422	return VINF_SUCCESS;
1423	}
1424
1425	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1426	{
1427	VBVACMDHDR cmd;
1428	cmd.x = (int16_t)(pScreen->xOrigin + x);
1429	cmd.y = (int16_t)(pScreen->yOrigin + y);
1430	cmd.w = (uint16_t)w;
1431	cmd.h = (uint16_t)h;
1432
1433	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1434	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1435	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1436	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1437
1438	return VINF_SUCCESS;
1439	}
1440
1441	#endif /* IN_RING3 */
1442	#if defined(IN_RING0) \|\| defined(IN_RING3)
1443
1444	/**
1445	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1446	*
1447	* @param pThis The shared VGA/VMSVGA instance data.
1448	* @param pThisCC The VGA/VMSVGA state for the current context.
1449	* @param fState The busy state.
1450	*/
1451	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1452	{
1453	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1454
1455	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1456	{
1457	/* Race / unfortunately scheduling. Highly unlikly. */
1458	uint32_t cLoops = 64;
1459	do
1460	{
1461	ASMNopPause();
1462	fState = (pThis->svga.fBusy != 0);
1463	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1464	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1465	}
1466	}
1467
1468
1469	/**
1470	* Update the scanline pitch in response to the guest changing mode
1471	* width/bpp.
1472	*
1473	* @param pThis The shared VGA/VMSVGA state.
1474	* @param pThisCC The VGA/VMSVGA state for the current context.
1475	*/
1476	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1477	{
1478	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1479	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1480	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1481	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1482
1483	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1484	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1485	* location but it has a different meaning.
1486	*/
1487	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1488	uFifoPitchLock = 0;
1489
1490	/* Sanitize values. */
1491	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1492	uFifoPitchLock = 0;
1493	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1494	uRegPitchLock = 0;
1495
1496	/* Prefer the register value to the FIFO value.*/
1497	if (uRegPitchLock)
1498	pThis->svga.cbScanline = uRegPitchLock;
1499	else if (uFifoPitchLock)
1500	pThis->svga.cbScanline = uFifoPitchLock;
1501	else
1502	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1503
1504	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1505	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1506	}
1507
1508	#endif /* IN_RING0 \|\| IN_RING3 */
1509
1510
1511	/**
1512	* Write port register
1513	*
1514	* @returns Strict VBox status code.
1515	* @param pDevIns The device instance.
1516	* @param pThis The shared VGA/VMSVGA state.
1517	* @param pThisCC The VGA/VMSVGA state for the current context.
1518	* @param u32 Value to write
1519	*/
1520	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1521	{
1522	#ifdef IN_RING3
1523	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1524	#endif
1525	VBOXSTRICTRC rc = VINF_SUCCESS;
1526	RT_NOREF(pThisCC);
1527
1528	/* Rough index register validation. */
1529	uint32_t idxReg = pThis->svga.u32IndexReg;
1530	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1531	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1532	VINF_IOM_R3_IOPORT_WRITE);
1533	#else
1534	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1535	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1536	VINF_SUCCESS);
1537	#endif
1538	RT_UNTRUSTED_VALIDATED_FENCE();
1539
1540	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1541	if ( idxReg >= SVGA_REG_CAPABILITIES
1542	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1543	{
1544	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1545	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1546	}
1547	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1548	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1549	switch (idxReg)
1550	{
1551	case SVGA_REG_WIDTH:
1552	case SVGA_REG_HEIGHT:
1553	case SVGA_REG_PITCHLOCK:
1554	case SVGA_REG_BITS_PER_PIXEL:
1555	pThis->svga.fGFBRegisters = true;
1556	break;
1557	default:
1558	break;
1559	}
1560
1561	switch (idxReg)
1562	{
1563	case SVGA_REG_ID:
1564	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1565	if ( u32 == SVGA_ID_0
1566	\|\| u32 == SVGA_ID_1
1567	\|\| u32 == SVGA_ID_2)
1568	pThis->svga.u32SVGAId = u32;
1569	else
1570	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1571	break;
1572
1573	case SVGA_REG_ENABLE:
1574	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1575	#ifdef IN_RING3
1576	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1577	&& pThis->svga.fEnabled == false)
1578	{
1579	/* Make a backup copy of the first 512kb in order to save font data etc. */
1580	/** @todo should probably swap here, rather than copy + zero */
1581	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1582	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1583	}
1584
1585	pThis->svga.fEnabled = u32;
1586	if (pThis->svga.fEnabled)
1587	{
1588	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1589	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1590	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1591	{
1592	/* Keep the current mode. */
1593	pThis->svga.uWidth = pThisCC->pDrv->cx;
1594	pThis->svga.uHeight = pThisCC->pDrv->cy;
1595	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1596	}
1597
1598	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1599	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1600	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1601	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1602	# ifdef LOG_ENABLED
1603	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1604	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1605	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1606	# endif
1607
1608	/* Disable or enable dirty page tracking according to the current fTraces value. */
1609	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1610
1611	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1612	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1613	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1614	}
1615	else
1616	{
1617	/* Restore the text mode backup. */
1618	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1619
1620	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1621
1622	/* Enable dirty page tracking again when going into legacy mode. */
1623	vmsvgaR3SetTraces(pDevIns, pThis, true);
1624
1625	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1626	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1627	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1628
1629	/* Clear the pitch lock. */
1630	pThis->svga.u32PitchLock = 0;
1631	}
1632	#else /* !IN_RING3 */
1633	rc = VINF_IOM_R3_IOPORT_WRITE;
1634	#endif /* !IN_RING3 */
1635	break;
1636
1637	case SVGA_REG_WIDTH:
1638	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1639	if (pThis->svga.uWidth != u32)
1640	{
1641	#if defined(IN_RING3) \|\| defined(IN_RING0)
1642	pThis->svga.uWidth = u32;
1643	vmsvgaHCUpdatePitch(pThis, pThisCC);
1644	if (pThis->svga.fEnabled)
1645	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1646	#else
1647	rc = VINF_IOM_R3_IOPORT_WRITE;
1648	#endif
1649	}
1650	/* else: nop */
1651	break;
1652
1653	case SVGA_REG_HEIGHT:
1654	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1655	if (pThis->svga.uHeight != u32)
1656	{
1657	pThis->svga.uHeight = u32;
1658	if (pThis->svga.fEnabled)
1659	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1660	}
1661	/* else: nop */
1662	break;
1663
1664	case SVGA_REG_DEPTH:
1665	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1666	/** @todo read-only?? */
1667	break;
1668
1669	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1670	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1671	if (pThis->svga.uBpp != u32)
1672	{
1673	#if defined(IN_RING3) \|\| defined(IN_RING0)
1674	pThis->svga.uBpp = u32;
1675	vmsvgaHCUpdatePitch(pThis, pThisCC);
1676	if (pThis->svga.fEnabled)
1677	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1678	#else
1679	rc = VINF_IOM_R3_IOPORT_WRITE;
1680	#endif
1681	}
1682	/* else: nop */
1683	break;
1684
1685	case SVGA_REG_PSEUDOCOLOR:
1686	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1687	break;
1688
1689	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1690	#ifdef IN_RING3
1691	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1692	pThis->svga.fConfigured = u32;
1693	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1694	if (!pThis->svga.fConfigured)
1695	pThis->svga.fTraces = true;
1696	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1697	#else
1698	rc = VINF_IOM_R3_IOPORT_WRITE;
1699	#endif
1700	break;
1701
1702	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1703	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1704	if ( pThis->svga.fEnabled
1705	&& pThis->svga.fConfigured)
1706	{
1707	#if defined(IN_RING3) \|\| defined(IN_RING0)
1708	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1709	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1710	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1711	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1712
1713	/* Kick the FIFO thread to start processing commands again. */
1714	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1715	#else
1716	rc = VINF_IOM_R3_IOPORT_WRITE;
1717	#endif
1718	}
1719	/* else nothing to do. */
1720	else
1721	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1722
1723	break;
1724
1725	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1726	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1727	break;
1728
1729	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1730	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1731	pThis->svga.u32GuestId = u32;
1732	break;
1733
1734	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1735	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1736	pThis->svga.u32PitchLock = u32;
1737	/* Should this also update the FIFO pitch lock? Unclear. */
1738	break;
1739
1740	case SVGA_REG_IRQMASK: /* Interrupt mask */
1741	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1742	pThis->svga.u32IrqMask = u32;
1743
1744	/* Irq pending after the above change? */
1745	if (pThis->svga.u32IrqStatus & u32)
1746	{
1747	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1748	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
1749	}
1750	else
1751	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1752	break;
1753
1754	/* Mouse cursor support */
1755	case SVGA_REG_CURSOR_ID:
1756	case SVGA_REG_CURSOR_X:
1757	case SVGA_REG_CURSOR_Y:
1758	case SVGA_REG_CURSOR_ON:
1759	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1760	break;
1761
1762	/* Legacy multi-monitor support */
1763	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1764	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1765	break;
1766	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1767	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1768	break;
1769	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1770	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1771	break;
1772	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1773	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1774	break;
1775	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1776	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1777	break;
1778	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1779	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1780	break;
1781	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1782	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1783	break;
1784	#ifdef VBOX_WITH_VMSVGA3D
1785	/* See "Guest memory regions" below. */
1786	case SVGA_REG_GMR_ID:
1787	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1788	pThis->svga.u32CurrentGMRId = u32;
1789	break;
1790
1791	case SVGA_REG_GMR_DESCRIPTOR:
1792	# ifndef IN_RING3
1793	rc = VINF_IOM_R3_IOPORT_WRITE;
1794	break;
1795	# else /* IN_RING3 */
1796	{
1797	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1798
1799	/* Validate current GMR id. */
1800	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1801	AssertBreak(idGMR < pThis->svga.cGMR);
1802	RT_UNTRUSTED_VALIDATED_FENCE();
1803
1804	/* Free the old GMR if present. */
1805	vmsvgaR3GmrFree(pThisCC, idGMR);
1806
1807	/* Just undefine the GMR? */
1808	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1809	if (GCPhys == 0)
1810	{
1811	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1812	break;
1813	}
1814
1815
1816	/* Never cross a page boundary automatically. */
1817	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1818	uint32_t cPagesTotal = 0;
1819	uint32_t iDesc = 0;
1820	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1821	uint32_t cLoops = 0;
1822	RTGCPHYS GCPhysBase = GCPhys;
1823	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1824	{
1825	/* Read descriptor. */
1826	SVGAGuestMemDescriptor desc;
1827	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
1828	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
1829
1830	if (desc.numPages != 0)
1831	{
1832	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1833	cPagesTotal += desc.numPages;
1834	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1835
1836	if ((iDesc & 15) == 0)
1837	{
1838	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1839	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1840	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1841	}
1842
1843	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1844	paDescs[iDesc++].numPages = desc.numPages;
1845
1846	/* Continue with the next descriptor. */
1847	GCPhys += sizeof(desc);
1848	}
1849	else if (desc.ppn == 0)
1850	break; /* terminator */
1851	else /* Pointer to the next physical page of descriptors. */
1852	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1853
1854	cLoops++;
1855	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1856	}
1857
1858	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1859	if (RT_SUCCESS(rc))
1860	{
1861	/* Commit the GMR. */
1862	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1863	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1864	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1865	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1866	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1867	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1868	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1869	}
1870	else
1871	{
1872	RTMemFree(paDescs);
1873	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1874	}
1875	break;
1876	}
1877	# endif /* IN_RING3 */
1878	#endif // VBOX_WITH_VMSVGA3D
1879
1880	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1881	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1882	if (pThis->svga.fTraces == u32)
1883	break; /* nothing to do */
1884
1885	#ifdef IN_RING3
1886	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
1887	#else
1888	rc = VINF_IOM_R3_IOPORT_WRITE;
1889	#endif
1890	break;
1891
1892	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1893	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1894	break;
1895
1896	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1897	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1898	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1899	break;
1900
1901	case SVGA_REG_FB_START:
1902	case SVGA_REG_MEM_START:
1903	case SVGA_REG_HOST_BITS_PER_PIXEL:
1904	case SVGA_REG_MAX_WIDTH:
1905	case SVGA_REG_MAX_HEIGHT:
1906	case SVGA_REG_VRAM_SIZE:
1907	case SVGA_REG_FB_SIZE:
1908	case SVGA_REG_CAPABILITIES:
1909	case SVGA_REG_MEM_SIZE:
1910	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1911	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1912	case SVGA_REG_BYTES_PER_LINE:
1913	case SVGA_REG_FB_OFFSET:
1914	case SVGA_REG_RED_MASK:
1915	case SVGA_REG_GREEN_MASK:
1916	case SVGA_REG_BLUE_MASK:
1917	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1918	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1919	case SVGA_REG_GMR_MAX_IDS:
1920	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1921	/* Read only - ignore. */
1922	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1923	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1924	break;
1925
1926	default:
1927	{
1928	uint32_t offReg;
1929	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1930	{
1931	RT_UNTRUSTED_VALIDATED_FENCE();
1932	pThis->svga.au32ScratchRegion[offReg] = u32;
1933	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1934	}
1935	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1936	{
1937	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1938	Btw, see rgb_to_pixel32. */
1939	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1940	u32 &= 0xff;
1941	RT_UNTRUSTED_VALIDATED_FENCE();
1942	uint32_t uRgb = pThis->last_palette[offReg / 3];
1943	switch (offReg % 3)
1944	{
1945	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1946	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1947	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1948	}
1949	pThis->last_palette[offReg / 3] = uRgb;
1950	}
1951	else
1952	{
1953	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1954	rc = VINF_IOM_R3_IOPORT_WRITE;
1955	#else
1956	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1957	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1958	#endif
1959	}
1960	break;
1961	}
1962	}
1963	return rc;
1964	}
1965
1966	/**
1967	* @callback_method_impl{FNIOMIOPORTNEWIN}
1968	*/
1969	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
1970	{
1971	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
1972	RT_NOREF_PV(pvUser);
1973
1974	/* Only dword accesses. */
1975	if (cb == 4)
1976	{
1977	switch (offPort)
1978	{
1979	case SVGA_INDEX_PORT:
1980	*pu32 = pThis->svga.u32IndexReg;
1981	break;
1982
1983	case SVGA_VALUE_PORT:
1984	return vmsvgaReadPort(pDevIns, pThis, pu32);
1985
1986	case SVGA_BIOS_PORT:
1987	Log(("Ignoring BIOS port read\n"));
1988	*pu32 = 0;
1989	break;
1990
1991	case SVGA_IRQSTATUS_PORT:
1992	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1993	*pu32 = pThis->svga.u32IrqStatus;
1994	break;
1995
1996	default:
1997	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
1998	*pu32 = UINT32_MAX;
1999	break;
2000	}
2001	}
2002	else
2003	{
2004	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2005	*pu32 = UINT32_MAX;
2006	}
2007	return VINF_SUCCESS;
2008	}
2009
2010	/**
2011	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2012	*/
2013	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2014	{
2015	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2016	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2017	RT_NOREF_PV(pvUser);
2018
2019	/* Only dword accesses. */
2020	if (cb == 4)
2021	switch (offPort)
2022	{
2023	case SVGA_INDEX_PORT:
2024	pThis->svga.u32IndexReg = u32;
2025	break;
2026
2027	case SVGA_VALUE_PORT:
2028	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2029
2030	case SVGA_BIOS_PORT:
2031	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2032	break;
2033
2034	case SVGA_IRQSTATUS_PORT:
2035	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2036	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2037	/* Clear the irq in case all events have been cleared. */
2038	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2039	{
2040	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2041	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2042	}
2043	break;
2044
2045	default:
2046	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2047	break;
2048	}
2049	else
2050	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2051
2052	return VINF_SUCCESS;
2053	}
2054
2055	#ifdef IN_RING3
2056
2057	# ifdef DEBUG_FIFO_ACCESS
2058	/**
2059	* Handle FIFO memory access.
2060	* @returns VBox status code.
2061	* @param pVM VM handle.
2062	* @param pThis The shared VGA/VMSVGA instance data.
2063	* @param GCPhys The access physical address.
2064	* @param fWriteAccess Read or write access
2065	*/
2066	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2067	{
2068	RT_NOREF(pVM);
2069	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2070	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2071
2072	switch (GCPhysOffset >> 2)
2073	{
2074	case SVGA_FIFO_MIN:
2075	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2076	break;
2077	case SVGA_FIFO_MAX:
2078	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2079	break;
2080	case SVGA_FIFO_NEXT_CMD:
2081	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2082	break;
2083	case SVGA_FIFO_STOP:
2084	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2085	break;
2086	case SVGA_FIFO_CAPABILITIES:
2087	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2088	break;
2089	case SVGA_FIFO_FLAGS:
2090	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2091	break;
2092	case SVGA_FIFO_FENCE:
2093	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2094	break;
2095	case SVGA_FIFO_3D_HWVERSION:
2096	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2097	break;
2098	case SVGA_FIFO_PITCHLOCK:
2099	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2100	break;
2101	case SVGA_FIFO_CURSOR_ON:
2102	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2103	break;
2104	case SVGA_FIFO_CURSOR_X:
2105	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2106	break;
2107	case SVGA_FIFO_CURSOR_Y:
2108	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2109	break;
2110	case SVGA_FIFO_CURSOR_COUNT:
2111	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2112	break;
2113	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2114	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2115	break;
2116	case SVGA_FIFO_RESERVED:
2117	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2118	break;
2119	case SVGA_FIFO_CURSOR_SCREEN_ID:
2120	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2121	break;
2122	case SVGA_FIFO_DEAD:
2123	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2124	break;
2125	case SVGA_FIFO_3D_HWVERSION_REVISED:
2126	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2127	break;
2128	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2129	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2130	break;
2131	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2132	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2133	break;
2134	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2135	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2136	break;
2137	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2138	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2139	break;
2140	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2141	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2142	break;
2143	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2144	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2145	break;
2146	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2147	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2148	break;
2149	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2150	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2151	break;
2152	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2153	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2154	break;
2155	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2156	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2157	break;
2158	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2159	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2160	break;
2161	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2162	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2163	break;
2164	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2165	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2166	break;
2167	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2168	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2169	break;
2170	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2171	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2172	break;
2173	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2174	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2175	break;
2176	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2177	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2178	break;
2179	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2180	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2181	break;
2182	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2183	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2184	break;
2185	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2186	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2187	break;
2188	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2189	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2190	break;
2191	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2192	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2193	break;
2194	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2195	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2196	break;
2197	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2198	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2199	break;
2200	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2201	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2202	break;
2203	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2204	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2205	break;
2206	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2207	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2208	break;
2209	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2210	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2211	break;
2212	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2213	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2214	break;
2215	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2216	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2217	break;
2218	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2219	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2220	break;
2221	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2222	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2223	break;
2224	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2225	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2226	break;
2227	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2228	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2229	break;
2230	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2231	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2232	break;
2233	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2234	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2235	break;
2236	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2237	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2238	break;
2239	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2240	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2241	break;
2242	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2243	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2244	break;
2245	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2246	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2247	break;
2248	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2249	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2250	break;
2251	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2252	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2253	break;
2254	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2255	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2256	break;
2257	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2258	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2259	break;
2260	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2261	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2262	break;
2263	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2264	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2265	break;
2266	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2267	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2268	break;
2269	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2270	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2271	break;
2272	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2273	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2274	break;
2275	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2276	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2277	break;
2278	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2279	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2280	break;
2281	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2282	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2283	break;
2284	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2285	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2286	break;
2287	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2288	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2289	break;
2290	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2291	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2292	break;
2293	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2294	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2295	break;
2296	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2297	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2298	break;
2299	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2300	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2301	break;
2302	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2303	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2304	break;
2305	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2306	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2307	break;
2308	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2309	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2310	break;
2311	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2312	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2313	break;
2314	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2315	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2316	break;
2317	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2318	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2319	break;
2320	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2321	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2322	break;
2323	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2324	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2325	break;
2326	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2327	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2328	break;
2329	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2330	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2331	break;
2332	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2333	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2334	break;
2335	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2336	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2337	break;
2338	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2339	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2340	break;
2341	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2342	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2343	break;
2344	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2345	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2346	break;
2347	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2348	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2349	break;
2350	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2351	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2352	break;
2353	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2354	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2355	break;
2356	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2357	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2358	break;
2359	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2360	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2361	break;
2362	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2363	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2364	break;
2365	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2366	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2367	break;
2368	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2369	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2370	break;
2371	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2372	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2373	break;
2374	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2375	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2376	break;
2377	case SVGA_FIFO_3D_CAPS_LAST:
2378	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2379	break;
2380	case SVGA_FIFO_GUEST_3D_HWVERSION:
2381	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2382	break;
2383	case SVGA_FIFO_FENCE_GOAL:
2384	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2385	break;
2386	case SVGA_FIFO_BUSY:
2387	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2388	break;
2389	default:
2390	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2391	break;
2392	}
2393
2394	return VINF_EM_RAW_EMULATE_INSTR;
2395	}
2396	# endif /* DEBUG_FIFO_ACCESS */
2397
2398	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2399	/**
2400	* HC access handler for the FIFO.
2401	*
2402	* @returns VINF_SUCCESS if the handler have carried out the operation.
2403	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2404	* @param pVM VM Handle.
2405	* @param pVCpu The cross context CPU structure for the calling EMT.
2406	* @param GCPhys The physical address the guest is writing to.
2407	* @param pvPhys The HC mapping of that address.
2408	* @param pvBuf What the guest is reading/writing.
2409	* @param cbBuf How much it's reading/writing.
2410	* @param enmAccessType The access type.
2411	* @param enmOrigin Who is making the access.
2412	* @param pvUser User argument.
2413	*/
2414	static DECLCALLBACK(VBOXSTRICTRC)
2415	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2416	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2417	{
2418	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2419	PVGASTATE pThis = (PVGASTATE)pvUser;
2420	AssertPtr(pThis);
2421
2422	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2423	/*
2424	* Wake up the FIFO thread as it might have work to do now.
2425	*/
2426	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2427	AssertLogRelRC(rc);
2428	# endif
2429
2430	# ifdef DEBUG_FIFO_ACCESS
2431	/*
2432	* When in debug-fifo-access mode, we do not disable the access handler,
2433	* but leave it on as we wish to catch all access.
2434	*/
2435	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2436	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2437	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2438	/*
2439	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2440	*/
2441	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2442	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2443	# endif
2444	if (RT_SUCCESS(rc))
2445	return VINF_PGM_HANDLER_DO_DEFAULT;
2446	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2447	return rc;
2448	}
2449	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2450
2451	#endif /* IN_RING3 */
2452
2453	#ifdef DEBUG_GMR_ACCESS
2454	# ifdef IN_RING3
2455
2456	/**
2457	* HC access handler for the FIFO.
2458	*
2459	* @returns VINF_SUCCESS if the handler have carried out the operation.
2460	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2461	* @param pVM VM Handle.
2462	* @param pVCpu The cross context CPU structure for the calling EMT.
2463	* @param GCPhys The physical address the guest is writing to.
2464	* @param pvPhys The HC mapping of that address.
2465	* @param pvBuf What the guest is reading/writing.
2466	* @param cbBuf How much it's reading/writing.
2467	* @param enmAccessType The access type.
2468	* @param enmOrigin Who is making the access.
2469	* @param pvUser User argument.
2470	*/
2471	static DECLCALLBACK(VBOXSTRICTRC)
2472	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2473	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2474	{
2475	PVGASTATE pThis = (PVGASTATE)pvUser;
2476	Assert(pThis);
2477	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2478	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2479
2480	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2481
2482	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2483	{
2484	PGMR pGMR = &pSVGAState->paGMR[i];
2485
2486	if (pGMR->numDescriptors)
2487	{
2488	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2489	{
2490	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2491	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2492	{
2493	/*
2494	* Turn off the write handler for this particular page and make it R/W.
2495	* Then return telling the caller to restart the guest instruction.
2496	*/
2497	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2498	AssertRC(rc);
2499	return VINF_PGM_HANDLER_DO_DEFAULT;
2500	}
2501	}
2502	}
2503	}
2504
2505	return VINF_PGM_HANDLER_DO_DEFAULT;
2506	}
2507
2508	/** Callback handler for VMR3ReqCallWaitU */
2509	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2510	{
2511	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2512	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2513	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2514	int rc;
2515
2516	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2517	{
2518	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2519	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2520	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2521	AssertRC(rc);
2522	}
2523	return VINF_SUCCESS;
2524	}
2525
2526	/** Callback handler for VMR3ReqCallWaitU */
2527	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2528	{
2529	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2530	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2531	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2532
2533	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2534	{
2535	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2536	AssertRC(rc);
2537	}
2538	return VINF_SUCCESS;
2539	}
2540
2541	/** Callback handler for VMR3ReqCallWaitU */
2542	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2543	{
2544	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2545
2546	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2547	{
2548	PGMR pGMR = &pSVGAState->paGMR[i];
2549
2550	if (pGMR->numDescriptors)
2551	{
2552	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2553	{
2554	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2555	AssertRC(rc);
2556	}
2557	}
2558	}
2559	return VINF_SUCCESS;
2560	}
2561
2562	# endif /* IN_RING3 */
2563	#endif /* DEBUG_GMR_ACCESS */
2564
2565	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2566
2567	#ifdef IN_RING3
2568
2569
2570	/**
2571	* Common worker for changing the pointer shape.
2572	*
2573	* @param pThisCC The VGA/VMSVGA state for ring-3.
2574	* @param pSVGAState The VMSVGA ring-3 instance data.
2575	* @param fAlpha Whether there is alpha or not.
2576	* @param xHot Hotspot x coordinate.
2577	* @param yHot Hotspot y coordinate.
2578	* @param cx Width.
2579	* @param cy Height.
2580	* @param pbData Heap copy of the cursor data. Consumed.
2581	* @param cbData The size of the data.
2582	*/
2583	static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2584	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2585	{
2586	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2587	# ifdef LOG_ENABLED
2588	if (LogIs2Enabled())
2589	{
2590	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2591	if (!fAlpha)
2592	{
2593	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2594	for (uint32_t y = 0; y < cy; y++)
2595	{
2596	Log2(("%3u:", y));
2597	uint8_t const pbLine = &pbData[y cbAndLine];
2598	for (uint32_t x = 0; x < cx; x += 8)
2599	{
2600	uint8_t b = pbLine[x / 8];
2601	char szByte[12];
2602	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2603	szByte[1] = b & 0x40 ? '*' : ' ';
2604	szByte[2] = b & 0x20 ? '*' : ' ';
2605	szByte[3] = b & 0x10 ? '*' : ' ';
2606	szByte[4] = b & 0x08 ? '*' : ' ';
2607	szByte[5] = b & 0x04 ? '*' : ' ';
2608	szByte[6] = b & 0x02 ? '*' : ' ';
2609	szByte[7] = b & 0x01 ? '*' : ' ';
2610	szByte[8] = '\0';
2611	Log2(("%s", szByte));
2612	}
2613	Log2(("\n"));
2614	}
2615	}
2616
2617	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2618	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2619	for (uint32_t y = 0; y < cy; y++)
2620	{
2621	Log2(("%3u:", y));
2622	uint32_t const pu32Line = &pu32Xor[y cx];
2623	for (uint32_t x = 0; x < cx; x++)
2624	Log2((" %08x", pu32Line[x]));
2625	Log2(("\n"));
2626	}
2627	}
2628	# endif
2629
2630	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2631	AssertRC(rc);
2632
2633	if (pSVGAState->Cursor.fActive)
2634	RTMemFree(pSVGAState->Cursor.pData);
2635
2636	pSVGAState->Cursor.fActive = true;
2637	pSVGAState->Cursor.xHotspot = xHot;
2638	pSVGAState->Cursor.yHotspot = yHot;
2639	pSVGAState->Cursor.width = cx;
2640	pSVGAState->Cursor.height = cy;
2641	pSVGAState->Cursor.cbData = cbData;
2642	pSVGAState->Cursor.pData = pbData;
2643	}
2644
2645
2646	/**
2647	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2648	*
2649	* @param pThis The shared VGA/VMSVGA state.
2650	* @param pThisCC The VGA/VMSVGA state for ring-3.
2651	* @param pSVGAState The VMSVGA ring-3 instance data.
2652	* @param pCursor The cursor.
2653	* @param pbSrcAndMask The AND mask.
2654	* @param cbSrcAndLine The scanline length of the AND mask.
2655	* @param pbSrcXorMask The XOR mask.
2656	* @param cbSrcXorLine The scanline length of the XOR mask.
2657	*/
2658	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState,
2659	SVGAFifoCmdDefineCursor const *pCursor,
2660	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2661	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2662	{
2663	uint32_t const cx = pCursor->width;
2664	uint32_t const cy = pCursor->height;
2665
2666	/*
2667	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2668	* The AND data uses 8-bit aligned scanlines.
2669	* The XOR data must be starting on a 32-bit boundrary.
2670	*/
2671	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2672	uint32_t cbDstAndMask = cbDstAndLine * cy;
2673	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2674	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2675
2676	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2677	AssertReturnVoid(pbCopy);
2678
2679	/* Convert the AND mask. */
2680	uint8_t *pbDst = pbCopy;
2681	uint8_t const *pbSrc = pbSrcAndMask;
2682	switch (pCursor->andMaskDepth)
2683	{
2684	case 1:
2685	if (cbSrcAndLine == cbDstAndLine)
2686	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2687	else
2688	{
2689	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2690	for (uint32_t y = 0; y < cy; y++)
2691	{
2692	memcpy(pbDst, pbSrc, cbDstAndLine);
2693	pbDst += cbDstAndLine;
2694	pbSrc += cbSrcAndLine;
2695	}
2696	}
2697	break;
2698	/* Should take the XOR mask into account for the multi-bit AND mask. */
2699	case 8:
2700	for (uint32_t y = 0; y < cy; y++)
2701	{
2702	for (uint32_t x = 0; x < cx; )
2703	{
2704	uint8_t bDst = 0;
2705	uint8_t fBit = 1;
2706	do
2707	{
2708	uintptr_t const idxPal = pbSrc[x] * 3;
2709	if ((( pThis->last_palette[idxPal]
2710	\| (pThis->last_palette[idxPal] >> 8)
2711	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2712	bDst \|= fBit;
2713	fBit <<= 1;
2714	x++;
2715	} while (x < cx && (x & 7));
2716	pbDst[(x - 1) / 8] = bDst;
2717	}
2718	pbDst += cbDstAndLine;
2719	pbSrc += cbSrcAndLine;
2720	}
2721	break;
2722	case 15:
2723	for (uint32_t y = 0; y < cy; y++)
2724	{
2725	for (uint32_t x = 0; x < cx; )
2726	{
2727	uint8_t bDst = 0;
2728	uint8_t fBit = 1;
2729	do
2730	{
2731	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2732	bDst \|= fBit;
2733	fBit <<= 1;
2734	x++;
2735	} while (x < cx && (x & 7));
2736	pbDst[(x - 1) / 8] = bDst;
2737	}
2738	pbDst += cbDstAndLine;
2739	pbSrc += cbSrcAndLine;
2740	}
2741	break;
2742	case 16:
2743	for (uint32_t y = 0; y < cy; y++)
2744	{
2745	for (uint32_t x = 0; x < cx; )
2746	{
2747	uint8_t bDst = 0;
2748	uint8_t fBit = 1;
2749	do
2750	{
2751	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2752	bDst \|= fBit;
2753	fBit <<= 1;
2754	x++;
2755	} while (x < cx && (x & 7));
2756	pbDst[(x - 1) / 8] = bDst;
2757	}
2758	pbDst += cbDstAndLine;
2759	pbSrc += cbSrcAndLine;
2760	}
2761	break;
2762	case 24:
2763	for (uint32_t y = 0; y < cy; y++)
2764	{
2765	for (uint32_t x = 0; x < cx; )
2766	{
2767	uint8_t bDst = 0;
2768	uint8_t fBit = 1;
2769	do
2770	{
2771	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2772	bDst \|= fBit;
2773	fBit <<= 1;
2774	x++;
2775	} while (x < cx && (x & 7));
2776	pbDst[(x - 1) / 8] = bDst;
2777	}
2778	pbDst += cbDstAndLine;
2779	pbSrc += cbSrcAndLine;
2780	}
2781	break;
2782	case 32:
2783	for (uint32_t y = 0; y < cy; y++)
2784	{
2785	for (uint32_t x = 0; x < cx; )
2786	{
2787	uint8_t bDst = 0;
2788	uint8_t fBit = 1;
2789	do
2790	{
2791	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2792	bDst \|= fBit;
2793	fBit <<= 1;
2794	x++;
2795	} while (x < cx && (x & 7));
2796	pbDst[(x - 1) / 8] = bDst;
2797	}
2798	pbDst += cbDstAndLine;
2799	pbSrc += cbSrcAndLine;
2800	}
2801	break;
2802	default:
2803	RTMemFree(pbCopy);
2804	AssertFailedReturnVoid();
2805	}
2806
2807	/* Convert the XOR mask. */
2808	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2809	pbSrc = pbSrcXorMask;
2810	switch (pCursor->xorMaskDepth)
2811	{
2812	case 1:
2813	for (uint32_t y = 0; y < cy; y++)
2814	{
2815	for (uint32_t x = 0; x < cx; )
2816	{
2817	/* most significant bit is the left most one. */
2818	uint8_t bSrc = pbSrc[x / 8];
2819	do
2820	{
2821	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2822	bSrc <<= 1;
2823	x++;
2824	} while ((x & 7) && x < cx);
2825	}
2826	pbSrc += cbSrcXorLine;
2827	}
2828	break;
2829	case 8:
2830	for (uint32_t y = 0; y < cy; y++)
2831	{
2832	for (uint32_t x = 0; x < cx; x++)
2833	{
2834	uint32_t u = pThis->last_palette[pbSrc[x]];
2835	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2836	}
2837	pbSrc += cbSrcXorLine;
2838	}
2839	break;
2840	case 15: /* Src: RGB-5-5-5 */
2841	for (uint32_t y = 0; y < cy; y++)
2842	{
2843	for (uint32_t x = 0; x < cx; x++)
2844	{
2845	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2846	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2847	((uValue >> 5) & 0x1f) << 3,
2848	((uValue >> 10) & 0x1f) << 3, 0);
2849	}
2850	pbSrc += cbSrcXorLine;
2851	}
2852	break;
2853	case 16: /* Src: RGB-5-6-5 */
2854	for (uint32_t y = 0; y < cy; y++)
2855	{
2856	for (uint32_t x = 0; x < cx; x++)
2857	{
2858	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2859	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2860	((uValue >> 5) & 0x3f) << 2,
2861	((uValue >> 11) & 0x1f) << 3, 0);
2862	}
2863	pbSrc += cbSrcXorLine;
2864	}
2865	break;
2866	case 24:
2867	for (uint32_t y = 0; y < cy; y++)
2868	{
2869	for (uint32_t x = 0; x < cx; x++)
2870	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2871	pbSrc += cbSrcXorLine;
2872	}
2873	break;
2874	case 32:
2875	for (uint32_t y = 0; y < cy; y++)
2876	{
2877	for (uint32_t x = 0; x < cx; x++)
2878	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2879	pbSrc += cbSrcXorLine;
2880	}
2881	break;
2882	default:
2883	RTMemFree(pbCopy);
2884	AssertFailedReturnVoid();
2885	}
2886
2887	/*
2888	* Pass it to the frontend/whatever.
2889	*/
2890	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2891	}
2892
2893
2894	/**
2895	* Worker for vmsvgaR3FifoThread that handles an external command.
2896	*
2897	* @param pDevIns The device instance.
2898	* @param pThis The shared VGA/VMSVGA instance data.
2899	* @param pThisCC The VGA/VMSVGA state for ring-3.
2900	*/
2901	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
2902	{
2903	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2904	switch (pThis->svga.u8FIFOExtCommand)
2905	{
2906	case VMSVGA_FIFO_EXTCMD_RESET:
2907	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
2908	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
2909	# ifdef VBOX_WITH_VMSVGA3D
2910	if (pThis->svga.f3DEnabled)
2911	{
2912	/* The 3d subsystem must be reset from the fifo thread. */
2913	vmsvga3dReset(pThisCC);
2914	}
2915	# endif
2916	break;
2917
2918	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2919	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
2920	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
2921	# ifdef VBOX_WITH_VMSVGA3D
2922	if (pThis->svga.f3DEnabled)
2923	{
2924	/* The 3d subsystem must be shut down from the fifo thread. */
2925	vmsvga3dTerminate(pThisCC);
2926	}
2927	# endif
2928	break;
2929
2930	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2931	{
2932	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2933	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
2934	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2935	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
2936	# ifdef VBOX_WITH_VMSVGA3D
2937	if (pThis->svga.f3DEnabled)
2938	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
2939	# endif
2940	break;
2941	}
2942
2943	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2944	{
2945	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2946	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
2947	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2948	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2949	# ifdef VBOX_WITH_VMSVGA3D
2950	if (pThis->svga.f3DEnabled)
2951	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2952	# endif
2953	break;
2954	}
2955
2956	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2957	{
2958	# ifdef VBOX_WITH_VMSVGA3D
2959	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
2960	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2961	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
2962	# endif
2963	break;
2964	}
2965
2966
2967	default:
2968	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
2969	break;
2970	}
2971
2972	/*
2973	* Signal the end of the external command.
2974	*/
2975	pThisCC->svga.pvFIFOExtCmdParam = NULL;
2976	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2977	ASMMemoryFence(); /* paranoia^2 */
2978	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
2979	AssertLogRelRC(rc);
2980	}
2981
2982	/**
2983	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2984	* doing a job on the FIFO thread (even when it's officially suspended).
2985	*
2986	* @returns VBox status code (fully asserted).
2987	* @param pDevIns The device instance.
2988	* @param pThis The shared VGA/VMSVGA instance data.
2989	* @param pThisCC The VGA/VMSVGA state for ring-3.
2990	* @param uExtCmd The command to execute on the FIFO thread.
2991	* @param pvParam Pointer to command parameters.
2992	* @param cMsWait The time to wait for the command, given in
2993	* milliseconds.
2994	*/
2995	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
2996	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2997	{
2998	Assert(cMsWait >= RT_MS_1SEC * 5);
2999	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3000	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3001
3002	int rc;
3003	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
3004	PDMTHREADSTATE enmState = pThread->enmState;
3005	if (enmState == PDMTHREADSTATE_SUSPENDED)
3006	{
3007	/*
3008	* The thread is suspended, we have to temporarily wake it up so it can
3009	* perform the task.
3010	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3011	*/
3012	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3013	/* Post the request. */
3014	pThis->svga.fFifoExtCommandWakeup = true;
3015	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3016	pThis->svga.u8FIFOExtCommand = uExtCmd;
3017	ASMMemoryFence(); /* paranoia^3 */
3018
3019	/* Resume the thread. */
3020	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3021	AssertLogRelRC(rc);
3022	if (RT_SUCCESS(rc))
3023	{
3024	/* Wait. Take care in case the semaphore was already posted (same as below). */
3025	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3026	if ( rc == VINF_SUCCESS
3027	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3028	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3029	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3030	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3031
3032	/* suspend the thread */
3033	pThis->svga.fFifoExtCommandWakeup = false;
3034	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3035	AssertLogRelRC(rc2);
3036	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3037	rc = rc2;
3038	}
3039	pThis->svga.fFifoExtCommandWakeup = false;
3040	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3041	}
3042	else if (enmState == PDMTHREADSTATE_RUNNING)
3043	{
3044	/*
3045	* The thread is running, should only happen during reset and vmsvga3dsfc.
3046	* We ASSUME not racing code here, both wrt thread state and ext commands.
3047	*/
3048	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3049	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3050
3051	/* Post the request. */
3052	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3053	pThis->svga.u8FIFOExtCommand = uExtCmd;
3054	ASMMemoryFence(); /* paranoia^2 */
3055	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3056	AssertLogRelRC(rc);
3057
3058	/* Wait. Take care in case the semaphore was already posted (same as above). */
3059	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3060	if ( rc == VINF_SUCCESS
3061	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3062	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3063	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3064	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3065
3066	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3067	}
3068	else
3069	{
3070	/*
3071	* Something is wrong with the thread!
3072	*/
3073	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3074	rc = VERR_INVALID_STATE;
3075	}
3076	return rc;
3077	}
3078
3079
3080	/**
3081	* Marks the FIFO non-busy, notifying any waiting EMTs.
3082	*
3083	* @param pDevIns The device instance.
3084	* @param pThis The shared VGA/VMSVGA instance data.
3085	* @param pThisCC The VGA/VMSVGA state for ring-3.
3086	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3087	* @param offFifoMin The start byte offset of the command FIFO.
3088	*/
3089	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3090	{
3091	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3092	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3093	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
3094
3095	/* Wake up any waiting EMTs. */
3096	if (pSVGAState->cBusyDelayedEmts > 0)
3097	{
3098	# ifdef VMSVGA_USE_EMT_HALT_CODE
3099	PVM pVM = PDMDevHlpGetVM(pDevIns);
3100	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3101	if (idCpu != NIL_VMCPUID)
3102	{
3103	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3104	while (idCpu-- > 0)
3105	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3106	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3107	}
3108	# else
3109	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3110	AssertRC(rc2);
3111	# endif
3112	}
3113	}
3114
3115	/**
3116	* Reads (more) payload into the command buffer.
3117	*
3118	* @returns pbBounceBuf on success
3119	* @retval (void *)1 if the thread was requested to stop.
3120	* @retval NULL on FIFO error.
3121	*
3122	* @param cbPayloadReq The number of bytes of payload requested.
3123	* @param pFIFO The FIFO.
3124	* @param offCurrentCmd The FIFO byte offset of the current command.
3125	* @param offFifoMin The start byte offset of the command FIFO.
3126	* @param offFifoMax The end byte offset of the command FIFO.
3127	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3128	* always sufficient size.
3129	* @param pcbAlreadyRead How much payload we've already read into the bounce
3130	* buffer. (We will NEVER re-read anything.)
3131	* @param pThread The calling PDM thread handle.
3132	* @param pThis The shared VGA/VMSVGA instance data.
3133	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3134	* statistics collection.
3135	* @param pDevIns The device instance.
3136	*/
3137	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3138	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3139	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3140	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
3141	{
3142	Assert(pbBounceBuf);
3143	Assert(pcbAlreadyRead);
3144	Assert(offFifoMin < offFifoMax);
3145	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3146	Assert(offFifoMax <= pThis->svga.cbFIFO);
3147
3148	/*
3149	* Check if the requested payload size has already been satisfied .
3150	* .
3151	* When called to read more, the caller is responsible for making sure the .
3152	* new command size (cbRequsted) never is smaller than what has already .
3153	* been read.
3154	*/
3155	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3156	if (cbPayloadReq <= cbAlreadyRead)
3157	{
3158	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3159	return pbBounceBuf;
3160	}
3161
3162	/*
3163	* Commands bigger than the fifo buffer are invalid.
3164	*/
3165	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3166	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3167	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3168	NULL);
3169
3170	/*
3171	* Move offCurrentCmd past the command dword.
3172	*/
3173	offCurrentCmd += sizeof(uint32_t);
3174	if (offCurrentCmd >= offFifoMax)
3175	offCurrentCmd = offFifoMin;
3176
3177	/*
3178	* Do we have sufficient payload data available already?
3179	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3180	*/
3181	uint32_t cbAfter, cbBefore;
3182	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3183	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3184	if (offNextCmd >= offCurrentCmd)
3185	{
3186	if (RT_LIKELY(offNextCmd < offFifoMax))
3187	cbAfter = offNextCmd - offCurrentCmd;
3188	else
3189	{
3190	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3191	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3192	offNextCmd, offFifoMin, offFifoMax));
3193	cbAfter = offFifoMax - offCurrentCmd;
3194	}
3195	cbBefore = 0;
3196	}
3197	else
3198	{
3199	cbAfter = offFifoMax - offCurrentCmd;
3200	if (offNextCmd >= offFifoMin)
3201	cbBefore = offNextCmd - offFifoMin;
3202	else
3203	{
3204	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3205	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3206	offNextCmd, offFifoMin, offFifoMax));
3207	cbBefore = 0;
3208	}
3209	}
3210	if (cbAfter + cbBefore < cbPayloadReq)
3211	{
3212	/*
3213	* Insufficient, must wait for it to arrive.
3214	*/
3215	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3216	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3217	for (uint32_t i = 0;; i++)
3218	{
3219	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3220	{
3221	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3222	return (void *)(uintptr_t)1;
3223	}
3224	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3225	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3226
3227	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
3228
3229	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3230	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3231	if (offNextCmd >= offCurrentCmd)
3232	{
3233	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3234	cbBefore = 0;
3235	}
3236	else
3237	{
3238	cbAfter = offFifoMax - offCurrentCmd;
3239	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3240	}
3241
3242	if (cbAfter + cbBefore >= cbPayloadReq)
3243	break;
3244	}
3245	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3246	}
3247
3248	/*
3249	* Copy out the memory and update what pcbAlreadyRead points to.
3250	*/
3251	if (cbAfter >= cbPayloadReq)
3252	memcpy(pbBounceBuf + cbAlreadyRead,
3253	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3254	cbPayloadReq - cbAlreadyRead);
3255	else
3256	{
3257	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3258	if (cbAlreadyRead < cbAfter)
3259	{
3260	memcpy(pbBounceBuf + cbAlreadyRead,
3261	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3262	cbAfter - cbAlreadyRead);
3263	cbAlreadyRead = cbAfter;
3264	}
3265	memcpy(pbBounceBuf + cbAlreadyRead,
3266	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3267	cbPayloadReq - cbAlreadyRead);
3268	}
3269	*pcbAlreadyRead = cbPayloadReq;
3270	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3271	return pbBounceBuf;
3272	}
3273
3274
3275	/**
3276	* Sends cursor position and visibility information from the FIFO to the front-end.
3277	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3278	*/
3279	static uint32_t
3280	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3281	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3282	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3283	{
3284	/*
3285	* Check if the cursor update counter has changed and try get a stable
3286	* set of values if it has. This is race-prone, especially consindering
3287	* the screen ID, but little we can do about that.
3288	*/
3289	uint32_t x, y, fVisible, idScreen;
3290	for (uint32_t i = 0; ; i++)
3291	{
3292	x = pFIFO[SVGA_FIFO_CURSOR_X];
3293	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3294	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3295	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3296	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3297	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3298	\|\| i > 3)
3299	break;
3300	if (i == 0)
3301	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3302	ASMNopPause();
3303	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3304	}
3305
3306	/*
3307	* Check if anything has changed, as calling into pDrv is not light-weight.
3308	*/
3309	if ( *pxLast == x
3310	&& *pyLast == y
3311	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3312	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3313	else
3314	{
3315	/*
3316	* Detected changes.
3317	*
3318	* We handle global, not per-screen visibility information by sending
3319	* pfnVBVAMousePointerShape without shape data.
3320	*/
3321	*pxLast = x;
3322	*pyLast = y;
3323	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3324	if (idScreen != SVGA_ID_INVALID)
3325	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3326	else if (*pfLastVisible != fVisible)
3327	{
3328	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3329	*pfLastVisible = fVisible;
3330	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3331	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3332	}
3333	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
3334	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3335	}
3336
3337	/*
3338	* Update done. Signal this to the guest.
3339	*/
3340	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3341
3342	return uCursorUpdateCount;
3343	}
3344
3345
3346	/**
3347	* Checks if there is work to be done, either cursor updating or FIFO commands.
3348	*
3349	* @returns true if pending work, false if not.
3350	* @param pFIFO The FIFO to examine.
3351	* @param uLastCursorCount The last cursor update counter value.
3352	*/
3353	DECLINLINE(bool) vmsvgaR3FifoHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3354	{
3355	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3356	return true;
3357
3358	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3359	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3360	return true;
3361
3362	return false;
3363	}
3364
3365
3366	/**
3367	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3368	*
3369	* @param pDevIns The device instance.
3370	* @param pThis The shared VGA/VMSVGA instance data.
3371	* @param pThisCC The VGA/VMSVGA state for ring-3.
3372	*/
3373	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3374	{
3375	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3376	to recheck it before doing the signalling. */
3377	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3378	AssertReturnVoid(pFIFO);
3379	if ( vmsvgaR3FifoHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3380	&& pThis->svga.fFIFOThreadSleeping)
3381	{
3382	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3383	AssertRC(rc);
3384	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3385	}
3386	}
3387
3388
3389	/*
3390	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
3391	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
3392	*/
3393	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3394	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
3395	*
3396	* Will break out of the switch on failure.
3397	* Will restart and quit the loop if the thread was requested to stop.
3398	*
3399	* @param a_PtrVar Request variable pointer.
3400	* @param a_Type Request typedef (not pointer) for casting.
3401	* @param a_cbPayloadReq How much payload to fetch.
3402	* @remarks Accesses a bunch of variables in the current scope!
3403	*/
3404	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3405	if (1) { \
3406	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3407	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
3408	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3409	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3410	} else do {} while (0)
3411	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3412	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
3413	* buffer after figuring out the actual command size.
3414	*
3415	* Will break out of the switch on failure.
3416	*
3417	* @param a_PtrVar Request variable pointer.
3418	* @param a_Type Request typedef (not pointer) for casting.
3419	* @param a_cbPayloadReq How much payload to fetch.
3420	* @remarks Accesses a bunch of variables in the current scope!
3421	*/
3422	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3423	if (1) { \
3424	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3425	} else do {} while (0)
3426
3427	/**
3428	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
3429	*/
3430	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3431	{
3432	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3433	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3434	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3435	int rc;
3436
3437	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3438	return VINF_SUCCESS;
3439
3440	/*
3441	* Special mode where we only execute an external command and the go back
3442	* to being suspended. Currently, all ext cmds ends up here, with the reset
3443	* one also being eligble for runtime execution further down as well.
3444	*/
3445	if (pThis->svga.fFifoExtCommandWakeup)
3446	{
3447	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3448	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3449	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3450	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
3451	else
3452	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3453	return VINF_SUCCESS;
3454	}
3455
3456
3457	/*
3458	* Signal the semaphore to make sure we don't wait for 250ms after a
3459	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
3460	*/
3461	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3462
3463	/*
3464	* Allocate a bounce buffer for command we get from the FIFO.
3465	* (All code must return via the end of the function to free this buffer.)
3466	*/
3467	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3468	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3469
3470	/*
3471	* Polling/sleep interval config.
3472	*
3473	* We wait for an a short interval if the guest has recently given us work
3474	* to do, but the interval increases the longer we're kept idle. Once we've
3475	* reached the refresh timer interval, we'll switch to extended waits,
3476	* depending on it or the guest to kick us into action when needed.
3477	*
3478	* Should the refresh time go fishing, we'll just continue increasing the
3479	* sleep length till we reaches the 250 ms max after about 16 seconds.
3480	*/
3481	RTMSINTERVAL const cMsMinSleep = 16;
3482	RTMSINTERVAL const cMsIncSleep = 2;
3483	RTMSINTERVAL const cMsMaxSleep = 250;
3484	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3485	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3486
3487	/*
3488	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3489	*
3490	* Initialize with values that will detect an update from the guest.
3491	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3492	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3493	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3494	*/
3495	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3496	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3497	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3498	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3499	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3500
3501	/*
3502	* The FIFO loop.
3503	*/
3504	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
3505	bool fBadOrDisabledFifo = false;
3506	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3507	{
3508	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3509	/*
3510	* Should service the run loop every so often.
3511	*/
3512	if (pThis->svga.f3DEnabled)
3513	vmsvga3dCocoaServiceRunLoop();
3514	# endif
3515
3516	/*
3517	* Unless there's already work pending, go to sleep for a short while.
3518	* (See polling/sleep interval config above.)
3519	*/
3520	if ( fBadOrDisabledFifo
3521	\|\| !vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3522	{
3523	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3524	Assert(pThis->cMilliesRefreshInterval > 0);
3525	if (cMsSleep < pThis->cMilliesRefreshInterval)
3526	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
3527	else
3528	{
3529	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3530	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3531	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3532	# endif
3533	if ( !fBadOrDisabledFifo
3534	&& vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3535	rc = VINF_SUCCESS;
3536	else
3537	{
3538	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3539	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
3540	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3541	}
3542	}
3543	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3544	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3545	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3546	{
3547	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
3548	break;
3549	}
3550	}
3551	else
3552	rc = VINF_SUCCESS;
3553	fBadOrDisabledFifo = false;
3554	if (rc == VERR_TIMEOUT)
3555	{
3556	if (!vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3557	{
3558	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3559	continue;
3560	}
3561	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3562
3563	Log(("vmsvgaR3FifoLoop: timeout\n"));
3564	}
3565	else if (vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3566	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3567	cMsSleep = cMsMinSleep;
3568
3569	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3570	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3571	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3572
3573	/*
3574	* Handle external commands (currently only reset).
3575	*/
3576	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3577	{
3578	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3579	continue;
3580	}
3581
3582	/*
3583	* The device must be enabled and configured.
3584	*/
3585	if ( !pThis->svga.fEnabled
3586	\|\| !pThis->svga.fConfigured)
3587	{
3588	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3589	fBadOrDisabledFifo = true;
3590	cMsSleep = cMsMaxSleep; /* cheat */
3591	continue;
3592	}
3593
3594	/*
3595	* Get and check the min/max values. We ASSUME that they will remain
3596	* unchanged while we process requests. A further ASSUMPTION is that
3597	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3598	* we don't read it back while in the loop.
3599	*/
3600	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3601	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3602	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3603	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3604	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3605	\|\| offFifoMax <= offFifoMin
3606	\|\| offFifoMax > pThis->svga.cbFIFO
3607	\|\| (offFifoMax & 3) != 0
3608	\|\| (offFifoMin & 3) != 0
3609	\|\| offCurrentCmd < offFifoMin
3610	\|\| offCurrentCmd > offFifoMax))
3611	{
3612	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3613	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3614	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
3615	fBadOrDisabledFifo = true;
3616	continue;
3617	}
3618	RT_UNTRUSTED_VALIDATED_FENCE();
3619	if (RT_UNLIKELY(offCurrentCmd & 3))
3620	{
3621	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3622	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3623	offCurrentCmd &= ~UINT32_C(3);
3624	}
3625
3626	/*
3627	* Update the cursor position before we start on the FIFO commands.
3628	*/
3629	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3630	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3631	{
3632	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3633	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3634	{ /* halfways likely */ }
3635	else
3636	{
3637	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3638	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3639	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
3640	}
3641	}
3642
3643	/*
3644	* Mark the FIFO as busy.
3645	*/
3646	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3647	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3648	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3649
3650	/*
3651	* Execute all queued FIFO commands.
3652	* Quit if pending external command or changes in the thread state.
3653	*/
3654	bool fDone = false;
3655	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3656	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3657	{
3658	uint32_t cbPayload = 0;
3659	uint32_t u32IrqStatus = 0;
3660
3661	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3662
3663	/* First check any pending actions. */
3664	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3665	{
3666	vmsvgaR3ChangeMode(pThis, pThisCC);
3667	# ifdef VBOX_WITH_VMSVGA3D
3668	if (pThisCC->svga.p3dState != NULL)
3669	vmsvga3dChangeMode(pThisCC);
3670	# endif
3671	}
3672
3673	/* Check for pending external commands (reset). */
3674	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3675	break;
3676
3677	/*
3678	* Process the command.
3679	*/
3680	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3681	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3682	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3683	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
3684	switch (enmCmdId)
3685	{
3686	case SVGA_CMD_INVALID_CMD:
3687	/* Nothing to do. */
3688	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3689	break;
3690
3691	case SVGA_CMD_FENCE:
3692	{
3693	SVGAFifoCmdFence *pCmdFence;
3694	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3695	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3696	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3697	{
3698	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3699	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3700
3701	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3702	{
3703	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
3704	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3705	}
3706	else
3707	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3708	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3709	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3710	{
3711	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3712	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3713	}
3714	}
3715	else
3716	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3717	break;
3718	}
3719	case SVGA_CMD_UPDATE:
3720	case SVGA_CMD_UPDATE_VERBOSE:
3721	{
3722	SVGAFifoCmdUpdate *pUpdate;
3723	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3724	if (enmCmdId == SVGA_CMD_UPDATE)
3725	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3726	else
3727	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3728	Log(("vmsvgaR3FifoLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3729	/** @todo Multiple screens? */
3730	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
3731	AssertBreak(pScreen);
3732	vmsvgaR3UpdateScreen(pThisCC, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3733	break;
3734	}
3735
3736	case SVGA_CMD_DEFINE_CURSOR:
3737	{
3738	/* Followed by bitmap data. */
3739	SVGAFifoCmdDefineCursor *pCursor;
3740	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3741	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3742
3743	Log(("vmsvgaR3FifoLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3744	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3745	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3746	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3747	AssertBreak(pCursor->andMaskDepth <= 32);
3748	AssertBreak(pCursor->xorMaskDepth <= 32);
3749	RT_UNTRUSTED_VALIDATED_FENCE();
3750
3751	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3752	uint32_t cbAndMask = cbAndLine * pCursor->height;
3753	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3754	uint32_t cbXorMask = cbXorLine * pCursor->height;
3755	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3756
3757	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3758	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3759	break;
3760	}
3761
3762	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3763	{
3764	/* Followed by bitmap data. */
3765	uint32_t cbCursorShape, cbAndMask;
3766	uint8_t *pCursorCopy;
3767	uint32_t cbCmd;
3768
3769	SVGAFifoCmdDefineAlphaCursor *pCursor;
3770	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3771	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3772
3773	Log(("vmsvgaR3FifoLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3774
3775	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3776	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3777	RT_UNTRUSTED_VALIDATED_FENCE();
3778
3779	/* Refetch the bitmap data as well. */
3780	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3781	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3782	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3783
3784	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3785	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3786	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3787	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3788
3789	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3790	AssertBreak(pCursorCopy);
3791
3792	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3793	memset(pCursorCopy, 0xff, cbAndMask);
3794	/* Colour data */
3795	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3796
3797	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3798	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3799	break;
3800	}
3801
3802	case SVGA_CMD_ESCAPE:
3803	{
3804	/* Followed by nsize bytes of data. */
3805	SVGAFifoCmdEscape *pEscape;
3806	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3807	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3808
3809	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3810	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3811	RT_UNTRUSTED_VALIDATED_FENCE();
3812	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3813	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3814
3815	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3816	{
3817	AssertBreak(pEscape->size >= sizeof(uint32_t));
3818	RT_UNTRUSTED_VALIDATED_FENCE();
3819	uint32_t cmd = (uint32_t )(pEscape + 1);
3820	Log(("vmsvgaR3FifoLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3821
3822	switch (cmd)
3823	{
3824	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3825	{
3826	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3827	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3828	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3829
3830	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3831	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3832	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3833
3834	RT_NOREF_PV(pVideoCmd);
3835	break;
3836
3837	}
3838
3839	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3840	{
3841	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3842	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3843	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3844	RT_NOREF_PV(pVideoCmd);
3845	break;
3846	}
3847
3848	default:
3849	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3850	break;
3851	}
3852	}
3853	else
3854	Log(("vmsvgaR3FifoLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3855
3856	break;
3857	}
3858	# ifdef VBOX_WITH_VMSVGA3D
3859	case SVGA_CMD_DEFINE_GMR2:
3860	{
3861	SVGAFifoCmdDefineGMR2 *pCmd;
3862	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3863	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3864	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3865
3866	/* Validate current GMR id. */
3867	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3868	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3869	RT_UNTRUSTED_VALIDATED_FENCE();
3870
3871	if (!pCmd->numPages)
3872	{
3873	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3874	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
3875	}
3876	else
3877	{
3878	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3879	if (pGMR->cMaxPages)
3880	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3881
3882	/* Not sure if we should always free the descriptor, but for simplicity
3883	we do so if the new size is smaller than the current. */
3884	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3885	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3886	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
3887
3888	pGMR->cMaxPages = pCmd->numPages;
3889	/* The rest is done by the REMAP_GMR2 command. */
3890	}
3891	break;
3892	}
3893
3894	case SVGA_CMD_REMAP_GMR2:
3895	{
3896	/* Followed by page descriptors or guest ptr. */
3897	SVGAFifoCmdRemapGMR2 *pCmd;
3898	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3899	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3900
3901	Log(("vmsvgaR3FifoLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3902	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3903	RT_UNTRUSTED_VALIDATED_FENCE();
3904
3905	/* Calculate the size of what comes after next and fetch it. */
3906	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3907	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3908	cbCmd += sizeof(SVGAGuestPtr);
3909	else
3910	{
3911	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3912	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3913	{
3914	cbCmd += cbPageDesc;
3915	pCmd->numPages = 1;
3916	}
3917	else
3918	{
3919	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3920	cbCmd += cbPageDesc * pCmd->numPages;
3921	}
3922	}
3923	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3924
3925	/* Validate current GMR id and size. */
3926	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3927	RT_UNTRUSTED_VALIDATED_FENCE();
3928	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3929	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3930	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3931	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3932
3933	if (pCmd->numPages == 0)
3934	break;
3935
3936	/** @todo Move to a separate function vmsvgaGMRRemap() */
3937
3938	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3939	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3940
3941	/*
3942	* We flatten the existing descriptors into a page array, overwrite the
3943	* pages specified in this command and then recompress the descriptor.
3944	*/
3945	/** @todo Optimize the GMR remap algorithm! */
3946
3947	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3948	uint64_t *paNewPage64 = NULL;
3949	if (pGMR->paDesc)
3950	{
3951	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3952
3953	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3954	AssertBreak(paNewPage64);
3955
3956	uint32_t idxPage = 0;
3957	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3958	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3959	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3960	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3961	RT_UNTRUSTED_VALIDATED_FENCE();
3962	}
3963
3964	/* Free the old GMR if present. */
3965	if (pGMR->paDesc)
3966	RTMemFree(pGMR->paDesc);
3967
3968	/* Allocate the maximum amount possible (everything non-continuous) */
3969	PVMSVGAGMRDESCRIPTOR paDescs;
3970	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3971	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3972
3973	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3974	{
3975	/** @todo */
3976	AssertFailed();
3977	pGMR->numDescriptors = 0;
3978	}
3979	else
3980	{
3981	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3982	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3983	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3984
3985	if (paNewPage64)
3986	{
3987	/* Overwrite the old page array with the new page values. */
3988	if (fGCPhys64)
3989	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3990	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3991	else
3992	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3993	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3994
3995	/* Use the updated page array instead of the command data. */
3996	fGCPhys64 = true;
3997	paPages64 = paNewPage64;
3998	pCmd->numPages = cNewTotalPages;
3999	}
4000
4001	/* The first page. */
4002	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
4003	* applied to paNewPage64. */
4004	RTGCPHYS GCPhys;
4005	if (fGCPhys64)
4006	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4007	else
4008	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4009	paDescs[0].GCPhys = GCPhys;
4010	paDescs[0].numPages = 1;
4011
4012	/* Subsequent pages. */
4013	uint32_t iDescriptor = 0;
4014	for (uint32_t i = 1; i < pCmd->numPages; i++)
4015	{
4016	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4017	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4018	else
4019	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4020
4021	/* Continuous physical memory? */
4022	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4023	{
4024	Assert(paDescs[iDescriptor].numPages);
4025	paDescs[iDescriptor].numPages++;
4026	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4027	}
4028	else
4029	{
4030	iDescriptor++;
4031	paDescs[iDescriptor].GCPhys = GCPhys;
4032	paDescs[iDescriptor].numPages = 1;
4033	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4034	}
4035	}
4036
4037	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4038	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4039	pGMR->numDescriptors = iDescriptor + 1;
4040	}
4041
4042	if (paNewPage64)
4043	RTMemFree(paNewPage64);
4044
4045	# ifdef DEBUG_GMR_ACCESS
4046	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4047	# endif
4048	break;
4049	}
4050	# endif // VBOX_WITH_VMSVGA3D
4051	case SVGA_CMD_DEFINE_SCREEN:
4052	{
4053	/* The size of this command is specified by the guest and depends on capabilities. */
4054	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4055
4056	SVGAFifoCmdDefineScreen *pCmd;
4057	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4058	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4059	RT_UNTRUSTED_VALIDATED_FENCE();
4060
4061	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4062	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4063	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4064
4065	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4066	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4067	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4068
4069	uint32_t const idScreen = pCmd->screen.id;
4070	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4071
4072	uint32_t const uWidth = pCmd->screen.size.width;
4073	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4074
4075	uint32_t const uHeight = pCmd->screen.size.height;
4076	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4077
4078	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4079	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4080	AssertBreak(cbWidth <= cbPitch);
4081
4082	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4083	AssertBreak(uScreenOffset < pThis->vram_size);
4084
4085	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4086	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4087	AssertBreak( (uHeight == 0 && cbPitch == 0)
4088	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4089	RT_UNTRUSTED_VALIDATED_FENCE();
4090
4091	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4092
4093	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4094
4095	pScreen->fDefined = true;
4096	pScreen->fModified = true;
4097	pScreen->fuScreen = pCmd->screen.flags;
4098	pScreen->idScreen = idScreen;
4099	if (!fBlank)
4100	{
4101	AssertBreak(uWidth > 0 && uHeight > 0);
4102
4103	pScreen->xOrigin = pCmd->screen.root.x;
4104	pScreen->yOrigin = pCmd->screen.root.y;
4105	pScreen->cWidth = uWidth;
4106	pScreen->cHeight = uHeight;
4107	pScreen->offVRAM = uScreenOffset;
4108	pScreen->cbPitch = cbPitch;
4109	pScreen->cBpp = 32;
4110	}
4111	else
4112	{
4113	/* Keep old values. */
4114	}
4115
4116	pThis->svga.fGFBRegisters = false;
4117	vmsvgaR3ChangeMode(pThis, pThisCC);
4118	break;
4119	}
4120
4121	case SVGA_CMD_DESTROY_SCREEN:
4122	{
4123	SVGAFifoCmdDestroyScreen *pCmd;
4124	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4125	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4126
4127	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4128
4129	uint32_t const idScreen = pCmd->screenId;
4130	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4131	RT_UNTRUSTED_VALIDATED_FENCE();
4132
4133	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4134	pScreen->fModified = true;
4135	pScreen->fDefined = false;
4136	pScreen->idScreen = idScreen;
4137
4138	vmsvgaR3ChangeMode(pThis, pThisCC);
4139	break;
4140	}
4141
4142	case SVGA_CMD_DEFINE_GMRFB:
4143	{
4144	SVGAFifoCmdDefineGMRFB *pCmd;
4145	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4146	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4147
4148	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4149	pSVGAState->GMRFB.ptr = pCmd->ptr;
4150	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4151	pSVGAState->GMRFB.format = pCmd->format;
4152	break;
4153	}
4154
4155	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4156	{
4157	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4158	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4159	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4160
4161	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4162	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4163
4164	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4165	RT_UNTRUSTED_VALIDATED_FENCE();
4166
4167	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
4168	AssertBreak(pScreen);
4169
4170	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4171	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4172
4173	/* Clip destRect to the screen dimensions. */
4174	SVGASignedRect screenRect;
4175	screenRect.left = 0;
4176	screenRect.top = 0;
4177	screenRect.right = pScreen->cWidth;
4178	screenRect.bottom = pScreen->cHeight;
4179	SVGASignedRect clipRect = pCmd->destRect;
4180	vmsvgaR3ClipRect(&screenRect, &clipRect);
4181	RT_UNTRUSTED_VALIDATED_FENCE();
4182
4183	uint32_t const width = clipRect.right - clipRect.left;
4184	uint32_t const height = clipRect.bottom - clipRect.top;
4185
4186	if ( width == 0
4187	\|\| height == 0)
4188	break; /* Nothing to do. */
4189
4190	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4191	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4192
4193	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4194	* Prepare parameters for vmsvgaR3GmrTransfer.
4195	*/
4196	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4197
4198	/* Destination: host buffer which describes the screen 0 VRAM.
4199	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4200	*/
4201	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4202	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4203	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4204	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4205	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4206	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4207	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4208	+ cbScanline * clipRect.top;
4209	int32_t const cbHstPitch = cbScanline;
4210
4211	/* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4212	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4213	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4214	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4215	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4216
4217	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
4218	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4219	gstPtr, offGst, cbGstPitch,
4220	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4221	AssertRC(rc);
4222	vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
4223	break;
4224	}
4225
4226	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4227	{
4228	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4229	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4230	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4231
4232	/* Note! This can fetch 3d render results as well!! */
4233	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4234	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4235
4236	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4237	RT_UNTRUSTED_VALIDATED_FENCE();
4238
4239	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
4240	AssertBreak(pScreen);
4241
4242	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4243	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4244
4245	/* Clip destRect to the screen dimensions. */
4246	SVGASignedRect screenRect;
4247	screenRect.left = 0;
4248	screenRect.top = 0;
4249	screenRect.right = pScreen->cWidth;
4250	screenRect.bottom = pScreen->cHeight;
4251	SVGASignedRect clipRect = pCmd->srcRect;
4252	vmsvgaR3ClipRect(&screenRect, &clipRect);
4253	RT_UNTRUSTED_VALIDATED_FENCE();
4254
4255	uint32_t const width = clipRect.right - clipRect.left;
4256	uint32_t const height = clipRect.bottom - clipRect.top;
4257
4258	if ( width == 0
4259	\|\| height == 0)
4260	break; /* Nothing to do. */
4261
4262	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4263	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4264
4265	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4266	* Prepare parameters for vmsvgaR3GmrTransfer.
4267	*/
4268	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4269
4270	/* Source: host buffer which describes the screen 0 VRAM.
4271	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4272	*/
4273	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4274	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4275	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4276	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4277	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4278	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4279	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4280	+ cbScanline * clipRect.top;
4281	int32_t const cbHstPitch = cbScanline;
4282
4283	/* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4284	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4285	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4286	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4287	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4288
4289	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
4290	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4291	gstPtr, offGst, cbGstPitch,
4292	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4293	AssertRC(rc);
4294	break;
4295	}
4296
4297	case SVGA_CMD_ANNOTATION_FILL:
4298	{
4299	SVGAFifoCmdAnnotationFill *pCmd;
4300	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4301	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4302
4303	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4304	pSVGAState->colorAnnotation = pCmd->color;
4305	break;
4306	}
4307
4308	case SVGA_CMD_ANNOTATION_COPY:
4309	{
4310	SVGAFifoCmdAnnotationCopy *pCmd;
4311	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4312	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4313
4314	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4315	AssertFailed();
4316	break;
4317	}
4318
4319	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4320
4321	default:
4322	# ifdef VBOX_WITH_VMSVGA3D
4323	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4324	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4325	{
4326	RT_UNTRUSTED_VALIDATED_FENCE();
4327
4328	/* All 3d commands start with a common header, which defines the size of the command. */
4329	SVGA3dCmdHeader *pHdr;
4330	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4331	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4332	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4333	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4334
4335	if (RT_LIKELY(pThis->svga.f3DEnabled))
4336	{ /* likely */ }
4337	else
4338	{
4339	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4340	break;
4341	}
4342
4343	/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4344	* Check that the 3D command has at least a_cbMin of payload bytes after the
4345	* header. Will break out of the switch if it doesn't.
4346	*/
4347	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4348	if (1) { \
4349	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4350	RT_UNTRUSTED_VALIDATED_FENCE(); \
4351	} else do {} while (0)
4352	switch ((int)enmCmdId)
4353	{
4354	case SVGA_3D_CMD_SURFACE_DEFINE:
4355	{
4356	uint32_t cMipLevels;
4357	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4358	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4359	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4360
4361	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4362	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4363	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4364	# ifdef DEBUG_GMR_ACCESS
4365	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4366	# endif
4367	break;
4368	}
4369
4370	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4371	{
4372	uint32_t cMipLevels;
4373	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4374	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4375	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4376
4377	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4378	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4379	pCmd->multisampleCount, pCmd->autogenFilter,
4380	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4381	break;
4382	}
4383
4384	case SVGA_3D_CMD_SURFACE_DESTROY:
4385	{
4386	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4387	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4388	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4389	rc = vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4390	break;
4391	}
4392
4393	case SVGA_3D_CMD_SURFACE_COPY:
4394	{
4395	uint32_t cCopyBoxes;
4396	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4397	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4398	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4399
4400	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4401	rc = vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4402	break;
4403	}
4404
4405	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4406	{
4407	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4408	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4409	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4410
4411	rc = vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4412	&pCmd->src, &pCmd->boxSrc, pCmd->mode);
4413	break;
4414	}
4415
4416	case SVGA_3D_CMD_SURFACE_DMA:
4417	{
4418	uint32_t cCopyBoxes;
4419	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4420	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4421	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4422
4423	uint64_t u64NanoTS = 0;
4424	if (LogRelIs3Enabled())
4425	u64NanoTS = RTTimeNanoTS();
4426	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4427	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4428	rc = vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4429	cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4430	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4431	if (LogRelIs3Enabled())
4432	{
4433	if (cCopyBoxes)
4434	{
4435	SVGA3dCopyBox pFirstBox = (SVGA3dCopyBox )(pCmd + 1);
4436	LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4437	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4438	pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4439	pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4440	}
4441	}
4442	break;
4443	}
4444
4445	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4446	{
4447	uint32_t cRects;
4448	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4449	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4450	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4451
4452	uint64_t u64NanoTS = 0;
4453	if (LogRelIs3Enabled())
4454	u64NanoTS = RTTimeNanoTS();
4455	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4456	STAM_REL_PROFILE_START(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4457	rc = vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4458	pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4459	STAM_REL_PROFILE_STOP(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4460	if (LogRelIs3Enabled())
4461	{
4462	SVGASignedRect pFirstRect = cRects ? (SVGASignedRect )(pCmd + 1) : &pCmd->destRect;
4463	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4464	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cRects,
4465	pFirstRect->left, pFirstRect->top,
4466	pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4467	}
4468	break;
4469	}
4470
4471	case SVGA_3D_CMD_CONTEXT_DEFINE:
4472	{
4473	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4474	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4475	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4476
4477	rc = vmsvga3dContextDefine(pThisCC, pCmd->cid);
4478	break;
4479	}
4480
4481	case SVGA_3D_CMD_CONTEXT_DESTROY:
4482	{
4483	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4484	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4485	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4486
4487	rc = vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4488	break;
4489	}
4490
4491	case SVGA_3D_CMD_SETTRANSFORM:
4492	{
4493	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4494	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4495	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4496
4497	rc = vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4498	break;
4499	}
4500
4501	case SVGA_3D_CMD_SETZRANGE:
4502	{
4503	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4504	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4505	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4506
4507	rc = vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4508	break;
4509	}
4510
4511	case SVGA_3D_CMD_SETRENDERSTATE:
4512	{
4513	uint32_t cRenderStates;
4514	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4515	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4516	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4517
4518	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4519	rc = vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4520	break;
4521	}
4522
4523	case SVGA_3D_CMD_SETRENDERTARGET:
4524	{
4525	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4526	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4527	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4528
4529	rc = vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4530	break;
4531	}
4532
4533	case SVGA_3D_CMD_SETTEXTURESTATE:
4534	{
4535	uint32_t cTextureStates;
4536	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4537	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4538	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4539
4540	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4541	rc = vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4542	break;
4543	}
4544
4545	case SVGA_3D_CMD_SETMATERIAL:
4546	{
4547	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4548	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4549	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4550
4551	rc = vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4552	break;
4553	}
4554
4555	case SVGA_3D_CMD_SETLIGHTDATA:
4556	{
4557	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4558	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4559	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4560
4561	rc = vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4562	break;
4563	}
4564
4565	case SVGA_3D_CMD_SETLIGHTENABLED:
4566	{
4567	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4568	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4569	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4570
4571	rc = vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4572	break;
4573	}
4574
4575	case SVGA_3D_CMD_SETVIEWPORT:
4576	{
4577	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4578	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4579	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4580
4581	rc = vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4582	break;
4583	}
4584
4585	case SVGA_3D_CMD_SETCLIPPLANE:
4586	{
4587	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4588	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4589	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4590
4591	rc = vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4592	break;
4593	}
4594
4595	case SVGA_3D_CMD_CLEAR:
4596	{
4597	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4598	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4599	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4600
4601	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4602	rc = vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4603	break;
4604	}
4605
4606	case SVGA_3D_CMD_PRESENT:
4607	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4608	{
4609	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4610	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4611	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4612	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4613	else
4614	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4615
4616	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4617
4618	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4619	rc = vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4620	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4621	break;
4622	}
4623
4624	case SVGA_3D_CMD_SHADER_DEFINE:
4625	{
4626	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4627	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4628	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4629
4630	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4631	rc = vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4632	break;
4633	}
4634
4635	case SVGA_3D_CMD_SHADER_DESTROY:
4636	{
4637	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4638	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4639	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4640
4641	rc = vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4642	break;
4643	}
4644
4645	case SVGA_3D_CMD_SET_SHADER:
4646	{
4647	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4648	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4649	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4650
4651	rc = vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4652	break;
4653	}
4654
4655	case SVGA_3D_CMD_SET_SHADER_CONST:
4656	{
4657	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4658	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4659	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4660
4661	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4662	rc = vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4663	break;
4664	}
4665
4666	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4667	{
4668	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4669	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4670	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4671
4672	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4673	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4674	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4675	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4676	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4677
4678	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4679	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4680
4681	RT_UNTRUSTED_VALIDATED_FENCE();
4682
4683	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4684	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4685	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4686
4687	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4688	rc = vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4689	pNumRange, cVertexDivisor, pVertexDivisor);
4690	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4691	break;
4692	}
4693
4694	case SVGA_3D_CMD_SETSCISSORRECT:
4695	{
4696	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4697	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4698	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4699
4700	rc = vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4701	break;
4702	}
4703
4704	case SVGA_3D_CMD_BEGIN_QUERY:
4705	{
4706	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4707	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4708	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4709
4710	rc = vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4711	break;
4712	}
4713
4714	case SVGA_3D_CMD_END_QUERY:
4715	{
4716	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4717	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4718	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4719
4720	rc = vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4721	break;
4722	}
4723
4724	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4725	{
4726	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4727	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4728	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4729
4730	rc = vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4731	break;
4732	}
4733
4734	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4735	{
4736	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4737	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4738	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4739
4740	rc = vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4741	break;
4742	}
4743
4744	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4745	/* context id + surface id? */
4746	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4747	break;
4748	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4749	/* context id + surface id? */
4750	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4751	break;
4752
4753	default:
4754	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4755	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4756	break;
4757	}
4758	}
4759	else
4760	# endif // VBOX_WITH_VMSVGA3D
4761	{
4762	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4763	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4764	}
4765	}
4766
4767	/* Go to the next slot */
4768	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4769	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4770	if (offCurrentCmd >= offFifoMax)
4771	{
4772	offCurrentCmd -= offFifoMax - offFifoMin;
4773	Assert(offCurrentCmd >= offFifoMin);
4774	Assert(offCurrentCmd < offFifoMax);
4775	}
4776	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4777	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4778
4779	/*
4780	* Raise IRQ if required. Must enter the critical section here
4781	* before making final decisions here, otherwise cubebench and
4782	* others may end up waiting forever.
4783	*/
4784	if ( u32IrqStatus
4785	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4786	{
4787	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4788	AssertRC(rc2);
4789
4790	/* FIFO progress might trigger an interrupt. */
4791	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4792	{
4793	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
4794	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4795	}
4796
4797	/* Unmasked IRQ pending? */
4798	if (pThis->svga.u32IrqMask & u32IrqStatus)
4799	{
4800	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4801	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4802	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4803	}
4804
4805	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4806	}
4807	}
4808
4809	/* If really done, clear the busy flag. */
4810	if (fDone)
4811	{
4812	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4813	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4814	}
4815	}
4816
4817	/*
4818	* Free the bounce buffer. (There are no returns above!)
4819	*/
4820	RTMemFree(pbBounceBuf);
4821
4822	return VINF_SUCCESS;
4823	}
4824
4825	#undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4826	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4827	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4828
4829	#ifdef VBOX_WITH_VMSVGA3D
4830	/**
4831	* Free the specified GMR
4832	*
4833	* @param pThisCC The VGA/VMSVGA state for ring-3.
4834	* @param idGMR GMR id
4835	*/
4836	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
4837	{
4838	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4839
4840	/* Free the old descriptor if present. */
4841	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4842	if ( pGMR->numDescriptors
4843	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4844	{
4845	# ifdef DEBUG_GMR_ACCESS
4846	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
4847	# endif
4848
4849	Assert(pGMR->paDesc);
4850	RTMemFree(pGMR->paDesc);
4851	pGMR->paDesc = NULL;
4852	pGMR->numDescriptors = 0;
4853	pGMR->cbTotal = 0;
4854	pGMR->cMaxPages = 0;
4855	}
4856	Assert(!pGMR->cMaxPages);
4857	Assert(!pGMR->cbTotal);
4858	}
4859	#endif /* VBOX_WITH_VMSVGA3D */
4860
4861	/**
4862	* Copy between a GMR and a host memory buffer.
4863	*
4864	* @returns VBox status code.
4865	* @param pThis The shared VGA/VMSVGA instance data.
4866	* @param pThisCC The VGA/VMSVGA state for ring-3.
4867	* @param enmTransferType Transfer type (read/write)
4868	* @param pbHstBuf Host buffer pointer (valid)
4869	* @param cbHstBuf Size of host buffer (valid)
4870	* @param offHst Host buffer offset of the first scanline
4871	* @param cbHstPitch Destination buffer pitch
4872	* @param gstPtr GMR description
4873	* @param offGst Guest buffer offset of the first scanline
4874	* @param cbGstPitch Guest buffer pitch
4875	* @param cbWidth Width in bytes to copy
4876	* @param cHeight Number of scanllines to copy
4877	*/
4878	int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
4879	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4880	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4881	uint32_t cbWidth, uint32_t cHeight)
4882	{
4883	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4884	PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
4885	int rc;
4886
4887	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4888	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4889	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4890	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4891	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4892
4893	PGMR pGMR;
4894	uint32_t cbGmr; /* The GMR size in bytes. */
4895	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4896	{
4897	pGMR = NULL;
4898	cbGmr = pThis->vram_size;
4899	}
4900	else
4901	{
4902	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4903	RT_UNTRUSTED_VALIDATED_FENCE();
4904	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4905	cbGmr = pGMR->cbTotal;
4906	}
4907
4908	/*
4909	* GMR
4910	*/
4911	/* Calculate GMR offset of the data to be copied. */
4912	AssertMsgReturn(gstPtr.offset < cbGmr,
4913	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4914	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4915	VERR_INVALID_PARAMETER);
4916	RT_UNTRUSTED_VALIDATED_FENCE();
4917	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4918	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4919	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4920	VERR_INVALID_PARAMETER);
4921	RT_UNTRUSTED_VALIDATED_FENCE();
4922	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4923
4924	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4925	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4926	AssertMsgReturn(cbGmrScanline != 0,
4927	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4928	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4929	VERR_INVALID_PARAMETER);
4930	RT_UNTRUSTED_VALIDATED_FENCE();
4931	AssertMsgReturn(cbWidth <= cbGmrScanline,
4932	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4933	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4934	VERR_INVALID_PARAMETER);
4935	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4936	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4937	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4938	VERR_INVALID_PARAMETER);
4939	RT_UNTRUSTED_VALIDATED_FENCE();
4940
4941	/* How many bytes are available for the data in the GMR. */
4942	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4943
4944	/* How many scanlines would fit into the available data. */
4945	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4946	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4947	if (cbWidth <= cbGmrLastScanline)
4948	++cGmrScanlines;
4949
4950	if (cHeight > cGmrScanlines)
4951	cHeight = cGmrScanlines;
4952
4953	AssertMsgReturn(cHeight > 0,
4954	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4955	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4956	VERR_INVALID_PARAMETER);
4957	RT_UNTRUSTED_VALIDATED_FENCE();
4958
4959	/*
4960	* Host buffer.
4961	*/
4962	AssertMsgReturn(offHst < cbHstBuf,
4963	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4964	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4965	VERR_INVALID_PARAMETER);
4966
4967	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4968	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4969	AssertMsgReturn(cbHstScanline != 0,
4970	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4971	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4972	VERR_INVALID_PARAMETER);
4973	AssertMsgReturn(cbWidth <= cbHstScanline,
4974	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4975	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4976	VERR_INVALID_PARAMETER);
4977	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4978	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4979	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4980	VERR_INVALID_PARAMETER);
4981
4982	/* How many bytes are available for the data in the buffer. */
4983	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4984
4985	/* How many scanlines would fit into the available data. */
4986	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4987	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4988	if (cbWidth <= cbHstLastScanline)
4989	++cHstScanlines;
4990
4991	if (cHeight > cHstScanlines)
4992	cHeight = cHstScanlines;
4993
4994	AssertMsgReturn(cHeight > 0,
4995	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4996	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4997	VERR_INVALID_PARAMETER);
4998
4999	uint8_t *pbHst = pbHstBuf + offHst;
5000
5001	/* Shortcut for the framebuffer. */
5002	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
5003	{
5004	uint8_t *pbGst = pThisCC->pbVRam + offGmr;
5005
5006	uint8_t const *pbSrc;
5007	int32_t cbSrcPitch;
5008	uint8_t *pbDst;
5009	int32_t cbDstPitch;
5010
5011	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
5012	{
5013	pbSrc = pbHst;
5014	cbSrcPitch = cbHstPitch;
5015	pbDst = pbGst;
5016	cbDstPitch = cbGstPitch;
5017	}
5018	else
5019	{
5020	pbSrc = pbGst;
5021	cbSrcPitch = cbGstPitch;
5022	pbDst = pbHst;
5023	cbDstPitch = cbHstPitch;
5024	}
5025
5026	if ( cbWidth == (uint32_t)cbGstPitch
5027	&& cbGstPitch == cbHstPitch)
5028	{
5029	/* Entire scanlines, positive pitch. */
5030	memcpy(pbDst, pbSrc, cbWidth * cHeight);
5031	}
5032	else
5033	{
5034	for (uint32_t i = 0; i < cHeight; ++i)
5035	{
5036	memcpy(pbDst, pbSrc, cbWidth);
5037
5038	pbDst += cbDstPitch;
5039	pbSrc += cbSrcPitch;
5040	}
5041	}
5042	return VINF_SUCCESS;
5043	}
5044
5045	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
5046	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
5047
5048	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
5049	uint32_t iDesc = 0; /* Index in the descriptor array. */
5050	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
5051	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
5052	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
5053	for (uint32_t i = 0; i < cHeight; ++i)
5054	{
5055	uint32_t cbCurrentWidth = cbWidth;
5056	uint32_t offGmrCurrent = offGmrScanline;
5057	uint8_t *pbCurrentHost = pbHstScanline;
5058
5059	/* Find the right descriptor */
5060	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5061	{
5062	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5063	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5064	++iDesc;
5065	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5066	}
5067
5068	while (cbCurrentWidth)
5069	{
5070	uint32_t cbToCopy;
5071
5072	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5073	{
5074	cbToCopy = cbCurrentWidth;
5075	}
5076	else
5077	{
5078	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5079	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5080	}
5081
5082	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5083
5084	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5085
5086	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5087	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5088	else
5089	rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5090	AssertRCBreak(rc);
5091
5092	cbCurrentWidth -= cbToCopy;
5093	offGmrCurrent += cbToCopy;
5094	pbCurrentHost += cbToCopy;
5095
5096	/* Go to the next descriptor if there's anything left. */
5097	if (cbCurrentWidth)
5098	{
5099	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5100	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5101	++iDesc;
5102	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5103	}
5104	}
5105
5106	offGmrScanline += cbGstPitch;
5107	pbHstScanline += cbHstPitch;
5108	}
5109
5110	return VINF_SUCCESS;
5111	}
5112
5113
5114	/**
5115	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5116	*
5117	* @param pSizeSrc Source surface dimensions.
5118	* @param pSizeDest Destination surface dimensions.
5119	* @param pBox Coordinates to be clipped.
5120	*/
5121	void vmsvgaR3ClipCopyBox(const SVGA3dSize pSizeSrc, const SVGA3dSize pSizeDest, SVGA3dCopyBox *pBox)
5122	{
5123	/* Src x, w */
5124	if (pBox->srcx > pSizeSrc->width)
5125	pBox->srcx = pSizeSrc->width;
5126	if (pBox->w > pSizeSrc->width - pBox->srcx)
5127	pBox->w = pSizeSrc->width - pBox->srcx;
5128
5129	/* Src y, h */
5130	if (pBox->srcy > pSizeSrc->height)
5131	pBox->srcy = pSizeSrc->height;
5132	if (pBox->h > pSizeSrc->height - pBox->srcy)
5133	pBox->h = pSizeSrc->height - pBox->srcy;
5134
5135	/* Src z, d */
5136	if (pBox->srcz > pSizeSrc->depth)
5137	pBox->srcz = pSizeSrc->depth;
5138	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5139	pBox->d = pSizeSrc->depth - pBox->srcz;
5140
5141	/* Dest x, w */
5142	if (pBox->x > pSizeDest->width)
5143	pBox->x = pSizeDest->width;
5144	if (pBox->w > pSizeDest->width - pBox->x)
5145	pBox->w = pSizeDest->width - pBox->x;
5146
5147	/* Dest y, h */
5148	if (pBox->y > pSizeDest->height)
5149	pBox->y = pSizeDest->height;
5150	if (pBox->h > pSizeDest->height - pBox->y)
5151	pBox->h = pSizeDest->height - pBox->y;
5152
5153	/* Dest z, d */
5154	if (pBox->z > pSizeDest->depth)
5155	pBox->z = pSizeDest->depth;
5156	if (pBox->d > pSizeDest->depth - pBox->z)
5157	pBox->d = pSizeDest->depth - pBox->z;
5158	}
5159
5160	/**
5161	* Unsigned coordinates in pBox. Clip to [0; pSize).
5162	*
5163	* @param pSize Source surface dimensions.
5164	* @param pBox Coordinates to be clipped.
5165	*/
5166	void vmsvgaR3ClipBox(const SVGA3dSize pSize, SVGA3dBox pBox)
5167	{
5168	/* x, w */
5169	if (pBox->x > pSize->width)
5170	pBox->x = pSize->width;
5171	if (pBox->w > pSize->width - pBox->x)
5172	pBox->w = pSize->width - pBox->x;
5173
5174	/* y, h */
5175	if (pBox->y > pSize->height)
5176	pBox->y = pSize->height;
5177	if (pBox->h > pSize->height - pBox->y)
5178	pBox->h = pSize->height - pBox->y;
5179
5180	/* z, d */
5181	if (pBox->z > pSize->depth)
5182	pBox->z = pSize->depth;
5183	if (pBox->d > pSize->depth - pBox->z)
5184	pBox->d = pSize->depth - pBox->z;
5185	}
5186
5187	/**
5188	* Clip.
5189	*
5190	* @param pBound Bounding rectangle.
5191	* @param pRect Rectangle to be clipped.
5192	*/
5193	void vmsvgaR3ClipRect(SVGASignedRect const pBound, SVGASignedRect pRect)
5194	{
5195	int32_t left;
5196	int32_t top;
5197	int32_t right;
5198	int32_t bottom;
5199
5200	/* Right order. */
5201	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5202	if (pRect->left < pRect->right)
5203	{
5204	left = pRect->left;
5205	right = pRect->right;
5206	}
5207	else
5208	{
5209	left = pRect->right;
5210	right = pRect->left;
5211	}
5212	if (pRect->top < pRect->bottom)
5213	{
5214	top = pRect->top;
5215	bottom = pRect->bottom;
5216	}
5217	else
5218	{
5219	top = pRect->bottom;
5220	bottom = pRect->top;
5221	}
5222
5223	if (left < pBound->left)
5224	left = pBound->left;
5225	if (right < pBound->left)
5226	right = pBound->left;
5227
5228	if (left > pBound->right)
5229	left = pBound->right;
5230	if (right > pBound->right)
5231	right = pBound->right;
5232
5233	if (top < pBound->top)
5234	top = pBound->top;
5235	if (bottom < pBound->top)
5236	bottom = pBound->top;
5237
5238	if (top > pBound->bottom)
5239	top = pBound->bottom;
5240	if (bottom > pBound->bottom)
5241	bottom = pBound->bottom;
5242
5243	pRect->left = left;
5244	pRect->right = right;
5245	pRect->top = top;
5246	pRect->bottom = bottom;
5247	}
5248
5249	/**
5250	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5251	* Unblock the FIFO I/O thread so it can respond to a state change.}
5252	*/
5253	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5254	{
5255	RT_NOREF(pDevIns);
5256	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5257	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5258	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5259	}
5260
5261	/**
5262	* Enables or disables dirty page tracking for the framebuffer
5263	*
5264	* @param pDevIns The device instance.
5265	* @param pThis The shared VGA/VMSVGA instance data.
5266	* @param fTraces Enable/disable traces
5267	*/
5268	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5269	{
5270	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5271	&& !fTraces)
5272	{
5273	//Assert(pThis->svga.fTraces);
5274	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5275	return;
5276	}
5277
5278	pThis->svga.fTraces = fTraces;
5279	if (pThis->svga.fTraces)
5280	{
5281	unsigned cbFrameBuffer = pThis->vram_size;
5282
5283	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5284	/** @todo How does this work with screens? */
5285	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5286	{
5287	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5288	Assert(pThis->svga.cbScanline);
5289	# endif
5290	/* Hardware enabled; return real framebuffer size .*/
5291	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5292	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5293	}
5294
5295	if (!pThis->svga.fVRAMTracking)
5296	{
5297	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5298	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5299	pThis->svga.fVRAMTracking = true;
5300	}
5301	}
5302	else
5303	{
5304	if (pThis->svga.fVRAMTracking)
5305	{
5306	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5307	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5308	pThis->svga.fVRAMTracking = false;
5309	}
5310	}
5311	}
5312
5313	/**
5314	* @callback_method_impl{FNPCIIOREGIONMAP}
5315	*/
5316	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5317	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5318	{
5319	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5320	int rc;
5321	RT_NOREF(pPciDev);
5322	Assert(pPciDev == pDevIns->apPciDevs[0]);
5323
5324	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5325	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5326	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5327	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5328	, VERR_INTERNAL_ERROR);
5329	if (GCPhysAddress != NIL_RTGCPHYS)
5330	{
5331	/*
5332	* Mapping the FIFO RAM.
5333	*/
5334	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5335	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5336	AssertRC(rc);
5337
5338	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5339	if (RT_SUCCESS(rc))
5340	{
5341	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5342	# ifdef DEBUG_FIFO_ACCESS
5343	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5344	# else
5345	GCPhysAddress + PAGE_SIZE - 1,
5346	# endif
5347	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5348	"VMSVGA FIFO");
5349	AssertRC(rc);
5350	}
5351	# endif
5352	if (RT_SUCCESS(rc))
5353	{
5354	pThis->svga.GCPhysFIFO = GCPhysAddress;
5355	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5356	}
5357	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite erros here. */
5358	}
5359	else
5360	{
5361	Assert(pThis->svga.GCPhysFIFO);
5362	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5363	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5364	AssertRC(rc);
5365	# else
5366	rc = VINF_SUCCESS;
5367	# endif
5368	pThis->svga.GCPhysFIFO = 0;
5369	}
5370	return rc;
5371	}
5372
5373	# ifdef VBOX_WITH_VMSVGA3D
5374
5375	/**
5376	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5377	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5378	*
5379	* @param pDevIns The device instance.
5380	* @param pThis The The shared VGA/VMSVGA instance data.
5381	* @param pThisCC The VGA/VMSVGA state for ring-3.
5382	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5383	* UINT32_MAX is used, all surfaces are processed.
5384	*/
5385	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5386	{
5387	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5388	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5389	}
5390
5391
5392	/**
5393	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5394	*/
5395	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5396	{
5397	/* There might be a specific surface ID at the start of the
5398	arguments, if not show all surfaces. */
5399	uint32_t sid = UINT32_MAX;
5400	if (pszArgs)
5401	pszArgs = RTStrStripL(pszArgs);
5402	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5403	sid = RTStrToUInt32(pszArgs);
5404
5405	/* Verbose or terse display, we default to verbose. */
5406	bool fVerbose = true;
5407	if (RTStrIStr(pszArgs, "terse"))
5408	fVerbose = false;
5409
5410	/* The size of the ascii art (x direction, y is 3/4 of x). */
5411	uint32_t cxAscii = 80;
5412	if (RTStrIStr(pszArgs, "gigantic"))
5413	cxAscii = 300;
5414	else if (RTStrIStr(pszArgs, "huge"))
5415	cxAscii = 180;
5416	else if (RTStrIStr(pszArgs, "big"))
5417	cxAscii = 132;
5418	else if (RTStrIStr(pszArgs, "normal"))
5419	cxAscii = 80;
5420	else if (RTStrIStr(pszArgs, "medium"))
5421	cxAscii = 64;
5422	else if (RTStrIStr(pszArgs, "small"))
5423	cxAscii = 48;
5424	else if (RTStrIStr(pszArgs, "tiny"))
5425	cxAscii = 24;
5426
5427	/* Y invert the image when producing the ASCII art. */
5428	bool fInvY = false;
5429	if (RTStrIStr(pszArgs, "invy"))
5430	fInvY = true;
5431
5432	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5433	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5434	}
5435
5436
5437	/**
5438	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5439	*/
5440	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5441	{
5442	/* pszArg = "sid[>dir]"
5443	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5444	*/
5445	char *pszBitmapPath = NULL;
5446	uint32_t sid = UINT32_MAX;
5447	if (pszArgs)
5448	pszArgs = RTStrStripL(pszArgs);
5449	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5450	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5451	if ( pszBitmapPath
5452	&& *pszBitmapPath == '>')
5453	++pszBitmapPath;
5454
5455	const bool fVerbose = true;
5456	const uint32_t cxAscii = 0; /* No ASCII */
5457	const bool fInvY = false; /* Do not invert. */
5458	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5459	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5460	}
5461
5462
5463	/**
5464	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5465	*/
5466	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5467	{
5468	/* There might be a specific surface ID at the start of the
5469	arguments, if not show all contexts. */
5470	uint32_t sid = UINT32_MAX;
5471	if (pszArgs)
5472	pszArgs = RTStrStripL(pszArgs);
5473	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5474	sid = RTStrToUInt32(pszArgs);
5475
5476	/* Verbose or terse display, we default to verbose. */
5477	bool fVerbose = true;
5478	if (RTStrIStr(pszArgs, "terse"))
5479	fVerbose = false;
5480
5481	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5482	}
5483
5484	# endif /* VBOX_WITH_VMSVGA3D */
5485
5486	/**
5487	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5488	*/
5489	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5490	{
5491	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5492	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5493	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5494	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5495	RT_NOREF(pszArgs);
5496
5497	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5498	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5499	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5500	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5501	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5502	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5503	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5504	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5505	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5506	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5507	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5508	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5509	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5510	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5511	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5512	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5513	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5514	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5515	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5516	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5517	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5518	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5519	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5520	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5521	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5522
5523	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5524	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5525	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5526	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5527
5528	# ifdef VBOX_WITH_VMSVGA3D
5529	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5530	# endif
5531	if (pThisCC->pDrv)
5532	{
5533	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5534	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5535	}
5536	}
5537
5538	/**
5539	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5540	*/
5541	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5542	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5543	{
5544	RT_NOREF(uPass);
5545
5546	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5547	int rc;
5548
5549	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5550	{
5551	uint32_t cScreens = 0;
5552	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5553	AssertRCReturn(rc, rc);
5554	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5555	("cScreens=%#x\n", cScreens),
5556	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5557
5558	for (uint32_t i = 0; i < cScreens; ++i)
5559	{
5560	VMSVGASCREENOBJECT screen;
5561	RT_ZERO(screen);
5562
5563	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5564	AssertLogRelRCReturn(rc, rc);
5565
5566	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5567	{
5568	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5569	*pScreen = screen;
5570	pScreen->fModified = true;
5571	}
5572	else
5573	{
5574	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5575	}
5576	}
5577	}
5578	else
5579	{
5580	/* Try to setup at least the first screen. */
5581	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5582	pScreen->fDefined = true;
5583	pScreen->fModified = true;
5584	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5585	pScreen->idScreen = 0;
5586	pScreen->xOrigin = 0;
5587	pScreen->yOrigin = 0;
5588	pScreen->offVRAM = pThis->svga.uScreenOffset;
5589	pScreen->cbPitch = pThis->svga.cbScanline;
5590	pScreen->cWidth = pThis->svga.uWidth;
5591	pScreen->cHeight = pThis->svga.uHeight;
5592	pScreen->cBpp = pThis->svga.uBpp;
5593	}
5594
5595	return VINF_SUCCESS;
5596	}
5597
5598	/**
5599	* @copydoc FNSSMDEVLOADEXEC
5600	*/
5601	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5602	{
5603	RT_NOREF(uPass);
5604	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5605	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5606	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5607	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5608	int rc;
5609
5610	/* Load our part of the VGAState */
5611	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5612	AssertRCReturn(rc, rc);
5613
5614	/* Load the VGA framebuffer. */
5615	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5616	uint32_t cbVgaFramebuffer = _32K;
5617	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5618	{
5619	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5620	AssertRCReturn(rc, rc);
5621	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5622	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5623	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5624	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5625	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5626	}
5627	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5628	AssertRCReturn(rc, rc);
5629	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5630	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5631	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5632	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5633
5634	/* Load the VMSVGA state. */
5635	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5636	AssertRCReturn(rc, rc);
5637
5638	/* Load the active cursor bitmaps. */
5639	if (pSVGAState->Cursor.fActive)
5640	{
5641	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5642	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5643
5644	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5645	AssertRCReturn(rc, rc);
5646	}
5647
5648	/* Load the GMR state. */
5649	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5650	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5651	{
5652	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5653	AssertRCReturn(rc, rc);
5654	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5655	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5656	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5657	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5658	}
5659
5660	if (pThis->svga.cGMR != cGMR)
5661	{
5662	/* Reallocate GMR array. */
5663	Assert(pSVGAState->paGMR != NULL);
5664	RTMemFree(pSVGAState->paGMR);
5665	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5666	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5667	pThis->svga.cGMR = cGMR;
5668	}
5669
5670	for (uint32_t i = 0; i < cGMR; ++i)
5671	{
5672	PGMR pGMR = &pSVGAState->paGMR[i];
5673
5674	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5675	AssertRCReturn(rc, rc);
5676
5677	if (pGMR->numDescriptors)
5678	{
5679	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5680	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5681	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5682
5683	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5684	{
5685	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5686	AssertRCReturn(rc, rc);
5687	}
5688	}
5689	}
5690
5691	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5692	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
5693	# endif
5694
5695	VMSVGA_STATE_LOAD LoadState;
5696	LoadState.pSSM = pSSM;
5697	LoadState.uVersion = uVersion;
5698	LoadState.uPass = uPass;
5699	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5700	AssertLogRelRCReturn(rc, rc);
5701
5702	return VINF_SUCCESS;
5703	}
5704
5705	/**
5706	* Reinit the video mode after the state has been loaded.
5707	*/
5708	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5709	{
5710	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5711	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5712	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5713
5714	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5715
5716	/* Set the active cursor. */
5717	if (pSVGAState->Cursor.fActive)
5718	{
5719	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
5720	true /fVisible/,
5721	true /fAlpha/,
5722	pSVGAState->Cursor.xHotspot,
5723	pSVGAState->Cursor.yHotspot,
5724	pSVGAState->Cursor.width,
5725	pSVGAState->Cursor.height,
5726	pSVGAState->Cursor.pData);
5727	AssertRC(rc);
5728	}
5729	return VINF_SUCCESS;
5730	}
5731
5732	/**
5733	* Portion of SVGA state which must be saved in the FIFO thread.
5734	*/
5735	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5736	{
5737	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5738	int rc;
5739
5740	/* Save the screen objects. */
5741	/* Count defined screen object. */
5742	uint32_t cScreens = 0;
5743	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5744	{
5745	if (pSVGAState->aScreens[i].fDefined)
5746	++cScreens;
5747	}
5748
5749	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5750	AssertLogRelRCReturn(rc, rc);
5751
5752	for (uint32_t i = 0; i < cScreens; ++i)
5753	{
5754	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5755
5756	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5757	AssertLogRelRCReturn(rc, rc);
5758	}
5759	return VINF_SUCCESS;
5760	}
5761
5762	/**
5763	* @copydoc FNSSMDEVSAVEEXEC
5764	*/
5765	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5766	{
5767	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5768	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5769	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5770	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5771	int rc;
5772
5773	/* Save our part of the VGAState */
5774	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5775	AssertLogRelRCReturn(rc, rc);
5776
5777	/* Save the framebuffer backup. */
5778	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5779	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5780	AssertLogRelRCReturn(rc, rc);
5781
5782	/* Save the VMSVGA state. */
5783	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5784	AssertLogRelRCReturn(rc, rc);
5785
5786	/* Save the active cursor bitmaps. */
5787	if (pSVGAState->Cursor.fActive)
5788	{
5789	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5790	AssertLogRelRCReturn(rc, rc);
5791	}
5792
5793	/* Save the GMR state */
5794	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5795	AssertLogRelRCReturn(rc, rc);
5796	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5797	{
5798	PGMR pGMR = &pSVGAState->paGMR[i];
5799
5800	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5801	AssertLogRelRCReturn(rc, rc);
5802
5803	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5804	{
5805	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5806	AssertLogRelRCReturn(rc, rc);
5807	}
5808	}
5809
5810	/*
5811	* Must save some state (3D in particular) in the FIFO thread.
5812	*/
5813	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5814	AssertLogRelRCReturn(rc, rc);
5815
5816	return VINF_SUCCESS;
5817	}
5818
5819	/**
5820	* Destructor for PVMSVGAR3STATE structure.
5821	*
5822	* @param pThis The shared VGA/VMSVGA instance data.
5823	* @param pSVGAState Pointer to the structure. It is not deallocated.
5824	*/
5825	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5826	{
5827	# ifndef VMSVGA_USE_EMT_HALT_CODE
5828	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5829	{
5830	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5831	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5832	}
5833	# endif
5834
5835	if (pSVGAState->Cursor.fActive)
5836	{
5837	RTMemFree(pSVGAState->Cursor.pData);
5838	pSVGAState->Cursor.pData = NULL;
5839	pSVGAState->Cursor.fActive = false;
5840	}
5841
5842	if (pSVGAState->paGMR)
5843	{
5844	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5845	if (pSVGAState->paGMR[i].paDesc)
5846	RTMemFree(pSVGAState->paGMR[i].paDesc);
5847
5848	RTMemFree(pSVGAState->paGMR);
5849	pSVGAState->paGMR = NULL;
5850	}
5851	}
5852
5853	/**
5854	* Constructor for PVMSVGAR3STATE structure.
5855	*
5856	* @returns VBox status code.
5857	* @param pThis The shared VGA/VMSVGA instance data.
5858	* @param pSVGAState Pointer to the structure. It is already allocated.
5859	*/
5860	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5861	{
5862	int rc = VINF_SUCCESS;
5863	RT_ZERO(*pSVGAState);
5864
5865	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5866	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5867
5868	# ifndef VMSVGA_USE_EMT_HALT_CODE
5869	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5870	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5871	AssertRCReturn(rc, rc);
5872	# endif
5873
5874	return rc;
5875	}
5876
5877	/**
5878	* Initializes the host capabilities: registers and FIFO.
5879	*
5880	* @returns VBox status code.
5881	* @param pThis The shared VGA/VMSVGA instance data.
5882	* @param pThisCC The VGA/VMSVGA state for ring-3.
5883	*/
5884	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5885	{
5886	/* Register caps. */
5887	pThis->svga.u32RegCaps = SVGA_CAP_GMR
5888	\| SVGA_CAP_GMR2
5889	\| SVGA_CAP_CURSOR
5890	\| SVGA_CAP_CURSOR_BYPASS_2
5891	\| SVGA_CAP_EXTENDED_FIFO
5892	\| SVGA_CAP_IRQMASK
5893	\| SVGA_CAP_PITCHLOCK
5894	\| SVGA_CAP_TRACES
5895	\| SVGA_CAP_SCREEN_OBJECT_2
5896	\| SVGA_CAP_ALPHA_CURSOR;
5897	# ifdef VBOX_WITH_VMSVGA3D
5898	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5899	# endif
5900
5901	/* Clear the FIFO. */
5902	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
5903
5904	/* Setup FIFO capabilities. */
5905	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5906	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5907	\| SVGA_FIFO_CAP_GMR2
5908	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5909	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
5910	\| SVGA_FIFO_CAP_RESERVE
5911	\| SVGA_FIFO_CAP_PITCHLOCK;
5912
5913	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5914	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5915	}
5916
5917	# ifdef VBOX_WITH_VMSVGA3D
5918	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5919	static const char * const g_apszVmSvgaDevCapNames[] =
5920	{
5921	"x3D", /* = 0 */
5922	"xMAX_LIGHTS",
5923	"xMAX_TEXTURES",
5924	"xMAX_CLIP_PLANES",
5925	"xVERTEX_SHADER_VERSION",
5926	"xVERTEX_SHADER",
5927	"xFRAGMENT_SHADER_VERSION",
5928	"xFRAGMENT_SHADER",
5929	"xMAX_RENDER_TARGETS",
5930	"xS23E8_TEXTURES",
5931	"xS10E5_TEXTURES",
5932	"xMAX_FIXED_VERTEXBLEND",
5933	"xD16_BUFFER_FORMAT",
5934	"xD24S8_BUFFER_FORMAT",
5935	"xD24X8_BUFFER_FORMAT",
5936	"xQUERY_TYPES",
5937	"xTEXTURE_GRADIENT_SAMPLING",
5938	"rMAX_POINT_SIZE",
5939	"xMAX_SHADER_TEXTURES",
5940	"xMAX_TEXTURE_WIDTH",
5941	"xMAX_TEXTURE_HEIGHT",
5942	"xMAX_VOLUME_EXTENT",
5943	"xMAX_TEXTURE_REPEAT",
5944	"xMAX_TEXTURE_ASPECT_RATIO",
5945	"xMAX_TEXTURE_ANISOTROPY",
5946	"xMAX_PRIMITIVE_COUNT",
5947	"xMAX_VERTEX_INDEX",
5948	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5949	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5950	"xMAX_VERTEX_SHADER_TEMPS",
5951	"xMAX_FRAGMENT_SHADER_TEMPS",
5952	"xTEXTURE_OPS",
5953	"xSURFACEFMT_X8R8G8B8",
5954	"xSURFACEFMT_A8R8G8B8",
5955	"xSURFACEFMT_A2R10G10B10",
5956	"xSURFACEFMT_X1R5G5B5",
5957	"xSURFACEFMT_A1R5G5B5",
5958	"xSURFACEFMT_A4R4G4B4",
5959	"xSURFACEFMT_R5G6B5",
5960	"xSURFACEFMT_LUMINANCE16",
5961	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5962	"xSURFACEFMT_ALPHA8",
5963	"xSURFACEFMT_LUMINANCE8",
5964	"xSURFACEFMT_Z_D16",
5965	"xSURFACEFMT_Z_D24S8",
5966	"xSURFACEFMT_Z_D24X8",
5967	"xSURFACEFMT_DXT1",
5968	"xSURFACEFMT_DXT2",
5969	"xSURFACEFMT_DXT3",
5970	"xSURFACEFMT_DXT4",
5971	"xSURFACEFMT_DXT5",
5972	"xSURFACEFMT_BUMPX8L8V8U8",
5973	"xSURFACEFMT_A2W10V10U10",
5974	"xSURFACEFMT_BUMPU8V8",
5975	"xSURFACEFMT_Q8W8V8U8",
5976	"xSURFACEFMT_CxV8U8",
5977	"xSURFACEFMT_R_S10E5",
5978	"xSURFACEFMT_R_S23E8",
5979	"xSURFACEFMT_RG_S10E5",
5980	"xSURFACEFMT_RG_S23E8",
5981	"xSURFACEFMT_ARGB_S10E5",
5982	"xSURFACEFMT_ARGB_S23E8",
5983	"xMISSING62",
5984	"xMAX_VERTEX_SHADER_TEXTURES",
5985	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
5986	"xSURFACEFMT_V16U16",
5987	"xSURFACEFMT_G16R16",
5988	"xSURFACEFMT_A16B16G16R16",
5989	"xSURFACEFMT_UYVY",
5990	"xSURFACEFMT_YUY2",
5991	"xMULTISAMPLE_NONMASKABLESAMPLES",
5992	"xMULTISAMPLE_MASKABLESAMPLES",
5993	"xALPHATOCOVERAGE",
5994	"xSUPERSAMPLE",
5995	"xAUTOGENMIPMAPS",
5996	"xSURFACEFMT_NV12",
5997	"xSURFACEFMT_AYUV",
5998	"xMAX_CONTEXT_IDS",
5999	"xMAX_SURFACE_IDS",
6000	"xSURFACEFMT_Z_DF16",
6001	"xSURFACEFMT_Z_DF24",
6002	"xSURFACEFMT_Z_D24S8_INT",
6003	"xSURFACEFMT_BC4_UNORM",
6004	"xSURFACEFMT_BC5_UNORM", /* 83 */
6005	};
6006
6007	/**
6008	* Initializes the host 3D capabilities in FIFO.
6009	*
6010	* @returns VBox status code.
6011	* @param pThis The shared VGA/VMSVGA instance data.
6012	* @param pThisCC The VGA/VMSVGA state for ring-3.
6013	*/
6014	static void vmsvgaR3InitFifo3DCaps(PVGASTATECC pThisCC)
6015	{
6016	/** @todo Probably query the capabilities once and cache in a memory buffer. */
6017	bool fSavedBuffering = RTLogRelSetBuffering(true);
6018	SVGA3dCapsRecord *pCaps;
6019	SVGA3dCapPair *pData;
6020	uint32_t idxCap = 0;
6021
6022	/* 3d hardware version; latest and greatest */
6023	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6024	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6025
6026	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
6027	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6028	pData = (SVGA3dCapPair *)&pCaps->data;
6029
6030	/* Fill out all 3d capabilities. */
6031	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6032	{
6033	uint32_t val = 0;
6034
6035	int rc = vmsvga3dQueryCaps(pThisCC, i, &val);
6036	if (RT_SUCCESS(rc))
6037	{
6038	pData[idxCap][0] = i;
6039	pData[idxCap][1] = val;
6040	idxCap++;
6041	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6042	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6043	else
6044	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6045	&g_apszVmSvgaDevCapNames[i][1]));
6046	}
6047	else
6048	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6049	}
6050	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6051	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6052
6053	/* Mark end of record array. */
6054	pCaps->header.length = 0;
6055
6056	RTLogRelSetBuffering(fSavedBuffering);
6057	}
6058
6059	# endif
6060
6061	/**
6062	* Resets the SVGA hardware state
6063	*
6064	* @returns VBox status code.
6065	* @param pDevIns The device instance.
6066	*/
6067	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6068	{
6069	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6070	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6071	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6072
6073	/* Reset before init? */
6074	if (!pSVGAState)
6075	return VINF_SUCCESS;
6076
6077	Log(("vmsvgaR3Reset\n"));
6078
6079	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6080	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6081	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6082
6083	/* Reset other stuff. */
6084	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6085	RT_ZERO(pThis->svga.au32ScratchRegion);
6086
6087	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6088	vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6089
6090	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6091
6092	/* Initialize FIFO and register capabilities. */
6093	vmsvgaR3InitCaps(pThis, pThisCC);
6094
6095	# ifdef VBOX_WITH_VMSVGA3D
6096	if (pThis->svga.f3DEnabled)
6097	vmsvgaR3InitFifo3DCaps(pThisCC);
6098	# endif
6099
6100	/* VRAM tracking is enabled by default during bootup. */
6101	pThis->svga.fVRAMTracking = true;
6102	pThis->svga.fEnabled = false;
6103
6104	/* Invalidate current settings. */
6105	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6106	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6107	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6108	pThis->svga.cbScanline = 0;
6109	pThis->svga.u32PitchLock = 0;
6110
6111	return rc;
6112	}
6113
6114	/**
6115	* Cleans up the SVGA hardware state
6116	*
6117	* @returns VBox status code.
6118	* @param pDevIns The device instance.
6119	*/
6120	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6121	{
6122	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6123	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6124
6125	/*
6126	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6127	*/
6128	if (pThisCC->svga.pFIFOIOThread)
6129	{
6130	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6131	NULL /pvParam/, 30000 /ms/);
6132	AssertLogRelRC(rc);
6133
6134	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6135	AssertLogRelRC(rc);
6136	pThisCC->svga.pFIFOIOThread = NULL;
6137	}
6138
6139	/*
6140	* Destroy the special SVGA state.
6141	*/
6142	if (pThisCC->svga.pSvgaR3State)
6143	{
6144	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6145
6146	RTMemFree(pThisCC->svga.pSvgaR3State);
6147	pThisCC->svga.pSvgaR3State = NULL;
6148	}
6149
6150	/*
6151	* Free our resources residing in the VGA state.
6152	*/
6153	if (pThisCC->svga.pbVgaFrameBufferR3)
6154	{
6155	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6156	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6157	}
6158	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6159	{
6160	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6161	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6162	}
6163	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6164	{
6165	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6166	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6167	}
6168
6169	return VINF_SUCCESS;
6170	}
6171
6172	/**
6173	* Initialize the SVGA hardware state
6174	*
6175	* @returns VBox status code.
6176	* @param pDevIns The device instance.
6177	*/
6178	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6179	{
6180	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6181	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6182	PVMSVGAR3STATE pSVGAState;
6183	int rc;
6184
6185	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6186	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6187
6188	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6189
6190	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6191	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6192	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6193
6194	/* Create event semaphore. */
6195	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6196	AssertRCReturn(rc, rc);
6197
6198	/* Create event semaphore. */
6199	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6200	AssertRCReturn(rc, rc);
6201
6202	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6203	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6204
6205	rc = vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6206	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6207
6208	pSVGAState = pThisCC->svga.pSvgaR3State;
6209
6210	/* Initialize FIFO and register capabilities. */
6211	vmsvgaR3InitCaps(pThis, pThisCC);
6212
6213	# ifdef VBOX_WITH_VMSVGA3D
6214	if (pThis->svga.f3DEnabled)
6215	{
6216	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6217	if (RT_FAILURE(rc))
6218	{
6219	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6220	pThis->svga.f3DEnabled = false;
6221	}
6222	}
6223	# endif
6224	/* VRAM tracking is enabled by default during bootup. */
6225	pThis->svga.fVRAMTracking = true;
6226
6227	/* Invalidate current settings. */
6228	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6229	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6230	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6231	pThis->svga.cbScanline = 0;
6232
6233	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6234	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6235	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6236	{
6237	pThis->svga.u32MaxWidth -= 256;
6238	pThis->svga.u32MaxHeight -= 256;
6239	}
6240	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6241
6242	# ifdef DEBUG_GMR_ACCESS
6243	/* Register the GMR access handler type. */
6244	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6245	vmsvgaR3GmrAccessHandler,
6246	NULL, NULL, NULL,
6247	NULL, NULL, NULL,
6248	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6249	AssertRCReturn(rc, rc);
6250	# endif
6251
6252	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6253	/* Register the FIFO access handler type. In addition to
6254	debugging FIFO access, this is also used to facilitate
6255	extended fifo thread sleeps. */
6256	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6257	# ifdef DEBUG_FIFO_ACCESS
6258	PGMPHYSHANDLERKIND_ALL,
6259	# else
6260	PGMPHYSHANDLERKIND_WRITE,
6261	# endif
6262	vmsvgaR3FifoAccessHandler,
6263	NULL, NULL, NULL,
6264	NULL, NULL, NULL,
6265	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6266	AssertRCReturn(rc, rc);
6267	# endif
6268
6269	/* Create the async IO thread. */
6270	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6271	RTTHREADTYPE_IO, "VMSVGA FIFO");
6272	if (RT_FAILURE(rc))
6273	{
6274	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6275	return rc;
6276	}
6277
6278	/*
6279	* Statistics.
6280	*/
6281	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6282	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6283	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6284	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6285	# ifdef VBOX_WITH_STATISTICS
6286	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6287	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6288	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6289	# endif
6290	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6291	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6292	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6293	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6294	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6295	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6296	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6297	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6298	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6299	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6300	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6301	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6302	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6303	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6304	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6305	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6306	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6307	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6308	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6309	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6310	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6311	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6312	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6313	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6314	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6315	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6316	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6317	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6318	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6319	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6320	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6321	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6322	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6323	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6324	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6325	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6326	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6327	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6328	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6329	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6330	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6331	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6332	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6333	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6334	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6335	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6336	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6337	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6338	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6339	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6340	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6341	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6342	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6343	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6344
6345	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6346	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6347	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6348	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6349	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6350	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6351	REG_CNT(&pThis->svga.StatRegCursorXxxxWr, "VMSVGA/Reg/CursorXxxxWrite", "SVGA_REG_CURSOR_XXXX writes.");
6352	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6353	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6354	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6355	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6356	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6357	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6358	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6359	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6360	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6361	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6362	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6363	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6364	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6365	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6366	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6367	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6368	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6369	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6370	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6371	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6372	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6373	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6374	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6375	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6376	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6377
6378	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6379	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6380	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6381	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6382	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6383	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6384	REG_CNT(&pThis->svga.StatRegCursorXxxxRd, "VMSVGA/Reg/CursorXxxxRead", "SVGA_REG_CURSOR_XXXX reads.");
6385	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6386	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6387	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6388	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6389	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6390	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6391	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6392	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6393	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6394	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6395	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6396	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6397	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6398	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6399	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6400	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6401	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6402	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6403	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6404	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6405	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6406	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6407	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6408	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6409	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6410	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6411	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6412	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6413	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6414	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6415	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6416	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6417	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6418	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6419	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6420	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6421	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6422	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6423	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6424	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6425	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6426	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6427
6428	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6429	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6430	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6431	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6432	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6433	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6434	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6435	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6436	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6437	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6438	# endif
6439	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6440	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6441	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6442	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6443	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6444
6445	# undef REG_CNT
6446	# undef REG_PRF
6447
6448	/*
6449	* Info handlers.
6450	*/
6451	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6452	# ifdef VBOX_WITH_VMSVGA3D
6453	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6454	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6455	"VMSVGA 3d surface details. "
6456	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6457	vmsvgaR3Info3dSurface);
6458	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6459	"VMSVGA 3d surface details and bitmap: "
6460	"sid[>dir]",
6461	vmsvgaR3Info3dSurfaceBmp);
6462	# endif
6463
6464	return VINF_SUCCESS;
6465	}
6466
6467	/**
6468	* Power On notification.
6469	*
6470	* @returns VBox status code.
6471	* @param pDevIns The device instance data.
6472	*
6473	* @remarks Caller enters the device critical section.
6474	*/
6475	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6476	{
6477	# ifdef VBOX_WITH_VMSVGA3D
6478	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6479	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6480	if (pThis->svga.f3DEnabled)
6481	{
6482	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
6483
6484	if (RT_SUCCESS(rc))
6485	{
6486	/* Initialize FIFO 3D capabilities. */
6487	vmsvgaR3InitFifo3DCaps(pThisCC);
6488	}
6489	}
6490	# else /* !VBOX_WITH_VMSVGA3D */
6491	RT_NOREF(pDevIns);
6492	# endif /* !VBOX_WITH_VMSVGA3D */
6493	}
6494
6495	#endif /* IN_RING3 */
6496

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 82968

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