DevVGA-SVGA.cpp@ 70775

Last change on this file since 70775 was 69963, checked in by vboxsync, 7 years ago
Devices/Graphics: VMSVGA: renamed helpers for initialization and destruction of VMSVGAR3STATE structure.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 257.1 KB

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1	/* $Id: DevVGA-SVGA.cpp 69963 2017-12-06 21:30:46Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	*/
12
13	/*
14	* Copyright (C) 2013-2017 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.virtualbox.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25
26	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
27	*
28	* This device emulation was contributed by trivirt AG. It offers an
29	* alternative to our Bochs based VGA graphics and 3d emulations. This is
30	* valuable for Xorg based guests, as there is driver support shipping with Xorg
31	* since it forked from XFree86.
32	*
33	*
34	* @section sec_dev_vmsvga_sdk The VMware SDK
35	*
36	* This is officially deprecated now, however it's still quite useful,
37	* especially for getting the old features working:
38	* http://vmware-svga.sourceforge.net/
39	*
40	* They currently point developers at the following resources.
41	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
42	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
43	* - http://cgit.freedesktop.org/mesa/vmwgfx/
44	*
45	* @subsection subsec_dev_vmsvga_sdk_results Test results
46	*
47	* Test results:
48	* - 2dmark.img:
49	* + todo
50	* - backdoor-tclo.img:
51	* + todo
52	* - blit-cube.img:
53	* + todo
54	* - bunnies.img:
55	* + todo
56	* - cube.img:
57	* + todo
58	* - cubemark.img:
59	* + todo
60	* - dynamic-vertex-stress.img:
61	* + todo
62	* - dynamic-vertex.img:
63	* + todo
64	* - fence-stress.img:
65	* + todo
66	* - gmr-test.img:
67	* + todo
68	* - half-float-test.img:
69	* + todo
70	* - noscreen-cursor.img:
71	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
72	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
73	* visible though.)
74	* - Cursor animation via the palette doesn't work.
75	* - During debugging, it turns out that the framebuffer content seems to
76	* be halfways ignore or something (memset(fb, 0xcc, lots)).
77	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
78	* grow it 0x10 fold (128KB -> 2MB like in WS10).
79	* - null.img:
80	* + todo
81	* - pong.img:
82	* + todo
83	* - presentReadback.img:
84	* + todo
85	* - resolution-set.img:
86	* + todo
87	* - rt-gamma-test.img:
88	* + todo
89	* - screen-annotation.img:
90	* + todo
91	* - screen-cursor.img:
92	* + todo
93	* - screen-dma-coalesce.img:
94	* + todo
95	* - screen-gmr-discontig.img:
96	* + todo
97	* - screen-gmr-remap.img:
98	* + todo
99	* - screen-multimon.img:
100	* + todo
101	* - screen-present-clip.img:
102	* + todo
103	* - screen-render-test.img:
104	* + todo
105	* - screen-simple.img:
106	* + todo
107	* - screen-text.img:
108	* + todo
109	* - simple-shaders.img:
110	* + todo
111	* - simple_blit.img:
112	* + todo
113	* - tiny-2d-updates.img:
114	* + todo
115	* - video-formats.img:
116	* + todo
117	* - video-sync.img:
118	* + todo
119	*
120	*/
121
122
123	/*********************************************************************************************************************************
124	* Header Files *
125	*********************************************************************************************************************************/
126	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
127	#define VMSVGA_USE_EMT_HALT_CODE
128	#include <VBox/vmm/pdmdev.h>
129	#include <VBox/version.h>
130	#include <VBox/err.h>
131	#include <VBox/log.h>
132	#include <VBox/vmm/pgm.h>
133	#ifdef VMSVGA_USE_EMT_HALT_CODE
134	# include <VBox/vmm/vmapi.h>
135	# include <VBox/vmm/vmcpuset.h>
136	#endif
137	#include <VBox/sup.h>
138
139	#include <iprt/assert.h>
140	#include <iprt/semaphore.h>
141	#include <iprt/uuid.h>
142	#ifdef IN_RING3
143	# include <iprt/ctype.h>
144	# include <iprt/mem.h>
145	#endif
146
147	#include <VBox/VMMDev.h>
148	#include <VBoxVideo.h>
149	#include <VBox/bioslogo.h>
150
151	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
152	#include "DevVGA.h"
153
154	#include "DevVGA-SVGA.h"
155	#include "vmsvga/svga_reg.h"
156	#include "vmsvga/svga_escape.h"
157	#include "vmsvga/svga_overlay.h"
158	#include "vmsvga/svga3d_reg.h"
159	#include "vmsvga/svga3d_caps.h"
160	#ifdef VBOX_WITH_VMSVGA3D
161	# include "DevVGA-SVGA3d.h"
162	# ifdef RT_OS_DARWIN
163	# include "DevVGA-SVGA3d-cocoa.h"
164	# endif
165	#endif
166
167
168	/*********************************************************************************************************************************
169	* Defined Constants And Macros *
170	*********************************************************************************************************************************/
171	/**
172	* Macro for checking if a fixed FIFO register is valid according to the
173	* current FIFO configuration.
174	*
175	* @returns true / false.
176	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
177	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
178	*/
179	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
180
181
182	/*********************************************************************************************************************************
183	* Structures and Typedefs *
184	*********************************************************************************************************************************/
185	/**
186	* 64-bit GMR descriptor.
187	*/
188	typedef struct
189	{
190	RTGCPHYS GCPhys;
191	uint64_t numPages;
192	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
193
194	/**
195	* GMR slot
196	*/
197	typedef struct
198	{
199	uint32_t cMaxPages;
200	uint32_t cbTotal;
201	uint32_t numDescriptors;
202	PVMSVGAGMRDESCRIPTOR paDesc;
203	} GMR, *PGMR;
204
205	#ifdef IN_RING3
206	/**
207	* Internal SVGA ring-3 only state.
208	*/
209	typedef struct VMSVGAR3STATE
210	{
211	GMR *paGMR; // [VMSVGAState::cGMR]
212	struct
213	{
214	SVGAGuestPtr ptr;
215	uint32_t bytesPerLine;
216	SVGAGMRImageFormat format;
217	} GMRFB;
218	struct
219	{
220	bool fActive;
221	uint32_t xHotspot;
222	uint32_t yHotspot;
223	uint32_t width;
224	uint32_t height;
225	uint32_t cbData;
226	void *pData;
227	} Cursor;
228	SVGAColorBGRX colorAnnotation;
229
230	# ifdef VMSVGA_USE_EMT_HALT_CODE
231	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
232	uint32_t volatile cBusyDelayedEmts;
233	/** Set of EMTs that are */
234	VMCPUSET BusyDelayedEmts;
235	# else
236	/** Number of EMTs waiting on hBusyDelayedEmts. */
237	uint32_t volatile cBusyDelayedEmts;
238	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
239	* busy (ugly). */
240	RTSEMEVENTMULTI hBusyDelayedEmts;
241	# endif
242	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
243	STAMPROFILE StatBusyDelayEmts;
244
245	STAMPROFILE StatR3Cmd3dPresentProf;
246	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
247	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
248	STAMCOUNTER StatR3CmdDefineGmr2;
249	STAMCOUNTER StatR3CmdDefineGmr2Free;
250	STAMCOUNTER StatR3CmdDefineGmr2Modify;
251	STAMCOUNTER StatR3CmdRemapGmr2;
252	STAMCOUNTER StatR3CmdRemapGmr2Modify;
253	STAMCOUNTER StatR3CmdInvalidCmd;
254	STAMCOUNTER StatR3CmdFence;
255	STAMCOUNTER StatR3CmdUpdate;
256	STAMCOUNTER StatR3CmdUpdateVerbose;
257	STAMCOUNTER StatR3CmdDefineCursor;
258	STAMCOUNTER StatR3CmdDefineAlphaCursor;
259	STAMCOUNTER StatR3CmdEscape;
260	STAMCOUNTER StatR3CmdDefineScreen;
261	STAMCOUNTER StatR3CmdDestroyScreen;
262	STAMCOUNTER StatR3CmdDefineGmrFb;
263	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
264	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
265	STAMCOUNTER StatR3CmdAnnotationFill;
266	STAMCOUNTER StatR3CmdAnnotationCopy;
267	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
268	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
269	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
270	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
271	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
272	STAMCOUNTER StatR3Cmd3dSurfaceDma;
273	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
274	STAMCOUNTER StatR3Cmd3dContextDefine;
275	STAMCOUNTER StatR3Cmd3dContextDestroy;
276	STAMCOUNTER StatR3Cmd3dSetTransform;
277	STAMCOUNTER StatR3Cmd3dSetZRange;
278	STAMCOUNTER StatR3Cmd3dSetRenderState;
279	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
280	STAMCOUNTER StatR3Cmd3dSetTextureState;
281	STAMCOUNTER StatR3Cmd3dSetMaterial;
282	STAMCOUNTER StatR3Cmd3dSetLightData;
283	STAMCOUNTER StatR3Cmd3dSetLightEnable;
284	STAMCOUNTER StatR3Cmd3dSetViewPort;
285	STAMCOUNTER StatR3Cmd3dSetClipPlane;
286	STAMCOUNTER StatR3Cmd3dClear;
287	STAMCOUNTER StatR3Cmd3dPresent;
288	STAMCOUNTER StatR3Cmd3dPresentReadBack;
289	STAMCOUNTER StatR3Cmd3dShaderDefine;
290	STAMCOUNTER StatR3Cmd3dShaderDestroy;
291	STAMCOUNTER StatR3Cmd3dSetShader;
292	STAMCOUNTER StatR3Cmd3dSetShaderConst;
293	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
294	STAMCOUNTER StatR3Cmd3dSetScissorRect;
295	STAMCOUNTER StatR3Cmd3dBeginQuery;
296	STAMCOUNTER StatR3Cmd3dEndQuery;
297	STAMCOUNTER StatR3Cmd3dWaitForQuery;
298	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
299	STAMCOUNTER StatR3Cmd3dActivateSurface;
300	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
301
302	STAMCOUNTER StatR3RegConfigDoneWr;
303	STAMCOUNTER StatR3RegGmrDescriptorWr;
304	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
305	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
306
307	STAMCOUNTER StatFifoCommands;
308	STAMCOUNTER StatFifoErrors;
309	STAMCOUNTER StatFifoUnkCmds;
310	STAMCOUNTER StatFifoTodoTimeout;
311	STAMCOUNTER StatFifoTodoWoken;
312	STAMPROFILE StatFifoStalls;
313
314	} VMSVGAR3STATE, *PVMSVGAR3STATE;
315	#endif /* IN_RING3 */
316
317
318	/*********************************************************************************************************************************
319	* Internal Functions *
320	*********************************************************************************************************************************/
321	#ifdef IN_RING3
322	# ifdef DEBUG_FIFO_ACCESS
323	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
324	# endif
325	# ifdef DEBUG_GMR_ACCESS
326	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
327	# endif
328	#endif
329
330
331	/*********************************************************************************************************************************
332	* Global Variables *
333	*********************************************************************************************************************************/
334	#ifdef IN_RING3
335
336	/**
337	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
338	*/
339	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
340	{
341	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
342	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
343	SSMFIELD_ENTRY_TERM()
344	};
345
346	/**
347	* SSM descriptor table for the GMR structure.
348	*/
349	static SSMFIELD const g_aGMRFields[] =
350	{
351	SSMFIELD_ENTRY( GMR, cMaxPages),
352	SSMFIELD_ENTRY( GMR, cbTotal),
353	SSMFIELD_ENTRY( GMR, numDescriptors),
354	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
355	SSMFIELD_ENTRY_TERM()
356	};
357
358	/**
359	* SSM descriptor table for the VMSVGAR3STATE structure.
360	*/
361	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
362	{
363	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
364	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
365	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
366	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
367	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
368	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
369	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
370	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
371	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
372	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
373	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
374	#ifdef VMSVGA_USE_EMT_HALT_CODE
375	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
376	#else
377	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
378	#endif
379	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
380	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
381	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
382	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
383	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
384	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
385	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
386	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
387	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
388	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
389	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
390	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
391	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
392	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
393	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
394	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
395	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
396	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
397	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
398	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
399	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
400	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
401	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
402	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
403	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
404	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
405	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
406	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
408	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
409	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
410	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
412	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
436
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
441
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
448	SSMFIELD_ENTRY_TERM()
449	};
450
451	/**
452	* SSM descriptor table for the VGAState.svga structure.
453	*/
454	static SSMFIELD const g_aVGAStateSVGAFields[] =
455	{
456	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u64HostWindowId),
457	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
458	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
459	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
460	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
461	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
462	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
463	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
466	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
467	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
468	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
469	SSMFIELD_ENTRY( VMSVGAState, fBusy),
470	SSMFIELD_ENTRY( VMSVGAState, fTraces),
471	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
472	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
473	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
474	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
475	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
476	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
477	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
478	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
480	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
483	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
484	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
485	SSMFIELD_ENTRY( VMSVGAState, uWidth),
486	SSMFIELD_ENTRY( VMSVGAState, uHeight),
487	SSMFIELD_ENTRY( VMSVGAState, uBpp),
488	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
489	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
490	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastScreenOffset), /* VGA_SAVEDSTATE_VERSION_VMSVGA */
491	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
492	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
493	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
494	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
495	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
496	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
497	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
498	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
499	SSMFIELD_ENTRY_TERM()
500	};
501
502	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
503
504	#endif /* IN_RING3 */
505
506	#ifdef LOG_ENABLED
507
508	/**
509	* Index register string name lookup
510	*
511	* @returns Index register string or "UNKNOWN"
512	* @param pThis VMSVGA State
513	* @param idxReg The index register.
514	*/
515	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
516	{
517	switch (idxReg)
518	{
519	case SVGA_REG_ID: return "SVGA_REG_ID";
520	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
521	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
522	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
523	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
524	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
525	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
526	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
527	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
528	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
529	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
530	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
531	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
532	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
533	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
534	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
535	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
536	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
537	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
538	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
539	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
540	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
541	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
542	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
543	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
544	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
545	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
546	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
547	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
548	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
549	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
550	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
551	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
552	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
553	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
554	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
555	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
556	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
557	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
558	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
559	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
560	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
561	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
562	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
563	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
564	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
565	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
566	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
567	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
568	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
569
570	default:
571	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
572	return "SVGA_SCRATCH_BASE reg";
573	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
574	return "SVGA_PALETTE_BASE reg";
575	return "UNKNOWN";
576	}
577	}
578
579	#ifdef IN_RING3
580	/**
581	* FIFO command name lookup
582	*
583	* @returns FIFO command string or "UNKNOWN"
584	* @param u32Cmd FIFO command
585	*/
586	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
587	{
588	switch (u32Cmd)
589	{
590	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
591	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
592	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
593	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
594	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
595	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
596	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
597	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
598	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
599	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
600	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
601	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
602	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
603	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
604	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
605	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
606	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
607	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
608	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
609	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
610	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
611	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
612	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
613	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
614	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
615	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
616	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
617	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
618	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
619	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
620	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
621	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
622	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
623	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
624	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
625	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
626	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
627	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
628	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
629	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
630	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
631	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
632	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
633	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
634	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
635	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
636	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
637	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
638	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
639	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
640	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
641	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
642	default: return "UNKNOWN";
643	}
644	}
645	# endif /* IN_RING3 */
646
647	#endif /* LOG_ENABLED */
648
649	#ifdef IN_RING3
650	/**
651	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
652	*/
653	DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
654	{
655	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
656
657	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
658	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
659
660	if (x < pThis->svga.uWidth)
661	{
662	pThis->svga.viewport.x = x;
663	pThis->svga.viewport.cx = RT_MIN(cx, pThis->svga.uWidth - x);
664	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
665	}
666	else
667	{
668	pThis->svga.viewport.x = pThis->svga.uWidth;
669	pThis->svga.viewport.cx = 0;
670	pThis->svga.viewport.xRight = pThis->svga.uWidth;
671	}
672	if (y < pThis->svga.uHeight)
673	{
674	pThis->svga.viewport.y = y;
675	pThis->svga.viewport.cy = RT_MIN(cy, pThis->svga.uHeight - y);
676	pThis->svga.viewport.yLowWC = pThis->svga.uHeight - y - pThis->svga.viewport.cy;
677	pThis->svga.viewport.yHighWC = pThis->svga.uHeight - y;
678	}
679	else
680	{
681	pThis->svga.viewport.y = pThis->svga.uHeight;
682	pThis->svga.viewport.cy = 0;
683	pThis->svga.viewport.yLowWC = 0;
684	pThis->svga.viewport.yHighWC = 0;
685	}
686
687	# ifdef VBOX_WITH_VMSVGA3D
688	/*
689	* Now inform the 3D backend.
690	*/
691	if (pThis->svga.f3DEnabled)
692	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
693	# else
694	RT_NOREF(idScreen, OldViewport);
695	# endif
696	}
697	#endif /* IN_RING3 */
698
699	/**
700	* Read port register
701	*
702	* @returns VBox status code.
703	* @param pThis VMSVGA State
704	* @param pu32 Where to store the read value
705	*/
706	PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
707	{
708	int rc = VINF_SUCCESS;
709	*pu32 = 0;
710
711	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
712	uint32_t idxReg = pThis->svga.u32IndexReg;
713	if ( idxReg >= SVGA_REG_CAPABILITIES
714	&& pThis->svga.u32SVGAId == SVGA_ID_0)
715	{
716	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
717	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
718	}
719
720	switch (idxReg)
721	{
722	case SVGA_REG_ID:
723	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
724	*pu32 = pThis->svga.u32SVGAId;
725	break;
726
727	case SVGA_REG_ENABLE:
728	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
729	*pu32 = pThis->svga.fEnabled;
730	break;
731
732	case SVGA_REG_WIDTH:
733	{
734	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
735	if ( pThis->svga.fEnabled
736	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
737	{
738	*pu32 = pThis->svga.uWidth;
739	}
740	else
741	{
742	#ifndef IN_RING3
743	rc = VINF_IOM_R3_IOPORT_READ;
744	#else
745	*pu32 = pThis->pDrv->cx;
746	#endif
747	}
748	break;
749	}
750
751	case SVGA_REG_HEIGHT:
752	{
753	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
754	if ( pThis->svga.fEnabled
755	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
756	{
757	*pu32 = pThis->svga.uHeight;
758	}
759	else
760	{
761	#ifndef IN_RING3
762	rc = VINF_IOM_R3_IOPORT_READ;
763	#else
764	*pu32 = pThis->pDrv->cy;
765	#endif
766	}
767	break;
768	}
769
770	case SVGA_REG_MAX_WIDTH:
771	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
772	*pu32 = pThis->svga.u32MaxWidth;
773	break;
774
775	case SVGA_REG_MAX_HEIGHT:
776	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
777	*pu32 = pThis->svga.u32MaxHeight;
778	break;
779
780	case SVGA_REG_DEPTH:
781	/* This returns the color depth of the current mode. */
782	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
783	switch (pThis->svga.uBpp)
784	{
785	case 15:
786	case 16:
787	case 24:
788	*pu32 = pThis->svga.uBpp;
789	break;
790
791	default:
792	case 32:
793	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
794	break;
795	}
796	break;
797
798	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
799	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
800	if ( pThis->svga.fEnabled
801	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
802	{
803	*pu32 = pThis->svga.uBpp;
804	}
805	else
806	{
807	#ifndef IN_RING3
808	rc = VINF_IOM_R3_IOPORT_READ;
809	#else
810	*pu32 = pThis->pDrv->cBits;
811	#endif
812	}
813	break;
814
815	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
816	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
817	if ( pThis->svga.fEnabled
818	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
819	{
820	*pu32 = (pThis->svga.uBpp + 7) & ~7;
821	}
822	else
823	{
824	#ifndef IN_RING3
825	rc = VINF_IOM_R3_IOPORT_READ;
826	#else
827	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
828	#endif
829	}
830	break;
831
832	case SVGA_REG_PSEUDOCOLOR:
833	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
834	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
835	break;
836
837	case SVGA_REG_RED_MASK:
838	case SVGA_REG_GREEN_MASK:
839	case SVGA_REG_BLUE_MASK:
840	{
841	uint32_t uBpp;
842
843	if ( pThis->svga.fEnabled
844	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
845	{
846	uBpp = pThis->svga.uBpp;
847	}
848	else
849	{
850	#ifndef IN_RING3
851	rc = VINF_IOM_R3_IOPORT_READ;
852	break;
853	#else
854	uBpp = pThis->pDrv->cBits;
855	#endif
856	}
857	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
858	switch (uBpp)
859	{
860	case 8:
861	u32RedMask = 0x07;
862	u32GreenMask = 0x38;
863	u32BlueMask = 0xc0;
864	break;
865
866	case 15:
867	u32RedMask = 0x0000001f;
868	u32GreenMask = 0x000003e0;
869	u32BlueMask = 0x00007c00;
870	break;
871
872	case 16:
873	u32RedMask = 0x0000001f;
874	u32GreenMask = 0x000007e0;
875	u32BlueMask = 0x0000f800;
876	break;
877
878	case 24:
879	case 32:
880	default:
881	u32RedMask = 0x00ff0000;
882	u32GreenMask = 0x0000ff00;
883	u32BlueMask = 0x000000ff;
884	break;
885	}
886	switch (idxReg)
887	{
888	case SVGA_REG_RED_MASK:
889	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
890	*pu32 = u32RedMask;
891	break;
892
893	case SVGA_REG_GREEN_MASK:
894	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
895	*pu32 = u32GreenMask;
896	break;
897
898	case SVGA_REG_BLUE_MASK:
899	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
900	*pu32 = u32BlueMask;
901	break;
902	}
903	break;
904	}
905
906	case SVGA_REG_BYTES_PER_LINE:
907	{
908	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
909	if ( pThis->svga.fEnabled
910	&& pThis->svga.cbScanline)
911	{
912	*pu32 = pThis->svga.cbScanline;
913	}
914	else
915	{
916	#ifndef IN_RING3
917	rc = VINF_IOM_R3_IOPORT_READ;
918	#else
919	*pu32 = pThis->pDrv->cbScanline;
920	#endif
921	}
922	break;
923	}
924
925	case SVGA_REG_VRAM_SIZE: /* VRAM size */
926	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
927	*pu32 = pThis->vram_size;
928	break;
929
930	case SVGA_REG_FB_START: /* Frame buffer physical address. */
931	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
932	Assert(pThis->GCPhysVRAM <= 0xffffffff);
933	*pu32 = pThis->GCPhysVRAM;
934	break;
935
936	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
937	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
938	/* Always zero in our case. */
939	*pu32 = 0;
940	break;
941
942	case SVGA_REG_FB_SIZE: /* Frame buffer size */
943	{
944	#ifndef IN_RING3
945	rc = VINF_IOM_R3_IOPORT_READ;
946	#else
947	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
948
949	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
950	if ( pThis->svga.fEnabled
951	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
952	{
953	/* Hardware enabled; return real framebuffer size .*/
954	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
955	}
956	else
957	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
958
959	pu32 = RT_MIN(pThis->vram_size, pu32);
960	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
961	#endif
962	break;
963	}
964
965	case SVGA_REG_CAPABILITIES:
966	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
967	*pu32 = pThis->svga.u32RegCaps;
968	break;
969
970	case SVGA_REG_MEM_START: /* FIFO start */
971	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
972	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
973	*pu32 = pThis->svga.GCPhysFIFO;
974	break;
975
976	case SVGA_REG_MEM_SIZE: /* FIFO size */
977	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
978	*pu32 = pThis->svga.cbFIFO;
979	break;
980
981	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
982	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
983	*pu32 = pThis->svga.fConfigured;
984	break;
985
986	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
987	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
988	*pu32 = 0;
989	break;
990
991	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
992	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
993	if (pThis->svga.fBusy)
994	{
995	#ifndef IN_RING3
996	/* Go to ring-3 and halt the CPU. */
997	rc = VINF_IOM_R3_IOPORT_READ;
998	break;
999	#else
1000	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1001	/* The guest is basically doing a HLT via the device here, but with
1002	a special wake up condition on FIFO completion. */
1003	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1004	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1005	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1006	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1007	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1008	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1009	if (pThis->svga.fBusy)
1010	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1011	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1012	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1013	# else
1014
1015	/* Delay the EMT a bit so the FIFO and others can get some work done.
1016	This used to be a crude 50 ms sleep. The current code tries to be
1017	more efficient, but the consept is still very crude. */
1018	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1019	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1020	RTThreadYield();
1021	if (pThis->svga.fBusy)
1022	{
1023	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1024
1025	if (pThis->svga.fBusy && cRefs == 1)
1026	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1027	if (pThis->svga.fBusy)
1028	{
1029	/** @todo If this code is going to stay, we need to call into the halt/wait
1030	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1031	* suffer when the guest is polling on a busy FIFO. */
1032	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1033	if (cNsMaxWait >= RT_NS_100US)
1034	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1035	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1036	RT_MIN(cNsMaxWait, RT_NS_10MS));
1037	}
1038
1039	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1040	}
1041	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1042	# endif
1043	*pu32 = pThis->svga.fBusy != 0;
1044	#endif
1045	}
1046	else
1047	*pu32 = false;
1048	break;
1049
1050	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1051	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1052	*pu32 = pThis->svga.u32GuestId;
1053	break;
1054
1055	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1056	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1057	*pu32 = pThis->svga.cScratchRegion;
1058	break;
1059
1060	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1061	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1062	*pu32 = SVGA_FIFO_NUM_REGS;
1063	break;
1064
1065	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1066	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1067	*pu32 = pThis->svga.u32PitchLock;
1068	break;
1069
1070	case SVGA_REG_IRQMASK: /* Interrupt mask */
1071	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1072	*pu32 = pThis->svga.u32IrqMask;
1073	break;
1074
1075	/* See "Guest memory regions" below. */
1076	case SVGA_REG_GMR_ID:
1077	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1078	*pu32 = pThis->svga.u32CurrentGMRId;
1079	break;
1080
1081	case SVGA_REG_GMR_DESCRIPTOR:
1082	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1083	/* Write only */
1084	*pu32 = 0;
1085	break;
1086
1087	case SVGA_REG_GMR_MAX_IDS:
1088	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1089	*pu32 = pThis->svga.cGMR;
1090	break;
1091
1092	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1093	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1094	*pu32 = VMSVGA_MAX_GMR_PAGES;
1095	break;
1096
1097	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1098	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1099	*pu32 = pThis->svga.fTraces;
1100	break;
1101
1102	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1103	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1104	*pu32 = VMSVGA_MAX_GMR_PAGES;
1105	break;
1106
1107	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1108	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1109	*pu32 = VMSVGA_SURFACE_SIZE;
1110	break;
1111
1112	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1113	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1114	break;
1115
1116	/* Mouse cursor support. */
1117	case SVGA_REG_CURSOR_ID:
1118	case SVGA_REG_CURSOR_X:
1119	case SVGA_REG_CURSOR_Y:
1120	case SVGA_REG_CURSOR_ON:
1121	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1122	break;
1123
1124	/* Legacy multi-monitor support */
1125	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1126	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1127	*pu32 = 1;
1128	break;
1129
1130	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1131	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1132	*pu32 = 0;
1133	break;
1134
1135	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1136	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1137	*pu32 = 0;
1138	break;
1139
1140	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1141	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1142	*pu32 = 0;
1143	break;
1144
1145	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1146	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1147	*pu32 = 0;
1148	break;
1149
1150	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1151	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1152	*pu32 = pThis->svga.uWidth;
1153	break;
1154
1155	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1156	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1157	*pu32 = pThis->svga.uHeight;
1158	break;
1159
1160	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1161	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1162	pu32 = 1; / Must return something sensible here otherwise the Linux driver will take a legacy code path without 3d support. */
1163	break;
1164
1165	default:
1166	{
1167	uint32_t offReg;
1168	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1169	{
1170	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1171	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1172	}
1173	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1174	{
1175	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1176	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1177	uint32_t u32 = pThis->last_palette[offReg / 3];
1178	switch (offReg % 3)
1179	{
1180	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1181	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1182	case 2: pu32 = u32 & 0xff; break; / blue */
1183	}
1184	}
1185	else
1186	{
1187	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1188	rc = VINF_IOM_R3_IOPORT_READ;
1189	#else
1190	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1191	# ifndef DEBUG_sunlover
1192	AssertMsgFailed(("reg=%#x\n", idxReg));
1193	# endif
1194	#endif
1195	}
1196	break;
1197	}
1198	}
1199	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1200	return rc;
1201	}
1202
1203	#ifdef IN_RING3
1204	/**
1205	* Apply the current resolution settings to change the video mode.
1206	*
1207	* @returns VBox status code.
1208	* @param pThis VMSVGA State
1209	*/
1210	int vmsvgaChangeMode(PVGASTATE pThis)
1211	{
1212	int rc;
1213
1214	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1215	\|\| pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1216	\|\| pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1217	{
1218	/* Mode change in progress; wait for all values to be set. */
1219	Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1220	return VINF_SUCCESS;
1221	}
1222
1223	if ( pThis->svga.uWidth == 0
1224	\|\| pThis->svga.uHeight == 0
1225	\|\| pThis->svga.uBpp == 0)
1226	{
1227	/* Invalid mode change - BB does this early in the boot up. */
1228	Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1229	return VINF_SUCCESS;
1230	}
1231
1232	if ( pThis->last_bpp == (unsigned)pThis->svga.uBpp
1233	&& pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1234	&& pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1235	&& pThis->last_width == (unsigned)pThis->svga.uWidth
1236	&& pThis->last_height == (unsigned)pThis->svga.uHeight
1237	&& pThis->svga.uLastScreenOffset == pThis->svga.uScreenOffset
1238	)
1239	{
1240	/* Nothing to do. */
1241	Log(("vmsvgaChangeMode: nothing changed; ignore\n"));
1242	return VINF_SUCCESS;
1243	}
1244
1245	LogFunc(("Enable LFB mode and resize to (%d,%d) bpp=%d uScreenOffset 0x%x\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp, pThis->svga.uScreenOffset));
1246	pThis->svga.cbScanline = ((pThis->svga.uWidth * pThis->svga.uBpp + 7) & ~7) / 8;
1247
1248	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1249
1250	VBVAINFOVIEW view;
1251	view.u32ViewIndex = 0;
1252	view.u32ViewOffset = 0;
1253	view.u32ViewSize = pThis->vram_size;
1254	view.u32MaxScreenSize = pThis->vram_size;
1255
1256	VBVAINFOSCREEN screen;
1257	screen.u32ViewIndex = 0;
1258	screen.i32OriginX = 0;
1259	screen.i32OriginY = 0;
1260	screen.u32StartOffset = pThis->svga.uScreenOffset;
1261	screen.u32LineSize = pThis->svga.cbScanline;
1262	screen.u32Width = pThis->svga.uWidth;
1263	screen.u32Height = pThis->svga.uHeight;
1264	screen.u16BitsPerPixel = pThis->svga.uBpp;
1265	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1266
1267	rc = pThis->pDrv->pfnVBVAResize(pThis->pDrv, &view, &screen, pThis->CTX_SUFF(vram_ptr), /fResetInputMapping=/ true);
1268	AssertRC(rc);
1269	AssertReturn(rc == VINF_SUCCESS \|\| rc == VINF_VGA_RESIZE_IN_PROGRESS, rc);
1270
1271	/* last stuff */
1272	pThis->last_bpp = pThis->svga.uBpp;
1273	pThis->last_scr_width = pThis->svga.uWidth;
1274	pThis->last_scr_height = pThis->svga.uHeight;
1275	pThis->last_width = pThis->svga.uWidth;
1276	pThis->last_height = pThis->svga.uHeight;
1277	pThis->svga.uLastScreenOffset = pThis->svga.uScreenOffset;
1278
1279	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1280
1281	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1282	if ( pThis->svga.viewport.cx == 0
1283	&& pThis->svga.viewport.cy == 0)
1284	{
1285	pThis->svga.viewport.cx = pThis->svga.uWidth;
1286	pThis->svga.viewport.xRight = pThis->svga.uWidth;
1287	pThis->svga.viewport.cy = pThis->svga.uHeight;
1288	pThis->svga.viewport.yHighWC = pThis->svga.uHeight;
1289	pThis->svga.viewport.yLowWC = 0;
1290	}
1291	return VINF_SUCCESS;
1292	}
1293	#endif /* IN_RING3 */
1294
1295	#if defined(IN_RING0) \|\| defined(IN_RING3)
1296	/**
1297	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1298	*
1299	* @param pThis The VMSVGA state.
1300	* @param fState The busy state.
1301	*/
1302	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1303	{
1304	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1305
1306	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1307	{
1308	/* Race / unfortunately scheduling. Highly unlikly. */
1309	uint32_t cLoops = 64;
1310	do
1311	{
1312	ASMNopPause();
1313	fState = (pThis->svga.fBusy != 0);
1314	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1315	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1316	}
1317	}
1318	#endif
1319
1320	/**
1321	* Write port register
1322	*
1323	* @returns VBox status code.
1324	* @param pThis VMSVGA State
1325	* @param u32 Value to write
1326	*/
1327	PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1328	{
1329	#ifdef IN_RING3
1330	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1331	#endif
1332	int rc = VINF_SUCCESS;
1333
1334	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1335	uint32_t idxReg = pThis->svga.u32IndexReg;
1336	if ( idxReg >= SVGA_REG_CAPABILITIES
1337	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1338	{
1339	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1340	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1341	}
1342	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1343	switch (idxReg)
1344	{
1345	case SVGA_REG_ID:
1346	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1347	if ( u32 == SVGA_ID_0
1348	\|\| u32 == SVGA_ID_1
1349	\|\| u32 == SVGA_ID_2)
1350	pThis->svga.u32SVGAId = u32;
1351	else
1352	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1353	break;
1354
1355	case SVGA_REG_ENABLE:
1356	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1357	if ( pThis->svga.fEnabled == u32
1358	&& pThis->last_bpp == (unsigned)pThis->svga.uBpp
1359	&& pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1360	&& pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1361	&& pThis->last_width == (unsigned)pThis->svga.uWidth
1362	&& pThis->last_height == (unsigned)pThis->svga.uHeight
1363	)
1364	/* Nothing to do. */
1365	break;
1366
1367	#ifdef IN_RING3
1368	if ( u32 == 1
1369	&& pThis->svga.fEnabled == false)
1370	{
1371	/* Make a backup copy of the first 512kb in order to save font data etc. */
1372	/** @todo should probably swap here, rather than copy + zero */
1373	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1374	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1375	}
1376
1377	pThis->svga.fEnabled = u32;
1378	if (pThis->svga.fEnabled)
1379	{
1380	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1381	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1382	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1383	{
1384	/* Keep the current mode. */
1385	pThis->svga.uWidth = pThis->pDrv->cx;
1386	pThis->svga.uHeight = pThis->pDrv->cy;
1387	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1388	}
1389
1390	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1391	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1392	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1393	{
1394	rc = vmsvgaChangeMode(pThis);
1395	AssertRCReturn(rc, rc);
1396	}
1397	# ifdef LOG_ENABLED
1398	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
1399	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1400	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1401	# endif
1402
1403	/* Disable or enable dirty page tracking according to the current fTraces value. */
1404	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1405	}
1406	else
1407	{
1408	/* Restore the text mode backup. */
1409	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1410
1411	/* pThis->svga.uHeight = -1;
1412	pThis->svga.uWidth = -1;
1413	pThis->svga.uBpp = -1;
1414	pThis->svga.cbScanline = 0; */
1415	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1416
1417	/* Enable dirty page tracking again when going into legacy mode. */
1418	vmsvgaSetTraces(pThis, true);
1419	}
1420	#else /* !IN_RING3 */
1421	rc = VINF_IOM_R3_IOPORT_WRITE;
1422	#endif /* !IN_RING3 */
1423	break;
1424
1425	case SVGA_REG_WIDTH:
1426	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1427	if (pThis->svga.uWidth != u32)
1428	{
1429	if (pThis->svga.fEnabled)
1430	{
1431	#ifdef IN_RING3
1432	pThis->svga.uWidth = u32;
1433	rc = vmsvgaChangeMode(pThis);
1434	AssertRCReturn(rc, rc);
1435	#else
1436	rc = VINF_IOM_R3_IOPORT_WRITE;
1437	#endif
1438	}
1439	else
1440	pThis->svga.uWidth = u32;
1441	}
1442	/* else: nop */
1443	break;
1444
1445	case SVGA_REG_HEIGHT:
1446	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1447	if (pThis->svga.uHeight != u32)
1448	{
1449	if (pThis->svga.fEnabled)
1450	{
1451	#ifdef IN_RING3
1452	pThis->svga.uHeight = u32;
1453	rc = vmsvgaChangeMode(pThis);
1454	AssertRCReturn(rc, rc);
1455	#else
1456	rc = VINF_IOM_R3_IOPORT_WRITE;
1457	#endif
1458	}
1459	else
1460	pThis->svga.uHeight = u32;
1461	}
1462	/* else: nop */
1463	break;
1464
1465	case SVGA_REG_DEPTH:
1466	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1467	/** @todo read-only?? */
1468	break;
1469
1470	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1471	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1472	if (pThis->svga.uBpp != u32)
1473	{
1474	if (pThis->svga.fEnabled)
1475	{
1476	#ifdef IN_RING3
1477	pThis->svga.uBpp = u32;
1478	rc = vmsvgaChangeMode(pThis);
1479	AssertRCReturn(rc, rc);
1480	#else
1481	rc = VINF_IOM_R3_IOPORT_WRITE;
1482	#endif
1483	}
1484	else
1485	pThis->svga.uBpp = u32;
1486	}
1487	/* else: nop */
1488	break;
1489
1490	case SVGA_REG_PSEUDOCOLOR:
1491	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1492	break;
1493
1494	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1495	#ifdef IN_RING3
1496	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1497	pThis->svga.fConfigured = u32;
1498	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1499	if (!pThis->svga.fConfigured)
1500	{
1501	pThis->svga.fTraces = true;
1502	}
1503	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1504	#else
1505	rc = VINF_IOM_R3_IOPORT_WRITE;
1506	#endif
1507	break;
1508
1509	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1510	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1511	if ( pThis->svga.fEnabled
1512	&& pThis->svga.fConfigured)
1513	{
1514	#if defined(IN_RING3) \|\| defined(IN_RING0)
1515	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1516	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1517	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1518	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1519
1520	/* Kick the FIFO thread to start processing commands again. */
1521	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1522	#else
1523	rc = VINF_IOM_R3_IOPORT_WRITE;
1524	#endif
1525	}
1526	/* else nothing to do. */
1527	else
1528	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1529
1530	break;
1531
1532	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1533	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1534	break;
1535
1536	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1537	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1538	pThis->svga.u32GuestId = u32;
1539	break;
1540
1541	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1542	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1543	pThis->svga.u32PitchLock = u32;
1544	break;
1545
1546	case SVGA_REG_IRQMASK: /* Interrupt mask */
1547	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1548	pThis->svga.u32IrqMask = u32;
1549
1550	/* Irq pending after the above change? */
1551	if (pThis->svga.u32IrqStatus & u32)
1552	{
1553	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1554	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1555	}
1556	else
1557	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1558	break;
1559
1560	/* Mouse cursor support */
1561	case SVGA_REG_CURSOR_ID:
1562	case SVGA_REG_CURSOR_X:
1563	case SVGA_REG_CURSOR_Y:
1564	case SVGA_REG_CURSOR_ON:
1565	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1566	break;
1567
1568	/* Legacy multi-monitor support */
1569	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1570	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1571	break;
1572	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1573	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1574	break;
1575	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1576	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1577	break;
1578	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1579	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1580	break;
1581	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1582	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1583	break;
1584	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1585	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1586	break;
1587	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1588	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1589	break;
1590	#ifdef VBOX_WITH_VMSVGA3D
1591	/* See "Guest memory regions" below. */
1592	case SVGA_REG_GMR_ID:
1593	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1594	pThis->svga.u32CurrentGMRId = u32;
1595	break;
1596
1597	case SVGA_REG_GMR_DESCRIPTOR:
1598	# ifndef IN_RING3
1599	rc = VINF_IOM_R3_IOPORT_WRITE;
1600	break;
1601	# else /* IN_RING3 */
1602	{
1603	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1604
1605	/* Validate current GMR id. */
1606	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1607	AssertBreak(idGMR < pThis->svga.cGMR);
1608
1609	/* Free the old GMR if present. */
1610	vmsvgaGMRFree(pThis, idGMR);
1611
1612	/* Just undefine the GMR? */
1613	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1614	if (GCPhys == 0)
1615	{
1616	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1617	break;
1618	}
1619
1620
1621	/* Never cross a page boundary automatically. */
1622	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1623	uint32_t cPagesTotal = 0;
1624	uint32_t iDesc = 0;
1625	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1626	uint32_t cLoops = 0;
1627	RTGCPHYS GCPhysBase = GCPhys;
1628	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1629	{
1630	/* Read descriptor. */
1631	SVGAGuestMemDescriptor desc;
1632	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1633	AssertRCBreak(rc);
1634
1635	if (desc.numPages != 0)
1636	{
1637	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1638	cPagesTotal += desc.numPages;
1639	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1640
1641	if ((iDesc & 15) == 0)
1642	{
1643	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1644	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1645	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1646	}
1647
1648	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1649	paDescs[iDesc++].numPages = desc.numPages;
1650
1651	/* Continue with the next descriptor. */
1652	GCPhys += sizeof(desc);
1653	}
1654	else if (desc.ppn == 0)
1655	break; /* terminator */
1656	else /* Pointer to the next physical page of descriptors. */
1657	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1658
1659	cLoops++;
1660	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1661	}
1662
1663	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1664	if (RT_SUCCESS(rc))
1665	{
1666	/* Commit the GMR. */
1667	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1668	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1669	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1670	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1671	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1672	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1673	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1674	}
1675	else
1676	{
1677	RTMemFree(paDescs);
1678	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1679	}
1680	break;
1681	}
1682	# endif /* IN_RING3 */
1683	#endif // VBOX_WITH_VMSVGA3D
1684
1685	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1686	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1687	if (pThis->svga.fTraces == u32)
1688	break; /* nothing to do */
1689
1690	#ifdef IN_RING3
1691	vmsvgaSetTraces(pThis, !!u32);
1692	#else
1693	rc = VINF_IOM_R3_IOPORT_WRITE;
1694	#endif
1695	break;
1696
1697	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1698	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1699	break;
1700
1701	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1702	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1703	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1704	break;
1705
1706	case SVGA_REG_FB_START:
1707	case SVGA_REG_MEM_START:
1708	case SVGA_REG_HOST_BITS_PER_PIXEL:
1709	case SVGA_REG_MAX_WIDTH:
1710	case SVGA_REG_MAX_HEIGHT:
1711	case SVGA_REG_VRAM_SIZE:
1712	case SVGA_REG_FB_SIZE:
1713	case SVGA_REG_CAPABILITIES:
1714	case SVGA_REG_MEM_SIZE:
1715	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1716	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1717	case SVGA_REG_BYTES_PER_LINE:
1718	case SVGA_REG_FB_OFFSET:
1719	case SVGA_REG_RED_MASK:
1720	case SVGA_REG_GREEN_MASK:
1721	case SVGA_REG_BLUE_MASK:
1722	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1723	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1724	case SVGA_REG_GMR_MAX_IDS:
1725	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1726	/* Read only - ignore. */
1727	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1728	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1729	break;
1730
1731	default:
1732	{
1733	uint32_t offReg;
1734	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1735	{
1736	pThis->svga.au32ScratchRegion[offReg] = u32;
1737	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1738	}
1739	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1740	{
1741	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1742	Btw, see rgb_to_pixel32. */
1743	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1744	u32 &= 0xff;
1745	uint32_t uRgb = pThis->last_palette[offReg / 3];
1746	switch (offReg % 3)
1747	{
1748	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1749	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1750	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1751	}
1752	pThis->last_palette[offReg / 3] = uRgb;
1753	}
1754	else
1755	{
1756	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1757	rc = VINF_IOM_R3_IOPORT_WRITE;
1758	#else
1759	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1760	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1761	#endif
1762	}
1763	break;
1764	}
1765	}
1766	return rc;
1767	}
1768
1769	/**
1770	* Port I/O Handler for IN operations.
1771	*
1772	* @returns VINF_SUCCESS or VINF_EM_*.
1773	* @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1774	*
1775	* @param pDevIns The device instance.
1776	* @param pvUser User argument.
1777	* @param uPort Port number used for the IN operation.
1778	* @param pu32 Where to store the result. This is always a 32-bit
1779	* variable regardless of what @a cb might say.
1780	* @param cb Number of bytes read.
1781	*/
1782	PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
1783	{
1784	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1785	RT_NOREF_PV(pvUser);
1786
1787	/* Ignore non-dword accesses. */
1788	if (cb != 4)
1789	{
1790	Log(("Ignoring non-dword read at %x cb=%d\n", uPort, cb));
1791	*pu32 = UINT32_MAX;
1792	return VINF_SUCCESS;
1793	}
1794
1795	switch (uPort - pThis->svga.BasePort)
1796	{
1797	case SVGA_INDEX_PORT:
1798	*pu32 = pThis->svga.u32IndexReg;
1799	break;
1800
1801	case SVGA_VALUE_PORT:
1802	return vmsvgaReadPort(pThis, pu32);
1803
1804	case SVGA_BIOS_PORT:
1805	Log(("Ignoring BIOS port read\n"));
1806	*pu32 = 0;
1807	break;
1808
1809	case SVGA_IRQSTATUS_PORT:
1810	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1811	*pu32 = pThis->svga.u32IrqStatus;
1812	break;
1813	}
1814
1815	return VINF_SUCCESS;
1816	}
1817
1818	/**
1819	* Port I/O Handler for OUT operations.
1820	*
1821	* @returns VINF_SUCCESS or VINF_EM_*.
1822	*
1823	* @param pDevIns The device instance.
1824	* @param pvUser User argument.
1825	* @param uPort Port number used for the OUT operation.
1826	* @param u32 The value to output.
1827	* @param cb The value size in bytes.
1828	*/
1829	PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
1830	{
1831	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1832	RT_NOREF_PV(pvUser);
1833
1834	/* Ignore non-dword accesses. */
1835	if (cb != 4)
1836	{
1837	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", uPort, u32, cb));
1838	return VINF_SUCCESS;
1839	}
1840
1841	switch (uPort - pThis->svga.BasePort)
1842	{
1843	case SVGA_INDEX_PORT:
1844	pThis->svga.u32IndexReg = u32;
1845	break;
1846
1847	case SVGA_VALUE_PORT:
1848	return vmsvgaWritePort(pThis, u32);
1849
1850	case SVGA_BIOS_PORT:
1851	Log(("Ignoring BIOS port write (val=%x)\n", u32));
1852	break;
1853
1854	case SVGA_IRQSTATUS_PORT:
1855	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
1856	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
1857	/* Clear the irq in case all events have been cleared. */
1858	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
1859	{
1860	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
1861	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1862	}
1863	break;
1864	}
1865	return VINF_SUCCESS;
1866	}
1867
1868	#ifdef DEBUG_FIFO_ACCESS
1869
1870	# ifdef IN_RING3
1871	/**
1872	* Handle LFB access.
1873	* @returns VBox status code.
1874	* @param pVM VM handle.
1875	* @param pThis VGA device instance data.
1876	* @param GCPhys The access physical address.
1877	* @param fWriteAccess Read or write access
1878	*/
1879	static int vmsvgaFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
1880	{
1881	RT_NOREF(pVM);
1882	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
1883	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1884
1885	switch (GCPhysOffset >> 2)
1886	{
1887	case SVGA_FIFO_MIN:
1888	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1889	break;
1890	case SVGA_FIFO_MAX:
1891	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1892	break;
1893	case SVGA_FIFO_NEXT_CMD:
1894	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1895	break;
1896	case SVGA_FIFO_STOP:
1897	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1898	break;
1899	case SVGA_FIFO_CAPABILITIES:
1900	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1901	break;
1902	case SVGA_FIFO_FLAGS:
1903	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1904	break;
1905	case SVGA_FIFO_FENCE:
1906	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1907	break;
1908	case SVGA_FIFO_3D_HWVERSION:
1909	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1910	break;
1911	case SVGA_FIFO_PITCHLOCK:
1912	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1913	break;
1914	case SVGA_FIFO_CURSOR_ON:
1915	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1916	break;
1917	case SVGA_FIFO_CURSOR_X:
1918	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1919	break;
1920	case SVGA_FIFO_CURSOR_Y:
1921	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1922	break;
1923	case SVGA_FIFO_CURSOR_COUNT:
1924	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1925	break;
1926	case SVGA_FIFO_CURSOR_LAST_UPDATED:
1927	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1928	break;
1929	case SVGA_FIFO_RESERVED:
1930	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1931	break;
1932	case SVGA_FIFO_CURSOR_SCREEN_ID:
1933	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1934	break;
1935	case SVGA_FIFO_DEAD:
1936	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1937	break;
1938	case SVGA_FIFO_3D_HWVERSION_REVISED:
1939	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1940	break;
1941	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
1942	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1943	break;
1944	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
1945	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1946	break;
1947	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
1948	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1949	break;
1950	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
1951	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1952	break;
1953	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
1954	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1955	break;
1956	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
1957	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1958	break;
1959	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
1960	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1961	break;
1962	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
1963	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1964	break;
1965	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
1966	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1967	break;
1968	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
1969	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1970	break;
1971	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
1972	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1973	break;
1974	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
1975	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1976	break;
1977	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
1978	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1979	break;
1980	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
1981	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1982	break;
1983	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
1984	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1985	break;
1986	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
1987	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1988	break;
1989	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
1990	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1991	break;
1992	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
1993	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1994	break;
1995	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
1996	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1997	break;
1998	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
1999	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2000	break;
2001	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2002	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2003	break;
2004	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2005	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2006	break;
2007	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2008	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2009	break;
2010	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2011	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2012	break;
2013	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2014	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2015	break;
2016	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2017	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2018	break;
2019	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2020	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2021	break;
2022	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2023	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2024	break;
2025	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2026	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2027	break;
2028	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2029	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2030	break;
2031	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2032	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2033	break;
2034	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2035	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2036	break;
2037	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2038	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2039	break;
2040	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2041	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2042	break;
2043	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2044	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2045	break;
2046	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2047	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2048	break;
2049	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2050	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2051	break;
2052	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2053	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2054	break;
2055	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2056	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2057	break;
2058	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2059	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2060	break;
2061	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2062	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2063	break;
2064	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2065	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2066	break;
2067	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2068	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2069	break;
2070	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2071	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2072	break;
2073	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2074	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2075	break;
2076	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2077	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2078	break;
2079	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2080	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2081	break;
2082	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2083	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2084	break;
2085	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2086	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2087	break;
2088	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2089	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2090	break;
2091	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2092	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2093	break;
2094	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2095	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2096	break;
2097	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2098	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2099	break;
2100	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2101	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2102	break;
2103	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2104	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2105	break;
2106	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2107	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2108	break;
2109	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2110	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2111	break;
2112	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2113	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2114	break;
2115	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2116	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2117	break;
2118	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2119	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2120	break;
2121	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2122	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2123	break;
2124	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2125	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2126	break;
2127	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2128	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2129	break;
2130	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2131	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2132	break;
2133	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2134	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2135	break;
2136	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2137	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2138	break;
2139	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2140	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2141	break;
2142	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2143	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2144	break;
2145	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2146	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2147	break;
2148	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2149	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2150	break;
2151	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2152	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2153	break;
2154	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2155	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2156	break;
2157	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2158	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2159	break;
2160	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2161	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2162	break;
2163	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2164	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2165	break;
2166	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2167	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2168	break;
2169	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2170	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2171	break;
2172	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2173	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2174	break;
2175	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2176	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2177	break;
2178	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2179	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2180	break;
2181	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2182	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2183	break;
2184	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2185	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2186	break;
2187	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2188	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2189	break;
2190	case SVGA_FIFO_3D_CAPS_LAST:
2191	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2192	break;
2193	case SVGA_FIFO_GUEST_3D_HWVERSION:
2194	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2195	break;
2196	case SVGA_FIFO_FENCE_GOAL:
2197	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2198	break;
2199	case SVGA_FIFO_BUSY:
2200	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2201	break;
2202	default:
2203	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2204	break;
2205	}
2206
2207	return VINF_EM_RAW_EMULATE_INSTR;
2208	}
2209
2210	/**
2211	* HC access handler for the FIFO.
2212	*
2213	* @returns VINF_SUCCESS if the handler have carried out the operation.
2214	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2215	* @param pVM VM Handle.
2216	* @param pVCpu The cross context CPU structure for the calling EMT.
2217	* @param GCPhys The physical address the guest is writing to.
2218	* @param pvPhys The HC mapping of that address.
2219	* @param pvBuf What the guest is reading/writing.
2220	* @param cbBuf How much it's reading/writing.
2221	* @param enmAccessType The access type.
2222	* @param enmOrigin Who is making the access.
2223	* @param pvUser User argument.
2224	*/
2225	static DECLCALLBACK(VBOXSTRICTRC)
2226	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2227	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2228	{
2229	PVGASTATE pThis = (PVGASTATE)pvUser;
2230	int rc;
2231	Assert(pThis);
2232	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2233	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
2234
2235	rc = vmsvgaFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2236	if (RT_SUCCESS(rc))
2237	return VINF_PGM_HANDLER_DO_DEFAULT;
2238	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2239	return rc;
2240	}
2241
2242	# endif /* IN_RING3 */
2243	#endif /* DEBUG_FIFO_ACCESS */
2244
2245	#ifdef DEBUG_GMR_ACCESS
2246	# ifdef IN_RING3
2247
2248	/**
2249	* HC access handler for the FIFO.
2250	*
2251	* @returns VINF_SUCCESS if the handler have carried out the operation.
2252	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2253	* @param pVM VM Handle.
2254	* @param pVCpu The cross context CPU structure for the calling EMT.
2255	* @param GCPhys The physical address the guest is writing to.
2256	* @param pvPhys The HC mapping of that address.
2257	* @param pvBuf What the guest is reading/writing.
2258	* @param cbBuf How much it's reading/writing.
2259	* @param enmAccessType The access type.
2260	* @param enmOrigin Who is making the access.
2261	* @param pvUser User argument.
2262	*/
2263	static DECLCALLBACK(VBOXSTRICTRC)
2264	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2265	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2266	{
2267	PVGASTATE pThis = (PVGASTATE)pvUser;
2268	Assert(pThis);
2269	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2270	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2271
2272	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2273
2274	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2275	{
2276	PGMR pGMR = &pSVGAState->paGMR[i];
2277
2278	if (pGMR->numDescriptors)
2279	{
2280	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2281	{
2282	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2283	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2284	{
2285	/*
2286	* Turn off the write handler for this particular page and make it R/W.
2287	* Then return telling the caller to restart the guest instruction.
2288	*/
2289	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2290	AssertRC(rc);
2291	goto end;
2292	}
2293	}
2294	}
2295	}
2296	end:
2297	return VINF_PGM_HANDLER_DO_DEFAULT;
2298	}
2299
2300	/* Callback handler for VMR3ReqCallWaitU */
2301	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2302	{
2303	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2304	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2305	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2306	int rc;
2307
2308	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2309	{
2310	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2311	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2312	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2313	AssertRC(rc);
2314	}
2315	return VINF_SUCCESS;
2316	}
2317
2318	/* Callback handler for VMR3ReqCallWaitU */
2319	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2320	{
2321	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2322	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2323	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2324
2325	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2326	{
2327	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2328	AssertRC(rc);
2329	}
2330	return VINF_SUCCESS;
2331	}
2332
2333	/* Callback handler for VMR3ReqCallWaitU */
2334	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2335	{
2336	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2337
2338	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2339	{
2340	PGMR pGMR = &pSVGAState->paGMR[i];
2341
2342	if (pGMR->numDescriptors)
2343	{
2344	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2345	{
2346	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2347	AssertRC(rc);
2348	}
2349	}
2350	}
2351	return VINF_SUCCESS;
2352	}
2353
2354	# endif /* IN_RING3 */
2355	#endif /* DEBUG_GMR_ACCESS */
2356
2357	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2358
2359	#ifdef IN_RING3
2360
2361
2362	/**
2363	* Common worker for changing the pointer shape.
2364	*
2365	* @param pThis The VGA instance data.
2366	* @param pSVGAState The VMSVGA ring-3 instance data.
2367	* @param fAlpha Whether there is alpha or not.
2368	* @param xHot Hotspot x coordinate.
2369	* @param yHot Hotspot y coordinate.
2370	* @param cx Width.
2371	* @param cy Height.
2372	* @param pbData Heap copy of the cursor data. Consumed.
2373	* @param cbData The size of the data.
2374	*/
2375	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2376	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2377	{
2378	Log(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2379	#ifdef LOG_ENABLED
2380	if (LogIs2Enabled())
2381	{
2382	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2383	if (!fAlpha)
2384	{
2385	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2386	for (uint32_t y = 0; y < cy; y++)
2387	{
2388	Log2(("%3u:", y));
2389	uint8_t const pbLine = &pbData[y cbAndLine];
2390	for (uint32_t x = 0; x < cx; x += 8)
2391	{
2392	uint8_t b = pbLine[x / 8];
2393	char szByte[12];
2394	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2395	szByte[1] = b & 0x40 ? '*' : ' ';
2396	szByte[2] = b & 0x20 ? '*' : ' ';
2397	szByte[3] = b & 0x10 ? '*' : ' ';
2398	szByte[4] = b & 0x08 ? '*' : ' ';
2399	szByte[5] = b & 0x04 ? '*' : ' ';
2400	szByte[6] = b & 0x02 ? '*' : ' ';
2401	szByte[7] = b & 0x01 ? '*' : ' ';
2402	szByte[8] = '\0';
2403	Log2(("%s", szByte));
2404	}
2405	Log2(("\n"));
2406	}
2407	}
2408
2409	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2410	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2411	for (uint32_t y = 0; y < cy; y++)
2412	{
2413	Log2(("%3u:", y));
2414	uint32_t const pu32Line = &pu32Xor[y cx];
2415	for (uint32_t x = 0; x < cx; x++)
2416	Log2((" %08x", pu32Line[x]));
2417	Log2(("\n"));
2418	}
2419	}
2420	#endif
2421
2422	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2423	AssertRC(rc);
2424
2425	if (pSVGAState->Cursor.fActive)
2426	RTMemFree(pSVGAState->Cursor.pData);
2427
2428	pSVGAState->Cursor.fActive = true;
2429	pSVGAState->Cursor.xHotspot = xHot;
2430	pSVGAState->Cursor.yHotspot = yHot;
2431	pSVGAState->Cursor.width = cx;
2432	pSVGAState->Cursor.height = cy;
2433	pSVGAState->Cursor.cbData = cbData;
2434	pSVGAState->Cursor.pData = pbData;
2435	}
2436
2437
2438	/**
2439	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2440	*
2441	* @param pThis The VGA instance data.
2442	* @param pSVGAState The VMSVGA ring-3 instance data.
2443	* @param pCursor The cursor.
2444	* @param pbSrcAndMask The AND mask.
2445	* @param cbSrcAndLine The scanline length of the AND mask.
2446	* @param pbSrcXorMask The XOR mask.
2447	* @param cbSrcXorLine The scanline length of the XOR mask.
2448	*/
2449	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2450	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2451	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2452	{
2453	uint32_t const cx = pCursor->width;
2454	uint32_t const cy = pCursor->height;
2455
2456	/*
2457	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2458	* The AND data uses 8-bit aligned scanlines.
2459	* The XOR data must be starting on a 32-bit boundrary.
2460	*/
2461	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2462	uint32_t cbDstAndMask = cbDstAndLine * cy;
2463	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2464	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2465
2466	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2467	AssertReturnVoid(pbCopy);
2468
2469	/* Convert the AND mask. */
2470	uint8_t *pbDst = pbCopy;
2471	uint8_t const *pbSrc = pbSrcAndMask;
2472	switch (pCursor->andMaskDepth)
2473	{
2474	case 1:
2475	if (cbSrcAndLine == cbDstAndLine)
2476	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2477	else
2478	{
2479	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2480	for (uint32_t y = 0; y < cy; y++)
2481	{
2482	memcpy(pbDst, pbSrc, cbDstAndLine);
2483	pbDst += cbDstAndLine;
2484	pbSrc += cbSrcAndLine;
2485	}
2486	}
2487	break;
2488	/* Should take the XOR mask into account for the multi-bit AND mask. */
2489	case 8:
2490	for (uint32_t y = 0; y < cy; y++)
2491	{
2492	for (uint32_t x = 0; x < cx; )
2493	{
2494	uint8_t bDst = 0;
2495	uint8_t fBit = 1;
2496	do
2497	{
2498	uintptr_t const idxPal = pbSrc[x] * 3;
2499	if ((( pThis->last_palette[idxPal]
2500	\| (pThis->last_palette[idxPal] >> 8)
2501	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2502	bDst \|= fBit;
2503	fBit <<= 1;
2504	x++;
2505	} while (x < cx && (x & 7));
2506	pbDst[(x - 1) / 8] = bDst;
2507	}
2508	pbDst += cbDstAndLine;
2509	pbSrc += cbSrcAndLine;
2510	}
2511	break;
2512	case 15:
2513	for (uint32_t y = 0; y < cy; y++)
2514	{
2515	for (uint32_t x = 0; x < cx; )
2516	{
2517	uint8_t bDst = 0;
2518	uint8_t fBit = 1;
2519	do
2520	{
2521	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2522	bDst \|= fBit;
2523	fBit <<= 1;
2524	x++;
2525	} while (x < cx && (x & 7));
2526	pbDst[(x - 1) / 8] = bDst;
2527	}
2528	pbDst += cbDstAndLine;
2529	pbSrc += cbSrcAndLine;
2530	}
2531	break;
2532	case 16:
2533	for (uint32_t y = 0; y < cy; y++)
2534	{
2535	for (uint32_t x = 0; x < cx; )
2536	{
2537	uint8_t bDst = 0;
2538	uint8_t fBit = 1;
2539	do
2540	{
2541	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2542	bDst \|= fBit;
2543	fBit <<= 1;
2544	x++;
2545	} while (x < cx && (x & 7));
2546	pbDst[(x - 1) / 8] = bDst;
2547	}
2548	pbDst += cbDstAndLine;
2549	pbSrc += cbSrcAndLine;
2550	}
2551	break;
2552	case 24:
2553	for (uint32_t y = 0; y < cy; y++)
2554	{
2555	for (uint32_t x = 0; x < cx; )
2556	{
2557	uint8_t bDst = 0;
2558	uint8_t fBit = 1;
2559	do
2560	{
2561	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2562	bDst \|= fBit;
2563	fBit <<= 1;
2564	x++;
2565	} while (x < cx && (x & 7));
2566	pbDst[(x - 1) / 8] = bDst;
2567	}
2568	pbDst += cbDstAndLine;
2569	pbSrc += cbSrcAndLine;
2570	}
2571	break;
2572	case 32:
2573	for (uint32_t y = 0; y < cy; y++)
2574	{
2575	for (uint32_t x = 0; x < cx; )
2576	{
2577	uint8_t bDst = 0;
2578	uint8_t fBit = 1;
2579	do
2580	{
2581	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2582	bDst \|= fBit;
2583	fBit <<= 1;
2584	x++;
2585	} while (x < cx && (x & 7));
2586	pbDst[(x - 1) / 8] = bDst;
2587	}
2588	pbDst += cbDstAndLine;
2589	pbSrc += cbSrcAndLine;
2590	}
2591	break;
2592	default:
2593	RTMemFree(pbCopy);
2594	AssertFailedReturnVoid();
2595	}
2596
2597	/* Convert the XOR mask. */
2598	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2599	pbSrc = pbSrcXorMask;
2600	switch (pCursor->xorMaskDepth)
2601	{
2602	case 1:
2603	for (uint32_t y = 0; y < cy; y++)
2604	{
2605	for (uint32_t x = 0; x < cx; )
2606	{
2607	/* most significant bit is the left most one. */
2608	uint8_t bSrc = pbSrc[x / 8];
2609	do
2610	{
2611	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2612	bSrc <<= 1;
2613	x++;
2614	} while ((x & 7) && x < cx);
2615	}
2616	pbSrc += cbSrcXorLine;
2617	}
2618	break;
2619	case 8:
2620	for (uint32_t y = 0; y < cy; y++)
2621	{
2622	for (uint32_t x = 0; x < cx; x++)
2623	{
2624	uint32_t u = pThis->last_palette[pbSrc[x]];
2625	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2626	}
2627	pbSrc += cbSrcXorLine;
2628	}
2629	break;
2630	case 15: /* Src: RGB-5-5-5 */
2631	for (uint32_t y = 0; y < cy; y++)
2632	{
2633	for (uint32_t x = 0; x < cx; x++)
2634	{
2635	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2636	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2637	((uValue >> 5) & 0x1f) << 3,
2638	((uValue >> 10) & 0x1f) << 3, 0);
2639	}
2640	pbSrc += cbSrcXorLine;
2641	}
2642	break;
2643	case 16: /* Src: RGB-5-6-5 */
2644	for (uint32_t y = 0; y < cy; y++)
2645	{
2646	for (uint32_t x = 0; x < cx; x++)
2647	{
2648	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2649	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2650	((uValue >> 5) & 0x3f) << 2,
2651	((uValue >> 11) & 0x1f) << 3, 0);
2652	}
2653	pbSrc += cbSrcXorLine;
2654	}
2655	break;
2656	case 24:
2657	for (uint32_t y = 0; y < cy; y++)
2658	{
2659	for (uint32_t x = 0; x < cx; x++)
2660	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2661	pbSrc += cbSrcXorLine;
2662	}
2663	break;
2664	case 32:
2665	for (uint32_t y = 0; y < cy; y++)
2666	{
2667	for (uint32_t x = 0; x < cx; x++)
2668	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2669	pbSrc += cbSrcXorLine;
2670	}
2671	break;
2672	default:
2673	RTMemFree(pbCopy);
2674	AssertFailedReturnVoid();
2675	}
2676
2677	/*
2678	* Pass it to the frontend/whatever.
2679	*/
2680	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2681	}
2682
2683
2684	/**
2685	* Worker for vmsvgaR3FifoThread that handles an external command.
2686	*
2687	* @param pThis VGA device instance data.
2688	*/
2689	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2690	{
2691	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2692	switch (pThis->svga.u8FIFOExtCommand)
2693	{
2694	case VMSVGA_FIFO_EXTCMD_RESET:
2695	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2696	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2697	# ifdef VBOX_WITH_VMSVGA3D
2698	if (pThis->svga.f3DEnabled)
2699	{
2700	/* The 3d subsystem must be reset from the fifo thread. */
2701	vmsvga3dReset(pThis);
2702	}
2703	# endif
2704	break;
2705
2706	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2707	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2708	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2709	# ifdef VBOX_WITH_VMSVGA3D
2710	if (pThis->svga.f3DEnabled)
2711	{
2712	/* The 3d subsystem must be shut down from the fifo thread. */
2713	vmsvga3dTerminate(pThis);
2714	}
2715	# endif
2716	break;
2717
2718	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2719	{
2720	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2721	# ifdef VBOX_WITH_VMSVGA3D
2722	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2723	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2724	vmsvga3dSaveExec(pThis, pSSM);
2725	# endif
2726	break;
2727	}
2728
2729	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2730	{
2731	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2732	# ifdef VBOX_WITH_VMSVGA3D
2733	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2734	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2735	vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2736	# endif
2737	break;
2738	}
2739
2740	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2741	{
2742	# ifdef VBOX_WITH_VMSVGA3D
2743	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2744	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2745	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2746	# endif
2747	break;
2748	}
2749
2750
2751	default:
2752	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2753	break;
2754	}
2755
2756	/*
2757	* Signal the end of the external command.
2758	*/
2759	pThis->svga.pvFIFOExtCmdParam = NULL;
2760	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2761	ASMMemoryFence(); /* paranoia^2 */
2762	int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2763	AssertLogRelRC(rc);
2764	}
2765
2766	/**
2767	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2768	* doing a job on the FIFO thread (even when it's officially suspended).
2769	*
2770	* @returns VBox status code (fully asserted).
2771	* @param pThis VGA device instance data.
2772	* @param uExtCmd The command to execute on the FIFO thread.
2773	* @param pvParam Pointer to command parameters.
2774	* @param cMsWait The time to wait for the command, given in
2775	* milliseconds.
2776	*/
2777	static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2778	{
2779	Assert(cMsWait >= RT_MS_1SEC * 5);
2780	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2781	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2782
2783	int rc;
2784	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2785	PDMTHREADSTATE enmState = pThread->enmState;
2786	if (enmState == PDMTHREADSTATE_SUSPENDED)
2787	{
2788	/*
2789	* The thread is suspended, we have to temporarily wake it up so it can
2790	* perform the task.
2791	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
2792	*/
2793	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2794	/* Post the request. */
2795	pThis->svga.fFifoExtCommandWakeup = true;
2796	pThis->svga.pvFIFOExtCmdParam = pvParam;
2797	pThis->svga.u8FIFOExtCommand = uExtCmd;
2798	ASMMemoryFence(); /* paranoia^3 */
2799
2800	/* Resume the thread. */
2801	rc = PDMR3ThreadResume(pThread);
2802	AssertLogRelRC(rc);
2803	if (RT_SUCCESS(rc))
2804	{
2805	/* Wait. Take care in case the semaphore was already posted (same as below). */
2806	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2807	if ( rc == VINF_SUCCESS
2808	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
2809	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2810	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
2811	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2812
2813	/* suspend the thread */
2814	pThis->svga.fFifoExtCommandWakeup = false;
2815	int rc2 = PDMR3ThreadSuspend(pThread);
2816	AssertLogRelRC(rc2);
2817	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2818	rc = rc2;
2819	}
2820	pThis->svga.fFifoExtCommandWakeup = false;
2821	pThis->svga.pvFIFOExtCmdParam = NULL;
2822	}
2823	else if (enmState == PDMTHREADSTATE_RUNNING)
2824	{
2825	/*
2826	* The thread is running, should only happen during reset and vmsvga3dsfc.
2827	* We ASSUME not racing code here, both wrt thread state and ext commands.
2828	*/
2829	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
2830	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
2831
2832	/* Post the request. */
2833	pThis->svga.pvFIFOExtCmdParam = pvParam;
2834	pThis->svga.u8FIFOExtCommand = uExtCmd;
2835	ASMMemoryFence(); /* paranoia^2 */
2836	rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2837	AssertLogRelRC(rc);
2838
2839	/* Wait. Take care in case the semaphore was already posted (same as above). */
2840	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2841	if ( rc == VINF_SUCCESS
2842	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
2843	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
2844	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
2845	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2846
2847	pThis->svga.pvFIFOExtCmdParam = NULL;
2848	}
2849	else
2850	{
2851	/*
2852	* Something is wrong with the thread!
2853	*/
2854	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
2855	rc = VERR_INVALID_STATE;
2856	}
2857	return rc;
2858	}
2859
2860
2861	/**
2862	* Marks the FIFO non-busy, notifying any waiting EMTs.
2863	*
2864	* @param pThis The VGA state.
2865	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
2866	* @param offFifoMin The start byte offset of the command FIFO.
2867	*/
2868	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
2869	{
2870	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
2871	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2872	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
2873
2874	/* Wake up any waiting EMTs. */
2875	if (pSVGAState->cBusyDelayedEmts > 0)
2876	{
2877	#ifdef VMSVGA_USE_EMT_HALT_CODE
2878	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
2879	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
2880	if (idCpu != NIL_VMCPUID)
2881	{
2882	VMR3NotifyCpuDeviceReady(pVM, idCpu);
2883	while (idCpu-- > 0)
2884	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
2885	VMR3NotifyCpuDeviceReady(pVM, idCpu);
2886	}
2887	#else
2888	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
2889	AssertRC(rc2);
2890	#endif
2891	}
2892	}
2893
2894	/**
2895	* Reads (more) payload into the command buffer.
2896	*
2897	* @returns pbBounceBuf on success
2898	* @retval (void *)1 if the thread was requested to stop.
2899	* @retval NULL on FIFO error.
2900	*
2901	* @param cbPayloadReq The number of bytes of payload requested.
2902	* @param pFIFO The FIFO.
2903	* @param offCurrentCmd The FIFO byte offset of the current command.
2904	* @param offFifoMin The start byte offset of the command FIFO.
2905	* @param offFifoMax The end byte offset of the command FIFO.
2906	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
2907	* always sufficient size.
2908	* @param pcbAlreadyRead How much payload we've already read into the bounce
2909	* buffer. (We will NEVER re-read anything.)
2910	* @param pThread The calling PDM thread handle.
2911	* @param pThis The VGA state.
2912	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
2913	* statistics collection.
2914	*/
2915	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t volatile pFIFO,
2916	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
2917	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
2918	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
2919	{
2920	Assert(pbBounceBuf);
2921	Assert(pcbAlreadyRead);
2922	Assert(offFifoMin < offFifoMax);
2923	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
2924	Assert(offFifoMax <= pThis->svga.cbFIFO);
2925
2926	/*
2927	* Check if the requested payload size has already been satisfied .
2928	* .
2929	* When called to read more, the caller is responsible for making sure the .
2930	* new command size (cbRequsted) never is smaller than what has already .
2931	* been read.
2932	*/
2933	uint32_t cbAlreadyRead = *pcbAlreadyRead;
2934	if (cbPayloadReq <= cbAlreadyRead)
2935	{
2936	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
2937	return pbBounceBuf;
2938	}
2939
2940	/*
2941	* Commands bigger than the fifo buffer are invalid.
2942	*/
2943	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
2944	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
2945	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
2946	NULL);
2947
2948	/*
2949	* Move offCurrentCmd past the command dword.
2950	*/
2951	offCurrentCmd += sizeof(uint32_t);
2952	if (offCurrentCmd >= offFifoMax)
2953	offCurrentCmd = offFifoMin;
2954
2955	/*
2956	* Do we have sufficient payload data available already?
2957	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
2958	*/
2959	uint32_t cbAfter, cbBefore;
2960	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2961	if (offNextCmd >= offCurrentCmd)
2962	{
2963	if (RT_LIKELY(offNextCmd < offFifoMax))
2964	cbAfter = offNextCmd - offCurrentCmd;
2965	else
2966	{
2967	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2968	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2969	offNextCmd, offFifoMin, offFifoMax));
2970	cbAfter = offFifoMax - offCurrentCmd;
2971	}
2972	cbBefore = 0;
2973	}
2974	else
2975	{
2976	cbAfter = offFifoMax - offCurrentCmd;
2977	if (offNextCmd >= offFifoMin)
2978	cbBefore = offNextCmd - offFifoMin;
2979	else
2980	{
2981	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2982	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2983	offNextCmd, offFifoMin, offFifoMax));
2984	cbBefore = 0;
2985	}
2986	}
2987	if (cbAfter + cbBefore < cbPayloadReq)
2988	{
2989	/*
2990	* Insufficient, must wait for it to arrive.
2991	*/
2992	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
2993	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
2994	for (uint32_t i = 0;; i++)
2995	{
2996	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2997	{
2998	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2999	return (void *)(uintptr_t)1;
3000	}
3001	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3002	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3003
3004	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
3005
3006	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3007	if (offNextCmd >= offCurrentCmd)
3008	{
3009	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3010	cbBefore = 0;
3011	}
3012	else
3013	{
3014	cbAfter = offFifoMax - offCurrentCmd;
3015	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3016	}
3017
3018	if (cbAfter + cbBefore >= cbPayloadReq)
3019	break;
3020	}
3021	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3022	}
3023
3024	/*
3025	* Copy out the memory and update what pcbAlreadyRead points to.
3026	*/
3027	if (cbAfter >= cbPayloadReq)
3028	memcpy(pbBounceBuf + cbAlreadyRead,
3029	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3030	cbPayloadReq - cbAlreadyRead);
3031	else
3032	{
3033	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3034	if (cbAlreadyRead < cbAfter)
3035	{
3036	memcpy(pbBounceBuf + cbAlreadyRead,
3037	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3038	cbAfter - cbAlreadyRead);
3039	cbAlreadyRead = cbAfter;
3040	}
3041	memcpy(pbBounceBuf + cbAlreadyRead,
3042	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3043	cbPayloadReq - cbAlreadyRead);
3044	}
3045	*pcbAlreadyRead = cbPayloadReq;
3046	return pbBounceBuf;
3047	}
3048
3049	/* The async FIFO handling thread. */
3050	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3051	{
3052	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3053	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3054	int rc;
3055
3056	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3057	return VINF_SUCCESS;
3058
3059	/*
3060	* Special mode where we only execute an external command and the go back
3061	* to being suspended. Currently, all ext cmds ends up here, with the reset
3062	* one also being eligble for runtime execution further down as well.
3063	*/
3064	if (pThis->svga.fFifoExtCommandWakeup)
3065	{
3066	vmsvgaR3FifoHandleExtCmd(pThis);
3067	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3068	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3069	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
3070	else
3071	vmsvgaR3FifoHandleExtCmd(pThis);
3072	return VINF_SUCCESS;
3073	}
3074
3075
3076	/*
3077	* Signal the semaphore to make sure we don't wait for 250ms after a
3078	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3079	*/
3080	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3081
3082	/*
3083	* Allocate a bounce buffer for command we get from the FIFO.
3084	* (All code must return via the end of the function to free this buffer.)
3085	*/
3086	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3087	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3088
3089	/*
3090	* Polling/sleep interval config.
3091	*
3092	* We wait for an a short interval if the guest has recently given us work
3093	* to do, but the interval increases the longer we're kept idle. With the
3094	* current parameters we'll be at a 64ms poll interval after 1 idle second,
3095	* at 90ms after 2 seconds, and reach the max 250ms interval after about
3096	* 16 seconds.
3097	*/
3098	RTMSINTERVAL const cMsMinSleep = 16;
3099	RTMSINTERVAL const cMsIncSleep = 2;
3100	RTMSINTERVAL const cMsMaxSleep = 250;
3101	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3102
3103	/*
3104	* The FIFO loop.
3105	*/
3106	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3107	bool fBadOrDisabledFifo = false;
3108	uint32_t volatile * const pFIFO = pThis->svga.pFIFOR3;
3109	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3110	{
3111	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3112	/*
3113	* Should service the run loop every so often.
3114	*/
3115	if (pThis->svga.f3DEnabled)
3116	vmsvga3dCocoaServiceRunLoop();
3117	# endif
3118
3119	/*
3120	* Unless there's already work pending, go to sleep for a short while.
3121	* (See polling/sleep interval config above.)
3122	*/
3123	if ( fBadOrDisabledFifo
3124	\|\| pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
3125	{
3126	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
3127	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3128	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3129	{
3130	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3131	break;
3132	}
3133	}
3134	else
3135	rc = VINF_SUCCESS;
3136	fBadOrDisabledFifo = false;
3137	if (rc == VERR_TIMEOUT)
3138	{
3139	if (pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
3140	{
3141	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3142	continue;
3143	}
3144	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3145
3146	Log(("vmsvgaFIFOLoop: timeout\n"));
3147	}
3148	else if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3149	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3150	cMsSleep = cMsMinSleep;
3151
3152	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
3153	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3154	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3155
3156	/*
3157	* Handle external commands (currently only reset).
3158	*/
3159	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3160	{
3161	vmsvgaR3FifoHandleExtCmd(pThis);
3162	continue;
3163	}
3164
3165	/*
3166	* The device must be enabled and configured.
3167	*/
3168	if ( !pThis->svga.fEnabled
3169	\|\| !pThis->svga.fConfigured)
3170	{
3171	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3172	fBadOrDisabledFifo = true;
3173	continue;
3174	}
3175
3176	/*
3177	* Get and check the min/max values. We ASSUME that they will remain
3178	* unchanged while we process requests. A further ASSUMPTION is that
3179	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3180	* we don't read it back while in the loop.
3181	*/
3182	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3183	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3184	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3185	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3186	\|\| offFifoMax <= offFifoMin
3187	\|\| offFifoMax > pThis->svga.cbFIFO
3188	\|\| (offFifoMax & 3) != 0
3189	\|\| (offFifoMin & 3) != 0
3190	\|\| offCurrentCmd < offFifoMin
3191	\|\| offCurrentCmd > offFifoMax))
3192	{
3193	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3194	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3195	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3196	fBadOrDisabledFifo = true;
3197	continue;
3198	}
3199	if (RT_UNLIKELY(offCurrentCmd & 3))
3200	{
3201	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3202	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3203	offCurrentCmd = ~UINT32_C(3);
3204	}
3205
3206	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3207	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3208	*
3209	* Will break out of the switch on failure.
3210	* Will restart and quit the loop if the thread was requested to stop.
3211	*
3212	* @param a_PtrVar Request variable pointer.
3213	* @param a_Type Request typedef (not pointer) for casting.
3214	* @param a_cbPayloadReq How much payload to fetch.
3215	* @remarks Accesses a bunch of variables in the current scope!
3216	*/
3217	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3218	if (1) { \
3219	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3220	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
3221	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3222	} else do {} while (0)
3223	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3224	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3225	* buffer after figuring out the actual command size.
3226	*
3227	* Will break out of the switch on failure.
3228	*
3229	* @param a_PtrVar Request variable pointer.
3230	* @param a_Type Request typedef (not pointer) for casting.
3231	* @param a_cbPayloadReq How much payload to fetch.
3232	* @remarks Accesses a bunch of variables in the current scope!
3233	*/
3234	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3235	if (1) { \
3236	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3237	} else do {} while (0)
3238
3239	/*
3240	* Mark the FIFO as busy.
3241	*/
3242	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3243	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3244	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3245
3246	/*
3247	* Execute all queued FIFO commands.
3248	* Quit if pending external command or changes in the thread state.
3249	*/
3250	bool fDone = false;
3251	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3252	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3253	{
3254	uint32_t cbPayload = 0;
3255	uint32_t u32IrqStatus = 0;
3256
3257	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3258
3259	/* First check any pending actions. */
3260	if ( ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT)
3261	&& pThis->svga.p3dState != NULL)
3262	# ifdef VBOX_WITH_VMSVGA3D
3263	vmsvga3dChangeMode(pThis);
3264	# else
3265	{/nothing/}
3266	# endif
3267	/* Check for pending external commands (reset). */
3268	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3269	break;
3270
3271	/*
3272	* Process the command.
3273	*/
3274	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3275	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3276	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3277	switch (enmCmdId)
3278	{
3279	case SVGA_CMD_INVALID_CMD:
3280	/* Nothing to do. */
3281	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3282	break;
3283
3284	case SVGA_CMD_FENCE:
3285	{
3286	SVGAFifoCmdFence *pCmdFence;
3287	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3288	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3289	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3290	{
3291	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3292	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3293
3294	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3295	{
3296	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3297	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3298	}
3299	else
3300	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3301	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3302	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3303	{
3304	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3305	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3306	}
3307	}
3308	else
3309	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3310	break;
3311	}
3312	case SVGA_CMD_UPDATE:
3313	case SVGA_CMD_UPDATE_VERBOSE:
3314	{
3315	SVGAFifoCmdUpdate *pUpdate;
3316	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3317	if (enmCmdId == SVGA_CMD_UPDATE)
3318	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3319	else
3320	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3321	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3322	vgaR3UpdateDisplay(pThis, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3323	break;
3324	}
3325
3326	case SVGA_CMD_DEFINE_CURSOR:
3327	{
3328	/* Followed by bitmap data. */
3329	SVGAFifoCmdDefineCursor *pCursor;
3330	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3331	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3332
3333	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3334	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3335	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3336	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3337	AssertBreak(pCursor->andMaskDepth <= 32);
3338	AssertBreak(pCursor->xorMaskDepth <= 32);
3339
3340	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3341	uint32_t cbAndMask = cbAndLine * pCursor->height;
3342	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3343	uint32_t cbXorMask = cbXorLine * pCursor->height;
3344	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3345
3346	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3347	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3348	break;
3349	}
3350
3351	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3352	{
3353	/* Followed by bitmap data. */
3354	uint32_t cbCursorShape, cbAndMask;
3355	uint8_t *pCursorCopy;
3356	uint32_t cbCmd;
3357
3358	SVGAFifoCmdDefineAlphaCursor *pCursor;
3359	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3360	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3361
3362	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3363
3364	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3365	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3366
3367	/* Refetch the bitmap data as well. */
3368	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3369	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3370	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3371
3372	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3373	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3374	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3375	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3376
3377	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3378	AssertBreak(pCursorCopy);
3379
3380	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3381	memset(pCursorCopy, 0xff, cbAndMask);
3382	/* Colour data */
3383	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3384
3385	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3386	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3387	break;
3388	}
3389
3390	case SVGA_CMD_ESCAPE:
3391	{
3392	/* Followed by nsize bytes of data. */
3393	SVGAFifoCmdEscape *pEscape;
3394	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3395	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3396
3397	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3398	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3399	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3400	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3401
3402	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3403	{
3404	AssertBreak(pEscape->size >= sizeof(uint32_t));
3405	uint32_t cmd = (uint32_t )(pEscape + 1);
3406	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3407
3408	switch (cmd)
3409	{
3410	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3411	{
3412	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3413	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3414	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3415
3416	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3417	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3418	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3419
3420	RT_NOREF_PV(pVideoCmd);
3421	break;
3422
3423	}
3424
3425	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3426	{
3427	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3428	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3429	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3430	RT_NOREF_PV(pVideoCmd);
3431	break;
3432	}
3433	}
3434	}
3435	else
3436	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3437
3438	break;
3439	}
3440	# ifdef VBOX_WITH_VMSVGA3D
3441	case SVGA_CMD_DEFINE_GMR2:
3442	{
3443	SVGAFifoCmdDefineGMR2 *pCmd;
3444	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3445	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3446	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3447
3448	/* Validate current GMR id. */
3449	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3450	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3451
3452	if (!pCmd->numPages)
3453	{
3454	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3455	vmsvgaGMRFree(pThis, pCmd->gmrId);
3456	}
3457	else
3458	{
3459	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3460	if (pGMR->cMaxPages)
3461	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3462
3463	/* Not sure if we should always free the descriptor, but for simplicity
3464	we do so if the new size is smaller than the current. */
3465	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3466	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3467	vmsvgaGMRFree(pThis, pCmd->gmrId);
3468
3469	pGMR->cMaxPages = pCmd->numPages;
3470	/* The rest is done by the REMAP_GMR2 command. */
3471	}
3472	break;
3473	}
3474
3475	case SVGA_CMD_REMAP_GMR2:
3476	{
3477	/* Followed by page descriptors or guest ptr. */
3478	SVGAFifoCmdRemapGMR2 *pCmd;
3479	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3480	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3481
3482	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3483	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3484
3485	/* Calculate the size of what comes after next and fetch it. */
3486	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3487	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3488	cbCmd += sizeof(SVGAGuestPtr);
3489	else
3490	{
3491	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3492	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3493	{
3494	cbCmd += cbPageDesc;
3495	pCmd->numPages = 1;
3496	}
3497	else
3498	{
3499	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3500	cbCmd += cbPageDesc * pCmd->numPages;
3501	}
3502	}
3503	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3504
3505	/* Validate current GMR id and size. */
3506	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3507	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3508	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3509	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3510	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3511
3512	if (pCmd->numPages == 0)
3513	break;
3514
3515	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3516	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3517
3518	/*
3519	* We flatten the existing descriptors into a page array, overwrite the
3520	* pages specified in this command and then recompress the descriptor.
3521	*/
3522	/** @todo Optimize the GMR remap algorithm! */
3523
3524	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3525	uint64_t *paNewPage64 = NULL;
3526	if (pGMR->paDesc)
3527	{
3528	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3529
3530	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3531	AssertBreak(paNewPage64);
3532
3533	uint32_t idxPage = 0;
3534	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3535	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3536	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3537	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3538	}
3539
3540	/* Free the old GMR if present. */
3541	if (pGMR->paDesc)
3542	RTMemFree(pGMR->paDesc);
3543
3544	/* Allocate the maximum amount possible (everything non-continuous) */
3545	PVMSVGAGMRDESCRIPTOR paDescs;
3546	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3547	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3548
3549	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3550	{
3551	/** @todo */
3552	AssertFailed();
3553	pGMR->numDescriptors = 0;
3554	}
3555	else
3556	{
3557	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3558	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3559	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3560
3561	if (paNewPage64)
3562	{
3563	/* Overwrite the old page array with the new page values. */
3564	if (fGCPhys64)
3565	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3566	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3567	else
3568	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3569	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3570
3571	/* Use the updated page array instead of the command data. */
3572	fGCPhys64 = true;
3573	paPages64 = paNewPage64;
3574	pCmd->numPages = cNewTotalPages;
3575	}
3576
3577	/* The first page. */
3578	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3579	* applied to paNewPage64. */
3580	RTGCPHYS GCPhys;
3581	if (fGCPhys64)
3582	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3583	else
3584	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
3585	paDescs[0].GCPhys = GCPhys;
3586	paDescs[0].numPages = 1;
3587
3588	/* Subsequent pages. */
3589	uint32_t iDescriptor = 0;
3590	for (uint32_t i = 1; i < pCmd->numPages; i++)
3591	{
3592	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
3593	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3594	else
3595	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
3596
3597	/* Continuous physical memory? */
3598	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
3599	{
3600	Assert(paDescs[iDescriptor].numPages);
3601	paDescs[iDescriptor].numPages++;
3602	LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
3603	}
3604	else
3605	{
3606	iDescriptor++;
3607	paDescs[iDescriptor].GCPhys = GCPhys;
3608	paDescs[iDescriptor].numPages = 1;
3609	LogFlow(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
3610	}
3611	}
3612
3613	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
3614	LogFlow(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
3615	pGMR->numDescriptors = iDescriptor + 1;
3616	}
3617
3618	if (paNewPage64)
3619	RTMemFree(paNewPage64);
3620
3621	# ifdef DEBUG_GMR_ACCESS
3622	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
3623	# endif
3624	break;
3625	}
3626	# endif // VBOX_WITH_VMSVGA3D
3627	case SVGA_CMD_DEFINE_SCREEN:
3628	{
3629	/* Note! The size of this command is specified by the guest and depends on capabilities. */
3630	Assert(!(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT));
3631	SVGAFifoCmdDefineScreen *pCmd;
3632	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
3633	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
3634	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
3635	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
3636
3637	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d)\n", pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y));
3638	if (pCmd->screen.flags & SVGA_SCREEN_HAS_ROOT)
3639	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_HAS_ROOT\n"));
3640	if (pCmd->screen.flags & SVGA_SCREEN_IS_PRIMARY)
3641	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_IS_PRIMARY\n"));
3642	if (pCmd->screen.flags & SVGA_SCREEN_FULLSCREEN_HINT)
3643	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_FULLSCREEN_HINT\n"));
3644	if (pCmd->screen.flags & SVGA_SCREEN_DEACTIVATE )
3645	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_DEACTIVATE \n"));
3646	if (pCmd->screen.flags & SVGA_SCREEN_BLANKING)
3647	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_BLANKING\n"));
3648
3649	const uint32_t uWidth = pCmd->screen.size.width;
3650	AssertBreak(0 < uWidth && uWidth <= pThis->svga.u32MaxWidth);
3651
3652	const uint32_t uHeight = pCmd->screen.size.height;
3653	AssertBreak(0 < uHeight && uHeight <= pThis->svga.u32MaxHeight);
3654
3655	const uint32_t cbWidth = uWidth * ((pThis->svga.uBpp + 7) / 8);
3656	const uint32_t cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
3657	AssertBreak(0 < cbWidth && cbWidth <= cbPitch);
3658
3659	const uint32_t uScreenOffset = pCmd->screen.backingStore.ptr.offset;
3660	AssertBreak(uScreenOffset < pThis->vram_size);
3661
3662	const uint32_t cbVram = pThis->vram_size - uScreenOffset;
3663	AssertBreak(uHeight <= cbVram / cbPitch);
3664
3665	/** @todo multi monitor support and screen object capabilities. */
3666	pThis->svga.uWidth = uWidth;
3667	pThis->svga.uHeight = uHeight;
3668	pThis->svga.uScreenOffset = uScreenOffset;
3669	vmsvgaChangeMode(pThis);
3670	break;
3671	}
3672
3673	case SVGA_CMD_DESTROY_SCREEN:
3674	{
3675	SVGAFifoCmdDestroyScreen *pCmd;
3676	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
3677	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
3678
3679	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
3680	break;
3681	}
3682	# ifdef VBOX_WITH_VMSVGA3D
3683	case SVGA_CMD_DEFINE_GMRFB:
3684	{
3685	SVGAFifoCmdDefineGMRFB *pCmd;
3686	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
3687	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
3688
3689	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
3690	pSVGAState->GMRFB.ptr = pCmd->ptr;
3691	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
3692	pSVGAState->GMRFB.format = pCmd->format;
3693	break;
3694	}
3695
3696	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3697	{
3698	uint32_t width, height;
3699	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
3700	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
3701	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
3702
3703	Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
3704
3705	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
3706	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pThis->svga.uBpp);
3707	AssertBreak(pCmd->destScreenId == 0);
3708
3709	if (pCmd->destRect.left < 0)
3710	pCmd->destRect.left = 0;
3711	if (pCmd->destRect.top < 0)
3712	pCmd->destRect.top = 0;
3713	if (pCmd->destRect.right < 0)
3714	pCmd->destRect.right = 0;
3715	if (pCmd->destRect.bottom < 0)
3716	pCmd->destRect.bottom = 0;
3717
3718	width = pCmd->destRect.right - pCmd->destRect.left;
3719	height = pCmd->destRect.bottom - pCmd->destRect.top;
3720
3721	if ( width == 0
3722	\|\| height == 0)
3723	break; /* Nothing to do. */
3724
3725	/* Clip to screen dimensions. */
3726	if (width > pThis->svga.uWidth)
3727	width = pThis->svga.uWidth;
3728	if (height > pThis->svga.uHeight)
3729	height = pThis->svga.uHeight;
3730
3731	/* srcOrigin */
3732	AssertBreak(pSVGAState->GMRFB.bytesPerLine != 0);
3733	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel != 0);
3734
3735	AssertBreak(pThis->svga.uScreenOffset < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
3736	const uint32_t cbVram = pThis->vram_size - pThis->svga.uScreenOffset;
3737
3738	const uint32_t cScanlines = cbVram / pSVGAState->GMRFB.bytesPerLine;
3739	AssertBreak(pCmd->srcOrigin.y < (int32_t)cScanlines);
3740
3741	AssertBreak(pCmd->srcOrigin.x < (int32_t)(pSVGAState->GMRFB.bytesPerLine / ((pSVGAState->GMRFB.format.s.bitsPerPixel + 7) / 8)));
3742
3743	unsigned offsetSource = (pCmd->srcOrigin.x * pSVGAState->GMRFB.format.s.bitsPerPixel) / 8 + pSVGAState->GMRFB.bytesPerLine * pCmd->srcOrigin.y;
3744	unsigned offsetDest = (pCmd->destRect.left * RT_ALIGN(pThis->svga.uBpp, 8)) / 8 + pThis->svga.cbScanline * pCmd->destRect.top;
3745	unsigned cbCopyWidth = (width * RT_ALIGN(pThis->svga.uBpp, 8)) / 8;
3746
3747	AssertBreak(offsetDest < cbVram);
3748	offsetDest += pThis->svga.uScreenOffset;
3749
3750	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM, pThis->CTX_SUFF(vram_ptr) + offsetDest, pThis->svga.cbScanline, pSVGAState->GMRFB.ptr, offsetSource, pSVGAState->GMRFB.bytesPerLine, cbCopyWidth, height);
3751	AssertRC(rc);
3752	vgaR3UpdateDisplay(pThis, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right - pCmd->destRect.left, pCmd->destRect.bottom - pCmd->destRect.top);
3753	break;
3754	}
3755
3756	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3757	{
3758	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
3759	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
3760	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
3761
3762	/* Note! This can fetch 3d render results as well!! */
3763	Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n", pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
3764	AssertFailed();
3765	break;
3766	}
3767	# endif // VBOX_WITH_VMSVGA3D
3768	case SVGA_CMD_ANNOTATION_FILL:
3769	{
3770	SVGAFifoCmdAnnotationFill *pCmd;
3771	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
3772	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
3773
3774	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
3775	pSVGAState->colorAnnotation = pCmd->color;
3776	break;
3777	}
3778
3779	case SVGA_CMD_ANNOTATION_COPY:
3780	{
3781	SVGAFifoCmdAnnotationCopy *pCmd;
3782	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
3783	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
3784
3785	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
3786	AssertFailed();
3787	break;
3788	}
3789
3790	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
3791
3792	default:
3793	# ifdef VBOX_WITH_VMSVGA3D
3794	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
3795	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
3796	{
3797	/* All 3d commands start with a common header, which defines the size of the command. */
3798	SVGA3dCmdHeader *pHdr;
3799	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
3800	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
3801	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
3802	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
3803
3804	/**
3805	* Check that the 3D command has at least a_cbMin of payload bytes after the
3806	* header. Will break out of the switch if it doesn't.
3807	*/
3808	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3809	AssertMsgBreak((a_cbMin) <= pHdr->size, ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin)))
3810	switch ((int)enmCmdId)
3811	{
3812	case SVGA_3D_CMD_SURFACE_DEFINE:
3813	{
3814	uint32_t cMipLevels;
3815	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
3816	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3817	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
3818
3819	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3820	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
3821	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
3822	# ifdef DEBUG_GMR_ACCESS
3823	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
3824	# endif
3825	break;
3826	}
3827
3828	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3829	{
3830	uint32_t cMipLevels;
3831	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
3832	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3833	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
3834
3835	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3836	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
3837	pCmd->multisampleCount, pCmd->autogenFilter,
3838	cMipLevels, (SVGA3dSize *)(pCmd + 1));
3839	break;
3840	}
3841
3842	case SVGA_3D_CMD_SURFACE_DESTROY:
3843	{
3844	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
3845	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3846	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
3847	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
3848	break;
3849	}
3850
3851	case SVGA_3D_CMD_SURFACE_COPY:
3852	{
3853	uint32_t cCopyBoxes;
3854	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
3855	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3856	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
3857
3858	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3859	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3860	break;
3861	}
3862
3863	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3864	{
3865	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
3866	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3867	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
3868
3869	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
3870	break;
3871	}
3872
3873	case SVGA_3D_CMD_SURFACE_DMA:
3874	{
3875	uint32_t cCopyBoxes;
3876	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
3877	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3878	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
3879
3880	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3881	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
3882	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3883	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
3884	break;
3885	}
3886
3887	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3888	{
3889	uint32_t cRects;
3890	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
3891	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3892	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
3893
3894	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3895	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3896	break;
3897	}
3898
3899	case SVGA_3D_CMD_CONTEXT_DEFINE:
3900	{
3901	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
3902	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3903	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
3904
3905	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
3906	break;
3907	}
3908
3909	case SVGA_3D_CMD_CONTEXT_DESTROY:
3910	{
3911	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
3912	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3913	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
3914
3915	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
3916	break;
3917	}
3918
3919	case SVGA_3D_CMD_SETTRANSFORM:
3920	{
3921	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
3922	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3923	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
3924
3925	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
3926	break;
3927	}
3928
3929	case SVGA_3D_CMD_SETZRANGE:
3930	{
3931	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
3932	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3933	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
3934
3935	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
3936	break;
3937	}
3938
3939	case SVGA_3D_CMD_SETRENDERSTATE:
3940	{
3941	uint32_t cRenderStates;
3942	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
3943	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3944	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
3945
3946	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3947	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3948	break;
3949	}
3950
3951	case SVGA_3D_CMD_SETRENDERTARGET:
3952	{
3953	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
3954	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3955	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
3956
3957	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
3958	break;
3959	}
3960
3961	case SVGA_3D_CMD_SETTEXTURESTATE:
3962	{
3963	uint32_t cTextureStates;
3964	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
3965	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3966	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
3967
3968	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3969	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3970	break;
3971	}
3972
3973	case SVGA_3D_CMD_SETMATERIAL:
3974	{
3975	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
3976	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3977	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
3978
3979	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
3980	break;
3981	}
3982
3983	case SVGA_3D_CMD_SETLIGHTDATA:
3984	{
3985	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
3986	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3987	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
3988
3989	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
3990	break;
3991	}
3992
3993	case SVGA_3D_CMD_SETLIGHTENABLED:
3994	{
3995	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
3996	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3997	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
3998
3999	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
4000	break;
4001	}
4002
4003	case SVGA_3D_CMD_SETVIEWPORT:
4004	{
4005	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4006	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4007	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4008
4009	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
4010	break;
4011	}
4012
4013	case SVGA_3D_CMD_SETCLIPPLANE:
4014	{
4015	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4016	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4017	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4018
4019	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
4020	break;
4021	}
4022
4023	case SVGA_3D_CMD_CLEAR:
4024	{
4025	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4026	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4027	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4028
4029	uint32_t cRects;
4030	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4031	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4032	break;
4033	}
4034
4035	case SVGA_3D_CMD_PRESENT:
4036	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4037	{
4038	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4039	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4040	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4041	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4042	else
4043	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4044
4045	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4046
4047	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4048	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4049	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4050	break;
4051	}
4052
4053	case SVGA_3D_CMD_SHADER_DEFINE:
4054	{
4055	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4056	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4057	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4058
4059	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4060	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4061	break;
4062	}
4063
4064	case SVGA_3D_CMD_SHADER_DESTROY:
4065	{
4066	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4067	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4068	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4069
4070	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4071	break;
4072	}
4073
4074	case SVGA_3D_CMD_SET_SHADER:
4075	{
4076	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4077	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4078	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4079
4080	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4081	break;
4082	}
4083
4084	case SVGA_3D_CMD_SET_SHADER_CONST:
4085	{
4086	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4087	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4088	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4089
4090	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4091	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4092	break;
4093	}
4094
4095	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4096	{
4097	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4098	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4099	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4100
4101	uint32_t cVertexDivisor = (pHdr->size - sizeof(pCmd) - sizeof(SVGA3dVertexDecl) pCmd->numVertexDecls - sizeof(SVGA3dPrimitiveRange) * pCmd->numRanges) / sizeof(uint32_t);
4102	Assert(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4103	Assert(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4104	Assert(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4105
4106	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4107	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange ) (&pVertexDecl[pCmd->numVertexDecls]);
4108	SVGA3dVertexDivisor pVertexDivisor = (cVertexDivisor) ? (SVGA3dVertexDivisor )(&pNumRange[pCmd->numRanges]) : NULL;
4109
4110	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4111	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges, pNumRange, cVertexDivisor, pVertexDivisor);
4112	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4113	break;
4114	}
4115
4116	case SVGA_3D_CMD_SETSCISSORRECT:
4117	{
4118	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4119	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4120	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4121
4122	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4123	break;
4124	}
4125
4126	case SVGA_3D_CMD_BEGIN_QUERY:
4127	{
4128	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4129	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4130	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4131
4132	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4133	break;
4134	}
4135
4136	case SVGA_3D_CMD_END_QUERY:
4137	{
4138	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4139	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4140	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4141
4142	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4143	break;
4144	}
4145
4146	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4147	{
4148	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4149	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4150	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4151
4152	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4153	break;
4154	}
4155
4156	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4157	{
4158	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4159	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4160	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4161
4162	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4163	break;
4164	}
4165
4166	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4167	/* context id + surface id? */
4168	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4169	break;
4170	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4171	/* context id + surface id? */
4172	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4173	break;
4174
4175	default:
4176	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4177	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4178	break;
4179	}
4180	}
4181	else
4182	# endif // VBOX_WITH_VMSVGA3D
4183	{
4184	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4185	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4186	}
4187	}
4188
4189	/* Go to the next slot */
4190	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4191	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4192	if (offCurrentCmd >= offFifoMax)
4193	{
4194	offCurrentCmd -= offFifoMax - offFifoMin;
4195	Assert(offCurrentCmd >= offFifoMin);
4196	Assert(offCurrentCmd < offFifoMax);
4197	}
4198	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4199	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4200
4201	/*
4202	* Raise IRQ if required. Must enter the critical section here
4203	* before making final decisions here, otherwise cubebench and
4204	* others may end up waiting forever.
4205	*/
4206	if ( u32IrqStatus
4207	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4208	{
4209	int rc2 = PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
4210	AssertRC(rc2);
4211
4212	/* FIFO progress might trigger an interrupt. */
4213	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4214	{
4215	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4216	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4217	}
4218
4219	/* Unmasked IRQ pending? */
4220	if (pThis->svga.u32IrqMask & u32IrqStatus)
4221	{
4222	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4223	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4224	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4225	}
4226
4227	PDMCritSectLeave(&pThis->CritSect);
4228	}
4229	}
4230
4231	/* If really done, clear the busy flag. */
4232	if (fDone)
4233	{
4234	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4235	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4236	}
4237	}
4238
4239	/*
4240	* Free the bounce buffer. (There are no returns above!)
4241	*/
4242	RTMemFree(pbBounceBuf);
4243
4244	return VINF_SUCCESS;
4245	}
4246
4247	/**
4248	* Free the specified GMR
4249	*
4250	* @param pThis VGA device instance data.
4251	* @param idGMR GMR id
4252	*/
4253	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4254	{
4255	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4256
4257	/* Free the old descriptor if present. */
4258	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4259	if ( pGMR->numDescriptors
4260	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4261	{
4262	# ifdef DEBUG_GMR_ACCESS
4263	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4264	# endif
4265
4266	Assert(pGMR->paDesc);
4267	RTMemFree(pGMR->paDesc);
4268	pGMR->paDesc = NULL;
4269	pGMR->numDescriptors = 0;
4270	pGMR->cbTotal = 0;
4271	pGMR->cMaxPages = 0;
4272	}
4273	Assert(!pGMR->cMaxPages);
4274	Assert(!pGMR->cbTotal);
4275	}
4276
4277	/**
4278	* Copy from a GMR to host memory or vice versa
4279	*
4280	* @returns VBox status code.
4281	* @param pThis VGA device instance data.
4282	* @param enmTransferType Transfer type (read/write)
4283	* @param pbDst Host destination pointer
4284	* @param cbDestPitch Destination buffer pitch
4285	* @param src GMR description
4286	* @param offSrc Source buffer offset
4287	* @param cbSrcPitch Source buffer pitch
4288	* @param cbWidth Source width in bytes
4289	* @param cHeight Source height
4290	*/
4291	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType, uint8_t *pbDst, int32_t cbDestPitch,
4292	SVGAGuestPtr src, uint32_t offSrc, int32_t cbSrcPitch, uint32_t cbWidth, uint32_t cHeight)
4293	{
4294	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4295	PGMR pGMR;
4296	int rc;
4297	PVMSVGAGMRDESCRIPTOR pDesc;
4298	unsigned offDesc = 0;
4299
4300	Log(("vmsvgaGMRTransfer: gmr=%x offset=%x pitch=%d cbWidth=%d cHeight=%d; src offset=%d src pitch=%d\n",
4301	src.gmrId, src.offset, cbDestPitch, cbWidth, cHeight, offSrc, cbSrcPitch));
4302	Assert(cbWidth && cHeight);
4303
4304	const uint32_t cbGmrScanline = cbSrcPitch > 0 ? cbSrcPitch : -cbSrcPitch;
4305
4306	uint32_t cbGmrTotal; /* The GMR size in bytes. */
4307	if (src.gmrId == SVGA_GMR_FRAMEBUFFER)
4308	{
4309	pGMR = NULL;
4310	cbGmrTotal = pThis->vram_size;
4311	}
4312	else
4313	{
4314	AssertReturn(src.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4315	pGMR = &pSVGAState->paGMR[src.gmrId];
4316	cbGmrTotal = pGMR->cbTotal;
4317	}
4318
4319	/* Check GMR parameters */
4320	AssertMsgReturn(src.offset < cbGmrTotal,
4321	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbGmrTotal=%#x\n",
4322	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, cbGmrTotal),
4323	VERR_INVALID_PARAMETER);
4324	AssertMsgReturn(offSrc < cbGmrTotal - src.offset,
4325	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbGmrTotal=%#x\n",
4326	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, cbGmrTotal),
4327	VERR_INVALID_PARAMETER);
4328	AssertMsgReturn(cbGmrScanline != 0,
4329	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbGmrTotal=%#x\n",
4330	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, cbGmrTotal),
4331	VERR_INVALID_PARAMETER);
4332	AssertMsgReturn(cbWidth <= cbGmrScanline,
4333	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbGmrTotal=%#x\n",
4334	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, cbGmrTotal),
4335	VERR_INVALID_PARAMETER);
4336
4337	offSrc += src.offset; /* Actual offset in the GMR, where the first scanline will be copied. */
4338
4339	AssertMsgReturn(cbWidth <= cbGmrTotal - offSrc,
4340	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbGmrTotal=%#x\n",
4341	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, cbGmrTotal),
4342	VERR_INVALID_PARAMETER);
4343
4344	uint32_t cbGmrLeft = cbSrcPitch > 0 ? cbGmrTotal - offSrc : offSrc + cbWidth;
4345
4346	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4347	uint32_t cbLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4348	if (cbWidth <= cbLastScanline)
4349	++cGmrScanlines;
4350
4351	if (cHeight > cGmrScanlines)
4352	cHeight = cGmrScanlines;
4353
4354	AssertMsgReturn(cHeight > 0,
4355	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbGmrTotal=%#x\n",
4356	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, cbGmrTotal),
4357	VERR_INVALID_PARAMETER);
4358
4359	/* Shortcut for the framebuffer. */
4360	if (src.gmrId == SVGA_GMR_FRAMEBUFFER)
4361	{
4362	uint8_t *pSrc = pThis->CTX_SUFF(vram_ptr) + offSrc;
4363
4364	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4365	{
4366	/* switch src & dest */
4367	uint8_t *pTemp = pbDst;
4368	int32_t cbTempPitch = cbDestPitch;
4369
4370	pbDst = pSrc;
4371	pSrc = pTemp;
4372
4373	cbDestPitch = cbSrcPitch;
4374	cbSrcPitch = cbTempPitch;
4375	}
4376
4377	if ( pThis->svga.cbScanline == (uint32_t)cbDestPitch
4378	&& cbWidth == (uint32_t)cbDestPitch
4379	&& cbSrcPitch == cbDestPitch)
4380	{
4381	memcpy(pbDst, pSrc, cbWidth * cHeight);
4382	}
4383	else
4384	{
4385	for(uint32_t i = 0; i < cHeight; i++)
4386	{
4387	memcpy(pbDst, pSrc, cbWidth);
4388
4389	pbDst += cbDestPitch;
4390	pSrc += cbSrcPitch;
4391	}
4392	}
4393	return VINF_SUCCESS;
4394	}
4395
4396	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
4397	pDesc = pGMR->paDesc;
4398
4399	for (uint32_t i = 0; i < cHeight; i++)
4400	{
4401	uint32_t cbCurrentWidth = cbWidth;
4402	uint32_t offCurrent = offSrc;
4403	uint8_t *pCurrentDest = pbDst;
4404
4405	/* Find the right descriptor */
4406	while (offDesc + pDesc->numPages * PAGE_SIZE <= offCurrent)
4407	{
4408	offDesc += pDesc->numPages * PAGE_SIZE;
4409	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
4410	pDesc++;
4411	}
4412
4413	while (cbCurrentWidth)
4414	{
4415	uint32_t cbToCopy;
4416
4417	if (offCurrent + cbCurrentWidth <= offDesc + pDesc->numPages * PAGE_SIZE)
4418	{
4419	cbToCopy = cbCurrentWidth;
4420	}
4421	else
4422	{
4423	cbToCopy = (offDesc + pDesc->numPages * PAGE_SIZE - offCurrent);
4424	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
4425	}
4426
4427	LogFlow(("vmsvgaGMRTransfer: %s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", pDesc->GCPhys + offCurrent - offDesc));
4428
4429	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
4430	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
4431	else
4432	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
4433	AssertRCBreak(rc);
4434
4435	cbCurrentWidth -= cbToCopy;
4436	offCurrent += cbToCopy;
4437	pCurrentDest += cbToCopy;
4438
4439	/* Go to the next descriptor if there's anything left. */
4440	if (cbCurrentWidth)
4441	{
4442	offDesc += pDesc->numPages * PAGE_SIZE;
4443	pDesc++;
4444	}
4445	}
4446
4447	offSrc += cbSrcPitch;
4448	pbDst += cbDestPitch;
4449	}
4450
4451	return VINF_SUCCESS;
4452	}
4453
4454	/**
4455	* Unblock the FIFO I/O thread so it can respond to a state change.
4456	*
4457	* @returns VBox status code.
4458	* @param pDevIns The VGA device instance.
4459	* @param pThread The send thread.
4460	*/
4461	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4462	{
4463	RT_NOREF(pDevIns);
4464	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
4465	Log(("vmsvgaFIFOLoopWakeUp\n"));
4466	return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
4467	}
4468
4469	/**
4470	* Enables or disables dirty page tracking for the framebuffer
4471	*
4472	* @param pThis VGA device instance data.
4473	* @param fTraces Enable/disable traces
4474	*/
4475	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
4476	{
4477	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
4478	&& !fTraces)
4479	{
4480	//Assert(pThis->svga.fTraces);
4481	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
4482	return;
4483	}
4484
4485	pThis->svga.fTraces = fTraces;
4486	if (pThis->svga.fTraces)
4487	{
4488	unsigned cbFrameBuffer = pThis->vram_size;
4489
4490	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
4491	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
4492	{
4493	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
4494	Assert(pThis->svga.cbScanline);
4495	#endif
4496	/* Hardware enabled; return real framebuffer size .*/
4497	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
4498	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
4499	}
4500
4501	if (!pThis->svga.fVRAMTracking)
4502	{
4503	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
4504	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
4505	pThis->svga.fVRAMTracking = true;
4506	}
4507	}
4508	else
4509	{
4510	if (pThis->svga.fVRAMTracking)
4511	{
4512	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
4513	vgaR3UnregisterVRAMHandler(pThis);
4514	pThis->svga.fVRAMTracking = false;
4515	}
4516	}
4517	}
4518
4519	/**
4520	* @callback_method_impl{FNPCIIOREGIONMAP}
4521	*/
4522	DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
4523	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
4524	{
4525	int rc;
4526	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4527
4528	Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
4529	if (enmType == PCI_ADDRESS_SPACE_IO)
4530	{
4531	AssertReturn(iRegion == 0, VERR_INTERNAL_ERROR);
4532	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
4533	vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr /, NULL / InStr */, "VMSVGA");
4534	if (RT_FAILURE(rc))
4535	return rc;
4536	if (pThis->fR0Enabled)
4537	{
4538	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
4539	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
4540	if (RT_FAILURE(rc))
4541	return rc;
4542	}
4543	if (pThis->fGCEnabled)
4544	{
4545	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
4546	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
4547	if (RT_FAILURE(rc))
4548	return rc;
4549	}
4550
4551	pThis->svga.BasePort = GCPhysAddress;
4552	Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
4553	}
4554	else
4555	{
4556	AssertReturn(iRegion == 2 && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
4557	if (GCPhysAddress != NIL_RTGCPHYS)
4558	{
4559	/*
4560	* Mapping the FIFO RAM.
4561	*/
4562	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
4563	rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
4564	AssertRC(rc);
4565
4566	# ifdef DEBUG_FIFO_ACCESS
4567	if (RT_SUCCESS(rc))
4568	{
4569	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress, GCPhysAddress + (pThis->svga.cbFIFO - 1),
4570	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
4571	"VMSVGA FIFO");
4572	AssertRC(rc);
4573	}
4574	# endif
4575	if (RT_SUCCESS(rc))
4576	{
4577	pThis->svga.GCPhysFIFO = GCPhysAddress;
4578	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
4579	}
4580	}
4581	else
4582	{
4583	Assert(pThis->svga.GCPhysFIFO);
4584	# ifdef DEBUG_FIFO_ACCESS
4585	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
4586	AssertRC(rc);
4587	# endif
4588	pThis->svga.GCPhysFIFO = 0;
4589	}
4590
4591	}
4592	return VINF_SUCCESS;
4593	}
4594
4595	# ifdef VBOX_WITH_VMSVGA3D
4596
4597	/**
4598	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
4599	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
4600	*
4601	* @param pThis The VGA device instance data.
4602	* @param sid Either UINT32_MAX or the ID of a specific
4603	* surface. If UINT32_MAX is used, all surfaces
4604	* are processed.
4605	*/
4606	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
4607	{
4608	vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
4609	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
4610	}
4611
4612
4613	/**
4614	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
4615	*/
4616	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4617	{
4618	/* There might be a specific surface ID at the start of the
4619	arguments, if not show all surfaces. */
4620	uint32_t sid = UINT32_MAX;
4621	if (pszArgs)
4622	pszArgs = RTStrStripL(pszArgs);
4623	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
4624	sid = RTStrToUInt32(pszArgs);
4625
4626	/* Verbose or terse display, we default to verbose. */
4627	bool fVerbose = true;
4628	if (RTStrIStr(pszArgs, "terse"))
4629	fVerbose = false;
4630
4631	/* The size of the ascii art (x direction, y is 3/4 of x). */
4632	uint32_t cxAscii = 80;
4633	if (RTStrIStr(pszArgs, "gigantic"))
4634	cxAscii = 300;
4635	else if (RTStrIStr(pszArgs, "huge"))
4636	cxAscii = 180;
4637	else if (RTStrIStr(pszArgs, "big"))
4638	cxAscii = 132;
4639	else if (RTStrIStr(pszArgs, "normal"))
4640	cxAscii = 80;
4641	else if (RTStrIStr(pszArgs, "medium"))
4642	cxAscii = 64;
4643	else if (RTStrIStr(pszArgs, "small"))
4644	cxAscii = 48;
4645	else if (RTStrIStr(pszArgs, "tiny"))
4646	cxAscii = 24;
4647
4648	/* Y invert the image when producing the ASCII art. */
4649	bool fInvY = false;
4650	if (RTStrIStr(pszArgs, "invy"))
4651	fInvY = true;
4652
4653	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
4654	}
4655
4656
4657	/**
4658	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
4659	*/
4660	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4661	{
4662	/* pszArg = "sid[>dir]"
4663	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
4664	*/
4665	char *pszBitmapPath = NULL;
4666	uint32_t sid = UINT32_MAX;
4667	if (pszArgs)
4668	pszArgs = RTStrStripL(pszArgs);
4669	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
4670	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
4671	if ( pszBitmapPath
4672	&& *pszBitmapPath == '>')
4673	++pszBitmapPath;
4674
4675	const bool fVerbose = true;
4676	const uint32_t cxAscii = 0; /* No ASCII */
4677	const bool fInvY = false; /* Do not invert. */
4678	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
4679	}
4680
4681
4682	/**
4683	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
4684	*/
4685	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4686	{
4687	/* There might be a specific surface ID at the start of the
4688	arguments, if not show all contexts. */
4689	uint32_t sid = UINT32_MAX;
4690	if (pszArgs)
4691	pszArgs = RTStrStripL(pszArgs);
4692	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
4693	sid = RTStrToUInt32(pszArgs);
4694
4695	/* Verbose or terse display, we default to verbose. */
4696	bool fVerbose = true;
4697	if (RTStrIStr(pszArgs, "terse"))
4698	fVerbose = false;
4699
4700	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
4701	}
4702
4703	# endif /* VBOX_WITH_VMSVGA3D */
4704
4705	/**
4706	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
4707	*/
4708	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4709	{
4710	RT_NOREF(pszArgs);
4711	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4712	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4713
4714	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
4715	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
4716	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
4717	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
4718	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
4719	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
4720	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
4721	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
4722	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
4723	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
4724	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
4725	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
4726	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x\n", pThis->svga.u32PitchLock);
4727	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
4728	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
4729	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
4730	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
4731	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
4732	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
4733	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
4734	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
4735	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
4736
4737	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
4738	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
4739	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
4740	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
4741
4742	# ifdef VBOX_WITH_VMSVGA3D
4743	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
4744	pHlp->pfnPrintf(pHlp, "Host windows ID: %#RX64\n", pThis->svga.u64HostWindowId);
4745	if (pThis->svga.u64HostWindowId != 0)
4746	vmsvga3dInfoHostWindow(pHlp, pThis->svga.u64HostWindowId);
4747	# endif
4748	}
4749
4750
4751	/**
4752	* @copydoc FNSSMDEVLOADEXEC
4753	*/
4754	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4755	{
4756	RT_NOREF(uPass);
4757	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4758	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4759	int rc;
4760
4761	/* Load our part of the VGAState */
4762	rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
4763	AssertRCReturn(rc, rc);
4764
4765	/* Load the VGA framebuffer. */
4766	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
4767	uint32_t cbVgaFramebuffer = _32K;
4768	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
4769	{
4770	rc = SSMR3GetU32(pSSM, &cbVgaFramebuffer);
4771	AssertRCReturn(rc, rc);
4772	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
4773	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
4774	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
4775	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
4776	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
4777	}
4778	rc = SSMR3GetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
4779	AssertRCReturn(rc, rc);
4780	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
4781	SSMR3Skip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
4782	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
4783	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
4784
4785	/* Load the VMSVGA state. */
4786	rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
4787	AssertRCReturn(rc, rc);
4788
4789	/* Load the active cursor bitmaps. */
4790	if (pSVGAState->Cursor.fActive)
4791	{
4792	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
4793	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
4794
4795	rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
4796	AssertRCReturn(rc, rc);
4797	}
4798
4799	/* Load the GMR state. */
4800	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
4801	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
4802	{
4803	rc = SSMR3GetU32(pSSM, &cGMR);
4804	AssertRCReturn(rc, rc);
4805	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
4806	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
4807	("cGMR=%#x - expected 256B..1MB\n", cGMR),
4808	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
4809	}
4810
4811	if (pThis->svga.cGMR != cGMR)
4812	{
4813	/* Reallocate GMR array. */
4814	Assert(pSVGAState->paGMR != NULL);
4815	RTMemFree(pSVGAState->paGMR);
4816	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
4817	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
4818	pThis->svga.cGMR = cGMR;
4819	}
4820
4821	for (uint32_t i = 0; i < cGMR; ++i)
4822	{
4823	PGMR pGMR = &pSVGAState->paGMR[i];
4824
4825	rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
4826	AssertRCReturn(rc, rc);
4827
4828	if (pGMR->numDescriptors)
4829	{
4830	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
4831	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
4832	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
4833
4834	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
4835	{
4836	rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
4837	AssertRCReturn(rc, rc);
4838	}
4839	}
4840	}
4841
4842	# ifdef VBOX_WITH_VMSVGA3D
4843	if (pThis->svga.f3DEnabled)
4844	{
4845	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
4846	vmsvga3dPowerOn(pThis);
4847	# endif
4848
4849	VMSVGA_STATE_LOAD LoadState;
4850	LoadState.pSSM = pSSM;
4851	LoadState.uVersion = uVersion;
4852	LoadState.uPass = uPass;
4853	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
4854	AssertLogRelRCReturn(rc, rc);
4855	}
4856	# endif
4857
4858	return VINF_SUCCESS;
4859	}
4860
4861	/**
4862	* Reinit the video mode after the state has been loaded.
4863	*/
4864	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
4865	{
4866	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4867	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4868
4869	pThis->last_bpp = VMSVGA_VAL_UNINITIALIZED; /* force mode reset */
4870	vmsvgaChangeMode(pThis);
4871
4872	/* Set the active cursor. */
4873	if (pSVGAState->Cursor.fActive)
4874	{
4875	int rc;
4876
4877	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
4878	true,
4879	true,
4880	pSVGAState->Cursor.xHotspot,
4881	pSVGAState->Cursor.yHotspot,
4882	pSVGAState->Cursor.width,
4883	pSVGAState->Cursor.height,
4884	pSVGAState->Cursor.pData);
4885	AssertRC(rc);
4886	}
4887	return VINF_SUCCESS;
4888	}
4889
4890	/**
4891	* @copydoc FNSSMDEVSAVEEXEC
4892	*/
4893	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4894	{
4895	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4896	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4897	int rc;
4898
4899	/* Save our part of the VGAState */
4900	rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
4901	AssertLogRelRCReturn(rc, rc);
4902
4903	/* Save the framebuffer backup. */
4904	rc = SSMR3PutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
4905	rc = SSMR3PutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
4906	AssertLogRelRCReturn(rc, rc);
4907
4908	/* Save the VMSVGA state. */
4909	rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
4910	AssertLogRelRCReturn(rc, rc);
4911
4912	/* Save the active cursor bitmaps. */
4913	if (pSVGAState->Cursor.fActive)
4914	{
4915	rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
4916	AssertLogRelRCReturn(rc, rc);
4917	}
4918
4919	/* Save the GMR state */
4920	rc = SSMR3PutU32(pSSM, pThis->svga.cGMR);
4921	AssertLogRelRCReturn(rc, rc);
4922	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
4923	{
4924	PGMR pGMR = &pSVGAState->paGMR[i];
4925
4926	rc = SSMR3PutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
4927	AssertLogRelRCReturn(rc, rc);
4928
4929	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
4930	{
4931	rc = SSMR3PutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
4932	AssertLogRelRCReturn(rc, rc);
4933	}
4934	}
4935
4936	# ifdef VBOX_WITH_VMSVGA3D
4937	/*
4938	* Must save the 3d state in the FIFO thread.
4939	*/
4940	if (pThis->svga.f3DEnabled)
4941	{
4942	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
4943	AssertLogRelRCReturn(rc, rc);
4944	}
4945	# endif
4946	return VINF_SUCCESS;
4947	}
4948
4949	/**
4950	* Destructor for PVMSVGAR3STATE structure.
4951	*
4952	* @param pThis The VGA instance.
4953	* @param pSVGAState Pointer to the structure. It is not deallocated.
4954	*/
4955	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
4956	{
4957	#ifndef VMSVGA_USE_EMT_HALT_CODE
4958	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
4959	{
4960	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
4961	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
4962	}
4963	#endif
4964
4965	if (pSVGAState->Cursor.fActive)
4966	{
4967	RTMemFree(pSVGAState->Cursor.pData);
4968	pSVGAState->Cursor.pData = NULL;
4969	pSVGAState->Cursor.fActive = false;
4970	}
4971
4972	if (pSVGAState->paGMR)
4973	{
4974	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
4975	if (pSVGAState->paGMR[i].paDesc)
4976	RTMemFree(pSVGAState->paGMR[i].paDesc);
4977
4978	RTMemFree(pSVGAState->paGMR);
4979	pSVGAState->paGMR = NULL;
4980	}
4981	}
4982
4983	/**
4984	* Constructor for PVMSVGAR3STATE structure.
4985	*
4986	* @returns VBox status code.
4987	* @param pThis The VGA instance.
4988	* @param pSVGAState Pointer to the structure. It is already allocated.
4989	*/
4990	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
4991	{
4992	int rc = VINF_SUCCESS;
4993	RT_ZERO(*pSVGAState);
4994
4995	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
4996	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
4997
4998	#ifndef VMSVGA_USE_EMT_HALT_CODE
4999	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5000	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5001	AssertRCReturn(rc, rc);
5002	#endif
5003
5004	return rc;
5005	}
5006
5007	/**
5008	* Resets the SVGA hardware state
5009	*
5010	* @returns VBox status code.
5011	* @param pDevIns The device instance.
5012	*/
5013	int vmsvgaReset(PPDMDEVINS pDevIns)
5014	{
5015	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5016	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5017
5018	/* Reset before init? */
5019	if (!pSVGAState)
5020	return VINF_SUCCESS;
5021
5022	Log(("vmsvgaReset\n"));
5023
5024	/* Reset the FIFO processing as well as the 3d state (if we have one). */
5025	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
5026	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
5027
5028	/* Reset other stuff. */
5029	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5030	RT_ZERO(pThis->svga.au32ScratchRegion);
5031
5032	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
5033	vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
5034
5035	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5036
5037	/* Register caps. */
5038	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5039	# ifdef VBOX_WITH_VMSVGA3D
5040	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5041	# endif
5042
5043	/* Setup FIFO capabilities. */
5044	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5045
5046	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5047	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5048
5049	/* VRAM tracking is enabled by default during bootup. */
5050	pThis->svga.fVRAMTracking = true;
5051	pThis->svga.fEnabled = false;
5052
5053	/* Invalidate current settings. */
5054	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5055	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5056	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5057	pThis->svga.cbScanline = 0;
5058
5059	return rc;
5060	}
5061
5062	/**
5063	* Cleans up the SVGA hardware state
5064	*
5065	* @returns VBox status code.
5066	* @param pDevIns The device instance.
5067	*/
5068	int vmsvgaDestruct(PPDMDEVINS pDevIns)
5069	{
5070	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5071
5072	/*
5073	* Ask the FIFO thread to terminate the 3d state and then terminate it.
5074	*/
5075	if (pThis->svga.pFIFOIOThread)
5076	{
5077	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
5078	AssertLogRelRC(rc);
5079
5080	rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
5081	AssertLogRelRC(rc);
5082	pThis->svga.pFIFOIOThread = NULL;
5083	}
5084
5085	/*
5086	* Destroy the special SVGA state.
5087	*/
5088	if (pThis->svga.pSvgaR3State)
5089	{
5090	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
5091
5092	RTMemFree(pThis->svga.pSvgaR3State);
5093	pThis->svga.pSvgaR3State = NULL;
5094	}
5095
5096	/*
5097	* Free our resources residing in the VGA state.
5098	*/
5099	if (pThis->svga.pbVgaFrameBufferR3)
5100	{
5101	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
5102	pThis->svga.pbVgaFrameBufferR3 = NULL;
5103	}
5104	if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
5105	{
5106	RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
5107	pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
5108	}
5109	if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
5110	{
5111	SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5112	pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
5113	}
5114
5115	return VINF_SUCCESS;
5116	}
5117
5118	/**
5119	* Initialize the SVGA hardware state
5120	*
5121	* @returns VBox status code.
5122	* @param pDevIns The device instance.
5123	*/
5124	int vmsvgaInit(PPDMDEVINS pDevIns)
5125	{
5126	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5127	PVMSVGAR3STATE pSVGAState;
5128	PVM pVM = PDMDevHlpGetVM(pDevIns);
5129	int rc;
5130
5131	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5132	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
5133
5134	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
5135
5136	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
5137	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
5138	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
5139
5140	/* Create event semaphore. */
5141	pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
5142
5143	rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
5144	if (RT_FAILURE(rc))
5145	{
5146	Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
5147	return rc;
5148	}
5149
5150	/* Create event semaphore. */
5151	rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
5152	if (RT_FAILURE(rc))
5153	{
5154	Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
5155	return rc;
5156	}
5157
5158	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
5159	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
5160
5161	rc = vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
5162	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
5163
5164	pSVGAState = pThis->svga.pSvgaR3State;
5165
5166	/* Register caps. */
5167	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5168	# ifdef VBOX_WITH_VMSVGA3D
5169	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5170	# endif
5171
5172	/* Setup FIFO capabilities. */
5173	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5174
5175	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5176	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5177
5178	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
5179	# ifdef VBOX_WITH_VMSVGA3D
5180	if (pThis->svga.f3DEnabled)
5181	{
5182	rc = vmsvga3dInit(pThis);
5183	if (RT_FAILURE(rc))
5184	{
5185	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
5186	pThis->svga.f3DEnabled = false;
5187	}
5188	}
5189	# endif
5190	/* VRAM tracking is enabled by default during bootup. */
5191	pThis->svga.fVRAMTracking = true;
5192
5193	/* Invalidate current settings. */
5194	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5195	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5196	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5197	pThis->svga.cbScanline = 0;
5198
5199	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
5200	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
5201	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
5202	{
5203	pThis->svga.u32MaxWidth -= 256;
5204	pThis->svga.u32MaxHeight -= 256;
5205	}
5206	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
5207
5208	# ifdef DEBUG_GMR_ACCESS
5209	/* Register the GMR access handler type. */
5210	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
5211	vmsvgaR3GMRAccessHandler,
5212	NULL, NULL, NULL,
5213	NULL, NULL, NULL,
5214	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
5215	AssertRCReturn(rc, rc);
5216	# endif
5217	# ifdef DEBUG_FIFO_ACCESS
5218	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_ALL,
5219	vmsvgaR3FIFOAccessHandler,
5220	NULL, NULL, NULL,
5221	NULL, NULL, NULL,
5222	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
5223	AssertRCReturn(rc, rc);
5224	#endif
5225
5226	/* Create the async IO thread. */
5227	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
5228	RTTHREADTYPE_IO, "VMSVGA FIFO");
5229	if (RT_FAILURE(rc))
5230	{
5231	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
5232	return rc;
5233	}
5234
5235	/*
5236	* Statistics.
5237	*/
5238	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dActivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dActivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_ACTIVATE_SURFACE");
5239	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dBeginQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dBeginQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_BEGIN_QUERY");
5240	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dClear, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dClear", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CLEAR");
5241	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DEFINE");
5242	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DESTROY");
5243	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDeactivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDeactivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DEACTIVATE_SURFACE");
5244	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitives, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDrawPrimitives", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DRAW_PRIMITIVES");
5245	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitivesProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dDrawPrimitivesProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
5246	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dEndQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dEndQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_END_QUERY");
5247	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dGenerateMipmaps, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dGenerateMipmaps", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_GENERATE_MIPMAPS");
5248	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresent, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresent", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT");
5249	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresentReadBack, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresentReadBack", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT_READBACK");
5250	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dPresentProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dPresentProfBoth", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
5251	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetClipPlane, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetClipPlane", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETCLIPPLANE");
5252	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightData, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightData", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTDATA");
5253	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightEnable, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightEnable", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTENABLE");
5254	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetMaterial, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetMaterial", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETMATERIAL");
5255	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERSTATE");
5256	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderTarget, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderTarget", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERTARGET");
5257	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetScissorRect, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetScissorRect", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETSCISSORRECT");
5258	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShader, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShader", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER");
5259	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShaderConst, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShaderConst", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER_CONST");
5260	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTextureState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTextureState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTEXTURESTATE");
5261	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTransform, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTransform", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTRANSFORM");
5262	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetViewPort, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetViewPort", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETVIEWPORT");
5263	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetZRange, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetZRange", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETZRANGE");
5264	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DEFINE");
5265	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DESTROY");
5266	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceCopy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_COPY");
5267	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE");
5268	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefineV2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefineV2", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE_V2");
5269	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DESTROY");
5270	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDma, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDma", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DMA");
5271	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDmaProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dSurfaceDmaProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
5272	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceScreen", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_SCREEN");
5273	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceStretchBlt, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceStretchBlt", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_STRETCHBLT");
5274	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dWaitForQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dWaitForQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_WAIT_FOR_QUERY");
5275	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationCopy", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_COPY");
5276	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationFill, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationFill", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_FILL");
5277	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitGmrFbToScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitGmrFbToScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
5278	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitScreentoGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitScreentoGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
5279	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineAlphaCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineAlphaCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_ALPHA_CURSOR");
5280	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_CURSOR");
5281	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMR2");
5282	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Free, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Free", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
5283	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
5284	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMRFB");
5285	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_SCREEN");
5286	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDestroyScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DestroyScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DESTROY_SCREEN");
5287	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdEscape, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Escape", STAMUNIT_OCCURENCES, "SVGA_CMD_ESCAPE");
5288	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdFence, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Fence", STAMUNIT_OCCURENCES, "SVGA_CMD_FENCE");
5289	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdInvalidCmd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/InvalidCmd", STAMUNIT_OCCURENCES, "SVGA_CMD_INVALID_CMD");
5290	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_REMAP_GMR2.");
5291	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
5292	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdate, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Update", STAMUNIT_OCCURENCES, "SVGA_CMD_UPATE");
5293	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdateVerbose, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/UpdateVerbose", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE_VERBOSE");
5294
5295	STAM_REL_REG(pVM, &pSVGAState->StatR3RegConfigDoneWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE writes");
5296	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_DESCRIPTOR writes");
5297	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Errors", STAMUNIT_OCCURENCES, "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
5298	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrFree, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Free", STAMUNIT_OCCURENCES, "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
5299	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL writes.");
5300	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY writes.");
5301	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX writes.");
5302	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH writes.");
5303	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT writes.");
5304	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID writes.");
5305	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
5306	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X writes.");
5307	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y writes.");
5308	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH writes.");
5309	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE writes.");
5310	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID writes.");
5311	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID writes.");
5312	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT writes.");
5313	STAM_REL_REG(pVM, &pThis->svga.StatRegIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ID writes.");
5314	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskWrite", STAMUNIT_OCCURENCES, "SVGA_REG_IRQMASK writes.");
5315	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS writes.");
5316	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
5317	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteWrite", STAMUNIT_OCCURENCES, "SVGA_PALETTE_XXXX writes.");
5318	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK writes.");
5319	STAM_REL_REG(pVM, &pThis->svga.StatRegPseudoColorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PseudoColorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR writes.");
5320	STAM_REL_REG(pVM, &pThis->svga.StatRegReadOnlyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ReadOnlyWrite", STAMUNIT_OCCURENCES, "Read-only SVGA_REG_XXXX writes.");
5321	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_XXXX writes.");
5322	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC writes.");
5323	STAM_REL_REG(pVM, &pThis->svga.StatRegTopWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TOP writes.");
5324	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES writes.");
5325	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownWrite", STAMUNIT_OCCURENCES, "Writes to unknown register.");
5326	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH writes.");
5327
5328	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL reads.");
5329	STAM_REL_REG(pVM, &pThis->svga.StatRegBlueMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BlueMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_BLUE_MASK reads.");
5330	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyRead", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY reads.");
5331	STAM_REL_REG(pVM, &pThis->svga.StatRegBytesPerLineRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BytesPerLineRead", STAMUNIT_OCCURENCES, "SVGA_REG_BYTES_PER_LINE reads.");
5332	STAM_REL_REG(pVM, &pThis->svga.StatRegCapabilitesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CapabilitesRead", STAMUNIT_OCCURENCES, "SVGA_REG_CAPABILITIES reads.");
5333	STAM_REL_REG(pVM, &pThis->svga.StatRegConfigDoneRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneRead", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE reads.");
5334	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxRead", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX reads.");
5335	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH reads.");
5336	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT reads.");
5337	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID reads.");
5338	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
5339	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X reads.");
5340	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y reads.");
5341	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH reads.");
5342	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableRead", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE reads.");
5343	STAM_REL_REG(pVM, &pThis->svga.StatRegFbOffsetRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbOffsetRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_OFFSET reads.");
5344	STAM_REL_REG(pVM, &pThis->svga.StatRegFbSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_SIZE reads.");
5345	STAM_REL_REG(pVM, &pThis->svga.StatRegFbStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_START reads.");
5346	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID reads.");
5347	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxDescriptorLengthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxDescriptorLengthRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
5348	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxIdsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxIdsRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_IDS reads.");
5349	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrsMaxPagesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrsMaxPagesRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMRS_MAX_PAGES reads.");
5350	STAM_REL_REG(pVM, &pThis->svga.StatRegGreenMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GreenMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_GREEN_MASK reads.");
5351	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID reads.");
5352	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT reads.");
5353	STAM_REL_REG(pVM, &pThis->svga.StatRegHostBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HostBitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
5354	STAM_REL_REG(pVM, &pThis->svga.StatRegIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdRead", STAMUNIT_OCCURENCES, "SVGA_REG_ID reads.");
5355	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_IRQ_MASK reads.");
5356	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_HEIGHT reads.");
5357	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_WIDTH reads.");
5358	STAM_REL_REG(pVM, &pThis->svga.StatRegMemorySizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemorySizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEMORY_SIZE reads.");
5359	STAM_REL_REG(pVM, &pThis->svga.StatRegMemRegsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemRegsRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_REGS reads.");
5360	STAM_REL_REG(pVM, &pThis->svga.StatRegMemSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_SIZE reads.");
5361	STAM_REL_REG(pVM, &pThis->svga.StatRegMemStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_START reads.");
5362	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS reads.");
5363	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
5364	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteRead", STAMUNIT_OCCURENCES, "SVGA_REG_PLAETTE_XXXX reads.");
5365	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockRead", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK reads.");
5366	STAM_REL_REG(pVM, &pThis->svga.StatRegPsuedoColorRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PsuedoColorRead", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR reads.");
5367	STAM_REL_REG(pVM, &pThis->svga.StatRegRedMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/RedMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_RED_MASK reads.");
5368	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH reads.");
5369	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_SIZE reads.");
5370	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncRead", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC reads.");
5371	STAM_REL_REG(pVM, &pThis->svga.StatRegTopRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopRead", STAMUNIT_OCCURENCES, "SVGA_REG_TOP reads.");
5372	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesRead", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES reads.");
5373	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownRead", STAMUNIT_OCCURENCES, "SVGA_REG_UNKNOWN reads.");
5374	STAM_REL_REG(pVM, &pThis->svga.StatRegVramSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/VramSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_VRAM_SIZE reads.");
5375	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH reads.");
5376	STAM_REL_REG(pVM, &pThis->svga.StatRegWriteOnlyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WriteOnlyRead", STAMUNIT_OCCURENCES, "Write-only SVGA_REG_XXXX reads.");
5377
5378	STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
5379	STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
5380	STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
5381	STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
5382	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
5383	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
5384	STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
5385
5386	/*
5387	* Info handlers.
5388	*/
5389	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
5390	# ifdef VBOX_WITH_VMSVGA3D
5391	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
5392	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
5393	"VMSVGA 3d surface details. "
5394	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
5395	vmsvgaR3Info3dSurface);
5396	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
5397	"VMSVGA 3d surface details and bitmap: "
5398	"sid[>dir]",
5399	vmsvgaR3Info3dSurfaceBmp);
5400	# endif
5401
5402	return VINF_SUCCESS;
5403	}
5404
5405	# ifdef VBOX_WITH_VMSVGA3D
5406	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5407	static const char * const g_apszVmSvgaDevCapNames[] =
5408	{
5409	"x3D", /* = 0 */
5410	"xMAX_LIGHTS",
5411	"xMAX_TEXTURES",
5412	"xMAX_CLIP_PLANES",
5413	"xVERTEX_SHADER_VERSION",
5414	"xVERTEX_SHADER",
5415	"xFRAGMENT_SHADER_VERSION",
5416	"xFRAGMENT_SHADER",
5417	"xMAX_RENDER_TARGETS",
5418	"xS23E8_TEXTURES",
5419	"xS10E5_TEXTURES",
5420	"xMAX_FIXED_VERTEXBLEND",
5421	"xD16_BUFFER_FORMAT",
5422	"xD24S8_BUFFER_FORMAT",
5423	"xD24X8_BUFFER_FORMAT",
5424	"xQUERY_TYPES",
5425	"xTEXTURE_GRADIENT_SAMPLING",
5426	"rMAX_POINT_SIZE",
5427	"xMAX_SHADER_TEXTURES",
5428	"xMAX_TEXTURE_WIDTH",
5429	"xMAX_TEXTURE_HEIGHT",
5430	"xMAX_VOLUME_EXTENT",
5431	"xMAX_TEXTURE_REPEAT",
5432	"xMAX_TEXTURE_ASPECT_RATIO",
5433	"xMAX_TEXTURE_ANISOTROPY",
5434	"xMAX_PRIMITIVE_COUNT",
5435	"xMAX_VERTEX_INDEX",
5436	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5437	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5438	"xMAX_VERTEX_SHADER_TEMPS",
5439	"xMAX_FRAGMENT_SHADER_TEMPS",
5440	"xTEXTURE_OPS",
5441	"xSURFACEFMT_X8R8G8B8",
5442	"xSURFACEFMT_A8R8G8B8",
5443	"xSURFACEFMT_A2R10G10B10",
5444	"xSURFACEFMT_X1R5G5B5",
5445	"xSURFACEFMT_A1R5G5B5",
5446	"xSURFACEFMT_A4R4G4B4",
5447	"xSURFACEFMT_R5G6B5",
5448	"xSURFACEFMT_LUMINANCE16",
5449	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5450	"xSURFACEFMT_ALPHA8",
5451	"xSURFACEFMT_LUMINANCE8",
5452	"xSURFACEFMT_Z_D16",
5453	"xSURFACEFMT_Z_D24S8",
5454	"xSURFACEFMT_Z_D24X8",
5455	"xSURFACEFMT_DXT1",
5456	"xSURFACEFMT_DXT2",
5457	"xSURFACEFMT_DXT3",
5458	"xSURFACEFMT_DXT4",
5459	"xSURFACEFMT_DXT5",
5460	"xSURFACEFMT_BUMPX8L8V8U8",
5461	"xSURFACEFMT_A2W10V10U10",
5462	"xSURFACEFMT_BUMPU8V8",
5463	"xSURFACEFMT_Q8W8V8U8",
5464	"xSURFACEFMT_CxV8U8",
5465	"xSURFACEFMT_R_S10E5",
5466	"xSURFACEFMT_R_S23E8",
5467	"xSURFACEFMT_RG_S10E5",
5468	"xSURFACEFMT_RG_S23E8",
5469	"xSURFACEFMT_ARGB_S10E5",
5470	"xSURFACEFMT_ARGB_S23E8",
5471	"xMISSING62",
5472	"xMAX_VERTEX_SHADER_TEXTURES",
5473	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
5474	"xSURFACEFMT_V16U16",
5475	"xSURFACEFMT_G16R16",
5476	"xSURFACEFMT_A16B16G16R16",
5477	"xSURFACEFMT_UYVY",
5478	"xSURFACEFMT_YUY2",
5479	"xMULTISAMPLE_NONMASKABLESAMPLES",
5480	"xMULTISAMPLE_MASKABLESAMPLES",
5481	"xALPHATOCOVERAGE",
5482	"xSUPERSAMPLE",
5483	"xAUTOGENMIPMAPS",
5484	"xSURFACEFMT_NV12",
5485	"xSURFACEFMT_AYUV",
5486	"xMAX_CONTEXT_IDS",
5487	"xMAX_SURFACE_IDS",
5488	"xSURFACEFMT_Z_DF16",
5489	"xSURFACEFMT_Z_DF24",
5490	"xSURFACEFMT_Z_D24S8_INT",
5491	"xSURFACEFMT_BC4_UNORM",
5492	"xSURFACEFMT_BC5_UNORM", /* 83 */
5493	};
5494	# endif
5495
5496
5497	/**
5498	* Power On notification.
5499	*
5500	* @returns VBox status code.
5501	* @param pDevIns The device instance data.
5502	*
5503	* @remarks Caller enters the device critical section.
5504	*/
5505	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
5506	{
5507	# ifdef VBOX_WITH_VMSVGA3D
5508	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5509	if (pThis->svga.f3DEnabled)
5510	{
5511	int rc = vmsvga3dPowerOn(pThis);
5512
5513	if (RT_SUCCESS(rc))
5514	{
5515	bool fSavedBuffering = RTLogRelSetBuffering(true);
5516	SVGA3dCapsRecord *pCaps;
5517	SVGA3dCapPair *pData;
5518	uint32_t idxCap = 0;
5519
5520	/* 3d hardware version; latest and greatest */
5521	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5522	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5523
5524	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
5525	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5526	pData = (SVGA3dCapPair *)&pCaps->data;
5527
5528	/* Fill out all 3d capabilities. */
5529	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
5530	{
5531	uint32_t val = 0;
5532
5533	rc = vmsvga3dQueryCaps(pThis, i, &val);
5534	if (RT_SUCCESS(rc))
5535	{
5536	pData[idxCap][0] = i;
5537	pData[idxCap][1] = val;
5538	idxCap++;
5539	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
5540	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
5541	else
5542	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
5543	&g_apszVmSvgaDevCapNames[i][1]));
5544	}
5545	else
5546	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
5547	}
5548	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
5549	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
5550
5551	/* Mark end of record array. */
5552	pCaps->header.length = 0;
5553
5554	RTLogRelSetBuffering(fSavedBuffering);
5555	}
5556	}
5557	# else /* !VBOX_WITH_VMSVGA3D */
5558	RT_NOREF(pDevIns);
5559	# endif /* !VBOX_WITH_VMSVGA3D */
5560	}
5561
5562	#endif /* IN_RING3 */
5563

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 70775

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