DevVGA-SVGA.cpp@ 69136

Last change on this file since 69136 was 69136, checked in by vboxsync, 7 years ago
Devices/Graphics: VMSVGA support for cubemaps and compressed textures (incomplete, only D3D backend); vertex/index buffer fixes; saved state fixes; cleanup.
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File size: 251.9 KB

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1	/* $Id: DevVGA-SVGA.cpp 69136 2017-10-20 07:13:09Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	*/
12
13	/*
14	* Copyright (C) 2013-2017 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.virtualbox.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25
26	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
27	*
28	* This device emulation was contributed by trivirt AG. It offers an
29	* alternative to our Bochs based VGA graphics and 3d emulations. This is
30	* valuable for Xorg based guests, as there is driver support shipping with Xorg
31	* since it forked from XFree86.
32	*
33	*
34	* @section sec_dev_vmsvga_sdk The VMware SDK
35	*
36	* This is officially deprecated now, however it's still quite useful,
37	* especially for getting the old features working:
38	* http://vmware-svga.sourceforge.net/
39	*
40	* They currently point developers at the following resources.
41	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
42	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
43	* - http://cgit.freedesktop.org/mesa/vmwgfx/
44	*
45	* @subsection subsec_dev_vmsvga_sdk_results Test results
46	*
47	* Test results:
48	* - 2dmark.img:
49	* + todo
50	* - backdoor-tclo.img:
51	* + todo
52	* - blit-cube.img:
53	* + todo
54	* - bunnies.img:
55	* + todo
56	* - cube.img:
57	* + todo
58	* - cubemark.img:
59	* + todo
60	* - dynamic-vertex-stress.img:
61	* + todo
62	* - dynamic-vertex.img:
63	* + todo
64	* - fence-stress.img:
65	* + todo
66	* - gmr-test.img:
67	* + todo
68	* - half-float-test.img:
69	* + todo
70	* - noscreen-cursor.img:
71	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
72	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
73	* visible though.)
74	* - Cursor animation via the palette doesn't work.
75	* - During debugging, it turns out that the framebuffer content seems to
76	* be halfways ignore or something (memset(fb, 0xcc, lots)).
77	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
78	* grow it 0x10 fold (128KB -> 2MB like in WS10).
79	* - null.img:
80	* + todo
81	* - pong.img:
82	* + todo
83	* - presentReadback.img:
84	* + todo
85	* - resolution-set.img:
86	* + todo
87	* - rt-gamma-test.img:
88	* + todo
89	* - screen-annotation.img:
90	* + todo
91	* - screen-cursor.img:
92	* + todo
93	* - screen-dma-coalesce.img:
94	* + todo
95	* - screen-gmr-discontig.img:
96	* + todo
97	* - screen-gmr-remap.img:
98	* + todo
99	* - screen-multimon.img:
100	* + todo
101	* - screen-present-clip.img:
102	* + todo
103	* - screen-render-test.img:
104	* + todo
105	* - screen-simple.img:
106	* + todo
107	* - screen-text.img:
108	* + todo
109	* - simple-shaders.img:
110	* + todo
111	* - simple_blit.img:
112	* + todo
113	* - tiny-2d-updates.img:
114	* + todo
115	* - video-formats.img:
116	* + todo
117	* - video-sync.img:
118	* + todo
119	*
120	*/
121
122
123	/*********************************************************************************************************************************
124	* Header Files *
125	*********************************************************************************************************************************/
126	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
127	#define VMSVGA_USE_EMT_HALT_CODE
128	#include <VBox/vmm/pdmdev.h>
129	#include <VBox/version.h>
130	#include <VBox/err.h>
131	#include <VBox/log.h>
132	#include <VBox/vmm/pgm.h>
133	#ifdef VMSVGA_USE_EMT_HALT_CODE
134	# include <VBox/vmm/vmapi.h>
135	# include <VBox/vmm/vmcpuset.h>
136	#endif
137	#include <VBox/sup.h>
138
139	#include <iprt/assert.h>
140	#include <iprt/semaphore.h>
141	#include <iprt/uuid.h>
142	#ifdef IN_RING3
143	# include <iprt/ctype.h>
144	# include <iprt/mem.h>
145	#endif
146
147	#include <VBox/VMMDev.h>
148	#include <VBoxVideo.h>
149	#include <VBox/bioslogo.h>
150
151	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
152	#include "DevVGA.h"
153
154	#include "DevVGA-SVGA.h"
155	#include "vmsvga/svga_reg.h"
156	#include "vmsvga/svga_escape.h"
157	#include "vmsvga/svga_overlay.h"
158	#include "vmsvga/svga3d_reg.h"
159	#include "vmsvga/svga3d_caps.h"
160	#ifdef VBOX_WITH_VMSVGA3D
161	# include "DevVGA-SVGA3d.h"
162	# ifdef RT_OS_DARWIN
163	# include "DevVGA-SVGA3d-cocoa.h"
164	# endif
165	#endif
166
167
168	/*********************************************************************************************************************************
169	* Defined Constants And Macros *
170	*********************************************************************************************************************************/
171	/**
172	* Macro for checking if a fixed FIFO register is valid according to the
173	* current FIFO configuration.
174	*
175	* @returns true / false.
176	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
177	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
178	*/
179	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
180
181
182	/*********************************************************************************************************************************
183	* Structures and Typedefs *
184	*********************************************************************************************************************************/
185	/**
186	* 64-bit GMR descriptor.
187	*/
188	typedef struct
189	{
190	RTGCPHYS GCPhys;
191	uint64_t numPages;
192	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
193
194	/**
195	* GMR slot
196	*/
197	typedef struct
198	{
199	uint32_t cMaxPages;
200	uint32_t cbTotal;
201	uint32_t numDescriptors;
202	PVMSVGAGMRDESCRIPTOR paDesc;
203	} GMR, *PGMR;
204
205	#ifdef IN_RING3
206	/**
207	* Internal SVGA ring-3 only state.
208	*/
209	typedef struct VMSVGAR3STATE
210	{
211	GMR aGMR[VMSVGA_MAX_GMR_IDS];
212	struct
213	{
214	SVGAGuestPtr ptr;
215	uint32_t bytesPerLine;
216	SVGAGMRImageFormat format;
217	} GMRFB;
218	struct
219	{
220	bool fActive;
221	uint32_t xHotspot;
222	uint32_t yHotspot;
223	uint32_t width;
224	uint32_t height;
225	uint32_t cbData;
226	void *pData;
227	} Cursor;
228	SVGAColorBGRX colorAnnotation;
229
230	# ifdef VMSVGA_USE_EMT_HALT_CODE
231	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
232	uint32_t volatile cBusyDelayedEmts;
233	/** Set of EMTs that are */
234	VMCPUSET BusyDelayedEmts;
235	# else
236	/** Number of EMTs waiting on hBusyDelayedEmts. */
237	uint32_t volatile cBusyDelayedEmts;
238	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
239	* busy (ugly). */
240	RTSEMEVENTMULTI hBusyDelayedEmts;
241	# endif
242	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
243	STAMPROFILE StatBusyDelayEmts;
244
245	STAMPROFILE StatR3Cmd3dPresentProf;
246	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
247	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
248	STAMCOUNTER StatR3CmdDefineGmr2;
249	STAMCOUNTER StatR3CmdDefineGmr2Free;
250	STAMCOUNTER StatR3CmdDefineGmr2Modify;
251	STAMCOUNTER StatR3CmdRemapGmr2;
252	STAMCOUNTER StatR3CmdRemapGmr2Modify;
253	STAMCOUNTER StatR3CmdInvalidCmd;
254	STAMCOUNTER StatR3CmdFence;
255	STAMCOUNTER StatR3CmdUpdate;
256	STAMCOUNTER StatR3CmdUpdateVerbose;
257	STAMCOUNTER StatR3CmdDefineCursor;
258	STAMCOUNTER StatR3CmdDefineAlphaCursor;
259	STAMCOUNTER StatR3CmdEscape;
260	STAMCOUNTER StatR3CmdDefineScreen;
261	STAMCOUNTER StatR3CmdDestroyScreen;
262	STAMCOUNTER StatR3CmdDefineGmrFb;
263	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
264	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
265	STAMCOUNTER StatR3CmdAnnotationFill;
266	STAMCOUNTER StatR3CmdAnnotationCopy;
267	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
268	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
269	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
270	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
271	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
272	STAMCOUNTER StatR3Cmd3dSurfaceDma;
273	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
274	STAMCOUNTER StatR3Cmd3dContextDefine;
275	STAMCOUNTER StatR3Cmd3dContextDestroy;
276	STAMCOUNTER StatR3Cmd3dSetTransform;
277	STAMCOUNTER StatR3Cmd3dSetZRange;
278	STAMCOUNTER StatR3Cmd3dSetRenderState;
279	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
280	STAMCOUNTER StatR3Cmd3dSetTextureState;
281	STAMCOUNTER StatR3Cmd3dSetMaterial;
282	STAMCOUNTER StatR3Cmd3dSetLightData;
283	STAMCOUNTER StatR3Cmd3dSetLightEnable;
284	STAMCOUNTER StatR3Cmd3dSetViewPort;
285	STAMCOUNTER StatR3Cmd3dSetClipPlane;
286	STAMCOUNTER StatR3Cmd3dClear;
287	STAMCOUNTER StatR3Cmd3dPresent;
288	STAMCOUNTER StatR3Cmd3dPresentReadBack;
289	STAMCOUNTER StatR3Cmd3dShaderDefine;
290	STAMCOUNTER StatR3Cmd3dShaderDestroy;
291	STAMCOUNTER StatR3Cmd3dSetShader;
292	STAMCOUNTER StatR3Cmd3dSetShaderConst;
293	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
294	STAMCOUNTER StatR3Cmd3dSetScissorRect;
295	STAMCOUNTER StatR3Cmd3dBeginQuery;
296	STAMCOUNTER StatR3Cmd3dEndQuery;
297	STAMCOUNTER StatR3Cmd3dWaitForQuery;
298	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
299	STAMCOUNTER StatR3Cmd3dActivateSurface;
300	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
301
302	STAMCOUNTER StatR3RegConfigDoneWr;
303	STAMCOUNTER StatR3RegGmrDescriptorWr;
304	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
305	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
306
307	STAMCOUNTER StatFifoCommands;
308	STAMCOUNTER StatFifoErrors;
309	STAMCOUNTER StatFifoUnkCmds;
310	STAMCOUNTER StatFifoTodoTimeout;
311	STAMCOUNTER StatFifoTodoWoken;
312	STAMPROFILE StatFifoStalls;
313
314	} VMSVGAR3STATE, *PVMSVGAR3STATE;
315	#endif /* IN_RING3 */
316
317
318	/*********************************************************************************************************************************
319	* Internal Functions *
320	*********************************************************************************************************************************/
321	#ifdef IN_RING3
322	# ifdef DEBUG_FIFO_ACCESS
323	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
324	# endif
325	# ifdef DEBUG_GMR_ACCESS
326	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
327	# endif
328	#endif
329
330
331	/*********************************************************************************************************************************
332	* Global Variables *
333	*********************************************************************************************************************************/
334	#ifdef IN_RING3
335
336	/**
337	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
338	*/
339	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
340	{
341	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
342	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
343	SSMFIELD_ENTRY_TERM()
344	};
345
346	/**
347	* SSM descriptor table for the GMR structure.
348	*/
349	static SSMFIELD const g_aGMRFields[] =
350	{
351	SSMFIELD_ENTRY( GMR, cMaxPages),
352	SSMFIELD_ENTRY( GMR, cbTotal),
353	SSMFIELD_ENTRY( GMR, numDescriptors),
354	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
355	SSMFIELD_ENTRY_TERM()
356	};
357
358	/**
359	* SSM descriptor table for the VMSVGAR3STATE structure.
360	*/
361	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
362	{
363	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, aGMR),
364	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
365	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
366	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
367	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
368	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
369	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
370	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
371	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
372	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
373	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
374	#ifdef VMSVGA_USE_EMT_HALT_CODE
375	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
376	#else
377	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
378	#endif
379	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
380	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
381	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
382	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
383	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
384	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
385	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
386	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
387	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
388	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
389	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
390	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
391	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
392	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
393	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
394	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
395	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
396	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
397	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
398	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
399	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
400	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
401	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
402	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
403	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
404	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
405	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
406	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
408	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
409	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
410	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
412	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
436
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
441
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
448	SSMFIELD_ENTRY_TERM()
449	};
450
451	/**
452	* SSM descriptor table for the VGAState.svga structure.
453	*/
454	static SSMFIELD const g_aVGAStateSVGAFields[] =
455	{
456	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u64HostWindowId),
457	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
458	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
459	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
460	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
461	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
462	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
463	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
466	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
467	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
468	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
469	SSMFIELD_ENTRY( VMSVGAState, fBusy),
470	SSMFIELD_ENTRY( VMSVGAState, fTraces),
471	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
472	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
473	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
474	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
475	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
476	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
477	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
478	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
480	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
483	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
484	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
485	SSMFIELD_ENTRY( VMSVGAState, uWidth),
486	SSMFIELD_ENTRY( VMSVGAState, uHeight),
487	SSMFIELD_ENTRY( VMSVGAState, uBpp),
488	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
489	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
490	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
491	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
492	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
493	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
494	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
495	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
496	SSMFIELD_ENTRY_TERM()
497	};
498
499	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
500
501	#endif /* IN_RING3 */
502
503	#ifdef LOG_ENABLED
504
505	/**
506	* Index register string name lookup
507	*
508	* @returns Index register string or "UNKNOWN"
509	* @param pThis VMSVGA State
510	* @param idxReg The index register.
511	*/
512	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
513	{
514	switch (idxReg)
515	{
516	case SVGA_REG_ID: return "SVGA_REG_ID";
517	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
518	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
519	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
520	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
521	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
522	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
523	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
524	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
525	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
526	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
527	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
528	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
529	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
530	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
531	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
532	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
533	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
534	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
535	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
536	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
537	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
538	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
539	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
540	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
541	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
542	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
543	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
544	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
545	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
546	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
547	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
548	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
549	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
550	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
551	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
552	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
553	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
554	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
555	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
556	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
557	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
558	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
559	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
560	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
561	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
562	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
563	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
564	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
565	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
566
567	default:
568	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
569	return "SVGA_SCRATCH_BASE reg";
570	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
571	return "SVGA_PALETTE_BASE reg";
572	return "UNKNOWN";
573	}
574	}
575
576	#ifdef IN_RING3
577	/**
578	* FIFO command name lookup
579	*
580	* @returns FIFO command string or "UNKNOWN"
581	* @param u32Cmd FIFO command
582	*/
583	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
584	{
585	switch (u32Cmd)
586	{
587	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
588	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
589	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
590	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
591	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
592	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
593	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
594	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
595	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
596	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
597	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
598	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
599	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
600	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
601	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
602	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
603	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
604	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
605	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
606	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
607	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
608	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
609	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
610	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
611	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
612	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
613	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
614	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
615	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
616	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
617	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
618	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
619	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
620	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
621	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
622	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
623	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
624	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
625	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
626	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
627	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
628	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
629	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
630	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
631	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
632	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
633	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
634	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
635	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
636	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
637	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
638	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
639	default: return "UNKNOWN";
640	}
641	}
642	# endif /* IN_RING3 */
643
644	#endif /* LOG_ENABLED */
645
646	#ifdef IN_RING3
647	/**
648	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
649	*/
650	DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
651	{
652	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
653
654	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
655	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
656
657	if (x < pThis->svga.uWidth)
658	{
659	pThis->svga.viewport.x = x;
660	pThis->svga.viewport.cx = RT_MIN(cx, pThis->svga.uWidth - x);
661	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
662	}
663	else
664	{
665	pThis->svga.viewport.x = pThis->svga.uWidth;
666	pThis->svga.viewport.cx = 0;
667	pThis->svga.viewport.xRight = pThis->svga.uWidth;
668	}
669	if (y < pThis->svga.uHeight)
670	{
671	pThis->svga.viewport.y = y;
672	pThis->svga.viewport.cy = RT_MIN(cy, pThis->svga.uHeight - y);
673	pThis->svga.viewport.yLowWC = pThis->svga.uHeight - y - pThis->svga.viewport.cy;
674	pThis->svga.viewport.yHighWC = pThis->svga.uHeight - y;
675	}
676	else
677	{
678	pThis->svga.viewport.y = pThis->svga.uHeight;
679	pThis->svga.viewport.cy = 0;
680	pThis->svga.viewport.yLowWC = 0;
681	pThis->svga.viewport.yHighWC = 0;
682	}
683
684	# ifdef VBOX_WITH_VMSVGA3D
685	/*
686	* Now inform the 3D backend.
687	*/
688	if (pThis->svga.f3DEnabled)
689	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
690	# else
691	RT_NOREF(idScreen, OldViewport);
692	# endif
693	}
694	#endif /* IN_RING3 */
695
696	/**
697	* Read port register
698	*
699	* @returns VBox status code.
700	* @param pThis VMSVGA State
701	* @param pu32 Where to store the read value
702	*/
703	PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
704	{
705	int rc = VINF_SUCCESS;
706	*pu32 = 0;
707
708	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
709	uint32_t idxReg = pThis->svga.u32IndexReg;
710	if ( idxReg >= SVGA_REG_CAPABILITIES
711	&& pThis->svga.u32SVGAId == SVGA_ID_0)
712	{
713	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
714	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
715	}
716
717	switch (idxReg)
718	{
719	case SVGA_REG_ID:
720	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
721	*pu32 = pThis->svga.u32SVGAId;
722	break;
723
724	case SVGA_REG_ENABLE:
725	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
726	*pu32 = pThis->svga.fEnabled;
727	break;
728
729	case SVGA_REG_WIDTH:
730	{
731	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
732	if ( pThis->svga.fEnabled
733	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
734	{
735	*pu32 = pThis->svga.uWidth;
736	}
737	else
738	{
739	#ifndef IN_RING3
740	rc = VINF_IOM_R3_IOPORT_READ;
741	#else
742	*pu32 = pThis->pDrv->cx;
743	#endif
744	}
745	break;
746	}
747
748	case SVGA_REG_HEIGHT:
749	{
750	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
751	if ( pThis->svga.fEnabled
752	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
753	{
754	*pu32 = pThis->svga.uHeight;
755	}
756	else
757	{
758	#ifndef IN_RING3
759	rc = VINF_IOM_R3_IOPORT_READ;
760	#else
761	*pu32 = pThis->pDrv->cy;
762	#endif
763	}
764	break;
765	}
766
767	case SVGA_REG_MAX_WIDTH:
768	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
769	*pu32 = pThis->svga.u32MaxWidth;
770	break;
771
772	case SVGA_REG_MAX_HEIGHT:
773	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
774	*pu32 = pThis->svga.u32MaxHeight;
775	break;
776
777	case SVGA_REG_DEPTH:
778	/* This returns the color depth of the current mode. */
779	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
780	switch (pThis->svga.uBpp)
781	{
782	case 15:
783	case 16:
784	case 24:
785	*pu32 = pThis->svga.uBpp;
786	break;
787
788	default:
789	case 32:
790	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
791	break;
792	}
793	break;
794
795	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
796	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
797	if ( pThis->svga.fEnabled
798	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
799	{
800	*pu32 = pThis->svga.uBpp;
801	}
802	else
803	{
804	#ifndef IN_RING3
805	rc = VINF_IOM_R3_IOPORT_READ;
806	#else
807	*pu32 = pThis->pDrv->cBits;
808	#endif
809	}
810	break;
811
812	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
813	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
814	if ( pThis->svga.fEnabled
815	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
816	{
817	*pu32 = (pThis->svga.uBpp + 7) & ~7;
818	}
819	else
820	{
821	#ifndef IN_RING3
822	rc = VINF_IOM_R3_IOPORT_READ;
823	#else
824	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
825	#endif
826	}
827	break;
828
829	case SVGA_REG_PSEUDOCOLOR:
830	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
831	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
832	break;
833
834	case SVGA_REG_RED_MASK:
835	case SVGA_REG_GREEN_MASK:
836	case SVGA_REG_BLUE_MASK:
837	{
838	uint32_t uBpp;
839
840	if ( pThis->svga.fEnabled
841	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
842	{
843	uBpp = pThis->svga.uBpp;
844	}
845	else
846	{
847	#ifndef IN_RING3
848	rc = VINF_IOM_R3_IOPORT_READ;
849	break;
850	#else
851	uBpp = pThis->pDrv->cBits;
852	#endif
853	}
854	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
855	switch (uBpp)
856	{
857	case 8:
858	u32RedMask = 0x07;
859	u32GreenMask = 0x38;
860	u32BlueMask = 0xc0;
861	break;
862
863	case 15:
864	u32RedMask = 0x0000001f;
865	u32GreenMask = 0x000003e0;
866	u32BlueMask = 0x00007c00;
867	break;
868
869	case 16:
870	u32RedMask = 0x0000001f;
871	u32GreenMask = 0x000007e0;
872	u32BlueMask = 0x0000f800;
873	break;
874
875	case 24:
876	case 32:
877	default:
878	u32RedMask = 0x00ff0000;
879	u32GreenMask = 0x0000ff00;
880	u32BlueMask = 0x000000ff;
881	break;
882	}
883	switch (idxReg)
884	{
885	case SVGA_REG_RED_MASK:
886	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
887	*pu32 = u32RedMask;
888	break;
889
890	case SVGA_REG_GREEN_MASK:
891	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
892	*pu32 = u32GreenMask;
893	break;
894
895	case SVGA_REG_BLUE_MASK:
896	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
897	*pu32 = u32BlueMask;
898	break;
899	}
900	break;
901	}
902
903	case SVGA_REG_BYTES_PER_LINE:
904	{
905	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
906	if ( pThis->svga.fEnabled
907	&& pThis->svga.cbScanline)
908	{
909	*pu32 = pThis->svga.cbScanline;
910	}
911	else
912	{
913	#ifndef IN_RING3
914	rc = VINF_IOM_R3_IOPORT_READ;
915	#else
916	*pu32 = pThis->pDrv->cbScanline;
917	#endif
918	}
919	break;
920	}
921
922	case SVGA_REG_VRAM_SIZE: /* VRAM size */
923	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
924	*pu32 = pThis->vram_size;
925	break;
926
927	case SVGA_REG_FB_START: /* Frame buffer physical address. */
928	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
929	Assert(pThis->GCPhysVRAM <= 0xffffffff);
930	*pu32 = pThis->GCPhysVRAM;
931	break;
932
933	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
934	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
935	/* Always zero in our case. */
936	*pu32 = 0;
937	break;
938
939	case SVGA_REG_FB_SIZE: /* Frame buffer size */
940	{
941	#ifndef IN_RING3
942	rc = VINF_IOM_R3_IOPORT_READ;
943	#else
944	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
945
946	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
947	if ( pThis->svga.fEnabled
948	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
949	{
950	/* Hardware enabled; return real framebuffer size .*/
951	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
952	}
953	else
954	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
955
956	pu32 = RT_MIN(pThis->vram_size, pu32);
957	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
958	#endif
959	break;
960	}
961
962	case SVGA_REG_CAPABILITIES:
963	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
964	*pu32 = pThis->svga.u32RegCaps;
965	break;
966
967	case SVGA_REG_MEM_START: /* FIFO start */
968	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
969	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
970	*pu32 = pThis->svga.GCPhysFIFO;
971	break;
972
973	case SVGA_REG_MEM_SIZE: /* FIFO size */
974	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
975	*pu32 = pThis->svga.cbFIFO;
976	break;
977
978	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
979	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
980	*pu32 = pThis->svga.fConfigured;
981	break;
982
983	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
984	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
985	*pu32 = 0;
986	break;
987
988	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
989	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
990	if (pThis->svga.fBusy)
991	{
992	#ifndef IN_RING3
993	/* Go to ring-3 and halt the CPU. */
994	rc = VINF_IOM_R3_IOPORT_READ;
995	break;
996	#else
997	# if defined(VMSVGA_USE_EMT_HALT_CODE)
998	/* The guest is basically doing a HLT via the device here, but with
999	a special wake up condition on FIFO completion. */
1000	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1001	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1002	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1003	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1004	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1005	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1006	if (pThis->svga.fBusy)
1007	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1008	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1009	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1010	# else
1011
1012	/* Delay the EMT a bit so the FIFO and others can get some work done.
1013	This used to be a crude 50 ms sleep. The current code tries to be
1014	more efficient, but the consept is still very crude. */
1015	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1016	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1017	RTThreadYield();
1018	if (pThis->svga.fBusy)
1019	{
1020	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1021
1022	if (pThis->svga.fBusy && cRefs == 1)
1023	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1024	if (pThis->svga.fBusy)
1025	{
1026	/** @todo If this code is going to stay, we need to call into the halt/wait
1027	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1028	* suffer when the guest is polling on a busy FIFO. */
1029	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1030	if (cNsMaxWait >= RT_NS_100US)
1031	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1032	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1033	RT_MIN(cNsMaxWait, RT_NS_10MS));
1034	}
1035
1036	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1037	}
1038	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1039	# endif
1040	*pu32 = pThis->svga.fBusy != 0;
1041	#endif
1042	}
1043	else
1044	*pu32 = false;
1045	break;
1046
1047	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1048	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1049	*pu32 = pThis->svga.u32GuestId;
1050	break;
1051
1052	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1053	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1054	*pu32 = pThis->svga.cScratchRegion;
1055	break;
1056
1057	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1058	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1059	*pu32 = SVGA_FIFO_NUM_REGS;
1060	break;
1061
1062	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1063	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1064	*pu32 = pThis->svga.u32PitchLock;
1065	break;
1066
1067	case SVGA_REG_IRQMASK: /* Interrupt mask */
1068	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1069	*pu32 = pThis->svga.u32IrqMask;
1070	break;
1071
1072	/* See "Guest memory regions" below. */
1073	case SVGA_REG_GMR_ID:
1074	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1075	*pu32 = pThis->svga.u32CurrentGMRId;
1076	break;
1077
1078	case SVGA_REG_GMR_DESCRIPTOR:
1079	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1080	/* Write only */
1081	*pu32 = 0;
1082	break;
1083
1084	case SVGA_REG_GMR_MAX_IDS:
1085	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1086	*pu32 = VMSVGA_MAX_GMR_IDS;
1087	break;
1088
1089	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1090	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1091	*pu32 = VMSVGA_MAX_GMR_PAGES;
1092	break;
1093
1094	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1095	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1096	*pu32 = pThis->svga.fTraces;
1097	break;
1098
1099	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1100	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1101	*pu32 = VMSVGA_MAX_GMR_PAGES;
1102	break;
1103
1104	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1105	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1106	*pu32 = VMSVGA_SURFACE_SIZE;
1107	break;
1108
1109	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1110	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1111	break;
1112
1113	/* Mouse cursor support. */
1114	case SVGA_REG_CURSOR_ID:
1115	case SVGA_REG_CURSOR_X:
1116	case SVGA_REG_CURSOR_Y:
1117	case SVGA_REG_CURSOR_ON:
1118	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1119	break;
1120
1121	/* Legacy multi-monitor support */
1122	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1123	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1124	*pu32 = 1;
1125	break;
1126
1127	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1128	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1129	*pu32 = 0;
1130	break;
1131
1132	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1133	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1134	*pu32 = 0;
1135	break;
1136
1137	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1138	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1139	*pu32 = 0;
1140	break;
1141
1142	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1143	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1144	*pu32 = 0;
1145	break;
1146
1147	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1148	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1149	*pu32 = pThis->svga.uWidth;
1150	break;
1151
1152	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1153	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1154	*pu32 = pThis->svga.uHeight;
1155	break;
1156
1157	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1158	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1159	pu32 = 1; / Must return something sensible here otherwise the Linux driver will take a legacy code path without 3d support. */
1160	break;
1161
1162	default:
1163	{
1164	uint32_t offReg;
1165	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1166	{
1167	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1168	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1169	}
1170	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1171	{
1172	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1173	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1174	uint32_t u32 = pThis->last_palette[offReg / 3];
1175	switch (offReg % 3)
1176	{
1177	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1178	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1179	case 2: pu32 = u32 & 0xff; break; / blue */
1180	}
1181	}
1182	else
1183	{
1184	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1185	rc = VINF_IOM_R3_IOPORT_READ;
1186	#else
1187	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1188	# ifndef DEBUG_sunlover
1189	AssertMsgFailed(("reg=%#x\n", idxReg));
1190	# endif
1191	#endif
1192	}
1193	break;
1194	}
1195	}
1196	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1197	return rc;
1198	}
1199
1200	#ifdef IN_RING3
1201	/**
1202	* Apply the current resolution settings to change the video mode.
1203	*
1204	* @returns VBox status code.
1205	* @param pThis VMSVGA State
1206	*/
1207	int vmsvgaChangeMode(PVGASTATE pThis)
1208	{
1209	int rc;
1210
1211	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1212	\|\| pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1213	\|\| pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1214	{
1215	/* Mode change in progress; wait for all values to be set. */
1216	Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1217	return VINF_SUCCESS;
1218	}
1219
1220	if ( pThis->svga.uWidth == 0
1221	\|\| pThis->svga.uHeight == 0
1222	\|\| pThis->svga.uBpp == 0)
1223	{
1224	/* Invalid mode change - BB does this early in the boot up. */
1225	Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1226	return VINF_SUCCESS;
1227	}
1228
1229	if ( pThis->last_bpp == (unsigned)pThis->svga.uBpp
1230	&& pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1231	&& pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1232	&& pThis->last_width == (unsigned)pThis->svga.uWidth
1233	&& pThis->last_height == (unsigned)pThis->svga.uHeight
1234	)
1235	{
1236	/* Nothing to do. */
1237	Log(("vmsvgaChangeMode: nothing changed; ignore\n"));
1238	return VINF_SUCCESS;
1239	}
1240
1241	Log(("vmsvgaChangeMode: sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1242	pThis->svga.cbScanline = ((pThis->svga.uWidth * pThis->svga.uBpp + 7) & ~7) / 8;
1243
1244	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1245	rc = pThis->pDrv->pfnResize(pThis->pDrv, pThis->svga.uBpp, pThis->CTX_SUFF(vram_ptr), pThis->svga.cbScanline, pThis->svga.uWidth, pThis->svga.uHeight);
1246	AssertRC(rc);
1247	AssertReturn(rc == VINF_SUCCESS \|\| rc == VINF_VGA_RESIZE_IN_PROGRESS, rc);
1248
1249	/* last stuff */
1250	pThis->last_bpp = pThis->svga.uBpp;
1251	pThis->last_scr_width = pThis->svga.uWidth;
1252	pThis->last_scr_height = pThis->svga.uHeight;
1253	pThis->last_width = pThis->svga.uWidth;
1254	pThis->last_height = pThis->svga.uHeight;
1255
1256	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1257
1258	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1259	if ( pThis->svga.viewport.cx == 0
1260	&& pThis->svga.viewport.cy == 0)
1261	{
1262	pThis->svga.viewport.cx = pThis->svga.uWidth;
1263	pThis->svga.viewport.xRight = pThis->svga.uWidth;
1264	pThis->svga.viewport.cy = pThis->svga.uHeight;
1265	pThis->svga.viewport.yHighWC = pThis->svga.uHeight;
1266	pThis->svga.viewport.yLowWC = 0;
1267	}
1268	return VINF_SUCCESS;
1269	}
1270	#endif /* IN_RING3 */
1271
1272	#if defined(IN_RING0) \|\| defined(IN_RING3)
1273	/**
1274	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1275	*
1276	* @param pThis The VMSVGA state.
1277	* @param fState The busy state.
1278	*/
1279	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1280	{
1281	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1282
1283	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1284	{
1285	/* Race / unfortunately scheduling. Highly unlikly. */
1286	uint32_t cLoops = 64;
1287	do
1288	{
1289	ASMNopPause();
1290	fState = (pThis->svga.fBusy != 0);
1291	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1292	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1293	}
1294	}
1295	#endif
1296
1297	/**
1298	* Write port register
1299	*
1300	* @returns VBox status code.
1301	* @param pThis VMSVGA State
1302	* @param u32 Value to write
1303	*/
1304	PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1305	{
1306	#ifdef IN_RING3
1307	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1308	#endif
1309	int rc = VINF_SUCCESS;
1310
1311	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1312	uint32_t idxReg = pThis->svga.u32IndexReg;
1313	if ( idxReg >= SVGA_REG_CAPABILITIES
1314	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1315	{
1316	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1317	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1318	}
1319	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1320	switch (idxReg)
1321	{
1322	case SVGA_REG_ID:
1323	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1324	if ( u32 == SVGA_ID_0
1325	\|\| u32 == SVGA_ID_1
1326	\|\| u32 == SVGA_ID_2)
1327	pThis->svga.u32SVGAId = u32;
1328	else
1329	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1330	break;
1331
1332	case SVGA_REG_ENABLE:
1333	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1334	if ( pThis->svga.fEnabled == u32
1335	&& pThis->last_bpp == (unsigned)pThis->svga.uBpp
1336	&& pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1337	&& pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1338	&& pThis->last_width == (unsigned)pThis->svga.uWidth
1339	&& pThis->last_height == (unsigned)pThis->svga.uHeight
1340	)
1341	/* Nothing to do. */
1342	break;
1343
1344	#ifdef IN_RING3
1345	if ( u32 == 1
1346	&& pThis->svga.fEnabled == false)
1347	{
1348	/* Make a backup copy of the first 512kb in order to save font data etc. */
1349	/** @todo should probably swap here, rather than copy + zero */
1350	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1351	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1352	}
1353
1354	pThis->svga.fEnabled = u32;
1355	if (pThis->svga.fEnabled)
1356	{
1357	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1358	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1359	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1360	{
1361	/* Keep the current mode. */
1362	pThis->svga.uWidth = pThis->pDrv->cx;
1363	pThis->svga.uHeight = pThis->pDrv->cy;
1364	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1365	}
1366
1367	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1368	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1369	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1370	{
1371	rc = vmsvgaChangeMode(pThis);
1372	AssertRCReturn(rc, rc);
1373	}
1374	# ifdef LOG_ENABLED
1375	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
1376	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1377	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1378	# endif
1379
1380	/* Disable or enable dirty page tracking according to the current fTraces value. */
1381	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1382	}
1383	else
1384	{
1385	/* Restore the text mode backup. */
1386	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1387
1388	/* pThis->svga.uHeight = -1;
1389	pThis->svga.uWidth = -1;
1390	pThis->svga.uBpp = -1;
1391	pThis->svga.cbScanline = 0; */
1392	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1393
1394	/* Enable dirty page tracking again when going into legacy mode. */
1395	vmsvgaSetTraces(pThis, true);
1396	}
1397	#else /* !IN_RING3 */
1398	rc = VINF_IOM_R3_IOPORT_WRITE;
1399	#endif /* !IN_RING3 */
1400	break;
1401
1402	case SVGA_REG_WIDTH:
1403	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1404	if (pThis->svga.uWidth != u32)
1405	{
1406	if (pThis->svga.fEnabled)
1407	{
1408	#ifdef IN_RING3
1409	pThis->svga.uWidth = u32;
1410	rc = vmsvgaChangeMode(pThis);
1411	AssertRCReturn(rc, rc);
1412	#else
1413	rc = VINF_IOM_R3_IOPORT_WRITE;
1414	#endif
1415	}
1416	else
1417	pThis->svga.uWidth = u32;
1418	}
1419	/* else: nop */
1420	break;
1421
1422	case SVGA_REG_HEIGHT:
1423	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1424	if (pThis->svga.uHeight != u32)
1425	{
1426	if (pThis->svga.fEnabled)
1427	{
1428	#ifdef IN_RING3
1429	pThis->svga.uHeight = u32;
1430	rc = vmsvgaChangeMode(pThis);
1431	AssertRCReturn(rc, rc);
1432	#else
1433	rc = VINF_IOM_R3_IOPORT_WRITE;
1434	#endif
1435	}
1436	else
1437	pThis->svga.uHeight = u32;
1438	}
1439	/* else: nop */
1440	break;
1441
1442	case SVGA_REG_DEPTH:
1443	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1444	/** @todo read-only?? */
1445	break;
1446
1447	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1448	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1449	if (pThis->svga.uBpp != u32)
1450	{
1451	if (pThis->svga.fEnabled)
1452	{
1453	#ifdef IN_RING3
1454	pThis->svga.uBpp = u32;
1455	rc = vmsvgaChangeMode(pThis);
1456	AssertRCReturn(rc, rc);
1457	#else
1458	rc = VINF_IOM_R3_IOPORT_WRITE;
1459	#endif
1460	}
1461	else
1462	pThis->svga.uBpp = u32;
1463	}
1464	/* else: nop */
1465	break;
1466
1467	case SVGA_REG_PSEUDOCOLOR:
1468	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1469	break;
1470
1471	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1472	#ifdef IN_RING3
1473	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1474	pThis->svga.fConfigured = u32;
1475	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1476	if (!pThis->svga.fConfigured)
1477	{
1478	pThis->svga.fTraces = true;
1479	}
1480	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1481	#else
1482	rc = VINF_IOM_R3_IOPORT_WRITE;
1483	#endif
1484	break;
1485
1486	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1487	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1488	if ( pThis->svga.fEnabled
1489	&& pThis->svga.fConfigured)
1490	{
1491	#if defined(IN_RING3) \|\| defined(IN_RING0)
1492	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1493	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1494	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1495	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1496
1497	/* Kick the FIFO thread to start processing commands again. */
1498	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1499	#else
1500	rc = VINF_IOM_R3_IOPORT_WRITE;
1501	#endif
1502	}
1503	/* else nothing to do. */
1504	else
1505	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1506
1507	break;
1508
1509	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1510	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1511	break;
1512
1513	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1514	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1515	pThis->svga.u32GuestId = u32;
1516	break;
1517
1518	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1519	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1520	pThis->svga.u32PitchLock = u32;
1521	break;
1522
1523	case SVGA_REG_IRQMASK: /* Interrupt mask */
1524	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1525	pThis->svga.u32IrqMask = u32;
1526
1527	/* Irq pending after the above change? */
1528	if (pThis->svga.u32IrqStatus & u32)
1529	{
1530	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1531	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1532	}
1533	else
1534	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1535	break;
1536
1537	/* Mouse cursor support */
1538	case SVGA_REG_CURSOR_ID:
1539	case SVGA_REG_CURSOR_X:
1540	case SVGA_REG_CURSOR_Y:
1541	case SVGA_REG_CURSOR_ON:
1542	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1543	break;
1544
1545	/* Legacy multi-monitor support */
1546	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1547	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1548	break;
1549	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1550	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1551	break;
1552	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1553	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1554	break;
1555	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1556	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1557	break;
1558	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1559	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1560	break;
1561	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1562	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1563	break;
1564	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1565	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1566	break;
1567	#ifdef VBOX_WITH_VMSVGA3D
1568	/* See "Guest memory regions" below. */
1569	case SVGA_REG_GMR_ID:
1570	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1571	pThis->svga.u32CurrentGMRId = u32;
1572	break;
1573
1574	case SVGA_REG_GMR_DESCRIPTOR:
1575	# ifndef IN_RING3
1576	rc = VINF_IOM_R3_IOPORT_WRITE;
1577	break;
1578	# else /* IN_RING3 */
1579	{
1580	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1581
1582	/* Validate current GMR id. */
1583	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1584	AssertBreak(idGMR < VMSVGA_MAX_GMR_IDS);
1585
1586	/* Free the old GMR if present. */
1587	vmsvgaGMRFree(pThis, idGMR);
1588
1589	/* Just undefine the GMR? */
1590	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1591	if (GCPhys == 0)
1592	{
1593	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1594	break;
1595	}
1596
1597
1598	/* Never cross a page boundary automatically. */
1599	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1600	uint32_t cPagesTotal = 0;
1601	uint32_t iDesc = 0;
1602	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1603	uint32_t cLoops = 0;
1604	RTGCPHYS GCPhysBase = GCPhys;
1605	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1606	{
1607	/* Read descriptor. */
1608	SVGAGuestMemDescriptor desc;
1609	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1610	AssertRCBreak(rc);
1611
1612	if (desc.numPages != 0)
1613	{
1614	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1615	cPagesTotal += desc.numPages;
1616	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1617
1618	if ((iDesc & 15) == 0)
1619	{
1620	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1621	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1622	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1623	}
1624
1625	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1626	paDescs[iDesc++].numPages = desc.numPages;
1627
1628	/* Continue with the next descriptor. */
1629	GCPhys += sizeof(desc);
1630	}
1631	else if (desc.ppn == 0)
1632	break; /* terminator */
1633	else /* Pointer to the next physical page of descriptors. */
1634	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1635
1636	cLoops++;
1637	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1638	}
1639
1640	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1641	if (RT_SUCCESS(rc))
1642	{
1643	/* Commit the GMR. */
1644	pSVGAState->aGMR[idGMR].paDesc = paDescs;
1645	pSVGAState->aGMR[idGMR].numDescriptors = iDesc;
1646	pSVGAState->aGMR[idGMR].cMaxPages = cPagesTotal;
1647	pSVGAState->aGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1648	Assert((pSVGAState->aGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1649	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1650	idGMR, iDesc, pSVGAState->aGMR[idGMR].cbTotal, cPagesTotal));
1651	}
1652	else
1653	{
1654	RTMemFree(paDescs);
1655	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1656	}
1657	break;
1658	}
1659	# endif /* IN_RING3 */
1660	#endif // VBOX_WITH_VMSVGA3D
1661
1662	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1663	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1664	if (pThis->svga.fTraces == u32)
1665	break; /* nothing to do */
1666
1667	#ifdef IN_RING3
1668	vmsvgaSetTraces(pThis, !!u32);
1669	#else
1670	rc = VINF_IOM_R3_IOPORT_WRITE;
1671	#endif
1672	break;
1673
1674	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1675	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1676	break;
1677
1678	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1679	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1680	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1681	break;
1682
1683	case SVGA_REG_FB_START:
1684	case SVGA_REG_MEM_START:
1685	case SVGA_REG_HOST_BITS_PER_PIXEL:
1686	case SVGA_REG_MAX_WIDTH:
1687	case SVGA_REG_MAX_HEIGHT:
1688	case SVGA_REG_VRAM_SIZE:
1689	case SVGA_REG_FB_SIZE:
1690	case SVGA_REG_CAPABILITIES:
1691	case SVGA_REG_MEM_SIZE:
1692	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1693	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1694	case SVGA_REG_BYTES_PER_LINE:
1695	case SVGA_REG_FB_OFFSET:
1696	case SVGA_REG_RED_MASK:
1697	case SVGA_REG_GREEN_MASK:
1698	case SVGA_REG_BLUE_MASK:
1699	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1700	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1701	case SVGA_REG_GMR_MAX_IDS:
1702	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1703	/* Read only - ignore. */
1704	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1705	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1706	break;
1707
1708	default:
1709	{
1710	uint32_t offReg;
1711	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1712	{
1713	pThis->svga.au32ScratchRegion[offReg] = u32;
1714	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1715	}
1716	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1717	{
1718	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1719	Btw, see rgb_to_pixel32. */
1720	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1721	u32 &= 0xff;
1722	uint32_t uRgb = pThis->last_palette[offReg / 3];
1723	switch (offReg % 3)
1724	{
1725	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1726	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1727	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1728	}
1729	pThis->last_palette[offReg / 3] = uRgb;
1730	}
1731	else
1732	{
1733	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1734	rc = VINF_IOM_R3_IOPORT_WRITE;
1735	#else
1736	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1737	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1738	#endif
1739	}
1740	break;
1741	}
1742	}
1743	return rc;
1744	}
1745
1746	/**
1747	* Port I/O Handler for IN operations.
1748	*
1749	* @returns VINF_SUCCESS or VINF_EM_*.
1750	* @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1751	*
1752	* @param pDevIns The device instance.
1753	* @param pvUser User argument.
1754	* @param uPort Port number used for the IN operation.
1755	* @param pu32 Where to store the result. This is always a 32-bit
1756	* variable regardless of what @a cb might say.
1757	* @param cb Number of bytes read.
1758	*/
1759	PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
1760	{
1761	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1762	RT_NOREF_PV(pvUser);
1763
1764	/* Ignore non-dword accesses. */
1765	if (cb != 4)
1766	{
1767	Log(("Ignoring non-dword read at %x cb=%d\n", uPort, cb));
1768	*pu32 = UINT32_MAX;
1769	return VINF_SUCCESS;
1770	}
1771
1772	switch (uPort - pThis->svga.BasePort)
1773	{
1774	case SVGA_INDEX_PORT:
1775	*pu32 = pThis->svga.u32IndexReg;
1776	break;
1777
1778	case SVGA_VALUE_PORT:
1779	return vmsvgaReadPort(pThis, pu32);
1780
1781	case SVGA_BIOS_PORT:
1782	Log(("Ignoring BIOS port read\n"));
1783	*pu32 = 0;
1784	break;
1785
1786	case SVGA_IRQSTATUS_PORT:
1787	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1788	*pu32 = pThis->svga.u32IrqStatus;
1789	break;
1790	}
1791
1792	return VINF_SUCCESS;
1793	}
1794
1795	/**
1796	* Port I/O Handler for OUT operations.
1797	*
1798	* @returns VINF_SUCCESS or VINF_EM_*.
1799	*
1800	* @param pDevIns The device instance.
1801	* @param pvUser User argument.
1802	* @param uPort Port number used for the OUT operation.
1803	* @param u32 The value to output.
1804	* @param cb The value size in bytes.
1805	*/
1806	PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
1807	{
1808	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1809	RT_NOREF_PV(pvUser);
1810
1811	/* Ignore non-dword accesses. */
1812	if (cb != 4)
1813	{
1814	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", uPort, u32, cb));
1815	return VINF_SUCCESS;
1816	}
1817
1818	switch (uPort - pThis->svga.BasePort)
1819	{
1820	case SVGA_INDEX_PORT:
1821	pThis->svga.u32IndexReg = u32;
1822	break;
1823
1824	case SVGA_VALUE_PORT:
1825	return vmsvgaWritePort(pThis, u32);
1826
1827	case SVGA_BIOS_PORT:
1828	Log(("Ignoring BIOS port write (val=%x)\n", u32));
1829	break;
1830
1831	case SVGA_IRQSTATUS_PORT:
1832	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
1833	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
1834	/* Clear the irq in case all events have been cleared. */
1835	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
1836	{
1837	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
1838	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1839	}
1840	break;
1841	}
1842	return VINF_SUCCESS;
1843	}
1844
1845	#ifdef DEBUG_FIFO_ACCESS
1846
1847	# ifdef IN_RING3
1848	/**
1849	* Handle LFB access.
1850	* @returns VBox status code.
1851	* @param pVM VM handle.
1852	* @param pThis VGA device instance data.
1853	* @param GCPhys The access physical address.
1854	* @param fWriteAccess Read or write access
1855	*/
1856	static int vmsvgaFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
1857	{
1858	RT_NOREF(pVM);
1859	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
1860	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1861
1862	switch (GCPhysOffset >> 2)
1863	{
1864	case SVGA_FIFO_MIN:
1865	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1866	break;
1867	case SVGA_FIFO_MAX:
1868	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1869	break;
1870	case SVGA_FIFO_NEXT_CMD:
1871	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1872	break;
1873	case SVGA_FIFO_STOP:
1874	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1875	break;
1876	case SVGA_FIFO_CAPABILITIES:
1877	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1878	break;
1879	case SVGA_FIFO_FLAGS:
1880	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1881	break;
1882	case SVGA_FIFO_FENCE:
1883	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1884	break;
1885	case SVGA_FIFO_3D_HWVERSION:
1886	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1887	break;
1888	case SVGA_FIFO_PITCHLOCK:
1889	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1890	break;
1891	case SVGA_FIFO_CURSOR_ON:
1892	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1893	break;
1894	case SVGA_FIFO_CURSOR_X:
1895	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1896	break;
1897	case SVGA_FIFO_CURSOR_Y:
1898	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1899	break;
1900	case SVGA_FIFO_CURSOR_COUNT:
1901	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1902	break;
1903	case SVGA_FIFO_CURSOR_LAST_UPDATED:
1904	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1905	break;
1906	case SVGA_FIFO_RESERVED:
1907	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1908	break;
1909	case SVGA_FIFO_CURSOR_SCREEN_ID:
1910	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1911	break;
1912	case SVGA_FIFO_DEAD:
1913	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1914	break;
1915	case SVGA_FIFO_3D_HWVERSION_REVISED:
1916	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1917	break;
1918	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
1919	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1920	break;
1921	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
1922	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1923	break;
1924	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
1925	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1926	break;
1927	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
1928	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1929	break;
1930	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
1931	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1932	break;
1933	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
1934	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1935	break;
1936	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
1937	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1938	break;
1939	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
1940	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1941	break;
1942	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
1943	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1944	break;
1945	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
1946	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1947	break;
1948	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
1949	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1950	break;
1951	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
1952	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1953	break;
1954	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
1955	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1956	break;
1957	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
1958	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1959	break;
1960	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
1961	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1962	break;
1963	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
1964	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1965	break;
1966	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
1967	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1968	break;
1969	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
1970	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1971	break;
1972	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
1973	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1974	break;
1975	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
1976	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1977	break;
1978	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
1979	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1980	break;
1981	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
1982	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1983	break;
1984	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
1985	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1986	break;
1987	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
1988	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1989	break;
1990	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
1991	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1992	break;
1993	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
1994	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1995	break;
1996	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
1997	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1998	break;
1999	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2000	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2001	break;
2002	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2003	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2004	break;
2005	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2006	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2007	break;
2008	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2009	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2010	break;
2011	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2012	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2013	break;
2014	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2015	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2016	break;
2017	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2018	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2019	break;
2020	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2021	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2022	break;
2023	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2024	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2025	break;
2026	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2027	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2028	break;
2029	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2030	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2031	break;
2032	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2033	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2034	break;
2035	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2036	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2037	break;
2038	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2039	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2040	break;
2041	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2042	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2043	break;
2044	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2045	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2046	break;
2047	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2048	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2049	break;
2050	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2051	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2052	break;
2053	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2054	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2055	break;
2056	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2057	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2058	break;
2059	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2060	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2061	break;
2062	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2063	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2064	break;
2065	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2066	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2067	break;
2068	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2069	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2070	break;
2071	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2072	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2073	break;
2074	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2075	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2076	break;
2077	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2078	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2079	break;
2080	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2081	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2082	break;
2083	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2084	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2085	break;
2086	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2087	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2088	break;
2089	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2090	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2091	break;
2092	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2093	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2094	break;
2095	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2096	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2097	break;
2098	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2099	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2100	break;
2101	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2102	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2103	break;
2104	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2105	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2106	break;
2107	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2108	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2109	break;
2110	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2111	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2112	break;
2113	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2114	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2115	break;
2116	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2117	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2118	break;
2119	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2120	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2121	break;
2122	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2123	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2124	break;
2125	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2126	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2127	break;
2128	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2129	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2130	break;
2131	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2132	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2133	break;
2134	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2135	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2136	break;
2137	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2138	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2139	break;
2140	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2141	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2142	break;
2143	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2144	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2145	break;
2146	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2147	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2148	break;
2149	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2150	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2151	break;
2152	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2153	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2154	break;
2155	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2156	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2157	break;
2158	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2159	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2160	break;
2161	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2162	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2163	break;
2164	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2165	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2166	break;
2167	case SVGA_FIFO_3D_CAPS_LAST:
2168	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2169	break;
2170	case SVGA_FIFO_GUEST_3D_HWVERSION:
2171	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2172	break;
2173	case SVGA_FIFO_FENCE_GOAL:
2174	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2175	break;
2176	case SVGA_FIFO_BUSY:
2177	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2178	break;
2179	default:
2180	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2181	break;
2182	}
2183
2184	return VINF_EM_RAW_EMULATE_INSTR;
2185	}
2186
2187	/**
2188	* HC access handler for the FIFO.
2189	*
2190	* @returns VINF_SUCCESS if the handler have carried out the operation.
2191	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2192	* @param pVM VM Handle.
2193	* @param pVCpu The cross context CPU structure for the calling EMT.
2194	* @param GCPhys The physical address the guest is writing to.
2195	* @param pvPhys The HC mapping of that address.
2196	* @param pvBuf What the guest is reading/writing.
2197	* @param cbBuf How much it's reading/writing.
2198	* @param enmAccessType The access type.
2199	* @param enmOrigin Who is making the access.
2200	* @param pvUser User argument.
2201	*/
2202	static DECLCALLBACK(VBOXSTRICTRC)
2203	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2204	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2205	{
2206	PVGASTATE pThis = (PVGASTATE)pvUser;
2207	int rc;
2208	Assert(pThis);
2209	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2210	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
2211
2212	rc = vmsvgaFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2213	if (RT_SUCCESS(rc))
2214	return VINF_PGM_HANDLER_DO_DEFAULT;
2215	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2216	return rc;
2217	}
2218
2219	# endif /* IN_RING3 */
2220	#endif /* DEBUG_FIFO_ACCESS */
2221
2222	#ifdef DEBUG_GMR_ACCESS
2223	# ifdef IN_RING3
2224
2225	/**
2226	* HC access handler for the FIFO.
2227	*
2228	* @returns VINF_SUCCESS if the handler have carried out the operation.
2229	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2230	* @param pVM VM Handle.
2231	* @param pVCpu The cross context CPU structure for the calling EMT.
2232	* @param GCPhys The physical address the guest is writing to.
2233	* @param pvPhys The HC mapping of that address.
2234	* @param pvBuf What the guest is reading/writing.
2235	* @param cbBuf How much it's reading/writing.
2236	* @param enmAccessType The access type.
2237	* @param enmOrigin Who is making the access.
2238	* @param pvUser User argument.
2239	*/
2240	static DECLCALLBACK(VBOXSTRICTRC)
2241	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2242	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2243	{
2244	PVGASTATE pThis = (PVGASTATE)pvUser;
2245	Assert(pThis);
2246	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2247	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2248
2249	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2250
2251	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
2252	{
2253	PGMR pGMR = &pSVGAState->aGMR[i];
2254
2255	if (pGMR->numDescriptors)
2256	{
2257	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2258	{
2259	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2260	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2261	{
2262	/*
2263	* Turn off the write handler for this particular page and make it R/W.
2264	* Then return telling the caller to restart the guest instruction.
2265	*/
2266	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2267	AssertRC(rc);
2268	goto end;
2269	}
2270	}
2271	}
2272	}
2273	end:
2274	return VINF_PGM_HANDLER_DO_DEFAULT;
2275	}
2276
2277	/* Callback handler for VMR3ReqCallWaitU */
2278	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2279	{
2280	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2281	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2282	PGMR pGMR = &pSVGAState->aGMR[gmrId];
2283	int rc;
2284
2285	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2286	{
2287	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2288	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2289	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2290	AssertRC(rc);
2291	}
2292	return VINF_SUCCESS;
2293	}
2294
2295	/* Callback handler for VMR3ReqCallWaitU */
2296	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2297	{
2298	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2299	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2300	PGMR pGMR = &pSVGAState->aGMR[gmrId];
2301
2302	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2303	{
2304	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2305	AssertRC(rc);
2306	}
2307	return VINF_SUCCESS;
2308	}
2309
2310	/* Callback handler for VMR3ReqCallWaitU */
2311	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2312	{
2313	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2314
2315	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
2316	{
2317	PGMR pGMR = &pSVGAState->aGMR[i];
2318
2319	if (pGMR->numDescriptors)
2320	{
2321	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2322	{
2323	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2324	AssertRC(rc);
2325	}
2326	}
2327	}
2328	return VINF_SUCCESS;
2329	}
2330
2331	# endif /* IN_RING3 */
2332	#endif /* DEBUG_GMR_ACCESS */
2333
2334	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2335
2336	#ifdef IN_RING3
2337
2338
2339	/**
2340	* Common worker for changing the pointer shape.
2341	*
2342	* @param pThis The VGA instance data.
2343	* @param pSVGAState The VMSVGA ring-3 instance data.
2344	* @param fAlpha Whether there is alpha or not.
2345	* @param xHot Hotspot x coordinate.
2346	* @param yHot Hotspot y coordinate.
2347	* @param cx Width.
2348	* @param cy Height.
2349	* @param pbData Heap copy of the cursor data. Consumed.
2350	* @param cbData The size of the data.
2351	*/
2352	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2353	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2354	{
2355	Log(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2356	#ifdef LOG_ENABLED
2357	if (LogIs2Enabled())
2358	{
2359	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2360	if (!fAlpha)
2361	{
2362	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2363	for (uint32_t y = 0; y < cy; y++)
2364	{
2365	Log2(("%3u:", y));
2366	uint8_t const pbLine = &pbData[y cbAndLine];
2367	for (uint32_t x = 0; x < cx; x += 8)
2368	{
2369	uint8_t b = pbLine[x / 8];
2370	char szByte[12];
2371	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2372	szByte[1] = b & 0x40 ? '*' : ' ';
2373	szByte[2] = b & 0x20 ? '*' : ' ';
2374	szByte[3] = b & 0x10 ? '*' : ' ';
2375	szByte[4] = b & 0x08 ? '*' : ' ';
2376	szByte[5] = b & 0x04 ? '*' : ' ';
2377	szByte[6] = b & 0x02 ? '*' : ' ';
2378	szByte[7] = b & 0x01 ? '*' : ' ';
2379	szByte[8] = '\0';
2380	Log2(("%s", szByte));
2381	}
2382	Log2(("\n"));
2383	}
2384	}
2385
2386	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2387	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2388	for (uint32_t y = 0; y < cy; y++)
2389	{
2390	Log2(("%3u:", y));
2391	uint32_t const pu32Line = &pu32Xor[y cx];
2392	for (uint32_t x = 0; x < cx; x++)
2393	Log2((" %08x", pu32Line[x]));
2394	Log2(("\n"));
2395	}
2396	}
2397	#endif
2398
2399	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2400	AssertRC(rc);
2401
2402	if (pSVGAState->Cursor.fActive)
2403	RTMemFree(pSVGAState->Cursor.pData);
2404
2405	pSVGAState->Cursor.fActive = true;
2406	pSVGAState->Cursor.xHotspot = xHot;
2407	pSVGAState->Cursor.yHotspot = yHot;
2408	pSVGAState->Cursor.width = cx;
2409	pSVGAState->Cursor.height = cy;
2410	pSVGAState->Cursor.cbData = cbData;
2411	pSVGAState->Cursor.pData = pbData;
2412	}
2413
2414
2415	/**
2416	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2417	*
2418	* @param pThis The VGA instance data.
2419	* @param pSVGAState The VMSVGA ring-3 instance data.
2420	* @param pCursor The cursor.
2421	* @param pbSrcAndMask The AND mask.
2422	* @param cbSrcAndLine The scanline length of the AND mask.
2423	* @param pbSrcXorMask The XOR mask.
2424	* @param cbSrcXorLine The scanline length of the XOR mask.
2425	*/
2426	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2427	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2428	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2429	{
2430	uint32_t const cx = pCursor->width;
2431	uint32_t const cy = pCursor->height;
2432
2433	/*
2434	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2435	* The AND data uses 8-bit aligned scanlines.
2436	* The XOR data must be starting on a 32-bit boundrary.
2437	*/
2438	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2439	uint32_t cbDstAndMask = cbDstAndLine * cy;
2440	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2441	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2442
2443	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2444	AssertReturnVoid(pbCopy);
2445
2446	/* Convert the AND mask. */
2447	uint8_t *pbDst = pbCopy;
2448	uint8_t const *pbSrc = pbSrcAndMask;
2449	switch (pCursor->andMaskDepth)
2450	{
2451	case 1:
2452	if (cbSrcAndLine == cbDstAndLine)
2453	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2454	else
2455	{
2456	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2457	for (uint32_t y = 0; y < cy; y++)
2458	{
2459	memcpy(pbDst, pbSrc, cbDstAndLine);
2460	pbDst += cbDstAndLine;
2461	pbSrc += cbSrcAndLine;
2462	}
2463	}
2464	break;
2465	/* Should take the XOR mask into account for the multi-bit AND mask. */
2466	case 8:
2467	for (uint32_t y = 0; y < cy; y++)
2468	{
2469	for (uint32_t x = 0; x < cx; )
2470	{
2471	uint8_t bDst = 0;
2472	uint8_t fBit = 1;
2473	do
2474	{
2475	uintptr_t const idxPal = pbSrc[x] * 3;
2476	if ((( pThis->last_palette[idxPal]
2477	\| (pThis->last_palette[idxPal] >> 8)
2478	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2479	bDst \|= fBit;
2480	fBit <<= 1;
2481	x++;
2482	} while (x < cx && (x & 7));
2483	pbDst[(x - 1) / 8] = bDst;
2484	}
2485	pbDst += cbDstAndLine;
2486	pbSrc += cbSrcAndLine;
2487	}
2488	break;
2489	case 15:
2490	for (uint32_t y = 0; y < cy; y++)
2491	{
2492	for (uint32_t x = 0; x < cx; )
2493	{
2494	uint8_t bDst = 0;
2495	uint8_t fBit = 1;
2496	do
2497	{
2498	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2499	bDst \|= fBit;
2500	fBit <<= 1;
2501	x++;
2502	} while (x < cx && (x & 7));
2503	pbDst[(x - 1) / 8] = bDst;
2504	}
2505	pbDst += cbDstAndLine;
2506	pbSrc += cbSrcAndLine;
2507	}
2508	break;
2509	case 16:
2510	for (uint32_t y = 0; y < cy; y++)
2511	{
2512	for (uint32_t x = 0; x < cx; )
2513	{
2514	uint8_t bDst = 0;
2515	uint8_t fBit = 1;
2516	do
2517	{
2518	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2519	bDst \|= fBit;
2520	fBit <<= 1;
2521	x++;
2522	} while (x < cx && (x & 7));
2523	pbDst[(x - 1) / 8] = bDst;
2524	}
2525	pbDst += cbDstAndLine;
2526	pbSrc += cbSrcAndLine;
2527	}
2528	break;
2529	case 24:
2530	for (uint32_t y = 0; y < cy; y++)
2531	{
2532	for (uint32_t x = 0; x < cx; )
2533	{
2534	uint8_t bDst = 0;
2535	uint8_t fBit = 1;
2536	do
2537	{
2538	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2539	bDst \|= fBit;
2540	fBit <<= 1;
2541	x++;
2542	} while (x < cx && (x & 7));
2543	pbDst[(x - 1) / 8] = bDst;
2544	}
2545	pbDst += cbDstAndLine;
2546	pbSrc += cbSrcAndLine;
2547	}
2548	break;
2549	case 32:
2550	for (uint32_t y = 0; y < cy; y++)
2551	{
2552	for (uint32_t x = 0; x < cx; )
2553	{
2554	uint8_t bDst = 0;
2555	uint8_t fBit = 1;
2556	do
2557	{
2558	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2559	bDst \|= fBit;
2560	fBit <<= 1;
2561	x++;
2562	} while (x < cx && (x & 7));
2563	pbDst[(x - 1) / 8] = bDst;
2564	}
2565	pbDst += cbDstAndLine;
2566	pbSrc += cbSrcAndLine;
2567	}
2568	break;
2569	default:
2570	RTMemFree(pbCopy);
2571	AssertFailedReturnVoid();
2572	}
2573
2574	/* Convert the XOR mask. */
2575	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2576	pbSrc = pbSrcXorMask;
2577	switch (pCursor->xorMaskDepth)
2578	{
2579	case 1:
2580	for (uint32_t y = 0; y < cy; y++)
2581	{
2582	for (uint32_t x = 0; x < cx; )
2583	{
2584	/* most significant bit is the left most one. */
2585	uint8_t bSrc = pbSrc[x / 8];
2586	do
2587	{
2588	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2589	bSrc <<= 1;
2590	x++;
2591	} while ((x & 7) && x < cx);
2592	}
2593	pbSrc += cbSrcXorLine;
2594	}
2595	break;
2596	case 8:
2597	for (uint32_t y = 0; y < cy; y++)
2598	{
2599	for (uint32_t x = 0; x < cx; x++)
2600	{
2601	uint32_t u = pThis->last_palette[pbSrc[x]];
2602	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2603	}
2604	pbSrc += cbSrcXorLine;
2605	}
2606	break;
2607	case 15: /* Src: RGB-5-5-5 */
2608	for (uint32_t y = 0; y < cy; y++)
2609	{
2610	for (uint32_t x = 0; x < cx; x++)
2611	{
2612	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2613	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2614	((uValue >> 5) & 0x1f) << 3,
2615	((uValue >> 10) & 0x1f) << 3, 0);
2616	}
2617	pbSrc += cbSrcXorLine;
2618	}
2619	break;
2620	case 16: /* Src: RGB-5-6-5 */
2621	for (uint32_t y = 0; y < cy; y++)
2622	{
2623	for (uint32_t x = 0; x < cx; x++)
2624	{
2625	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2626	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2627	((uValue >> 5) & 0x3f) << 2,
2628	((uValue >> 11) & 0x1f) << 3, 0);
2629	}
2630	pbSrc += cbSrcXorLine;
2631	}
2632	break;
2633	case 24:
2634	for (uint32_t y = 0; y < cy; y++)
2635	{
2636	for (uint32_t x = 0; x < cx; x++)
2637	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2638	pbSrc += cbSrcXorLine;
2639	}
2640	break;
2641	case 32:
2642	for (uint32_t y = 0; y < cy; y++)
2643	{
2644	for (uint32_t x = 0; x < cx; x++)
2645	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2646	pbSrc += cbSrcXorLine;
2647	}
2648	break;
2649	default:
2650	RTMemFree(pbCopy);
2651	AssertFailedReturnVoid();
2652	}
2653
2654	/*
2655	* Pass it to the frontend/whatever.
2656	*/
2657	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2658	}
2659
2660
2661	/**
2662	* Worker for vmsvgaR3FifoThread that handles an external command.
2663	*
2664	* @param pThis VGA device instance data.
2665	*/
2666	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2667	{
2668	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2669	switch (pThis->svga.u8FIFOExtCommand)
2670	{
2671	case VMSVGA_FIFO_EXTCMD_RESET:
2672	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2673	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2674	# ifdef VBOX_WITH_VMSVGA3D
2675	if (pThis->svga.f3DEnabled)
2676	{
2677	/* The 3d subsystem must be reset from the fifo thread. */
2678	vmsvga3dReset(pThis);
2679	}
2680	# endif
2681	break;
2682
2683	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2684	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2685	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2686	# ifdef VBOX_WITH_VMSVGA3D
2687	if (pThis->svga.f3DEnabled)
2688	{
2689	/* The 3d subsystem must be shut down from the fifo thread. */
2690	vmsvga3dTerminate(pThis);
2691	}
2692	# endif
2693	break;
2694
2695	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2696	{
2697	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2698	# ifdef VBOX_WITH_VMSVGA3D
2699	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2700	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2701	vmsvga3dSaveExec(pThis, pSSM);
2702	# endif
2703	break;
2704	}
2705
2706	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2707	{
2708	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2709	# ifdef VBOX_WITH_VMSVGA3D
2710	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2711	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2712	vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2713	# endif
2714	break;
2715	}
2716
2717	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2718	{
2719	# ifdef VBOX_WITH_VMSVGA3D
2720	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2721	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2722	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2723	# endif
2724	break;
2725	}
2726
2727
2728	default:
2729	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2730	break;
2731	}
2732
2733	/*
2734	* Signal the end of the external command.
2735	*/
2736	pThis->svga.pvFIFOExtCmdParam = NULL;
2737	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2738	ASMMemoryFence(); /* paranoia^2 */
2739	int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2740	AssertLogRelRC(rc);
2741	}
2742
2743	/**
2744	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2745	* doing a job on the FIFO thread (even when it's officially suspended).
2746	*
2747	* @returns VBox status code (fully asserted).
2748	* @param pThis VGA device instance data.
2749	* @param uExtCmd The command to execute on the FIFO thread.
2750	* @param pvParam Pointer to command parameters.
2751	* @param cMsWait The time to wait for the command, given in
2752	* milliseconds.
2753	*/
2754	static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2755	{
2756	Assert(cMsWait >= RT_MS_1SEC * 5);
2757	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2758	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2759
2760	int rc;
2761	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2762	PDMTHREADSTATE enmState = pThread->enmState;
2763	if (enmState == PDMTHREADSTATE_SUSPENDED)
2764	{
2765	/*
2766	* The thread is suspended, we have to temporarily wake it up so it can
2767	* perform the task.
2768	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
2769	*/
2770	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2771	/* Post the request. */
2772	pThis->svga.fFifoExtCommandWakeup = true;
2773	pThis->svga.pvFIFOExtCmdParam = pvParam;
2774	pThis->svga.u8FIFOExtCommand = uExtCmd;
2775	ASMMemoryFence(); /* paranoia^3 */
2776
2777	/* Resume the thread. */
2778	rc = PDMR3ThreadResume(pThread);
2779	AssertLogRelRC(rc);
2780	if (RT_SUCCESS(rc))
2781	{
2782	/* Wait. Take care in case the semaphore was already posted (same as below). */
2783	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2784	if ( rc == VINF_SUCCESS
2785	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
2786	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2787	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
2788	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2789
2790	/* suspend the thread */
2791	pThis->svga.fFifoExtCommandWakeup = false;
2792	int rc2 = PDMR3ThreadSuspend(pThread);
2793	AssertLogRelRC(rc2);
2794	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2795	rc = rc2;
2796	}
2797	pThis->svga.fFifoExtCommandWakeup = false;
2798	pThis->svga.pvFIFOExtCmdParam = NULL;
2799	}
2800	else if (enmState == PDMTHREADSTATE_RUNNING)
2801	{
2802	/*
2803	* The thread is running, should only happen during reset and vmsvga3dsfc.
2804	* We ASSUME not racing code here, both wrt thread state and ext commands.
2805	*/
2806	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
2807	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
2808
2809	/* Post the request. */
2810	pThis->svga.pvFIFOExtCmdParam = pvParam;
2811	pThis->svga.u8FIFOExtCommand = uExtCmd;
2812	ASMMemoryFence(); /* paranoia^2 */
2813	rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2814	AssertLogRelRC(rc);
2815
2816	/* Wait. Take care in case the semaphore was already posted (same as above). */
2817	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2818	if ( rc == VINF_SUCCESS
2819	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
2820	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
2821	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
2822	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2823
2824	pThis->svga.pvFIFOExtCmdParam = NULL;
2825	}
2826	else
2827	{
2828	/*
2829	* Something is wrong with the thread!
2830	*/
2831	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
2832	rc = VERR_INVALID_STATE;
2833	}
2834	return rc;
2835	}
2836
2837
2838	/**
2839	* Marks the FIFO non-busy, notifying any waiting EMTs.
2840	*
2841	* @param pThis The VGA state.
2842	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
2843	* @param offFifoMin The start byte offset of the command FIFO.
2844	*/
2845	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
2846	{
2847	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
2848	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2849	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
2850
2851	/* Wake up any waiting EMTs. */
2852	if (pSVGAState->cBusyDelayedEmts > 0)
2853	{
2854	#ifdef VMSVGA_USE_EMT_HALT_CODE
2855	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
2856	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
2857	if (idCpu != NIL_VMCPUID)
2858	{
2859	VMR3NotifyCpuDeviceReady(pVM, idCpu);
2860	while (idCpu-- > 0)
2861	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
2862	VMR3NotifyCpuDeviceReady(pVM, idCpu);
2863	}
2864	#else
2865	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
2866	AssertRC(rc2);
2867	#endif
2868	}
2869	}
2870
2871	/**
2872	* Reads (more) payload into the command buffer.
2873	*
2874	* @returns pbBounceBuf on success
2875	* @retval (void *)1 if the thread was requested to stop.
2876	* @retval NULL on FIFO error.
2877	*
2878	* @param cbPayloadReq The number of bytes of payload requested.
2879	* @param pFIFO The FIFO.
2880	* @param offCurrentCmd The FIFO byte offset of the current command.
2881	* @param offFifoMin The start byte offset of the command FIFO.
2882	* @param offFifoMax The end byte offset of the command FIFO.
2883	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
2884	* always sufficient size.
2885	* @param pcbAlreadyRead How much payload we've already read into the bounce
2886	* buffer. (We will NEVER re-read anything.)
2887	* @param pThread The calling PDM thread handle.
2888	* @param pThis The VGA state.
2889	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
2890	* statistics collection.
2891	*/
2892	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t volatile pFIFO,
2893	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
2894	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
2895	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
2896	{
2897	Assert(pbBounceBuf);
2898	Assert(pcbAlreadyRead);
2899	Assert(offFifoMin < offFifoMax);
2900	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
2901	Assert(offFifoMax <= pThis->svga.cbFIFO);
2902
2903	/*
2904	* Check if the requested payload size has already been satisfied .
2905	* .
2906	* When called to read more, the caller is responsible for making sure the .
2907	* new command size (cbRequsted) never is smaller than what has already .
2908	* been read.
2909	*/
2910	uint32_t cbAlreadyRead = *pcbAlreadyRead;
2911	if (cbPayloadReq <= cbAlreadyRead)
2912	{
2913	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
2914	return pbBounceBuf;
2915	}
2916
2917	/*
2918	* Commands bigger than the fifo buffer are invalid.
2919	*/
2920	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
2921	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
2922	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
2923	NULL);
2924
2925	/*
2926	* Move offCurrentCmd past the command dword.
2927	*/
2928	offCurrentCmd += sizeof(uint32_t);
2929	if (offCurrentCmd >= offFifoMax)
2930	offCurrentCmd = offFifoMin;
2931
2932	/*
2933	* Do we have sufficient payload data available already?
2934	*/
2935	uint32_t cbAfter, cbBefore;
2936	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2937	if (offNextCmd > offCurrentCmd)
2938	{
2939	if (RT_LIKELY(offNextCmd < offFifoMax))
2940	cbAfter = offNextCmd - offCurrentCmd;
2941	else
2942	{
2943	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2944	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2945	offNextCmd, offFifoMin, offFifoMax));
2946	cbAfter = offFifoMax - offCurrentCmd;
2947	}
2948	cbBefore = 0;
2949	}
2950	else
2951	{
2952	cbAfter = offFifoMax - offCurrentCmd;
2953	if (offNextCmd >= offFifoMin)
2954	cbBefore = offNextCmd - offFifoMin;
2955	else
2956	{
2957	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2958	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2959	offNextCmd, offFifoMin, offFifoMax));
2960	cbBefore = 0;
2961	}
2962	}
2963	if (cbAfter + cbBefore < cbPayloadReq)
2964	{
2965	/*
2966	* Insufficient, must wait for it to arrive.
2967	*/
2968	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
2969	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
2970	for (uint32_t i = 0;; i++)
2971	{
2972	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2973	{
2974	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2975	return (void *)(uintptr_t)1;
2976	}
2977	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
2978	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
2979
2980	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
2981
2982	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2983	if (offNextCmd > offCurrentCmd)
2984	{
2985	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
2986	cbBefore = 0;
2987	}
2988	else
2989	{
2990	cbAfter = offFifoMax - offCurrentCmd;
2991	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
2992	}
2993
2994	if (cbAfter + cbBefore >= cbPayloadReq)
2995	break;
2996	}
2997	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2998	}
2999
3000	/*
3001	* Copy out the memory and update what pcbAlreadyRead points to.
3002	*/
3003	if (cbAfter >= cbPayloadReq)
3004	memcpy(pbBounceBuf + cbAlreadyRead,
3005	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3006	cbPayloadReq - cbAlreadyRead);
3007	else
3008	{
3009	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3010	if (cbAlreadyRead < cbAfter)
3011	{
3012	memcpy(pbBounceBuf + cbAlreadyRead,
3013	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3014	cbAfter - cbAlreadyRead);
3015	cbAlreadyRead = cbAfter;
3016	}
3017	memcpy(pbBounceBuf + cbAlreadyRead,
3018	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3019	cbPayloadReq - cbAlreadyRead);
3020	}
3021	*pcbAlreadyRead = cbPayloadReq;
3022	return pbBounceBuf;
3023	}
3024
3025	/* The async FIFO handling thread. */
3026	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3027	{
3028	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3029	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3030	int rc;
3031
3032	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3033	return VINF_SUCCESS;
3034
3035	/*
3036	* Special mode where we only execute an external command and the go back
3037	* to being suspended. Currently, all ext cmds ends up here, with the reset
3038	* one also being eligble for runtime execution further down as well.
3039	*/
3040	if (pThis->svga.fFifoExtCommandWakeup)
3041	{
3042	vmsvgaR3FifoHandleExtCmd(pThis);
3043	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3044	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3045	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
3046	else
3047	vmsvgaR3FifoHandleExtCmd(pThis);
3048	return VINF_SUCCESS;
3049	}
3050
3051
3052	/*
3053	* Signal the semaphore to make sure we don't wait for 250ms after a
3054	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3055	*/
3056	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3057
3058	/*
3059	* Allocate a bounce buffer for command we get from the FIFO.
3060	* (All code must return via the end of the function to free this buffer.)
3061	*/
3062	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3063	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3064
3065	/*
3066	* Polling/sleep interval config.
3067	*
3068	* We wait for an a short interval if the guest has recently given us work
3069	* to do, but the interval increases the longer we're kept idle. With the
3070	* current parameters we'll be at a 64ms poll interval after 1 idle second,
3071	* at 90ms after 2 seconds, and reach the max 250ms interval after about
3072	* 16 seconds.
3073	*/
3074	RTMSINTERVAL const cMsMinSleep = 16;
3075	RTMSINTERVAL const cMsIncSleep = 2;
3076	RTMSINTERVAL const cMsMaxSleep = 250;
3077	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3078
3079	/*
3080	* The FIFO loop.
3081	*/
3082	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3083	bool fBadOrDisabledFifo = false;
3084	uint32_t volatile * const pFIFO = pThis->svga.pFIFOR3;
3085	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3086	{
3087	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3088	/*
3089	* Should service the run loop every so often.
3090	*/
3091	if (pThis->svga.f3DEnabled)
3092	vmsvga3dCocoaServiceRunLoop();
3093	# endif
3094
3095	/*
3096	* Unless there's already work pending, go to sleep for a short while.
3097	* (See polling/sleep interval config above.)
3098	*/
3099	if ( fBadOrDisabledFifo
3100	\|\| pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
3101	{
3102	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
3103	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3104	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3105	{
3106	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3107	break;
3108	}
3109	}
3110	else
3111	rc = VINF_SUCCESS;
3112	fBadOrDisabledFifo = false;
3113	if (rc == VERR_TIMEOUT)
3114	{
3115	if (pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
3116	{
3117	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3118	continue;
3119	}
3120	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3121
3122	Log(("vmsvgaFIFOLoop: timeout\n"));
3123	}
3124	else if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3125	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3126	cMsSleep = cMsMinSleep;
3127
3128	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
3129	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3130	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3131
3132	/*
3133	* Handle external commands (currently only reset).
3134	*/
3135	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3136	{
3137	vmsvgaR3FifoHandleExtCmd(pThis);
3138	continue;
3139	}
3140
3141	/*
3142	* The device must be enabled and configured.
3143	*/
3144	if ( !pThis->svga.fEnabled
3145	\|\| !pThis->svga.fConfigured)
3146	{
3147	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3148	fBadOrDisabledFifo = true;
3149	continue;
3150	}
3151
3152	/*
3153	* Get and check the min/max values. We ASSUME that they will remain
3154	* unchanged while we process requests. A further ASSUMPTION is that
3155	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3156	* we don't read it back while in the loop.
3157	*/
3158	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3159	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3160	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3161	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3162	\|\| offFifoMax <= offFifoMin
3163	\|\| offFifoMax > pThis->svga.cbFIFO
3164	\|\| (offFifoMax & 3) != 0
3165	\|\| (offFifoMin & 3) != 0
3166	\|\| offCurrentCmd < offFifoMin
3167	\|\| offCurrentCmd > offFifoMax))
3168	{
3169	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3170	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3171	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3172	fBadOrDisabledFifo = true;
3173	continue;
3174	}
3175	if (RT_UNLIKELY(offCurrentCmd & 3))
3176	{
3177	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3178	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3179	offCurrentCmd = ~UINT32_C(3);
3180	}
3181
3182	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3183	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3184	*
3185	* Will break out of the switch on failure.
3186	* Will restart and quit the loop if the thread was requested to stop.
3187	*
3188	* @param a_PtrVar Request variable pointer.
3189	* @param a_Type Request typedef (not pointer) for casting.
3190	* @param a_cbPayloadReq How much payload to fetch.
3191	* @remarks Accesses a bunch of variables in the current scope!
3192	*/
3193	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3194	if (1) { \
3195	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3196	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
3197	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3198	} else do {} while (0)
3199	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3200	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3201	* buffer after figuring out the actual command size.
3202	*
3203	* Will break out of the switch on failure.
3204	*
3205	* @param a_PtrVar Request variable pointer.
3206	* @param a_Type Request typedef (not pointer) for casting.
3207	* @param a_cbPayloadReq How much payload to fetch.
3208	* @remarks Accesses a bunch of variables in the current scope!
3209	*/
3210	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3211	if (1) { \
3212	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3213	} else do {} while (0)
3214
3215	/*
3216	* Mark the FIFO as busy.
3217	*/
3218	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3219	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3220	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3221
3222	/*
3223	* Execute all queued FIFO commands.
3224	* Quit if pending external command or changes in the thread state.
3225	*/
3226	bool fDone = false;
3227	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3228	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3229	{
3230	uint32_t cbPayload = 0;
3231	uint32_t u32IrqStatus = 0;
3232
3233	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3234
3235	/* First check any pending actions. */
3236	if ( ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT)
3237	&& pThis->svga.p3dState != NULL)
3238	# ifdef VBOX_WITH_VMSVGA3D
3239	vmsvga3dChangeMode(pThis);
3240	# else
3241	{/nothing/}
3242	# endif
3243	/* Check for pending external commands (reset). */
3244	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3245	break;
3246
3247	/*
3248	* Process the command.
3249	*/
3250	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3251	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3252	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3253	switch (enmCmdId)
3254	{
3255	case SVGA_CMD_INVALID_CMD:
3256	/* Nothing to do. */
3257	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3258	break;
3259
3260	case SVGA_CMD_FENCE:
3261	{
3262	SVGAFifoCmdFence *pCmdFence;
3263	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3264	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3265	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3266	{
3267	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3268	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3269
3270	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3271	{
3272	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3273	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3274	}
3275	else
3276	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3277	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3278	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3279	{
3280	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3281	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3282	}
3283	}
3284	else
3285	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3286	break;
3287	}
3288	case SVGA_CMD_UPDATE:
3289	case SVGA_CMD_UPDATE_VERBOSE:
3290	{
3291	SVGAFifoCmdUpdate *pUpdate;
3292	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3293	if (enmCmdId == SVGA_CMD_UPDATE)
3294	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3295	else
3296	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3297	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3298	vgaR3UpdateDisplay(pThis, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3299	break;
3300	}
3301
3302	case SVGA_CMD_DEFINE_CURSOR:
3303	{
3304	/* Followed by bitmap data. */
3305	SVGAFifoCmdDefineCursor *pCursor;
3306	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3307	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3308
3309	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3310	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3311	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3312	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3313	AssertBreak(pCursor->andMaskDepth <= 32);
3314	AssertBreak(pCursor->xorMaskDepth <= 32);
3315
3316	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3317	uint32_t cbAndMask = cbAndLine * pCursor->height;
3318	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3319	uint32_t cbXorMask = cbXorLine * pCursor->height;
3320	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3321
3322	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3323	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3324	break;
3325	}
3326
3327	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3328	{
3329	/* Followed by bitmap data. */
3330	uint32_t cbCursorShape, cbAndMask;
3331	uint8_t *pCursorCopy;
3332	uint32_t cbCmd;
3333
3334	SVGAFifoCmdDefineAlphaCursor *pCursor;
3335	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3336	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3337
3338	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3339
3340	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3341	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3342
3343	/* Refetch the bitmap data as well. */
3344	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3345	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3346	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3347
3348	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3349	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3350	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3351	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3352
3353	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3354	AssertBreak(pCursorCopy);
3355
3356	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3357	memset(pCursorCopy, 0xff, cbAndMask);
3358	/* Colour data */
3359	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3360
3361	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3362	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3363	break;
3364	}
3365
3366	case SVGA_CMD_ESCAPE:
3367	{
3368	/* Followed by nsize bytes of data. */
3369	SVGAFifoCmdEscape *pEscape;
3370	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3371	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3372
3373	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3374	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3375	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3376	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3377
3378	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3379	{
3380	AssertBreak(pEscape->size >= sizeof(uint32_t));
3381	uint32_t cmd = (uint32_t )(pEscape + 1);
3382	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3383
3384	switch (cmd)
3385	{
3386	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3387	{
3388	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3389	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3390	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3391
3392	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3393	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3394	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3395
3396	RT_NOREF_PV(pVideoCmd);
3397	break;
3398
3399	}
3400
3401	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3402	{
3403	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3404	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3405	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3406	RT_NOREF_PV(pVideoCmd);
3407	break;
3408	}
3409	}
3410	}
3411	else
3412	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3413
3414	break;
3415	}
3416	# ifdef VBOX_WITH_VMSVGA3D
3417	case SVGA_CMD_DEFINE_GMR2:
3418	{
3419	SVGAFifoCmdDefineGMR2 *pCmd;
3420	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3421	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3422	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3423
3424	/* Validate current GMR id. */
3425	AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
3426	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3427
3428	if (!pCmd->numPages)
3429	{
3430	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3431	vmsvgaGMRFree(pThis, pCmd->gmrId);
3432	}
3433	else
3434	{
3435	PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
3436	if (pGMR->cMaxPages)
3437	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3438
3439	/* Not sure if we should always free the descriptor, but for simplicity
3440	we do so if the new size is smaller than the current. */
3441	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3442	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3443	vmsvgaGMRFree(pThis, pCmd->gmrId);
3444
3445	pGMR->cMaxPages = pCmd->numPages;
3446	/* The rest is done by the REMAP_GMR2 command. */
3447	}
3448	break;
3449	}
3450
3451	case SVGA_CMD_REMAP_GMR2:
3452	{
3453	/* Followed by page descriptors or guest ptr. */
3454	SVGAFifoCmdRemapGMR2 *pCmd;
3455	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3456	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3457
3458	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3459	AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
3460
3461	/* Calculate the size of what comes after next and fetch it. */
3462	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3463	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3464	cbCmd += sizeof(SVGAGuestPtr);
3465	else
3466	{
3467	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3468	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3469	{
3470	cbCmd += cbPageDesc;
3471	pCmd->numPages = 1;
3472	}
3473	else
3474	{
3475	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3476	cbCmd += cbPageDesc * pCmd->numPages;
3477	}
3478	}
3479	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3480
3481	/* Validate current GMR id and size. */
3482	AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
3483	PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
3484	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3485	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3486	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3487
3488	if (pCmd->numPages == 0)
3489	break;
3490
3491	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3492	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3493
3494	/*
3495	* We flatten the existing descriptors into a page array, overwrite the
3496	* pages specified in this command and then recompress the descriptor.
3497	*/
3498	/** @todo Optimize the GMR remap algorithm! */
3499
3500	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3501	uint64_t *paNewPage64 = NULL;
3502	if (pGMR->paDesc)
3503	{
3504	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3505
3506	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3507	AssertBreak(paNewPage64);
3508
3509	uint32_t idxPage = 0;
3510	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3511	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3512	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3513	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3514	}
3515
3516	/* Free the old GMR if present. */
3517	if (pGMR->paDesc)
3518	RTMemFree(pGMR->paDesc);
3519
3520	/* Allocate the maximum amount possible (everything non-continuous) */
3521	PVMSVGAGMRDESCRIPTOR paDescs;
3522	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3523	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3524
3525	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3526	{
3527	/** @todo */
3528	AssertFailed();
3529	pGMR->numDescriptors = 0;
3530	}
3531	else
3532	{
3533	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3534	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3535	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3536
3537	if (paNewPage64)
3538	{
3539	/* Overwrite the old page array with the new page values. */
3540	if (fGCPhys64)
3541	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3542	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3543	else
3544	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3545	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3546
3547	/* Use the updated page array instead of the command data. */
3548	fGCPhys64 = true;
3549	paPages64 = paNewPage64;
3550	pCmd->numPages = cNewTotalPages;
3551	}
3552
3553	/* The first page. */
3554	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3555	* applied to paNewPage64. */
3556	RTGCPHYS GCPhys;
3557	if (fGCPhys64)
3558	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3559	else
3560	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
3561	paDescs[0].GCPhys = GCPhys;
3562	paDescs[0].numPages = 1;
3563
3564	/* Subsequent pages. */
3565	uint32_t iDescriptor = 0;
3566	for (uint32_t i = 1; i < pCmd->numPages; i++)
3567	{
3568	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
3569	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3570	else
3571	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
3572
3573	/* Continuous physical memory? */
3574	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
3575	{
3576	Assert(paDescs[iDescriptor].numPages);
3577	paDescs[iDescriptor].numPages++;
3578	LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
3579	}
3580	else
3581	{
3582	iDescriptor++;
3583	paDescs[iDescriptor].GCPhys = GCPhys;
3584	paDescs[iDescriptor].numPages = 1;
3585	LogFlow(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
3586	}
3587	}
3588
3589	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
3590	LogFlow(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
3591	pGMR->numDescriptors = iDescriptor + 1;
3592	}
3593
3594	if (paNewPage64)
3595	RTMemFree(paNewPage64);
3596
3597	# ifdef DEBUG_GMR_ACCESS
3598	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
3599	# endif
3600	break;
3601	}
3602	# endif // VBOX_WITH_VMSVGA3D
3603	case SVGA_CMD_DEFINE_SCREEN:
3604	{
3605	/* Note! The size of this command is specified by the guest and depends on capabilities. */
3606	Assert(!(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT));
3607	SVGAFifoCmdDefineScreen *pCmd;
3608	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
3609	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.structSize));
3610	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
3611	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
3612
3613	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d)\n", pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y));
3614	if (pCmd->screen.flags & SVGA_SCREEN_HAS_ROOT)
3615	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_HAS_ROOT\n"));
3616	if (pCmd->screen.flags & SVGA_SCREEN_IS_PRIMARY)
3617	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_IS_PRIMARY\n"));
3618	if (pCmd->screen.flags & SVGA_SCREEN_FULLSCREEN_HINT)
3619	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_FULLSCREEN_HINT\n"));
3620	if (pCmd->screen.flags & SVGA_SCREEN_DEACTIVATE )
3621	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_DEACTIVATE \n"));
3622	if (pCmd->screen.flags & SVGA_SCREEN_BLANKING)
3623	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_BLANKING\n"));
3624
3625	/** @todo multi monitor support and screen object capabilities. */
3626	pThis->svga.uWidth = pCmd->screen.size.width;
3627	pThis->svga.uHeight = pCmd->screen.size.height;
3628	vmsvgaChangeMode(pThis);
3629	break;
3630	}
3631
3632	case SVGA_CMD_DESTROY_SCREEN:
3633	{
3634	SVGAFifoCmdDestroyScreen *pCmd;
3635	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
3636	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
3637
3638	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
3639	break;
3640	}
3641	# ifdef VBOX_WITH_VMSVGA3D
3642	case SVGA_CMD_DEFINE_GMRFB:
3643	{
3644	SVGAFifoCmdDefineGMRFB *pCmd;
3645	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
3646	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
3647
3648	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
3649	pSVGAState->GMRFB.ptr = pCmd->ptr;
3650	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
3651	pSVGAState->GMRFB.format = pCmd->format;
3652	break;
3653	}
3654
3655	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3656	{
3657	uint32_t width, height;
3658	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
3659	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
3660	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
3661
3662	Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
3663
3664	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
3665	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pThis->svga.uBpp);
3666	AssertBreak(pCmd->destScreenId == 0);
3667
3668	if (pCmd->destRect.left < 0)
3669	pCmd->destRect.left = 0;
3670	if (pCmd->destRect.top < 0)
3671	pCmd->destRect.top = 0;
3672	if (pCmd->destRect.right < 0)
3673	pCmd->destRect.right = 0;
3674	if (pCmd->destRect.bottom < 0)
3675	pCmd->destRect.bottom = 0;
3676
3677	width = pCmd->destRect.right - pCmd->destRect.left;
3678	height = pCmd->destRect.bottom - pCmd->destRect.top;
3679
3680	if ( width == 0
3681	\|\| height == 0)
3682	break; /* Nothing to do. */
3683
3684	/* Clip to screen dimensions. */
3685	if (width > pThis->svga.uWidth)
3686	width = pThis->svga.uWidth;
3687	if (height > pThis->svga.uHeight)
3688	height = pThis->svga.uHeight;
3689
3690	/* srcOrigin */
3691	AssertBreak(pSVGAState->GMRFB.bytesPerLine != 0);
3692	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel != 0);
3693
3694	const uint32_t cScanlines = pThis->vram_size / pSVGAState->GMRFB.bytesPerLine;
3695	AssertBreak(pCmd->srcOrigin.y < (int32_t)cScanlines);
3696
3697	AssertBreak(pCmd->srcOrigin.x < (int32_t)(pSVGAState->GMRFB.bytesPerLine / ((pSVGAState->GMRFB.format.s.bitsPerPixel + 7) / 8)));
3698
3699	unsigned offsetSource = (pCmd->srcOrigin.x * pSVGAState->GMRFB.format.s.bitsPerPixel) / 8 + pSVGAState->GMRFB.bytesPerLine * pCmd->srcOrigin.y;
3700	unsigned offsetDest = (pCmd->destRect.left * RT_ALIGN(pThis->svga.uBpp, 8)) / 8 + pThis->svga.cbScanline * pCmd->destRect.top;
3701	unsigned cbCopyWidth = (width * RT_ALIGN(pThis->svga.uBpp, 8)) / 8;
3702
3703	AssertBreak(offsetDest < pThis->vram_size);
3704
3705	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM, pThis->CTX_SUFF(vram_ptr) + offsetDest, pThis->svga.cbScanline, pSVGAState->GMRFB.ptr, offsetSource, pSVGAState->GMRFB.bytesPerLine, cbCopyWidth, height);
3706	AssertRC(rc);
3707	vgaR3UpdateDisplay(pThis, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right - pCmd->destRect.left, pCmd->destRect.bottom - pCmd->destRect.top);
3708	break;
3709	}
3710
3711	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3712	{
3713	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
3714	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
3715	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
3716
3717	/* Note! This can fetch 3d render results as well!! */
3718	Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n", pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
3719	AssertFailed();
3720	break;
3721	}
3722	# endif // VBOX_WITH_VMSVGA3D
3723	case SVGA_CMD_ANNOTATION_FILL:
3724	{
3725	SVGAFifoCmdAnnotationFill *pCmd;
3726	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
3727	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
3728
3729	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
3730	pSVGAState->colorAnnotation = pCmd->color;
3731	break;
3732	}
3733
3734	case SVGA_CMD_ANNOTATION_COPY:
3735	{
3736	SVGAFifoCmdAnnotationCopy *pCmd;
3737	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
3738	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
3739
3740	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
3741	AssertFailed();
3742	break;
3743	}
3744
3745	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
3746
3747	default:
3748	# ifdef VBOX_WITH_VMSVGA3D
3749	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
3750	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
3751	{
3752	/* All 3d commands start with a common header, which defines the size of the command. */
3753	SVGA3dCmdHeader *pHdr;
3754	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
3755	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
3756	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
3757	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
3758
3759	/**
3760	* Check that the 3D command has at least a_cbMin of payload bytes after the
3761	* header. Will break out of the switch if it doesn't.
3762	*/
3763	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3764	AssertMsgBreak((a_cbMin) <= pHdr->size, ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin)))
3765	switch ((int)enmCmdId)
3766	{
3767	case SVGA_3D_CMD_SURFACE_DEFINE:
3768	{
3769	uint32_t cMipLevels;
3770	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
3771	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3772	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
3773
3774	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3775	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
3776	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
3777	# ifdef DEBUG_GMR_ACCESS
3778	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
3779	# endif
3780	break;
3781	}
3782
3783	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3784	{
3785	uint32_t cMipLevels;
3786	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
3787	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3788	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
3789
3790	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3791	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
3792	pCmd->multisampleCount, pCmd->autogenFilter,
3793	cMipLevels, (SVGA3dSize *)(pCmd + 1));
3794	break;
3795	}
3796
3797	case SVGA_3D_CMD_SURFACE_DESTROY:
3798	{
3799	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
3800	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3801	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
3802	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
3803	break;
3804	}
3805
3806	case SVGA_3D_CMD_SURFACE_COPY:
3807	{
3808	uint32_t cCopyBoxes;
3809	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
3810	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3811	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
3812
3813	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3814	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3815	break;
3816	}
3817
3818	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3819	{
3820	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
3821	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3822	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
3823
3824	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
3825	break;
3826	}
3827
3828	case SVGA_3D_CMD_SURFACE_DMA:
3829	{
3830	uint32_t cCopyBoxes;
3831	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
3832	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3833	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
3834
3835	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3836	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
3837	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3838	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
3839	break;
3840	}
3841
3842	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3843	{
3844	uint32_t cRects;
3845	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
3846	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3847	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
3848
3849	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3850	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3851	break;
3852	}
3853
3854	case SVGA_3D_CMD_CONTEXT_DEFINE:
3855	{
3856	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
3857	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3858	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
3859
3860	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
3861	break;
3862	}
3863
3864	case SVGA_3D_CMD_CONTEXT_DESTROY:
3865	{
3866	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
3867	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3868	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
3869
3870	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
3871	break;
3872	}
3873
3874	case SVGA_3D_CMD_SETTRANSFORM:
3875	{
3876	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
3877	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3878	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
3879
3880	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
3881	break;
3882	}
3883
3884	case SVGA_3D_CMD_SETZRANGE:
3885	{
3886	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
3887	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3888	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
3889
3890	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
3891	break;
3892	}
3893
3894	case SVGA_3D_CMD_SETRENDERSTATE:
3895	{
3896	uint32_t cRenderStates;
3897	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
3898	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3899	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
3900
3901	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3902	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3903	break;
3904	}
3905
3906	case SVGA_3D_CMD_SETRENDERTARGET:
3907	{
3908	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
3909	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3910	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
3911
3912	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
3913	break;
3914	}
3915
3916	case SVGA_3D_CMD_SETTEXTURESTATE:
3917	{
3918	uint32_t cTextureStates;
3919	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
3920	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3921	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
3922
3923	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3924	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3925	break;
3926	}
3927
3928	case SVGA_3D_CMD_SETMATERIAL:
3929	{
3930	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
3931	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3932	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
3933
3934	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
3935	break;
3936	}
3937
3938	case SVGA_3D_CMD_SETLIGHTDATA:
3939	{
3940	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
3941	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3942	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
3943
3944	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
3945	break;
3946	}
3947
3948	case SVGA_3D_CMD_SETLIGHTENABLED:
3949	{
3950	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
3951	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3952	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
3953
3954	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
3955	break;
3956	}
3957
3958	case SVGA_3D_CMD_SETVIEWPORT:
3959	{
3960	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
3961	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3962	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
3963
3964	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
3965	break;
3966	}
3967
3968	case SVGA_3D_CMD_SETCLIPPLANE:
3969	{
3970	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
3971	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3972	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
3973
3974	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
3975	break;
3976	}
3977
3978	case SVGA_3D_CMD_CLEAR:
3979	{
3980	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
3981	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3982	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
3983
3984	uint32_t cRects;
3985	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
3986	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
3987	break;
3988	}
3989
3990	case SVGA_3D_CMD_PRESENT:
3991	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
3992	{
3993	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
3994	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3995	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
3996	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
3997	else
3998	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
3999
4000	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4001
4002	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4003	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4004	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4005	break;
4006	}
4007
4008	case SVGA_3D_CMD_SHADER_DEFINE:
4009	{
4010	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4011	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4012	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4013
4014	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4015	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4016	break;
4017	}
4018
4019	case SVGA_3D_CMD_SHADER_DESTROY:
4020	{
4021	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4022	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4023	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4024
4025	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4026	break;
4027	}
4028
4029	case SVGA_3D_CMD_SET_SHADER:
4030	{
4031	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4032	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4033	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4034
4035	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4036	break;
4037	}
4038
4039	case SVGA_3D_CMD_SET_SHADER_CONST:
4040	{
4041	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4042	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4043	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4044
4045	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4046	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4047	break;
4048	}
4049
4050	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4051	{
4052	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4053	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4054	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4055
4056	uint32_t cVertexDivisor = (pHdr->size - sizeof(pCmd) - sizeof(SVGA3dVertexDecl) pCmd->numVertexDecls - sizeof(SVGA3dPrimitiveRange) * pCmd->numRanges);
4057	Assert(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4058	Assert(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4059	Assert(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4060
4061	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4062	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange ) (&pVertexDecl[pCmd->numVertexDecls]);
4063	SVGA3dVertexDivisor pVertexDivisor = (cVertexDivisor) ? (SVGA3dVertexDivisor )(&pNumRange[pCmd->numRanges]) : NULL;
4064
4065	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4066	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges, pNumRange, cVertexDivisor, pVertexDivisor);
4067	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4068	break;
4069	}
4070
4071	case SVGA_3D_CMD_SETSCISSORRECT:
4072	{
4073	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4074	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4075	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4076
4077	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4078	break;
4079	}
4080
4081	case SVGA_3D_CMD_BEGIN_QUERY:
4082	{
4083	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4084	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4085	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4086
4087	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4088	break;
4089	}
4090
4091	case SVGA_3D_CMD_END_QUERY:
4092	{
4093	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4094	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4095	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4096
4097	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4098	break;
4099	}
4100
4101	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4102	{
4103	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4104	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4105	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4106
4107	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4108	break;
4109	}
4110
4111	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4112	{
4113	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4114	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4115	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4116
4117	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4118	break;
4119	}
4120
4121	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4122	/* context id + surface id? */
4123	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4124	break;
4125	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4126	/* context id + surface id? */
4127	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4128	break;
4129
4130	default:
4131	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4132	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4133	break;
4134	}
4135	}
4136	else
4137	# endif // VBOX_WITH_VMSVGA3D
4138	{
4139	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4140	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4141	}
4142	}
4143
4144	/* Go to the next slot */
4145	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4146	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4147	if (offCurrentCmd >= offFifoMax)
4148	{
4149	offCurrentCmd -= offFifoMax - offFifoMin;
4150	Assert(offCurrentCmd >= offFifoMin);
4151	Assert(offCurrentCmd < offFifoMax);
4152	}
4153	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4154	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4155
4156	/*
4157	* Raise IRQ if required. Must enter the critical section here
4158	* before making final decisions here, otherwise cubebench and
4159	* others may end up waiting forever.
4160	*/
4161	if ( u32IrqStatus
4162	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4163	{
4164	int rc2 = PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
4165	AssertRC(rc2);
4166
4167	/* FIFO progress might trigger an interrupt. */
4168	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4169	{
4170	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4171	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4172	}
4173
4174	/* Unmasked IRQ pending? */
4175	if (pThis->svga.u32IrqMask & u32IrqStatus)
4176	{
4177	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4178	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4179	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4180	}
4181
4182	PDMCritSectLeave(&pThis->CritSect);
4183	}
4184	}
4185
4186	/* If really done, clear the busy flag. */
4187	if (fDone)
4188	{
4189	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4190	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4191	}
4192	}
4193
4194	/*
4195	* Free the bounce buffer. (There are no returns above!)
4196	*/
4197	RTMemFree(pbBounceBuf);
4198
4199	return VINF_SUCCESS;
4200	}
4201
4202	/**
4203	* Free the specified GMR
4204	*
4205	* @param pThis VGA device instance data.
4206	* @param idGMR GMR id
4207	*/
4208	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4209	{
4210	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4211
4212	/* Free the old descriptor if present. */
4213	PGMR pGMR = &pSVGAState->aGMR[idGMR];
4214	if ( pGMR->numDescriptors
4215	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4216	{
4217	# ifdef DEBUG_GMR_ACCESS
4218	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4219	# endif
4220
4221	Assert(pGMR->paDesc);
4222	RTMemFree(pGMR->paDesc);
4223	pGMR->paDesc = NULL;
4224	pGMR->numDescriptors = 0;
4225	pGMR->cbTotal = 0;
4226	pGMR->cMaxPages = 0;
4227	}
4228	Assert(!pGMR->cMaxPages);
4229	Assert(!pGMR->cbTotal);
4230	}
4231
4232	/**
4233	* Copy from a GMR to host memory or vice versa
4234	*
4235	* @returns VBox status code.
4236	* @param pThis VGA device instance data.
4237	* @param enmTransferType Transfer type (read/write)
4238	* @param pbDst Host destination pointer
4239	* @param cbDestPitch Destination buffer pitch
4240	* @param src GMR description
4241	* @param offSrc Source buffer offset
4242	* @param cbSrcPitch Source buffer pitch
4243	* @param cbWidth Source width in bytes
4244	* @param cHeight Source height
4245	*/
4246	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType, uint8_t *pbDst, int32_t cbDestPitch,
4247	SVGAGuestPtr src, uint32_t offSrc, int32_t cbSrcPitch, uint32_t cbWidth, uint32_t cHeight)
4248	{
4249	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4250	PGMR pGMR;
4251	int rc;
4252	PVMSVGAGMRDESCRIPTOR pDesc;
4253	unsigned offDesc = 0;
4254
4255	Log(("vmsvgaGMRTransfer: gmr=%x offset=%x pitch=%d cbWidth=%d cHeight=%d; src offset=%d src pitch=%d\n",
4256	src.gmrId, src.offset, cbDestPitch, cbWidth, cHeight, offSrc, cbSrcPitch));
4257	Assert(cbWidth && cHeight);
4258
4259	const uint32_t cbGmrScanline = cbSrcPitch > 0 ? cbSrcPitch : -cbSrcPitch;
4260
4261	uint32_t cbGmrTotal; /* The GMR size in bytes. */
4262	if (src.gmrId == SVGA_GMR_FRAMEBUFFER)
4263	{
4264	pGMR = NULL;
4265	cbGmrTotal = pThis->vram_size;
4266	}
4267	else
4268	{
4269	AssertReturn(src.gmrId < VMSVGA_MAX_GMR_IDS, VERR_INVALID_PARAMETER);
4270	pGMR = &pSVGAState->aGMR[src.gmrId];
4271	cbGmrTotal = pGMR->cbTotal;
4272	}
4273
4274	/* Check GMR parameters */
4275	AssertMsgReturn(src.offset < cbGmrTotal,
4276	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbGmrTotal=%#x\n",
4277	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, cbGmrTotal),
4278	VERR_INVALID_PARAMETER);
4279	AssertMsgReturn(offSrc < cbGmrTotal - src.offset,
4280	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbGmrTotal=%#x\n",
4281	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, cbGmrTotal),
4282	VERR_INVALID_PARAMETER);
4283	AssertMsgReturn(cbGmrScanline != 0,
4284	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbGmrTotal=%#x\n",
4285	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, cbGmrTotal),
4286	VERR_INVALID_PARAMETER);
4287	AssertMsgReturn(cbWidth <= cbGmrScanline,
4288	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbGmrTotal=%#x\n",
4289	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, cbGmrTotal),
4290	VERR_INVALID_PARAMETER);
4291
4292	offSrc += src.offset; /* Actual offset in the GMR, where the first scanline will be copied. */
4293
4294	AssertMsgReturn(cbWidth <= cbGmrTotal - offSrc,
4295	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbGmrTotal=%#x\n",
4296	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, cbGmrTotal),
4297	VERR_INVALID_PARAMETER);
4298
4299	uint32_t cbGmrLeft = cbSrcPitch > 0 ? cbGmrTotal - offSrc : offSrc + cbWidth;
4300
4301	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4302	uint32_t cbLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4303	if (cbWidth <= cbLastScanline)
4304	++cGmrScanlines;
4305
4306	if (cHeight > cGmrScanlines)
4307	cHeight = cGmrScanlines;
4308
4309	AssertMsgReturn(cHeight > 0,
4310	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbGmrTotal=%#x\n",
4311	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, cbGmrTotal),
4312	VERR_INVALID_PARAMETER);
4313
4314	/* Shortcut for the framebuffer. */
4315	if (src.gmrId == SVGA_GMR_FRAMEBUFFER)
4316	{
4317	uint8_t *pSrc = pThis->CTX_SUFF(vram_ptr) + offSrc;
4318
4319	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4320	{
4321	/* switch src & dest */
4322	uint8_t *pTemp = pbDst;
4323	int32_t cbTempPitch = cbDestPitch;
4324
4325	pbDst = pSrc;
4326	pSrc = pTemp;
4327
4328	cbDestPitch = cbSrcPitch;
4329	cbSrcPitch = cbTempPitch;
4330	}
4331
4332	if ( pThis->svga.cbScanline == (uint32_t)cbDestPitch
4333	&& cbWidth == (uint32_t)cbDestPitch
4334	&& cbSrcPitch == cbDestPitch)
4335	{
4336	memcpy(pbDst, pSrc, cbWidth * cHeight);
4337	}
4338	else
4339	{
4340	for(uint32_t i = 0; i < cHeight; i++)
4341	{
4342	memcpy(pbDst, pSrc, cbWidth);
4343
4344	pbDst += cbDestPitch;
4345	pSrc += cbSrcPitch;
4346	}
4347	}
4348	return VINF_SUCCESS;
4349	}
4350
4351	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
4352	pDesc = pGMR->paDesc;
4353
4354	for (uint32_t i = 0; i < cHeight; i++)
4355	{
4356	uint32_t cbCurrentWidth = cbWidth;
4357	uint32_t offCurrent = offSrc;
4358	uint8_t *pCurrentDest = pbDst;
4359
4360	/* Find the right descriptor */
4361	while (offDesc + pDesc->numPages * PAGE_SIZE <= offCurrent)
4362	{
4363	offDesc += pDesc->numPages * PAGE_SIZE;
4364	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
4365	pDesc++;
4366	}
4367
4368	while (cbCurrentWidth)
4369	{
4370	uint32_t cbToCopy;
4371
4372	if (offCurrent + cbCurrentWidth <= offDesc + pDesc->numPages * PAGE_SIZE)
4373	{
4374	cbToCopy = cbCurrentWidth;
4375	}
4376	else
4377	{
4378	cbToCopy = (offDesc + pDesc->numPages * PAGE_SIZE - offCurrent);
4379	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
4380	}
4381
4382	LogFlow(("vmsvgaGMRTransfer: %s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", pDesc->GCPhys + offCurrent - offDesc));
4383
4384	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
4385	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
4386	else
4387	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
4388	AssertRCBreak(rc);
4389
4390	cbCurrentWidth -= cbToCopy;
4391	offCurrent += cbToCopy;
4392	pCurrentDest += cbToCopy;
4393
4394	/* Go to the next descriptor if there's anything left. */
4395	if (cbCurrentWidth)
4396	{
4397	offDesc += pDesc->numPages * PAGE_SIZE;
4398	pDesc++;
4399	}
4400	}
4401
4402	offSrc += cbSrcPitch;
4403	pbDst += cbDestPitch;
4404	}
4405
4406	return VINF_SUCCESS;
4407	}
4408
4409	/**
4410	* Unblock the FIFO I/O thread so it can respond to a state change.
4411	*
4412	* @returns VBox status code.
4413	* @param pDevIns The VGA device instance.
4414	* @param pThread The send thread.
4415	*/
4416	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4417	{
4418	RT_NOREF(pDevIns);
4419	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
4420	Log(("vmsvgaFIFOLoopWakeUp\n"));
4421	return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
4422	}
4423
4424	/**
4425	* Enables or disables dirty page tracking for the framebuffer
4426	*
4427	* @param pThis VGA device instance data.
4428	* @param fTraces Enable/disable traces
4429	*/
4430	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
4431	{
4432	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
4433	&& !fTraces)
4434	{
4435	//Assert(pThis->svga.fTraces);
4436	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
4437	return;
4438	}
4439
4440	pThis->svga.fTraces = fTraces;
4441	if (pThis->svga.fTraces)
4442	{
4443	unsigned cbFrameBuffer = pThis->vram_size;
4444
4445	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
4446	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
4447	{
4448	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
4449	Assert(pThis->svga.cbScanline);
4450	#endif
4451	/* Hardware enabled; return real framebuffer size .*/
4452	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
4453	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
4454	}
4455
4456	if (!pThis->svga.fVRAMTracking)
4457	{
4458	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
4459	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
4460	pThis->svga.fVRAMTracking = true;
4461	}
4462	}
4463	else
4464	{
4465	if (pThis->svga.fVRAMTracking)
4466	{
4467	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
4468	vgaR3UnregisterVRAMHandler(pThis);
4469	pThis->svga.fVRAMTracking = false;
4470	}
4471	}
4472	}
4473
4474	/**
4475	* @callback_method_impl{FNPCIIOREGIONMAP}
4476	*/
4477	DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
4478	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
4479	{
4480	int rc;
4481	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4482
4483	Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
4484	if (enmType == PCI_ADDRESS_SPACE_IO)
4485	{
4486	AssertReturn(iRegion == 0, VERR_INTERNAL_ERROR);
4487	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
4488	vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr /, NULL / InStr */, "VMSVGA");
4489	if (RT_FAILURE(rc))
4490	return rc;
4491	if (pThis->fR0Enabled)
4492	{
4493	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
4494	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
4495	if (RT_FAILURE(rc))
4496	return rc;
4497	}
4498	if (pThis->fGCEnabled)
4499	{
4500	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
4501	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
4502	if (RT_FAILURE(rc))
4503	return rc;
4504	}
4505
4506	pThis->svga.BasePort = GCPhysAddress;
4507	Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
4508	}
4509	else
4510	{
4511	AssertReturn(iRegion == 2 && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
4512	if (GCPhysAddress != NIL_RTGCPHYS)
4513	{
4514	/*
4515	* Mapping the FIFO RAM.
4516	*/
4517	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
4518	rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
4519	AssertRC(rc);
4520
4521	# ifdef DEBUG_FIFO_ACCESS
4522	if (RT_SUCCESS(rc))
4523	{
4524	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress, GCPhysAddress + (pThis->svga.cbFIFO - 1),
4525	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
4526	"VMSVGA FIFO");
4527	AssertRC(rc);
4528	}
4529	# endif
4530	if (RT_SUCCESS(rc))
4531	{
4532	pThis->svga.GCPhysFIFO = GCPhysAddress;
4533	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
4534	}
4535	}
4536	else
4537	{
4538	Assert(pThis->svga.GCPhysFIFO);
4539	# ifdef DEBUG_FIFO_ACCESS
4540	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
4541	AssertRC(rc);
4542	# endif
4543	pThis->svga.GCPhysFIFO = 0;
4544	}
4545
4546	}
4547	return VINF_SUCCESS;
4548	}
4549
4550	# ifdef VBOX_WITH_VMSVGA3D
4551
4552	/**
4553	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
4554	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
4555	*
4556	* @param pThis The VGA device instance data.
4557	* @param sid Either UINT32_MAX or the ID of a specific
4558	* surface. If UINT32_MAX is used, all surfaces
4559	* are processed.
4560	*/
4561	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
4562	{
4563	vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
4564	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
4565	}
4566
4567
4568	/**
4569	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
4570	*/
4571	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4572	{
4573	/* There might be a specific context ID at the start of the
4574	arguments, if not show all contexts. */
4575	uint32_t cid = UINT32_MAX;
4576	if (pszArgs)
4577	pszArgs = RTStrStripL(pszArgs);
4578	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
4579	cid = RTStrToUInt32(pszArgs);
4580
4581	/* Verbose or terse display, we default to verbose. */
4582	bool fVerbose = true;
4583	if (RTStrIStr(pszArgs, "terse"))
4584	fVerbose = false;
4585
4586	/* The size of the ascii art (x direction, y is 3/4 of x). */
4587	uint32_t cxAscii = 80;
4588	if (RTStrIStr(pszArgs, "gigantic"))
4589	cxAscii = 300;
4590	else if (RTStrIStr(pszArgs, "huge"))
4591	cxAscii = 180;
4592	else if (RTStrIStr(pszArgs, "big"))
4593	cxAscii = 132;
4594	else if (RTStrIStr(pszArgs, "normal"))
4595	cxAscii = 80;
4596	else if (RTStrIStr(pszArgs, "medium"))
4597	cxAscii = 64;
4598	else if (RTStrIStr(pszArgs, "small"))
4599	cxAscii = 48;
4600	else if (RTStrIStr(pszArgs, "tiny"))
4601	cxAscii = 24;
4602
4603	/* Y invert the image when producing the ASCII art. */
4604	bool fInvY = false;
4605	if (RTStrIStr(pszArgs, "invy"))
4606	fInvY = true;
4607
4608	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, cid, fVerbose, cxAscii, fInvY);
4609	}
4610
4611
4612	/**
4613	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
4614	*/
4615	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4616	{
4617	/* There might be a specific surface ID at the start of the
4618	arguments, if not show all contexts. */
4619	uint32_t sid = UINT32_MAX;
4620	if (pszArgs)
4621	pszArgs = RTStrStripL(pszArgs);
4622	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
4623	sid = RTStrToUInt32(pszArgs);
4624
4625	/* Verbose or terse display, we default to verbose. */
4626	bool fVerbose = true;
4627	if (RTStrIStr(pszArgs, "terse"))
4628	fVerbose = false;
4629
4630	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
4631	}
4632
4633	# endif /* VBOX_WITH_VMSVGA3D */
4634
4635	/**
4636	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
4637	*/
4638	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4639	{
4640	RT_NOREF(pszArgs);
4641	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4642	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4643
4644	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
4645	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
4646	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
4647	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
4648	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
4649	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
4650	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
4651	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
4652	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
4653	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
4654	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
4655	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
4656	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x\n", pThis->svga.u32PitchLock);
4657	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
4658	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
4659	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
4660	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
4661	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
4662	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
4663	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
4664	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
4665	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
4666
4667	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
4668	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
4669	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
4670	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
4671
4672	# ifdef VBOX_WITH_VMSVGA3D
4673	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
4674	pHlp->pfnPrintf(pHlp, "Host windows ID: %#RX64\n", pThis->svga.u64HostWindowId);
4675	if (pThis->svga.u64HostWindowId != 0)
4676	vmsvga3dInfoHostWindow(pHlp, pThis->svga.u64HostWindowId);
4677	# endif
4678	}
4679
4680
4681	/**
4682	* @copydoc FNSSMDEVLOADEXEC
4683	*/
4684	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4685	{
4686	RT_NOREF(uVersion, uPass);
4687	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4688	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4689	int rc;
4690
4691	/* Load our part of the VGAState */
4692	rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
4693	AssertRCReturn(rc, rc);
4694
4695	/* Load the VGA framebuffer. */
4696	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
4697	uint32_t cbVgaFramebuffer = _32K;
4698	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
4699	{
4700	rc = SSMR3GetU32(pSSM, &cbVgaFramebuffer);
4701	AssertRCReturn(rc, rc);
4702	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
4703	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
4704	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
4705	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
4706	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
4707	}
4708	rc = SSMR3GetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
4709	AssertRCReturn(rc, rc);
4710	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
4711	SSMR3Skip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
4712	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
4713	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
4714
4715	/* Load the VMSVGA state. */
4716	rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
4717	AssertRCReturn(rc, rc);
4718
4719	/* Load the active cursor bitmaps. */
4720	if (pSVGAState->Cursor.fActive)
4721	{
4722	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
4723	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
4724
4725	rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
4726	AssertRCReturn(rc, rc);
4727	}
4728
4729	/* Load the GMR state */
4730	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4731	{
4732	PGMR pGMR = &pSVGAState->aGMR[i];
4733
4734	rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
4735	AssertRCReturn(rc, rc);
4736
4737	if (pGMR->numDescriptors)
4738	{
4739	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
4740	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
4741	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
4742
4743	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
4744	{
4745	rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
4746	AssertRCReturn(rc, rc);
4747	}
4748	}
4749	}
4750
4751	# ifdef VBOX_WITH_VMSVGA3D
4752	if (pThis->svga.f3DEnabled)
4753	{
4754	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
4755	vmsvga3dPowerOn(pThis);
4756	# endif
4757
4758	VMSVGA_STATE_LOAD LoadState;
4759	LoadState.pSSM = pSSM;
4760	LoadState.uVersion = uVersion;
4761	LoadState.uPass = uPass;
4762	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
4763	AssertLogRelRCReturn(rc, rc);
4764	}
4765	# endif
4766
4767	return VINF_SUCCESS;
4768	}
4769
4770	/**
4771	* Reinit the video mode after the state has been loaded.
4772	*/
4773	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
4774	{
4775	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4776	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4777
4778	pThis->last_bpp = VMSVGA_VAL_UNINITIALIZED; /* force mode reset */
4779	vmsvgaChangeMode(pThis);
4780
4781	/* Set the active cursor. */
4782	if (pSVGAState->Cursor.fActive)
4783	{
4784	int rc;
4785
4786	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
4787	true,
4788	true,
4789	pSVGAState->Cursor.xHotspot,
4790	pSVGAState->Cursor.yHotspot,
4791	pSVGAState->Cursor.width,
4792	pSVGAState->Cursor.height,
4793	pSVGAState->Cursor.pData);
4794	AssertRC(rc);
4795	}
4796	return VINF_SUCCESS;
4797	}
4798
4799	/**
4800	* @copydoc FNSSMDEVSAVEEXEC
4801	*/
4802	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4803	{
4804	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4805	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4806	int rc;
4807
4808	/* Save our part of the VGAState */
4809	rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
4810	AssertLogRelRCReturn(rc, rc);
4811
4812	/* Save the framebuffer backup. */
4813	rc = SSMR3PutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
4814	rc = SSMR3PutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
4815	AssertLogRelRCReturn(rc, rc);
4816
4817	/* Save the VMSVGA state. */
4818	rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
4819	AssertLogRelRCReturn(rc, rc);
4820
4821	/* Save the active cursor bitmaps. */
4822	if (pSVGAState->Cursor.fActive)
4823	{
4824	rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
4825	AssertLogRelRCReturn(rc, rc);
4826	}
4827
4828	/* Save the GMR state */
4829	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4830	{
4831	rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i], sizeof(pSVGAState->aGMR[i]), 0, g_aGMRFields, NULL);
4832	AssertLogRelRCReturn(rc, rc);
4833
4834	for (uint32_t j = 0; j < pSVGAState->aGMR[i].numDescriptors; j++)
4835	{
4836	rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i].paDesc[j], sizeof(pSVGAState->aGMR[i].paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
4837	AssertLogRelRCReturn(rc, rc);
4838	}
4839	}
4840
4841	# ifdef VBOX_WITH_VMSVGA3D
4842	/*
4843	* Must save the 3d state in the FIFO thread.
4844	*/
4845	if (pThis->svga.f3DEnabled)
4846	{
4847	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
4848	AssertLogRelRCReturn(rc, rc);
4849	}
4850	# endif
4851	return VINF_SUCCESS;
4852	}
4853
4854	/**
4855	* Resets the SVGA hardware state
4856	*
4857	* @returns VBox status code.
4858	* @param pDevIns The device instance.
4859	*/
4860	int vmsvgaReset(PPDMDEVINS pDevIns)
4861	{
4862	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4863	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4864
4865	/* Reset before init? */
4866	if (!pSVGAState)
4867	return VINF_SUCCESS;
4868
4869	Log(("vmsvgaReset\n"));
4870
4871
4872	/* Reset the FIFO processing as well as the 3d state (if we have one). */
4873	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
4874	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
4875
4876	/* Reset other stuff. */
4877	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4878	RT_ZERO(pThis->svga.au32ScratchRegion);
4879	RT_ZERO(*pThis->svga.pSvgaR3State);
4880	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
4881
4882	/* Register caps. */
4883	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
4884	# ifdef VBOX_WITH_VMSVGA3D
4885	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
4886	# endif
4887
4888	/* Setup FIFO capabilities. */
4889	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
4890
4891	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
4892	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
4893
4894	/* VRAM tracking is enabled by default during bootup. */
4895	pThis->svga.fVRAMTracking = true;
4896	pThis->svga.fEnabled = false;
4897
4898	/* Invalidate current settings. */
4899	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
4900	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
4901	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
4902	pThis->svga.cbScanline = 0;
4903
4904	return rc;
4905	}
4906
4907	/**
4908	* Cleans up the SVGA hardware state
4909	*
4910	* @returns VBox status code.
4911	* @param pDevIns The device instance.
4912	*/
4913	int vmsvgaDestruct(PPDMDEVINS pDevIns)
4914	{
4915	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4916
4917	/*
4918	* Ask the FIFO thread to terminate the 3d state and then terminate it.
4919	*/
4920	if (pThis->svga.pFIFOIOThread)
4921	{
4922	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
4923	AssertLogRelRC(rc);
4924
4925	rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
4926	AssertLogRelRC(rc);
4927	pThis->svga.pFIFOIOThread = NULL;
4928	}
4929
4930	/*
4931	* Destroy the special SVGA state.
4932	*/
4933	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4934	if (pSVGAState)
4935	{
4936	# ifndef VMSVGA_USE_EMT_HALT_CODE
4937	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
4938	{
4939	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
4940	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
4941	}
4942	# endif
4943	if (pSVGAState->Cursor.fActive)
4944	RTMemFree(pSVGAState->Cursor.pData);
4945
4946	for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4947	if (pSVGAState->aGMR[i].paDesc)
4948	RTMemFree(pSVGAState->aGMR[i].paDesc);
4949
4950	RTMemFree(pSVGAState);
4951	pThis->svga.pSvgaR3State = NULL;
4952	}
4953
4954	/*
4955	* Free our resources residing in the VGA state.
4956	*/
4957	if (pThis->svga.pbVgaFrameBufferR3)
4958	{
4959	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
4960	pThis->svga.pbVgaFrameBufferR3 = NULL;
4961	}
4962	if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
4963	{
4964	RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
4965	pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
4966	}
4967	if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
4968	{
4969	SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
4970	pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
4971	}
4972
4973	return VINF_SUCCESS;
4974	}
4975
4976	/**
4977	* Initialize the SVGA hardware state
4978	*
4979	* @returns VBox status code.
4980	* @param pDevIns The device instance.
4981	*/
4982	int vmsvgaInit(PPDMDEVINS pDevIns)
4983	{
4984	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4985	PVMSVGAR3STATE pSVGAState;
4986	PVM pVM = PDMDevHlpGetVM(pDevIns);
4987	int rc;
4988
4989	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4990	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
4991
4992	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
4993	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
4994	pSVGAState = pThis->svga.pSvgaR3State;
4995
4996	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
4997	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
4998	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
4999
5000	/* Create event semaphore. */
5001	pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
5002
5003	rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
5004	if (RT_FAILURE(rc))
5005	{
5006	Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
5007	return rc;
5008	}
5009
5010	/* Create event semaphore. */
5011	rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
5012	if (RT_FAILURE(rc))
5013	{
5014	Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
5015	return rc;
5016	}
5017
5018	# ifndef VMSVGA_USE_EMT_HALT_CODE
5019	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5020	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5021	AssertRCReturn(rc, rc);
5022	# endif
5023
5024	/* Register caps. */
5025	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5026	# ifdef VBOX_WITH_VMSVGA3D
5027	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5028	# endif
5029
5030	/* Setup FIFO capabilities. */
5031	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5032
5033	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5034	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5035
5036	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
5037	# ifdef VBOX_WITH_VMSVGA3D
5038	if (pThis->svga.f3DEnabled)
5039	{
5040	rc = vmsvga3dInit(pThis);
5041	if (RT_FAILURE(rc))
5042	{
5043	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
5044	pThis->svga.f3DEnabled = false;
5045	}
5046	}
5047	# endif
5048	/* VRAM tracking is enabled by default during bootup. */
5049	pThis->svga.fVRAMTracking = true;
5050
5051	/* Invalidate current settings. */
5052	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5053	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5054	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5055	pThis->svga.cbScanline = 0;
5056
5057	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
5058	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
5059	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
5060	{
5061	pThis->svga.u32MaxWidth -= 256;
5062	pThis->svga.u32MaxHeight -= 256;
5063	}
5064	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
5065
5066	# ifdef DEBUG_GMR_ACCESS
5067	/* Register the GMR access handler type. */
5068	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
5069	vmsvgaR3GMRAccessHandler,
5070	NULL, NULL, NULL,
5071	NULL, NULL, NULL,
5072	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
5073	AssertRCReturn(rc, rc);
5074	# endif
5075	# ifdef DEBUG_FIFO_ACCESS
5076	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_ALL,
5077	vmsvgaR3FIFOAccessHandler,
5078	NULL, NULL, NULL,
5079	NULL, NULL, NULL,
5080	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
5081	AssertRCReturn(rc, rc);
5082	#endif
5083
5084	/* Create the async IO thread. */
5085	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
5086	RTTHREADTYPE_IO, "VMSVGA FIFO");
5087	if (RT_FAILURE(rc))
5088	{
5089	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
5090	return rc;
5091	}
5092
5093	/*
5094	* Statistics.
5095	*/
5096	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dActivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dActivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_ACTIVATE_SURFACE");
5097	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dBeginQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dBeginQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_BEGIN_QUERY");
5098	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dClear, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dClear", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CLEAR");
5099	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DEFINE");
5100	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DESTROY");
5101	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDeactivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDeactivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DEACTIVATE_SURFACE");
5102	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitives, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDrawPrimitives", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DRAW_PRIMITIVES");
5103	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitivesProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dDrawPrimitivesProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
5104	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dEndQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dEndQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_END_QUERY");
5105	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dGenerateMipmaps, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dGenerateMipmaps", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_GENERATE_MIPMAPS");
5106	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresent, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresent", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT");
5107	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresentReadBack, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresentReadBack", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT_READBACK");
5108	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dPresentProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dPresentProfBoth", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
5109	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetClipPlane, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetClipPlane", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETCLIPPLANE");
5110	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightData, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightData", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTDATA");
5111	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightEnable, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightEnable", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTENABLE");
5112	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetMaterial, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetMaterial", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETMATERIAL");
5113	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERSTATE");
5114	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderTarget, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderTarget", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERTARGET");
5115	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetScissorRect, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetScissorRect", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETSCISSORRECT");
5116	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShader, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShader", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER");
5117	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShaderConst, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShaderConst", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER_CONST");
5118	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTextureState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTextureState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTEXTURESTATE");
5119	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTransform, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTransform", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTRANSFORM");
5120	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetViewPort, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetViewPort", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETVIEWPORT");
5121	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetZRange, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetZRange", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETZRANGE");
5122	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DEFINE");
5123	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DESTROY");
5124	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceCopy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_COPY");
5125	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE");
5126	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefineV2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefineV2", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE_V2");
5127	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DESTROY");
5128	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDma, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDma", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DMA");
5129	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDmaProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dSurfaceDmaProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
5130	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceScreen", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_SCREEN");
5131	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceStretchBlt, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceStretchBlt", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_STRETCHBLT");
5132	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dWaitForQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dWaitForQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_WAIT_FOR_QUERY");
5133	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationCopy", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_COPY");
5134	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationFill, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationFill", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_FILL");
5135	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitGmrFbToScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitGmrFbToScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
5136	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitScreentoGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitScreentoGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
5137	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineAlphaCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineAlphaCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_ALPHA_CURSOR");
5138	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_CURSOR");
5139	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMR2");
5140	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Free, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Free", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
5141	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
5142	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMRFB");
5143	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_SCREEN");
5144	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDestroyScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DestroyScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DESTROY_SCREEN");
5145	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdEscape, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Escape", STAMUNIT_OCCURENCES, "SVGA_CMD_ESCAPE");
5146	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdFence, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Fence", STAMUNIT_OCCURENCES, "SVGA_CMD_FENCE");
5147	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdInvalidCmd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/InvalidCmd", STAMUNIT_OCCURENCES, "SVGA_CMD_INVALID_CMD");
5148	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_REMAP_GMR2.");
5149	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
5150	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdate, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Update", STAMUNIT_OCCURENCES, "SVGA_CMD_UPATE");
5151	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdateVerbose, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/UpdateVerbose", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE_VERBOSE");
5152
5153	STAM_REL_REG(pVM, &pSVGAState->StatR3RegConfigDoneWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE writes");
5154	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_DESCRIPTOR writes");
5155	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Errors", STAMUNIT_OCCURENCES, "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
5156	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrFree, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Free", STAMUNIT_OCCURENCES, "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
5157	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL writes.");
5158	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY writes.");
5159	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX writes.");
5160	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH writes.");
5161	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT writes.");
5162	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID writes.");
5163	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
5164	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X writes.");
5165	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y writes.");
5166	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH writes.");
5167	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE writes.");
5168	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID writes.");
5169	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID writes.");
5170	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT writes.");
5171	STAM_REL_REG(pVM, &pThis->svga.StatRegIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ID writes.");
5172	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskWrite", STAMUNIT_OCCURENCES, "SVGA_REG_IRQMASK writes.");
5173	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS writes.");
5174	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
5175	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteWrite", STAMUNIT_OCCURENCES, "SVGA_PALETTE_XXXX writes.");
5176	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK writes.");
5177	STAM_REL_REG(pVM, &pThis->svga.StatRegPseudoColorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PseudoColorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR writes.");
5178	STAM_REL_REG(pVM, &pThis->svga.StatRegReadOnlyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ReadOnlyWrite", STAMUNIT_OCCURENCES, "Read-only SVGA_REG_XXXX writes.");
5179	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_XXXX writes.");
5180	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC writes.");
5181	STAM_REL_REG(pVM, &pThis->svga.StatRegTopWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TOP writes.");
5182	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES writes.");
5183	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownWrite", STAMUNIT_OCCURENCES, "Writes to unknown register.");
5184	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH writes.");
5185
5186	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL reads.");
5187	STAM_REL_REG(pVM, &pThis->svga.StatRegBlueMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BlueMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_BLUE_MASK reads.");
5188	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyRead", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY reads.");
5189	STAM_REL_REG(pVM, &pThis->svga.StatRegBytesPerLineRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BytesPerLineRead", STAMUNIT_OCCURENCES, "SVGA_REG_BYTES_PER_LINE reads.");
5190	STAM_REL_REG(pVM, &pThis->svga.StatRegCapabilitesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CapabilitesRead", STAMUNIT_OCCURENCES, "SVGA_REG_CAPABILITIES reads.");
5191	STAM_REL_REG(pVM, &pThis->svga.StatRegConfigDoneRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneRead", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE reads.");
5192	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxRead", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX reads.");
5193	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH reads.");
5194	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT reads.");
5195	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID reads.");
5196	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
5197	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X reads.");
5198	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y reads.");
5199	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH reads.");
5200	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableRead", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE reads.");
5201	STAM_REL_REG(pVM, &pThis->svga.StatRegFbOffsetRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbOffsetRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_OFFSET reads.");
5202	STAM_REL_REG(pVM, &pThis->svga.StatRegFbSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_SIZE reads.");
5203	STAM_REL_REG(pVM, &pThis->svga.StatRegFbStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_START reads.");
5204	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID reads.");
5205	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxDescriptorLengthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxDescriptorLengthRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
5206	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxIdsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxIdsRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_IDS reads.");
5207	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrsMaxPagesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrsMaxPagesRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMRS_MAX_PAGES reads.");
5208	STAM_REL_REG(pVM, &pThis->svga.StatRegGreenMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GreenMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_GREEN_MASK reads.");
5209	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID reads.");
5210	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT reads.");
5211	STAM_REL_REG(pVM, &pThis->svga.StatRegHostBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HostBitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
5212	STAM_REL_REG(pVM, &pThis->svga.StatRegIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdRead", STAMUNIT_OCCURENCES, "SVGA_REG_ID reads.");
5213	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_IRQ_MASK reads.");
5214	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_HEIGHT reads.");
5215	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_WIDTH reads.");
5216	STAM_REL_REG(pVM, &pThis->svga.StatRegMemorySizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemorySizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEMORY_SIZE reads.");
5217	STAM_REL_REG(pVM, &pThis->svga.StatRegMemRegsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemRegsRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_REGS reads.");
5218	STAM_REL_REG(pVM, &pThis->svga.StatRegMemSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_SIZE reads.");
5219	STAM_REL_REG(pVM, &pThis->svga.StatRegMemStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_START reads.");
5220	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS reads.");
5221	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
5222	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteRead", STAMUNIT_OCCURENCES, "SVGA_REG_PLAETTE_XXXX reads.");
5223	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockRead", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK reads.");
5224	STAM_REL_REG(pVM, &pThis->svga.StatRegPsuedoColorRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PsuedoColorRead", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR reads.");
5225	STAM_REL_REG(pVM, &pThis->svga.StatRegRedMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/RedMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_RED_MASK reads.");
5226	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH reads.");
5227	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_SIZE reads.");
5228	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncRead", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC reads.");
5229	STAM_REL_REG(pVM, &pThis->svga.StatRegTopRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopRead", STAMUNIT_OCCURENCES, "SVGA_REG_TOP reads.");
5230	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesRead", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES reads.");
5231	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownRead", STAMUNIT_OCCURENCES, "SVGA_REG_UNKNOWN reads.");
5232	STAM_REL_REG(pVM, &pThis->svga.StatRegVramSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/VramSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_VRAM_SIZE reads.");
5233	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH reads.");
5234	STAM_REL_REG(pVM, &pThis->svga.StatRegWriteOnlyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WriteOnlyRead", STAMUNIT_OCCURENCES, "Write-only SVGA_REG_XXXX reads.");
5235
5236	STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
5237	STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
5238	STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
5239	STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
5240	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
5241	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
5242	STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
5243
5244	/*
5245	* Info handlers.
5246	*/
5247	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
5248	# ifdef VBOX_WITH_VMSVGA3D
5249	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
5250	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
5251	"VMSVGA 3d surface details. "
5252	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
5253	vmsvgaR3Info3dSurface);
5254	# endif
5255
5256	return VINF_SUCCESS;
5257	}
5258
5259	# ifdef VBOX_WITH_VMSVGA3D
5260	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5261	static const char * const g_apszVmSvgaDevCapNames[] =
5262	{
5263	"x3D", /* = 0 */
5264	"xMAX_LIGHTS",
5265	"xMAX_TEXTURES",
5266	"xMAX_CLIP_PLANES",
5267	"xVERTEX_SHADER_VERSION",
5268	"xVERTEX_SHADER",
5269	"xFRAGMENT_SHADER_VERSION",
5270	"xFRAGMENT_SHADER",
5271	"xMAX_RENDER_TARGETS",
5272	"xS23E8_TEXTURES",
5273	"xS10E5_TEXTURES",
5274	"xMAX_FIXED_VERTEXBLEND",
5275	"xD16_BUFFER_FORMAT",
5276	"xD24S8_BUFFER_FORMAT",
5277	"xD24X8_BUFFER_FORMAT",
5278	"xQUERY_TYPES",
5279	"xTEXTURE_GRADIENT_SAMPLING",
5280	"rMAX_POINT_SIZE",
5281	"xMAX_SHADER_TEXTURES",
5282	"xMAX_TEXTURE_WIDTH",
5283	"xMAX_TEXTURE_HEIGHT",
5284	"xMAX_VOLUME_EXTENT",
5285	"xMAX_TEXTURE_REPEAT",
5286	"xMAX_TEXTURE_ASPECT_RATIO",
5287	"xMAX_TEXTURE_ANISOTROPY",
5288	"xMAX_PRIMITIVE_COUNT",
5289	"xMAX_VERTEX_INDEX",
5290	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5291	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5292	"xMAX_VERTEX_SHADER_TEMPS",
5293	"xMAX_FRAGMENT_SHADER_TEMPS",
5294	"xTEXTURE_OPS",
5295	"xSURFACEFMT_X8R8G8B8",
5296	"xSURFACEFMT_A8R8G8B8",
5297	"xSURFACEFMT_A2R10G10B10",
5298	"xSURFACEFMT_X1R5G5B5",
5299	"xSURFACEFMT_A1R5G5B5",
5300	"xSURFACEFMT_A4R4G4B4",
5301	"xSURFACEFMT_R5G6B5",
5302	"xSURFACEFMT_LUMINANCE16",
5303	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5304	"xSURFACEFMT_ALPHA8",
5305	"xSURFACEFMT_LUMINANCE8",
5306	"xSURFACEFMT_Z_D16",
5307	"xSURFACEFMT_Z_D24S8",
5308	"xSURFACEFMT_Z_D24X8",
5309	"xSURFACEFMT_DXT1",
5310	"xSURFACEFMT_DXT2",
5311	"xSURFACEFMT_DXT3",
5312	"xSURFACEFMT_DXT4",
5313	"xSURFACEFMT_DXT5",
5314	"xSURFACEFMT_BUMPX8L8V8U8",
5315	"xSURFACEFMT_A2W10V10U10",
5316	"xSURFACEFMT_BUMPU8V8",
5317	"xSURFACEFMT_Q8W8V8U8",
5318	"xSURFACEFMT_CxV8U8",
5319	"xSURFACEFMT_R_S10E5",
5320	"xSURFACEFMT_R_S23E8",
5321	"xSURFACEFMT_RG_S10E5",
5322	"xSURFACEFMT_RG_S23E8",
5323	"xSURFACEFMT_ARGB_S10E5",
5324	"xSURFACEFMT_ARGB_S23E8",
5325	"xMISSING62",
5326	"xMAX_VERTEX_SHADER_TEXTURES",
5327	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
5328	"xSURFACEFMT_V16U16",
5329	"xSURFACEFMT_G16R16",
5330	"xSURFACEFMT_A16B16G16R16",
5331	"xSURFACEFMT_UYVY",
5332	"xSURFACEFMT_YUY2",
5333	"xMULTISAMPLE_NONMASKABLESAMPLES",
5334	"xMULTISAMPLE_MASKABLESAMPLES",
5335	"xALPHATOCOVERAGE",
5336	"xSUPERSAMPLE",
5337	"xAUTOGENMIPMAPS",
5338	"xSURFACEFMT_NV12",
5339	"xSURFACEFMT_AYUV",
5340	"xMAX_CONTEXT_IDS",
5341	"xMAX_SURFACE_IDS",
5342	"xSURFACEFMT_Z_DF16",
5343	"xSURFACEFMT_Z_DF24",
5344	"xSURFACEFMT_Z_D24S8_INT",
5345	"xSURFACEFMT_BC4_UNORM",
5346	"xSURFACEFMT_BC5_UNORM", /* 83 */
5347	};
5348	# endif
5349
5350
5351	/**
5352	* Power On notification.
5353	*
5354	* @returns VBox status code.
5355	* @param pDevIns The device instance data.
5356	*
5357	* @remarks Caller enters the device critical section.
5358	*/
5359	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
5360	{
5361	# ifdef VBOX_WITH_VMSVGA3D
5362	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5363	if (pThis->svga.f3DEnabled)
5364	{
5365	int rc = vmsvga3dPowerOn(pThis);
5366
5367	if (RT_SUCCESS(rc))
5368	{
5369	bool fSavedBuffering = RTLogRelSetBuffering(true);
5370	SVGA3dCapsRecord *pCaps;
5371	SVGA3dCapPair *pData;
5372	uint32_t idxCap = 0;
5373
5374	/* 3d hardware version; latest and greatest */
5375	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5376	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5377
5378	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
5379	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5380	pData = (SVGA3dCapPair *)&pCaps->data;
5381
5382	/* Fill out all 3d capabilities. */
5383	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
5384	{
5385	uint32_t val = 0;
5386
5387	rc = vmsvga3dQueryCaps(pThis, i, &val);
5388	if (RT_SUCCESS(rc))
5389	{
5390	pData[idxCap][0] = i;
5391	pData[idxCap][1] = val;
5392	idxCap++;
5393	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
5394	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
5395	else
5396	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
5397	&g_apszVmSvgaDevCapNames[i][1]));
5398	}
5399	else
5400	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
5401	}
5402	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
5403	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
5404
5405	/* Mark end of record array. */
5406	pCaps->header.length = 0;
5407
5408	RTLogRelSetBuffering(fSavedBuffering);
5409	}
5410	}
5411	# else /* !VBOX_WITH_VMSVGA3D */
5412	RT_NOREF(pDevIns);
5413	# endif /* !VBOX_WITH_VMSVGA3D */
5414	}
5415
5416	#endif /* IN_RING3 */
5417

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 69136

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