VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 65101

Last change on this file since 65101 was 65101, checked in by vboxsync, 8 years ago

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1/* $Id: DevVGA-SVGA.cpp 65101 2017-01-04 12:07:43Z vboxsync $ */
2/** @file
3 * VMWare SVGA device.
4 *
5 * Logging levels guidelines for this and related files:
6 * - Log() for normal bits.
7 * - LogFlow() for more info.
8 * - Log2 for hex dump of cursor data.
9 * - Log3 for hex dump of shader code.
10 * - Log4 for hex dumps of 3D data.
11 */
12
13/*
14 * Copyright (C) 2013-2016 Oracle Corporation
15 *
16 * This file is part of VirtualBox Open Source Edition (OSE), as
17 * available from http://www.virtualbox.org. This file is free software;
18 * you can redistribute it and/or modify it under the terms of the GNU
19 * General Public License (GPL) as published by the Free Software
20 * Foundation, in version 2 as it comes in the "COPYING" file of the
21 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23 */
24
25
26/*********************************************************************************************************************************
27* Header Files *
28*********************************************************************************************************************************/
29#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
30#define VMSVGA_USE_EMT_HALT_CODE
31#include <VBox/vmm/pdmdev.h>
32#include <VBox/version.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/vmm/pgm.h>
36#ifdef VMSVGA_USE_EMT_HALT_CODE
37# include <VBox/vmm/vmapi.h>
38# include <VBox/vmm/vmcpuset.h>
39#endif
40#include <VBox/sup.h>
41
42#include <iprt/assert.h>
43#include <iprt/semaphore.h>
44#include <iprt/uuid.h>
45#ifdef IN_RING3
46# include <iprt/ctype.h>
47# include <iprt/mem.h>
48#endif
49
50#include <VBox/VMMDev.h>
51#include <VBox/VBoxVideo.h>
52#include <VBox/bioslogo.h>
53
54/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
55#include "DevVGA.h"
56
57#include "DevVGA-SVGA.h"
58#include "vmsvga/svga_reg.h"
59#include "vmsvga/svga_escape.h"
60#include "vmsvga/svga_overlay.h"
61#include "vmsvga/svga3d_reg.h"
62#include "vmsvga/svga3d_caps.h"
63#ifdef VBOX_WITH_VMSVGA3D
64# include "DevVGA-SVGA3d.h"
65# ifdef RT_OS_DARWIN
66# include "DevVGA-SVGA3d-cocoa.h"
67# endif
68#endif
69
70
71/*********************************************************************************************************************************
72* Defined Constants And Macros *
73*********************************************************************************************************************************/
74/**
75 * Macro for checking if a fixed FIFO register is valid according to the
76 * current FIFO configuration.
77 *
78 * @returns true / false.
79 * @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
80 * @param a_offFifoMin A valid SVGA_FIFO_MIN value.
81 */
82#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
83
84
85/*********************************************************************************************************************************
86* Structures and Typedefs *
87*********************************************************************************************************************************/
88/**
89 * 64-bit GMR descriptor.
90 */
91typedef struct
92{
93 RTGCPHYS GCPhys;
94 uint64_t numPages;
95} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
96
97/**
98 * GMR slot
99 */
100typedef struct
101{
102 uint32_t cMaxPages;
103 uint32_t cbTotal;
104 uint32_t numDescriptors;
105 PVMSVGAGMRDESCRIPTOR paDesc;
106} GMR, *PGMR;
107
108#ifdef IN_RING3
109/**
110 * Internal SVGA ring-3 only state.
111 */
112typedef struct VMSVGAR3STATE
113{
114 GMR aGMR[VMSVGA_MAX_GMR_IDS];
115 struct
116 {
117 SVGAGuestPtr ptr;
118 uint32_t bytesPerLine;
119 SVGAGMRImageFormat format;
120 } GMRFB;
121 struct
122 {
123 bool fActive;
124 uint32_t xHotspot;
125 uint32_t yHotspot;
126 uint32_t width;
127 uint32_t height;
128 uint32_t cbData;
129 void *pData;
130 } Cursor;
131 SVGAColorBGRX colorAnnotation;
132
133# ifdef VMSVGA_USE_EMT_HALT_CODE
134 /** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
135 uint32_t volatile cBusyDelayedEmts;
136 /** Set of EMTs that are */
137 VMCPUSET BusyDelayedEmts;
138# else
139 /** Number of EMTs waiting on hBusyDelayedEmts. */
140 uint32_t volatile cBusyDelayedEmts;
141 /** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
142 * busy (ugly). */
143 RTSEMEVENTMULTI hBusyDelayedEmts;
144# endif
145 /** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
146 STAMPROFILE StatBusyDelayEmts;
147
148 STAMPROFILE StatR3CmdPresent;
149 STAMPROFILE StatR3CmdDrawPrimitive;
150 STAMPROFILE StatR3CmdSurfaceDMA;
151
152 STAMCOUNTER StatFifoCommands;
153 STAMCOUNTER StatFifoErrors;
154 STAMCOUNTER StatFifoUnkCmds;
155 STAMCOUNTER StatFifoTodoTimeout;
156 STAMCOUNTER StatFifoTodoWoken;
157 STAMPROFILE StatFifoStalls;
158
159} VMSVGAR3STATE, *PVMSVGAR3STATE;
160#endif /* IN_RING3 */
161
162
163/*********************************************************************************************************************************
164* Internal Functions *
165*********************************************************************************************************************************/
166#ifdef IN_RING3
167# ifdef DEBUG_FIFO_ACCESS
168static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
169# endif
170# ifdef DEBUG_GMR_ACCESS
171static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
172# endif
173#endif
174
175
176/*********************************************************************************************************************************
177* Global Variables *
178*********************************************************************************************************************************/
179#ifdef IN_RING3
180
181/**
182 * SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
183 */
184static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
185{
186 SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
187 SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
188 SSMFIELD_ENTRY_TERM()
189};
190
191/**
192 * SSM descriptor table for the GMR structure.
193 */
194static SSMFIELD const g_aGMRFields[] =
195{
196 SSMFIELD_ENTRY( GMR, cMaxPages),
197 SSMFIELD_ENTRY( GMR, cbTotal),
198 SSMFIELD_ENTRY( GMR, numDescriptors),
199 SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
200 SSMFIELD_ENTRY_TERM()
201};
202
203/**
204 * SSM descriptor table for the VMSVGAR3STATE structure.
205 */
206static SSMFIELD const g_aVMSVGAR3STATEFields[] =
207{
208 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, aGMR),
209 SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
210 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
211 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
212 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
213 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
214 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
215 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
216 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
217 SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
218 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
219#ifdef VMSVGA_USE_EMT_HALT_CODE
220 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
221#else
222 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
223#endif
224 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
225 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdPresent),
226 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDrawPrimitive),
227 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdSurfaceDMA),
228 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
229 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
230 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
231 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
232 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
233 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
234 SSMFIELD_ENTRY_TERM()
235};
236
237/**
238 * SSM descriptor table for the VGAState.svga structure.
239 */
240static SSMFIELD const g_aVGAStateSVGAFields[] =
241{
242 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u64HostWindowId),
243 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
244 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
245 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
246 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
247 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFrameBufferBackup),
248 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
249 SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
250 SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
251 SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
252 SSMFIELD_ENTRY( VMSVGAState, fEnabled),
253 SSMFIELD_ENTRY( VMSVGAState, fConfigured),
254 SSMFIELD_ENTRY( VMSVGAState, fBusy),
255 SSMFIELD_ENTRY( VMSVGAState, fTraces),
256 SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
257 SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
258 SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
259 SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
260 SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
261 SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
262 SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
263 SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
264 SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
265 SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
266 SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
267 SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
268 SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
269 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
270 SSMFIELD_ENTRY( VMSVGAState, uWidth),
271 SSMFIELD_ENTRY( VMSVGAState, uHeight),
272 SSMFIELD_ENTRY( VMSVGAState, uBpp),
273 SSMFIELD_ENTRY( VMSVGAState, cbScanline),
274 SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
275 SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
276 SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
277 SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
278 SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
279 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
280 SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
281 SSMFIELD_ENTRY_TERM()
282};
283
284static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
285
286#endif /* IN_RING3 */
287
288#ifdef LOG_ENABLED
289
290/**
291 * Index register string name lookup
292 *
293 * @returns Index register string or "UNKNOWN"
294 * @param pThis VMSVGA State
295 */
296static const char *vmsvgaIndexToString(PVGASTATE pThis)
297{
298 switch (pThis->svga.u32IndexReg)
299 {
300 case SVGA_REG_ID:
301 return "SVGA_REG_ID";
302 case SVGA_REG_ENABLE:
303 return "SVGA_REG_ENABLE";
304 case SVGA_REG_WIDTH:
305 return "SVGA_REG_WIDTH";
306 case SVGA_REG_HEIGHT:
307 return "SVGA_REG_HEIGHT";
308 case SVGA_REG_MAX_WIDTH:
309 return "SVGA_REG_MAX_WIDTH";
310 case SVGA_REG_MAX_HEIGHT:
311 return "SVGA_REG_MAX_HEIGHT";
312 case SVGA_REG_DEPTH:
313 return "SVGA_REG_DEPTH";
314 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
315 return "SVGA_REG_BITS_PER_PIXEL";
316 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
317 return "SVGA_REG_HOST_BITS_PER_PIXEL";
318 case SVGA_REG_PSEUDOCOLOR:
319 return "SVGA_REG_PSEUDOCOLOR";
320 case SVGA_REG_RED_MASK:
321 return "SVGA_REG_RED_MASK";
322 case SVGA_REG_GREEN_MASK:
323 return "SVGA_REG_GREEN_MASK";
324 case SVGA_REG_BLUE_MASK:
325 return "SVGA_REG_BLUE_MASK";
326 case SVGA_REG_BYTES_PER_LINE:
327 return "SVGA_REG_BYTES_PER_LINE";
328 case SVGA_REG_VRAM_SIZE: /* VRAM size */
329 return "SVGA_REG_VRAM_SIZE";
330 case SVGA_REG_FB_START: /* Frame buffer physical address. */
331 return "SVGA_REG_FB_START";
332 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
333 return "SVGA_REG_FB_OFFSET";
334 case SVGA_REG_FB_SIZE: /* Frame buffer size */
335 return "SVGA_REG_FB_SIZE";
336 case SVGA_REG_CAPABILITIES:
337 return "SVGA_REG_CAPABILITIES";
338 case SVGA_REG_MEM_START: /* FIFO start */
339 return "SVGA_REG_MEM_START";
340 case SVGA_REG_MEM_SIZE: /* FIFO size */
341 return "SVGA_REG_MEM_SIZE";
342 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
343 return "SVGA_REG_CONFIG_DONE";
344 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
345 return "SVGA_REG_SYNC";
346 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
347 return "SVGA_REG_BUSY";
348 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
349 return "SVGA_REG_GUEST_ID";
350 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
351 return "SVGA_REG_SCRATCH_SIZE";
352 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
353 return "SVGA_REG_MEM_REGS";
354 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
355 return "SVGA_REG_PITCHLOCK";
356 case SVGA_REG_IRQMASK: /* Interrupt mask */
357 return "SVGA_REG_IRQMASK";
358 case SVGA_REG_GMR_ID:
359 return "SVGA_REG_GMR_ID";
360 case SVGA_REG_GMR_DESCRIPTOR:
361 return "SVGA_REG_GMR_DESCRIPTOR";
362 case SVGA_REG_GMR_MAX_IDS:
363 return "SVGA_REG_GMR_MAX_IDS";
364 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
365 return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
366 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
367 return "SVGA_REG_TRACES";
368 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
369 return "SVGA_REG_GMRS_MAX_PAGES";
370 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
371 return "SVGA_REG_MEMORY_SIZE";
372 case SVGA_REG_TOP: /* Must be 1 more than the last register */
373 return "SVGA_REG_TOP";
374 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
375 return "SVGA_PALETTE_BASE";
376 case SVGA_REG_CURSOR_ID:
377 return "SVGA_REG_CURSOR_ID";
378 case SVGA_REG_CURSOR_X:
379 return "SVGA_REG_CURSOR_X";
380 case SVGA_REG_CURSOR_Y:
381 return "SVGA_REG_CURSOR_Y";
382 case SVGA_REG_CURSOR_ON:
383 return "SVGA_REG_CURSOR_ON";
384 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
385 return "SVGA_REG_NUM_GUEST_DISPLAYS";
386 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
387 return "SVGA_REG_DISPLAY_ID";
388 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
389 return "SVGA_REG_DISPLAY_IS_PRIMARY";
390 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
391 return "SVGA_REG_DISPLAY_POSITION_X";
392 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
393 return "SVGA_REG_DISPLAY_POSITION_Y";
394 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
395 return "SVGA_REG_DISPLAY_WIDTH";
396 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
397 return "SVGA_REG_DISPLAY_HEIGHT";
398 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
399 return "SVGA_REG_NUM_DISPLAYS";
400
401 default:
402 if (pThis->svga.u32IndexReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
403 return "SVGA_SCRATCH_BASE reg";
404 if (pThis->svga.u32IndexReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
405 return "SVGA_PALETTE_BASE reg";
406 return "UNKNOWN";
407 }
408}
409
410#ifdef IN_RING3
411/**
412 * FIFO command name lookup
413 *
414 * @returns FIFO command string or "UNKNOWN"
415 * @param u32Cmd FIFO command
416 */
417static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
418{
419 switch (u32Cmd)
420 {
421 case SVGA_CMD_INVALID_CMD:
422 return "SVGA_CMD_INVALID_CMD";
423 case SVGA_CMD_UPDATE:
424 return "SVGA_CMD_UPDATE";
425 case SVGA_CMD_RECT_COPY:
426 return "SVGA_CMD_RECT_COPY";
427 case SVGA_CMD_DEFINE_CURSOR:
428 return "SVGA_CMD_DEFINE_CURSOR";
429 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
430 return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
431 case SVGA_CMD_UPDATE_VERBOSE:
432 return "SVGA_CMD_UPDATE_VERBOSE";
433 case SVGA_CMD_FRONT_ROP_FILL:
434 return "SVGA_CMD_FRONT_ROP_FILL";
435 case SVGA_CMD_FENCE:
436 return "SVGA_CMD_FENCE";
437 case SVGA_CMD_ESCAPE:
438 return "SVGA_CMD_ESCAPE";
439 case SVGA_CMD_DEFINE_SCREEN:
440 return "SVGA_CMD_DEFINE_SCREEN";
441 case SVGA_CMD_DESTROY_SCREEN:
442 return "SVGA_CMD_DESTROY_SCREEN";
443 case SVGA_CMD_DEFINE_GMRFB:
444 return "SVGA_CMD_DEFINE_GMRFB";
445 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
446 return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
447 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
448 return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
449 case SVGA_CMD_ANNOTATION_FILL:
450 return "SVGA_CMD_ANNOTATION_FILL";
451 case SVGA_CMD_ANNOTATION_COPY:
452 return "SVGA_CMD_ANNOTATION_COPY";
453 case SVGA_CMD_DEFINE_GMR2:
454 return "SVGA_CMD_DEFINE_GMR2";
455 case SVGA_CMD_REMAP_GMR2:
456 return "SVGA_CMD_REMAP_GMR2";
457 case SVGA_3D_CMD_SURFACE_DEFINE:
458 return "SVGA_3D_CMD_SURFACE_DEFINE";
459 case SVGA_3D_CMD_SURFACE_DESTROY:
460 return "SVGA_3D_CMD_SURFACE_DESTROY";
461 case SVGA_3D_CMD_SURFACE_COPY:
462 return "SVGA_3D_CMD_SURFACE_COPY";
463 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
464 return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
465 case SVGA_3D_CMD_SURFACE_DMA:
466 return "SVGA_3D_CMD_SURFACE_DMA";
467 case SVGA_3D_CMD_CONTEXT_DEFINE:
468 return "SVGA_3D_CMD_CONTEXT_DEFINE";
469 case SVGA_3D_CMD_CONTEXT_DESTROY:
470 return "SVGA_3D_CMD_CONTEXT_DESTROY";
471 case SVGA_3D_CMD_SETTRANSFORM:
472 return "SVGA_3D_CMD_SETTRANSFORM";
473 case SVGA_3D_CMD_SETZRANGE:
474 return "SVGA_3D_CMD_SETZRANGE";
475 case SVGA_3D_CMD_SETRENDERSTATE:
476 return "SVGA_3D_CMD_SETRENDERSTATE";
477 case SVGA_3D_CMD_SETRENDERTARGET:
478 return "SVGA_3D_CMD_SETRENDERTARGET";
479 case SVGA_3D_CMD_SETTEXTURESTATE:
480 return "SVGA_3D_CMD_SETTEXTURESTATE";
481 case SVGA_3D_CMD_SETMATERIAL:
482 return "SVGA_3D_CMD_SETMATERIAL";
483 case SVGA_3D_CMD_SETLIGHTDATA:
484 return "SVGA_3D_CMD_SETLIGHTDATA";
485 case SVGA_3D_CMD_SETLIGHTENABLED:
486 return "SVGA_3D_CMD_SETLIGHTENABLED";
487 case SVGA_3D_CMD_SETVIEWPORT:
488 return "SVGA_3D_CMD_SETVIEWPORT";
489 case SVGA_3D_CMD_SETCLIPPLANE:
490 return "SVGA_3D_CMD_SETCLIPPLANE";
491 case SVGA_3D_CMD_CLEAR:
492 return "SVGA_3D_CMD_CLEAR";
493 case SVGA_3D_CMD_PRESENT:
494 return "SVGA_3D_CMD_PRESENT";
495 case SVGA_3D_CMD_SHADER_DEFINE:
496 return "SVGA_3D_CMD_SHADER_DEFINE";
497 case SVGA_3D_CMD_SHADER_DESTROY:
498 return "SVGA_3D_CMD_SHADER_DESTROY";
499 case SVGA_3D_CMD_SET_SHADER:
500 return "SVGA_3D_CMD_SET_SHADER";
501 case SVGA_3D_CMD_SET_SHADER_CONST:
502 return "SVGA_3D_CMD_SET_SHADER_CONST";
503 case SVGA_3D_CMD_DRAW_PRIMITIVES:
504 return "SVGA_3D_CMD_DRAW_PRIMITIVES";
505 case SVGA_3D_CMD_SETSCISSORRECT:
506 return "SVGA_3D_CMD_SETSCISSORRECT";
507 case SVGA_3D_CMD_BEGIN_QUERY:
508 return "SVGA_3D_CMD_BEGIN_QUERY";
509 case SVGA_3D_CMD_END_QUERY:
510 return "SVGA_3D_CMD_END_QUERY";
511 case SVGA_3D_CMD_WAIT_FOR_QUERY:
512 return "SVGA_3D_CMD_WAIT_FOR_QUERY";
513 case SVGA_3D_CMD_PRESENT_READBACK:
514 return "SVGA_3D_CMD_PRESENT_READBACK";
515 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
516 return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
517 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
518 return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
519 case SVGA_3D_CMD_GENERATE_MIPMAPS:
520 return "SVGA_3D_CMD_GENERATE_MIPMAPS";
521 case SVGA_3D_CMD_ACTIVATE_SURFACE:
522 return "SVGA_3D_CMD_ACTIVATE_SURFACE";
523 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
524 return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
525 default:
526 return "UNKNOWN";
527 }
528}
529# endif /* IN_RING3 */
530
531#endif /* LOG_ENABLED */
532
533#ifdef IN_RING3
534/**
535 * @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
536 */
537DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
538{
539 PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
540
541 Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
542 VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
543
544 if (x < pThis->svga.uWidth)
545 {
546 pThis->svga.viewport.x = x;
547 pThis->svga.viewport.cx = RT_MIN(cx, pThis->svga.uWidth - x);
548 pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
549 }
550 else
551 {
552 pThis->svga.viewport.x = pThis->svga.uWidth;
553 pThis->svga.viewport.cx = 0;
554 pThis->svga.viewport.xRight = pThis->svga.uWidth;
555 }
556 if (y < pThis->svga.uHeight)
557 {
558 pThis->svga.viewport.y = y;
559 pThis->svga.viewport.cy = RT_MIN(cy, pThis->svga.uHeight - y);
560 pThis->svga.viewport.yLowWC = pThis->svga.uHeight - y - pThis->svga.viewport.cy;
561 pThis->svga.viewport.yHighWC = pThis->svga.uHeight - y;
562 }
563 else
564 {
565 pThis->svga.viewport.y = pThis->svga.uHeight;
566 pThis->svga.viewport.cy = 0;
567 pThis->svga.viewport.yLowWC = 0;
568 pThis->svga.viewport.yHighWC = 0;
569 }
570
571# ifdef VBOX_WITH_VMSVGA3D
572 /*
573 * Now inform the 3D backend.
574 */
575 if (pThis->svga.f3DEnabled)
576 vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
577# else
578 RT_NOREF(idScreen, OldViewport);
579# endif
580}
581#endif /* IN_RING3 */
582
583/**
584 * Read port register
585 *
586 * @returns VBox status code.
587 * @param pThis VMSVGA State
588 * @param pu32 Where to store the read value
589 */
590PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
591{
592 int rc = VINF_SUCCESS;
593
594 *pu32 = 0;
595 switch (pThis->svga.u32IndexReg)
596 {
597 case SVGA_REG_ID:
598 *pu32 = pThis->svga.u32SVGAId;
599 break;
600
601 case SVGA_REG_ENABLE:
602 *pu32 = pThis->svga.fEnabled;
603 break;
604
605 case SVGA_REG_WIDTH:
606 {
607 if ( pThis->svga.fEnabled
608 && pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
609 {
610 *pu32 = pThis->svga.uWidth;
611 }
612 else
613 {
614#ifndef IN_RING3
615 rc = VINF_IOM_R3_IOPORT_READ;
616#else
617 *pu32 = pThis->pDrv->cx;
618#endif
619 }
620 break;
621 }
622
623 case SVGA_REG_HEIGHT:
624 {
625 if ( pThis->svga.fEnabled
626 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
627 {
628 *pu32 = pThis->svga.uHeight;
629 }
630 else
631 {
632#ifndef IN_RING3
633 rc = VINF_IOM_R3_IOPORT_READ;
634#else
635 *pu32 = pThis->pDrv->cy;
636#endif
637 }
638 break;
639 }
640
641 case SVGA_REG_MAX_WIDTH:
642 *pu32 = pThis->svga.u32MaxWidth;
643 break;
644
645 case SVGA_REG_MAX_HEIGHT:
646 *pu32 = pThis->svga.u32MaxHeight;
647 break;
648
649 case SVGA_REG_DEPTH:
650 /* This returns the color depth of the current mode. */
651 switch (pThis->svga.uBpp)
652 {
653 case 15:
654 case 16:
655 case 24:
656 *pu32 = pThis->svga.uBpp;
657 break;
658
659 default:
660 case 32:
661 *pu32 = 24; /* The upper 8 bits are either alpha bits or not used. */
662 break;
663 }
664 break;
665
666 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
667 if ( pThis->svga.fEnabled
668 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
669 {
670 *pu32 = pThis->svga.uBpp;
671 }
672 else
673 {
674#ifndef IN_RING3
675 rc = VINF_IOM_R3_IOPORT_READ;
676#else
677 *pu32 = pThis->pDrv->cBits;
678#endif
679 }
680 break;
681
682 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
683 if ( pThis->svga.fEnabled
684 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
685 {
686 *pu32 = (pThis->svga.uBpp + 7) & ~7;
687 }
688 else
689 {
690#ifndef IN_RING3
691 rc = VINF_IOM_R3_IOPORT_READ;
692#else
693 *pu32 = (pThis->pDrv->cBits + 7) & ~7;
694#endif
695 }
696 break;
697
698 case SVGA_REG_PSEUDOCOLOR:
699 *pu32 = 0;
700 break;
701
702 case SVGA_REG_RED_MASK:
703 case SVGA_REG_GREEN_MASK:
704 case SVGA_REG_BLUE_MASK:
705 {
706 uint32_t uBpp;
707
708 if ( pThis->svga.fEnabled
709 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
710 {
711 uBpp = pThis->svga.uBpp;
712 }
713 else
714 {
715#ifndef IN_RING3
716 rc = VINF_IOM_R3_IOPORT_READ;
717 break;
718#else
719 uBpp = pThis->pDrv->cBits;
720#endif
721 }
722 uint32_t u32RedMask, u32GreenMask, u32BlueMask;
723 switch (uBpp)
724 {
725 case 8:
726 u32RedMask = 0x07;
727 u32GreenMask = 0x38;
728 u32BlueMask = 0xc0;
729 break;
730
731 case 15:
732 u32RedMask = 0x0000001f;
733 u32GreenMask = 0x000003e0;
734 u32BlueMask = 0x00007c00;
735 break;
736
737 case 16:
738 u32RedMask = 0x0000001f;
739 u32GreenMask = 0x000007e0;
740 u32BlueMask = 0x0000f800;
741 break;
742
743 case 24:
744 case 32:
745 default:
746 u32RedMask = 0x00ff0000;
747 u32GreenMask = 0x0000ff00;
748 u32BlueMask = 0x000000ff;
749 break;
750 }
751 switch (pThis->svga.u32IndexReg)
752 {
753 case SVGA_REG_RED_MASK:
754 *pu32 = u32RedMask;
755 break;
756
757 case SVGA_REG_GREEN_MASK:
758 *pu32 = u32GreenMask;
759 break;
760
761 case SVGA_REG_BLUE_MASK:
762 *pu32 = u32BlueMask;
763 break;
764 }
765 break;
766 }
767
768 case SVGA_REG_BYTES_PER_LINE:
769 {
770 if ( pThis->svga.fEnabled
771 && pThis->svga.cbScanline)
772 {
773 *pu32 = pThis->svga.cbScanline;
774 }
775 else
776 {
777#ifndef IN_RING3
778 rc = VINF_IOM_R3_IOPORT_READ;
779#else
780 *pu32 = pThis->pDrv->cbScanline;
781#endif
782 }
783 break;
784 }
785
786 case SVGA_REG_VRAM_SIZE: /* VRAM size */
787 *pu32 = pThis->vram_size;
788 break;
789
790 case SVGA_REG_FB_START: /* Frame buffer physical address. */
791 Assert(pThis->GCPhysVRAM <= 0xffffffff);
792 *pu32 = pThis->GCPhysVRAM;
793 break;
794
795 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
796 /* Always zero in our case. */
797 *pu32 = 0;
798 break;
799
800 case SVGA_REG_FB_SIZE: /* Frame buffer size */
801 {
802#ifndef IN_RING3
803 rc = VINF_IOM_R3_IOPORT_READ;
804#else
805 /* VMWare testcases want at least 4 MB in case the hardware is disabled. */
806 if ( pThis->svga.fEnabled
807 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
808 {
809 /* Hardware enabled; return real framebuffer size .*/
810 *pu32 = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
811 }
812 else
813 *pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy * pThis->pDrv->cbScanline);
814
815 *pu32 = RT_MIN(pThis->vram_size, *pu32);
816 Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
817#endif
818 break;
819 }
820
821 case SVGA_REG_CAPABILITIES:
822 *pu32 = pThis->svga.u32RegCaps;
823 break;
824
825 case SVGA_REG_MEM_START: /* FIFO start */
826 Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
827 *pu32 = pThis->svga.GCPhysFIFO;
828 break;
829
830 case SVGA_REG_MEM_SIZE: /* FIFO size */
831 *pu32 = pThis->svga.cbFIFO;
832 break;
833
834 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
835 *pu32 = pThis->svga.fConfigured;
836 break;
837
838 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
839 *pu32 = 0;
840 break;
841
842 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
843 if (pThis->svga.fBusy)
844 {
845#ifndef IN_RING3
846 /* Go to ring-3 and halt the CPU. */
847 rc = VINF_IOM_R3_IOPORT_READ;
848 break;
849#else
850# if defined(VMSVGA_USE_EMT_HALT_CODE)
851 /* The guest is basically doing a HLT via the device here, but with
852 a special wake up condition on FIFO completion. */
853 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
854 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
855 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
856 VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
857 VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
858 ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
859 if (pThis->svga.fBusy)
860 rc = VMR3WaitForDeviceReady(pVM, idCpu);
861 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
862 VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
863# else
864
865 /* Delay the EMT a bit so the FIFO and others can get some work done.
866 This used to be a crude 50 ms sleep. The current code tries to be
867 more efficient, but the consept is still very crude. */
868 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
869 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
870 RTThreadYield();
871 if (pThis->svga.fBusy)
872 {
873 uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
874
875 if (pThis->svga.fBusy && cRefs == 1)
876 RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
877 if (pThis->svga.fBusy)
878 {
879 /** @todo If this code is going to stay, we need to call into the halt/wait
880 * code in VMEmt.cpp here, otherwise all kind of EMT interaction will
881 * suffer when the guest is polling on a busy FIFO. */
882 uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
883 if (cNsMaxWait >= RT_NS_100US)
884 RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
885 RTSEMWAIT_FLAGS_NANOSECS | RTSEMWAIT_FLAGS_RELATIVE | RTSEMWAIT_FLAGS_NORESUME,
886 RT_MIN(cNsMaxWait, RT_NS_10MS));
887 }
888
889 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
890 }
891 STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
892# endif
893 *pu32 = pThis->svga.fBusy != 0;
894#endif
895 }
896 else
897 *pu32 = false;
898 break;
899
900 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
901 *pu32 = pThis->svga.u32GuestId;
902 break;
903
904 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
905 *pu32 = pThis->svga.cScratchRegion;
906 break;
907
908 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
909 *pu32 = SVGA_FIFO_NUM_REGS;
910 break;
911
912 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
913 *pu32 = pThis->svga.u32PitchLock;
914 break;
915
916 case SVGA_REG_IRQMASK: /* Interrupt mask */
917 *pu32 = pThis->svga.u32IrqMask;
918 break;
919
920 /* See "Guest memory regions" below. */
921 case SVGA_REG_GMR_ID:
922 *pu32 = pThis->svga.u32CurrentGMRId;
923 break;
924
925 case SVGA_REG_GMR_DESCRIPTOR:
926 /* Write only */
927 *pu32 = 0;
928 break;
929
930 case SVGA_REG_GMR_MAX_IDS:
931 *pu32 = VMSVGA_MAX_GMR_IDS;
932 break;
933
934 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
935 *pu32 = VMSVGA_MAX_GMR_PAGES;
936 break;
937
938 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
939 *pu32 = pThis->svga.fTraces;
940 break;
941
942 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
943 *pu32 = VMSVGA_MAX_GMR_PAGES;
944 break;
945
946 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
947 *pu32 = VMSVGA_SURFACE_SIZE;
948 break;
949
950 case SVGA_REG_TOP: /* Must be 1 more than the last register */
951 break;
952
953 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
954 break;
955 /* Next 768 (== 256*3) registers exist for colormap */
956
957 /* Mouse cursor support. */
958 case SVGA_REG_CURSOR_ID:
959 case SVGA_REG_CURSOR_X:
960 case SVGA_REG_CURSOR_Y:
961 case SVGA_REG_CURSOR_ON:
962 break;
963
964 /* Legacy multi-monitor support */
965 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
966 *pu32 = 1;
967 break;
968
969 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
970 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
971 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
972 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
973 *pu32 = 0;
974 break;
975
976 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
977 *pu32 = pThis->svga.uWidth;
978 break;
979
980 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
981 *pu32 = pThis->svga.uHeight;
982 break;
983
984 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
985 *pu32 = 1; /* Must return something sensible here otherwise the Linux driver will take a legacy code path without 3d support. */
986 break;
987
988 default:
989 if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE
990 && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
991 {
992 *pu32 = pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE];
993 }
994 break;
995 }
996 Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, *pu32, rc));
997 return rc;
998}
999
1000#ifdef IN_RING3
1001/**
1002 * Apply the current resolution settings to change the video mode.
1003 *
1004 * @returns VBox status code.
1005 * @param pThis VMSVGA State
1006 */
1007int vmsvgaChangeMode(PVGASTATE pThis)
1008{
1009 int rc;
1010
1011 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1012 || pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1013 || pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1014 {
1015 /* Mode change in progress; wait for all values to be set. */
1016 Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1017 return VINF_SUCCESS;
1018 }
1019
1020 if ( pThis->svga.uWidth == 0
1021 || pThis->svga.uHeight == 0
1022 || pThis->svga.uBpp == 0)
1023 {
1024 /* Invalid mode change - BB does this early in the boot up. */
1025 Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1026 return VINF_SUCCESS;
1027 }
1028
1029 if ( pThis->last_bpp == (unsigned)pThis->svga.uBpp
1030 && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1031 && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1032 && pThis->last_width == (unsigned)pThis->svga.uWidth
1033 && pThis->last_height == (unsigned)pThis->svga.uHeight
1034 )
1035 {
1036 /* Nothing to do. */
1037 Log(("vmsvgaChangeMode: nothing changed; ignore\n"));
1038 return VINF_SUCCESS;
1039 }
1040
1041 Log(("vmsvgaChangeMode: sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1042 pThis->svga.cbScanline = ((pThis->svga.uWidth * pThis->svga.uBpp + 7) & ~7) / 8;
1043
1044 pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1045 rc = pThis->pDrv->pfnResize(pThis->pDrv, pThis->svga.uBpp, pThis->CTX_SUFF(vram_ptr), pThis->svga.cbScanline, pThis->svga.uWidth, pThis->svga.uHeight);
1046 AssertRC(rc);
1047 AssertReturn(rc == VINF_SUCCESS || rc == VINF_VGA_RESIZE_IN_PROGRESS, rc);
1048
1049 /* last stuff */
1050 pThis->last_bpp = pThis->svga.uBpp;
1051 pThis->last_scr_width = pThis->svga.uWidth;
1052 pThis->last_scr_height = pThis->svga.uHeight;
1053 pThis->last_width = pThis->svga.uWidth;
1054 pThis->last_height = pThis->svga.uHeight;
1055
1056 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1057
1058 /* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1059 if ( pThis->svga.viewport.cx == 0
1060 && pThis->svga.viewport.cy == 0)
1061 {
1062 pThis->svga.viewport.cx = pThis->svga.uWidth;
1063 pThis->svga.viewport.xRight = pThis->svga.uWidth;
1064 pThis->svga.viewport.cy = pThis->svga.uHeight;
1065 pThis->svga.viewport.yHighWC = pThis->svga.uHeight;
1066 pThis->svga.viewport.yLowWC = 0;
1067 }
1068 return VINF_SUCCESS;
1069}
1070#endif /* IN_RING3 */
1071
1072#if defined(IN_RING0) || defined(IN_RING3)
1073/**
1074 * Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1075 *
1076 * @param pThis The VMSVGA state.
1077 * @param fState The busy state.
1078 */
1079DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1080{
1081 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1082
1083 if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1084 {
1085 /* Race / unfortunately scheduling. Highly unlikly. */
1086 uint32_t cLoops = 64;
1087 do
1088 {
1089 ASMNopPause();
1090 fState = (pThis->svga.fBusy != 0);
1091 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1092 } while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1093 }
1094}
1095#endif
1096
1097/**
1098 * Write port register
1099 *
1100 * @returns VBox status code.
1101 * @param pThis VMSVGA State
1102 * @param u32 Value to write
1103 */
1104PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1105{
1106#if defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D)
1107 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1108#endif
1109 int rc = VINF_SUCCESS;
1110
1111 Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, u32));
1112 switch (pThis->svga.u32IndexReg)
1113 {
1114 case SVGA_REG_ID:
1115 if ( u32 == SVGA_ID_0
1116 || u32 == SVGA_ID_1
1117 || u32 == SVGA_ID_2)
1118 pThis->svga.u32SVGAId = u32;
1119 break;
1120
1121 case SVGA_REG_ENABLE:
1122 if ( pThis->svga.fEnabled == u32
1123 && pThis->last_bpp == (unsigned)pThis->svga.uBpp
1124 && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1125 && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1126 && pThis->last_width == (unsigned)pThis->svga.uWidth
1127 && pThis->last_height == (unsigned)pThis->svga.uHeight
1128 )
1129 /* Nothing to do. */
1130 break;
1131
1132#ifdef IN_RING3
1133 if ( u32 == 1
1134 && pThis->svga.fEnabled == false)
1135 {
1136 /* Make a backup copy of the first 32k in order to save font data etc. */
1137 memcpy(pThis->svga.pFrameBufferBackup, pThis->vram_ptrR3, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
1138 }
1139
1140 pThis->svga.fEnabled = u32;
1141 if (pThis->svga.fEnabled)
1142 {
1143 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1144 && pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1145 && pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1146 {
1147 /* Keep the current mode. */
1148 pThis->svga.uWidth = pThis->pDrv->cx;
1149 pThis->svga.uHeight = pThis->pDrv->cy;
1150 pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1151 }
1152
1153 if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1154 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1155 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1156 {
1157 rc = vmsvgaChangeMode(pThis);
1158 AssertRCReturn(rc, rc);
1159 }
1160# ifdef LOG_ENABLED
1161 Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
1162 uint32_t *pFIFO = pThis->svga.pFIFOR3;
1163 Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1164# endif
1165
1166 /* Disable or enable dirty page tracking according to the current fTraces value. */
1167 vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1168 }
1169 else
1170 {
1171 /* Restore the text mode backup. */
1172 memcpy(pThis->vram_ptrR3, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
1173
1174/* pThis->svga.uHeight = -1;
1175 pThis->svga.uWidth = -1;
1176 pThis->svga.uBpp = -1;
1177 pThis->svga.cbScanline = 0; */
1178 pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1179
1180 /* Enable dirty page tracking again when going into legacy mode. */
1181 vmsvgaSetTraces(pThis, true);
1182 }
1183#else
1184 rc = VINF_IOM_R3_IOPORT_WRITE;
1185#endif
1186 break;
1187
1188 case SVGA_REG_WIDTH:
1189 if (pThis->svga.uWidth != u32)
1190 {
1191 if (pThis->svga.fEnabled)
1192 {
1193#ifdef IN_RING3
1194 pThis->svga.uWidth = u32;
1195 rc = vmsvgaChangeMode(pThis);
1196 AssertRCReturn(rc, rc);
1197#else
1198 rc = VINF_IOM_R3_IOPORT_WRITE;
1199#endif
1200 }
1201 else
1202 pThis->svga.uWidth = u32;
1203 }
1204 /* else: nop */
1205 break;
1206
1207 case SVGA_REG_HEIGHT:
1208 if (pThis->svga.uHeight != u32)
1209 {
1210 if (pThis->svga.fEnabled)
1211 {
1212#ifdef IN_RING3
1213 pThis->svga.uHeight = u32;
1214 rc = vmsvgaChangeMode(pThis);
1215 AssertRCReturn(rc, rc);
1216#else
1217 rc = VINF_IOM_R3_IOPORT_WRITE;
1218#endif
1219 }
1220 else
1221 pThis->svga.uHeight = u32;
1222 }
1223 /* else: nop */
1224 break;
1225
1226 case SVGA_REG_DEPTH:
1227 /** @todo read-only?? */
1228 break;
1229
1230 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1231 if (pThis->svga.uBpp != u32)
1232 {
1233 if (pThis->svga.fEnabled)
1234 {
1235#ifdef IN_RING3
1236 pThis->svga.uBpp = u32;
1237 rc = vmsvgaChangeMode(pThis);
1238 AssertRCReturn(rc, rc);
1239#else
1240 rc = VINF_IOM_R3_IOPORT_WRITE;
1241#endif
1242 }
1243 else
1244 pThis->svga.uBpp = u32;
1245 }
1246 /* else: nop */
1247 break;
1248
1249 case SVGA_REG_PSEUDOCOLOR:
1250 break;
1251
1252 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1253#ifdef IN_RING3
1254 pThis->svga.fConfigured = u32;
1255 /* Disabling the FIFO enables tracing (dirty page detection) by default. */
1256 if (!pThis->svga.fConfigured)
1257 {
1258 pThis->svga.fTraces = true;
1259 }
1260 vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1261#else
1262 rc = VINF_IOM_R3_IOPORT_WRITE;
1263#endif
1264 break;
1265
1266 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1267 if ( pThis->svga.fEnabled
1268 && pThis->svga.fConfigured)
1269 {
1270#if defined(IN_RING3) || defined(IN_RING0)
1271 Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1272 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE | VMSVGA_BUSY_F_FIFO);
1273 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1274 vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1275
1276 /* Kick the FIFO thread to start processing commands again. */
1277 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1278#else
1279 rc = VINF_IOM_R3_IOPORT_WRITE;
1280#endif
1281 }
1282 /* else nothing to do. */
1283 else
1284 Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1285
1286 break;
1287
1288 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1289 break;
1290
1291 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1292 pThis->svga.u32GuestId = u32;
1293 break;
1294
1295 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1296 pThis->svga.u32PitchLock = u32;
1297 break;
1298
1299 case SVGA_REG_IRQMASK: /* Interrupt mask */
1300 pThis->svga.u32IrqMask = u32;
1301
1302 /* Irq pending after the above change? */
1303 if (pThis->svga.u32IrqStatus & u32)
1304 {
1305 Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1306 PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1307 }
1308 else
1309 PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1310 break;
1311
1312 /* Mouse cursor support */
1313 case SVGA_REG_CURSOR_ID:
1314 case SVGA_REG_CURSOR_X:
1315 case SVGA_REG_CURSOR_Y:
1316 case SVGA_REG_CURSOR_ON:
1317 break;
1318
1319 /* Legacy multi-monitor support */
1320 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1321 break;
1322 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1323 break;
1324 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1325 break;
1326 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1327 break;
1328 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1329 break;
1330 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1331 break;
1332 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1333 break;
1334#ifdef VBOX_WITH_VMSVGA3D
1335 /* See "Guest memory regions" below. */
1336 case SVGA_REG_GMR_ID:
1337 pThis->svga.u32CurrentGMRId = u32;
1338 break;
1339
1340 case SVGA_REG_GMR_DESCRIPTOR:
1341# ifndef IN_RING3
1342 rc = VINF_IOM_R3_IOPORT_WRITE;
1343 break;
1344# else /* IN_RING3 */
1345 {
1346 SVGAGuestMemDescriptor desc;
1347 RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1348 RTGCPHYS GCPhysBase = GCPhys;
1349 uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1350 uint32_t cDescriptorsAllocated = 16;
1351 uint32_t iDescriptor = 0;
1352
1353 /* Validate current GMR id. */
1354 AssertBreak(idGMR < VMSVGA_MAX_GMR_IDS);
1355
1356 /* Free the old GMR if present. */
1357 vmsvgaGMRFree(pThis, idGMR);
1358
1359 /* Just undefine the GMR? */
1360 if (GCPhys == 0)
1361 break;
1362
1363 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1364 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1365
1366 /* Never cross a page boundary automatically. */
1367 while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1368 {
1369 /* Read descriptor. */
1370 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1371 AssertRCBreak(rc);
1372
1373 if ( desc.ppn == 0
1374 && desc.numPages == 0)
1375 break; /* terminator */
1376
1377 if ( desc.ppn != 0
1378 && desc.numPages == 0)
1379 {
1380 /* Pointer to the next physical page of descriptors. */
1381 GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1382 }
1383 else
1384 {
1385 if (iDescriptor == cDescriptorsAllocated)
1386 {
1387 cDescriptorsAllocated += 16;
1388 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemRealloc(pSVGAState->aGMR[idGMR].paDesc, cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1389 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1390 }
1391
1392 pSVGAState->aGMR[idGMR].paDesc[iDescriptor].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1393 pSVGAState->aGMR[idGMR].paDesc[iDescriptor++].numPages = desc.numPages;
1394 pSVGAState->aGMR[idGMR].cbTotal += desc.numPages * PAGE_SIZE;
1395
1396 /* Continue with the next descriptor. */
1397 GCPhys += sizeof(desc);
1398 }
1399 }
1400 pSVGAState->aGMR[idGMR].numDescriptors = iDescriptor;
1401 Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x\n", idGMR, iDescriptor, pSVGAState->aGMR[idGMR].cbTotal));
1402
1403 if (!pSVGAState->aGMR[idGMR].numDescriptors)
1404 {
1405 AssertFailed();
1406 RTMemFree(pSVGAState->aGMR[idGMR].paDesc);
1407 pSVGAState->aGMR[idGMR].paDesc = NULL;
1408 }
1409 AssertRC(rc);
1410 break;
1411 }
1412# endif /* IN_RING3 */
1413#endif // VBOX_WITH_VMSVGA3D
1414
1415 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1416 if (pThis->svga.fTraces == u32)
1417 break; /* nothing to do */
1418
1419#ifdef IN_RING3
1420 vmsvgaSetTraces(pThis, !!u32);
1421#else
1422 rc = VINF_IOM_R3_IOPORT_WRITE;
1423#endif
1424 break;
1425
1426 case SVGA_REG_TOP: /* Must be 1 more than the last register */
1427 break;
1428
1429 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
1430 break;
1431 /* Next 768 (== 256*3) registers exist for colormap */
1432
1433 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1434 Log(("Write to deprecated register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
1435 break;
1436
1437 case SVGA_REG_FB_START:
1438 case SVGA_REG_MEM_START:
1439 case SVGA_REG_HOST_BITS_PER_PIXEL:
1440 case SVGA_REG_MAX_WIDTH:
1441 case SVGA_REG_MAX_HEIGHT:
1442 case SVGA_REG_VRAM_SIZE:
1443 case SVGA_REG_FB_SIZE:
1444 case SVGA_REG_CAPABILITIES:
1445 case SVGA_REG_MEM_SIZE:
1446 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1447 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1448 case SVGA_REG_BYTES_PER_LINE:
1449 case SVGA_REG_FB_OFFSET:
1450 case SVGA_REG_RED_MASK:
1451 case SVGA_REG_GREEN_MASK:
1452 case SVGA_REG_BLUE_MASK:
1453 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1454 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1455 case SVGA_REG_GMR_MAX_IDS:
1456 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1457 /* Read only - ignore. */
1458 Log(("Write to R/O register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
1459 break;
1460
1461 default:
1462 if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE
1463 && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
1464 {
1465 pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE] = u32;
1466 }
1467 break;
1468 }
1469 return rc;
1470}
1471
1472/**
1473 * Port I/O Handler for IN operations.
1474 *
1475 * @returns VINF_SUCCESS or VINF_EM_*.
1476 * @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1477 *
1478 * @param pDevIns The device instance.
1479 * @param pvUser User argument.
1480 * @param uPort Port number used for the IN operation.
1481 * @param pu32 Where to store the result. This is always a 32-bit
1482 * variable regardless of what @a cb might say.
1483 * @param cb Number of bytes read.
1484 */
1485PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
1486{
1487 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1488 RT_NOREF_PV(pvUser);
1489
1490 /* Ignore non-dword accesses. */
1491 if (cb != 4)
1492 {
1493 Log(("Ignoring non-dword read at %x cb=%d\n", uPort, cb));
1494 *pu32 = UINT32_MAX;
1495 return VINF_SUCCESS;
1496 }
1497
1498 switch (uPort - pThis->svga.BasePort)
1499 {
1500 case SVGA_INDEX_PORT:
1501 *pu32 = pThis->svga.u32IndexReg;
1502 break;
1503
1504 case SVGA_VALUE_PORT:
1505 return vmsvgaReadPort(pThis, pu32);
1506
1507 case SVGA_BIOS_PORT:
1508 Log(("Ignoring BIOS port read\n"));
1509 *pu32 = 0;
1510 break;
1511
1512 case SVGA_IRQSTATUS_PORT:
1513 LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1514 *pu32 = pThis->svga.u32IrqStatus;
1515 break;
1516 }
1517
1518 return VINF_SUCCESS;
1519}
1520
1521/**
1522 * Port I/O Handler for OUT operations.
1523 *
1524 * @returns VINF_SUCCESS or VINF_EM_*.
1525 *
1526 * @param pDevIns The device instance.
1527 * @param pvUser User argument.
1528 * @param uPort Port number used for the OUT operation.
1529 * @param u32 The value to output.
1530 * @param cb The value size in bytes.
1531 */
1532PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
1533{
1534 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1535 RT_NOREF_PV(pvUser);
1536
1537 /* Ignore non-dword accesses. */
1538 if (cb != 4)
1539 {
1540 Log(("Ignoring non-dword write at %x val=%x cb=%d\n", uPort, u32, cb));
1541 return VINF_SUCCESS;
1542 }
1543
1544 switch (uPort - pThis->svga.BasePort)
1545 {
1546 case SVGA_INDEX_PORT:
1547 pThis->svga.u32IndexReg = u32;
1548 break;
1549
1550 case SVGA_VALUE_PORT:
1551 return vmsvgaWritePort(pThis, u32);
1552
1553 case SVGA_BIOS_PORT:
1554 Log(("Ignoring BIOS port write (val=%x)\n", u32));
1555 break;
1556
1557 case SVGA_IRQSTATUS_PORT:
1558 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
1559 ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
1560 /* Clear the irq in case all events have been cleared. */
1561 if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
1562 {
1563 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
1564 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1565 }
1566 break;
1567 }
1568 return VINF_SUCCESS;
1569}
1570
1571#ifdef DEBUG_FIFO_ACCESS
1572
1573# ifdef IN_RING3
1574/**
1575 * Handle LFB access.
1576 * @returns VBox status code.
1577 * @param pVM VM handle.
1578 * @param pThis VGA device instance data.
1579 * @param GCPhys The access physical address.
1580 * @param fWriteAccess Read or write access
1581 */
1582static int vmsvgaFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
1583{
1584 RT_NOREF(pVM);
1585 RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
1586 uint32_t *pFIFO = pThis->svga.pFIFOR3;
1587
1588 switch (GCPhysOffset >> 2)
1589 {
1590 case SVGA_FIFO_MIN:
1591 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1592 break;
1593 case SVGA_FIFO_MAX:
1594 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1595 break;
1596 case SVGA_FIFO_NEXT_CMD:
1597 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1598 break;
1599 case SVGA_FIFO_STOP:
1600 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1601 break;
1602 case SVGA_FIFO_CAPABILITIES:
1603 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1604 break;
1605 case SVGA_FIFO_FLAGS:
1606 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1607 break;
1608 case SVGA_FIFO_FENCE:
1609 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1610 break;
1611 case SVGA_FIFO_3D_HWVERSION:
1612 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1613 break;
1614 case SVGA_FIFO_PITCHLOCK:
1615 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1616 break;
1617 case SVGA_FIFO_CURSOR_ON:
1618 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1619 break;
1620 case SVGA_FIFO_CURSOR_X:
1621 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1622 break;
1623 case SVGA_FIFO_CURSOR_Y:
1624 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1625 break;
1626 case SVGA_FIFO_CURSOR_COUNT:
1627 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1628 break;
1629 case SVGA_FIFO_CURSOR_LAST_UPDATED:
1630 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1631 break;
1632 case SVGA_FIFO_RESERVED:
1633 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1634 break;
1635 case SVGA_FIFO_CURSOR_SCREEN_ID:
1636 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1637 break;
1638 case SVGA_FIFO_DEAD:
1639 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1640 break;
1641 case SVGA_FIFO_3D_HWVERSION_REVISED:
1642 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1643 break;
1644 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
1645 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1646 break;
1647 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
1648 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1649 break;
1650 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
1651 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1652 break;
1653 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
1654 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1655 break;
1656 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
1657 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1658 break;
1659 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
1660 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1661 break;
1662 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
1663 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1664 break;
1665 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
1666 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1667 break;
1668 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
1669 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1670 break;
1671 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
1672 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1673 break;
1674 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
1675 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1676 break;
1677 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
1678 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1679 break;
1680 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
1681 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1682 break;
1683 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
1684 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1685 break;
1686 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
1687 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1688 break;
1689 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
1690 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1691 break;
1692 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
1693 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1694 break;
1695 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
1696 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1697 break;
1698 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
1699 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1700 break;
1701 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
1702 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1703 break;
1704 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
1705 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1706 break;
1707 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
1708 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1709 break;
1710 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
1711 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1712 break;
1713 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
1714 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1715 break;
1716 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
1717 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1718 break;
1719 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
1720 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1721 break;
1722 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
1723 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1724 break;
1725 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
1726 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1727 break;
1728 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
1729 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1730 break;
1731 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
1732 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1733 break;
1734 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
1735 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1736 break;
1737 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
1738 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1739 break;
1740 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
1741 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1742 break;
1743 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
1744 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1745 break;
1746 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
1747 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1748 break;
1749 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
1750 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1751 break;
1752 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
1753 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1754 break;
1755 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
1756 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1757 break;
1758 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
1759 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1760 break;
1761 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
1762 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1763 break;
1764 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
1765 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1766 break;
1767 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
1768 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1769 break;
1770 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
1771 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1772 break;
1773 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
1774 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1775 break;
1776 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
1777 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1778 break;
1779 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
1780 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1781 break;
1782 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
1783 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1784 break;
1785 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
1786 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1787 break;
1788 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
1789 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1790 break;
1791 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
1792 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1793 break;
1794 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
1795 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1796 break;
1797 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
1798 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1799 break;
1800 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
1801 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1802 break;
1803 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
1804 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1805 break;
1806 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
1807 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1808 break;
1809 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
1810 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1811 break;
1812 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
1813 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1814 break;
1815 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
1816 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1817 break;
1818 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
1819 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1820 break;
1821 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
1822 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1823 break;
1824 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
1825 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1826 break;
1827 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
1828 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1829 break;
1830 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
1831 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1832 break;
1833 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
1834 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1835 break;
1836 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
1837 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1838 break;
1839 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
1840 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1841 break;
1842 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
1843 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1844 break;
1845 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
1846 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1847 break;
1848 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
1849 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1850 break;
1851 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
1852 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1853 break;
1854 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
1855 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1856 break;
1857 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
1858 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1859 break;
1860 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
1861 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1862 break;
1863 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
1864 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1865 break;
1866 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
1867 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1868 break;
1869 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
1870 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1871 break;
1872 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
1873 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1874 break;
1875 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
1876 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1877 break;
1878 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
1879 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1880 break;
1881 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
1882 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1883 break;
1884 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
1885 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1886 break;
1887 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
1888 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1889 break;
1890 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
1891 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1892 break;
1893 case SVGA_FIFO_3D_CAPS_LAST:
1894 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1895 break;
1896 case SVGA_FIFO_GUEST_3D_HWVERSION:
1897 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1898 break;
1899 case SVGA_FIFO_FENCE_GOAL:
1900 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1901 break;
1902 case SVGA_FIFO_BUSY:
1903 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1904 break;
1905 default:
1906 Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
1907 break;
1908 }
1909
1910 return VINF_EM_RAW_EMULATE_INSTR;
1911}
1912
1913/**
1914 * HC access handler for the FIFO.
1915 *
1916 * @returns VINF_SUCCESS if the handler have carried out the operation.
1917 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1918 * @param pVM VM Handle.
1919 * @param pVCpu The cross context CPU structure for the calling EMT.
1920 * @param GCPhys The physical address the guest is writing to.
1921 * @param pvPhys The HC mapping of that address.
1922 * @param pvBuf What the guest is reading/writing.
1923 * @param cbBuf How much it's reading/writing.
1924 * @param enmAccessType The access type.
1925 * @param enmOrigin Who is making the access.
1926 * @param pvUser User argument.
1927 */
1928static DECLCALLBACK(VBOXSTRICTRC)
1929vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
1930 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1931{
1932 PVGASTATE pThis = (PVGASTATE)pvUser;
1933 int rc;
1934 Assert(pThis);
1935 Assert(GCPhys >= pThis->svga.GCPhysFIFO);
1936 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
1937
1938 rc = vmsvgaFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
1939 if (RT_SUCCESS(rc))
1940 return VINF_PGM_HANDLER_DO_DEFAULT;
1941 AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
1942 return rc;
1943}
1944
1945# endif /* IN_RING3 */
1946#endif /* DEBUG_FIFO_ACCESS */
1947
1948#ifdef DEBUG_GMR_ACCESS
1949# ifdef IN_RING3
1950
1951/**
1952 * HC access handler for the FIFO.
1953 *
1954 * @returns VINF_SUCCESS if the handler have carried out the operation.
1955 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1956 * @param pVM VM Handle.
1957 * @param pVCpu The cross context CPU structure for the calling EMT.
1958 * @param GCPhys The physical address the guest is writing to.
1959 * @param pvPhys The HC mapping of that address.
1960 * @param pvBuf What the guest is reading/writing.
1961 * @param cbBuf How much it's reading/writing.
1962 * @param enmAccessType The access type.
1963 * @param enmOrigin Who is making the access.
1964 * @param pvUser User argument.
1965 */
1966static DECLCALLBACK(VBOXSTRICTRC)
1967vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
1968 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1969{
1970 PVGASTATE pThis = (PVGASTATE)pvUser;
1971 Assert(pThis);
1972 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1973 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
1974
1975 Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
1976
1977 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
1978 {
1979 PGMR pGMR = &pSVGAState->aGMR[i];
1980
1981 if (pGMR->numDescriptors)
1982 {
1983 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
1984 {
1985 if ( GCPhys >= pGMR->paDesc[j].GCPhys
1986 && GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
1987 {
1988 /*
1989 * Turn off the write handler for this particular page and make it R/W.
1990 * Then return telling the caller to restart the guest instruction.
1991 */
1992 int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
1993 AssertRC(rc);
1994 goto end;
1995 }
1996 }
1997 }
1998 }
1999end:
2000 return VINF_PGM_HANDLER_DO_DEFAULT;
2001}
2002
2003/* Callback handler for VMR3ReqCallWaitU */
2004static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2005{
2006 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2007 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2008 PGMR pGMR = &pSVGAState->aGMR[gmrId];
2009 int rc;
2010
2011 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2012 {
2013 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2014 pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2015 pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2016 AssertRC(rc);
2017 }
2018 return VINF_SUCCESS;
2019}
2020
2021/* Callback handler for VMR3ReqCallWaitU */
2022static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2023{
2024 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2025 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2026 PGMR pGMR = &pSVGAState->aGMR[gmrId];
2027
2028 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2029 {
2030 int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2031 AssertRC(rc);
2032 }
2033 return VINF_SUCCESS;
2034}
2035
2036/* Callback handler for VMR3ReqCallWaitU */
2037static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2038{
2039 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2040
2041 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
2042 {
2043 PGMR pGMR = &pSVGAState->aGMR[i];
2044
2045 if (pGMR->numDescriptors)
2046 {
2047 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2048 {
2049 int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2050 AssertRC(rc);
2051 }
2052 }
2053 }
2054 return VINF_SUCCESS;
2055}
2056
2057# endif /* IN_RING3 */
2058#endif /* DEBUG_GMR_ACCESS */
2059
2060/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2061
2062#ifdef IN_RING3
2063
2064/**
2065 * Worker for vmsvgaR3FifoThread that handles an external command.
2066 *
2067 * @param pThis VGA device instance data.
2068 */
2069static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2070{
2071 uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2072 switch (pThis->svga.u8FIFOExtCommand)
2073 {
2074 case VMSVGA_FIFO_EXTCMD_RESET:
2075 Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2076 Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2077# ifdef VBOX_WITH_VMSVGA3D
2078 if (pThis->svga.f3DEnabled)
2079 {
2080 /* The 3d subsystem must be reset from the fifo thread. */
2081 vmsvga3dReset(pThis);
2082 }
2083# endif
2084 break;
2085
2086 case VMSVGA_FIFO_EXTCMD_TERMINATE:
2087 Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2088 Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2089# ifdef VBOX_WITH_VMSVGA3D
2090 if (pThis->svga.f3DEnabled)
2091 {
2092 /* The 3d subsystem must be shut down from the fifo thread. */
2093 vmsvga3dTerminate(pThis);
2094 }
2095# endif
2096 break;
2097
2098 case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2099 {
2100 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2101# ifdef VBOX_WITH_VMSVGA3D
2102 PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2103 AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2104 vmsvga3dSaveExec(pThis, pSSM);
2105# endif
2106 break;
2107 }
2108
2109 case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2110 {
2111 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2112# ifdef VBOX_WITH_VMSVGA3D
2113 PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2114 AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2115 vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2116# endif
2117 break;
2118 }
2119
2120 case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2121 {
2122# ifdef VBOX_WITH_VMSVGA3D
2123 uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2124 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2125 vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2126# endif
2127 break;
2128 }
2129
2130
2131 default:
2132 AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2133 break;
2134 }
2135
2136 /*
2137 * Signal the end of the external command.
2138 */
2139 pThis->svga.pvFIFOExtCmdParam = NULL;
2140 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2141 ASMMemoryFence(); /* paranoia^2 */
2142 int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2143 AssertLogRelRC(rc);
2144}
2145
2146/**
2147 * Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2148 * doing a job on the FIFO thread (even when it's officially suspended).
2149 *
2150 * @returns VBox status code (fully asserted).
2151 * @param pThis VGA device instance data.
2152 * @param uExtCmd The command to execute on the FIFO thread.
2153 * @param pvParam Pointer to command parameters.
2154 * @param cMsWait The time to wait for the command, given in
2155 * milliseconds.
2156 */
2157static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2158{
2159 Assert(cMsWait >= RT_MS_1SEC * 5);
2160 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2161 ("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2162
2163 int rc;
2164 PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2165 PDMTHREADSTATE enmState = pThread->enmState;
2166 if (enmState == PDMTHREADSTATE_SUSPENDED)
2167 {
2168 /*
2169 * The thread is suspended, we have to temporarily wake it up so it can
2170 * perform the task.
2171 * (We ASSUME not racing code here, both wrt thread state and ext commands.)
2172 */
2173 Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2174 /* Post the request. */
2175 pThis->svga.fFifoExtCommandWakeup = true;
2176 pThis->svga.pvFIFOExtCmdParam = pvParam;
2177 pThis->svga.u8FIFOExtCommand = uExtCmd;
2178 ASMMemoryFence(); /* paranoia^3 */
2179
2180 /* Resume the thread. */
2181 rc = PDMR3ThreadResume(pThread);
2182 AssertLogRelRC(rc);
2183 if (RT_SUCCESS(rc))
2184 {
2185 /* Wait. Take care in case the semaphore was already posted (same as below). */
2186 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2187 if ( rc == VINF_SUCCESS
2188 && pThis->svga.u8FIFOExtCommand == uExtCmd)
2189 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2190 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
2191 ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2192
2193 /* suspend the thread */
2194 pThis->svga.fFifoExtCommandWakeup = false;
2195 int rc2 = PDMR3ThreadSuspend(pThread);
2196 AssertLogRelRC(rc2);
2197 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2198 rc = rc2;
2199 }
2200 pThis->svga.fFifoExtCommandWakeup = false;
2201 pThis->svga.pvFIFOExtCmdParam = NULL;
2202 }
2203 else if (enmState == PDMTHREADSTATE_RUNNING)
2204 {
2205 /*
2206 * The thread is running, should only happen during reset and vmsvga3dsfc.
2207 * We ASSUME not racing code here, both wrt thread state and ext commands.
2208 */
2209 Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
2210 Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET || uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
2211
2212 /* Post the request. */
2213 pThis->svga.pvFIFOExtCmdParam = pvParam;
2214 pThis->svga.u8FIFOExtCommand = uExtCmd;
2215 ASMMemoryFence(); /* paranoia^2 */
2216 rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2217 AssertLogRelRC(rc);
2218
2219 /* Wait. Take care in case the semaphore was already posted (same as above). */
2220 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2221 if ( rc == VINF_SUCCESS
2222 && pThis->svga.u8FIFOExtCommand == uExtCmd)
2223 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
2224 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
2225 ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2226
2227 pThis->svga.pvFIFOExtCmdParam = NULL;
2228 }
2229 else
2230 {
2231 /*
2232 * Something is wrong with the thread!
2233 */
2234 AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
2235 rc = VERR_INVALID_STATE;
2236 }
2237 return rc;
2238}
2239
2240
2241/**
2242 * Marks the FIFO non-busy, notifying any waiting EMTs.
2243 *
2244 * @param pThis The VGA state.
2245 * @param pSVGAState Pointer to the ring-3 only SVGA state data.
2246 * @param offFifoMin The start byte offset of the command FIFO.
2247 */
2248static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
2249{
2250 ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
2251 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2252 vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
2253
2254 /* Wake up any waiting EMTs. */
2255 if (pSVGAState->cBusyDelayedEmts > 0)
2256 {
2257#ifdef VMSVGA_USE_EMT_HALT_CODE
2258 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
2259 VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
2260 if (idCpu != NIL_VMCPUID)
2261 {
2262 VMR3NotifyCpuDeviceReady(pVM, idCpu);
2263 while (idCpu-- > 0)
2264 if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
2265 VMR3NotifyCpuDeviceReady(pVM, idCpu);
2266 }
2267#else
2268 int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
2269 AssertRC(rc2);
2270#endif
2271 }
2272}
2273
2274/**
2275 * Reads (more) payload into the command buffer.
2276 *
2277 * @returns pbBounceBuf on success
2278 * @retval (void *)1 if the thread was requested to stop.
2279 * @retval NULL on FIFO error.
2280 *
2281 * @param cbPayloadReq The number of bytes of payload requested.
2282 * @param pFIFO The FIFO.
2283 * @param offCurrentCmd The FIFO byte offset of the current command.
2284 * @param offFifoMin The start byte offset of the command FIFO.
2285 * @param offFifoMax The end byte offset of the command FIFO.
2286 * @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
2287 * always sufficient size.
2288 * @param pcbAlreadyRead How much payload we've already read into the bounce
2289 * buffer. (We will NEVER re-read anything.)
2290 * @param pThread The calling PDM thread handle.
2291 * @param pThis The VGA state.
2292 * @param pSVGAState Pointer to the ring-3 only SVGA state data. For
2293 * statistics collection.
2294 */
2295static void *vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t volatile *pFIFO,
2296 uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
2297 uint8_t *pbBounceBuf, uint32_t *pcbAlreadyRead,
2298 PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
2299{
2300 Assert(pbBounceBuf);
2301 Assert(pcbAlreadyRead);
2302 Assert(offFifoMin < offFifoMax);
2303 Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
2304 Assert(offFifoMax <= VMSVGA_FIFO_SIZE);
2305
2306 /*
2307 * Check if the requested payload size has already been satisfied .
2308 * .
2309 * When called to read more, the caller is responsible for making sure the .
2310 * new command size (cbRequsted) never is smaller than what has already .
2311 * been read.
2312 */
2313 uint32_t cbAlreadyRead = *pcbAlreadyRead;
2314 if (cbPayloadReq <= cbAlreadyRead)
2315 {
2316 AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
2317 return pbBounceBuf;
2318 }
2319
2320 /*
2321 * Commands bigger than the fifo buffer are invalid.
2322 */
2323 uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
2324 AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
2325 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
2326 NULL);
2327
2328 /*
2329 * Move offCurrentCmd past the command dword.
2330 */
2331 offCurrentCmd += sizeof(uint32_t);
2332 if (offCurrentCmd >= offFifoMax)
2333 offCurrentCmd = offFifoMin;
2334
2335 /*
2336 * Do we have sufficient payload data available already?
2337 */
2338 uint32_t cbAfter, cbBefore;
2339 uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2340 if (offNextCmd > offCurrentCmd)
2341 {
2342 if (RT_LIKELY(offNextCmd < offFifoMax))
2343 cbAfter = offNextCmd - offCurrentCmd;
2344 else
2345 {
2346 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2347 LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2348 offNextCmd, offFifoMin, offFifoMax));
2349 cbAfter = offFifoMax - offCurrentCmd;
2350 }
2351 cbBefore = 0;
2352 }
2353 else
2354 {
2355 cbAfter = offFifoMax - offCurrentCmd;
2356 if (offNextCmd >= offFifoMin)
2357 cbBefore = offNextCmd - offFifoMin;
2358 else
2359 {
2360 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2361 LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2362 offNextCmd, offFifoMin, offFifoMax));
2363 cbBefore = 0;
2364 }
2365 }
2366 if (cbAfter + cbBefore < cbPayloadReq)
2367 {
2368 /*
2369 * Insufficient, must wait for it to arrive.
2370 */
2371/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
2372 STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
2373 for (uint32_t i = 0;; i++)
2374 {
2375 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2376 {
2377 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2378 return (void *)(uintptr_t)1;
2379 }
2380 Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
2381 cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
2382
2383 SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
2384
2385 offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2386 if (offNextCmd > offCurrentCmd)
2387 {
2388 cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
2389 cbBefore = 0;
2390 }
2391 else
2392 {
2393 cbAfter = offFifoMax - offCurrentCmd;
2394 cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
2395 }
2396
2397 if (cbAfter + cbBefore >= cbPayloadReq)
2398 break;
2399 }
2400 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2401 }
2402
2403 /*
2404 * Copy out the memory and update what pcbAlreadyRead points to.
2405 */
2406 if (cbAfter >= cbPayloadReq)
2407 memcpy(pbBounceBuf + cbAlreadyRead,
2408 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
2409 cbPayloadReq - cbAlreadyRead);
2410 else
2411 {
2412 LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
2413 if (cbAlreadyRead < cbAfter)
2414 {
2415 memcpy(pbBounceBuf + cbAlreadyRead,
2416 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
2417 cbAfter - cbAlreadyRead);
2418 cbAlreadyRead = cbAfter;
2419 }
2420 memcpy(pbBounceBuf + cbAlreadyRead,
2421 (uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
2422 cbPayloadReq - cbAlreadyRead);
2423 }
2424 *pcbAlreadyRead = cbPayloadReq;
2425 return pbBounceBuf;
2426}
2427
2428/* The async FIFO handling thread. */
2429static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2430{
2431 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
2432 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2433 int rc;
2434
2435 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2436 return VINF_SUCCESS;
2437
2438 /*
2439 * Special mode where we only execute an external command and the go back
2440 * to being suspended. Currently, all ext cmds ends up here, with the reset
2441 * one also being eligble for runtime execution further down as well.
2442 */
2443 if (pThis->svga.fFifoExtCommandWakeup)
2444 {
2445 vmsvgaR3FifoHandleExtCmd(pThis);
2446 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2447 if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
2448 SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
2449 else
2450 vmsvgaR3FifoHandleExtCmd(pThis);
2451 return VINF_SUCCESS;
2452 }
2453
2454
2455 /*
2456 * Signal the semaphore to make sure we don't wait for 250ms after a
2457 * suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
2458 */
2459 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2460
2461 /*
2462 * Allocate a bounce buffer for command we get from the FIFO.
2463 * (All code must return via the end of the function to free this buffer.)
2464 */
2465 uint8_t *pbBounceBuf = (uint8_t *)RTMemAllocZ(VMSVGA_FIFO_SIZE);
2466 AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
2467
2468 /*
2469 * Polling/sleep interval config.
2470 *
2471 * We wait for an a short interval if the guest has recently given us work
2472 * to do, but the interval increases the longer we're kept idle. With the
2473 * current parameters we'll be at a 64ms poll interval after 1 idle second,
2474 * at 90ms after 2 seconds, and reach the max 250ms interval after about
2475 * 16 seconds.
2476 */
2477 RTMSINTERVAL const cMsMinSleep = 16;
2478 RTMSINTERVAL const cMsIncSleep = 2;
2479 RTMSINTERVAL const cMsMaxSleep = 250;
2480 RTMSINTERVAL cMsSleep = cMsMaxSleep;
2481
2482 /*
2483 * The FIFO loop.
2484 */
2485 LogFlow(("vmsvgaFIFOLoop: started loop\n"));
2486 bool fBadOrDisabledFifo = false;
2487 uint32_t volatile * const pFIFO = pThis->svga.pFIFOR3;
2488 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2489 {
2490# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
2491 /*
2492 * Should service the run loop every so often.
2493 */
2494 if (pThis->svga.f3DEnabled)
2495 vmsvga3dCocoaServiceRunLoop();
2496# endif
2497
2498 /*
2499 * Unless there's already work pending, go to sleep for a short while.
2500 * (See polling/sleep interval config above.)
2501 */
2502 if ( fBadOrDisabledFifo
2503 || pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
2504 {
2505 rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
2506 AssertBreak(RT_SUCCESS(rc) || rc == VERR_TIMEOUT || rc == VERR_INTERRUPTED);
2507 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2508 {
2509 LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
2510 break;
2511 }
2512 }
2513 else
2514 rc = VINF_SUCCESS;
2515 fBadOrDisabledFifo = false;
2516 if (rc == VERR_TIMEOUT)
2517 {
2518 if (pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
2519 {
2520 cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
2521 continue;
2522 }
2523 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
2524
2525 Log(("vmsvgaFIFOLoop: timeout\n"));
2526 }
2527 else if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
2528 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
2529 cMsSleep = cMsMinSleep;
2530
2531 Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
2532 Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
2533 Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
2534
2535 /*
2536 * Handle external commands (currently only reset).
2537 */
2538 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
2539 {
2540 vmsvgaR3FifoHandleExtCmd(pThis);
2541 continue;
2542 }
2543
2544 /*
2545 * The device must be enabled and configured.
2546 */
2547 if ( !pThis->svga.fEnabled
2548 || !pThis->svga.fConfigured)
2549 {
2550 vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
2551 fBadOrDisabledFifo = true;
2552 continue;
2553 }
2554
2555 /*
2556 * Get and check the min/max values. We ASSUME that they will remain
2557 * unchanged while we process requests. A further ASSUMPTION is that
2558 * the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
2559 * we don't read it back while in the loop.
2560 */
2561 uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
2562 uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
2563 uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
2564 if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
2565 || offFifoMax <= offFifoMin
2566 || offFifoMax > VMSVGA_FIFO_SIZE
2567 || (offFifoMax & 3) != 0
2568 || (offFifoMin & 3) != 0
2569 || offCurrentCmd < offFifoMin
2570 || offCurrentCmd > offFifoMax))
2571 {
2572 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2573 LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
2574 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
2575 fBadOrDisabledFifo = true;
2576 continue;
2577 }
2578 if (RT_UNLIKELY(offCurrentCmd & 3))
2579 {
2580 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2581 LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
2582 offCurrentCmd = ~UINT32_C(3);
2583 }
2584
2585/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
2586 * Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
2587 *
2588 * Will break out of the switch on failure.
2589 * Will restart and quit the loop if the thread was requested to stop.
2590 *
2591 * @param a_PtrVar Request variable pointer.
2592 * @param a_Type Request typedef (not pointer) for casting.
2593 * @param a_cbPayloadReq How much payload to fetch.
2594 * @remarks Accesses a bunch of variables in the current scope!
2595 */
2596# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
2597 if (1) { \
2598 (a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
2599 pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
2600 if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
2601 } else do {} while (0)
2602/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
2603 * Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
2604 * buffer after figuring out the actual command size.
2605 *
2606 * Will break out of the switch on failure.
2607 *
2608 * @param a_PtrVar Request variable pointer.
2609 * @param a_Type Request typedef (not pointer) for casting.
2610 * @param a_cbPayloadReq How much payload to fetch.
2611 * @remarks Accesses a bunch of variables in the current scope!
2612 */
2613# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
2614 if (1) { \
2615 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
2616 } else do {} while (0)
2617
2618 /*
2619 * Mark the FIFO as busy.
2620 */
2621 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
2622 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2623 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
2624
2625 /*
2626 * Execute all queued FIFO commands.
2627 * Quit if pending external command or changes in the thread state.
2628 */
2629 bool fDone = false;
2630 while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
2631 && pThread->enmState == PDMTHREADSTATE_RUNNING)
2632 {
2633 uint32_t cbPayload = 0;
2634 uint32_t u32IrqStatus = 0;
2635
2636 Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
2637
2638 /* First check any pending actions. */
2639 if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
2640# ifdef VBOX_WITH_VMSVGA3D
2641 vmsvga3dChangeMode(pThis);
2642# else
2643 {/*nothing*/}
2644# endif
2645 /* Check for pending external commands (reset). */
2646 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
2647 break;
2648
2649 /*
2650 * Process the command.
2651 */
2652 SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
2653 LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
2654 offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
2655 switch (enmCmdId)
2656 {
2657 case SVGA_CMD_INVALID_CMD:
2658 /* Nothing to do. */
2659 break;
2660
2661 case SVGA_CMD_FENCE:
2662 {
2663 SVGAFifoCmdFence *pCmdFence;
2664 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
2665 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
2666 {
2667 Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
2668 pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
2669
2670 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
2671 {
2672 Log(("vmsvgaFIFOLoop: any fence irq\n"));
2673 u32IrqStatus |= SVGA_IRQFLAG_ANY_FENCE;
2674 }
2675 else
2676 if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
2677 && (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
2678 && pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
2679 {
2680 Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
2681 u32IrqStatus |= SVGA_IRQFLAG_FENCE_GOAL;
2682 }
2683 }
2684 else
2685 Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
2686 break;
2687 }
2688 case SVGA_CMD_UPDATE:
2689 case SVGA_CMD_UPDATE_VERBOSE:
2690 {
2691 SVGAFifoCmdUpdate *pUpdate;
2692 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
2693 Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
2694 vgaR3UpdateDisplay(pThis, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
2695 break;
2696 }
2697
2698 case SVGA_CMD_DEFINE_CURSOR:
2699 {
2700 /* Followed by bitmap data. */
2701 SVGAFifoCmdDefineCursor *pCursor;
2702 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
2703 AssertFailed(); /** @todo implement when necessary. */
2704 break;
2705 }
2706
2707 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
2708 {
2709 /* Followed by bitmap data. */
2710 uint32_t cbCursorShape, cbAndMask;
2711 uint8_t *pCursorCopy;
2712 uint32_t cbCmd;
2713
2714 SVGAFifoCmdDefineAlphaCursor *pCursor;
2715 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
2716
2717 Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
2718
2719 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
2720 AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
2721
2722 /* Refetch the bitmap data as well. */
2723 cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
2724 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
2725 /** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
2726
2727 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
2728 cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
2729 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
2730 cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
2731
2732 pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
2733 AssertBreak(pCursorCopy);
2734
2735 Log2(("Cursor data:\n%.*Rhxd\n", pCursor->width * pCursor->height * sizeof(uint32_t), pCursor+1));
2736
2737 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
2738 memset(pCursorCopy, 0xff, cbAndMask);
2739 /* Colour data */
2740 memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
2741
2742 rc = pThis->pDrv->pfnVBVAMousePointerShape (pThis->pDrv,
2743 true,
2744 true,
2745 pCursor->hotspotX,
2746 pCursor->hotspotY,
2747 pCursor->width,
2748 pCursor->height,
2749 pCursorCopy);
2750 AssertRC(rc);
2751
2752 if (pSVGAState->Cursor.fActive)
2753 RTMemFree(pSVGAState->Cursor.pData);
2754
2755 pSVGAState->Cursor.fActive = true;
2756 pSVGAState->Cursor.xHotspot = pCursor->hotspotX;
2757 pSVGAState->Cursor.yHotspot = pCursor->hotspotY;
2758 pSVGAState->Cursor.width = pCursor->width;
2759 pSVGAState->Cursor.height = pCursor->height;
2760 pSVGAState->Cursor.cbData = cbCursorShape;
2761 pSVGAState->Cursor.pData = pCursorCopy;
2762 break;
2763 }
2764
2765 case SVGA_CMD_ESCAPE:
2766 {
2767 /* Followed by nsize bytes of data. */
2768 SVGAFifoCmdEscape *pEscape;
2769 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
2770
2771 /* Refetch the command buffer with the variable data; undo size increase (ugly) */
2772 AssertBreak(pEscape->size < VMSVGA_FIFO_SIZE);
2773 uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
2774 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
2775
2776 if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
2777 {
2778 AssertBreak(pEscape->size >= sizeof(uint32_t));
2779 uint32_t cmd = *(uint32_t *)(pEscape + 1);
2780 Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
2781
2782 switch (cmd)
2783 {
2784 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
2785 {
2786 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pEscape + 1);
2787 AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
2788 uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
2789
2790 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
2791 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
2792 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
2793
2794 RT_NOREF_PV(pVideoCmd);
2795 break;
2796
2797 }
2798
2799 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
2800 {
2801 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pEscape + 1);
2802 AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
2803 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
2804 RT_NOREF_PV(pVideoCmd);
2805 break;
2806 }
2807 }
2808 }
2809 else
2810 Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
2811
2812 break;
2813 }
2814# ifdef VBOX_WITH_VMSVGA3D
2815 case SVGA_CMD_DEFINE_GMR2:
2816 {
2817 SVGAFifoCmdDefineGMR2 *pCmd;
2818 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
2819 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
2820
2821 /* Validate current GMR id. */
2822 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2823 AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
2824
2825 if (!pCmd->numPages)
2826 {
2827 vmsvgaGMRFree(pThis, pCmd->gmrId);
2828 }
2829 else
2830 {
2831 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2832 pGMR->cMaxPages = pCmd->numPages;
2833 }
2834 /* everything done in remap */
2835 break;
2836 }
2837
2838 case SVGA_CMD_REMAP_GMR2:
2839 {
2840 /* Followed by page descriptors or guest ptr. */
2841 SVGAFifoCmdRemapGMR2 *pCmd;
2842 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
2843 uint32_t cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
2844 uint32_t cbCmd;
2845 uint64_t *paNewPage64 = NULL;
2846
2847 Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
2848 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2849
2850 /* Calculate the size of what comes after next and fetch it. */
2851 cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
2852 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
2853 cbCmd += sizeof(SVGAGuestPtr);
2854 else
2855 if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
2856 {
2857 cbCmd += cbPageDesc;
2858 pCmd->numPages = 1;
2859 }
2860 else
2861 {
2862 AssertBreak(pCmd->numPages <= VMSVGA_FIFO_SIZE);
2863 cbCmd += cbPageDesc * pCmd->numPages;
2864 }
2865 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
2866
2867 /* Validate current GMR id. */
2868 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2869 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2870 AssertBreak(pCmd->offsetPages + pCmd->numPages <= pGMR->cMaxPages);
2871 AssertBreak(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
2872
2873 /* Save the old page descriptors as an array of page addresses (>> PAGE_SHIFT) */
2874 if (pGMR->paDesc)
2875 {
2876 uint32_t idxPage = 0;
2877 paNewPage64 = (uint64_t *)RTMemAllocZ(pGMR->cMaxPages * sizeof(uint64_t));
2878 AssertBreak(paNewPage64);
2879
2880 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2881 {
2882 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
2883 {
2884 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * PAGE_SIZE) >> PAGE_SHIFT;
2885 }
2886 }
2887 AssertBreak(idxPage == pGMR->cbTotal >> PAGE_SHIFT);
2888 }
2889
2890 /* Free the old GMR if present. */
2891 if (pGMR->paDesc)
2892 RTMemFree(pGMR->paDesc);
2893
2894 /* Allocate the maximum amount possible (everything non-continuous) */
2895 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->cMaxPages * sizeof(VMSVGAGMRDESCRIPTOR));
2896 AssertBreak(pGMR->paDesc);
2897
2898 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
2899 {
2900 /** @todo */
2901 AssertFailed();
2902 }
2903 else
2904 {
2905 uint32_t *pPage32 = (uint32_t *)(pCmd + 1);
2906 uint64_t *pPage64 = (uint64_t *)(pCmd + 1);
2907 uint32_t iDescriptor = 0;
2908 RTGCPHYS GCPhys;
2909 bool fGCPhys64 = !!(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
2910
2911 if (paNewPage64)
2912 {
2913 /* Overwrite the old page array with the new page values. */
2914 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
2915 {
2916 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
2917 paNewPage64[i] = pPage64[i - pCmd->offsetPages];
2918 else
2919 paNewPage64[i] = pPage32[i - pCmd->offsetPages];
2920 }
2921 /* Use the updated page array instead of the command data. */
2922 fGCPhys64 = true;
2923 pPage64 = paNewPage64;
2924 pCmd->numPages = pGMR->cbTotal >> PAGE_SHIFT;
2925 }
2926
2927 if (fGCPhys64)
2928 GCPhys = (pPage64[0] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
2929 else
2930 GCPhys = (RTGCPHYS)pPage32[0] << PAGE_SHIFT;
2931
2932 pGMR->paDesc[0].GCPhys = GCPhys;
2933 pGMR->paDesc[0].numPages = 1;
2934 pGMR->cbTotal = PAGE_SIZE;
2935
2936 for (uint32_t i = 1; i < pCmd->numPages; i++)
2937 {
2938 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
2939 GCPhys = (pPage64[i] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
2940 else
2941 GCPhys = (RTGCPHYS)pPage32[i] << PAGE_SHIFT;
2942
2943 /* Continuous physical memory? */
2944 if (GCPhys == pGMR->paDesc[iDescriptor].GCPhys + pGMR->paDesc[iDescriptor].numPages * PAGE_SIZE)
2945 {
2946 Assert(pGMR->paDesc[iDescriptor].numPages);
2947 pGMR->paDesc[iDescriptor].numPages++;
2948 LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
2949 }
2950 else
2951 {
2952 iDescriptor++;
2953 pGMR->paDesc[iDescriptor].GCPhys = GCPhys;
2954 pGMR->paDesc[iDescriptor].numPages = 1;
2955 LogFlow(("Page %x GCPhys=%RGp\n", i, pGMR->paDesc[iDescriptor].GCPhys));
2956 }
2957
2958 pGMR->cbTotal += PAGE_SIZE;
2959 }
2960 LogFlow(("Nr of descriptors %x\n", iDescriptor + 1));
2961 pGMR->numDescriptors = iDescriptor + 1;
2962 }
2963
2964 if (paNewPage64)
2965 RTMemFree(paNewPage64);
2966
2967# ifdef DEBUG_GMR_ACCESS
2968 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
2969# endif
2970 break;
2971 }
2972# endif // VBOX_WITH_VMSVGA3D
2973 case SVGA_CMD_DEFINE_SCREEN:
2974 {
2975 /* Note! The size of this command is specified by the guest and depends on capabilities. */
2976 Assert(!(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT));
2977 SVGAFifoCmdDefineScreen *pCmd;
2978 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
2979 RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.structSize));
2980 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
2981
2982 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d)\n", pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y));
2983 if (pCmd->screen.flags & SVGA_SCREEN_HAS_ROOT)
2984 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_HAS_ROOT\n"));
2985 if (pCmd->screen.flags & SVGA_SCREEN_IS_PRIMARY)
2986 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_IS_PRIMARY\n"));
2987 if (pCmd->screen.flags & SVGA_SCREEN_FULLSCREEN_HINT)
2988 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_FULLSCREEN_HINT\n"));
2989 if (pCmd->screen.flags & SVGA_SCREEN_DEACTIVATE )
2990 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_DEACTIVATE \n"));
2991 if (pCmd->screen.flags & SVGA_SCREEN_BLANKING)
2992 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_BLANKING\n"));
2993
2994 /** @todo multi monitor support and screen object capabilities. */
2995 pThis->svga.uWidth = pCmd->screen.size.width;
2996 pThis->svga.uHeight = pCmd->screen.size.height;
2997 vmsvgaChangeMode(pThis);
2998 break;
2999 }
3000
3001 case SVGA_CMD_DESTROY_SCREEN:
3002 {
3003 SVGAFifoCmdDestroyScreen *pCmd;
3004 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
3005
3006 Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
3007 break;
3008 }
3009# ifdef VBOX_WITH_VMSVGA3D
3010 case SVGA_CMD_DEFINE_GMRFB:
3011 {
3012 SVGAFifoCmdDefineGMRFB *pCmd;
3013 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
3014
3015 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
3016 pSVGAState->GMRFB.ptr = pCmd->ptr;
3017 pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
3018 pSVGAState->GMRFB.format = pCmd->format;
3019 break;
3020 }
3021
3022 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3023 {
3024 uint32_t width, height;
3025 SVGAFifoCmdBlitGMRFBToScreen *pCmd;
3026 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
3027
3028 Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
3029
3030 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
3031 AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pThis->svga.uBpp);
3032 AssertBreak(pCmd->destScreenId == 0);
3033
3034 if (pCmd->destRect.left < 0)
3035 pCmd->destRect.left = 0;
3036 if (pCmd->destRect.top < 0)
3037 pCmd->destRect.top = 0;
3038 if (pCmd->destRect.right < 0)
3039 pCmd->destRect.right = 0;
3040 if (pCmd->destRect.bottom < 0)
3041 pCmd->destRect.bottom = 0;
3042
3043 width = pCmd->destRect.right - pCmd->destRect.left;
3044 height = pCmd->destRect.bottom - pCmd->destRect.top;
3045
3046 if ( width == 0
3047 || height == 0)
3048 break; /* Nothing to do. */
3049
3050 /* Clip to screen dimensions. */
3051 if (width > pThis->svga.uWidth)
3052 width = pThis->svga.uWidth;
3053 if (height > pThis->svga.uHeight)
3054 height = pThis->svga.uHeight;
3055
3056 unsigned offsetSource = (pCmd->srcOrigin.x * pSVGAState->GMRFB.format.s.bitsPerPixel) / 8 + pSVGAState->GMRFB.bytesPerLine * pCmd->srcOrigin.y;
3057 unsigned offsetDest = (pCmd->destRect.left * RT_ALIGN(pThis->svga.uBpp, 8)) / 8 + pThis->svga.cbScanline * pCmd->destRect.top;
3058 unsigned cbCopyWidth = (width * RT_ALIGN(pThis->svga.uBpp, 8)) / 8;
3059
3060 AssertBreak(offsetDest < pThis->vram_size);
3061
3062 rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM, pThis->CTX_SUFF(vram_ptr) + offsetDest, pThis->svga.cbScanline, pSVGAState->GMRFB.ptr, offsetSource, pSVGAState->GMRFB.bytesPerLine, cbCopyWidth, height);
3063 AssertRC(rc);
3064 vgaR3UpdateDisplay(pThis, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right - pCmd->destRect.left, pCmd->destRect.bottom - pCmd->destRect.top);
3065 break;
3066 }
3067
3068 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3069 {
3070 SVGAFifoCmdBlitScreenToGMRFB *pCmd;
3071 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
3072
3073 /* Note! This can fetch 3d render results as well!! */
3074 Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n", pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
3075 AssertFailed();
3076 break;
3077 }
3078# endif // VBOX_WITH_VMSVGA3D
3079 case SVGA_CMD_ANNOTATION_FILL:
3080 {
3081 SVGAFifoCmdAnnotationFill *pCmd;
3082 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
3083
3084 Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
3085 pSVGAState->colorAnnotation = pCmd->color;
3086 break;
3087 }
3088
3089 case SVGA_CMD_ANNOTATION_COPY:
3090 {
3091 SVGAFifoCmdAnnotationCopy *pCmd;
3092 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
3093
3094 Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
3095 AssertFailed();
3096 break;
3097 }
3098
3099 /** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
3100
3101 default:
3102# ifdef VBOX_WITH_VMSVGA3D
3103 if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
3104 && (int)enmCmdId < SVGA_3D_CMD_MAX)
3105 {
3106 /* All 3d commands start with a common header, which defines the size of the command. */
3107 SVGA3dCmdHeader *pHdr;
3108 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
3109 AssertBreak(pHdr->size < VMSVGA_FIFO_SIZE);
3110 uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
3111 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
3112
3113/**
3114 * Check that the 3D command has at least a_cbMin of payload bytes after the
3115 * header. Will break out of the switch if it doesn't.
3116 */
3117# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3118 AssertMsgBreak((a_cbMin) <= pHdr->size, ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin)))
3119 switch ((int)enmCmdId)
3120 {
3121 case SVGA_3D_CMD_SURFACE_DEFINE:
3122 {
3123 uint32_t cMipLevels;
3124 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)(pHdr + 1);
3125 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3126
3127 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3128 rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
3129 SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
3130# ifdef DEBUG_GMR_ACCESS
3131 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
3132# endif
3133 break;
3134 }
3135
3136 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3137 {
3138 uint32_t cMipLevels;
3139 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)(pHdr + 1);
3140 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3141
3142 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3143 rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
3144 pCmd->multisampleCount, pCmd->autogenFilter,
3145 cMipLevels, (SVGA3dSize *)(pCmd + 1));
3146 break;
3147 }
3148
3149 case SVGA_3D_CMD_SURFACE_DESTROY:
3150 {
3151 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)(pHdr + 1);
3152 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3153 rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
3154 break;
3155 }
3156
3157 case SVGA_3D_CMD_SURFACE_COPY:
3158 {
3159 uint32_t cCopyBoxes;
3160 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)(pHdr + 1);
3161 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3162
3163 cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3164 rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3165 break;
3166 }
3167
3168 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3169 {
3170 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)(pHdr + 1);
3171 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3172
3173 rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
3174 break;
3175 }
3176
3177 case SVGA_3D_CMD_SURFACE_DMA:
3178 {
3179 uint32_t cCopyBoxes;
3180 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)(pHdr + 1);
3181 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3182
3183 cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3184 STAM_PROFILE_START(&pSVGAState->StatR3CmdSurfaceDMA, a);
3185 rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3186 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdSurfaceDMA, a);
3187 break;
3188 }
3189
3190 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3191 {
3192 uint32_t cRects;
3193 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)(pHdr + 1);
3194 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3195
3196 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3197 rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3198 break;
3199 }
3200
3201 case SVGA_3D_CMD_CONTEXT_DEFINE:
3202 {
3203 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)(pHdr + 1);
3204 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3205
3206 rc = vmsvga3dContextDefine(pThis, pCmd->cid);
3207 break;
3208 }
3209
3210 case SVGA_3D_CMD_CONTEXT_DESTROY:
3211 {
3212 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)(pHdr + 1);
3213 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3214
3215 rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
3216 break;
3217 }
3218
3219 case SVGA_3D_CMD_SETTRANSFORM:
3220 {
3221 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)(pHdr + 1);
3222 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3223
3224 rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
3225 break;
3226 }
3227
3228 case SVGA_3D_CMD_SETZRANGE:
3229 {
3230 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)(pHdr + 1);
3231 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3232
3233 rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
3234 break;
3235 }
3236
3237 case SVGA_3D_CMD_SETRENDERSTATE:
3238 {
3239 uint32_t cRenderStates;
3240 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)(pHdr + 1);
3241 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3242
3243 cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3244 rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3245 break;
3246 }
3247
3248 case SVGA_3D_CMD_SETRENDERTARGET:
3249 {
3250 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)(pHdr + 1);
3251 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3252
3253 rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
3254 break;
3255 }
3256
3257 case SVGA_3D_CMD_SETTEXTURESTATE:
3258 {
3259 uint32_t cTextureStates;
3260 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)(pHdr + 1);
3261 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3262
3263 cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3264 rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3265 break;
3266 }
3267
3268 case SVGA_3D_CMD_SETMATERIAL:
3269 {
3270 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)(pHdr + 1);
3271 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3272
3273 rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
3274 break;
3275 }
3276
3277 case SVGA_3D_CMD_SETLIGHTDATA:
3278 {
3279 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)(pHdr + 1);
3280 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3281
3282 rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
3283 break;
3284 }
3285
3286 case SVGA_3D_CMD_SETLIGHTENABLED:
3287 {
3288 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)(pHdr + 1);
3289 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3290
3291 rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
3292 break;
3293 }
3294
3295 case SVGA_3D_CMD_SETVIEWPORT:
3296 {
3297 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)(pHdr + 1);
3298 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3299
3300 rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
3301 break;
3302 }
3303
3304 case SVGA_3D_CMD_SETCLIPPLANE:
3305 {
3306 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)(pHdr + 1);
3307 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3308
3309 rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
3310 break;
3311 }
3312
3313 case SVGA_3D_CMD_CLEAR:
3314 {
3315 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)(pHdr + 1);
3316 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3317 uint32_t cRects;
3318
3319 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
3320 rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
3321 break;
3322 }
3323
3324 case SVGA_3D_CMD_PRESENT:
3325 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
3326 {
3327 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)(pHdr + 1);
3328 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3329 uint32_t cRects;
3330
3331 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
3332
3333 STAM_PROFILE_START(&pSVGAState->StatR3CmdPresent, a);
3334 rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
3335 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdPresent, a);
3336 break;
3337 }
3338
3339 case SVGA_3D_CMD_SHADER_DEFINE:
3340 {
3341 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)(pHdr + 1);
3342 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3343 uint32_t cbData;
3344
3345 cbData = (pHdr->size - sizeof(*pCmd));
3346 rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
3347 break;
3348 }
3349
3350 case SVGA_3D_CMD_SHADER_DESTROY:
3351 {
3352 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)(pHdr + 1);
3353 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3354
3355 rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
3356 break;
3357 }
3358
3359 case SVGA_3D_CMD_SET_SHADER:
3360 {
3361 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)(pHdr + 1);
3362 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3363
3364 rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
3365 break;
3366 }
3367
3368 case SVGA_3D_CMD_SET_SHADER_CONST:
3369 {
3370 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)(pHdr + 1);
3371 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3372
3373 uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
3374 rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
3375 break;
3376 }
3377
3378 case SVGA_3D_CMD_DRAW_PRIMITIVES:
3379 {
3380 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)(pHdr + 1);
3381 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3382 uint32_t cVertexDivisor;
3383
3384 cVertexDivisor = (pHdr->size - sizeof(*pCmd) - sizeof(SVGA3dVertexDecl) * pCmd->numVertexDecls - sizeof(SVGA3dPrimitiveRange) * pCmd->numRanges);
3385 Assert(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
3386 Assert(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
3387 Assert(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls);
3388
3389 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
3390 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *) (&pVertexDecl[pCmd->numVertexDecls]);
3391 SVGA3dVertexDivisor *pVertexDivisor = (cVertexDivisor) ? (SVGA3dVertexDivisor *)(&pNumRange[pCmd->numRanges]) : NULL;
3392
3393 STAM_PROFILE_START(&pSVGAState->StatR3CmdDrawPrimitive, a);
3394 rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges, pNumRange, cVertexDivisor, pVertexDivisor);
3395 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdDrawPrimitive, a);
3396 break;
3397 }
3398
3399 case SVGA_3D_CMD_SETSCISSORRECT:
3400 {
3401 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)(pHdr + 1);
3402 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3403
3404 rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
3405 break;
3406 }
3407
3408 case SVGA_3D_CMD_BEGIN_QUERY:
3409 {
3410 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)(pHdr + 1);
3411 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3412
3413 rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
3414 break;
3415 }
3416
3417 case SVGA_3D_CMD_END_QUERY:
3418 {
3419 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)(pHdr + 1);
3420 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3421
3422 rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
3423 break;
3424 }
3425
3426 case SVGA_3D_CMD_WAIT_FOR_QUERY:
3427 {
3428 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)(pHdr + 1);
3429 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3430
3431 rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
3432 break;
3433 }
3434
3435 case SVGA_3D_CMD_GENERATE_MIPMAPS:
3436 {
3437 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)(pHdr + 1);
3438 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3439
3440 rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
3441 break;
3442 }
3443
3444 case SVGA_3D_CMD_ACTIVATE_SURFACE:
3445 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
3446 /* context id + surface id? */
3447 break;
3448
3449 default:
3450 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3451 AssertFailed();
3452 break;
3453 }
3454 }
3455 else
3456# endif // VBOX_WITH_VMSVGA3D
3457 {
3458 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3459 AssertFailed();
3460 }
3461 }
3462
3463 /* Go to the next slot */
3464 Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
3465 offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
3466 if (offCurrentCmd >= offFifoMax)
3467 {
3468 offCurrentCmd -= offFifoMax - offFifoMin;
3469 Assert(offCurrentCmd >= offFifoMin);
3470 Assert(offCurrentCmd < offFifoMax);
3471 }
3472 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
3473 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
3474
3475 /*
3476 * Raise IRQ if required. Must enter the critical section here
3477 * before making final decisions here, otherwise cubebench and
3478 * others may end up waiting forever.
3479 */
3480 if ( u32IrqStatus
3481 || (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
3482 {
3483 int rc2 = PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
3484 AssertRC(rc2);
3485
3486 /* FIFO progress might trigger an interrupt. */
3487 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
3488 {
3489 Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
3490 u32IrqStatus |= SVGA_IRQFLAG_FIFO_PROGRESS;
3491 }
3492
3493 /* Unmasked IRQ pending? */
3494 if (pThis->svga.u32IrqMask & u32IrqStatus)
3495 {
3496 Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
3497 ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
3498 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
3499 }
3500
3501 PDMCritSectLeave(&pThis->CritSect);
3502 }
3503 }
3504
3505 /* If really done, clear the busy flag. */
3506 if (fDone)
3507 {
3508 Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
3509 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3510 }
3511 }
3512
3513 /*
3514 * Free the bounce buffer. (There are no returns above!)
3515 */
3516 RTMemFree(pbBounceBuf);
3517
3518 return VINF_SUCCESS;
3519}
3520
3521/**
3522 * Free the specified GMR
3523 *
3524 * @param pThis VGA device instance data.
3525 * @param idGMR GMR id
3526 */
3527void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
3528{
3529 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3530
3531 /* Free the old descriptor if present. */
3532 if (pSVGAState->aGMR[idGMR].numDescriptors)
3533 {
3534 PGMR pGMR = &pSVGAState->aGMR[idGMR];
3535# ifdef DEBUG_GMR_ACCESS
3536 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
3537# endif
3538
3539 Assert(pGMR->paDesc);
3540 RTMemFree(pGMR->paDesc);
3541 pGMR->paDesc = NULL;
3542 pGMR->numDescriptors = 0;
3543 pGMR->cbTotal = 0;
3544 pGMR->cMaxPages = 0;
3545 }
3546 Assert(!pSVGAState->aGMR[idGMR].cbTotal);
3547}
3548
3549/**
3550 * Copy from a GMR to host memory or vice versa
3551 *
3552 * @returns VBox status code.
3553 * @param pThis VGA device instance data.
3554 * @param enmTransferType Transfer type (read/write)
3555 * @param pbDst Host destination pointer
3556 * @param cbDestPitch Destination buffer pitch
3557 * @param src GMR description
3558 * @param offSrc Source buffer offset
3559 * @param cbSrcPitch Source buffer pitch
3560 * @param cbWidth Source width in bytes
3561 * @param cHeight Source height
3562 */
3563int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType, uint8_t *pbDst, int32_t cbDestPitch,
3564 SVGAGuestPtr src, uint32_t offSrc, int32_t cbSrcPitch, uint32_t cbWidth, uint32_t cHeight)
3565{
3566 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3567 PGMR pGMR;
3568 int rc;
3569 PVMSVGAGMRDESCRIPTOR pDesc;
3570 unsigned offDesc = 0;
3571
3572 Log(("vmsvgaGMRTransfer: gmr=%x offset=%x pitch=%d cbWidth=%d cHeight=%d; src offset=%d src pitch=%d\n",
3573 src.gmrId, src.offset, cbDestPitch, cbWidth, cHeight, offSrc, cbSrcPitch));
3574 Assert(cbWidth && cHeight);
3575
3576 /* Shortcut for the framebuffer. */
3577 if (src.gmrId == SVGA_GMR_FRAMEBUFFER)
3578 {
3579 offSrc += src.offset;
3580 AssertMsgReturn(src.offset < pThis->vram_size,
3581 ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x vram_size=%#x\n",
3582 src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
3583 VERR_INVALID_PARAMETER);
3584 AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pThis->vram_size,
3585 ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x vram_size=%#x\n",
3586 src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
3587 VERR_INVALID_PARAMETER);
3588
3589 uint8_t *pSrc = pThis->CTX_SUFF(vram_ptr) + offSrc;
3590
3591 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
3592 {
3593 /* switch src & dest */
3594 uint8_t *pTemp = pbDst;
3595 int32_t cbTempPitch = cbDestPitch;
3596
3597 pbDst = pSrc;
3598 pSrc = pTemp;
3599
3600 cbDestPitch = cbSrcPitch;
3601 cbSrcPitch = cbTempPitch;
3602 }
3603
3604 if ( pThis->svga.cbScanline == (uint32_t)cbDestPitch
3605 && cbWidth == (uint32_t)cbDestPitch
3606 && cbSrcPitch == cbDestPitch)
3607 {
3608 memcpy(pbDst, pSrc, cbWidth * cHeight);
3609 }
3610 else
3611 {
3612 for(uint32_t i = 0; i < cHeight; i++)
3613 {
3614 memcpy(pbDst, pSrc, cbWidth);
3615
3616 pbDst += cbDestPitch;
3617 pSrc += cbSrcPitch;
3618 }
3619 }
3620 return VINF_SUCCESS;
3621 }
3622
3623 AssertReturn(src.gmrId < VMSVGA_MAX_GMR_IDS, VERR_INVALID_PARAMETER);
3624 pGMR = &pSVGAState->aGMR[src.gmrId];
3625 pDesc = pGMR->paDesc;
3626
3627 offSrc += src.offset;
3628 AssertMsgReturn(src.offset < pGMR->cbTotal,
3629 ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
3630 src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
3631 VERR_INVALID_PARAMETER);
3632 AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pGMR->cbTotal,
3633 ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
3634 src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
3635 VERR_INVALID_PARAMETER);
3636
3637 for (uint32_t i = 0; i < cHeight; i++)
3638 {
3639 uint32_t cbCurrentWidth = cbWidth;
3640 uint32_t offCurrent = offSrc;
3641 uint8_t *pCurrentDest = pbDst;
3642
3643 /* Find the right descriptor */
3644 while (offDesc + pDesc->numPages * PAGE_SIZE <= offCurrent)
3645 {
3646 offDesc += pDesc->numPages * PAGE_SIZE;
3647 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
3648 pDesc++;
3649 }
3650
3651 while (cbCurrentWidth)
3652 {
3653 uint32_t cbToCopy;
3654
3655 if (offCurrent + cbCurrentWidth <= offDesc + pDesc->numPages * PAGE_SIZE)
3656 {
3657 cbToCopy = cbCurrentWidth;
3658 }
3659 else
3660 {
3661 cbToCopy = (offDesc + pDesc->numPages * PAGE_SIZE - offCurrent);
3662 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
3663 }
3664
3665 LogFlow(("vmsvgaGMRTransfer: %s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", pDesc->GCPhys + offCurrent - offDesc));
3666
3667 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
3668 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
3669 else
3670 rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
3671 AssertRCBreak(rc);
3672
3673 cbCurrentWidth -= cbToCopy;
3674 offCurrent += cbToCopy;
3675 pCurrentDest += cbToCopy;
3676
3677 /* Go to the next descriptor if there's anything left. */
3678 if (cbCurrentWidth)
3679 {
3680 offDesc += pDesc->numPages * PAGE_SIZE;
3681 pDesc++;
3682 }
3683 }
3684
3685 offSrc += cbSrcPitch;
3686 pbDst += cbDestPitch;
3687 }
3688
3689 return VINF_SUCCESS;
3690}
3691
3692/**
3693 * Unblock the FIFO I/O thread so it can respond to a state change.
3694 *
3695 * @returns VBox status code.
3696 * @param pDevIns The VGA device instance.
3697 * @param pThread The send thread.
3698 */
3699static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3700{
3701 RT_NOREF(pDevIns);
3702 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3703 Log(("vmsvgaFIFOLoopWakeUp\n"));
3704 return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3705}
3706
3707/**
3708 * Enables or disables dirty page tracking for the framebuffer
3709 *
3710 * @param pThis VGA device instance data.
3711 * @param fTraces Enable/disable traces
3712 */
3713static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
3714{
3715 if ( (!pThis->svga.fConfigured || !pThis->svga.fEnabled)
3716 && !fTraces)
3717 {
3718 //Assert(pThis->svga.fTraces);
3719 Log(("vmsvgaSetTraces: *not* allowed to disable dirty page tracking when the device is in legacy mode.\n"));
3720 return;
3721 }
3722
3723 pThis->svga.fTraces = fTraces;
3724 if (pThis->svga.fTraces)
3725 {
3726 unsigned cbFrameBuffer = pThis->vram_size;
3727
3728 Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
3729 if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
3730 {
3731#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
3732 Assert(pThis->svga.cbScanline);
3733#endif
3734 /* Hardware enabled; return real framebuffer size .*/
3735 cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
3736 cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
3737 }
3738
3739 if (!pThis->svga.fVRAMTracking)
3740 {
3741 Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
3742 vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
3743 pThis->svga.fVRAMTracking = true;
3744 }
3745 }
3746 else
3747 {
3748 if (pThis->svga.fVRAMTracking)
3749 {
3750 Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
3751 vgaR3UnregisterVRAMHandler(pThis);
3752 pThis->svga.fVRAMTracking = false;
3753 }
3754 }
3755}
3756
3757/**
3758 * @callback_method_impl{FNPCIIOREGIONMAP}
3759 */
3760DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3761 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
3762{
3763 int rc;
3764 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3765
3766 Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
3767 if (enmType == PCI_ADDRESS_SPACE_IO)
3768 {
3769 AssertReturn(iRegion == 0, VERR_INTERNAL_ERROR);
3770 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3771 vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr */, NULL /* InStr */, "VMSVGA");
3772 if (RT_FAILURE(rc))
3773 return rc;
3774 if (pThis->fR0Enabled)
3775 {
3776 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3777 "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
3778 if (RT_FAILURE(rc))
3779 return rc;
3780 }
3781 if (pThis->fGCEnabled)
3782 {
3783 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3784 "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
3785 if (RT_FAILURE(rc))
3786 return rc;
3787 }
3788
3789 pThis->svga.BasePort = GCPhysAddress;
3790 Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
3791 }
3792 else
3793 {
3794 AssertReturn(iRegion == 2 && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
3795 if (GCPhysAddress != NIL_RTGCPHYS)
3796 {
3797 /*
3798 * Mapping the FIFO RAM.
3799 */
3800 rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
3801 AssertRC(rc);
3802
3803# ifdef DEBUG_FIFO_ACCESS
3804 if (RT_SUCCESS(rc))
3805 {
3806 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress, GCPhysAddress + (VMSVGA_FIFO_SIZE - 1),
3807 pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
3808 "VMSVGA FIFO");
3809 AssertRC(rc);
3810 }
3811# endif
3812 if (RT_SUCCESS(rc))
3813 {
3814 pThis->svga.GCPhysFIFO = GCPhysAddress;
3815 Log(("vmsvgaR3IORegionMap: FIFO address = %RGp\n", GCPhysAddress));
3816 }
3817 }
3818 else
3819 {
3820 Assert(pThis->svga.GCPhysFIFO);
3821# ifdef DEBUG_FIFO_ACCESS
3822 rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3823 AssertRC(rc);
3824# endif
3825 pThis->svga.GCPhysFIFO = 0;
3826 }
3827
3828 }
3829 return VINF_SUCCESS;
3830}
3831
3832# ifdef VBOX_WITH_VMSVGA3D
3833
3834/**
3835 * Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
3836 * surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
3837 *
3838 * @param pThis The VGA device instance data.
3839 * @param sid Either UINT32_MAX or the ID of a specific
3840 * surface. If UINT32_MAX is used, all surfaces
3841 * are processed.
3842 */
3843void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
3844{
3845 vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
3846 sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
3847}
3848
3849
3850/**
3851 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
3852 */
3853DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3854{
3855 /* There might be a specific context ID at the start of the
3856 arguments, if not show all contexts. */
3857 uint32_t cid = UINT32_MAX;
3858 if (pszArgs)
3859 pszArgs = RTStrStripL(pszArgs);
3860 if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
3861 cid = RTStrToUInt32(pszArgs);
3862
3863 /* Verbose or terse display, we default to verbose. */
3864 bool fVerbose = true;
3865 if (RTStrIStr(pszArgs, "terse"))
3866 fVerbose = false;
3867
3868 /* The size of the ascii art (x direction, y is 3/4 of x). */
3869 uint32_t cxAscii = 80;
3870 if (RTStrIStr(pszArgs, "gigantic"))
3871 cxAscii = 300;
3872 else if (RTStrIStr(pszArgs, "huge"))
3873 cxAscii = 180;
3874 else if (RTStrIStr(pszArgs, "big"))
3875 cxAscii = 132;
3876 else if (RTStrIStr(pszArgs, "normal"))
3877 cxAscii = 80;
3878 else if (RTStrIStr(pszArgs, "medium"))
3879 cxAscii = 64;
3880 else if (RTStrIStr(pszArgs, "small"))
3881 cxAscii = 48;
3882 else if (RTStrIStr(pszArgs, "tiny"))
3883 cxAscii = 24;
3884
3885 /* Y invert the image when producing the ASCII art. */
3886 bool fInvY = false;
3887 if (RTStrIStr(pszArgs, "invy"))
3888 fInvY = true;
3889
3890 vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, cid, fVerbose, cxAscii, fInvY);
3891}
3892
3893
3894/**
3895 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
3896 */
3897DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3898{
3899 /* There might be a specific surface ID at the start of the
3900 arguments, if not show all contexts. */
3901 uint32_t sid = UINT32_MAX;
3902 if (pszArgs)
3903 pszArgs = RTStrStripL(pszArgs);
3904 if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
3905 sid = RTStrToUInt32(pszArgs);
3906
3907 /* Verbose or terse display, we default to verbose. */
3908 bool fVerbose = true;
3909 if (RTStrIStr(pszArgs, "terse"))
3910 fVerbose = false;
3911
3912 vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
3913}
3914
3915# endif /* VBOX_WITH_VMSVGA3D */
3916
3917/**
3918 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
3919 */
3920static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3921{
3922 RT_NOREF(pszArgs);
3923 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3924 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3925
3926 pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
3927 pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
3928 pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
3929 pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
3930 pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
3931 pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
3932 pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
3933 pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
3934 pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
3935 pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
3936 pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
3937 pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
3938 pHlp->pfnPrintf(pHlp, "Pitch lock: %#x\n", pThis->svga.u32PitchLock);
3939 pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
3940 pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
3941 pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
3942 pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
3943 pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
3944 pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
3945 pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
3946 pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
3947 pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
3948
3949 pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
3950 pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
3951 pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
3952 pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
3953
3954# ifdef VBOX_WITH_VMSVGA3D
3955 pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
3956 pHlp->pfnPrintf(pHlp, "Host windows ID: %#RX64\n", pThis->svga.u64HostWindowId);
3957 if (pThis->svga.u64HostWindowId != 0)
3958 vmsvga3dInfoHostWindow(pHlp, pThis->svga.u64HostWindowId);
3959# endif
3960}
3961
3962
3963/**
3964 * @copydoc FNSSMDEVLOADEXEC
3965 */
3966int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3967{
3968 RT_NOREF(uVersion, uPass);
3969 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3970 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3971 int rc;
3972
3973 /* Load our part of the VGAState */
3974 rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
3975 AssertRCReturn(rc, rc);
3976
3977 /* Load the framebuffer backup. */
3978 rc = SSMR3GetMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
3979 AssertRCReturn(rc, rc);
3980
3981 /* Load the VMSVGA state. */
3982 rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
3983 AssertRCReturn(rc, rc);
3984
3985 /* Load the active cursor bitmaps. */
3986 if (pSVGAState->Cursor.fActive)
3987 {
3988 pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
3989 AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
3990
3991 rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
3992 AssertRCReturn(rc, rc);
3993 }
3994
3995 /* Load the GMR state */
3996 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
3997 {
3998 PGMR pGMR = &pSVGAState->aGMR[i];
3999
4000 rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
4001 AssertRCReturn(rc, rc);
4002
4003 if (pGMR->numDescriptors)
4004 {
4005 /* Allocate the maximum amount possible (everything non-continuous) */
4006 Assert(pGMR->cMaxPages || pGMR->cbTotal);
4007 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ((pGMR->cMaxPages) ? pGMR->cMaxPages : (pGMR->cbTotal >> PAGE_SHIFT) * sizeof(VMSVGAGMRDESCRIPTOR));
4008 AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
4009
4010 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
4011 {
4012 rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
4013 AssertRCReturn(rc, rc);
4014 }
4015 }
4016 }
4017
4018# ifdef VBOX_WITH_VMSVGA3D
4019 if (pThis->svga.f3DEnabled)
4020 {
4021# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
4022 vmsvga3dPowerOn(pThis);
4023# endif
4024
4025 VMSVGA_STATE_LOAD LoadState;
4026 LoadState.pSSM = pSSM;
4027 LoadState.uVersion = uVersion;
4028 LoadState.uPass = uPass;
4029 rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
4030 AssertLogRelRCReturn(rc, rc);
4031 }
4032# endif
4033
4034 return VINF_SUCCESS;
4035}
4036
4037/**
4038 * Reinit the video mode after the state has been loaded.
4039 */
4040int vmsvgaLoadDone(PPDMDEVINS pDevIns)
4041{
4042 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4043 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4044
4045 pThis->last_bpp = VMSVGA_VAL_UNINITIALIZED; /* force mode reset */
4046 vmsvgaChangeMode(pThis);
4047
4048 /* Set the active cursor. */
4049 if (pSVGAState->Cursor.fActive)
4050 {
4051 int rc;
4052
4053 rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
4054 true,
4055 true,
4056 pSVGAState->Cursor.xHotspot,
4057 pSVGAState->Cursor.yHotspot,
4058 pSVGAState->Cursor.width,
4059 pSVGAState->Cursor.height,
4060 pSVGAState->Cursor.pData);
4061 AssertRC(rc);
4062 }
4063 return VINF_SUCCESS;
4064}
4065
4066/**
4067 * @copydoc FNSSMDEVSAVEEXEC
4068 */
4069int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4070{
4071 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4072 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4073 int rc;
4074
4075 /* Save our part of the VGAState */
4076 rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
4077 AssertLogRelRCReturn(rc, rc);
4078
4079 /* Save the framebuffer backup. */
4080 rc = SSMR3PutMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4081 AssertLogRelRCReturn(rc, rc);
4082
4083 /* Save the VMSVGA state. */
4084 rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
4085 AssertLogRelRCReturn(rc, rc);
4086
4087 /* Save the active cursor bitmaps. */
4088 if (pSVGAState->Cursor.fActive)
4089 {
4090 rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
4091 AssertLogRelRCReturn(rc, rc);
4092 }
4093
4094 /* Save the GMR state */
4095 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4096 {
4097 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i], sizeof(pSVGAState->aGMR[i]), 0, g_aGMRFields, NULL);
4098 AssertLogRelRCReturn(rc, rc);
4099
4100 for (uint32_t j = 0; j < pSVGAState->aGMR[i].numDescriptors; j++)
4101 {
4102 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i].paDesc[j], sizeof(pSVGAState->aGMR[i].paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
4103 AssertLogRelRCReturn(rc, rc);
4104 }
4105 }
4106
4107# ifdef VBOX_WITH_VMSVGA3D
4108 /*
4109 * Must save the 3d state in the FIFO thread.
4110 */
4111 if (pThis->svga.f3DEnabled)
4112 {
4113 rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
4114 AssertLogRelRCReturn(rc, rc);
4115 }
4116# endif
4117 return VINF_SUCCESS;
4118}
4119
4120/**
4121 * Resets the SVGA hardware state
4122 *
4123 * @returns VBox status code.
4124 * @param pDevIns The device instance.
4125 */
4126int vmsvgaReset(PPDMDEVINS pDevIns)
4127{
4128 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4129 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4130
4131 /* Reset before init? */
4132 if (!pSVGAState)
4133 return VINF_SUCCESS;
4134
4135 Log(("vmsvgaReset\n"));
4136
4137
4138 /* Reset the FIFO processing as well as the 3d state (if we have one). */
4139 pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
4140 int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /*pvParam*/, 10000 /*ms*/);
4141
4142 /* Reset other stuff. */
4143 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4144 RT_ZERO(pThis->svga.au32ScratchRegion);
4145 RT_ZERO(*pThis->svga.pSvgaR3State);
4146 RT_BZERO(pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4147
4148 /* Register caps. */
4149 pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
4150# ifdef VBOX_WITH_VMSVGA3D
4151 pThis->svga.u32RegCaps |= SVGA_CAP_3D;
4152# endif
4153
4154 /* Setup FIFO capabilities. */
4155 pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
4156
4157 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
4158 pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
4159
4160 /* VRAM tracking is enabled by default during bootup. */
4161 pThis->svga.fVRAMTracking = true;
4162 pThis->svga.fEnabled = false;
4163
4164 /* Invalidate current settings. */
4165 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
4166 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
4167 pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
4168 pThis->svga.cbScanline = 0;
4169
4170 return rc;
4171}
4172
4173/**
4174 * Cleans up the SVGA hardware state
4175 *
4176 * @returns VBox status code.
4177 * @param pDevIns The device instance.
4178 */
4179int vmsvgaDestruct(PPDMDEVINS pDevIns)
4180{
4181 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4182
4183 /*
4184 * Ask the FIFO thread to terminate the 3d state and then terminate it.
4185 */
4186 if (pThis->svga.pFIFOIOThread)
4187 {
4188 int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /*pvParam*/, 30000 /*ms*/);
4189 AssertLogRelRC(rc);
4190
4191 rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
4192 AssertLogRelRC(rc);
4193 pThis->svga.pFIFOIOThread = NULL;
4194 }
4195
4196 /*
4197 * Destroy the special SVGA state.
4198 */
4199 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4200 if (pSVGAState)
4201 {
4202# ifndef VMSVGA_USE_EMT_HALT_CODE
4203 if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
4204 {
4205 RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
4206 pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
4207 }
4208# endif
4209 if (pSVGAState->Cursor.fActive)
4210 RTMemFree(pSVGAState->Cursor.pData);
4211
4212 for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4213 if (pSVGAState->aGMR[i].paDesc)
4214 RTMemFree(pSVGAState->aGMR[i].paDesc);
4215
4216 RTMemFree(pSVGAState);
4217 pThis->svga.pSvgaR3State = NULL;
4218 }
4219
4220 /*
4221 * Free our resources residing in the VGA state.
4222 */
4223 if (pThis->svga.pFrameBufferBackup)
4224 RTMemFree(pThis->svga.pFrameBufferBackup);
4225 if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
4226 {
4227 RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
4228 pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
4229 }
4230 if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
4231 {
4232 SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
4233 pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
4234 }
4235
4236 return VINF_SUCCESS;
4237}
4238
4239/**
4240 * Initialize the SVGA hardware state
4241 *
4242 * @returns VBox status code.
4243 * @param pDevIns The device instance.
4244 */
4245int vmsvgaInit(PPDMDEVINS pDevIns)
4246{
4247 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4248 PVMSVGAR3STATE pSVGAState;
4249 PVM pVM = PDMDevHlpGetVM(pDevIns);
4250 int rc;
4251
4252 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4253 memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
4254
4255 pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
4256 AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
4257 pSVGAState = pThis->svga.pSvgaR3State;
4258
4259 /* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
4260 pThis->svga.pFrameBufferBackup = RTMemAllocZ(VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4261 AssertReturn(pThis->svga.pFrameBufferBackup, VERR_NO_MEMORY);
4262
4263 /* Create event semaphore. */
4264 pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
4265
4266 rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
4267 if (RT_FAILURE(rc))
4268 {
4269 Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
4270 return rc;
4271 }
4272
4273 /* Create event semaphore. */
4274 rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
4275 if (RT_FAILURE(rc))
4276 {
4277 Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
4278 return rc;
4279 }
4280
4281# ifndef VMSVGA_USE_EMT_HALT_CODE
4282 /* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
4283 rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
4284 AssertRCReturn(rc, rc);
4285# endif
4286
4287 /* Register caps. */
4288 pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
4289# ifdef VBOX_WITH_VMSVGA3D
4290 pThis->svga.u32RegCaps |= SVGA_CAP_3D;
4291# endif
4292
4293 /* Setup FIFO capabilities. */
4294 pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
4295
4296 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
4297 pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
4298
4299 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
4300# ifdef VBOX_WITH_VMSVGA3D
4301 if (pThis->svga.f3DEnabled)
4302 {
4303 rc = vmsvga3dInit(pThis);
4304 if (RT_FAILURE(rc))
4305 {
4306 LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
4307 pThis->svga.f3DEnabled = false;
4308 }
4309 }
4310# endif
4311 /* VRAM tracking is enabled by default during bootup. */
4312 pThis->svga.fVRAMTracking = true;
4313
4314 /* Invalidate current settings. */
4315 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
4316 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
4317 pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
4318 pThis->svga.cbScanline = 0;
4319
4320 pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
4321 pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
4322 while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
4323 {
4324 pThis->svga.u32MaxWidth -= 256;
4325 pThis->svga.u32MaxHeight -= 256;
4326 }
4327 Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
4328
4329# ifdef DEBUG_GMR_ACCESS
4330 /* Register the GMR access handler type. */
4331 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
4332 vmsvgaR3GMRAccessHandler,
4333 NULL, NULL, NULL,
4334 NULL, NULL, NULL,
4335 "VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
4336 AssertRCReturn(rc, rc);
4337# endif
4338# ifdef DEBUG_FIFO_ACCESS
4339 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_ALL,
4340 vmsvgaR3FIFOAccessHandler,
4341 NULL, NULL, NULL,
4342 NULL, NULL, NULL,
4343 "VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
4344 AssertRCReturn(rc, rc);
4345#endif
4346
4347 /* Create the async IO thread. */
4348 rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
4349 RTTHREADTYPE_IO, "VMSVGA FIFO");
4350 if (RT_FAILURE(rc))
4351 {
4352 AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
4353 return rc;
4354 }
4355
4356 /*
4357 * Statistics.
4358 */
4359 STAM_REG(pVM, &pSVGAState->StatR3CmdPresent, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/Present", STAMUNIT_TICKS_PER_CALL, "Profiling of Present.");
4360 STAM_REG(pVM, &pSVGAState->StatR3CmdDrawPrimitive, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/DrawPrimitive", STAMUNIT_TICKS_PER_CALL, "Profiling of DrawPrimitive.");
4361 STAM_REG(pVM, &pSVGAState->StatR3CmdSurfaceDMA, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/SurfaceDMA", STAMUNIT_TICKS_PER_CALL, "Profiling of SurfaceDMA.");
4362 STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
4363 STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
4364 STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
4365 STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
4366 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
4367 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
4368 STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
4369
4370 /*
4371 * Info handlers.
4372 */
4373 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
4374# ifdef VBOX_WITH_VMSVGA3D
4375 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
4376 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
4377 "VMSVGA 3d surface details. "
4378 "Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
4379 vmsvgaR3Info3dSurface);
4380# endif
4381
4382 return VINF_SUCCESS;
4383}
4384
4385# ifdef VBOX_WITH_VMSVGA3D
4386/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
4387static const char * const g_apszVmSvgaDevCapNames[] =
4388{
4389 "x3D", /* = 0 */
4390 "xMAX_LIGHTS",
4391 "xMAX_TEXTURES",
4392 "xMAX_CLIP_PLANES",
4393 "xVERTEX_SHADER_VERSION",
4394 "xVERTEX_SHADER",
4395 "xFRAGMENT_SHADER_VERSION",
4396 "xFRAGMENT_SHADER",
4397 "xMAX_RENDER_TARGETS",
4398 "xS23E8_TEXTURES",
4399 "xS10E5_TEXTURES",
4400 "xMAX_FIXED_VERTEXBLEND",
4401 "xD16_BUFFER_FORMAT",
4402 "xD24S8_BUFFER_FORMAT",
4403 "xD24X8_BUFFER_FORMAT",
4404 "xQUERY_TYPES",
4405 "xTEXTURE_GRADIENT_SAMPLING",
4406 "rMAX_POINT_SIZE",
4407 "xMAX_SHADER_TEXTURES",
4408 "xMAX_TEXTURE_WIDTH",
4409 "xMAX_TEXTURE_HEIGHT",
4410 "xMAX_VOLUME_EXTENT",
4411 "xMAX_TEXTURE_REPEAT",
4412 "xMAX_TEXTURE_ASPECT_RATIO",
4413 "xMAX_TEXTURE_ANISOTROPY",
4414 "xMAX_PRIMITIVE_COUNT",
4415 "xMAX_VERTEX_INDEX",
4416 "xMAX_VERTEX_SHADER_INSTRUCTIONS",
4417 "xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
4418 "xMAX_VERTEX_SHADER_TEMPS",
4419 "xMAX_FRAGMENT_SHADER_TEMPS",
4420 "xTEXTURE_OPS",
4421 "xSURFACEFMT_X8R8G8B8",
4422 "xSURFACEFMT_A8R8G8B8",
4423 "xSURFACEFMT_A2R10G10B10",
4424 "xSURFACEFMT_X1R5G5B5",
4425 "xSURFACEFMT_A1R5G5B5",
4426 "xSURFACEFMT_A4R4G4B4",
4427 "xSURFACEFMT_R5G6B5",
4428 "xSURFACEFMT_LUMINANCE16",
4429 "xSURFACEFMT_LUMINANCE8_ALPHA8",
4430 "xSURFACEFMT_ALPHA8",
4431 "xSURFACEFMT_LUMINANCE8",
4432 "xSURFACEFMT_Z_D16",
4433 "xSURFACEFMT_Z_D24S8",
4434 "xSURFACEFMT_Z_D24X8",
4435 "xSURFACEFMT_DXT1",
4436 "xSURFACEFMT_DXT2",
4437 "xSURFACEFMT_DXT3",
4438 "xSURFACEFMT_DXT4",
4439 "xSURFACEFMT_DXT5",
4440 "xSURFACEFMT_BUMPX8L8V8U8",
4441 "xSURFACEFMT_A2W10V10U10",
4442 "xSURFACEFMT_BUMPU8V8",
4443 "xSURFACEFMT_Q8W8V8U8",
4444 "xSURFACEFMT_CxV8U8",
4445 "xSURFACEFMT_R_S10E5",
4446 "xSURFACEFMT_R_S23E8",
4447 "xSURFACEFMT_RG_S10E5",
4448 "xSURFACEFMT_RG_S23E8",
4449 "xSURFACEFMT_ARGB_S10E5",
4450 "xSURFACEFMT_ARGB_S23E8",
4451 "xMISSING62",
4452 "xMAX_VERTEX_SHADER_TEXTURES",
4453 "xMAX_SIMULTANEOUS_RENDER_TARGETS",
4454 "xSURFACEFMT_V16U16",
4455 "xSURFACEFMT_G16R16",
4456 "xSURFACEFMT_A16B16G16R16",
4457 "xSURFACEFMT_UYVY",
4458 "xSURFACEFMT_YUY2",
4459 "xMULTISAMPLE_NONMASKABLESAMPLES",
4460 "xMULTISAMPLE_MASKABLESAMPLES",
4461 "xALPHATOCOVERAGE",
4462 "xSUPERSAMPLE",
4463 "xAUTOGENMIPMAPS",
4464 "xSURFACEFMT_NV12",
4465 "xSURFACEFMT_AYUV",
4466 "xMAX_CONTEXT_IDS",
4467 "xMAX_SURFACE_IDS",
4468 "xSURFACEFMT_Z_DF16",
4469 "xSURFACEFMT_Z_DF24",
4470 "xSURFACEFMT_Z_D24S8_INT",
4471 "xSURFACEFMT_BC4_UNORM",
4472 "xSURFACEFMT_BC5_UNORM", /* 83 */
4473};
4474# endif
4475
4476
4477/**
4478 * Power On notification.
4479 *
4480 * @returns VBox status code.
4481 * @param pDevIns The device instance data.
4482 *
4483 * @remarks Caller enters the device critical section.
4484 */
4485DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
4486{
4487# ifdef VBOX_WITH_VMSVGA3D
4488 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4489 if (pThis->svga.f3DEnabled)
4490 {
4491 int rc = vmsvga3dPowerOn(pThis);
4492
4493 if (RT_SUCCESS(rc))
4494 {
4495 bool fSavedBuffering = RTLogRelSetBuffering(true);
4496 SVGA3dCapsRecord *pCaps;
4497 SVGA3dCapPair *pData;
4498 uint32_t idxCap = 0;
4499
4500 /* 3d hardware version; latest and greatest */
4501 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
4502 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
4503
4504 pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
4505 pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
4506 pData = (SVGA3dCapPair *)&pCaps->data;
4507
4508 /* Fill out all 3d capabilities. */
4509 for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
4510 {
4511 uint32_t val = 0;
4512
4513 rc = vmsvga3dQueryCaps(pThis, i, &val);
4514 if (RT_SUCCESS(rc))
4515 {
4516 pData[idxCap][0] = i;
4517 pData[idxCap][1] = val;
4518 idxCap++;
4519 if (g_apszVmSvgaDevCapNames[i][0] == 'x')
4520 LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
4521 else
4522 LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)*(float *)&val, (unsigned)(*(float *)&val * 10000) % 10000,
4523 &g_apszVmSvgaDevCapNames[i][1]));
4524 }
4525 else
4526 LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
4527 }
4528 pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
4529 pCaps = (SVGA3dCapsRecord *)((uint32_t *)pCaps + pCaps->header.length);
4530
4531 /* Mark end of record array. */
4532 pCaps->header.length = 0;
4533
4534 RTLogRelSetBuffering(fSavedBuffering);
4535 }
4536 }
4537# else /* !VBOX_WITH_VMSVGA3D */
4538 RT_NOREF(pDevIns);
4539# endif /* !VBOX_WITH_VMSVGA3D */
4540}
4541
4542#endif /* IN_RING3 */
4543
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