VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 55909

Last change on this file since 55909 was 55909, checked in by vboxsync, 10 years ago

PGM,++: Made the ring-3 physical access handler callbacks present in all contexts, where applicable. They are not yet registered or used. Taking things slowly.
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File size: 173.9 KB
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1/* $Id: DevVGA-SVGA.cpp 55909 2015-05-18 13:09:16Z vboxsync $ */
2/** @file
3 * VMWare SVGA device.
4 *
5 * Logging levels guidelines for this and related files:
6 * - Log() for normal bits.
7 * - LogFlow() for more info.
8 * - Log2 for hex dump of cursor data.
9 * - Log3 for hex dump of shader code.
10 * - Log4 for hex dumps of 3D data.
11 */
12
13/*
14 * Copyright (C) 2013-2014 Oracle Corporation
15 *
16 * This file is part of VirtualBox Open Source Edition (OSE), as
17 * available from http://www.virtualbox.org. This file is free software;
18 * you can redistribute it and/or modify it under the terms of the GNU
19 * General Public License (GPL) as published by the Free Software
20 * Foundation, in version 2 as it comes in the "COPYING" file of the
21 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23 */
24
25
26/*******************************************************************************
27* Header Files *
28*******************************************************************************/
29#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
30#define VMSVGA_USE_EMT_HALT_CODE
31#include <VBox/vmm/pdmdev.h>
32#include <VBox/version.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/vmm/pgm.h>
36#ifdef VMSVGA_USE_EMT_HALT_CODE
37# include <VBox/vmm/vmapi.h>
38# include <VBox/vmm/vmcpuset.h>
39#endif
40#include <VBox/sup.h>
41
42#include <iprt/assert.h>
43#include <iprt/semaphore.h>
44#include <iprt/uuid.h>
45#ifdef IN_RING3
46# include <iprt/mem.h>
47#endif
48
49#include <VBox/VMMDev.h>
50#include <VBox/VBoxVideo.h>
51#include <VBox/bioslogo.h>
52
53/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
54#include "DevVGA.h"
55
56#ifdef DEBUG
57/* Enable to log FIFO register accesses. */
58//# define DEBUG_FIFO_ACCESS
59/* Enable to log GMR page accesses. */
60//# define DEBUG_GMR_ACCESS
61#endif
62
63#include "DevVGA-SVGA.h"
64#include "vmsvga/svga_reg.h"
65#include "vmsvga/svga_escape.h"
66#include "vmsvga/svga_overlay.h"
67#include "vmsvga/svga3d_reg.h"
68#include "vmsvga/svga3d_caps.h"
69#ifdef VBOX_WITH_VMSVGA3D
70# include "DevVGA-SVGA3d.h"
71# ifdef RT_OS_DARWIN
72# include "DevVGA-SVGA3d-cocoa.h"
73# endif
74#endif
75
76
77/*******************************************************************************
78* Defined Constants And Macros *
79*******************************************************************************/
80/**
81 * Macro for checking if a fixed FIFO register is valid according to the
82 * current FIFO configuration.
83 *
84 * @returns true / false.
85 * @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
86 * @param a_offFifoMin A valid SVGA_FIFO_MIN value.
87 */
88#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
89
90
91/*******************************************************************************
92* Structures and Typedefs *
93*******************************************************************************/
94/* 64-bit GMR descriptor */
95typedef struct
96{
97 RTGCPHYS GCPhys;
98 uint64_t numPages;
99} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
100
101/* GMR slot */
102typedef struct
103{
104 uint32_t cMaxPages;
105 uint32_t cbTotal;
106 uint32_t numDescriptors;
107 PVMSVGAGMRDESCRIPTOR paDesc;
108} GMR, *PGMR;
109
110/* Internal SVGA state. */
111typedef struct
112{
113 GMR aGMR[VMSVGA_MAX_GMR_IDS];
114 struct
115 {
116 SVGAGuestPtr ptr;
117 uint32_t bytesPerLine;
118 SVGAGMRImageFormat format;
119 } GMRFB;
120 struct
121 {
122 bool fActive;
123 uint32_t xHotspot;
124 uint32_t yHotspot;
125 uint32_t width;
126 uint32_t height;
127 uint32_t cbData;
128 void *pData;
129 } Cursor;
130 SVGAColorBGRX colorAnnotation;
131
132#ifdef VMSVGA_USE_EMT_HALT_CODE
133 /** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
134 uint32_t volatile cBusyDelayedEmts;
135 /** Set of EMTs that are */
136 VMCPUSET BusyDelayedEmts;
137#else
138 /** Number of EMTs waiting on hBusyDelayedEmts. */
139 uint32_t volatile cBusyDelayedEmts;
140 /** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
141 * busy (ugly). */
142 RTSEMEVENTMULTI hBusyDelayedEmts;
143#endif
144 /** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
145 STAMPROFILE StatBusyDelayEmts;
146
147 STAMPROFILE StatR3CmdPresent;
148 STAMPROFILE StatR3CmdDrawPrimitive;
149 STAMPROFILE StatR3CmdSurfaceDMA;
150
151 STAMCOUNTER StatFifoCommands;
152 STAMCOUNTER StatFifoErrors;
153 STAMCOUNTER StatFifoUnkCmds;
154 STAMCOUNTER StatFifoTodoTimeout;
155 STAMCOUNTER StatFifoTodoWoken;
156 STAMPROFILE StatFifoStalls;
157
158} VMSVGASTATE, *PVMSVGASTATE;
159
160
161/*******************************************************************************
162* Internal Functions *
163*******************************************************************************/
164#ifdef IN_RING3
165# ifdef DEBUG_FIFO_ACCESS
166static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
167# endif
168# ifdef DEBUG_GMR_ACCESS
169static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
170# endif
171#endif
172
173
174/*******************************************************************************
175* Global Variables *
176*******************************************************************************/
177#ifdef IN_RING3
178
179/**
180 * SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
181 */
182static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
183{
184 SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
185 SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
186 SSMFIELD_ENTRY_TERM()
187};
188
189/**
190 * SSM descriptor table for the GMR structure.
191 */
192static SSMFIELD const g_aGMRFields[] =
193{
194 SSMFIELD_ENTRY( GMR, cMaxPages),
195 SSMFIELD_ENTRY( GMR, cbTotal),
196 SSMFIELD_ENTRY( GMR, numDescriptors),
197 SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
198 SSMFIELD_ENTRY_TERM()
199};
200
201/**
202 * SSM descriptor table for the VMSVGASTATE structure.
203 */
204static SSMFIELD const g_aVMSVGASTATEFields[] =
205{
206 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, aGMR),
207 SSMFIELD_ENTRY( VMSVGASTATE, GMRFB),
208 SSMFIELD_ENTRY( VMSVGASTATE, Cursor.fActive),
209 SSMFIELD_ENTRY( VMSVGASTATE, Cursor.xHotspot),
210 SSMFIELD_ENTRY( VMSVGASTATE, Cursor.yHotspot),
211 SSMFIELD_ENTRY( VMSVGASTATE, Cursor.width),
212 SSMFIELD_ENTRY( VMSVGASTATE, Cursor.height),
213 SSMFIELD_ENTRY( VMSVGASTATE, Cursor.cbData),
214 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGASTATE, Cursor.pData),
215 SSMFIELD_ENTRY( VMSVGASTATE, colorAnnotation),
216 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, cBusyDelayedEmts),
217#ifdef VMSVGA_USE_EMT_HALT_CODE
218 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, BusyDelayedEmts),
219#else
220 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, hBusyDelayedEmts),
221#endif
222 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatBusyDelayEmts),
223 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatR3CmdPresent),
224 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatR3CmdDrawPrimitive),
225 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatR3CmdSurfaceDMA),
226 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatFifoCommands),
227 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatFifoErrors),
228 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatFifoUnkCmds),
229 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatFifoTodoTimeout),
230 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatFifoTodoWoken),
231 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatFifoStalls),
232 SSMFIELD_ENTRY_TERM()
233};
234
235/**
236 * SSM descriptor table for the VGAState.svga structure.
237 */
238static SSMFIELD const g_aVGAStateSVGAFields[] =
239{
240 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u64HostWindowId),
241 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
242 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
243 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSVGAState),
244 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
245 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFrameBufferBackup),
246 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOExtCmdParam),
247 SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
248 SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
249 SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
250 SSMFIELD_ENTRY( VMSVGAState, fEnabled),
251 SSMFIELD_ENTRY( VMSVGAState, fConfigured),
252 SSMFIELD_ENTRY( VMSVGAState, fBusy),
253 SSMFIELD_ENTRY( VMSVGAState, fTraces),
254 SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
255 SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
256 SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
257 SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
258 SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
259 SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
260 SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
261 SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
262 SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
263 SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
264 SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
265 SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
266 SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
267 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
268 SSMFIELD_ENTRY( VMSVGAState, uWidth),
269 SSMFIELD_ENTRY( VMSVGAState, uHeight),
270 SSMFIELD_ENTRY( VMSVGAState, uBpp),
271 SSMFIELD_ENTRY( VMSVGAState, cbScanline),
272 SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
273 SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
274 SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
275 SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
276 SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
277 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
278 SSMFIELD_ENTRY_TERM()
279};
280
281static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
282
283#endif /* IN_RING3 */
284
285
286#ifdef LOG_ENABLED
287/**
288 * Index register string name lookup
289 *
290 * @returns Index register string or "UNKNOWN"
291 * @param pThis VMSVGA State
292 */
293static const char *vmsvgaIndexToString(PVGASTATE pThis)
294{
295 switch (pThis->svga.u32IndexReg)
296 {
297 case SVGA_REG_ID:
298 return "SVGA_REG_ID";
299 case SVGA_REG_ENABLE:
300 return "SVGA_REG_ENABLE";
301 case SVGA_REG_WIDTH:
302 return "SVGA_REG_WIDTH";
303 case SVGA_REG_HEIGHT:
304 return "SVGA_REG_HEIGHT";
305 case SVGA_REG_MAX_WIDTH:
306 return "SVGA_REG_MAX_WIDTH";
307 case SVGA_REG_MAX_HEIGHT:
308 return "SVGA_REG_MAX_HEIGHT";
309 case SVGA_REG_DEPTH:
310 return "SVGA_REG_DEPTH";
311 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
312 return "SVGA_REG_BITS_PER_PIXEL";
313 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
314 return "SVGA_REG_HOST_BITS_PER_PIXEL";
315 case SVGA_REG_PSEUDOCOLOR:
316 return "SVGA_REG_PSEUDOCOLOR";
317 case SVGA_REG_RED_MASK:
318 return "SVGA_REG_RED_MASK";
319 case SVGA_REG_GREEN_MASK:
320 return "SVGA_REG_GREEN_MASK";
321 case SVGA_REG_BLUE_MASK:
322 return "SVGA_REG_BLUE_MASK";
323 case SVGA_REG_BYTES_PER_LINE:
324 return "SVGA_REG_BYTES_PER_LINE";
325 case SVGA_REG_VRAM_SIZE: /* VRAM size */
326 return "SVGA_REG_VRAM_SIZE";
327 case SVGA_REG_FB_START: /* Frame buffer physical address. */
328 return "SVGA_REG_FB_START";
329 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
330 return "SVGA_REG_FB_OFFSET";
331 case SVGA_REG_FB_SIZE: /* Frame buffer size */
332 return "SVGA_REG_FB_SIZE";
333 case SVGA_REG_CAPABILITIES:
334 return "SVGA_REG_CAPABILITIES";
335 case SVGA_REG_MEM_START: /* FIFO start */
336 return "SVGA_REG_MEM_START";
337 case SVGA_REG_MEM_SIZE: /* FIFO size */
338 return "SVGA_REG_MEM_SIZE";
339 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
340 return "SVGA_REG_CONFIG_DONE";
341 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
342 return "SVGA_REG_SYNC";
343 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
344 return "SVGA_REG_BUSY";
345 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
346 return "SVGA_REG_GUEST_ID";
347 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
348 return "SVGA_REG_SCRATCH_SIZE";
349 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
350 return "SVGA_REG_MEM_REGS";
351 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
352 return "SVGA_REG_PITCHLOCK";
353 case SVGA_REG_IRQMASK: /* Interrupt mask */
354 return "SVGA_REG_IRQMASK";
355 case SVGA_REG_GMR_ID:
356 return "SVGA_REG_GMR_ID";
357 case SVGA_REG_GMR_DESCRIPTOR:
358 return "SVGA_REG_GMR_DESCRIPTOR";
359 case SVGA_REG_GMR_MAX_IDS:
360 return "SVGA_REG_GMR_MAX_IDS";
361 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
362 return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
363 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
364 return "SVGA_REG_TRACES";
365 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
366 return "SVGA_REG_GMRS_MAX_PAGES";
367 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
368 return "SVGA_REG_MEMORY_SIZE";
369 case SVGA_REG_TOP: /* Must be 1 more than the last register */
370 return "SVGA_REG_TOP";
371 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
372 return "SVGA_PALETTE_BASE";
373 case SVGA_REG_CURSOR_ID:
374 return "SVGA_REG_CURSOR_ID";
375 case SVGA_REG_CURSOR_X:
376 return "SVGA_REG_CURSOR_X";
377 case SVGA_REG_CURSOR_Y:
378 return "SVGA_REG_CURSOR_Y";
379 case SVGA_REG_CURSOR_ON:
380 return "SVGA_REG_CURSOR_ON";
381 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
382 return "SVGA_REG_NUM_GUEST_DISPLAYS";
383 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
384 return "SVGA_REG_DISPLAY_ID";
385 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
386 return "SVGA_REG_DISPLAY_IS_PRIMARY";
387 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
388 return "SVGA_REG_DISPLAY_POSITION_X";
389 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
390 return "SVGA_REG_DISPLAY_POSITION_Y";
391 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
392 return "SVGA_REG_DISPLAY_WIDTH";
393 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
394 return "SVGA_REG_DISPLAY_HEIGHT";
395 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
396 return "SVGA_REG_NUM_DISPLAYS";
397
398 default:
399 if (pThis->svga.u32IndexReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
400 return "SVGA_SCRATCH_BASE reg";
401 if (pThis->svga.u32IndexReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
402 return "SVGA_PALETTE_BASE reg";
403 return "UNKNOWN";
404 }
405}
406
407/**
408 * FIFO command name lookup
409 *
410 * @returns FIFO command string or "UNKNOWN"
411 * @param u32Cmd FIFO command
412 */
413static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
414{
415 switch (u32Cmd)
416 {
417 case SVGA_CMD_INVALID_CMD:
418 return "SVGA_CMD_INVALID_CMD";
419 case SVGA_CMD_UPDATE:
420 return "SVGA_CMD_UPDATE";
421 case SVGA_CMD_RECT_COPY:
422 return "SVGA_CMD_RECT_COPY";
423 case SVGA_CMD_DEFINE_CURSOR:
424 return "SVGA_CMD_DEFINE_CURSOR";
425 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
426 return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
427 case SVGA_CMD_UPDATE_VERBOSE:
428 return "SVGA_CMD_UPDATE_VERBOSE";
429 case SVGA_CMD_FRONT_ROP_FILL:
430 return "SVGA_CMD_FRONT_ROP_FILL";
431 case SVGA_CMD_FENCE:
432 return "SVGA_CMD_FENCE";
433 case SVGA_CMD_ESCAPE:
434 return "SVGA_CMD_ESCAPE";
435 case SVGA_CMD_DEFINE_SCREEN:
436 return "SVGA_CMD_DEFINE_SCREEN";
437 case SVGA_CMD_DESTROY_SCREEN:
438 return "SVGA_CMD_DESTROY_SCREEN";
439 case SVGA_CMD_DEFINE_GMRFB:
440 return "SVGA_CMD_DEFINE_GMRFB";
441 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
442 return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
443 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
444 return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
445 case SVGA_CMD_ANNOTATION_FILL:
446 return "SVGA_CMD_ANNOTATION_FILL";
447 case SVGA_CMD_ANNOTATION_COPY:
448 return "SVGA_CMD_ANNOTATION_COPY";
449 case SVGA_CMD_DEFINE_GMR2:
450 return "SVGA_CMD_DEFINE_GMR2";
451 case SVGA_CMD_REMAP_GMR2:
452 return "SVGA_CMD_REMAP_GMR2";
453 case SVGA_3D_CMD_SURFACE_DEFINE:
454 return "SVGA_3D_CMD_SURFACE_DEFINE";
455 case SVGA_3D_CMD_SURFACE_DESTROY:
456 return "SVGA_3D_CMD_SURFACE_DESTROY";
457 case SVGA_3D_CMD_SURFACE_COPY:
458 return "SVGA_3D_CMD_SURFACE_COPY";
459 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
460 return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
461 case SVGA_3D_CMD_SURFACE_DMA:
462 return "SVGA_3D_CMD_SURFACE_DMA";
463 case SVGA_3D_CMD_CONTEXT_DEFINE:
464 return "SVGA_3D_CMD_CONTEXT_DEFINE";
465 case SVGA_3D_CMD_CONTEXT_DESTROY:
466 return "SVGA_3D_CMD_CONTEXT_DESTROY";
467 case SVGA_3D_CMD_SETTRANSFORM:
468 return "SVGA_3D_CMD_SETTRANSFORM";
469 case SVGA_3D_CMD_SETZRANGE:
470 return "SVGA_3D_CMD_SETZRANGE";
471 case SVGA_3D_CMD_SETRENDERSTATE:
472 return "SVGA_3D_CMD_SETRENDERSTATE";
473 case SVGA_3D_CMD_SETRENDERTARGET:
474 return "SVGA_3D_CMD_SETRENDERTARGET";
475 case SVGA_3D_CMD_SETTEXTURESTATE:
476 return "SVGA_3D_CMD_SETTEXTURESTATE";
477 case SVGA_3D_CMD_SETMATERIAL:
478 return "SVGA_3D_CMD_SETMATERIAL";
479 case SVGA_3D_CMD_SETLIGHTDATA:
480 return "SVGA_3D_CMD_SETLIGHTDATA";
481 case SVGA_3D_CMD_SETLIGHTENABLED:
482 return "SVGA_3D_CMD_SETLIGHTENABLED";
483 case SVGA_3D_CMD_SETVIEWPORT:
484 return "SVGA_3D_CMD_SETVIEWPORT";
485 case SVGA_3D_CMD_SETCLIPPLANE:
486 return "SVGA_3D_CMD_SETCLIPPLANE";
487 case SVGA_3D_CMD_CLEAR:
488 return "SVGA_3D_CMD_CLEAR";
489 case SVGA_3D_CMD_PRESENT:
490 return "SVGA_3D_CMD_PRESENT";
491 case SVGA_3D_CMD_SHADER_DEFINE:
492 return "SVGA_3D_CMD_SHADER_DEFINE";
493 case SVGA_3D_CMD_SHADER_DESTROY:
494 return "SVGA_3D_CMD_SHADER_DESTROY";
495 case SVGA_3D_CMD_SET_SHADER:
496 return "SVGA_3D_CMD_SET_SHADER";
497 case SVGA_3D_CMD_SET_SHADER_CONST:
498 return "SVGA_3D_CMD_SET_SHADER_CONST";
499 case SVGA_3D_CMD_DRAW_PRIMITIVES:
500 return "SVGA_3D_CMD_DRAW_PRIMITIVES";
501 case SVGA_3D_CMD_SETSCISSORRECT:
502 return "SVGA_3D_CMD_SETSCISSORRECT";
503 case SVGA_3D_CMD_BEGIN_QUERY:
504 return "SVGA_3D_CMD_BEGIN_QUERY";
505 case SVGA_3D_CMD_END_QUERY:
506 return "SVGA_3D_CMD_END_QUERY";
507 case SVGA_3D_CMD_WAIT_FOR_QUERY:
508 return "SVGA_3D_CMD_WAIT_FOR_QUERY";
509 case SVGA_3D_CMD_PRESENT_READBACK:
510 return "SVGA_3D_CMD_PRESENT_READBACK";
511 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
512 return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
513 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
514 return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
515 case SVGA_3D_CMD_GENERATE_MIPMAPS:
516 return "SVGA_3D_CMD_GENERATE_MIPMAPS";
517 case SVGA_3D_CMD_ACTIVATE_SURFACE:
518 return "SVGA_3D_CMD_ACTIVATE_SURFACE";
519 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
520 return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
521 default:
522 return "UNKNOWN";
523 }
524}
525#endif
526
527/**
528 * Inform the VGA device of viewport changes (as a result of e.g. scrolling)
529 *
530 * @param pInterface Pointer to this interface.
531 * @param
532 * @param uScreenId The screen updates are for.
533 * @param x The upper left corner x coordinate of the new viewport rectangle
534 * @param y The upper left corner y coordinate of the new viewport rectangle
535 * @param cx The width of the new viewport rectangle
536 * @param cy The height of the new viewport rectangle
537 * @thread The emulation thread.
538 */
539DECLCALLBACK(void) vmsvgaPortSetViewPort(PPDMIDISPLAYPORT pInterface, uint32_t uScreenId, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
540{
541 PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
542
543 Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", uScreenId, x, y, cx, cy));
544
545 pThis->svga.viewport.x = x;
546 pThis->svga.viewport.y = y;
547 pThis->svga.viewport.cx = RT_MIN(cx, (uint32_t)pThis->svga.uWidth);
548 pThis->svga.viewport.cy = RT_MIN(cy, (uint32_t)pThis->svga.uHeight);
549 return;
550}
551
552/**
553 * Read port register
554 *
555 * @returns VBox status code.
556 * @param pThis VMSVGA State
557 * @param pu32 Where to store the read value
558 */
559PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
560{
561 int rc = VINF_SUCCESS;
562
563 *pu32 = 0;
564 switch (pThis->svga.u32IndexReg)
565 {
566 case SVGA_REG_ID:
567 *pu32 = pThis->svga.u32SVGAId;
568 break;
569
570 case SVGA_REG_ENABLE:
571 *pu32 = pThis->svga.fEnabled;
572 break;
573
574 case SVGA_REG_WIDTH:
575 {
576 if ( pThis->svga.fEnabled
577 && pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
578 {
579 *pu32 = pThis->svga.uWidth;
580 }
581 else
582 {
583#ifndef IN_RING3
584 rc = VINF_IOM_R3_IOPORT_READ;
585#else
586 *pu32 = pThis->pDrv->cx;
587#endif
588 }
589 break;
590 }
591
592 case SVGA_REG_HEIGHT:
593 {
594 if ( pThis->svga.fEnabled
595 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
596 {
597 *pu32 = pThis->svga.uHeight;
598 }
599 else
600 {
601#ifndef IN_RING3
602 rc = VINF_IOM_R3_IOPORT_READ;
603#else
604 *pu32 = pThis->pDrv->cy;
605#endif
606 }
607 break;
608 }
609
610 case SVGA_REG_MAX_WIDTH:
611 *pu32 = pThis->svga.u32MaxWidth;
612 break;
613
614 case SVGA_REG_MAX_HEIGHT:
615 *pu32 = pThis->svga.u32MaxHeight;
616 break;
617
618 case SVGA_REG_DEPTH:
619 /* This returns the color depth of the current mode. */
620 switch (pThis->svga.uBpp)
621 {
622 case 15:
623 case 16:
624 case 24:
625 *pu32 = pThis->svga.uBpp;
626 break;
627
628 default:
629 case 32:
630 *pu32 = 24; /* The upper 8 bits are either alpha bits or not used. */
631 break;
632 }
633 break;
634
635 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
636 if ( pThis->svga.fEnabled
637 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
638 {
639 *pu32 = pThis->svga.uBpp;
640 }
641 else
642 {
643#ifndef IN_RING3
644 rc = VINF_IOM_R3_IOPORT_READ;
645#else
646 *pu32 = pThis->pDrv->cBits;
647#endif
648 }
649 break;
650
651 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
652 if ( pThis->svga.fEnabled
653 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
654 {
655 *pu32 = (pThis->svga.uBpp + 7) & ~7;
656 }
657 else
658 {
659#ifndef IN_RING3
660 rc = VINF_IOM_R3_IOPORT_READ;
661#else
662 *pu32 = (pThis->pDrv->cBits + 7) & ~7;
663#endif
664 }
665 break;
666
667 case SVGA_REG_PSEUDOCOLOR:
668 *pu32 = 0;
669 break;
670
671 case SVGA_REG_RED_MASK:
672 case SVGA_REG_GREEN_MASK:
673 case SVGA_REG_BLUE_MASK:
674 {
675 uint32_t uBpp;
676
677 if ( pThis->svga.fEnabled
678 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
679 {
680 uBpp = pThis->svga.uBpp;
681 }
682 else
683 {
684#ifndef IN_RING3
685 rc = VINF_IOM_R3_IOPORT_READ;
686 break;
687#else
688 uBpp = pThis->pDrv->cBits;
689#endif
690 }
691 uint32_t u32RedMask, u32GreenMask, u32BlueMask;
692 switch (uBpp)
693 {
694 case 8:
695 u32RedMask = 0x07;
696 u32GreenMask = 0x38;
697 u32BlueMask = 0xc0;
698 break;
699
700 case 15:
701 u32RedMask = 0x0000001f;
702 u32GreenMask = 0x000003e0;
703 u32BlueMask = 0x00007c00;
704 break;
705
706 case 16:
707 u32RedMask = 0x0000001f;
708 u32GreenMask = 0x000007e0;
709 u32BlueMask = 0x0000f800;
710 break;
711
712 case 24:
713 case 32:
714 default:
715 u32RedMask = 0x00ff0000;
716 u32GreenMask = 0x0000ff00;
717 u32BlueMask = 0x000000ff;
718 break;
719 }
720 switch (pThis->svga.u32IndexReg)
721 {
722 case SVGA_REG_RED_MASK:
723 *pu32 = u32RedMask;
724 break;
725
726 case SVGA_REG_GREEN_MASK:
727 *pu32 = u32GreenMask;
728 break;
729
730 case SVGA_REG_BLUE_MASK:
731 *pu32 = u32BlueMask;
732 break;
733 }
734 break;
735 }
736
737 case SVGA_REG_BYTES_PER_LINE:
738 {
739 if ( pThis->svga.fEnabled
740 && pThis->svga.cbScanline)
741 {
742 *pu32 = pThis->svga.cbScanline;
743 }
744 else
745 {
746#ifndef IN_RING3
747 rc = VINF_IOM_R3_IOPORT_READ;
748#else
749 *pu32 = pThis->pDrv->cbScanline;
750#endif
751 }
752 break;
753 }
754
755 case SVGA_REG_VRAM_SIZE: /* VRAM size */
756 *pu32 = pThis->vram_size;
757 break;
758
759 case SVGA_REG_FB_START: /* Frame buffer physical address. */
760 Assert(pThis->GCPhysVRAM <= 0xffffffff);
761 *pu32 = pThis->GCPhysVRAM;
762 break;
763
764 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
765 /* Always zero in our case. */
766 *pu32 = 0;
767 break;
768
769 case SVGA_REG_FB_SIZE: /* Frame buffer size */
770 {
771#ifndef IN_RING3
772 rc = VINF_IOM_R3_IOPORT_READ;
773#else
774 /* VMWare testcases want at least 4 MB in case the hardware is disabled. */
775 if ( pThis->svga.fEnabled
776 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
777 {
778 /* Hardware enabled; return real framebuffer size .*/
779 *pu32 = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
780 }
781 else
782 *pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy * pThis->pDrv->cbScanline);
783
784 *pu32 = RT_MIN(pThis->vram_size, *pu32);
785 Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
786#endif
787 break;
788 }
789
790 case SVGA_REG_CAPABILITIES:
791 *pu32 = pThis->svga.u32RegCaps;
792 break;
793
794 case SVGA_REG_MEM_START: /* FIFO start */
795 Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
796 *pu32 = pThis->svga.GCPhysFIFO;
797 break;
798
799 case SVGA_REG_MEM_SIZE: /* FIFO size */
800 *pu32 = pThis->svga.cbFIFO;
801 break;
802
803 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
804 *pu32 = pThis->svga.fConfigured;
805 break;
806
807 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
808 *pu32 = 0;
809 break;
810
811 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
812 if (pThis->svga.fBusy)
813 {
814#ifndef IN_RING3
815 /* Go to ring-3 and halt the CPU. */
816 rc = VINF_IOM_R3_IOPORT_READ;
817 break;
818#elif defined(VMSVGA_USE_EMT_HALT_CODE)
819 /* The guest is basically doing a HLT via the device here, but with
820 a special wake up condition on FIFO completion. */
821 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
822 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
823 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
824 VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
825 VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
826 ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
827 if (pThis->svga.fBusy)
828 rc = VMR3WaitForDeviceReady(pVM, idCpu);
829 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
830 VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
831#else
832
833 /* Delay the EMT a bit so the FIFO and others can get some work done.
834 This used to be a crude 50 ms sleep. The current code tries to be
835 more efficient, but the consept is still very crude. */
836 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
837 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
838 RTThreadYield();
839 if (pThis->svga.fBusy)
840 {
841 uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
842
843 if (pThis->svga.fBusy && cRefs == 1)
844 RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
845 if (pThis->svga.fBusy)
846 {
847 /** @todo If this code is going to stay, we need to call into the halt/wait
848 * code in VMEmt.cpp here, otherwise all kind of EMT interaction will
849 * suffer when the guest is polling on a busy FIFO. */
850 uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
851 if (cNsMaxWait >= RT_NS_100US)
852 RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
853 RTSEMWAIT_FLAGS_NANOSECS | RTSEMWAIT_FLAGS_RELATIVE | RTSEMWAIT_FLAGS_NORESUME,
854 RT_MIN(cNsMaxWait, RT_NS_10MS));
855 }
856
857 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
858 }
859 STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
860#endif
861 *pu32 = pThis->svga.fBusy != 0;
862 }
863 else
864 *pu32 = false;
865 break;
866
867 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
868 *pu32 = pThis->svga.u32GuestId;
869 break;
870
871 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
872 *pu32 = pThis->svga.cScratchRegion;
873 break;
874
875 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
876 *pu32 = SVGA_FIFO_NUM_REGS;
877 break;
878
879 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
880 *pu32 = pThis->svga.u32PitchLock;
881 break;
882
883 case SVGA_REG_IRQMASK: /* Interrupt mask */
884 *pu32 = pThis->svga.u32IrqMask;
885 break;
886
887 /* See "Guest memory regions" below. */
888 case SVGA_REG_GMR_ID:
889 *pu32 = pThis->svga.u32CurrentGMRId;
890 break;
891
892 case SVGA_REG_GMR_DESCRIPTOR:
893 /* Write only */
894 *pu32 = 0;
895 break;
896
897 case SVGA_REG_GMR_MAX_IDS:
898 *pu32 = VMSVGA_MAX_GMR_IDS;
899 break;
900
901 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
902 *pu32 = VMSVGA_MAX_GMR_PAGES;
903 break;
904
905 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
906 *pu32 = pThis->svga.fTraces;
907 break;
908
909 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
910 *pu32 = VMSVGA_MAX_GMR_PAGES;
911 break;
912
913 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
914 *pu32 = VMSVGA_SURFACE_SIZE;
915 break;
916
917 case SVGA_REG_TOP: /* Must be 1 more than the last register */
918 break;
919
920 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
921 break;
922 /* Next 768 (== 256*3) registers exist for colormap */
923
924 /* Mouse cursor support. */
925 case SVGA_REG_CURSOR_ID:
926 case SVGA_REG_CURSOR_X:
927 case SVGA_REG_CURSOR_Y:
928 case SVGA_REG_CURSOR_ON:
929 break;
930
931 /* Legacy multi-monitor support */
932 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
933 *pu32 = 1;
934 break;
935
936 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
937 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
938 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
939 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
940 *pu32 = 0;
941 break;
942
943 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
944 *pu32 = pThis->svga.uWidth;
945 break;
946
947 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
948 *pu32 = pThis->svga.uHeight;
949 break;
950
951 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
952 *pu32 = 1; /* Must return something sensible here otherwise the Linux driver will take a legacy code path without 3d support. */
953 break;
954
955 default:
956 if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE
957 && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
958 {
959 *pu32 = pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE];
960 }
961 break;
962 }
963 Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, *pu32, rc));
964 return rc;
965}
966
967#ifdef IN_RING3
968/**
969 * Apply the current resolution settings to change the video mode.
970 *
971 * @returns VBox status code.
972 * @param pThis VMSVGA State
973 */
974int vmsvgaChangeMode(PVGASTATE pThis)
975{
976 int rc;
977
978 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
979 || pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
980 || pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
981 {
982 /* Mode change in progress; wait for all values to be set. */
983 Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
984 return VINF_SUCCESS;
985 }
986
987 if ( pThis->svga.uWidth == 0
988 || pThis->svga.uHeight == 0
989 || pThis->svga.uBpp == 0)
990 {
991 /* Invalid mode change. */
992 Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
993 return VINF_SUCCESS;
994 }
995
996 if ( pThis->last_bpp == (unsigned)pThis->svga.uBpp
997 && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
998 && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
999 && pThis->last_width == (unsigned)pThis->svga.uWidth
1000 && pThis->last_height == (unsigned)pThis->svga.uHeight
1001 )
1002 {
1003 /* Nothing to do. */
1004 Log(("vmsvgaChangeMode: nothing changed; ignore\n"));
1005 return VINF_SUCCESS;
1006 }
1007
1008 Log(("vmsvgaChangeMode: sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1009 pThis->svga.cbScanline = ((pThis->svga.uWidth * pThis->svga.uBpp + 7) & ~7) / 8;
1010
1011 pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1012 rc = pThis->pDrv->pfnResize(pThis->pDrv, pThis->svga.uBpp, pThis->CTX_SUFF(vram_ptr), pThis->svga.cbScanline, pThis->svga.uWidth, pThis->svga.uHeight);
1013 AssertRC(rc);
1014 AssertReturn(rc == VINF_SUCCESS || rc == VINF_VGA_RESIZE_IN_PROGRESS, rc);
1015
1016 /* last stuff */
1017 pThis->last_bpp = pThis->svga.uBpp;
1018 pThis->last_scr_width = pThis->svga.uWidth;
1019 pThis->last_scr_height = pThis->svga.uHeight;
1020 pThis->last_width = pThis->svga.uWidth;
1021 pThis->last_height = pThis->svga.uHeight;
1022
1023 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1024
1025 /* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1026 if ( pThis->svga.viewport.cx == 0
1027 && pThis->svga.viewport.cy == 0)
1028 {
1029 pThis->svga.viewport.cx = pThis->svga.uWidth;
1030 pThis->svga.viewport.cy = pThis->svga.uHeight;
1031 }
1032 return VINF_SUCCESS;
1033}
1034#endif /* IN_RING3 */
1035
1036#if defined(IN_RING0) || defined(IN_RING3)
1037/**
1038 * Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1039 *
1040 * @param pThis The VMSVGA state.
1041 * @param fState The busy state.
1042 */
1043DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1044{
1045 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1046
1047 if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1048 {
1049 /* Race / unfortunately scheduling. Highly unlikly. */
1050 uint32_t cLoops = 64;
1051 do
1052 {
1053 ASMNopPause();
1054 fState = (pThis->svga.fBusy != 0);
1055 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1056 } while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1057 }
1058}
1059#endif
1060
1061/**
1062 * Write port register
1063 *
1064 * @returns VBox status code.
1065 * @param pThis VMSVGA State
1066 * @param u32 Value to write
1067 */
1068PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1069{
1070 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
1071 int rc = VINF_SUCCESS;
1072
1073 Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, u32));
1074 switch (pThis->svga.u32IndexReg)
1075 {
1076 case SVGA_REG_ID:
1077 if ( u32 == SVGA_ID_0
1078 || u32 == SVGA_ID_1
1079 || u32 == SVGA_ID_2)
1080 pThis->svga.u32SVGAId = u32;
1081 break;
1082
1083 case SVGA_REG_ENABLE:
1084 if ( pThis->svga.fEnabled == u32
1085 && pThis->last_bpp == (unsigned)pThis->svga.uBpp
1086 && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1087 && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1088 && pThis->last_width == (unsigned)pThis->svga.uWidth
1089 && pThis->last_height == (unsigned)pThis->svga.uHeight
1090 )
1091 /* Nothing to do. */
1092 break;
1093
1094#ifdef IN_RING3
1095 if ( u32 == 1
1096 && pThis->svga.fEnabled == false)
1097 {
1098 /* Make a backup copy of the first 32k in order to save font data etc. */
1099 memcpy(pThis->svga.pFrameBufferBackup, pThis->vram_ptrR3, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
1100 }
1101
1102 pThis->svga.fEnabled = u32;
1103 if (pThis->svga.fEnabled)
1104 {
1105 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1106 && pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1107 && pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1108 {
1109 /* Keep the current mode. */
1110 pThis->svga.uWidth = pThis->pDrv->cx;
1111 pThis->svga.uHeight = pThis->pDrv->cy;
1112 pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1113 }
1114
1115 if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1116 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1117 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1118 {
1119 rc = vmsvgaChangeMode(pThis);
1120 AssertRCReturn(rc, rc);
1121 }
1122 Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
1123 uint32_t *pFIFO = pThis->svga.pFIFOR3;
1124 Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1125
1126 /* Disable or enable dirty page tracking according to the current fTraces value. */
1127 vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1128 }
1129 else
1130 {
1131 /* Restore the text mode backup. */
1132 memcpy(pThis->vram_ptrR3, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
1133
1134/* pThis->svga.uHeight = -1;
1135 pThis->svga.uWidth = -1;
1136 pThis->svga.uBpp = -1;
1137 pThis->svga.cbScanline = 0; */
1138 pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1139
1140 /* Enable dirty page tracking again when going into legacy mode. */
1141 vmsvgaSetTraces(pThis, true);
1142 }
1143#else
1144 rc = VINF_IOM_R3_IOPORT_WRITE;
1145#endif
1146 break;
1147
1148 case SVGA_REG_WIDTH:
1149 if (pThis->svga.uWidth != u32)
1150 {
1151 if (pThis->svga.fEnabled)
1152 {
1153#ifdef IN_RING3
1154 pThis->svga.uWidth = u32;
1155 rc = vmsvgaChangeMode(pThis);
1156 AssertRCReturn(rc, rc);
1157#else
1158 rc = VINF_IOM_R3_IOPORT_WRITE;
1159#endif
1160 }
1161 else
1162 pThis->svga.uWidth = u32;
1163 }
1164 /* else: nop */
1165 break;
1166
1167 case SVGA_REG_HEIGHT:
1168 if (pThis->svga.uHeight != u32)
1169 {
1170 if (pThis->svga.fEnabled)
1171 {
1172#ifdef IN_RING3
1173 pThis->svga.uHeight = u32;
1174 rc = vmsvgaChangeMode(pThis);
1175 AssertRCReturn(rc, rc);
1176#else
1177 rc = VINF_IOM_R3_IOPORT_WRITE;
1178#endif
1179 }
1180 else
1181 pThis->svga.uHeight = u32;
1182 }
1183 /* else: nop */
1184 break;
1185
1186 case SVGA_REG_DEPTH:
1187 /** @todo read-only?? */
1188 break;
1189
1190 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1191 if (pThis->svga.uBpp != u32)
1192 {
1193 if (pThis->svga.fEnabled)
1194 {
1195#ifdef IN_RING3
1196 pThis->svga.uBpp = u32;
1197 rc = vmsvgaChangeMode(pThis);
1198 AssertRCReturn(rc, rc);
1199#else
1200 rc = VINF_IOM_R3_IOPORT_WRITE;
1201#endif
1202 }
1203 else
1204 pThis->svga.uBpp = u32;
1205 }
1206 /* else: nop */
1207 break;
1208
1209 case SVGA_REG_PSEUDOCOLOR:
1210 break;
1211
1212 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1213#ifdef IN_RING3
1214 pThis->svga.fConfigured = u32;
1215 /* Disabling the FIFO enables tracing (dirty page detection) by default. */
1216 if (!pThis->svga.fConfigured)
1217 {
1218 pThis->svga.fTraces = true;
1219 }
1220 vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1221#else
1222 rc = VINF_IOM_R3_IOPORT_WRITE;
1223#endif
1224 break;
1225
1226 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1227 if ( pThis->svga.fEnabled
1228 && pThis->svga.fConfigured)
1229 {
1230#if defined(IN_RING3) || defined(IN_RING0)
1231 Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1232 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE | VMSVGA_BUSY_F_FIFO);
1233 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1234 vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1235
1236 /* Kick the FIFO thread to start processing commands again. */
1237 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1238#else
1239 rc = VINF_IOM_R3_IOPORT_WRITE;
1240#endif
1241 }
1242 /* else nothing to do. */
1243 else
1244 Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1245
1246 break;
1247
1248 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1249 break;
1250
1251 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1252 pThis->svga.u32GuestId = u32;
1253 break;
1254
1255 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1256 pThis->svga.u32PitchLock = u32;
1257 break;
1258
1259 case SVGA_REG_IRQMASK: /* Interrupt mask */
1260 pThis->svga.u32IrqMask = u32;
1261
1262 /* Irq pending after the above change? */
1263 if (pThis->svga.u32IrqStatus & u32)
1264 {
1265 Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1266 PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1267 }
1268 else
1269 PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1270 break;
1271
1272 /* Mouse cursor support */
1273 case SVGA_REG_CURSOR_ID:
1274 case SVGA_REG_CURSOR_X:
1275 case SVGA_REG_CURSOR_Y:
1276 case SVGA_REG_CURSOR_ON:
1277 break;
1278
1279 /* Legacy multi-monitor support */
1280 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1281 break;
1282 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1283 break;
1284 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1285 break;
1286 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1287 break;
1288 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1289 break;
1290 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1291 break;
1292 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1293 break;
1294#ifdef VBOX_WITH_VMSVGA3D
1295 /* See "Guest memory regions" below. */
1296 case SVGA_REG_GMR_ID:
1297 pThis->svga.u32CurrentGMRId = u32;
1298 break;
1299
1300 case SVGA_REG_GMR_DESCRIPTOR:
1301# ifndef IN_RING3
1302 rc = VINF_IOM_R3_IOPORT_WRITE;
1303 break;
1304# else /* IN_RING3 */
1305 {
1306 SVGAGuestMemDescriptor desc;
1307 RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1308 RTGCPHYS GCPhysBase = GCPhys;
1309 uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1310 uint32_t cDescriptorsAllocated = 16;
1311 uint32_t iDescriptor = 0;
1312
1313 /* Validate current GMR id. */
1314 AssertBreak(idGMR < VMSVGA_MAX_GMR_IDS);
1315
1316 /* Free the old GMR if present. */
1317 vmsvgaGMRFree(pThis, idGMR);
1318
1319 /* Just undefine the GMR? */
1320 if (GCPhys == 0)
1321 break;
1322
1323 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1324 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1325
1326 /* Never cross a page boundary automatically. */
1327 while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1328 {
1329 /* Read descriptor. */
1330 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1331 AssertRCBreak(rc);
1332
1333 if ( desc.ppn == 0
1334 && desc.numPages == 0)
1335 break; /* terminator */
1336
1337 if ( desc.ppn != 0
1338 && desc.numPages == 0)
1339 {
1340 /* Pointer to the next physical page of descriptors. */
1341 GCPhys = GCPhysBase = desc.ppn << PAGE_SHIFT;
1342 }
1343 else
1344 {
1345 if (iDescriptor == cDescriptorsAllocated)
1346 {
1347 cDescriptorsAllocated += 16;
1348 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemRealloc(pSVGAState->aGMR[idGMR].paDesc, cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1349 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1350 }
1351
1352 pSVGAState->aGMR[idGMR].paDesc[iDescriptor].GCPhys = desc.ppn << PAGE_SHIFT;
1353 pSVGAState->aGMR[idGMR].paDesc[iDescriptor++].numPages = desc.numPages;
1354 pSVGAState->aGMR[idGMR].cbTotal += desc.numPages * PAGE_SIZE;
1355
1356 /* Continue with the next descriptor. */
1357 GCPhys += sizeof(desc);
1358 }
1359 }
1360 pSVGAState->aGMR[idGMR].numDescriptors = iDescriptor;
1361 Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x\n", idGMR, iDescriptor, pSVGAState->aGMR[idGMR].cbTotal));
1362
1363 if (!pSVGAState->aGMR[idGMR].numDescriptors)
1364 {
1365 AssertFailed();
1366 RTMemFree(pSVGAState->aGMR[idGMR].paDesc);
1367 pSVGAState->aGMR[idGMR].paDesc = NULL;
1368 }
1369 AssertRC(rc);
1370 break;
1371 }
1372# endif /* IN_RING3 */
1373#endif // VBOX_WITH_VMSVGA3D
1374
1375 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1376 if (pThis->svga.fTraces == u32)
1377 break; /* nothing to do */
1378
1379#ifdef IN_RING3
1380 vmsvgaSetTraces(pThis, !!u32);
1381#else
1382 rc = VINF_IOM_R3_IOPORT_WRITE;
1383#endif
1384 break;
1385
1386 case SVGA_REG_TOP: /* Must be 1 more than the last register */
1387 break;
1388
1389 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
1390 break;
1391 /* Next 768 (== 256*3) registers exist for colormap */
1392
1393 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1394 Log(("Write to deprecated register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
1395 break;
1396
1397 case SVGA_REG_FB_START:
1398 case SVGA_REG_MEM_START:
1399 case SVGA_REG_HOST_BITS_PER_PIXEL:
1400 case SVGA_REG_MAX_WIDTH:
1401 case SVGA_REG_MAX_HEIGHT:
1402 case SVGA_REG_VRAM_SIZE:
1403 case SVGA_REG_FB_SIZE:
1404 case SVGA_REG_CAPABILITIES:
1405 case SVGA_REG_MEM_SIZE:
1406 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1407 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1408 case SVGA_REG_BYTES_PER_LINE:
1409 case SVGA_REG_FB_OFFSET:
1410 case SVGA_REG_RED_MASK:
1411 case SVGA_REG_GREEN_MASK:
1412 case SVGA_REG_BLUE_MASK:
1413 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1414 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1415 case SVGA_REG_GMR_MAX_IDS:
1416 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1417 /* Read only - ignore. */
1418 Log(("Write to R/O register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
1419 break;
1420
1421 default:
1422 if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE
1423 && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
1424 {
1425 pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE] = u32;
1426 }
1427 break;
1428 }
1429 return rc;
1430}
1431
1432/**
1433 * Port I/O Handler for IN operations.
1434 *
1435 * @returns VINF_SUCCESS or VINF_EM_*.
1436 * @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1437 *
1438 * @param pDevIns The device instance.
1439 * @param pvUser User argument.
1440 * @param uPort Port number used for the IN operation.
1441 * @param pu32 Where to store the result. This is always a 32-bit
1442 * variable regardless of what @a cb might say.
1443 * @param cb Number of bytes read.
1444 */
1445PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1446{
1447 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1448 int rc = VINF_SUCCESS;
1449
1450 /* Ignore non-dword accesses. */
1451 if (cb != 4)
1452 {
1453 Log(("Ignoring non-dword read at %x cb=%d\n", Port, cb));
1454 *pu32 = ~0;
1455 return VINF_SUCCESS;
1456 }
1457
1458 switch (Port - pThis->svga.BasePort)
1459 {
1460 case SVGA_INDEX_PORT:
1461 *pu32 = pThis->svga.u32IndexReg;
1462 break;
1463
1464 case SVGA_VALUE_PORT:
1465 return vmsvgaReadPort(pThis, pu32);
1466
1467 case SVGA_BIOS_PORT:
1468 Log(("Ignoring BIOS port read\n"));
1469 *pu32 = 0;
1470 break;
1471
1472 case SVGA_IRQSTATUS_PORT:
1473 LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1474 *pu32 = pThis->svga.u32IrqStatus;
1475 break;
1476 }
1477 return rc;
1478}
1479
1480/**
1481 * Port I/O Handler for OUT operations.
1482 *
1483 * @returns VINF_SUCCESS or VINF_EM_*.
1484 *
1485 * @param pDevIns The device instance.
1486 * @param pvUser User argument.
1487 * @param uPort Port number used for the OUT operation.
1488 * @param u32 The value to output.
1489 * @param cb The value size in bytes.
1490 */
1491PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1492{
1493 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1494 int rc = VINF_SUCCESS;
1495
1496 /* Ignore non-dword accesses. */
1497 if (cb != 4)
1498 {
1499 Log(("Ignoring non-dword write at %x val=%x cb=%d\n", Port, u32, cb));
1500 return VINF_SUCCESS;
1501 }
1502
1503 switch (Port - pThis->svga.BasePort)
1504 {
1505 case SVGA_INDEX_PORT:
1506 pThis->svga.u32IndexReg = u32;
1507 break;
1508
1509 case SVGA_VALUE_PORT:
1510 return vmsvgaWritePort(pThis, u32);
1511
1512 case SVGA_BIOS_PORT:
1513 Log(("Ignoring BIOS port write (val=%x)\n", u32));
1514 break;
1515
1516 case SVGA_IRQSTATUS_PORT:
1517 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
1518 ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
1519 /* Clear the irq in case all events have been cleared. */
1520 if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
1521 {
1522 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
1523 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1524 }
1525 break;
1526 }
1527 return rc;
1528}
1529
1530#ifdef DEBUG_FIFO_ACCESS
1531
1532# ifdef IN_RING3
1533/**
1534 * Handle LFB access.
1535 * @returns VBox status code.
1536 * @param pVM VM handle.
1537 * @param pThis VGA device instance data.
1538 * @param GCPhys The access physical address.
1539 * @param fWriteAccess Read or write access
1540 */
1541static int vmsvgaFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
1542{
1543 RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
1544 uint32_t *pFIFO = pThis->svga.pFIFOR3;
1545
1546 switch (GCPhysOffset >> 2)
1547 {
1548 case SVGA_FIFO_MIN:
1549 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1550 break;
1551 case SVGA_FIFO_MAX:
1552 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1553 break;
1554 case SVGA_FIFO_NEXT_CMD:
1555 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1556 break;
1557 case SVGA_FIFO_STOP:
1558 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1559 break;
1560 case SVGA_FIFO_CAPABILITIES:
1561 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1562 break;
1563 case SVGA_FIFO_FLAGS:
1564 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1565 break;
1566 case SVGA_FIFO_FENCE:
1567 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1568 break;
1569 case SVGA_FIFO_3D_HWVERSION:
1570 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1571 break;
1572 case SVGA_FIFO_PITCHLOCK:
1573 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1574 break;
1575 case SVGA_FIFO_CURSOR_ON:
1576 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1577 break;
1578 case SVGA_FIFO_CURSOR_X:
1579 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1580 break;
1581 case SVGA_FIFO_CURSOR_Y:
1582 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1583 break;
1584 case SVGA_FIFO_CURSOR_COUNT:
1585 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1586 break;
1587 case SVGA_FIFO_CURSOR_LAST_UPDATED:
1588 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1589 break;
1590 case SVGA_FIFO_RESERVED:
1591 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1592 break;
1593 case SVGA_FIFO_CURSOR_SCREEN_ID:
1594 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1595 break;
1596 case SVGA_FIFO_DEAD:
1597 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1598 break;
1599 case SVGA_FIFO_3D_HWVERSION_REVISED:
1600 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1601 break;
1602 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
1603 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1604 break;
1605 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
1606 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1607 break;
1608 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
1609 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1610 break;
1611 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
1612 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1613 break;
1614 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
1615 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1616 break;
1617 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
1618 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1619 break;
1620 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
1621 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1622 break;
1623 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
1624 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1625 break;
1626 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
1627 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1628 break;
1629 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
1630 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1631 break;
1632 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
1633 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1634 break;
1635 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
1636 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1637 break;
1638 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
1639 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1640 break;
1641 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
1642 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1643 break;
1644 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
1645 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1646 break;
1647 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
1648 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1649 break;
1650 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
1651 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1652 break;
1653 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
1654 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1655 break;
1656 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
1657 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1658 break;
1659 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
1660 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1661 break;
1662 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
1663 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1664 break;
1665 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
1666 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1667 break;
1668 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
1669 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1670 break;
1671 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
1672 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1673 break;
1674 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
1675 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1676 break;
1677 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
1678 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1679 break;
1680 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
1681 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1682 break;
1683 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
1684 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1685 break;
1686 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
1687 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1688 break;
1689 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
1690 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1691 break;
1692 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
1693 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1694 break;
1695 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
1696 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1697 break;
1698 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
1699 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1700 break;
1701 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
1702 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1703 break;
1704 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
1705 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1706 break;
1707 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
1708 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1709 break;
1710 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
1711 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1712 break;
1713 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
1714 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1715 break;
1716 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
1717 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1718 break;
1719 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
1720 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1721 break;
1722 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
1723 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1724 break;
1725 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
1726 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1727 break;
1728 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
1729 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1730 break;
1731 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
1732 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1733 break;
1734 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
1735 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1736 break;
1737 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
1738 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1739 break;
1740 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
1741 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1742 break;
1743 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
1744 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1745 break;
1746 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
1747 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1748 break;
1749 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
1750 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1751 break;
1752 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
1753 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1754 break;
1755 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
1756 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1757 break;
1758 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
1759 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1760 break;
1761 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
1762 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1763 break;
1764 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
1765 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1766 break;
1767 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
1768 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1769 break;
1770 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
1771 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1772 break;
1773 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
1774 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1775 break;
1776 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
1777 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1778 break;
1779 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
1780 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1781 break;
1782 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
1783 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1784 break;
1785 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
1786 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1787 break;
1788 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
1789 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1790 break;
1791 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
1792 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1793 break;
1794 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
1795 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1796 break;
1797 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
1798 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1799 break;
1800 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
1801 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1802 break;
1803 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
1804 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1805 break;
1806 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
1807 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1808 break;
1809 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
1810 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1811 break;
1812 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
1813 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1814 break;
1815 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
1816 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1817 break;
1818 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
1819 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1820 break;
1821 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
1822 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1823 break;
1824 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
1825 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1826 break;
1827 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
1828 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1829 break;
1830 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
1831 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1832 break;
1833 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
1834 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1835 break;
1836 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
1837 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1838 break;
1839 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
1840 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1841 break;
1842 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
1843 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1844 break;
1845 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
1846 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1847 break;
1848 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
1849 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1850 break;
1851 case SVGA_FIFO_3D_CAPS_LAST:
1852 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1853 break;
1854 case SVGA_FIFO_GUEST_3D_HWVERSION:
1855 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1856 break;
1857 case SVGA_FIFO_FENCE_GOAL:
1858 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1859 break;
1860 case SVGA_FIFO_BUSY:
1861 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1862 break;
1863 default:
1864 Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
1865 break;
1866 }
1867
1868 return VINF_EM_RAW_EMULATE_INSTR;
1869}
1870
1871/**
1872 * HC access handler for the FIFO.
1873 *
1874 * @returns VINF_SUCCESS if the handler have carried out the operation.
1875 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1876 * @param pVM VM Handle.
1877 * @param pVCpu The cross context CPU structure for the calling EMT.
1878 * @param GCPhys The physical address the guest is writing to.
1879 * @param pvPhys The HC mapping of that address.
1880 * @param pvBuf What the guest is reading/writing.
1881 * @param cbBuf How much it's reading/writing.
1882 * @param enmAccessType The access type.
1883 * @param enmOrigin Who is making the access.
1884 * @param pvUser User argument.
1885 */
1886static DECLCALLBACK(int) vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
1887 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1888{
1889 PVGASTATE pThis = (PVGASTATE)pvUser;
1890 int rc;
1891 Assert(pThis);
1892 Assert(GCPhys >= pThis->GCPhysVRAM);
1893 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
1894
1895 rc = vmsvgaFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
1896 if (RT_SUCCESS(rc))
1897 return VINF_PGM_HANDLER_DO_DEFAULT;
1898 AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
1899 return rc;
1900}
1901
1902# endif /* IN_RING3 */
1903#endif /* DEBUG_FIFO_ACCESS */
1904
1905#ifdef DEBUG_GMR_ACCESS
1906/**
1907 * HC access handler for the FIFO.
1908 *
1909 * @returns VINF_SUCCESS if the handler have carried out the operation.
1910 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1911 * @param pVM VM Handle.
1912 * @param pVCpu The cross context CPU structure for the calling EMT.
1913 * @param GCPhys The physical address the guest is writing to.
1914 * @param pvPhys The HC mapping of that address.
1915 * @param pvBuf What the guest is reading/writing.
1916 * @param cbBuf How much it's reading/writing.
1917 * @param enmAccessType The access type.
1918 * @param enmOrigin Who is making the access.
1919 * @param pvUser User argument.
1920 */
1921static DECLCALLBACK(int) vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
1922 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1923{
1924 PVGASTATE pThis = (PVGASTATE)pvUser;
1925 Assert(pThis);
1926 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
1927 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
1928
1929 Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
1930
1931 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
1932 {
1933 PGMR pGMR = &pSVGAState->aGMR[i];
1934
1935 if (pGMR->numDescriptors)
1936 {
1937 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
1938 {
1939 if ( GCPhys >= pGMR->paDesc[j].GCPhys
1940 && GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
1941 {
1942 /*
1943 * Turn off the write handler for this particular page and make it R/W.
1944 * Then return telling the caller to restart the guest instruction.
1945 */
1946 int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
1947 goto end;
1948 }
1949 }
1950 }
1951 }
1952end:
1953 return VINF_PGM_HANDLER_DO_DEFAULT;
1954}
1955
1956# ifdef IN_RING3
1957
1958/* Callback handler for VMR3ReqCallWait */
1959static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
1960{
1961 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1962 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
1963 PGMR pGMR = &pSVGAState->aGMR[gmrId];
1964 int rc;
1965
1966 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
1967 {
1968 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
1969 pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
1970 pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
1971 AssertRC(rc);
1972 }
1973 return VINF_SUCCESS;
1974}
1975
1976/* Callback handler for VMR3ReqCallWait */
1977static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
1978{
1979 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1980 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
1981 PGMR pGMR = &pSVGAState->aGMR[gmrId];
1982
1983 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
1984 {
1985 int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
1986 AssertRC(rc);
1987 }
1988 return VINF_SUCCESS;
1989}
1990
1991/* Callback handler for VMR3ReqCallWait */
1992static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
1993{
1994 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
1995
1996 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
1997 {
1998 PGMR pGMR = &pSVGAState->aGMR[i];
1999
2000 if (pGMR->numDescriptors)
2001 {
2002 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2003 {
2004 int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2005 AssertRC(rc);
2006 }
2007 }
2008 }
2009 return VINF_SUCCESS;
2010}
2011
2012# endif /* IN_RING3 */
2013#endif /* DEBUG_GMR_ACCESS */
2014
2015/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2016
2017#ifdef IN_RING3
2018
2019/**
2020 * Marks the FIFO non-busy, notifying any waiting EMTs.
2021 *
2022 * @param pThis The VGA state.
2023 * @param pSVGAState Pointer to the ring-3 only SVGA state data.
2024 * @param offFifoMin The start byte offset of the command FIFO.
2025 */
2026static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGASTATE pSVGAState, uint32_t offFifoMin)
2027{
2028 ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
2029 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2030 vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
2031
2032 /* Wake up any waiting EMTs. */
2033 if (pSVGAState->cBusyDelayedEmts > 0)
2034 {
2035#ifdef VMSVGA_USE_EMT_HALT_CODE
2036 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
2037 VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
2038 if (idCpu != NIL_VMCPUID)
2039 {
2040 VMR3NotifyCpuDeviceReady(pVM, idCpu);
2041 while (idCpu-- > 0)
2042 if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
2043 VMR3NotifyCpuDeviceReady(pVM, idCpu);
2044 }
2045#else
2046 int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
2047 AssertRC(rc2);
2048#endif
2049 }
2050}
2051
2052/**
2053 * Reads (more) payload into the command buffer.
2054 *
2055 * @returns pbBounceBuf on success
2056 * @retval (void *)1 if the thread was requested to stop.
2057 * @retval NULL on FIFO error.
2058 *
2059 * @param cbPayloadReq The number of bytes of payload requested.
2060 * @param pFIFO The FIFO.
2061 * @param offCurrentCmd The FIFO byte offset of the current command.
2062 * @param offFifoMin The start byte offset of the command FIFO.
2063 * @param offFifoMax The end byte offset of the command FIFO.
2064 * @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
2065 * always sufficient size.
2066 * @param pcbAlreadyRead How much payload we've already read into the bounce
2067 * buffer. (We will NEVER re-read anything.)
2068 * @param pThread The calling PDM thread handle.
2069 * @param pThis The VGA state.
2070 * @param pSVGAState Pointer to the ring-3 only SVGA state data. For
2071 * statistics collection.
2072 */
2073static void *vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t volatile *pFIFO,
2074 uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
2075 uint8_t *pbBounceBuf, uint32_t *pcbAlreadyRead,
2076 PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGASTATE pSVGAState)
2077{
2078 Assert(pbBounceBuf);
2079 Assert(pcbAlreadyRead);
2080 Assert(offFifoMin < offFifoMax);
2081 Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
2082 Assert(offFifoMax <= VMSVGA_FIFO_SIZE);
2083
2084 /*
2085 * Check if the requested payload size has already been satisfied .
2086 * .
2087 * When called to read more, the caller is responsible for making sure the .
2088 * new command size (cbRequsted) never is smaller than what has already .
2089 * been read.
2090 */
2091 uint32_t cbAlreadyRead = *pcbAlreadyRead;
2092 if (cbPayloadReq <= cbAlreadyRead)
2093 {
2094 AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
2095 return pbBounceBuf;
2096 }
2097
2098 /*
2099 * Commands bigger than the fifo buffer are invalid.
2100 */
2101 uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
2102 AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
2103 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
2104 NULL);
2105
2106 /*
2107 * Move offCurrentCmd past the command dword.
2108 */
2109 offCurrentCmd += sizeof(uint32_t);
2110 if (offCurrentCmd >= offFifoMax)
2111 offCurrentCmd = offFifoMin;
2112
2113 /*
2114 * Do we have sufficient payload data available already?
2115 */
2116 uint32_t cbAfter, cbBefore;
2117 uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2118 if (offNextCmd > offCurrentCmd)
2119 {
2120 if (RT_LIKELY(offNextCmd < offFifoMax))
2121 cbAfter = offNextCmd - offCurrentCmd;
2122 else
2123 {
2124 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2125 LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2126 offNextCmd, offFifoMin, offFifoMax));
2127 cbAfter = offFifoMax - offCurrentCmd;
2128 }
2129 cbBefore = 0;
2130 }
2131 else
2132 {
2133 cbAfter = offFifoMax - offCurrentCmd;
2134 if (offNextCmd >= offFifoMin)
2135 cbBefore = offNextCmd - offFifoMin;
2136 else
2137 {
2138 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2139 LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2140 offNextCmd, offFifoMin, offFifoMax));
2141 cbBefore = 0;
2142 }
2143 }
2144 if (cbAfter + cbBefore < cbPayloadReq)
2145 {
2146 /*
2147 * Insufficient, must wait for it to arrive.
2148 */
2149 STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
2150 for (uint32_t i = 0;; i++)
2151 {
2152 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2153 {
2154 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2155 return (void *)(uintptr_t)1;
2156 }
2157 Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
2158 cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
2159
2160 SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
2161
2162 offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2163 if (offNextCmd > offCurrentCmd)
2164 {
2165 cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
2166 cbBefore = 0;
2167 }
2168 else
2169 {
2170 cbAfter = offFifoMax - offCurrentCmd;
2171 cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
2172 }
2173
2174 if (cbAfter + cbBefore >= cbPayloadReq)
2175 break;
2176 }
2177 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2178 }
2179
2180 /*
2181 * Copy out the memory and update what pcbAlreadyRead points to.
2182 */
2183 if (cbAfter >= cbPayloadReq)
2184 memcpy(pbBounceBuf + cbAlreadyRead,
2185 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
2186 cbPayloadReq - cbAlreadyRead);
2187 else
2188 {
2189 LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
2190 if (cbAlreadyRead < cbAfter)
2191 {
2192 memcpy(pbBounceBuf + cbAlreadyRead,
2193 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
2194 cbAfter - cbAlreadyRead);
2195 cbAlreadyRead = cbAfter;
2196 }
2197 memcpy(pbBounceBuf + cbAlreadyRead,
2198 (uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
2199 cbPayloadReq - cbAlreadyRead);
2200 }
2201 *pcbAlreadyRead = cbPayloadReq;
2202 return pbBounceBuf;
2203}
2204
2205/* The async FIFO handling thread. */
2206static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2207{
2208 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
2209 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
2210 int rc;
2211
2212 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2213 return VINF_SUCCESS;
2214
2215 /*
2216 * Signal the semaphore to make sure we don't wait for 250 after a
2217 * suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
2218 */
2219 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2220
2221 /*
2222 * Allocate a bounce buffer for command we get from the FIFO.
2223 * (All code must return via the end of the function to free this buffer.)
2224 */
2225 uint8_t *pbBounceBuf = (uint8_t *)RTMemAllocZ(VMSVGA_FIFO_SIZE);
2226 AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
2227
2228 LogFlow(("vmsvgaFIFOLoop: started loop\n"));
2229 uint32_t volatile * const pFIFO = pThis->svga.pFIFOR3;
2230 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2231 {
2232# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
2233 /*
2234 * Should service the run loop every so often.
2235 */
2236 if (pThis->svga.f3DEnabled)
2237 vmsvga3dCocoaServiceRunLoop();
2238# endif
2239
2240 /*
2241 * Wait for at most 250 ms to start polling.
2242 */
2243 rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, 250);
2244 AssertBreak(RT_SUCCESS(rc) || rc == VERR_TIMEOUT || rc == VERR_INTERRUPTED);
2245 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2246 {
2247 LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
2248 break;
2249 }
2250 if (rc == VERR_TIMEOUT)
2251 {
2252 if (pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
2253 continue;
2254 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
2255
2256 Log(("vmsvgaFIFOLoop: timeout\n"));
2257 }
2258 else if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
2259 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
2260
2261 Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
2262 Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
2263 Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
2264
2265 /*
2266 * Handle external commands.
2267 */
2268 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
2269 {
2270 switch (pThis->svga.u8FIFOExtCommand)
2271 {
2272 case VMSVGA_FIFO_EXTCMD_RESET:
2273 Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2274# ifdef VBOX_WITH_VMSVGA3D
2275 if (pThis->svga.f3DEnabled)
2276 {
2277 /* The 3d subsystem must be reset from the fifo thread. */
2278 vmsvga3dReset(pThis);
2279 }
2280# endif
2281 break;
2282
2283 case VMSVGA_FIFO_EXTCMD_TERMINATE:
2284 Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2285# ifdef VBOX_WITH_VMSVGA3D
2286 if (pThis->svga.f3DEnabled)
2287 {
2288 /* The 3d subsystem must be shut down from the fifo thread. */
2289 vmsvga3dTerminate(pThis);
2290 }
2291# endif
2292 break;
2293
2294 case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2295 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2296# ifdef VBOX_WITH_VMSVGA3D
2297 vmsvga3dSaveExec(pThis, (PSSMHANDLE)pThis->svga.pFIFOExtCmdParam);
2298# endif
2299 break;
2300
2301 case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2302 {
2303 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2304# ifdef VBOX_WITH_VMSVGA3D
2305 PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pFIFOExtCmdParam;
2306 vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2307# endif
2308 break;
2309 }
2310 }
2311
2312 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2313
2314 /* Signal the end of the external command. */
2315 RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2316 continue;
2317 }
2318
2319 if ( !pThis->svga.fEnabled
2320 || !pThis->svga.fConfigured)
2321 {
2322 vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
2323 continue; /* device not enabled. */
2324 }
2325
2326 /*
2327 * Get and check the min/max values. We ASSUME that they will remain
2328 * unchanged while we process requests. A further ASSUMPTION is that
2329 * the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
2330 * we don't read it back while in the loop.
2331 */
2332 uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
2333 uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
2334 uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
2335 if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
2336 || offFifoMax <= offFifoMin
2337 || offFifoMax > VMSVGA_FIFO_SIZE
2338 || (offFifoMax & 3) != 0
2339 || (offFifoMin & 3) != 0
2340 || offCurrentCmd < offFifoMin
2341 || offCurrentCmd > offFifoMax))
2342 {
2343 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2344 LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
2345 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
2346 continue;
2347 }
2348 if (RT_UNLIKELY(offCurrentCmd & 3))
2349 {
2350 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2351 LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
2352 offCurrentCmd = ~UINT32_C(3);
2353 }
2354
2355/**
2356 * Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
2357 *
2358 * Will break out of the switch on failure.
2359 * Will restart and quit the loop if the thread was requested to stop.
2360 *
2361 * @param a_cbPayloadReq How much payload to fetch.
2362 * @remarks Access a bunch of variables in the current scope!
2363 */
2364# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
2365 if (1) { \
2366 (a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
2367 pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
2368 if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
2369 } else do {} while (0)
2370/**
2371 * Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
2372 * buffer after figuring out the actual command size.
2373 * Will break out of the switch on failure.
2374 * @param a_cbPayloadReq How much payload to fetch.
2375 * @remarks Access a bunch of variables in the current scope!
2376 */
2377# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
2378 if (1) { \
2379 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
2380 } else do {} while (0)
2381
2382 /*
2383 * Mark the FIFO as busy.
2384 */
2385 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
2386 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2387 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
2388
2389 /*
2390 * Execute all queued FIFO commands.
2391 * Quit if pending external command or changes in the thread state.
2392 */
2393 bool fDone = false;
2394 while ( !(fDone = pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd)
2395 && pThread->enmState == PDMTHREADSTATE_RUNNING)
2396 {
2397 uint32_t cbPayload = 0;
2398 uint32_t u32IrqStatus = 0;
2399 bool fTriggerIrq = false;
2400
2401 Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
2402
2403 /* First check any pending actions. */
2404 if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
2405# ifdef VBOX_WITH_VMSVGA3D
2406 vmsvga3dChangeMode(pThis);
2407# else
2408 {/*nothing*/}
2409# endif
2410 /* Check for pending external commands. */
2411 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
2412 break;
2413
2414 /*
2415 * Process the command.
2416 */
2417 SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
2418 LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
2419 offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
2420 switch (enmCmdId)
2421 {
2422 case SVGA_CMD_INVALID_CMD:
2423 /* Nothing to do. */
2424 break;
2425
2426 case SVGA_CMD_FENCE:
2427 {
2428 SVGAFifoCmdFence *pCmdFence;
2429 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
2430 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
2431 {
2432 Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
2433 pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
2434
2435 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
2436 {
2437 Log(("vmsvgaFIFOLoop: any fence irq\n"));
2438 u32IrqStatus |= SVGA_IRQFLAG_ANY_FENCE;
2439 }
2440 else
2441 if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
2442 && (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
2443 && pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
2444 {
2445 Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
2446 u32IrqStatus |= SVGA_IRQFLAG_FENCE_GOAL;
2447 }
2448 }
2449 else
2450 Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
2451 break;
2452 }
2453 case SVGA_CMD_UPDATE:
2454 case SVGA_CMD_UPDATE_VERBOSE:
2455 {
2456 SVGAFifoCmdUpdate *pUpdate;
2457 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
2458 Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
2459 vgaR3UpdateDisplay(pThis, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
2460 break;
2461 }
2462
2463 case SVGA_CMD_DEFINE_CURSOR:
2464 {
2465 /* Followed by bitmap data. */
2466 SVGAFifoCmdDefineCursor *pCursor;
2467 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
2468 AssertFailed(); /** @todo implement when necessary. */
2469 break;
2470 }
2471
2472 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
2473 {
2474 /* Followed by bitmap data. */
2475 uint32_t cbCursorShape, cbAndMask;
2476 uint8_t *pCursorCopy;
2477 uint32_t cbCmd;
2478
2479 SVGAFifoCmdDefineAlphaCursor *pCursor;
2480 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
2481
2482 Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
2483
2484 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
2485 AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
2486
2487 /* Refetch the bitmap data as well. */
2488 cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
2489 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
2490 /** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
2491
2492 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
2493 cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
2494 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
2495 cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
2496
2497 pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
2498 AssertBreak(pCursorCopy);
2499
2500 Log2(("Cursor data:\n%.*Rhxd\n", pCursor->width * pCursor->height * sizeof(uint32_t), pCursor+1));
2501
2502 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
2503 memset(pCursorCopy, 0xff, cbAndMask);
2504 /* Colour data */
2505 memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
2506
2507 rc = pThis->pDrv->pfnVBVAMousePointerShape (pThis->pDrv,
2508 true,
2509 true,
2510 pCursor->hotspotX,
2511 pCursor->hotspotY,
2512 pCursor->width,
2513 pCursor->height,
2514 pCursorCopy);
2515 AssertRC(rc);
2516
2517 if (pSVGAState->Cursor.fActive)
2518 RTMemFree(pSVGAState->Cursor.pData);
2519
2520 pSVGAState->Cursor.fActive = true;
2521 pSVGAState->Cursor.xHotspot = pCursor->hotspotX;
2522 pSVGAState->Cursor.yHotspot = pCursor->hotspotY;
2523 pSVGAState->Cursor.width = pCursor->width;
2524 pSVGAState->Cursor.height = pCursor->height;
2525 pSVGAState->Cursor.cbData = cbCursorShape;
2526 pSVGAState->Cursor.pData = pCursorCopy;
2527 break;
2528 }
2529
2530 case SVGA_CMD_ESCAPE:
2531 {
2532 /* Followed by nsize bytes of data. */
2533 SVGAFifoCmdEscape *pEscape;
2534 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
2535
2536 /* Refetch the command buffer with the variable data; undo size increase (ugly) */
2537 AssertBreak(pEscape->size < VMSVGA_FIFO_SIZE);
2538 uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
2539 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
2540
2541 if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
2542 {
2543 AssertBreak(pEscape->size >= sizeof(uint32_t));
2544 uint32_t cmd = *(uint32_t *)(pEscape + 1);
2545 Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
2546
2547 switch (cmd)
2548 {
2549 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
2550 {
2551 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pEscape + 1);
2552 AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
2553 uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
2554
2555 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
2556 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
2557 {
2558 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
2559 }
2560 break;
2561 }
2562
2563 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
2564 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pEscape + 1);
2565 AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
2566 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
2567 break;
2568 }
2569 }
2570 else
2571 Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
2572
2573 break;
2574 }
2575# ifdef VBOX_WITH_VMSVGA3D
2576 case SVGA_CMD_DEFINE_GMR2:
2577 {
2578 SVGAFifoCmdDefineGMR2 *pCmd;
2579 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
2580 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
2581
2582 /* Validate current GMR id. */
2583 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2584 AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
2585
2586 if (!pCmd->numPages)
2587 {
2588 vmsvgaGMRFree(pThis, pCmd->gmrId);
2589 }
2590 else
2591 {
2592 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2593 pGMR->cMaxPages = pCmd->numPages;
2594 }
2595 /* everything done in remap */
2596 break;
2597 }
2598
2599 case SVGA_CMD_REMAP_GMR2:
2600 {
2601 /* Followed by page descriptors or guest ptr. */
2602 SVGAFifoCmdRemapGMR2 *pCmd;
2603 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
2604 uint32_t cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
2605 uint32_t cbCmd;
2606 uint64_t *paNewPage64 = NULL;
2607
2608 Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
2609 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2610
2611 /* Calculate the size of what comes after next and fetch it. */
2612 cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
2613 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
2614 cbCmd += sizeof(SVGAGuestPtr);
2615 else
2616 if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
2617 {
2618 cbCmd += cbPageDesc;
2619 pCmd->numPages = 1;
2620 }
2621 else
2622 {
2623 AssertBreak(pCmd->numPages <= VMSVGA_FIFO_SIZE);
2624 cbCmd += cbPageDesc * pCmd->numPages;
2625 }
2626 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
2627
2628 /* Validate current GMR id. */
2629 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2630 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2631 AssertBreak(pCmd->offsetPages + pCmd->numPages <= pGMR->cMaxPages);
2632 AssertBreak(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
2633
2634 /* Save the old page descriptors as an array of page addresses (>> PAGE_SHIFT) */
2635 if (pGMR->paDesc)
2636 {
2637 uint32_t idxPage = 0;
2638 paNewPage64 = (uint64_t *)RTMemAllocZ(pGMR->cMaxPages * sizeof(uint64_t));
2639 AssertBreak(paNewPage64);
2640
2641 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2642 {
2643 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
2644 {
2645 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * PAGE_SIZE) >> PAGE_SHIFT;
2646 }
2647 }
2648 AssertBreak(idxPage == pGMR->cbTotal >> PAGE_SHIFT);
2649 }
2650
2651 /* Free the old GMR if present. */
2652 if (pGMR->paDesc)
2653 RTMemFree(pGMR->paDesc);
2654
2655 /* Allocate the maximum amount possible (everything non-continuous) */
2656 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->cMaxPages * sizeof(VMSVGAGMRDESCRIPTOR));
2657 AssertBreak(pGMR->paDesc);
2658
2659 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
2660 {
2661 /** @todo */
2662 AssertFailed();
2663 }
2664 else
2665 {
2666 uint32_t *pPage32 = (uint32_t *)(pCmd + 1);
2667 uint64_t *pPage64 = (uint64_t *)(pCmd + 1);
2668 uint32_t iDescriptor = 0;
2669 RTGCPHYS GCPhys;
2670 PVMSVGAGMRDESCRIPTOR paDescOld = NULL;
2671 bool fGCPhys64 = !!(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
2672
2673 if (paNewPage64)
2674 {
2675 /* Overwrite the old page array with the new page values. */
2676 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
2677 {
2678 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
2679 paNewPage64[i] = pPage64[i - pCmd->offsetPages];
2680 else
2681 paNewPage64[i] = pPage32[i - pCmd->offsetPages];
2682 }
2683 /* Use the updated page array instead of the command data. */
2684 fGCPhys64 = true;
2685 pPage64 = paNewPage64;
2686 pCmd->numPages = pGMR->cbTotal >> PAGE_SHIFT;
2687 }
2688
2689 if (fGCPhys64)
2690 GCPhys = (pPage64[0] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
2691 else
2692 GCPhys = pPage32[0] << PAGE_SHIFT;
2693
2694 pGMR->paDesc[0].GCPhys = GCPhys;
2695 pGMR->paDesc[0].numPages = 1;
2696 pGMR->cbTotal = PAGE_SIZE;
2697
2698 for (uint32_t i = 1; i < pCmd->numPages; i++)
2699 {
2700 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
2701 GCPhys = (pPage64[i] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
2702 else
2703 GCPhys = pPage32[i] << PAGE_SHIFT;
2704
2705 /* Continuous physical memory? */
2706 if (GCPhys == pGMR->paDesc[iDescriptor].GCPhys + pGMR->paDesc[iDescriptor].numPages * PAGE_SIZE)
2707 {
2708 Assert(pGMR->paDesc[iDescriptor].numPages);
2709 pGMR->paDesc[iDescriptor].numPages++;
2710 LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
2711 }
2712 else
2713 {
2714 iDescriptor++;
2715 pGMR->paDesc[iDescriptor].GCPhys = GCPhys;
2716 pGMR->paDesc[iDescriptor].numPages = 1;
2717 LogFlow(("Page %x GCPhys=%RGp\n", i, pGMR->paDesc[iDescriptor].GCPhys));
2718 }
2719
2720 pGMR->cbTotal += PAGE_SIZE;
2721 }
2722 LogFlow(("Nr of descriptors %x\n", iDescriptor + 1));
2723 pGMR->numDescriptors = iDescriptor + 1;
2724 }
2725
2726 if (paNewPage64)
2727 RTMemFree(paNewPage64);
2728
2729# ifdef DEBUG_GMR_ACCESS
2730 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
2731# endif
2732 break;
2733 }
2734# endif // VBOX_WITH_VMSVGA3D
2735 case SVGA_CMD_DEFINE_SCREEN:
2736 {
2737 /* Note! The size of this command is specified by the guest and depends on capabilities. */
2738 Assert(!(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT));
2739 SVGAFifoCmdDefineScreen *pCmd;
2740 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
2741 RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.structSize));
2742 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
2743
2744 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d)\n", pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y));
2745 if (pCmd->screen.flags & SVGA_SCREEN_HAS_ROOT)
2746 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_HAS_ROOT\n"));
2747 if (pCmd->screen.flags & SVGA_SCREEN_IS_PRIMARY)
2748 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_IS_PRIMARY\n"));
2749 if (pCmd->screen.flags & SVGA_SCREEN_FULLSCREEN_HINT)
2750 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_FULLSCREEN_HINT\n"));
2751 if (pCmd->screen.flags & SVGA_SCREEN_DEACTIVATE )
2752 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_DEACTIVATE \n"));
2753 if (pCmd->screen.flags & SVGA_SCREEN_BLANKING)
2754 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_BLANKING\n"));
2755
2756 /** @todo multi monitor support and screen object capabilities. */
2757 pThis->svga.uWidth = pCmd->screen.size.width;
2758 pThis->svga.uHeight = pCmd->screen.size.height;
2759 vmsvgaChangeMode(pThis);
2760 break;
2761 }
2762
2763 case SVGA_CMD_DESTROY_SCREEN:
2764 {
2765 SVGAFifoCmdDestroyScreen *pCmd;
2766 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
2767
2768 Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
2769 break;
2770 }
2771# ifdef VBOX_WITH_VMSVGA3D
2772 case SVGA_CMD_DEFINE_GMRFB:
2773 {
2774 SVGAFifoCmdDefineGMRFB *pCmd;
2775 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
2776
2777 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
2778 pSVGAState->GMRFB.ptr = pCmd->ptr;
2779 pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
2780 pSVGAState->GMRFB.format = pCmd->format;
2781 break;
2782 }
2783
2784 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
2785 {
2786 uint32_t width, height;
2787 SVGAFifoCmdBlitGMRFBToScreen *pCmd;
2788 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
2789
2790 Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
2791
2792 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
2793 AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pThis->svga.uBpp);
2794 AssertBreak(pCmd->destScreenId == 0);
2795
2796 if (pCmd->destRect.left < 0)
2797 pCmd->destRect.left = 0;
2798 if (pCmd->destRect.top < 0)
2799 pCmd->destRect.top = 0;
2800 if (pCmd->destRect.right < 0)
2801 pCmd->destRect.right = 0;
2802 if (pCmd->destRect.bottom < 0)
2803 pCmd->destRect.bottom = 0;
2804
2805 width = pCmd->destRect.right - pCmd->destRect.left;
2806 height = pCmd->destRect.bottom - pCmd->destRect.top;
2807
2808 if ( width == 0
2809 || height == 0)
2810 break; /* Nothing to do. */
2811
2812 /* Clip to screen dimensions. */
2813 if (width > pThis->svga.uWidth)
2814 width = pThis->svga.uWidth;
2815 if (height > pThis->svga.uHeight)
2816 height = pThis->svga.uHeight;
2817
2818 unsigned offsetSource = (pCmd->srcOrigin.x * pSVGAState->GMRFB.format.s.bitsPerPixel) / 8 + pSVGAState->GMRFB.bytesPerLine * pCmd->srcOrigin.y;
2819 unsigned offsetDest = (pCmd->destRect.left * RT_ALIGN(pThis->svga.uBpp, 8)) / 8 + pThis->svga.cbScanline * pCmd->destRect.top;
2820 unsigned cbCopyWidth = (width * RT_ALIGN(pThis->svga.uBpp, 8)) / 8;
2821
2822 AssertBreak(offsetDest < pThis->vram_size);
2823
2824 rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM, pThis->CTX_SUFF(vram_ptr) + offsetDest, pThis->svga.cbScanline, pSVGAState->GMRFB.ptr, offsetSource, pSVGAState->GMRFB.bytesPerLine, cbCopyWidth, height);
2825 AssertRC(rc);
2826 vgaR3UpdateDisplay(pThis, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right - pCmd->destRect.left, pCmd->destRect.bottom - pCmd->destRect.top);
2827 break;
2828 }
2829
2830 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
2831 {
2832 SVGAFifoCmdBlitScreenToGMRFB *pCmd;
2833 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
2834
2835 /* Note! This can fetch 3d render results as well!! */
2836 Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n", pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
2837 AssertFailed();
2838 break;
2839 }
2840# endif // VBOX_WITH_VMSVGA3D
2841 case SVGA_CMD_ANNOTATION_FILL:
2842 {
2843 SVGAFifoCmdAnnotationFill *pCmd;
2844 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
2845
2846 Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
2847 pSVGAState->colorAnnotation = pCmd->color;
2848 break;
2849 }
2850
2851 case SVGA_CMD_ANNOTATION_COPY:
2852 {
2853 SVGAFifoCmdAnnotationCopy *pCmd;
2854 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
2855
2856 Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
2857 AssertFailed();
2858 break;
2859 }
2860
2861 /** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
2862
2863 default:
2864# ifdef VBOX_WITH_VMSVGA3D
2865 if ( enmCmdId >= SVGA_3D_CMD_BASE
2866 && enmCmdId < SVGA_3D_CMD_MAX)
2867 {
2868 /* All 3d commands start with a common header, which defines the size of the command. */
2869 SVGA3dCmdHeader *pHdr;
2870 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
2871 AssertBreak(pHdr->size < VMSVGA_FIFO_SIZE);
2872 uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
2873 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
2874
2875/**
2876 * Check that the 3D command has at least a_cbMin of payload bytes after the
2877 * header. Will break out of the switch if it doesn't.
2878 */
2879# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
2880 AssertMsgBreak((a_cbMin) <= pHdr->size, ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin)))
2881 switch ((int)enmCmdId)
2882 {
2883 case SVGA_3D_CMD_SURFACE_DEFINE:
2884 {
2885 uint32_t cMipLevels;
2886 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)(pHdr + 1);
2887 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2888
2889 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
2890 rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0, SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
2891# ifdef DEBUG_GMR_ACCESS
2892 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
2893# endif
2894 break;
2895 }
2896
2897 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
2898 {
2899 uint32_t cMipLevels;
2900 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)(pHdr + 1);
2901 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2902
2903 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
2904 rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face, pCmd->multisampleCount, pCmd->autogenFilter, cMipLevels, (SVGA3dSize *)(pCmd + 1));
2905 break;
2906 }
2907
2908 case SVGA_3D_CMD_SURFACE_DESTROY:
2909 {
2910 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)(pHdr + 1);
2911 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2912 rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
2913 break;
2914 }
2915
2916 case SVGA_3D_CMD_SURFACE_COPY:
2917 {
2918 uint32_t cCopyBoxes;
2919 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)(pHdr + 1);
2920 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2921
2922 cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
2923 rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
2924 break;
2925 }
2926
2927 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
2928 {
2929 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)(pHdr + 1);
2930 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2931
2932 rc = vmsvga3dSurfaceStretchBlt(pThis, pCmd->dest, pCmd->boxDest, pCmd->src, pCmd->boxSrc, pCmd->mode);
2933 break;
2934 }
2935
2936 case SVGA_3D_CMD_SURFACE_DMA:
2937 {
2938 uint32_t cCopyBoxes;
2939 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)(pHdr + 1);
2940 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2941
2942 cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
2943 STAM_PROFILE_START(&pSVGAState->StatR3CmdSurfaceDMA, a);
2944 rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
2945 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdSurfaceDMA, a);
2946 break;
2947 }
2948
2949 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
2950 {
2951 uint32_t cRects;
2952 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)(pHdr + 1);
2953 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2954
2955 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
2956 rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
2957 break;
2958 }
2959
2960 case SVGA_3D_CMD_CONTEXT_DEFINE:
2961 {
2962 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)(pHdr + 1);
2963 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2964
2965 rc = vmsvga3dContextDefine(pThis, pCmd->cid);
2966 break;
2967 }
2968
2969 case SVGA_3D_CMD_CONTEXT_DESTROY:
2970 {
2971 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)(pHdr + 1);
2972 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2973
2974 rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
2975 break;
2976 }
2977
2978 case SVGA_3D_CMD_SETTRANSFORM:
2979 {
2980 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)(pHdr + 1);
2981 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2982
2983 rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
2984 break;
2985 }
2986
2987 case SVGA_3D_CMD_SETZRANGE:
2988 {
2989 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)(pHdr + 1);
2990 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2991
2992 rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
2993 break;
2994 }
2995
2996 case SVGA_3D_CMD_SETRENDERSTATE:
2997 {
2998 uint32_t cRenderStates;
2999 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)(pHdr + 1);
3000 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3001
3002 cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3003 rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3004 break;
3005 }
3006
3007 case SVGA_3D_CMD_SETRENDERTARGET:
3008 {
3009 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)(pHdr + 1);
3010 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3011
3012 rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
3013 break;
3014 }
3015
3016 case SVGA_3D_CMD_SETTEXTURESTATE:
3017 {
3018 uint32_t cTextureStates;
3019 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)(pHdr + 1);
3020 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3021
3022 cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3023 rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3024 break;
3025 }
3026
3027 case SVGA_3D_CMD_SETMATERIAL:
3028 {
3029 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)(pHdr + 1);
3030 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3031
3032 rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
3033 break;
3034 }
3035
3036 case SVGA_3D_CMD_SETLIGHTDATA:
3037 {
3038 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)(pHdr + 1);
3039 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3040
3041 rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
3042 break;
3043 }
3044
3045 case SVGA_3D_CMD_SETLIGHTENABLED:
3046 {
3047 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)(pHdr + 1);
3048 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3049
3050 rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
3051 break;
3052 }
3053
3054 case SVGA_3D_CMD_SETVIEWPORT:
3055 {
3056 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)(pHdr + 1);
3057 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3058
3059 rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
3060 break;
3061 }
3062
3063 case SVGA_3D_CMD_SETCLIPPLANE:
3064 {
3065 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)(pHdr + 1);
3066 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3067
3068 rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
3069 break;
3070 }
3071
3072 case SVGA_3D_CMD_CLEAR:
3073 {
3074 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)(pHdr + 1);
3075 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3076 uint32_t cRects;
3077
3078 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
3079 rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
3080 break;
3081 }
3082
3083 case SVGA_3D_CMD_PRESENT:
3084 {
3085 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)(pHdr + 1);
3086 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3087 uint32_t cRects;
3088
3089 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
3090
3091 STAM_PROFILE_START(&pSVGAState->StatR3CmdPresent, a);
3092 rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
3093 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdPresent, a);
3094 break;
3095 }
3096
3097 case SVGA_3D_CMD_SHADER_DEFINE:
3098 {
3099 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)(pHdr + 1);
3100 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3101 uint32_t cbData;
3102
3103 cbData = (pHdr->size - sizeof(*pCmd));
3104 rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
3105 break;
3106 }
3107
3108 case SVGA_3D_CMD_SHADER_DESTROY:
3109 {
3110 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)(pHdr + 1);
3111 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3112
3113 rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
3114 break;
3115 }
3116
3117 case SVGA_3D_CMD_SET_SHADER:
3118 {
3119 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)(pHdr + 1);
3120 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3121
3122 rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
3123 break;
3124 }
3125
3126 case SVGA_3D_CMD_SET_SHADER_CONST:
3127 {
3128 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)(pHdr + 1);
3129 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3130
3131 uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
3132 rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
3133 break;
3134 }
3135
3136 case SVGA_3D_CMD_DRAW_PRIMITIVES:
3137 {
3138 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)(pHdr + 1);
3139 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3140 uint32_t cVertexDivisor;
3141
3142 cVertexDivisor = (pHdr->size - sizeof(*pCmd) - sizeof(SVGA3dVertexDecl) * pCmd->numVertexDecls - sizeof(SVGA3dPrimitiveRange) * pCmd->numRanges);
3143 Assert(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
3144 Assert(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
3145 Assert(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls);
3146
3147 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
3148 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *) (&pVertexDecl[pCmd->numVertexDecls]);
3149 SVGA3dVertexDivisor *pVertexDivisor = (cVertexDivisor) ? (SVGA3dVertexDivisor *)(&pNumRange[pCmd->numRanges]) : NULL;
3150
3151 STAM_PROFILE_START(&pSVGAState->StatR3CmdDrawPrimitive, a);
3152 rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges, pNumRange, cVertexDivisor, pVertexDivisor);
3153 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdDrawPrimitive, a);
3154 break;
3155 }
3156
3157 case SVGA_3D_CMD_SETSCISSORRECT:
3158 {
3159 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)(pHdr + 1);
3160 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3161
3162 rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
3163 break;
3164 }
3165
3166 case SVGA_3D_CMD_BEGIN_QUERY:
3167 {
3168 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)(pHdr + 1);
3169 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3170
3171 rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
3172 break;
3173 }
3174
3175 case SVGA_3D_CMD_END_QUERY:
3176 {
3177 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)(pHdr + 1);
3178 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3179
3180 rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
3181 break;
3182 }
3183
3184 case SVGA_3D_CMD_WAIT_FOR_QUERY:
3185 {
3186 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)(pHdr + 1);
3187 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3188
3189 rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
3190 break;
3191 }
3192
3193 case SVGA_3D_CMD_GENERATE_MIPMAPS:
3194 {
3195 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)(pHdr + 1);
3196 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3197
3198 rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
3199 break;
3200 }
3201
3202 case SVGA_3D_CMD_ACTIVATE_SURFACE:
3203 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
3204 /* context id + surface id? */
3205 break;
3206
3207 default:
3208 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3209 AssertFailed();
3210 break;
3211 }
3212 }
3213 else
3214# endif // VBOX_WITH_VMSVGA3D
3215 {
3216 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3217 AssertFailed();
3218 }
3219 }
3220
3221 /* Go to the next slot */
3222 Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
3223 offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
3224 if (offCurrentCmd >= offFifoMax)
3225 {
3226 offCurrentCmd -= offFifoMax - offFifoMin;
3227 Assert(offCurrentCmd >= offFifoMin);
3228 Assert(offCurrentCmd < offFifoMax);
3229 }
3230 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
3231 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
3232
3233 /*
3234 * Raise IRQ if required. Must enter the critical section here
3235 * before making final decisions here, otherwise cubebench and
3236 * others may end up waiting forever.
3237 */
3238 if ( u32IrqStatus
3239 || (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
3240 {
3241 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
3242
3243 /* FIFO progress might trigger an interrupt. */
3244 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
3245 {
3246 Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
3247 u32IrqStatus |= SVGA_IRQFLAG_FIFO_PROGRESS;
3248 }
3249
3250 /* Unmasked IRQ pending? */
3251 if (pThis->svga.u32IrqMask & u32IrqStatus)
3252 {
3253 Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
3254 ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
3255 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
3256 }
3257
3258 PDMCritSectLeave(&pThis->CritSect);
3259 }
3260 }
3261
3262 /* If really done, clear the busy flag. */
3263 if (fDone)
3264 {
3265 Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
3266 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3267 }
3268 }
3269
3270 /*
3271 * Free the bounce buffer. (There are no returns above!)
3272 */
3273 RTMemFree(pbBounceBuf);
3274
3275 return VINF_SUCCESS;
3276}
3277
3278/**
3279 * Free the specified GMR
3280 *
3281 * @param pThis VGA device instance data.
3282 * @param idGMR GMR id
3283 */
3284void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
3285{
3286 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3287
3288 /* Free the old descriptor if present. */
3289 if (pSVGAState->aGMR[idGMR].numDescriptors)
3290 {
3291 PGMR pGMR = &pSVGAState->aGMR[idGMR];
3292# ifdef DEBUG_GMR_ACCESS
3293 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
3294# endif
3295
3296 Assert(pGMR->paDesc);
3297 RTMemFree(pGMR->paDesc);
3298 pGMR->paDesc = NULL;
3299 pGMR->numDescriptors = 0;
3300 pGMR->cbTotal = 0;
3301 pGMR->cMaxPages = 0;
3302 }
3303 Assert(!pSVGAState->aGMR[idGMR].cbTotal);
3304}
3305
3306/**
3307 * Copy from a GMR to host memory or vice versa
3308 *
3309 * @returns VBox status code.
3310 * @param pThis VGA device instance data.
3311 * @param enmTransferType Transfer type (read/write)
3312 * @param pbDst Host destination pointer
3313 * @param cbDestPitch Destination buffer pitch
3314 * @param src GMR description
3315 * @param offSrc Source buffer offset
3316 * @param cbSrcPitch Source buffer pitch
3317 * @param cbWidth Source width in bytes
3318 * @param cHeight Source height
3319 */
3320int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType, uint8_t *pbDst, int32_t cbDestPitch,
3321 SVGAGuestPtr src, uint32_t offSrc, int32_t cbSrcPitch, uint32_t cbWidth, uint32_t cHeight)
3322{
3323 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3324 PGMR pGMR;
3325 int rc;
3326 PVMSVGAGMRDESCRIPTOR pDesc;
3327 unsigned offDesc = 0;
3328
3329 Log(("vmsvgaGMRTransfer: gmr=%x offset=%x pitch=%d cbWidth=%d cHeight=%d; src offset=%d src pitch=%d\n",
3330 src.gmrId, src.offset, cbDestPitch, cbWidth, cHeight, offSrc, cbSrcPitch));
3331 Assert(cbWidth && cHeight);
3332
3333 /* Shortcut for the framebuffer. */
3334 if (src.gmrId == SVGA_GMR_FRAMEBUFFER)
3335 {
3336 offSrc += src.offset;
3337 AssertMsgReturn(src.offset < pThis->vram_size,
3338 ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x vram_size=%#x\n",
3339 src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
3340 VERR_INVALID_PARAMETER);
3341 AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pThis->vram_size,
3342 ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x vram_size=%#x\n",
3343 src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
3344 VERR_INVALID_PARAMETER);
3345
3346 uint8_t *pSrc = pThis->CTX_SUFF(vram_ptr) + offSrc;
3347
3348 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
3349 {
3350 /* switch src & dest */
3351 uint8_t *pTemp = pbDst;
3352 int32_t cbTempPitch = cbDestPitch;
3353
3354 pbDst = pSrc;
3355 pSrc = pTemp;
3356
3357 cbDestPitch = cbSrcPitch;
3358 cbSrcPitch = cbTempPitch;
3359 }
3360
3361 if ( pThis->svga.cbScanline == (uint32_t)cbDestPitch
3362 && cbWidth == (uint32_t)cbDestPitch
3363 && cbSrcPitch == cbDestPitch)
3364 {
3365 memcpy(pbDst, pSrc, cbWidth * cHeight);
3366 }
3367 else
3368 {
3369 for(uint32_t i = 0; i < cHeight; i++)
3370 {
3371 memcpy(pbDst, pSrc, cbWidth);
3372
3373 pbDst += cbDestPitch;
3374 pSrc += cbSrcPitch;
3375 }
3376 }
3377 return VINF_SUCCESS;
3378 }
3379
3380 AssertReturn(src.gmrId < VMSVGA_MAX_GMR_IDS, VERR_INVALID_PARAMETER);
3381 pGMR = &pSVGAState->aGMR[src.gmrId];
3382 pDesc = pGMR->paDesc;
3383
3384 offSrc += src.offset;
3385 AssertMsgReturn(src.offset < pGMR->cbTotal,
3386 ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
3387 src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
3388 VERR_INVALID_PARAMETER);
3389 AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pGMR->cbTotal,
3390 ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
3391 src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
3392 VERR_INVALID_PARAMETER);
3393
3394 for (uint32_t i = 0; i < cHeight; i++)
3395 {
3396 uint32_t cbCurrentWidth = cbWidth;
3397 uint32_t offCurrent = offSrc;
3398 uint8_t *pCurrentDest = pbDst;
3399
3400 /* Find the right descriptor */
3401 while (offDesc + pDesc->numPages * PAGE_SIZE <= offCurrent)
3402 {
3403 offDesc += pDesc->numPages * PAGE_SIZE;
3404 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
3405 pDesc++;
3406 }
3407
3408 while (cbCurrentWidth)
3409 {
3410 uint32_t cbToCopy;
3411
3412 if (offCurrent + cbCurrentWidth <= offDesc + pDesc->numPages * PAGE_SIZE)
3413 {
3414 cbToCopy = cbCurrentWidth;
3415 }
3416 else
3417 {
3418 cbToCopy = (offDesc + pDesc->numPages * PAGE_SIZE - offCurrent);
3419 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
3420 }
3421
3422 LogFlow(("vmsvgaGMRTransfer: %s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", pDesc->GCPhys + offCurrent - offDesc));
3423
3424 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
3425 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
3426 else
3427 rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
3428 AssertRCBreak(rc);
3429
3430 cbCurrentWidth -= cbToCopy;
3431 offCurrent += cbToCopy;
3432 pCurrentDest += cbToCopy;
3433
3434 /* Go to the next descriptor if there's anything left. */
3435 if (cbCurrentWidth)
3436 {
3437 offDesc += pDesc->numPages * PAGE_SIZE;
3438 pDesc++;
3439 }
3440 }
3441
3442 offSrc += cbSrcPitch;
3443 pbDst += cbDestPitch;
3444 }
3445
3446 return VINF_SUCCESS;
3447}
3448
3449/**
3450 * Unblock the FIFO I/O thread so it can respond to a state change.
3451 *
3452 * @returns VBox status code.
3453 * @param pDevIns The VGA device instance.
3454 * @param pThread The send thread.
3455 */
3456static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3457{
3458 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3459 Log(("vmsvgaFIFOLoopWakeUp\n"));
3460 return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3461}
3462
3463/**
3464 * Enables or disables dirty page tracking for the framebuffer
3465 *
3466 * @param pThis VGA device instance data.
3467 * @param fTraces Enable/disable traces
3468 */
3469static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
3470{
3471 if ( (!pThis->svga.fConfigured || !pThis->svga.fEnabled)
3472 && !fTraces)
3473 {
3474 //Assert(pThis->svga.fTraces);
3475 Log(("vmsvgaSetTraces: *not* allowed to disable dirty page tracking when the device is in legacy mode.\n"));
3476 return;
3477 }
3478
3479 pThis->svga.fTraces = fTraces;
3480 if (pThis->svga.fTraces)
3481 {
3482 unsigned cbFrameBuffer = pThis->vram_size;
3483
3484 Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
3485 if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
3486 {
3487 Assert(pThis->svga.cbScanline);
3488 /* Hardware enabled; return real framebuffer size .*/
3489 cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
3490 cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
3491 }
3492
3493 if (!pThis->svga.fVRAMTracking)
3494 {
3495 Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
3496 vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
3497 pThis->svga.fVRAMTracking = true;
3498 }
3499 }
3500 else
3501 {
3502 if (pThis->svga.fVRAMTracking)
3503 {
3504 Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
3505 vgaR3UnregisterVRAMHandler(pThis);
3506 pThis->svga.fVRAMTracking = false;
3507 }
3508 }
3509}
3510
3511/**
3512 * Callback function for mapping a PCI I/O region.
3513 *
3514 * @return VBox status code.
3515 * @param pPciDev Pointer to PCI device.
3516 * Use pPciDev->pDevIns to get the device instance.
3517 * @param iRegion The region number.
3518 * @param GCPhysAddress Physical address of the region.
3519 * If iType is PCI_ADDRESS_SPACE_IO, this is an
3520 * I/O port, else it's a physical address.
3521 * This address is *NOT* relative
3522 * to pci_mem_base like earlier!
3523 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
3524 */
3525DECLCALLBACK(int) vmsvgaR3IORegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
3526{
3527 int rc;
3528 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3529 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3530
3531 Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%#x enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
3532 if (enmType == PCI_ADDRESS_SPACE_IO)
3533 {
3534 AssertReturn(iRegion == 0, VERR_INTERNAL_ERROR);
3535 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3536 vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr */, NULL /* InStr */, "VMSVGA");
3537 if (RT_FAILURE(rc))
3538 return rc;
3539 if (pThis->fR0Enabled)
3540 {
3541 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3542 "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
3543 if (RT_FAILURE(rc))
3544 return rc;
3545 }
3546 if (pThis->fGCEnabled)
3547 {
3548 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3549 "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
3550 if (RT_FAILURE(rc))
3551 return rc;
3552 }
3553
3554 pThis->svga.BasePort = GCPhysAddress;
3555 Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
3556 }
3557 else
3558 {
3559 AssertReturn(iRegion == 2 && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
3560 if (GCPhysAddress != NIL_RTGCPHYS)
3561 {
3562 /*
3563 * Mapping the FIFO RAM.
3564 */
3565 rc = PDMDevHlpMMIO2Map(pDevIns, iRegion, GCPhysAddress);
3566 AssertRC(rc);
3567
3568# ifdef DEBUG_FIFO_ACCESS
3569 if (RT_SUCCESS(rc))
3570 {
3571 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress, GCPhysAddress + (VMSVGA_FIFO_SIZE - 1),
3572 pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
3573 "VMSVGA FIFO");
3574 AssertRC(rc);
3575 }
3576# endif
3577 if (RT_SUCCESS(rc))
3578 {
3579 pThis->svga.GCPhysFIFO = GCPhysAddress;
3580 Log(("vmsvgaR3IORegionMap: FIFO address = %RGp\n", GCPhysAddress));
3581 }
3582 }
3583 else
3584 {
3585 Assert(pThis->svga.GCPhysFIFO);
3586# ifdef DEBUG_FIFO_ACCESS
3587 rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3588 AssertRC(rc);
3589# endif
3590 pThis->svga.GCPhysFIFO = 0;
3591 }
3592
3593 }
3594 return VINF_SUCCESS;
3595}
3596
3597
3598/**
3599 * @copydoc FNSSMDEVLOADEXEC
3600 */
3601int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3602{
3603 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3604 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3605 int rc;
3606
3607 /* Load our part of the VGAState */
3608 rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
3609 AssertRCReturn(rc, rc);
3610
3611 /* Load the framebuffer backup. */
3612 rc = SSMR3GetMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
3613 AssertRCReturn(rc, rc);
3614
3615 /* Load the VMSVGA state. */
3616 rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGASTATEFields, NULL);
3617 AssertRCReturn(rc, rc);
3618
3619 /* Load the active cursor bitmaps. */
3620 if (pSVGAState->Cursor.fActive)
3621 {
3622 pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
3623 AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
3624
3625 rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
3626 AssertRCReturn(rc, rc);
3627 }
3628
3629 /* Load the GMR state */
3630 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
3631 {
3632 PGMR pGMR = &pSVGAState->aGMR[i];
3633
3634 rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
3635 AssertRCReturn(rc, rc);
3636
3637 if (pGMR->numDescriptors)
3638 {
3639 /* Allocate the maximum amount possible (everything non-continuous) */
3640 Assert(pGMR->cMaxPages || pGMR->cbTotal);
3641 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ((pGMR->cMaxPages) ? pGMR->cMaxPages : (pGMR->cbTotal >> PAGE_SHIFT) * sizeof(VMSVGAGMRDESCRIPTOR));
3642 AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
3643
3644 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
3645 {
3646 rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
3647 AssertRCReturn(rc, rc);
3648 }
3649 }
3650 }
3651
3652# ifdef VBOX_WITH_VMSVGA3D
3653 if (pThis->svga.f3DEnabled)
3654 {
3655 VMSVGA_STATE_LOAD loadstate;
3656
3657 loadstate.pSSM = pSSM;
3658 loadstate.uVersion = uVersion;
3659 loadstate.uPass = uPass;
3660
3661 /* Save the 3d state in the FIFO thread. */
3662 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_LOADSTATE;
3663 pThis->svga.pFIFOExtCmdParam = (void *)&loadstate;
3664 /* Hack alert: resume the IO thread as it has been suspended before the destruct callback.
3665 * The PowerOff notification isn't working, so not an option in this case.
3666 */
3667 PDMR3ThreadResume(pThis->svga.pFIFOIOThread);
3668 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3669 /* Wait for the end of the command. */
3670 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, RT_INDEFINITE_WAIT);
3671 AssertRC(rc);
3672 PDMR3ThreadSuspend(pThis->svga.pFIFOIOThread);
3673 }
3674# endif
3675
3676 return VINF_SUCCESS;
3677}
3678
3679/**
3680 * Reinit the video mode after the state has been loaded.
3681 */
3682int vmsvgaLoadDone(PPDMDEVINS pDevIns)
3683{
3684 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3685 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3686
3687 pThis->last_bpp = VMSVGA_VAL_UNINITIALIZED; /* force mode reset */
3688 vmsvgaChangeMode(pThis);
3689
3690 /* Set the active cursor. */
3691 if (pSVGAState->Cursor.fActive)
3692 {
3693 int rc;
3694
3695 rc = pThis->pDrv->pfnVBVAMousePointerShape (pThis->pDrv,
3696 true,
3697 true,
3698 pSVGAState->Cursor.xHotspot,
3699 pSVGAState->Cursor.yHotspot,
3700 pSVGAState->Cursor.width,
3701 pSVGAState->Cursor.height,
3702 pSVGAState->Cursor.pData);
3703 AssertRC(rc);
3704 }
3705 return VINF_SUCCESS;
3706}
3707
3708/**
3709 * @copydoc FNSSMDEVSAVEEXEC
3710 */
3711int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3712{
3713 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3714 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3715 int rc;
3716
3717 /* Save our part of the VGAState */
3718 rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
3719 AssertRCReturn(rc, rc);
3720
3721 /* Save the framebuffer backup. */
3722 rc = SSMR3PutMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
3723 AssertRCReturn(rc, rc);
3724
3725 /* Save the VMSVGA state. */
3726 rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGASTATEFields, NULL);
3727 AssertRCReturn(rc, rc);
3728
3729 /* Save the active cursor bitmaps. */
3730 if (pSVGAState->Cursor.fActive)
3731 {
3732 rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
3733 AssertRCReturn(rc, rc);
3734 }
3735
3736 /* Save the GMR state */
3737 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
3738 {
3739 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i], sizeof(pSVGAState->aGMR[i]), 0, g_aGMRFields, NULL);
3740 AssertRCReturn(rc, rc);
3741
3742 for (uint32_t j = 0; j < pSVGAState->aGMR[i].numDescriptors; j++)
3743 {
3744 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i].paDesc[j], sizeof(pSVGAState->aGMR[i].paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
3745 AssertRCReturn(rc, rc);
3746 }
3747 }
3748
3749# ifdef VBOX_WITH_VMSVGA3D
3750 if (pThis->svga.f3DEnabled)
3751 {
3752 /* Save the 3d state in the FIFO thread. */
3753 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_SAVESTATE;
3754 pThis->svga.pFIFOExtCmdParam = (void *)pSSM;
3755 /* Hack alert: resume the IO thread as it has been suspended before the destruct callback.
3756 * The PowerOff notification isn't working, so not an option in this case.
3757 */
3758 PDMR3ThreadResume(pThis->svga.pFIFOIOThread);
3759 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3760 /* Wait for the end of the external command. */
3761 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, RT_INDEFINITE_WAIT);
3762 AssertRC(rc);
3763 PDMR3ThreadSuspend(pThis->svga.pFIFOIOThread);
3764 }
3765# endif
3766 return VINF_SUCCESS;
3767}
3768
3769/**
3770 * Resets the SVGA hardware state
3771 *
3772 * @returns VBox status code.
3773 * @param pDevIns The device instance.
3774 */
3775int vmsvgaReset(PPDMDEVINS pDevIns)
3776{
3777 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3778 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3779
3780 /* Reset before init? */
3781 if (!pSVGAState)
3782 return VINF_SUCCESS;
3783
3784 Log(("vmsvgaReset\n"));
3785
3786 pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0;
3787
3788 /* Reset the FIFO thread. */
3789 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_RESET;
3790 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3791 /* Wait for the end of the termination sequence. */
3792 int rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, 10000);
3793 AssertRC(rc);
3794
3795 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
3796 memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
3797 memset(pThis->svga.pSVGAState, 0, sizeof(VMSVGASTATE));
3798 memset(pThis->svga.pFrameBufferBackup, 0, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
3799
3800 /* Register caps. */
3801 pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
3802# ifdef VBOX_WITH_VMSVGA3D
3803 pThis->svga.u32RegCaps |= SVGA_CAP_3D;
3804# endif
3805
3806 /* Setup FIFO capabilities. */
3807 pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
3808
3809 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
3810 pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
3811
3812 /* VRAM tracking is enabled by default during bootup. */
3813 pThis->svga.fVRAMTracking = true;
3814 pThis->svga.fEnabled = false;
3815
3816 /* Invalidate current settings. */
3817 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
3818 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
3819 pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
3820 pThis->svga.cbScanline = 0;
3821
3822 return rc;
3823}
3824
3825/**
3826 * Cleans up the SVGA hardware state
3827 *
3828 * @returns VBox status code.
3829 * @param pDevIns The device instance.
3830 */
3831int vmsvgaDestruct(PPDMDEVINS pDevIns)
3832{
3833 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3834 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3835 int rc;
3836
3837 /* Stop the FIFO thread. */
3838 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_TERMINATE;
3839 /* Hack alert: resume the IO thread as it has been suspended before the destruct callback.
3840 * The PowerOff notification isn't working, so not an option in this case.
3841 */
3842 PDMR3ThreadResume(pThis->svga.pFIFOIOThread);
3843 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3844
3845 /* Wait for the end of the termination sequence. */
3846 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, 10000);
3847 AssertRC(rc);
3848 PDMR3ThreadSuspend(pThis->svga.pFIFOIOThread);
3849
3850 if (pSVGAState)
3851 {
3852# ifndef VMSVGA_USE_EMT_HALT_CODE
3853 if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
3854 {
3855 RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
3856 pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
3857 }
3858# endif
3859 if (pSVGAState->Cursor.fActive)
3860 RTMemFree(pSVGAState->Cursor.pData);
3861
3862 for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
3863 {
3864 if (pSVGAState->aGMR[i].paDesc)
3865 RTMemFree(pSVGAState->aGMR[i].paDesc);
3866 }
3867 RTMemFree(pSVGAState);
3868 }
3869 if (pThis->svga.pFrameBufferBackup)
3870 RTMemFree(pThis->svga.pFrameBufferBackup);
3871 if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
3872 {
3873 RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
3874 pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
3875 }
3876 if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
3877 {
3878 SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3879 pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
3880 }
3881
3882 return VINF_SUCCESS;
3883}
3884
3885/**
3886 * Initialize the SVGA hardware state
3887 *
3888 * @returns VBox status code.
3889 * @param pDevIns The device instance.
3890 */
3891int vmsvgaInit(PPDMDEVINS pDevIns)
3892{
3893 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3894 PVMSVGASTATE pSVGAState;
3895 PVM pVM = PDMDevHlpGetVM(pDevIns);
3896 int rc;
3897
3898 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
3899 memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
3900
3901 pThis->svga.pSVGAState = RTMemAllocZ(sizeof(VMSVGASTATE));
3902 AssertReturn(pThis->svga.pSVGAState, VERR_NO_MEMORY);
3903 pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3904
3905 /* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
3906 pThis->svga.pFrameBufferBackup = RTMemAllocZ(VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
3907 AssertReturn(pThis->svga.pFrameBufferBackup, VERR_NO_MEMORY);
3908
3909 /* Create event semaphore. */
3910 pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
3911
3912 rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
3913 if (RT_FAILURE(rc))
3914 {
3915 Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
3916 return rc;
3917 }
3918
3919 /* Create event semaphore. */
3920 rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
3921 if (RT_FAILURE(rc))
3922 {
3923 Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
3924 return rc;
3925 }
3926
3927# ifndef VMSVGA_USE_EMT_HALT_CODE
3928 /* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
3929 rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
3930 AssertRCReturn(rc, rc);
3931# endif
3932
3933 /* Register caps. */
3934 pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
3935# ifdef VBOX_WITH_VMSVGA3D
3936 pThis->svga.u32RegCaps |= SVGA_CAP_3D;
3937# endif
3938
3939 /* Setup FIFO capabilities. */
3940 pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
3941
3942 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
3943 pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
3944
3945 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
3946# ifdef VBOX_WITH_VMSVGA3D
3947 if (pThis->svga.f3DEnabled)
3948 {
3949 rc = vmsvga3dInit(pThis);
3950 if (RT_FAILURE(rc))
3951 {
3952 LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
3953 pThis->svga.f3DEnabled = false;
3954 }
3955 }
3956# endif
3957 /* VRAM tracking is enabled by default during bootup. */
3958 pThis->svga.fVRAMTracking = true;
3959
3960 /* Invalidate current settings. */
3961 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
3962 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
3963 pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
3964 pThis->svga.cbScanline = 0;
3965
3966 pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
3967 pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
3968 while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
3969 {
3970 pThis->svga.u32MaxWidth -= 256;
3971 pThis->svga.u32MaxHeight -= 256;
3972 }
3973 Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
3974
3975# ifdef DEBUG_GMR_ACCESS
3976 /* Register the GMR access handler type. */
3977 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
3978 vmsvgaR3GMRAccessHandler, NULL, NULL, NULL, NULL, "VMSVGA GMR",
3979 &pThis->svga.hGmrAccessHandlerType);
3980 AssertRCReturn(rc, rc);
3981# endif
3982# ifdef DEBUG_FIFO_ACCESS
3983 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_ALL,
3984 vmsvgaR3FIFOAccessHandler, NULL, NULL, NULL, NULL, "VMSVGA FIFO",
3985 &pThis->svga.hFifoAccessHandlerType);
3986 AssertRCReturn(rc, rc);
3987#endif
3988
3989 /* Create the async IO thread. */
3990 rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
3991 RTTHREADTYPE_IO, "VMSVGA FIFO");
3992 if (RT_FAILURE(rc))
3993 {
3994 AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
3995 return rc;
3996 }
3997
3998 /*
3999 * Statistics.
4000 */
4001 STAM_REG(pVM, &pSVGAState->StatR3CmdPresent, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/Present", STAMUNIT_TICKS_PER_CALL, "Profiling of Present.");
4002 STAM_REG(pVM, &pSVGAState->StatR3CmdDrawPrimitive, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/DrawPrimitive", STAMUNIT_TICKS_PER_CALL, "Profiling of DrawPrimitive.");
4003 STAM_REG(pVM, &pSVGAState->StatR3CmdSurfaceDMA, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/SurfaceDMA", STAMUNIT_TICKS_PER_CALL, "Profiling of SurfaceDMA.");
4004 STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
4005 STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
4006 STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
4007 STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
4008 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
4009 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
4010 STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
4011
4012 return VINF_SUCCESS;
4013}
4014
4015# ifdef VBOX_WITH_VMSVGA3D
4016/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
4017static const char * const g_apszVmSvgaDevCapNames[] =
4018{
4019 "x3D", /* = 0 */
4020 "xMAX_LIGHTS",
4021 "xMAX_TEXTURES",
4022 "xMAX_CLIP_PLANES",
4023 "xVERTEX_SHADER_VERSION",
4024 "xVERTEX_SHADER",
4025 "xFRAGMENT_SHADER_VERSION",
4026 "xFRAGMENT_SHADER",
4027 "xMAX_RENDER_TARGETS",
4028 "xS23E8_TEXTURES",
4029 "xS10E5_TEXTURES",
4030 "xMAX_FIXED_VERTEXBLEND",
4031 "xD16_BUFFER_FORMAT",
4032 "xD24S8_BUFFER_FORMAT",
4033 "xD24X8_BUFFER_FORMAT",
4034 "xQUERY_TYPES",
4035 "xTEXTURE_GRADIENT_SAMPLING",
4036 "rMAX_POINT_SIZE",
4037 "xMAX_SHADER_TEXTURES",
4038 "xMAX_TEXTURE_WIDTH",
4039 "xMAX_TEXTURE_HEIGHT",
4040 "xMAX_VOLUME_EXTENT",
4041 "xMAX_TEXTURE_REPEAT",
4042 "xMAX_TEXTURE_ASPECT_RATIO",
4043 "xMAX_TEXTURE_ANISOTROPY",
4044 "xMAX_PRIMITIVE_COUNT",
4045 "xMAX_VERTEX_INDEX",
4046 "xMAX_VERTEX_SHADER_INSTRUCTIONS",
4047 "xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
4048 "xMAX_VERTEX_SHADER_TEMPS",
4049 "xMAX_FRAGMENT_SHADER_TEMPS",
4050 "xTEXTURE_OPS",
4051 "xSURFACEFMT_X8R8G8B8",
4052 "xSURFACEFMT_A8R8G8B8",
4053 "xSURFACEFMT_A2R10G10B10",
4054 "xSURFACEFMT_X1R5G5B5",
4055 "xSURFACEFMT_A1R5G5B5",
4056 "xSURFACEFMT_A4R4G4B4",
4057 "xSURFACEFMT_R5G6B5",
4058 "xSURFACEFMT_LUMINANCE16",
4059 "xSURFACEFMT_LUMINANCE8_ALPHA8",
4060 "xSURFACEFMT_ALPHA8",
4061 "xSURFACEFMT_LUMINANCE8",
4062 "xSURFACEFMT_Z_D16",
4063 "xSURFACEFMT_Z_D24S8",
4064 "xSURFACEFMT_Z_D24X8",
4065 "xSURFACEFMT_DXT1",
4066 "xSURFACEFMT_DXT2",
4067 "xSURFACEFMT_DXT3",
4068 "xSURFACEFMT_DXT4",
4069 "xSURFACEFMT_DXT5",
4070 "xSURFACEFMT_BUMPX8L8V8U8",
4071 "xSURFACEFMT_A2W10V10U10",
4072 "xSURFACEFMT_BUMPU8V8",
4073 "xSURFACEFMT_Q8W8V8U8",
4074 "xSURFACEFMT_CxV8U8",
4075 "xSURFACEFMT_R_S10E5",
4076 "xSURFACEFMT_R_S23E8",
4077 "xSURFACEFMT_RG_S10E5",
4078 "xSURFACEFMT_RG_S23E8",
4079 "xSURFACEFMT_ARGB_S10E5",
4080 "xSURFACEFMT_ARGB_S23E8",
4081 "xMISSING62",
4082 "xMAX_VERTEX_SHADER_TEXTURES",
4083 "xMAX_SIMULTANEOUS_RENDER_TARGETS",
4084 "xSURFACEFMT_V16U16",
4085 "xSURFACEFMT_G16R16",
4086 "xSURFACEFMT_A16B16G16R16",
4087 "xSURFACEFMT_UYVY",
4088 "xSURFACEFMT_YUY2",
4089 "xMULTISAMPLE_NONMASKABLESAMPLES",
4090 "xMULTISAMPLE_MASKABLESAMPLES",
4091 "xALPHATOCOVERAGE",
4092 "xSUPERSAMPLE",
4093 "xAUTOGENMIPMAPS",
4094 "xSURFACEFMT_NV12",
4095 "xSURFACEFMT_AYUV",
4096 "xMAX_CONTEXT_IDS",
4097 "xMAX_SURFACE_IDS",
4098 "xSURFACEFMT_Z_DF16",
4099 "xSURFACEFMT_Z_DF24",
4100 "xSURFACEFMT_Z_D24S8_INT",
4101 "xSURFACEFMT_BC4_UNORM",
4102 "xSURFACEFMT_BC5_UNORM", /* 83 */
4103};
4104# endif
4105
4106
4107/**
4108 * Power On notification.
4109 *
4110 * @returns VBox status.
4111 * @param pDevIns The device instance data.
4112 *
4113 * @remarks Caller enters the device critical section.
4114 */
4115DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
4116{
4117 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4118 int rc;
4119
4120# ifdef VBOX_WITH_VMSVGA3D
4121 if (pThis->svga.f3DEnabled)
4122 {
4123 rc = vmsvga3dPowerOn(pThis);
4124
4125 if (RT_SUCCESS(rc))
4126 {
4127 bool fSavedBuffering = RTLogRelSetBuffering(true);
4128 SVGA3dCapsRecord *pCaps;
4129 SVGA3dCapPair *pData;
4130 uint32_t idxCap = 0;
4131
4132 /* 3d hardware version; latest and greatest */
4133 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
4134 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
4135
4136 pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
4137 pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
4138 pData = (SVGA3dCapPair *)&pCaps->data;
4139
4140 /* Fill out all 3d capabilities. */
4141 for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
4142 {
4143 uint32_t val = 0;
4144
4145 rc = vmsvga3dQueryCaps(pThis, i, &val);
4146 if (RT_SUCCESS(rc))
4147 {
4148 pData[idxCap][0] = i;
4149 pData[idxCap][1] = val;
4150 idxCap++;
4151 if (g_apszVmSvgaDevCapNames[i][0] == 'x')
4152 LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
4153 else
4154 LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)*(float *)&val, (unsigned)(*(float *)&val * 10000) % 10000,
4155 &g_apszVmSvgaDevCapNames[i][1]));
4156 }
4157 else
4158 LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
4159 }
4160 pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
4161 pCaps = (SVGA3dCapsRecord *)((uint32_t *)pCaps + pCaps->header.length);
4162
4163 /* Mark end of record array. */
4164 pCaps->header.length = 0;
4165
4166 RTLogRelSetBuffering(fSavedBuffering);
4167 }
4168 }
4169# endif // VBOX_WITH_VMSVGA3D
4170}
4171
4172#endif /* IN_RING3 */
4173
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