VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 55784

Last change on this file since 55784 was 55693, checked in by vboxsync, 10 years ago

DevVGA-SVGA.cpp: Fixed for cubebench hang. The FIFO must take the lock when working over the IRQ state, just like the EMT (implicitly) does.
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File size: 172.4 KB
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1/* $Id: DevVGA-SVGA.cpp 55693 2015-05-06 14:00:15Z vboxsync $ */
2/** @file
3 * VMWare SVGA device.
4 *
5 * Logging levels guidelines for this and related files:
6 * - Log() for normal bits.
7 * - LogFlow() for more info.
8 * - Log2 for hex dump of cursor data.
9 * - Log3 for hex dump of shader code.
10 * - Log4 for hex dumps of 3D data.
11 */
12
13/*
14 * Copyright (C) 2013-2014 Oracle Corporation
15 *
16 * This file is part of VirtualBox Open Source Edition (OSE), as
17 * available from http://www.virtualbox.org. This file is free software;
18 * you can redistribute it and/or modify it under the terms of the GNU
19 * General Public License (GPL) as published by the Free Software
20 * Foundation, in version 2 as it comes in the "COPYING" file of the
21 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23 */
24
25
26/*******************************************************************************
27* Header Files *
28*******************************************************************************/
29#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
30#define VMSVGA_USE_EMT_HALT_CODE
31#include <VBox/vmm/pdmdev.h>
32#include <VBox/version.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/vmm/pgm.h>
36#ifdef VMSVGA_USE_EMT_HALT_CODE
37# include <VBox/vmm/vmapi.h>
38# include <VBox/vmm/vmcpuset.h>
39#endif
40#include <VBox/sup.h>
41
42#include <iprt/assert.h>
43#include <iprt/semaphore.h>
44#include <iprt/uuid.h>
45#ifdef IN_RING3
46# include <iprt/mem.h>
47#endif
48
49#include <VBox/VMMDev.h>
50#include <VBox/VBoxVideo.h>
51#include <VBox/bioslogo.h>
52
53/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
54#include "DevVGA.h"
55
56#ifdef DEBUG
57/* Enable to log FIFO register accesses. */
58//# define DEBUG_FIFO_ACCESS
59/* Enable to log GMR page accesses. */
60//# define DEBUG_GMR_ACCESS
61#endif
62
63#include "DevVGA-SVGA.h"
64#include "vmsvga/svga_reg.h"
65#include "vmsvga/svga_escape.h"
66#include "vmsvga/svga_overlay.h"
67#include "vmsvga/svga3d_reg.h"
68#include "vmsvga/svga3d_caps.h"
69#ifdef VBOX_WITH_VMSVGA3D
70# include "DevVGA-SVGA3d.h"
71#endif
72
73/*******************************************************************************
74* Defined Constants And Macros *
75*******************************************************************************/
76/**
77 * Macro for checking if a fixed FIFO register is valid according to the
78 * current FIFO configuration.
79 *
80 * @returns true / false.
81 * @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
82 * @param a_offFifoMin A valid SVGA_FIFO_MIN value.
83 */
84#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
85
86
87/*******************************************************************************
88* Structures and Typedefs *
89*******************************************************************************/
90/* 64-bit GMR descriptor */
91typedef struct
92{
93 RTGCPHYS GCPhys;
94 uint64_t numPages;
95} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
96
97/* GMR slot */
98typedef struct
99{
100 uint32_t cMaxPages;
101 uint32_t cbTotal;
102 uint32_t numDescriptors;
103 PVMSVGAGMRDESCRIPTOR paDesc;
104} GMR, *PGMR;
105
106/* Internal SVGA state. */
107typedef struct
108{
109 GMR aGMR[VMSVGA_MAX_GMR_IDS];
110 struct
111 {
112 SVGAGuestPtr ptr;
113 uint32_t bytesPerLine;
114 SVGAGMRImageFormat format;
115 } GMRFB;
116 struct
117 {
118 bool fActive;
119 uint32_t xHotspot;
120 uint32_t yHotspot;
121 uint32_t width;
122 uint32_t height;
123 uint32_t cbData;
124 void *pData;
125 } Cursor;
126 SVGAColorBGRX colorAnnotation;
127
128#ifdef VMSVGA_USE_EMT_HALT_CODE
129 /** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
130 uint32_t volatile cBusyDelayedEmts;
131 /** Set of EMTs that are */
132 VMCPUSET BusyDelayedEmts;
133#else
134 /** Number of EMTs waiting on hBusyDelayedEmts. */
135 uint32_t volatile cBusyDelayedEmts;
136 /** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
137 * busy (ugly). */
138 RTSEMEVENTMULTI hBusyDelayedEmts;
139#endif
140 /** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
141 STAMPROFILE StatBusyDelayEmts;
142
143 STAMPROFILE StatR3CmdPresent;
144 STAMPROFILE StatR3CmdDrawPrimitive;
145 STAMPROFILE StatR3CmdSurfaceDMA;
146
147 STAMCOUNTER StatFifoCommands;
148 STAMCOUNTER StatFifoErrors;
149 STAMCOUNTER StatFifoUnkCmds;
150 STAMCOUNTER StatFifoTodoTimeout;
151 STAMCOUNTER StatFifoTodoWoken;
152 STAMPROFILE StatFifoStalls;
153
154} VMSVGASTATE, *PVMSVGASTATE;
155
156#ifdef IN_RING3
157
158/**
159 * SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
160 */
161static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
162{
163 SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
164 SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
165 SSMFIELD_ENTRY_TERM()
166};
167
168/**
169 * SSM descriptor table for the GMR structure.
170 */
171static SSMFIELD const g_aGMRFields[] =
172{
173 SSMFIELD_ENTRY( GMR, cMaxPages),
174 SSMFIELD_ENTRY( GMR, cbTotal),
175 SSMFIELD_ENTRY( GMR, numDescriptors),
176 SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
177 SSMFIELD_ENTRY_TERM()
178};
179
180/**
181 * SSM descriptor table for the VMSVGASTATE structure.
182 */
183static SSMFIELD const g_aVMSVGASTATEFields[] =
184{
185 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, aGMR),
186 SSMFIELD_ENTRY( VMSVGASTATE, GMRFB),
187 SSMFIELD_ENTRY( VMSVGASTATE, Cursor.fActive),
188 SSMFIELD_ENTRY( VMSVGASTATE, Cursor.xHotspot),
189 SSMFIELD_ENTRY( VMSVGASTATE, Cursor.yHotspot),
190 SSMFIELD_ENTRY( VMSVGASTATE, Cursor.width),
191 SSMFIELD_ENTRY( VMSVGASTATE, Cursor.height),
192 SSMFIELD_ENTRY( VMSVGASTATE, Cursor.cbData),
193 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGASTATE, Cursor.pData),
194 SSMFIELD_ENTRY( VMSVGASTATE, colorAnnotation),
195 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, cBusyDelayedEmts),
196#ifdef VMSVGA_USE_EMT_HALT_CODE
197 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, BusyDelayedEmts),
198#else
199 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, hBusyDelayedEmts),
200#endif
201 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatBusyDelayEmts),
202 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatR3CmdPresent),
203 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatR3CmdDrawPrimitive),
204 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatR3CmdSurfaceDMA),
205 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatFifoCommands),
206 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatFifoErrors),
207 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatFifoUnkCmds),
208 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatFifoTodoTimeout),
209 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatFifoTodoWoken),
210 SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatFifoStalls),
211 SSMFIELD_ENTRY_TERM()
212};
213
214/**
215 * SSM descriptor table for the VGAState.svga structure.
216 */
217static SSMFIELD const g_aVGAStateSVGAFields[] =
218{
219 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u64HostWindowId),
220 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
221 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
222 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSVGAState),
223 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
224 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFrameBufferBackup),
225 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOExtCmdParam),
226 SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
227 SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
228 SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
229 SSMFIELD_ENTRY( VMSVGAState, fEnabled),
230 SSMFIELD_ENTRY( VMSVGAState, fConfigured),
231 SSMFIELD_ENTRY( VMSVGAState, fBusy),
232 SSMFIELD_ENTRY( VMSVGAState, fTraces),
233 SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
234 SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
235 SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
236 SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
237 SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
238 SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
239 SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
240 SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
241 SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
242 SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
243 SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
244 SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
245 SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
246 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
247 SSMFIELD_ENTRY( VMSVGAState, uWidth),
248 SSMFIELD_ENTRY( VMSVGAState, uHeight),
249 SSMFIELD_ENTRY( VMSVGAState, uBpp),
250 SSMFIELD_ENTRY( VMSVGAState, cbScanline),
251 SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
252 SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
253 SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
254 SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
255 SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
256 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
257 SSMFIELD_ENTRY_TERM()
258};
259
260static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
261
262#endif /* IN_RING3 */
263
264
265#ifdef LOG_ENABLED
266/**
267 * Index register string name lookup
268 *
269 * @returns Index register string or "UNKNOWN"
270 * @param pThis VMSVGA State
271 */
272static const char *vmsvgaIndexToString(PVGASTATE pThis)
273{
274 switch (pThis->svga.u32IndexReg)
275 {
276 case SVGA_REG_ID:
277 return "SVGA_REG_ID";
278 case SVGA_REG_ENABLE:
279 return "SVGA_REG_ENABLE";
280 case SVGA_REG_WIDTH:
281 return "SVGA_REG_WIDTH";
282 case SVGA_REG_HEIGHT:
283 return "SVGA_REG_HEIGHT";
284 case SVGA_REG_MAX_WIDTH:
285 return "SVGA_REG_MAX_WIDTH";
286 case SVGA_REG_MAX_HEIGHT:
287 return "SVGA_REG_MAX_HEIGHT";
288 case SVGA_REG_DEPTH:
289 return "SVGA_REG_DEPTH";
290 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
291 return "SVGA_REG_BITS_PER_PIXEL";
292 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
293 return "SVGA_REG_HOST_BITS_PER_PIXEL";
294 case SVGA_REG_PSEUDOCOLOR:
295 return "SVGA_REG_PSEUDOCOLOR";
296 case SVGA_REG_RED_MASK:
297 return "SVGA_REG_RED_MASK";
298 case SVGA_REG_GREEN_MASK:
299 return "SVGA_REG_GREEN_MASK";
300 case SVGA_REG_BLUE_MASK:
301 return "SVGA_REG_BLUE_MASK";
302 case SVGA_REG_BYTES_PER_LINE:
303 return "SVGA_REG_BYTES_PER_LINE";
304 case SVGA_REG_VRAM_SIZE: /* VRAM size */
305 return "SVGA_REG_VRAM_SIZE";
306 case SVGA_REG_FB_START: /* Frame buffer physical address. */
307 return "SVGA_REG_FB_START";
308 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
309 return "SVGA_REG_FB_OFFSET";
310 case SVGA_REG_FB_SIZE: /* Frame buffer size */
311 return "SVGA_REG_FB_SIZE";
312 case SVGA_REG_CAPABILITIES:
313 return "SVGA_REG_CAPABILITIES";
314 case SVGA_REG_MEM_START: /* FIFO start */
315 return "SVGA_REG_MEM_START";
316 case SVGA_REG_MEM_SIZE: /* FIFO size */
317 return "SVGA_REG_MEM_SIZE";
318 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
319 return "SVGA_REG_CONFIG_DONE";
320 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
321 return "SVGA_REG_SYNC";
322 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
323 return "SVGA_REG_BUSY";
324 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
325 return "SVGA_REG_GUEST_ID";
326 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
327 return "SVGA_REG_SCRATCH_SIZE";
328 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
329 return "SVGA_REG_MEM_REGS";
330 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
331 return "SVGA_REG_PITCHLOCK";
332 case SVGA_REG_IRQMASK: /* Interrupt mask */
333 return "SVGA_REG_IRQMASK";
334 case SVGA_REG_GMR_ID:
335 return "SVGA_REG_GMR_ID";
336 case SVGA_REG_GMR_DESCRIPTOR:
337 return "SVGA_REG_GMR_DESCRIPTOR";
338 case SVGA_REG_GMR_MAX_IDS:
339 return "SVGA_REG_GMR_MAX_IDS";
340 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
341 return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
342 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
343 return "SVGA_REG_TRACES";
344 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
345 return "SVGA_REG_GMRS_MAX_PAGES";
346 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
347 return "SVGA_REG_MEMORY_SIZE";
348 case SVGA_REG_TOP: /* Must be 1 more than the last register */
349 return "SVGA_REG_TOP";
350 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
351 return "SVGA_PALETTE_BASE";
352 case SVGA_REG_CURSOR_ID:
353 return "SVGA_REG_CURSOR_ID";
354 case SVGA_REG_CURSOR_X:
355 return "SVGA_REG_CURSOR_X";
356 case SVGA_REG_CURSOR_Y:
357 return "SVGA_REG_CURSOR_Y";
358 case SVGA_REG_CURSOR_ON:
359 return "SVGA_REG_CURSOR_ON";
360 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
361 return "SVGA_REG_NUM_GUEST_DISPLAYS";
362 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
363 return "SVGA_REG_DISPLAY_ID";
364 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
365 return "SVGA_REG_DISPLAY_IS_PRIMARY";
366 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
367 return "SVGA_REG_DISPLAY_POSITION_X";
368 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
369 return "SVGA_REG_DISPLAY_POSITION_Y";
370 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
371 return "SVGA_REG_DISPLAY_WIDTH";
372 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
373 return "SVGA_REG_DISPLAY_HEIGHT";
374 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
375 return "SVGA_REG_NUM_DISPLAYS";
376
377 default:
378 if (pThis->svga.u32IndexReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
379 return "SVGA_SCRATCH_BASE reg";
380 if (pThis->svga.u32IndexReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
381 return "SVGA_PALETTE_BASE reg";
382 return "UNKNOWN";
383 }
384}
385
386/**
387 * FIFO command name lookup
388 *
389 * @returns FIFO command string or "UNKNOWN"
390 * @param u32Cmd FIFO command
391 */
392static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
393{
394 switch (u32Cmd)
395 {
396 case SVGA_CMD_INVALID_CMD:
397 return "SVGA_CMD_INVALID_CMD";
398 case SVGA_CMD_UPDATE:
399 return "SVGA_CMD_UPDATE";
400 case SVGA_CMD_RECT_COPY:
401 return "SVGA_CMD_RECT_COPY";
402 case SVGA_CMD_DEFINE_CURSOR:
403 return "SVGA_CMD_DEFINE_CURSOR";
404 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
405 return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
406 case SVGA_CMD_UPDATE_VERBOSE:
407 return "SVGA_CMD_UPDATE_VERBOSE";
408 case SVGA_CMD_FRONT_ROP_FILL:
409 return "SVGA_CMD_FRONT_ROP_FILL";
410 case SVGA_CMD_FENCE:
411 return "SVGA_CMD_FENCE";
412 case SVGA_CMD_ESCAPE:
413 return "SVGA_CMD_ESCAPE";
414 case SVGA_CMD_DEFINE_SCREEN:
415 return "SVGA_CMD_DEFINE_SCREEN";
416 case SVGA_CMD_DESTROY_SCREEN:
417 return "SVGA_CMD_DESTROY_SCREEN";
418 case SVGA_CMD_DEFINE_GMRFB:
419 return "SVGA_CMD_DEFINE_GMRFB";
420 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
421 return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
422 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
423 return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
424 case SVGA_CMD_ANNOTATION_FILL:
425 return "SVGA_CMD_ANNOTATION_FILL";
426 case SVGA_CMD_ANNOTATION_COPY:
427 return "SVGA_CMD_ANNOTATION_COPY";
428 case SVGA_CMD_DEFINE_GMR2:
429 return "SVGA_CMD_DEFINE_GMR2";
430 case SVGA_CMD_REMAP_GMR2:
431 return "SVGA_CMD_REMAP_GMR2";
432 case SVGA_3D_CMD_SURFACE_DEFINE:
433 return "SVGA_3D_CMD_SURFACE_DEFINE";
434 case SVGA_3D_CMD_SURFACE_DESTROY:
435 return "SVGA_3D_CMD_SURFACE_DESTROY";
436 case SVGA_3D_CMD_SURFACE_COPY:
437 return "SVGA_3D_CMD_SURFACE_COPY";
438 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
439 return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
440 case SVGA_3D_CMD_SURFACE_DMA:
441 return "SVGA_3D_CMD_SURFACE_DMA";
442 case SVGA_3D_CMD_CONTEXT_DEFINE:
443 return "SVGA_3D_CMD_CONTEXT_DEFINE";
444 case SVGA_3D_CMD_CONTEXT_DESTROY:
445 return "SVGA_3D_CMD_CONTEXT_DESTROY";
446 case SVGA_3D_CMD_SETTRANSFORM:
447 return "SVGA_3D_CMD_SETTRANSFORM";
448 case SVGA_3D_CMD_SETZRANGE:
449 return "SVGA_3D_CMD_SETZRANGE";
450 case SVGA_3D_CMD_SETRENDERSTATE:
451 return "SVGA_3D_CMD_SETRENDERSTATE";
452 case SVGA_3D_CMD_SETRENDERTARGET:
453 return "SVGA_3D_CMD_SETRENDERTARGET";
454 case SVGA_3D_CMD_SETTEXTURESTATE:
455 return "SVGA_3D_CMD_SETTEXTURESTATE";
456 case SVGA_3D_CMD_SETMATERIAL:
457 return "SVGA_3D_CMD_SETMATERIAL";
458 case SVGA_3D_CMD_SETLIGHTDATA:
459 return "SVGA_3D_CMD_SETLIGHTDATA";
460 case SVGA_3D_CMD_SETLIGHTENABLED:
461 return "SVGA_3D_CMD_SETLIGHTENABLED";
462 case SVGA_3D_CMD_SETVIEWPORT:
463 return "SVGA_3D_CMD_SETVIEWPORT";
464 case SVGA_3D_CMD_SETCLIPPLANE:
465 return "SVGA_3D_CMD_SETCLIPPLANE";
466 case SVGA_3D_CMD_CLEAR:
467 return "SVGA_3D_CMD_CLEAR";
468 case SVGA_3D_CMD_PRESENT:
469 return "SVGA_3D_CMD_PRESENT";
470 case SVGA_3D_CMD_SHADER_DEFINE:
471 return "SVGA_3D_CMD_SHADER_DEFINE";
472 case SVGA_3D_CMD_SHADER_DESTROY:
473 return "SVGA_3D_CMD_SHADER_DESTROY";
474 case SVGA_3D_CMD_SET_SHADER:
475 return "SVGA_3D_CMD_SET_SHADER";
476 case SVGA_3D_CMD_SET_SHADER_CONST:
477 return "SVGA_3D_CMD_SET_SHADER_CONST";
478 case SVGA_3D_CMD_DRAW_PRIMITIVES:
479 return "SVGA_3D_CMD_DRAW_PRIMITIVES";
480 case SVGA_3D_CMD_SETSCISSORRECT:
481 return "SVGA_3D_CMD_SETSCISSORRECT";
482 case SVGA_3D_CMD_BEGIN_QUERY:
483 return "SVGA_3D_CMD_BEGIN_QUERY";
484 case SVGA_3D_CMD_END_QUERY:
485 return "SVGA_3D_CMD_END_QUERY";
486 case SVGA_3D_CMD_WAIT_FOR_QUERY:
487 return "SVGA_3D_CMD_WAIT_FOR_QUERY";
488 case SVGA_3D_CMD_PRESENT_READBACK:
489 return "SVGA_3D_CMD_PRESENT_READBACK";
490 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
491 return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
492 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
493 return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
494 case SVGA_3D_CMD_GENERATE_MIPMAPS:
495 return "SVGA_3D_CMD_GENERATE_MIPMAPS";
496 case SVGA_3D_CMD_ACTIVATE_SURFACE:
497 return "SVGA_3D_CMD_ACTIVATE_SURFACE";
498 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
499 return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
500 default:
501 return "UNKNOWN";
502 }
503}
504#endif
505
506/**
507 * Inform the VGA device of viewport changes (as a result of e.g. scrolling)
508 *
509 * @param pInterface Pointer to this interface.
510 * @param
511 * @param uScreenId The screen updates are for.
512 * @param x The upper left corner x coordinate of the new viewport rectangle
513 * @param y The upper left corner y coordinate of the new viewport rectangle
514 * @param cx The width of the new viewport rectangle
515 * @param cy The height of the new viewport rectangle
516 * @thread The emulation thread.
517 */
518DECLCALLBACK(void) vmsvgaPortSetViewPort(PPDMIDISPLAYPORT pInterface, uint32_t uScreenId, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
519{
520 PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
521
522 Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", uScreenId, x, y, cx, cy));
523
524 pThis->svga.viewport.x = x;
525 pThis->svga.viewport.y = y;
526 pThis->svga.viewport.cx = RT_MIN(cx, (uint32_t)pThis->svga.uWidth);
527 pThis->svga.viewport.cy = RT_MIN(cy, (uint32_t)pThis->svga.uHeight);
528 return;
529}
530
531/**
532 * Read port register
533 *
534 * @returns VBox status code.
535 * @param pThis VMSVGA State
536 * @param pu32 Where to store the read value
537 */
538PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
539{
540 int rc = VINF_SUCCESS;
541
542 *pu32 = 0;
543 switch (pThis->svga.u32IndexReg)
544 {
545 case SVGA_REG_ID:
546 *pu32 = pThis->svga.u32SVGAId;
547 break;
548
549 case SVGA_REG_ENABLE:
550 *pu32 = pThis->svga.fEnabled;
551 break;
552
553 case SVGA_REG_WIDTH:
554 {
555 if ( pThis->svga.fEnabled
556 && pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
557 {
558 *pu32 = pThis->svga.uWidth;
559 }
560 else
561 {
562#ifndef IN_RING3
563 rc = VINF_IOM_R3_IOPORT_READ;
564#else
565 *pu32 = pThis->pDrv->cx;
566#endif
567 }
568 break;
569 }
570
571 case SVGA_REG_HEIGHT:
572 {
573 if ( pThis->svga.fEnabled
574 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
575 {
576 *pu32 = pThis->svga.uHeight;
577 }
578 else
579 {
580#ifndef IN_RING3
581 rc = VINF_IOM_R3_IOPORT_READ;
582#else
583 *pu32 = pThis->pDrv->cy;
584#endif
585 }
586 break;
587 }
588
589 case SVGA_REG_MAX_WIDTH:
590 *pu32 = pThis->svga.u32MaxWidth;
591 break;
592
593 case SVGA_REG_MAX_HEIGHT:
594 *pu32 = pThis->svga.u32MaxHeight;
595 break;
596
597 case SVGA_REG_DEPTH:
598 /* This returns the color depth of the current mode. */
599 switch (pThis->svga.uBpp)
600 {
601 case 15:
602 case 16:
603 case 24:
604 *pu32 = pThis->svga.uBpp;
605 break;
606
607 default:
608 case 32:
609 *pu32 = 24; /* The upper 8 bits are either alpha bits or not used. */
610 break;
611 }
612 break;
613
614 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
615 if ( pThis->svga.fEnabled
616 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
617 {
618 *pu32 = pThis->svga.uBpp;
619 }
620 else
621 {
622#ifndef IN_RING3
623 rc = VINF_IOM_R3_IOPORT_READ;
624#else
625 *pu32 = pThis->pDrv->cBits;
626#endif
627 }
628 break;
629
630 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
631 if ( pThis->svga.fEnabled
632 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
633 {
634 *pu32 = (pThis->svga.uBpp + 7) & ~7;
635 }
636 else
637 {
638#ifndef IN_RING3
639 rc = VINF_IOM_R3_IOPORT_READ;
640#else
641 *pu32 = (pThis->pDrv->cBits + 7) & ~7;
642#endif
643 }
644 break;
645
646 case SVGA_REG_PSEUDOCOLOR:
647 *pu32 = 0;
648 break;
649
650 case SVGA_REG_RED_MASK:
651 case SVGA_REG_GREEN_MASK:
652 case SVGA_REG_BLUE_MASK:
653 {
654 uint32_t uBpp;
655
656 if ( pThis->svga.fEnabled
657 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
658 {
659 uBpp = pThis->svga.uBpp;
660 }
661 else
662 {
663#ifndef IN_RING3
664 rc = VINF_IOM_R3_IOPORT_READ;
665 break;
666#else
667 uBpp = pThis->pDrv->cBits;
668#endif
669 }
670 uint32_t u32RedMask, u32GreenMask, u32BlueMask;
671 switch (uBpp)
672 {
673 case 8:
674 u32RedMask = 0x07;
675 u32GreenMask = 0x38;
676 u32BlueMask = 0xc0;
677 break;
678
679 case 15:
680 u32RedMask = 0x0000001f;
681 u32GreenMask = 0x000003e0;
682 u32BlueMask = 0x00007c00;
683 break;
684
685 case 16:
686 u32RedMask = 0x0000001f;
687 u32GreenMask = 0x000007e0;
688 u32BlueMask = 0x0000f800;
689 break;
690
691 case 24:
692 case 32:
693 default:
694 u32RedMask = 0x00ff0000;
695 u32GreenMask = 0x0000ff00;
696 u32BlueMask = 0x000000ff;
697 break;
698 }
699 switch (pThis->svga.u32IndexReg)
700 {
701 case SVGA_REG_RED_MASK:
702 *pu32 = u32RedMask;
703 break;
704
705 case SVGA_REG_GREEN_MASK:
706 *pu32 = u32GreenMask;
707 break;
708
709 case SVGA_REG_BLUE_MASK:
710 *pu32 = u32BlueMask;
711 break;
712 }
713 break;
714 }
715
716 case SVGA_REG_BYTES_PER_LINE:
717 {
718 if ( pThis->svga.fEnabled
719 && pThis->svga.cbScanline)
720 {
721 *pu32 = pThis->svga.cbScanline;
722 }
723 else
724 {
725#ifndef IN_RING3
726 rc = VINF_IOM_R3_IOPORT_READ;
727#else
728 *pu32 = pThis->pDrv->cbScanline;
729#endif
730 }
731 break;
732 }
733
734 case SVGA_REG_VRAM_SIZE: /* VRAM size */
735 *pu32 = pThis->vram_size;
736 break;
737
738 case SVGA_REG_FB_START: /* Frame buffer physical address. */
739 Assert(pThis->GCPhysVRAM <= 0xffffffff);
740 *pu32 = pThis->GCPhysVRAM;
741 break;
742
743 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
744 /* Always zero in our case. */
745 *pu32 = 0;
746 break;
747
748 case SVGA_REG_FB_SIZE: /* Frame buffer size */
749 {
750#ifndef IN_RING3
751 rc = VINF_IOM_R3_IOPORT_READ;
752#else
753 /* VMWare testcases want at least 4 MB in case the hardware is disabled. */
754 if ( pThis->svga.fEnabled
755 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
756 {
757 /* Hardware enabled; return real framebuffer size .*/
758 *pu32 = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
759 }
760 else
761 *pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy * pThis->pDrv->cbScanline);
762
763 *pu32 = RT_MIN(pThis->vram_size, *pu32);
764 Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
765#endif
766 break;
767 }
768
769 case SVGA_REG_CAPABILITIES:
770 *pu32 = pThis->svga.u32RegCaps;
771 break;
772
773 case SVGA_REG_MEM_START: /* FIFO start */
774 Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
775 *pu32 = pThis->svga.GCPhysFIFO;
776 break;
777
778 case SVGA_REG_MEM_SIZE: /* FIFO size */
779 *pu32 = pThis->svga.cbFIFO;
780 break;
781
782 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
783 *pu32 = pThis->svga.fConfigured;
784 break;
785
786 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
787 *pu32 = 0;
788 break;
789
790 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
791 if (pThis->svga.fBusy)
792 {
793#ifndef IN_RING3
794 /* Go to ring-3 and halt the CPU. */
795 rc = VINF_IOM_R3_IOPORT_READ;
796 break;
797#elif defined(VMSVGA_USE_EMT_HALT_CODE)
798 /* The guest is basically doing a HLT via the device here, but with
799 a special wake up condition on FIFO completion. */
800 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
801 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
802 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
803 VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
804 VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
805 ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
806 if (pThis->svga.fBusy)
807 rc = VMR3WaitForDeviceReady(pVM, idCpu);
808 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
809 VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
810#else
811
812 /* Delay the EMT a bit so the FIFO and others can get some work done.
813 This used to be a crude 50 ms sleep. The current code tries to be
814 more efficient, but the consept is still very crude. */
815 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
816 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
817 RTThreadYield();
818 if (pThis->svga.fBusy)
819 {
820 uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
821
822 if (pThis->svga.fBusy && cRefs == 1)
823 RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
824 if (pThis->svga.fBusy)
825 {
826 /** @todo If this code is going to stay, we need to call into the halt/wait
827 * code in VMEmt.cpp here, otherwise all kind of EMT interaction will
828 * suffer when the guest is polling on a busy FIFO. */
829 uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
830 if (cNsMaxWait >= RT_NS_100US)
831 RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
832 RTSEMWAIT_FLAGS_NANOSECS | RTSEMWAIT_FLAGS_RELATIVE | RTSEMWAIT_FLAGS_NORESUME,
833 RT_MIN(cNsMaxWait, RT_NS_10MS));
834 }
835
836 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
837 }
838 STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
839#endif
840 *pu32 = pThis->svga.fBusy != 0;
841 }
842 else
843 *pu32 = false;
844 break;
845
846 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
847 *pu32 = pThis->svga.u32GuestId;
848 break;
849
850 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
851 *pu32 = pThis->svga.cScratchRegion;
852 break;
853
854 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
855 *pu32 = SVGA_FIFO_NUM_REGS;
856 break;
857
858 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
859 *pu32 = pThis->svga.u32PitchLock;
860 break;
861
862 case SVGA_REG_IRQMASK: /* Interrupt mask */
863 *pu32 = pThis->svga.u32IrqMask;
864 break;
865
866 /* See "Guest memory regions" below. */
867 case SVGA_REG_GMR_ID:
868 *pu32 = pThis->svga.u32CurrentGMRId;
869 break;
870
871 case SVGA_REG_GMR_DESCRIPTOR:
872 /* Write only */
873 *pu32 = 0;
874 break;
875
876 case SVGA_REG_GMR_MAX_IDS:
877 *pu32 = VMSVGA_MAX_GMR_IDS;
878 break;
879
880 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
881 *pu32 = VMSVGA_MAX_GMR_PAGES;
882 break;
883
884 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
885 *pu32 = pThis->svga.fTraces;
886 break;
887
888 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
889 *pu32 = VMSVGA_MAX_GMR_PAGES;
890 break;
891
892 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
893 *pu32 = VMSVGA_SURFACE_SIZE;
894 break;
895
896 case SVGA_REG_TOP: /* Must be 1 more than the last register */
897 break;
898
899 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
900 break;
901 /* Next 768 (== 256*3) registers exist for colormap */
902
903 /* Mouse cursor support. */
904 case SVGA_REG_CURSOR_ID:
905 case SVGA_REG_CURSOR_X:
906 case SVGA_REG_CURSOR_Y:
907 case SVGA_REG_CURSOR_ON:
908 break;
909
910 /* Legacy multi-monitor support */
911 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
912 *pu32 = 1;
913 break;
914
915 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
916 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
917 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
918 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
919 *pu32 = 0;
920 break;
921
922 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
923 *pu32 = pThis->svga.uWidth;
924 break;
925
926 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
927 *pu32 = pThis->svga.uHeight;
928 break;
929
930 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
931 *pu32 = 1; /* Must return something sensible here otherwise the Linux driver will take a legacy code path without 3d support. */
932 break;
933
934 default:
935 if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE
936 && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
937 {
938 *pu32 = pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE];
939 }
940 break;
941 }
942 Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, *pu32, rc));
943 return rc;
944}
945
946#ifdef IN_RING3
947/**
948 * Apply the current resolution settings to change the video mode.
949 *
950 * @returns VBox status code.
951 * @param pThis VMSVGA State
952 */
953int vmsvgaChangeMode(PVGASTATE pThis)
954{
955 int rc;
956
957 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
958 || pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
959 || pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
960 {
961 /* Mode change in progress; wait for all values to be set. */
962 Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
963 return VINF_SUCCESS;
964 }
965
966 if ( pThis->svga.uWidth == 0
967 || pThis->svga.uHeight == 0
968 || pThis->svga.uBpp == 0)
969 {
970 /* Invalid mode change. */
971 Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
972 return VINF_SUCCESS;
973 }
974
975 if ( pThis->last_bpp == (unsigned)pThis->svga.uBpp
976 && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
977 && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
978 && pThis->last_width == (unsigned)pThis->svga.uWidth
979 && pThis->last_height == (unsigned)pThis->svga.uHeight
980 )
981 {
982 /* Nothing to do. */
983 Log(("vmsvgaChangeMode: nothing changed; ignore\n"));
984 return VINF_SUCCESS;
985 }
986
987 Log(("vmsvgaChangeMode: sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
988 pThis->svga.cbScanline = ((pThis->svga.uWidth * pThis->svga.uBpp + 7) & ~7) / 8;
989
990 pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
991 rc = pThis->pDrv->pfnResize(pThis->pDrv, pThis->svga.uBpp, pThis->CTX_SUFF(vram_ptr), pThis->svga.cbScanline, pThis->svga.uWidth, pThis->svga.uHeight);
992 AssertRC(rc);
993 AssertReturn(rc == VINF_SUCCESS || rc == VINF_VGA_RESIZE_IN_PROGRESS, rc);
994
995 /* last stuff */
996 pThis->last_bpp = pThis->svga.uBpp;
997 pThis->last_scr_width = pThis->svga.uWidth;
998 pThis->last_scr_height = pThis->svga.uHeight;
999 pThis->last_width = pThis->svga.uWidth;
1000 pThis->last_height = pThis->svga.uHeight;
1001
1002 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1003
1004 /* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1005 if ( pThis->svga.viewport.cx == 0
1006 && pThis->svga.viewport.cy == 0)
1007 {
1008 pThis->svga.viewport.cx = pThis->svga.uWidth;
1009 pThis->svga.viewport.cy = pThis->svga.uHeight;
1010 }
1011 return VINF_SUCCESS;
1012}
1013#endif /* IN_RING3 */
1014
1015#if defined(IN_RING0) || defined(IN_RING3)
1016/**
1017 * Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1018 *
1019 * @param pThis The VMSVGA state.
1020 * @param fState The busy state.
1021 */
1022DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1023{
1024 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1025
1026 if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1027 {
1028 /* Race / unfortunately scheduling. Highly unlikly. */
1029 uint32_t cLoops = 64;
1030 do
1031 {
1032 ASMNopPause();
1033 fState = (pThis->svga.fBusy != 0);
1034 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1035 } while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1036 }
1037}
1038#endif
1039
1040/**
1041 * Write port register
1042 *
1043 * @returns VBox status code.
1044 * @param pThis VMSVGA State
1045 * @param u32 Value to write
1046 */
1047PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1048{
1049 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
1050 int rc = VINF_SUCCESS;
1051
1052 Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, u32));
1053 switch (pThis->svga.u32IndexReg)
1054 {
1055 case SVGA_REG_ID:
1056 if ( u32 == SVGA_ID_0
1057 || u32 == SVGA_ID_1
1058 || u32 == SVGA_ID_2)
1059 pThis->svga.u32SVGAId = u32;
1060 break;
1061
1062 case SVGA_REG_ENABLE:
1063 if ( pThis->svga.fEnabled == u32
1064 && pThis->last_bpp == (unsigned)pThis->svga.uBpp
1065 && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1066 && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1067 && pThis->last_width == (unsigned)pThis->svga.uWidth
1068 && pThis->last_height == (unsigned)pThis->svga.uHeight
1069 )
1070 /* Nothing to do. */
1071 break;
1072
1073#ifdef IN_RING3
1074 if ( u32 == 1
1075 && pThis->svga.fEnabled == false)
1076 {
1077 /* Make a backup copy of the first 32k in order to save font data etc. */
1078 memcpy(pThis->svga.pFrameBufferBackup, pThis->vram_ptrR3, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
1079 }
1080
1081 pThis->svga.fEnabled = u32;
1082 if (pThis->svga.fEnabled)
1083 {
1084 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1085 && pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1086 && pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1087 {
1088 /* Keep the current mode. */
1089 pThis->svga.uWidth = pThis->pDrv->cx;
1090 pThis->svga.uHeight = pThis->pDrv->cy;
1091 pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1092 }
1093
1094 if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1095 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1096 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1097 {
1098 rc = vmsvgaChangeMode(pThis);
1099 AssertRCReturn(rc, rc);
1100 }
1101 Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
1102 uint32_t *pFIFO = pThis->svga.pFIFOR3;
1103 Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1104
1105 /* Disable or enable dirty page tracking according to the current fTraces value. */
1106 vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1107 }
1108 else
1109 {
1110 /* Restore the text mode backup. */
1111 memcpy(pThis->vram_ptrR3, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
1112
1113/* pThis->svga.uHeight = -1;
1114 pThis->svga.uWidth = -1;
1115 pThis->svga.uBpp = -1;
1116 pThis->svga.cbScanline = 0; */
1117 pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1118
1119 /* Enable dirty page tracking again when going into legacy mode. */
1120 vmsvgaSetTraces(pThis, true);
1121 }
1122#else
1123 rc = VINF_IOM_R3_IOPORT_WRITE;
1124#endif
1125 break;
1126
1127 case SVGA_REG_WIDTH:
1128 if (pThis->svga.uWidth != u32)
1129 {
1130 if (pThis->svga.fEnabled)
1131 {
1132#ifdef IN_RING3
1133 pThis->svga.uWidth = u32;
1134 rc = vmsvgaChangeMode(pThis);
1135 AssertRCReturn(rc, rc);
1136#else
1137 rc = VINF_IOM_R3_IOPORT_WRITE;
1138#endif
1139 }
1140 else
1141 pThis->svga.uWidth = u32;
1142 }
1143 /* else: nop */
1144 break;
1145
1146 case SVGA_REG_HEIGHT:
1147 if (pThis->svga.uHeight != u32)
1148 {
1149 if (pThis->svga.fEnabled)
1150 {
1151#ifdef IN_RING3
1152 pThis->svga.uHeight = u32;
1153 rc = vmsvgaChangeMode(pThis);
1154 AssertRCReturn(rc, rc);
1155#else
1156 rc = VINF_IOM_R3_IOPORT_WRITE;
1157#endif
1158 }
1159 else
1160 pThis->svga.uHeight = u32;
1161 }
1162 /* else: nop */
1163 break;
1164
1165 case SVGA_REG_DEPTH:
1166 /** @todo read-only?? */
1167 break;
1168
1169 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1170 if (pThis->svga.uBpp != u32)
1171 {
1172 if (pThis->svga.fEnabled)
1173 {
1174#ifdef IN_RING3
1175 pThis->svga.uBpp = u32;
1176 rc = vmsvgaChangeMode(pThis);
1177 AssertRCReturn(rc, rc);
1178#else
1179 rc = VINF_IOM_R3_IOPORT_WRITE;
1180#endif
1181 }
1182 else
1183 pThis->svga.uBpp = u32;
1184 }
1185 /* else: nop */
1186 break;
1187
1188 case SVGA_REG_PSEUDOCOLOR:
1189 break;
1190
1191 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1192#ifdef IN_RING3
1193 pThis->svga.fConfigured = u32;
1194 /* Disabling the FIFO enables tracing (dirty page detection) by default. */
1195 if (!pThis->svga.fConfigured)
1196 {
1197 pThis->svga.fTraces = true;
1198 }
1199 vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1200#else
1201 rc = VINF_IOM_R3_IOPORT_WRITE;
1202#endif
1203 break;
1204
1205 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1206 if ( pThis->svga.fEnabled
1207 && pThis->svga.fConfigured)
1208 {
1209#if defined(IN_RING3) || defined(IN_RING0)
1210 Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1211 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE | VMSVGA_BUSY_F_FIFO);
1212 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1213 vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1214
1215 /* Kick the FIFO thread to start processing commands again. */
1216 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1217#else
1218 rc = VINF_IOM_R3_IOPORT_WRITE;
1219#endif
1220 }
1221 /* else nothing to do. */
1222 else
1223 Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1224
1225 break;
1226
1227 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1228 break;
1229
1230 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1231 pThis->svga.u32GuestId = u32;
1232 break;
1233
1234 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1235 pThis->svga.u32PitchLock = u32;
1236 break;
1237
1238 case SVGA_REG_IRQMASK: /* Interrupt mask */
1239 pThis->svga.u32IrqMask = u32;
1240
1241 /* Irq pending after the above change? */
1242 if (pThis->svga.u32IrqStatus & u32)
1243 {
1244 Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1245 PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1246 }
1247 else
1248 PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1249 break;
1250
1251 /* Mouse cursor support */
1252 case SVGA_REG_CURSOR_ID:
1253 case SVGA_REG_CURSOR_X:
1254 case SVGA_REG_CURSOR_Y:
1255 case SVGA_REG_CURSOR_ON:
1256 break;
1257
1258 /* Legacy multi-monitor support */
1259 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1260 break;
1261 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1262 break;
1263 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1264 break;
1265 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1266 break;
1267 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1268 break;
1269 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1270 break;
1271 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1272 break;
1273#ifdef VBOX_WITH_VMSVGA3D
1274 /* See "Guest memory regions" below. */
1275 case SVGA_REG_GMR_ID:
1276 pThis->svga.u32CurrentGMRId = u32;
1277 break;
1278
1279 case SVGA_REG_GMR_DESCRIPTOR:
1280# ifndef IN_RING3
1281 rc = VINF_IOM_R3_IOPORT_WRITE;
1282 break;
1283# else /* IN_RING3 */
1284 {
1285 SVGAGuestMemDescriptor desc;
1286 RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1287 RTGCPHYS GCPhysBase = GCPhys;
1288 uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1289 uint32_t cDescriptorsAllocated = 16;
1290 uint32_t iDescriptor = 0;
1291
1292 /* Validate current GMR id. */
1293 AssertBreak(idGMR < VMSVGA_MAX_GMR_IDS);
1294
1295 /* Free the old GMR if present. */
1296 vmsvgaGMRFree(pThis, idGMR);
1297
1298 /* Just undefine the GMR? */
1299 if (GCPhys == 0)
1300 break;
1301
1302 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1303 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1304
1305 /* Never cross a page boundary automatically. */
1306 while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1307 {
1308 /* Read descriptor. */
1309 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1310 AssertRCBreak(rc);
1311
1312 if ( desc.ppn == 0
1313 && desc.numPages == 0)
1314 break; /* terminator */
1315
1316 if ( desc.ppn != 0
1317 && desc.numPages == 0)
1318 {
1319 /* Pointer to the next physical page of descriptors. */
1320 GCPhys = GCPhysBase = desc.ppn << PAGE_SHIFT;
1321 }
1322 else
1323 {
1324 if (iDescriptor == cDescriptorsAllocated)
1325 {
1326 cDescriptorsAllocated += 16;
1327 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemRealloc(pSVGAState->aGMR[idGMR].paDesc, cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1328 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1329 }
1330
1331 pSVGAState->aGMR[idGMR].paDesc[iDescriptor].GCPhys = desc.ppn << PAGE_SHIFT;
1332 pSVGAState->aGMR[idGMR].paDesc[iDescriptor++].numPages = desc.numPages;
1333 pSVGAState->aGMR[idGMR].cbTotal += desc.numPages * PAGE_SIZE;
1334
1335 /* Continue with the next descriptor. */
1336 GCPhys += sizeof(desc);
1337 }
1338 }
1339 pSVGAState->aGMR[idGMR].numDescriptors = iDescriptor;
1340 Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x\n", idGMR, iDescriptor, pSVGAState->aGMR[idGMR].cbTotal));
1341
1342 if (!pSVGAState->aGMR[idGMR].numDescriptors)
1343 {
1344 AssertFailed();
1345 RTMemFree(pSVGAState->aGMR[idGMR].paDesc);
1346 pSVGAState->aGMR[idGMR].paDesc = NULL;
1347 }
1348 AssertRC(rc);
1349 break;
1350 }
1351# endif /* IN_RING3 */
1352#endif // VBOX_WITH_VMSVGA3D
1353
1354 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1355 if (pThis->svga.fTraces == u32)
1356 break; /* nothing to do */
1357
1358#ifdef IN_RING3
1359 vmsvgaSetTraces(pThis, !!u32);
1360#else
1361 rc = VINF_IOM_R3_IOPORT_WRITE;
1362#endif
1363 break;
1364
1365 case SVGA_REG_TOP: /* Must be 1 more than the last register */
1366 break;
1367
1368 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
1369 break;
1370 /* Next 768 (== 256*3) registers exist for colormap */
1371
1372 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1373 Log(("Write to deprecated register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
1374 break;
1375
1376 case SVGA_REG_FB_START:
1377 case SVGA_REG_MEM_START:
1378 case SVGA_REG_HOST_BITS_PER_PIXEL:
1379 case SVGA_REG_MAX_WIDTH:
1380 case SVGA_REG_MAX_HEIGHT:
1381 case SVGA_REG_VRAM_SIZE:
1382 case SVGA_REG_FB_SIZE:
1383 case SVGA_REG_CAPABILITIES:
1384 case SVGA_REG_MEM_SIZE:
1385 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1386 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1387 case SVGA_REG_BYTES_PER_LINE:
1388 case SVGA_REG_FB_OFFSET:
1389 case SVGA_REG_RED_MASK:
1390 case SVGA_REG_GREEN_MASK:
1391 case SVGA_REG_BLUE_MASK:
1392 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1393 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1394 case SVGA_REG_GMR_MAX_IDS:
1395 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1396 /* Read only - ignore. */
1397 Log(("Write to R/O register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
1398 break;
1399
1400 default:
1401 if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE
1402 && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
1403 {
1404 pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE] = u32;
1405 }
1406 break;
1407 }
1408 return rc;
1409}
1410
1411/**
1412 * Port I/O Handler for IN operations.
1413 *
1414 * @returns VINF_SUCCESS or VINF_EM_*.
1415 * @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1416 *
1417 * @param pDevIns The device instance.
1418 * @param pvUser User argument.
1419 * @param uPort Port number used for the IN operation.
1420 * @param pu32 Where to store the result. This is always a 32-bit
1421 * variable regardless of what @a cb might say.
1422 * @param cb Number of bytes read.
1423 */
1424PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1425{
1426 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1427 int rc = VINF_SUCCESS;
1428
1429 /* Ignore non-dword accesses. */
1430 if (cb != 4)
1431 {
1432 Log(("Ignoring non-dword read at %x cb=%d\n", Port, cb));
1433 *pu32 = ~0;
1434 return VINF_SUCCESS;
1435 }
1436
1437 switch (Port - pThis->svga.BasePort)
1438 {
1439 case SVGA_INDEX_PORT:
1440 *pu32 = pThis->svga.u32IndexReg;
1441 break;
1442
1443 case SVGA_VALUE_PORT:
1444 return vmsvgaReadPort(pThis, pu32);
1445
1446 case SVGA_BIOS_PORT:
1447 Log(("Ignoring BIOS port read\n"));
1448 *pu32 = 0;
1449 break;
1450
1451 case SVGA_IRQSTATUS_PORT:
1452 LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1453 *pu32 = pThis->svga.u32IrqStatus;
1454 break;
1455 }
1456 return rc;
1457}
1458
1459/**
1460 * Port I/O Handler for OUT operations.
1461 *
1462 * @returns VINF_SUCCESS or VINF_EM_*.
1463 *
1464 * @param pDevIns The device instance.
1465 * @param pvUser User argument.
1466 * @param uPort Port number used for the OUT operation.
1467 * @param u32 The value to output.
1468 * @param cb The value size in bytes.
1469 */
1470PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1471{
1472 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1473 int rc = VINF_SUCCESS;
1474
1475 /* Ignore non-dword accesses. */
1476 if (cb != 4)
1477 {
1478 Log(("Ignoring non-dword write at %x val=%x cb=%d\n", Port, u32, cb));
1479 return VINF_SUCCESS;
1480 }
1481
1482 switch (Port - pThis->svga.BasePort)
1483 {
1484 case SVGA_INDEX_PORT:
1485 pThis->svga.u32IndexReg = u32;
1486 break;
1487
1488 case SVGA_VALUE_PORT:
1489 return vmsvgaWritePort(pThis, u32);
1490
1491 case SVGA_BIOS_PORT:
1492 Log(("Ignoring BIOS port write (val=%x)\n", u32));
1493 break;
1494
1495 case SVGA_IRQSTATUS_PORT:
1496 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
1497 ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
1498 /* Clear the irq in case all events have been cleared. */
1499 if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
1500 {
1501 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
1502 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1503 }
1504 break;
1505 }
1506 return rc;
1507}
1508
1509#ifdef DEBUG_FIFO_ACCESS
1510
1511# ifdef IN_RING3
1512/**
1513 * Handle LFB access.
1514 * @returns VBox status code.
1515 * @param pVM VM handle.
1516 * @param pThis VGA device instance data.
1517 * @param GCPhys The access physical address.
1518 * @param fWriteAccess Read or write access
1519 */
1520static int vmsvgaFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
1521{
1522 RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
1523 uint32_t *pFIFO = pThis->svga.pFIFOR3;
1524
1525 switch (GCPhysOffset >> 2)
1526 {
1527 case SVGA_FIFO_MIN:
1528 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1529 break;
1530 case SVGA_FIFO_MAX:
1531 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1532 break;
1533 case SVGA_FIFO_NEXT_CMD:
1534 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1535 break;
1536 case SVGA_FIFO_STOP:
1537 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1538 break;
1539 case SVGA_FIFO_CAPABILITIES:
1540 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1541 break;
1542 case SVGA_FIFO_FLAGS:
1543 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1544 break;
1545 case SVGA_FIFO_FENCE:
1546 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1547 break;
1548 case SVGA_FIFO_3D_HWVERSION:
1549 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1550 break;
1551 case SVGA_FIFO_PITCHLOCK:
1552 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1553 break;
1554 case SVGA_FIFO_CURSOR_ON:
1555 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1556 break;
1557 case SVGA_FIFO_CURSOR_X:
1558 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1559 break;
1560 case SVGA_FIFO_CURSOR_Y:
1561 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1562 break;
1563 case SVGA_FIFO_CURSOR_COUNT:
1564 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1565 break;
1566 case SVGA_FIFO_CURSOR_LAST_UPDATED:
1567 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1568 break;
1569 case SVGA_FIFO_RESERVED:
1570 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1571 break;
1572 case SVGA_FIFO_CURSOR_SCREEN_ID:
1573 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1574 break;
1575 case SVGA_FIFO_DEAD:
1576 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1577 break;
1578 case SVGA_FIFO_3D_HWVERSION_REVISED:
1579 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1580 break;
1581 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
1582 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1583 break;
1584 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
1585 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1586 break;
1587 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
1588 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1589 break;
1590 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
1591 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1592 break;
1593 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
1594 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1595 break;
1596 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
1597 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1598 break;
1599 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
1600 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1601 break;
1602 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
1603 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1604 break;
1605 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
1606 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1607 break;
1608 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
1609 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1610 break;
1611 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
1612 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1613 break;
1614 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
1615 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1616 break;
1617 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
1618 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1619 break;
1620 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
1621 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1622 break;
1623 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
1624 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1625 break;
1626 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
1627 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1628 break;
1629 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
1630 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1631 break;
1632 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
1633 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1634 break;
1635 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
1636 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1637 break;
1638 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
1639 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1640 break;
1641 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
1642 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1643 break;
1644 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
1645 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1646 break;
1647 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
1648 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1649 break;
1650 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
1651 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1652 break;
1653 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
1654 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1655 break;
1656 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
1657 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1658 break;
1659 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
1660 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1661 break;
1662 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
1663 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1664 break;
1665 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
1666 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1667 break;
1668 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
1669 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1670 break;
1671 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
1672 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1673 break;
1674 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
1675 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1676 break;
1677 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
1678 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1679 break;
1680 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
1681 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1682 break;
1683 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
1684 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1685 break;
1686 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
1687 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1688 break;
1689 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
1690 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1691 break;
1692 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
1693 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1694 break;
1695 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
1696 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1697 break;
1698 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
1699 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1700 break;
1701 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
1702 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1703 break;
1704 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
1705 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1706 break;
1707 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
1708 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1709 break;
1710 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
1711 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1712 break;
1713 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
1714 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1715 break;
1716 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
1717 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1718 break;
1719 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
1720 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1721 break;
1722 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
1723 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1724 break;
1725 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
1726 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1727 break;
1728 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
1729 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1730 break;
1731 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
1732 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1733 break;
1734 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
1735 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1736 break;
1737 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
1738 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1739 break;
1740 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
1741 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1742 break;
1743 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
1744 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1745 break;
1746 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
1747 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1748 break;
1749 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
1750 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1751 break;
1752 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
1753 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1754 break;
1755 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
1756 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1757 break;
1758 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
1759 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1760 break;
1761 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
1762 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1763 break;
1764 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
1765 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1766 break;
1767 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
1768 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1769 break;
1770 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
1771 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1772 break;
1773 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
1774 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1775 break;
1776 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
1777 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1778 break;
1779 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
1780 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1781 break;
1782 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
1783 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1784 break;
1785 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
1786 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1787 break;
1788 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
1789 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1790 break;
1791 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
1792 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1793 break;
1794 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
1795 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1796 break;
1797 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
1798 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1799 break;
1800 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
1801 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1802 break;
1803 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
1804 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1805 break;
1806 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
1807 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1808 break;
1809 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
1810 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1811 break;
1812 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
1813 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1814 break;
1815 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
1816 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1817 break;
1818 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
1819 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1820 break;
1821 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
1822 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1823 break;
1824 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
1825 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1826 break;
1827 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
1828 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1829 break;
1830 case SVGA_FIFO_3D_CAPS_LAST:
1831 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1832 break;
1833 case SVGA_FIFO_GUEST_3D_HWVERSION:
1834 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1835 break;
1836 case SVGA_FIFO_FENCE_GOAL:
1837 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1838 break;
1839 case SVGA_FIFO_BUSY:
1840 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1841 break;
1842 default:
1843 Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
1844 break;
1845 }
1846
1847 return VINF_EM_RAW_EMULATE_INSTR;
1848}
1849
1850/**
1851 * HC access handler for the FIFO.
1852 *
1853 * @returns VINF_SUCCESS if the handler have carried out the operation.
1854 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1855 * @param pVM VM Handle.
1856 * @param GCPhys The physical address the guest is writing to.
1857 * @param pvPhys The HC mapping of that address.
1858 * @param pvBuf What the guest is reading/writing.
1859 * @param cbBuf How much it's reading/writing.
1860 * @param enmAccessType The access type.
1861 * @param pvUser User argument.
1862 */
1863static DECLCALLBACK(int) vmsvgaR3FIFOAccessHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1864{
1865 PVGASTATE pThis = (PVGASTATE)pvUser;
1866 int rc;
1867 Assert(pThis);
1868 Assert(GCPhys >= pThis->GCPhysVRAM);
1869 NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf);
1870
1871 rc = vmsvgaFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
1872 if (RT_SUCCESS(rc))
1873 return VINF_PGM_HANDLER_DO_DEFAULT;
1874 AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
1875 return rc;
1876}
1877
1878# endif /* IN_RING3 */
1879#endif /* DEBUG_FIFO_ACCESS */
1880
1881#ifdef DEBUG_GMR_ACCESS
1882/**
1883 * HC access handler for the FIFO.
1884 *
1885 * @returns VINF_SUCCESS if the handler have carried out the operation.
1886 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1887 * @param pVM VM Handle.
1888 * @param GCPhys The physical address the guest is writing to.
1889 * @param pvPhys The HC mapping of that address.
1890 * @param pvBuf What the guest is reading/writing.
1891 * @param cbBuf How much it's reading/writing.
1892 * @param enmAccessType The access type.
1893 * @param pvUser User argument.
1894 */
1895static DECLCALLBACK(int) vmsvgaR3GMRAccessHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1896{
1897 PVGASTATE pThis = (PVGASTATE)pvUser;
1898 Assert(pThis);
1899 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
1900 NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf);
1901
1902 Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
1903
1904 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
1905 {
1906 PGMR pGMR = &pSVGAState->aGMR[i];
1907
1908 if (pGMR->numDescriptors)
1909 {
1910 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
1911 {
1912 if ( GCPhys >= pGMR->paDesc[j].GCPhys
1913 && GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
1914 {
1915 /*
1916 * Turn off the write handler for this particular page and make it R/W.
1917 * Then return telling the caller to restart the guest instruction.
1918 */
1919 int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
1920 goto end;
1921 }
1922 }
1923 }
1924 }
1925end:
1926 return VINF_PGM_HANDLER_DO_DEFAULT;
1927}
1928
1929# ifdef IN_RING3
1930
1931/* Callback handler for VMR3ReqCallWait */
1932static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
1933{
1934 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1935 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
1936 PGMR pGMR = &pSVGAState->aGMR[gmrId];
1937 int rc;
1938
1939 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
1940 {
1941 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
1942 pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
1943 pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
1944 AssertRC(rc);
1945 }
1946 return VINF_SUCCESS;
1947}
1948
1949/* Callback handler for VMR3ReqCallWait */
1950static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
1951{
1952 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1953 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
1954 PGMR pGMR = &pSVGAState->aGMR[gmrId];
1955
1956 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
1957 {
1958 int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
1959 AssertRC(rc);
1960 }
1961 return VINF_SUCCESS;
1962}
1963
1964/* Callback handler for VMR3ReqCallWait */
1965static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
1966{
1967 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
1968
1969 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
1970 {
1971 PGMR pGMR = &pSVGAState->aGMR[i];
1972
1973 if (pGMR->numDescriptors)
1974 {
1975 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
1976 {
1977 int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
1978 AssertRC(rc);
1979 }
1980 }
1981 }
1982 return VINF_SUCCESS;
1983}
1984
1985# endif /* IN_RING3 */
1986#endif /* DEBUG_GMR_ACCESS */
1987
1988/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
1989
1990#ifdef IN_RING3
1991
1992/**
1993 * Marks the FIFO non-busy, notifying any waiting EMTs.
1994 *
1995 * @param pThis The VGA state.
1996 * @param pSVGAState Pointer to the ring-3 only SVGA state data.
1997 * @param offFifoMin The start byte offset of the command FIFO.
1998 */
1999static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGASTATE pSVGAState, uint32_t offFifoMin)
2000{
2001 ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
2002 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2003 vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
2004
2005 /* Wake up any waiting EMTs. */
2006 if (pSVGAState->cBusyDelayedEmts > 0)
2007 {
2008#ifdef VMSVGA_USE_EMT_HALT_CODE
2009 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
2010 VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
2011 if (idCpu != NIL_VMCPUID)
2012 {
2013 VMR3NotifyCpuDeviceReady(pVM, idCpu);
2014 while (idCpu-- > 0)
2015 if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
2016 VMR3NotifyCpuDeviceReady(pVM, idCpu);
2017 }
2018#else
2019 int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
2020 AssertRC(rc2);
2021#endif
2022 }
2023}
2024
2025/**
2026 * Reads (more) payload into the command buffer.
2027 *
2028 * @returns pbBounceBuf on success
2029 * @retval (void *)1 if the thread was requested to stop.
2030 * @retval NULL on FIFO error.
2031 *
2032 * @param cbPayloadReq The number of bytes of payload requested.
2033 * @param pFIFO The FIFO.
2034 * @param offCurrentCmd The FIFO byte offset of the current command.
2035 * @param offFifoMin The start byte offset of the command FIFO.
2036 * @param offFifoMax The end byte offset of the command FIFO.
2037 * @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
2038 * always sufficient size.
2039 * @param pcbAlreadyRead How much payload we've already read into the bounce
2040 * buffer. (We will NEVER re-read anything.)
2041 * @param pThread The calling PDM thread handle.
2042 * @param pThis The VGA state.
2043 * @param pSVGAState Pointer to the ring-3 only SVGA state data. For
2044 * statistics collection.
2045 */
2046static void *vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t volatile *pFIFO,
2047 uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
2048 uint8_t *pbBounceBuf, uint32_t *pcbAlreadyRead,
2049 PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGASTATE pSVGAState)
2050{
2051 Assert(pbBounceBuf);
2052 Assert(pcbAlreadyRead);
2053 Assert(offFifoMin < offFifoMax);
2054 Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
2055 Assert(offFifoMax <= VMSVGA_FIFO_SIZE);
2056
2057 /*
2058 * Check if the requested payload size has already been satisfied .
2059 * .
2060 * When called to read more, the caller is responsible for making sure the .
2061 * new command size (cbRequsted) never is smaller than what has already .
2062 * been read.
2063 */
2064 uint32_t cbAlreadyRead = *pcbAlreadyRead;
2065 if (cbPayloadReq <= cbAlreadyRead)
2066 {
2067 AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
2068 return pbBounceBuf;
2069 }
2070
2071 /*
2072 * Commands bigger than the fifo buffer are invalid.
2073 */
2074 uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
2075 AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
2076 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
2077 NULL);
2078
2079 /*
2080 * Move offCurrentCmd past the command dword.
2081 */
2082 offCurrentCmd += sizeof(uint32_t);
2083 if (offCurrentCmd >= offFifoMax)
2084 offCurrentCmd = offFifoMin;
2085
2086 /*
2087 * Do we have sufficient payload data available already?
2088 */
2089 uint32_t cbAfter, cbBefore;
2090 uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2091 if (offNextCmd > offCurrentCmd)
2092 {
2093 if (RT_LIKELY(offNextCmd < offFifoMax))
2094 cbAfter = offNextCmd - offCurrentCmd;
2095 else
2096 {
2097 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2098 LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2099 offNextCmd, offFifoMin, offFifoMax));
2100 cbAfter = offFifoMax - offCurrentCmd;
2101 }
2102 cbBefore = 0;
2103 }
2104 else
2105 {
2106 cbAfter = offFifoMax - offCurrentCmd;
2107 if (offNextCmd >= offFifoMin)
2108 cbBefore = offNextCmd - offFifoMin;
2109 else
2110 {
2111 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2112 LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2113 offNextCmd, offFifoMin, offFifoMax));
2114 cbBefore = 0;
2115 }
2116 }
2117 if (cbAfter + cbBefore < cbPayloadReq)
2118 {
2119 /*
2120 * Insufficient, must wait for it to arrive.
2121 */
2122 STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
2123 for (uint32_t i = 0;; i++)
2124 {
2125 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2126 {
2127 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2128 return (void *)(uintptr_t)1;
2129 }
2130 Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
2131 cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
2132
2133 SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
2134
2135 offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2136 if (offNextCmd > offCurrentCmd)
2137 {
2138 cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
2139 cbBefore = 0;
2140 }
2141 else
2142 {
2143 cbAfter = offFifoMax - offCurrentCmd;
2144 cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
2145 }
2146
2147 if (cbAfter + cbBefore >= cbPayloadReq)
2148 break;
2149 }
2150 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2151 }
2152
2153 /*
2154 * Copy out the memory and update what pcbAlreadyRead points to.
2155 */
2156 if (cbAfter >= cbPayloadReq)
2157 memcpy(pbBounceBuf + cbAlreadyRead,
2158 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
2159 cbPayloadReq - cbAlreadyRead);
2160 else
2161 {
2162 LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
2163 if (cbAlreadyRead < cbAfter)
2164 {
2165 memcpy(pbBounceBuf + cbAlreadyRead,
2166 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
2167 cbAfter - cbAlreadyRead);
2168 cbAlreadyRead = cbAfter;
2169 }
2170 memcpy(pbBounceBuf + cbAlreadyRead,
2171 (uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
2172 cbPayloadReq - cbAlreadyRead);
2173 }
2174 *pcbAlreadyRead = cbPayloadReq;
2175 return pbBounceBuf;
2176}
2177
2178/* The async FIFO handling thread. */
2179static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2180{
2181 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
2182 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
2183 int rc;
2184
2185 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2186 return VINF_SUCCESS;
2187
2188 /*
2189 * Signal the semaphore to make sure we don't wait for 250 after a
2190 * suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
2191 */
2192 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2193
2194 /*
2195 * Allocate a bounce buffer for command we get from the FIFO.
2196 * (All code must return via the end of the function to free this buffer.)
2197 */
2198 uint8_t *pbBounceBuf = (uint8_t *)RTMemAllocZ(VMSVGA_FIFO_SIZE);
2199 AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
2200
2201 LogFlow(("vmsvgaFIFOLoop: started loop\n"));
2202 uint32_t volatile * const pFIFO = pThis->svga.pFIFOR3;
2203 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2204 {
2205
2206 /*
2207 * Wait for at most 250 ms to start polling.
2208 */
2209 rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, 250);
2210 AssertBreak(RT_SUCCESS(rc) || rc == VERR_TIMEOUT || rc == VERR_INTERRUPTED);
2211 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2212 {
2213 LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
2214 break;
2215 }
2216 if (rc == VERR_TIMEOUT)
2217 {
2218 if (pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
2219 continue;
2220 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
2221
2222 Log(("vmsvgaFIFOLoop: timeout\n"));
2223 }
2224 else if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
2225 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
2226
2227 Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
2228 Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
2229 Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
2230
2231 /*
2232 * Handle external commands.
2233 */
2234 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
2235 {
2236 switch (pThis->svga.u8FIFOExtCommand)
2237 {
2238 case VMSVGA_FIFO_EXTCMD_RESET:
2239 Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2240# ifdef VBOX_WITH_VMSVGA3D
2241 if (pThis->svga.f3DEnabled)
2242 {
2243 /* The 3d subsystem must be reset from the fifo thread. */
2244 vmsvga3dReset(pThis);
2245 }
2246# endif
2247 break;
2248
2249 case VMSVGA_FIFO_EXTCMD_TERMINATE:
2250 Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2251# ifdef VBOX_WITH_VMSVGA3D
2252 if (pThis->svga.f3DEnabled)
2253 {
2254 /* The 3d subsystem must be shut down from the fifo thread. */
2255 vmsvga3dTerminate(pThis);
2256 }
2257# endif
2258 break;
2259
2260 case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2261 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2262# ifdef VBOX_WITH_VMSVGA3D
2263 vmsvga3dSaveExec(pThis, (PSSMHANDLE)pThis->svga.pFIFOExtCmdParam);
2264# endif
2265 break;
2266
2267 case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2268 {
2269 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2270# ifdef VBOX_WITH_VMSVGA3D
2271 PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pFIFOExtCmdParam;
2272 vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2273# endif
2274 break;
2275 }
2276 }
2277
2278 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2279
2280 /* Signal the end of the external command. */
2281 RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2282 continue;
2283 }
2284
2285 if ( !pThis->svga.fEnabled
2286 || !pThis->svga.fConfigured)
2287 {
2288 vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
2289 continue; /* device not enabled. */
2290 }
2291
2292 /*
2293 * Get and check the min/max values. We ASSUME that they will remain
2294 * unchanged while we process requests. A further ASSUMPTION is that
2295 * the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
2296 * we don't read it back while in the loop.
2297 */
2298 uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
2299 uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
2300 uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
2301 if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
2302 || offFifoMax <= offFifoMin
2303 || offFifoMax > VMSVGA_FIFO_SIZE
2304 || (offFifoMax & 3) != 0
2305 || (offFifoMin & 3) != 0
2306 || offCurrentCmd < offFifoMin
2307 || offCurrentCmd > offFifoMax))
2308 {
2309 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2310 LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
2311 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
2312 continue;
2313 }
2314 if (RT_UNLIKELY(offCurrentCmd & 3))
2315 {
2316 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2317 LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
2318 offCurrentCmd = ~UINT32_C(3);
2319 }
2320
2321/**
2322 * Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
2323 *
2324 * Will break out of the switch on failure.
2325 * Will restart and quit the loop if the thread was requested to stop.
2326 *
2327 * @param a_cbPayloadReq How much payload to fetch.
2328 * @remarks Access a bunch of variables in the current scope!
2329 */
2330# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
2331 if (1) { \
2332 (a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
2333 pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
2334 if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
2335 } else do {} while (0)
2336/**
2337 * Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
2338 * buffer after figuring out the actual command size.
2339 * Will break out of the switch on failure.
2340 * @param a_cbPayloadReq How much payload to fetch.
2341 * @remarks Access a bunch of variables in the current scope!
2342 */
2343# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
2344 if (1) { \
2345 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
2346 } else do {} while (0)
2347
2348 /*
2349 * Mark the FIFO as busy.
2350 */
2351 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
2352 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2353 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
2354
2355 /*
2356 * Execute all queued FIFO commands.
2357 * Quit if pending external command or changes in the thread state.
2358 */
2359 bool fDone = false;
2360 while ( !(fDone = pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd)
2361 && pThread->enmState == PDMTHREADSTATE_RUNNING)
2362 {
2363 uint32_t cbPayload = 0;
2364 uint32_t u32IrqStatus = 0;
2365 bool fTriggerIrq = false;
2366
2367 Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
2368
2369 /* First check any pending actions. */
2370 if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
2371# ifdef VBOX_WITH_VMSVGA3D
2372 vmsvga3dChangeMode(pThis);
2373# else
2374 {/*nothing*/}
2375# endif
2376 /* Check for pending external commands. */
2377 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
2378 break;
2379
2380 /*
2381 * Process the command.
2382 */
2383 SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
2384 LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
2385 offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
2386 switch (enmCmdId)
2387 {
2388 case SVGA_CMD_INVALID_CMD:
2389 /* Nothing to do. */
2390 break;
2391
2392 case SVGA_CMD_FENCE:
2393 {
2394 SVGAFifoCmdFence *pCmdFence;
2395 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
2396 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
2397 {
2398 Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
2399 pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
2400
2401 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
2402 {
2403 Log(("vmsvgaFIFOLoop: any fence irq\n"));
2404 u32IrqStatus |= SVGA_IRQFLAG_ANY_FENCE;
2405 }
2406 else
2407 if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
2408 && (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
2409 && pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
2410 {
2411 Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
2412 u32IrqStatus |= SVGA_IRQFLAG_FENCE_GOAL;
2413 }
2414 }
2415 else
2416 Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
2417 break;
2418 }
2419 case SVGA_CMD_UPDATE:
2420 case SVGA_CMD_UPDATE_VERBOSE:
2421 {
2422 SVGAFifoCmdUpdate *pUpdate;
2423 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
2424 Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
2425 vgaR3UpdateDisplay(pThis, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
2426 break;
2427 }
2428
2429 case SVGA_CMD_DEFINE_CURSOR:
2430 {
2431 /* Followed by bitmap data. */
2432 SVGAFifoCmdDefineCursor *pCursor;
2433 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
2434 AssertFailed(); /** @todo implement when necessary. */
2435 break;
2436 }
2437
2438 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
2439 {
2440 /* Followed by bitmap data. */
2441 uint32_t cbCursorShape, cbAndMask;
2442 uint8_t *pCursorCopy;
2443 uint32_t cbCmd;
2444
2445 SVGAFifoCmdDefineAlphaCursor *pCursor;
2446 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
2447
2448 Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
2449
2450 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
2451 AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
2452
2453 /* Refetch the bitmap data as well. */
2454 cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
2455 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
2456 /** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
2457
2458 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
2459 cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
2460 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
2461 cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
2462
2463 pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
2464 AssertBreak(pCursorCopy);
2465
2466 Log2(("Cursor data:\n%.*Rhxd\n", pCursor->width * pCursor->height * sizeof(uint32_t), pCursor+1));
2467
2468 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
2469 memset(pCursorCopy, 0xff, cbAndMask);
2470 /* Colour data */
2471 memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
2472
2473 rc = pThis->pDrv->pfnVBVAMousePointerShape (pThis->pDrv,
2474 true,
2475 true,
2476 pCursor->hotspotX,
2477 pCursor->hotspotY,
2478 pCursor->width,
2479 pCursor->height,
2480 pCursorCopy);
2481 AssertRC(rc);
2482
2483 if (pSVGAState->Cursor.fActive)
2484 RTMemFree(pSVGAState->Cursor.pData);
2485
2486 pSVGAState->Cursor.fActive = true;
2487 pSVGAState->Cursor.xHotspot = pCursor->hotspotX;
2488 pSVGAState->Cursor.yHotspot = pCursor->hotspotY;
2489 pSVGAState->Cursor.width = pCursor->width;
2490 pSVGAState->Cursor.height = pCursor->height;
2491 pSVGAState->Cursor.cbData = cbCursorShape;
2492 pSVGAState->Cursor.pData = pCursorCopy;
2493 break;
2494 }
2495
2496 case SVGA_CMD_ESCAPE:
2497 {
2498 /* Followed by nsize bytes of data. */
2499 SVGAFifoCmdEscape *pEscape;
2500 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
2501
2502 /* Refetch the command buffer with the variable data; undo size increase (ugly) */
2503 AssertBreak(pEscape->size < VMSVGA_FIFO_SIZE);
2504 uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
2505 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
2506
2507 if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
2508 {
2509 AssertBreak(pEscape->size >= sizeof(uint32_t));
2510 uint32_t cmd = *(uint32_t *)(pEscape + 1);
2511 Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
2512
2513 switch (cmd)
2514 {
2515 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
2516 {
2517 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pEscape + 1);
2518 AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
2519 uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
2520
2521 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
2522 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
2523 {
2524 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
2525 }
2526 break;
2527 }
2528
2529 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
2530 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pEscape + 1);
2531 AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
2532 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
2533 break;
2534 }
2535 }
2536 else
2537 Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
2538
2539 break;
2540 }
2541# ifdef VBOX_WITH_VMSVGA3D
2542 case SVGA_CMD_DEFINE_GMR2:
2543 {
2544 SVGAFifoCmdDefineGMR2 *pCmd;
2545 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
2546 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
2547
2548 /* Validate current GMR id. */
2549 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2550 AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
2551
2552 if (!pCmd->numPages)
2553 {
2554 vmsvgaGMRFree(pThis, pCmd->gmrId);
2555 }
2556 else
2557 {
2558 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2559 pGMR->cMaxPages = pCmd->numPages;
2560 }
2561 /* everything done in remap */
2562 break;
2563 }
2564
2565 case SVGA_CMD_REMAP_GMR2:
2566 {
2567 /* Followed by page descriptors or guest ptr. */
2568 SVGAFifoCmdRemapGMR2 *pCmd;
2569 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
2570 uint32_t cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
2571 uint32_t cbCmd;
2572 uint64_t *paNewPage64 = NULL;
2573
2574 Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
2575 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2576
2577 /* Calculate the size of what comes after next and fetch it. */
2578 cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
2579 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
2580 cbCmd += sizeof(SVGAGuestPtr);
2581 else
2582 if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
2583 {
2584 cbCmd += cbPageDesc;
2585 pCmd->numPages = 1;
2586 }
2587 else
2588 {
2589 AssertBreak(pCmd->numPages <= VMSVGA_FIFO_SIZE);
2590 cbCmd += cbPageDesc * pCmd->numPages;
2591 }
2592 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
2593
2594 /* Validate current GMR id. */
2595 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2596 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2597 AssertBreak(pCmd->offsetPages + pCmd->numPages <= pGMR->cMaxPages);
2598 AssertBreak(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
2599
2600 /* Save the old page descriptors as an array of page addresses (>> PAGE_SHIFT) */
2601 if (pGMR->paDesc)
2602 {
2603 uint32_t idxPage = 0;
2604 paNewPage64 = (uint64_t *)RTMemAllocZ(pGMR->cMaxPages * sizeof(uint64_t));
2605 AssertBreak(paNewPage64);
2606
2607 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2608 {
2609 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
2610 {
2611 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * PAGE_SIZE) >> PAGE_SHIFT;
2612 }
2613 }
2614 AssertBreak(idxPage == pGMR->cbTotal >> PAGE_SHIFT);
2615 }
2616
2617 /* Free the old GMR if present. */
2618 if (pGMR->paDesc)
2619 RTMemFree(pGMR->paDesc);
2620
2621 /* Allocate the maximum amount possible (everything non-continuous) */
2622 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->cMaxPages * sizeof(VMSVGAGMRDESCRIPTOR));
2623 AssertBreak(pGMR->paDesc);
2624
2625 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
2626 {
2627 /** @todo */
2628 AssertFailed();
2629 }
2630 else
2631 {
2632 uint32_t *pPage32 = (uint32_t *)(pCmd + 1);
2633 uint64_t *pPage64 = (uint64_t *)(pCmd + 1);
2634 uint32_t iDescriptor = 0;
2635 RTGCPHYS GCPhys;
2636 PVMSVGAGMRDESCRIPTOR paDescOld = NULL;
2637 bool fGCPhys64 = !!(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
2638
2639 if (paNewPage64)
2640 {
2641 /* Overwrite the old page array with the new page values. */
2642 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
2643 {
2644 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
2645 paNewPage64[i] = pPage64[i - pCmd->offsetPages];
2646 else
2647 paNewPage64[i] = pPage32[i - pCmd->offsetPages];
2648 }
2649 /* Use the updated page array instead of the command data. */
2650 fGCPhys64 = true;
2651 pPage64 = paNewPage64;
2652 pCmd->numPages = pGMR->cbTotal >> PAGE_SHIFT;
2653 }
2654
2655 if (fGCPhys64)
2656 GCPhys = (pPage64[0] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
2657 else
2658 GCPhys = pPage32[0] << PAGE_SHIFT;
2659
2660 pGMR->paDesc[0].GCPhys = GCPhys;
2661 pGMR->paDesc[0].numPages = 1;
2662 pGMR->cbTotal = PAGE_SIZE;
2663
2664 for (uint32_t i = 1; i < pCmd->numPages; i++)
2665 {
2666 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
2667 GCPhys = (pPage64[i] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
2668 else
2669 GCPhys = pPage32[i] << PAGE_SHIFT;
2670
2671 /* Continuous physical memory? */
2672 if (GCPhys == pGMR->paDesc[iDescriptor].GCPhys + pGMR->paDesc[iDescriptor].numPages * PAGE_SIZE)
2673 {
2674 Assert(pGMR->paDesc[iDescriptor].numPages);
2675 pGMR->paDesc[iDescriptor].numPages++;
2676 LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
2677 }
2678 else
2679 {
2680 iDescriptor++;
2681 pGMR->paDesc[iDescriptor].GCPhys = GCPhys;
2682 pGMR->paDesc[iDescriptor].numPages = 1;
2683 LogFlow(("Page %x GCPhys=%RGp\n", i, pGMR->paDesc[iDescriptor].GCPhys));
2684 }
2685
2686 pGMR->cbTotal += PAGE_SIZE;
2687 }
2688 LogFlow(("Nr of descriptors %x\n", iDescriptor + 1));
2689 pGMR->numDescriptors = iDescriptor + 1;
2690 }
2691
2692 if (paNewPage64)
2693 RTMemFree(paNewPage64);
2694
2695# ifdef DEBUG_GMR_ACCESS
2696 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
2697# endif
2698 break;
2699 }
2700# endif // VBOX_WITH_VMSVGA3D
2701 case SVGA_CMD_DEFINE_SCREEN:
2702 {
2703 /* Note! The size of this command is specified by the guest and depends on capabilities. */
2704 Assert(!(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT));
2705 SVGAFifoCmdDefineScreen *pCmd;
2706 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
2707 RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.structSize));
2708 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
2709
2710 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d)\n", pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y));
2711 if (pCmd->screen.flags & SVGA_SCREEN_HAS_ROOT)
2712 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_HAS_ROOT\n"));
2713 if (pCmd->screen.flags & SVGA_SCREEN_IS_PRIMARY)
2714 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_IS_PRIMARY\n"));
2715 if (pCmd->screen.flags & SVGA_SCREEN_FULLSCREEN_HINT)
2716 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_FULLSCREEN_HINT\n"));
2717 if (pCmd->screen.flags & SVGA_SCREEN_DEACTIVATE )
2718 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_DEACTIVATE \n"));
2719 if (pCmd->screen.flags & SVGA_SCREEN_BLANKING)
2720 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_BLANKING\n"));
2721
2722 /** @todo multi monitor support and screen object capabilities. */
2723 pThis->svga.uWidth = pCmd->screen.size.width;
2724 pThis->svga.uHeight = pCmd->screen.size.height;
2725 vmsvgaChangeMode(pThis);
2726 break;
2727 }
2728
2729 case SVGA_CMD_DESTROY_SCREEN:
2730 {
2731 SVGAFifoCmdDestroyScreen *pCmd;
2732 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
2733
2734 Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
2735 break;
2736 }
2737# ifdef VBOX_WITH_VMSVGA3D
2738 case SVGA_CMD_DEFINE_GMRFB:
2739 {
2740 SVGAFifoCmdDefineGMRFB *pCmd;
2741 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
2742
2743 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
2744 pSVGAState->GMRFB.ptr = pCmd->ptr;
2745 pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
2746 pSVGAState->GMRFB.format = pCmd->format;
2747 break;
2748 }
2749
2750 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
2751 {
2752 uint32_t width, height;
2753 SVGAFifoCmdBlitGMRFBToScreen *pCmd;
2754 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
2755
2756 Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
2757
2758 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
2759 AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pThis->svga.uBpp);
2760 AssertBreak(pCmd->destScreenId == 0);
2761
2762 if (pCmd->destRect.left < 0)
2763 pCmd->destRect.left = 0;
2764 if (pCmd->destRect.top < 0)
2765 pCmd->destRect.top = 0;
2766 if (pCmd->destRect.right < 0)
2767 pCmd->destRect.right = 0;
2768 if (pCmd->destRect.bottom < 0)
2769 pCmd->destRect.bottom = 0;
2770
2771 width = pCmd->destRect.right - pCmd->destRect.left;
2772 height = pCmd->destRect.bottom - pCmd->destRect.top;
2773
2774 if ( width == 0
2775 || height == 0)
2776 break; /* Nothing to do. */
2777
2778 /* Clip to screen dimensions. */
2779 if (width > pThis->svga.uWidth)
2780 width = pThis->svga.uWidth;
2781 if (height > pThis->svga.uHeight)
2782 height = pThis->svga.uHeight;
2783
2784 unsigned offsetSource = (pCmd->srcOrigin.x * pSVGAState->GMRFB.format.s.bitsPerPixel) / 8 + pSVGAState->GMRFB.bytesPerLine * pCmd->srcOrigin.y;
2785 unsigned offsetDest = (pCmd->destRect.left * RT_ALIGN(pThis->svga.uBpp, 8)) / 8 + pThis->svga.cbScanline * pCmd->destRect.top;
2786 unsigned cbCopyWidth = (width * RT_ALIGN(pThis->svga.uBpp, 8)) / 8;
2787
2788 AssertBreak(offsetDest < pThis->vram_size);
2789
2790 rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM, pThis->CTX_SUFF(vram_ptr) + offsetDest, pThis->svga.cbScanline, pSVGAState->GMRFB.ptr, offsetSource, pSVGAState->GMRFB.bytesPerLine, cbCopyWidth, height);
2791 AssertRC(rc);
2792 vgaR3UpdateDisplay(pThis, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right - pCmd->destRect.left, pCmd->destRect.bottom - pCmd->destRect.top);
2793 break;
2794 }
2795
2796 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
2797 {
2798 SVGAFifoCmdBlitScreenToGMRFB *pCmd;
2799 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
2800
2801 /* Note! This can fetch 3d render results as well!! */
2802 Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n", pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
2803 AssertFailed();
2804 break;
2805 }
2806# endif // VBOX_WITH_VMSVGA3D
2807 case SVGA_CMD_ANNOTATION_FILL:
2808 {
2809 SVGAFifoCmdAnnotationFill *pCmd;
2810 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
2811
2812 Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
2813 pSVGAState->colorAnnotation = pCmd->color;
2814 break;
2815 }
2816
2817 case SVGA_CMD_ANNOTATION_COPY:
2818 {
2819 SVGAFifoCmdAnnotationCopy *pCmd;
2820 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
2821
2822 Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
2823 AssertFailed();
2824 break;
2825 }
2826
2827 /** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
2828
2829 default:
2830# ifdef VBOX_WITH_VMSVGA3D
2831 if ( enmCmdId >= SVGA_3D_CMD_BASE
2832 && enmCmdId < SVGA_3D_CMD_MAX)
2833 {
2834 /* All 3d commands start with a common header, which defines the size of the command. */
2835 SVGA3dCmdHeader *pHdr;
2836 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
2837 AssertBreak(pHdr->size < VMSVGA_FIFO_SIZE);
2838 uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
2839 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
2840
2841/**
2842 * Check that the 3D command has at least a_cbMin of payload bytes after the
2843 * header. Will break out of the switch if it doesn't.
2844 */
2845# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
2846 AssertMsgBreak((a_cbMin) <= pHdr->size, ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin)))
2847 switch ((int)enmCmdId)
2848 {
2849 case SVGA_3D_CMD_SURFACE_DEFINE:
2850 {
2851 uint32_t cMipLevels;
2852 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)(pHdr + 1);
2853 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2854
2855 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
2856 rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0, SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
2857# ifdef DEBUG_GMR_ACCESS
2858 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
2859# endif
2860 break;
2861 }
2862
2863 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
2864 {
2865 uint32_t cMipLevels;
2866 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)(pHdr + 1);
2867 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2868
2869 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
2870 rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face, pCmd->multisampleCount, pCmd->autogenFilter, cMipLevels, (SVGA3dSize *)(pCmd + 1));
2871 break;
2872 }
2873
2874 case SVGA_3D_CMD_SURFACE_DESTROY:
2875 {
2876 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)(pHdr + 1);
2877 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2878 rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
2879 break;
2880 }
2881
2882 case SVGA_3D_CMD_SURFACE_COPY:
2883 {
2884 uint32_t cCopyBoxes;
2885 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)(pHdr + 1);
2886 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2887
2888 cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
2889 rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
2890 break;
2891 }
2892
2893 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
2894 {
2895 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)(pHdr + 1);
2896 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2897
2898 rc = vmsvga3dSurfaceStretchBlt(pThis, pCmd->dest, pCmd->boxDest, pCmd->src, pCmd->boxSrc, pCmd->mode);
2899 break;
2900 }
2901
2902 case SVGA_3D_CMD_SURFACE_DMA:
2903 {
2904 uint32_t cCopyBoxes;
2905 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)(pHdr + 1);
2906 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2907
2908 cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
2909 STAM_PROFILE_START(&pSVGAState->StatR3CmdSurfaceDMA, a);
2910 rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
2911 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdSurfaceDMA, a);
2912 break;
2913 }
2914
2915 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
2916 {
2917 uint32_t cRects;
2918 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)(pHdr + 1);
2919 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2920
2921 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
2922 rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
2923 break;
2924 }
2925
2926 case SVGA_3D_CMD_CONTEXT_DEFINE:
2927 {
2928 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)(pHdr + 1);
2929 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2930
2931 rc = vmsvga3dContextDefine(pThis, pCmd->cid);
2932 break;
2933 }
2934
2935 case SVGA_3D_CMD_CONTEXT_DESTROY:
2936 {
2937 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)(pHdr + 1);
2938 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2939
2940 rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
2941 break;
2942 }
2943
2944 case SVGA_3D_CMD_SETTRANSFORM:
2945 {
2946 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)(pHdr + 1);
2947 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2948
2949 rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
2950 break;
2951 }
2952
2953 case SVGA_3D_CMD_SETZRANGE:
2954 {
2955 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)(pHdr + 1);
2956 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2957
2958 rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
2959 break;
2960 }
2961
2962 case SVGA_3D_CMD_SETRENDERSTATE:
2963 {
2964 uint32_t cRenderStates;
2965 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)(pHdr + 1);
2966 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2967
2968 cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
2969 rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
2970 break;
2971 }
2972
2973 case SVGA_3D_CMD_SETRENDERTARGET:
2974 {
2975 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)(pHdr + 1);
2976 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2977
2978 rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
2979 break;
2980 }
2981
2982 case SVGA_3D_CMD_SETTEXTURESTATE:
2983 {
2984 uint32_t cTextureStates;
2985 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)(pHdr + 1);
2986 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2987
2988 cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
2989 rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
2990 break;
2991 }
2992
2993 case SVGA_3D_CMD_SETMATERIAL:
2994 {
2995 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)(pHdr + 1);
2996 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
2997
2998 rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
2999 break;
3000 }
3001
3002 case SVGA_3D_CMD_SETLIGHTDATA:
3003 {
3004 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)(pHdr + 1);
3005 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3006
3007 rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
3008 break;
3009 }
3010
3011 case SVGA_3D_CMD_SETLIGHTENABLED:
3012 {
3013 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)(pHdr + 1);
3014 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3015
3016 rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
3017 break;
3018 }
3019
3020 case SVGA_3D_CMD_SETVIEWPORT:
3021 {
3022 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)(pHdr + 1);
3023 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3024
3025 rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
3026 break;
3027 }
3028
3029 case SVGA_3D_CMD_SETCLIPPLANE:
3030 {
3031 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)(pHdr + 1);
3032 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3033
3034 rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
3035 break;
3036 }
3037
3038 case SVGA_3D_CMD_CLEAR:
3039 {
3040 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)(pHdr + 1);
3041 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3042 uint32_t cRects;
3043
3044 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
3045 rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
3046 break;
3047 }
3048
3049 case SVGA_3D_CMD_PRESENT:
3050 {
3051 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)(pHdr + 1);
3052 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3053 uint32_t cRects;
3054
3055 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
3056
3057 STAM_PROFILE_START(&pSVGAState->StatR3CmdPresent, a);
3058 rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
3059 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdPresent, a);
3060 break;
3061 }
3062
3063 case SVGA_3D_CMD_SHADER_DEFINE:
3064 {
3065 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)(pHdr + 1);
3066 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3067 uint32_t cbData;
3068
3069 cbData = (pHdr->size - sizeof(*pCmd));
3070 rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
3071 break;
3072 }
3073
3074 case SVGA_3D_CMD_SHADER_DESTROY:
3075 {
3076 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)(pHdr + 1);
3077 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3078
3079 rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
3080 break;
3081 }
3082
3083 case SVGA_3D_CMD_SET_SHADER:
3084 {
3085 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)(pHdr + 1);
3086 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3087
3088 rc = vmsvga3dShaderSet(pThis, pCmd->cid, pCmd->type, pCmd->shid);
3089 break;
3090 }
3091
3092 case SVGA_3D_CMD_SET_SHADER_CONST:
3093 {
3094 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)(pHdr + 1);
3095 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3096
3097 uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
3098 rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
3099 break;
3100 }
3101
3102 case SVGA_3D_CMD_DRAW_PRIMITIVES:
3103 {
3104 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)(pHdr + 1);
3105 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3106 uint32_t cVertexDivisor;
3107
3108 cVertexDivisor = (pHdr->size - sizeof(*pCmd) - sizeof(SVGA3dVertexDecl) * pCmd->numVertexDecls - sizeof(SVGA3dPrimitiveRange) * pCmd->numRanges);
3109 Assert(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
3110 Assert(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
3111 Assert(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls);
3112
3113 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
3114 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *) (&pVertexDecl[pCmd->numVertexDecls]);
3115 SVGA3dVertexDivisor *pVertexDivisor = (cVertexDivisor) ? (SVGA3dVertexDivisor *)(&pNumRange[pCmd->numRanges]) : NULL;
3116
3117 STAM_PROFILE_START(&pSVGAState->StatR3CmdDrawPrimitive, a);
3118 rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges, pNumRange, cVertexDivisor, pVertexDivisor);
3119 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdDrawPrimitive, a);
3120 break;
3121 }
3122
3123 case SVGA_3D_CMD_SETSCISSORRECT:
3124 {
3125 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)(pHdr + 1);
3126 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3127
3128 rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
3129 break;
3130 }
3131
3132 case SVGA_3D_CMD_BEGIN_QUERY:
3133 {
3134 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)(pHdr + 1);
3135 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3136
3137 rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
3138 break;
3139 }
3140
3141 case SVGA_3D_CMD_END_QUERY:
3142 {
3143 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)(pHdr + 1);
3144 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3145
3146 rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
3147 break;
3148 }
3149
3150 case SVGA_3D_CMD_WAIT_FOR_QUERY:
3151 {
3152 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)(pHdr + 1);
3153 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3154
3155 rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
3156 break;
3157 }
3158
3159 case SVGA_3D_CMD_GENERATE_MIPMAPS:
3160 {
3161 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)(pHdr + 1);
3162 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3163
3164 rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
3165 break;
3166 }
3167
3168 case SVGA_3D_CMD_ACTIVATE_SURFACE:
3169 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
3170 /* context id + surface id? */
3171 break;
3172
3173 default:
3174 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3175 AssertFailed();
3176 break;
3177 }
3178 }
3179 else
3180# endif // VBOX_WITH_VMSVGA3D
3181 {
3182 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3183 AssertFailed();
3184 }
3185 }
3186
3187 /* Go to the next slot */
3188 Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
3189 offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
3190 if (offCurrentCmd >= offFifoMax)
3191 {
3192 offCurrentCmd -= offFifoMax - offFifoMin;
3193 Assert(offCurrentCmd >= offFifoMin);
3194 Assert(offCurrentCmd < offFifoMax);
3195 }
3196 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
3197 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
3198
3199 /*
3200 * Raise IRQ if required. Must enter the critical section here
3201 * before making final decisions here, otherwise cubebench and
3202 * others may end up waiting forever.
3203 */
3204 if ( u32IrqStatus
3205 || (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
3206 {
3207 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
3208
3209 /* FIFO progress might trigger an interrupt. */
3210 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
3211 {
3212 Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
3213 u32IrqStatus |= SVGA_IRQFLAG_FIFO_PROGRESS;
3214 }
3215
3216 /* Unmasked IRQ pending? */
3217 if (pThis->svga.u32IrqMask & u32IrqStatus)
3218 {
3219 Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
3220 ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
3221 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
3222 }
3223
3224 PDMCritSectLeave(&pThis->CritSect);
3225 }
3226 }
3227
3228 /* If really done, clear the busy flag. */
3229 if (fDone)
3230 {
3231 Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
3232 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3233 }
3234 }
3235
3236 /*
3237 * Free the bounce buffer. (There are no returns above!)
3238 */
3239 RTMemFree(pbBounceBuf);
3240
3241 return VINF_SUCCESS;
3242}
3243
3244/**
3245 * Free the specified GMR
3246 *
3247 * @param pThis VGA device instance data.
3248 * @param idGMR GMR id
3249 */
3250void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
3251{
3252 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3253
3254 /* Free the old descriptor if present. */
3255 if (pSVGAState->aGMR[idGMR].numDescriptors)
3256 {
3257 PGMR pGMR = &pSVGAState->aGMR[idGMR];
3258# ifdef DEBUG_GMR_ACCESS
3259 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
3260# endif
3261
3262 Assert(pGMR->paDesc);
3263 RTMemFree(pGMR->paDesc);
3264 pGMR->paDesc = NULL;
3265 pGMR->numDescriptors = 0;
3266 pGMR->cbTotal = 0;
3267 pGMR->cMaxPages = 0;
3268 }
3269 Assert(!pSVGAState->aGMR[idGMR].cbTotal);
3270}
3271
3272/**
3273 * Copy from a GMR to host memory or vice versa
3274 *
3275 * @returns VBox status code.
3276 * @param pThis VGA device instance data.
3277 * @param enmTransferType Transfer type (read/write)
3278 * @param pbDst Host destination pointer
3279 * @param cbDestPitch Destination buffer pitch
3280 * @param src GMR description
3281 * @param offSrc Source buffer offset
3282 * @param cbSrcPitch Source buffer pitch
3283 * @param cbWidth Source width in bytes
3284 * @param cHeight Source height
3285 */
3286int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType, uint8_t *pbDst, int32_t cbDestPitch,
3287 SVGAGuestPtr src, uint32_t offSrc, int32_t cbSrcPitch, uint32_t cbWidth, uint32_t cHeight)
3288{
3289 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3290 PGMR pGMR;
3291 int rc;
3292 PVMSVGAGMRDESCRIPTOR pDesc;
3293 unsigned offDesc = 0;
3294
3295 Log(("vmsvgaGMRTransfer: gmr=%x offset=%x pitch=%d cbWidth=%d cHeight=%d; src offset=%d src pitch=%d\n",
3296 src.gmrId, src.offset, cbDestPitch, cbWidth, cHeight, offSrc, cbSrcPitch));
3297 Assert(cbWidth && cHeight);
3298
3299 /* Shortcut for the framebuffer. */
3300 if (src.gmrId == SVGA_GMR_FRAMEBUFFER)
3301 {
3302 offSrc += src.offset;
3303 AssertMsgReturn(src.offset < pThis->vram_size,
3304 ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x vram_size=%#x\n",
3305 src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
3306 VERR_INVALID_PARAMETER);
3307 AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pThis->vram_size,
3308 ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x vram_size=%#x\n",
3309 src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
3310 VERR_INVALID_PARAMETER);
3311
3312 uint8_t *pSrc = pThis->CTX_SUFF(vram_ptr) + offSrc;
3313
3314 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
3315 {
3316 /* switch src & dest */
3317 uint8_t *pTemp = pbDst;
3318 int32_t cbTempPitch = cbDestPitch;
3319
3320 pbDst = pSrc;
3321 pSrc = pTemp;
3322
3323 cbDestPitch = cbSrcPitch;
3324 cbSrcPitch = cbTempPitch;
3325 }
3326
3327 if ( pThis->svga.cbScanline == (uint32_t)cbDestPitch
3328 && cbWidth == (uint32_t)cbDestPitch
3329 && cbSrcPitch == cbDestPitch)
3330 {
3331 memcpy(pbDst, pSrc, cbWidth * cHeight);
3332 }
3333 else
3334 {
3335 for(uint32_t i = 0; i < cHeight; i++)
3336 {
3337 memcpy(pbDst, pSrc, cbWidth);
3338
3339 pbDst += cbDestPitch;
3340 pSrc += cbSrcPitch;
3341 }
3342 }
3343 return VINF_SUCCESS;
3344 }
3345
3346 AssertReturn(src.gmrId < VMSVGA_MAX_GMR_IDS, VERR_INVALID_PARAMETER);
3347 pGMR = &pSVGAState->aGMR[src.gmrId];
3348 pDesc = pGMR->paDesc;
3349
3350 offSrc += src.offset;
3351 AssertMsgReturn(src.offset < pGMR->cbTotal,
3352 ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
3353 src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
3354 VERR_INVALID_PARAMETER);
3355 AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pGMR->cbTotal,
3356 ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
3357 src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
3358 VERR_INVALID_PARAMETER);
3359
3360 for (uint32_t i = 0; i < cHeight; i++)
3361 {
3362 uint32_t cbCurrentWidth = cbWidth;
3363 uint32_t offCurrent = offSrc;
3364 uint8_t *pCurrentDest = pbDst;
3365
3366 /* Find the right descriptor */
3367 while (offDesc + pDesc->numPages * PAGE_SIZE <= offCurrent)
3368 {
3369 offDesc += pDesc->numPages * PAGE_SIZE;
3370 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
3371 pDesc++;
3372 }
3373
3374 while (cbCurrentWidth)
3375 {
3376 uint32_t cbToCopy;
3377
3378 if (offCurrent + cbCurrentWidth <= offDesc + pDesc->numPages * PAGE_SIZE)
3379 {
3380 cbToCopy = cbCurrentWidth;
3381 }
3382 else
3383 {
3384 cbToCopy = (offDesc + pDesc->numPages * PAGE_SIZE - offCurrent);
3385 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
3386 }
3387
3388 LogFlow(("vmsvgaGMRTransfer: %s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", pDesc->GCPhys + offCurrent - offDesc));
3389
3390 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
3391 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
3392 else
3393 rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
3394 AssertRCBreak(rc);
3395
3396 cbCurrentWidth -= cbToCopy;
3397 offCurrent += cbToCopy;
3398 pCurrentDest += cbToCopy;
3399
3400 /* Go to the next descriptor if there's anything left. */
3401 if (cbCurrentWidth)
3402 {
3403 offDesc += pDesc->numPages * PAGE_SIZE;
3404 pDesc++;
3405 }
3406 }
3407
3408 offSrc += cbSrcPitch;
3409 pbDst += cbDestPitch;
3410 }
3411
3412 return VINF_SUCCESS;
3413}
3414
3415/**
3416 * Unblock the FIFO I/O thread so it can respond to a state change.
3417 *
3418 * @returns VBox status code.
3419 * @param pDevIns The VGA device instance.
3420 * @param pThread The send thread.
3421 */
3422static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3423{
3424 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3425 Log(("vmsvgaFIFOLoopWakeUp\n"));
3426 return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3427}
3428
3429/**
3430 * Enables or disables dirty page tracking for the framebuffer
3431 *
3432 * @param pThis VGA device instance data.
3433 * @param fTraces Enable/disable traces
3434 */
3435static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
3436{
3437 if ( (!pThis->svga.fConfigured || !pThis->svga.fEnabled)
3438 && !fTraces)
3439 {
3440 //Assert(pThis->svga.fTraces);
3441 Log(("vmsvgaSetTraces: *not* allowed to disable dirty page tracking when the device is in legacy mode.\n"));
3442 return;
3443 }
3444
3445 pThis->svga.fTraces = fTraces;
3446 if (pThis->svga.fTraces)
3447 {
3448 unsigned cbFrameBuffer = pThis->vram_size;
3449
3450 Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
3451 if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
3452 {
3453 Assert(pThis->svga.cbScanline);
3454 /* Hardware enabled; return real framebuffer size .*/
3455 cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
3456 cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
3457 }
3458
3459 if (!pThis->svga.fVRAMTracking)
3460 {
3461 Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
3462 vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
3463 pThis->svga.fVRAMTracking = true;
3464 }
3465 }
3466 else
3467 {
3468 if (pThis->svga.fVRAMTracking)
3469 {
3470 Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
3471 vgaR3UnregisterVRAMHandler(pThis);
3472 pThis->svga.fVRAMTracking = false;
3473 }
3474 }
3475}
3476
3477/**
3478 * Callback function for mapping a PCI I/O region.
3479 *
3480 * @return VBox status code.
3481 * @param pPciDev Pointer to PCI device.
3482 * Use pPciDev->pDevIns to get the device instance.
3483 * @param iRegion The region number.
3484 * @param GCPhysAddress Physical address of the region.
3485 * If iType is PCI_ADDRESS_SPACE_IO, this is an
3486 * I/O port, else it's a physical address.
3487 * This address is *NOT* relative
3488 * to pci_mem_base like earlier!
3489 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
3490 */
3491DECLCALLBACK(int) vmsvgaR3IORegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
3492{
3493 int rc;
3494 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3495 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3496
3497 Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%#x enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
3498 if (enmType == PCI_ADDRESS_SPACE_IO)
3499 {
3500 AssertReturn(iRegion == 0, VERR_INTERNAL_ERROR);
3501 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3502 vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr */, NULL /* InStr */, "VMSVGA");
3503 if (RT_FAILURE(rc))
3504 return rc;
3505 if (pThis->fR0Enabled)
3506 {
3507 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3508 "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
3509 if (RT_FAILURE(rc))
3510 return rc;
3511 }
3512 if (pThis->fGCEnabled)
3513 {
3514 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3515 "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
3516 if (RT_FAILURE(rc))
3517 return rc;
3518 }
3519
3520 pThis->svga.BasePort = GCPhysAddress;
3521 Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
3522 }
3523 else
3524 {
3525 AssertReturn(iRegion == 2 && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
3526 if (GCPhysAddress != NIL_RTGCPHYS)
3527 {
3528 /*
3529 * Mapping the FIFO RAM.
3530 */
3531 rc = PDMDevHlpMMIO2Map(pDevIns, iRegion, GCPhysAddress);
3532 AssertRC(rc);
3533
3534# ifdef DEBUG_FIFO_ACCESS
3535 if (RT_SUCCESS(rc))
3536 {
3537 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress, GCPhysAddress + (VMSVGA_FIFO_SIZE - 1),
3538 pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
3539 "VMSVGA FIFO");
3540 AssertRC(rc);
3541 }
3542# endif
3543 if (RT_SUCCESS(rc))
3544 {
3545 pThis->svga.GCPhysFIFO = GCPhysAddress;
3546 Log(("vmsvgaR3IORegionMap: FIFO address = %RGp\n", GCPhysAddress));
3547 }
3548 }
3549 else
3550 {
3551 Assert(pThis->svga.GCPhysFIFO);
3552# ifdef DEBUG_FIFO_ACCESS
3553 rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3554 AssertRC(rc);
3555# endif
3556 pThis->svga.GCPhysFIFO = 0;
3557 }
3558
3559 }
3560 return VINF_SUCCESS;
3561}
3562
3563
3564/**
3565 * @copydoc FNSSMDEVLOADEXEC
3566 */
3567int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3568{
3569 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3570 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3571 int rc;
3572
3573 /* Load our part of the VGAState */
3574 rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
3575 AssertRCReturn(rc, rc);
3576
3577 /* Load the framebuffer backup. */
3578 rc = SSMR3GetMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
3579 AssertRCReturn(rc, rc);
3580
3581 /* Load the VMSVGA state. */
3582 rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGASTATEFields, NULL);
3583 AssertRCReturn(rc, rc);
3584
3585 /* Load the active cursor bitmaps. */
3586 if (pSVGAState->Cursor.fActive)
3587 {
3588 pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
3589 AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
3590
3591 rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
3592 AssertRCReturn(rc, rc);
3593 }
3594
3595 /* Load the GMR state */
3596 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
3597 {
3598 PGMR pGMR = &pSVGAState->aGMR[i];
3599
3600 rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
3601 AssertRCReturn(rc, rc);
3602
3603 if (pGMR->numDescriptors)
3604 {
3605 /* Allocate the maximum amount possible (everything non-continuous) */
3606 Assert(pGMR->cMaxPages || pGMR->cbTotal);
3607 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ((pGMR->cMaxPages) ? pGMR->cMaxPages : (pGMR->cbTotal >> PAGE_SHIFT) * sizeof(VMSVGAGMRDESCRIPTOR));
3608 AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
3609
3610 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
3611 {
3612 rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
3613 AssertRCReturn(rc, rc);
3614 }
3615 }
3616 }
3617
3618# ifdef VBOX_WITH_VMSVGA3D
3619 if (pThis->svga.f3DEnabled)
3620 {
3621 VMSVGA_STATE_LOAD loadstate;
3622
3623 loadstate.pSSM = pSSM;
3624 loadstate.uVersion = uVersion;
3625 loadstate.uPass = uPass;
3626
3627 /* Save the 3d state in the FIFO thread. */
3628 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_LOADSTATE;
3629 pThis->svga.pFIFOExtCmdParam = (void *)&loadstate;
3630 /* Hack alert: resume the IO thread as it has been suspended before the destruct callback.
3631 * The PowerOff notification isn't working, so not an option in this case.
3632 */
3633 PDMR3ThreadResume(pThis->svga.pFIFOIOThread);
3634 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3635 /* Wait for the end of the command. */
3636 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, RT_INDEFINITE_WAIT);
3637 AssertRC(rc);
3638 PDMR3ThreadSuspend(pThis->svga.pFIFOIOThread);
3639 }
3640# endif
3641
3642 return VINF_SUCCESS;
3643}
3644
3645/**
3646 * Reinit the video mode after the state has been loaded.
3647 */
3648int vmsvgaLoadDone(PPDMDEVINS pDevIns)
3649{
3650 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3651 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3652
3653 pThis->last_bpp = VMSVGA_VAL_UNINITIALIZED; /* force mode reset */
3654 vmsvgaChangeMode(pThis);
3655
3656 /* Set the active cursor. */
3657 if (pSVGAState->Cursor.fActive)
3658 {
3659 int rc;
3660
3661 rc = pThis->pDrv->pfnVBVAMousePointerShape (pThis->pDrv,
3662 true,
3663 true,
3664 pSVGAState->Cursor.xHotspot,
3665 pSVGAState->Cursor.yHotspot,
3666 pSVGAState->Cursor.width,
3667 pSVGAState->Cursor.height,
3668 pSVGAState->Cursor.pData);
3669 AssertRC(rc);
3670 }
3671 return VINF_SUCCESS;
3672}
3673
3674/**
3675 * @copydoc FNSSMDEVSAVEEXEC
3676 */
3677int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3678{
3679 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3680 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3681 int rc;
3682
3683 /* Save our part of the VGAState */
3684 rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
3685 AssertRCReturn(rc, rc);
3686
3687 /* Save the framebuffer backup. */
3688 rc = SSMR3PutMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
3689 AssertRCReturn(rc, rc);
3690
3691 /* Save the VMSVGA state. */
3692 rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGASTATEFields, NULL);
3693 AssertRCReturn(rc, rc);
3694
3695 /* Save the active cursor bitmaps. */
3696 if (pSVGAState->Cursor.fActive)
3697 {
3698 rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
3699 AssertRCReturn(rc, rc);
3700 }
3701
3702 /* Save the GMR state */
3703 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
3704 {
3705 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i], sizeof(pSVGAState->aGMR[i]), 0, g_aGMRFields, NULL);
3706 AssertRCReturn(rc, rc);
3707
3708 for (uint32_t j = 0; j < pSVGAState->aGMR[i].numDescriptors; j++)
3709 {
3710 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i].paDesc[j], sizeof(pSVGAState->aGMR[i].paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
3711 AssertRCReturn(rc, rc);
3712 }
3713 }
3714
3715# ifdef VBOX_WITH_VMSVGA3D
3716 if (pThis->svga.f3DEnabled)
3717 {
3718 /* Save the 3d state in the FIFO thread. */
3719 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_SAVESTATE;
3720 pThis->svga.pFIFOExtCmdParam = (void *)pSSM;
3721 /* Hack alert: resume the IO thread as it has been suspended before the destruct callback.
3722 * The PowerOff notification isn't working, so not an option in this case.
3723 */
3724 PDMR3ThreadResume(pThis->svga.pFIFOIOThread);
3725 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3726 /* Wait for the end of the external command. */
3727 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, RT_INDEFINITE_WAIT);
3728 AssertRC(rc);
3729 PDMR3ThreadSuspend(pThis->svga.pFIFOIOThread);
3730 }
3731# endif
3732 return VINF_SUCCESS;
3733}
3734
3735/**
3736 * Resets the SVGA hardware state
3737 *
3738 * @returns VBox status code.
3739 * @param pDevIns The device instance.
3740 */
3741int vmsvgaReset(PPDMDEVINS pDevIns)
3742{
3743 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3744 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3745
3746 /* Reset before init? */
3747 if (!pSVGAState)
3748 return VINF_SUCCESS;
3749
3750 Log(("vmsvgaReset\n"));
3751
3752 pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0;
3753
3754 /* Reset the FIFO thread. */
3755 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_RESET;
3756 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3757 /* Wait for the end of the termination sequence. */
3758 int rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, 10000);
3759 AssertRC(rc);
3760
3761 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
3762 memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
3763 memset(pThis->svga.pSVGAState, 0, sizeof(VMSVGASTATE));
3764 memset(pThis->svga.pFrameBufferBackup, 0, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
3765
3766 /* Register caps. */
3767 pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
3768# ifdef VBOX_WITH_VMSVGA3D
3769 pThis->svga.u32RegCaps |= SVGA_CAP_3D;
3770# endif
3771
3772 /* Setup FIFO capabilities. */
3773 pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
3774
3775 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
3776 pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
3777
3778 /* VRAM tracking is enabled by default during bootup. */
3779 pThis->svga.fVRAMTracking = true;
3780 pThis->svga.fEnabled = false;
3781
3782 /* Invalidate current settings. */
3783 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
3784 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
3785 pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
3786 pThis->svga.cbScanline = 0;
3787
3788 return rc;
3789}
3790
3791/**
3792 * Cleans up the SVGA hardware state
3793 *
3794 * @returns VBox status code.
3795 * @param pDevIns The device instance.
3796 */
3797int vmsvgaDestruct(PPDMDEVINS pDevIns)
3798{
3799 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3800 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3801 int rc;
3802
3803 /* Stop the FIFO thread. */
3804 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_TERMINATE;
3805 /* Hack alert: resume the IO thread as it has been suspended before the destruct callback.
3806 * The PowerOff notification isn't working, so not an option in this case.
3807 */
3808 PDMR3ThreadResume(pThis->svga.pFIFOIOThread);
3809 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3810
3811 /* Wait for the end of the termination sequence. */
3812 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, 10000);
3813 AssertRC(rc);
3814 PDMR3ThreadSuspend(pThis->svga.pFIFOIOThread);
3815
3816 if (pSVGAState)
3817 {
3818# ifndef VMSVGA_USE_EMT_HALT_CODE
3819 if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
3820 {
3821 RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
3822 pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
3823 }
3824# endif
3825 if (pSVGAState->Cursor.fActive)
3826 RTMemFree(pSVGAState->Cursor.pData);
3827
3828 for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
3829 {
3830 if (pSVGAState->aGMR[i].paDesc)
3831 RTMemFree(pSVGAState->aGMR[i].paDesc);
3832 }
3833 RTMemFree(pSVGAState);
3834 }
3835 if (pThis->svga.pFrameBufferBackup)
3836 RTMemFree(pThis->svga.pFrameBufferBackup);
3837 if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
3838 {
3839 RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
3840 pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
3841 }
3842 if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
3843 {
3844 SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3845 pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
3846 }
3847
3848 return VINF_SUCCESS;
3849}
3850
3851/**
3852 * Initialize the SVGA hardware state
3853 *
3854 * @returns VBox status code.
3855 * @param pDevIns The device instance.
3856 */
3857int vmsvgaInit(PPDMDEVINS pDevIns)
3858{
3859 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3860 PVMSVGASTATE pSVGAState;
3861 PVM pVM = PDMDevHlpGetVM(pDevIns);
3862 int rc;
3863
3864 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
3865 memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
3866
3867 pThis->svga.pSVGAState = RTMemAllocZ(sizeof(VMSVGASTATE));
3868 AssertReturn(pThis->svga.pSVGAState, VERR_NO_MEMORY);
3869 pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3870
3871 /* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
3872 pThis->svga.pFrameBufferBackup = RTMemAllocZ(VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
3873 AssertReturn(pThis->svga.pFrameBufferBackup, VERR_NO_MEMORY);
3874
3875 /* Create event semaphore. */
3876 pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
3877
3878 rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
3879 if (RT_FAILURE(rc))
3880 {
3881 Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
3882 return rc;
3883 }
3884
3885 /* Create event semaphore. */
3886 rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
3887 if (RT_FAILURE(rc))
3888 {
3889 Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
3890 return rc;
3891 }
3892
3893# ifndef VMSVGA_USE_EMT_HALT_CODE
3894 /* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
3895 rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
3896 AssertRCReturn(rc, rc);
3897# endif
3898
3899 /* Register caps. */
3900 pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
3901# ifdef VBOX_WITH_VMSVGA3D
3902 pThis->svga.u32RegCaps |= SVGA_CAP_3D;
3903# endif
3904
3905 /* Setup FIFO capabilities. */
3906 pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
3907
3908 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
3909 pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
3910
3911 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
3912# ifdef VBOX_WITH_VMSVGA3D
3913 if (pThis->svga.f3DEnabled)
3914 {
3915 rc = vmsvga3dInit(pThis);
3916 if (RT_FAILURE(rc))
3917 {
3918 LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
3919 pThis->svga.f3DEnabled = false;
3920 }
3921 }
3922# endif
3923 /* VRAM tracking is enabled by default during bootup. */
3924 pThis->svga.fVRAMTracking = true;
3925
3926 /* Invalidate current settings. */
3927 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
3928 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
3929 pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
3930 pThis->svga.cbScanline = 0;
3931
3932 pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
3933 pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
3934 while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
3935 {
3936 pThis->svga.u32MaxWidth -= 256;
3937 pThis->svga.u32MaxHeight -= 256;
3938 }
3939 Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
3940
3941# ifdef DEBUG_GMR_ACCESS
3942 /* Register the GMR access handler type. */
3943 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
3944 vmsvgaR3GMRAccessHandler, NULL, NULL, NULL, NULL, "VMSVGA GMR",
3945 &pThis->svga.hGmrAccessHandlerType);
3946 AssertRCReturn(rc, rc);
3947# endif
3948# ifdef DEBUG_FIFO_ACCESS
3949 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_ALL,
3950 vmsvgaR3FIFOAccessHandler, NULL, NULL, NULL, NULL, "VMSVGA FIFO",
3951 &pThis->svga.hFifoAccessHandlerType);
3952 AssertRCReturn(rc, rc);
3953#endif
3954
3955 /* Create the async IO thread. */
3956 rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
3957 RTTHREADTYPE_IO, "VMSVGA FIFO");
3958 if (RT_FAILURE(rc))
3959 {
3960 AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
3961 return rc;
3962 }
3963
3964 /*
3965 * Statistics.
3966 */
3967 STAM_REG(pVM, &pSVGAState->StatR3CmdPresent, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/Present", STAMUNIT_TICKS_PER_CALL, "Profiling of Present.");
3968 STAM_REG(pVM, &pSVGAState->StatR3CmdDrawPrimitive, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/DrawPrimitive", STAMUNIT_TICKS_PER_CALL, "Profiling of DrawPrimitive.");
3969 STAM_REG(pVM, &pSVGAState->StatR3CmdSurfaceDMA, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/SurfaceDMA", STAMUNIT_TICKS_PER_CALL, "Profiling of SurfaceDMA.");
3970 STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
3971 STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
3972 STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
3973 STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
3974 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
3975 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
3976 STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
3977
3978 return VINF_SUCCESS;
3979}
3980
3981# ifdef VBOX_WITH_VMSVGA3D
3982/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
3983static const char * const g_apszVmSvgaDevCapNames[] =
3984{
3985 "x3D", /* = 0 */
3986 "xMAX_LIGHTS",
3987 "xMAX_TEXTURES",
3988 "xMAX_CLIP_PLANES",
3989 "xVERTEX_SHADER_VERSION",
3990 "xVERTEX_SHADER",
3991 "xFRAGMENT_SHADER_VERSION",
3992 "xFRAGMENT_SHADER",
3993 "xMAX_RENDER_TARGETS",
3994 "xS23E8_TEXTURES",
3995 "xS10E5_TEXTURES",
3996 "xMAX_FIXED_VERTEXBLEND",
3997 "xD16_BUFFER_FORMAT",
3998 "xD24S8_BUFFER_FORMAT",
3999 "xD24X8_BUFFER_FORMAT",
4000 "xQUERY_TYPES",
4001 "xTEXTURE_GRADIENT_SAMPLING",
4002 "rMAX_POINT_SIZE",
4003 "xMAX_SHADER_TEXTURES",
4004 "xMAX_TEXTURE_WIDTH",
4005 "xMAX_TEXTURE_HEIGHT",
4006 "xMAX_VOLUME_EXTENT",
4007 "xMAX_TEXTURE_REPEAT",
4008 "xMAX_TEXTURE_ASPECT_RATIO",
4009 "xMAX_TEXTURE_ANISOTROPY",
4010 "xMAX_PRIMITIVE_COUNT",
4011 "xMAX_VERTEX_INDEX",
4012 "xMAX_VERTEX_SHADER_INSTRUCTIONS",
4013 "xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
4014 "xMAX_VERTEX_SHADER_TEMPS",
4015 "xMAX_FRAGMENT_SHADER_TEMPS",
4016 "xTEXTURE_OPS",
4017 "xSURFACEFMT_X8R8G8B8",
4018 "xSURFACEFMT_A8R8G8B8",
4019 "xSURFACEFMT_A2R10G10B10",
4020 "xSURFACEFMT_X1R5G5B5",
4021 "xSURFACEFMT_A1R5G5B5",
4022 "xSURFACEFMT_A4R4G4B4",
4023 "xSURFACEFMT_R5G6B5",
4024 "xSURFACEFMT_LUMINANCE16",
4025 "xSURFACEFMT_LUMINANCE8_ALPHA8",
4026 "xSURFACEFMT_ALPHA8",
4027 "xSURFACEFMT_LUMINANCE8",
4028 "xSURFACEFMT_Z_D16",
4029 "xSURFACEFMT_Z_D24S8",
4030 "xSURFACEFMT_Z_D24X8",
4031 "xSURFACEFMT_DXT1",
4032 "xSURFACEFMT_DXT2",
4033 "xSURFACEFMT_DXT3",
4034 "xSURFACEFMT_DXT4",
4035 "xSURFACEFMT_DXT5",
4036 "xSURFACEFMT_BUMPX8L8V8U8",
4037 "xSURFACEFMT_A2W10V10U10",
4038 "xSURFACEFMT_BUMPU8V8",
4039 "xSURFACEFMT_Q8W8V8U8",
4040 "xSURFACEFMT_CxV8U8",
4041 "xSURFACEFMT_R_S10E5",
4042 "xSURFACEFMT_R_S23E8",
4043 "xSURFACEFMT_RG_S10E5",
4044 "xSURFACEFMT_RG_S23E8",
4045 "xSURFACEFMT_ARGB_S10E5",
4046 "xSURFACEFMT_ARGB_S23E8",
4047 "xMISSING62",
4048 "xMAX_VERTEX_SHADER_TEXTURES",
4049 "xMAX_SIMULTANEOUS_RENDER_TARGETS",
4050 "xSURFACEFMT_V16U16",
4051 "xSURFACEFMT_G16R16",
4052 "xSURFACEFMT_A16B16G16R16",
4053 "xSURFACEFMT_UYVY",
4054 "xSURFACEFMT_YUY2",
4055 "xMULTISAMPLE_NONMASKABLESAMPLES",
4056 "xMULTISAMPLE_MASKABLESAMPLES",
4057 "xALPHATOCOVERAGE",
4058 "xSUPERSAMPLE",
4059 "xAUTOGENMIPMAPS",
4060 "xSURFACEFMT_NV12",
4061 "xSURFACEFMT_AYUV",
4062 "xMAX_CONTEXT_IDS",
4063 "xMAX_SURFACE_IDS",
4064 "xSURFACEFMT_Z_DF16",
4065 "xSURFACEFMT_Z_DF24",
4066 "xSURFACEFMT_Z_D24S8_INT",
4067 "xSURFACEFMT_BC4_UNORM",
4068 "xSURFACEFMT_BC5_UNORM", /* 83 */
4069};
4070# endif
4071
4072
4073/**
4074 * Power On notification.
4075 *
4076 * @returns VBox status.
4077 * @param pDevIns The device instance data.
4078 *
4079 * @remarks Caller enters the device critical section.
4080 */
4081DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
4082{
4083 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4084 int rc;
4085
4086# ifdef VBOX_WITH_VMSVGA3D
4087 if (pThis->svga.f3DEnabled)
4088 {
4089 rc = vmsvga3dPowerOn(pThis);
4090
4091 if (RT_SUCCESS(rc))
4092 {
4093 bool fSavedBuffering = RTLogRelSetBuffering(true);
4094 SVGA3dCapsRecord *pCaps;
4095 SVGA3dCapPair *pData;
4096 uint32_t idxCap = 0;
4097
4098 /* 3d hardware version; latest and greatest */
4099 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
4100 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
4101
4102 pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
4103 pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
4104 pData = (SVGA3dCapPair *)&pCaps->data;
4105
4106 /* Fill out all 3d capabilities. */
4107 for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
4108 {
4109 uint32_t val = 0;
4110
4111 rc = vmsvga3dQueryCaps(pThis, i, &val);
4112 if (RT_SUCCESS(rc))
4113 {
4114 pData[idxCap][0] = i;
4115 pData[idxCap][1] = val;
4116 idxCap++;
4117 if (g_apszVmSvgaDevCapNames[i][0] == 'x')
4118 LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
4119 else
4120 LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)*(float *)&val, (unsigned)(*(float *)&val * 10000) % 10000,
4121 &g_apszVmSvgaDevCapNames[i][1]));
4122 }
4123 else
4124 LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
4125 }
4126 pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
4127 pCaps = (SVGA3dCapsRecord *)((uint32_t *)pCaps + pCaps->header.length);
4128
4129 /* Mark end of record array. */
4130 pCaps->header.length = 0;
4131
4132 RTLogRelSetBuffering(fSavedBuffering);
4133 }
4134 }
4135# endif // VBOX_WITH_VMSVGA3D
4136}
4137
4138#endif /* IN_RING3 */
4139
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