DevVGA-SVGA.cpp@ 89153

Last change on this file since 89153 was 89124, checked in by vboxsync, 4 years ago
Devices/Graphics: Fixed regression from r144462 on darwin when loading state w/o 3D enabled. bugref:9830
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1	/* $Id: DevVGA-SVGA.cpp 89124 2021-05-17 23:18:45Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - Log6 for DX shaders.
13	* - Log7 for SVGA command dump.
14	* - LogRel for the usual important stuff.
15	* - LogRel2 for cursor.
16	* - LogRel3 for 3D performance data.
17	* - LogRel4 for HW accelerated graphics output.
18	*/
19
20	/*
21	* Copyright (C) 2013-2020 Oracle Corporation
22	*
23	* This file is part of VirtualBox Open Source Edition (OSE), as
24	* available from http://www.virtualbox.org. This file is free software;
25	* you can redistribute it and/or modify it under the terms of the GNU
26	* General Public License (GPL) as published by the Free Software
27	* Foundation, in version 2 as it comes in the "COPYING" file of the
28	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
29	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
30	*/
31
32
33	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
34	*
35	* This device emulation was contributed by trivirt AG. It offers an
36	* alternative to our Bochs based VGA graphics and 3d emulations. This is
37	* valuable for Xorg based guests, as there is driver support shipping with Xorg
38	* since it forked from XFree86.
39	*
40	*
41	* @section sec_dev_vmsvga_sdk The VMware SDK
42	*
43	* This is officially deprecated now, however it's still quite useful,
44	* especially for getting the old features working:
45	* http://vmware-svga.sourceforge.net/
46	*
47	* They currently point developers at the following resources.
48	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
49	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
50	* - http://cgit.freedesktop.org/mesa/vmwgfx/
51	*
52	* @subsection subsec_dev_vmsvga_sdk_results Test results
53	*
54	* Test results:
55	* - 2dmark.img:
56	* + todo
57	* - backdoor-tclo.img:
58	* + todo
59	* - blit-cube.img:
60	* + todo
61	* - bunnies.img:
62	* + todo
63	* - cube.img:
64	* + todo
65	* - cubemark.img:
66	* + todo
67	* - dynamic-vertex-stress.img:
68	* + todo
69	* - dynamic-vertex.img:
70	* + todo
71	* - fence-stress.img:
72	* + todo
73	* - gmr-test.img:
74	* + todo
75	* - half-float-test.img:
76	* + todo
77	* - noscreen-cursor.img:
78	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
79	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
80	* visible though.)
81	* - Cursor animation via the palette doesn't work.
82	* - During debugging, it turns out that the framebuffer content seems to
83	* be halfways ignore or something (memset(fb, 0xcc, lots)).
84	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
85	* grow it 0x10 fold (128KB -> 2MB like in WS10).
86	* - null.img:
87	* + todo
88	* - pong.img:
89	* + todo
90	* - presentReadback.img:
91	* + todo
92	* - resolution-set.img:
93	* + todo
94	* - rt-gamma-test.img:
95	* + todo
96	* - screen-annotation.img:
97	* + todo
98	* - screen-cursor.img:
99	* + todo
100	* - screen-dma-coalesce.img:
101	* + todo
102	* - screen-gmr-discontig.img:
103	* + todo
104	* - screen-gmr-remap.img:
105	* + todo
106	* - screen-multimon.img:
107	* + todo
108	* - screen-present-clip.img:
109	* + todo
110	* - screen-render-test.img:
111	* + todo
112	* - screen-simple.img:
113	* + todo
114	* - screen-text.img:
115	* + todo
116	* - simple-shaders.img:
117	* + todo
118	* - simple_blit.img:
119	* + todo
120	* - tiny-2d-updates.img:
121	* + todo
122	* - video-formats.img:
123	* + todo
124	* - video-sync.img:
125	* + todo
126	*
127	*/
128
129
130	/*********************************************************************************************************************************
131	* Header Files *
132	*********************************************************************************************************************************/
133	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
134	#include <VBox/vmm/pdmdev.h>
135	#include <VBox/version.h>
136	#include <VBox/err.h>
137	#include <VBox/log.h>
138	#include <VBox/vmm/pgm.h>
139	#include <VBox/sup.h>
140
141	#include <iprt/assert.h>
142	#include <iprt/semaphore.h>
143	#include <iprt/uuid.h>
144	#ifdef IN_RING3
145	# include <iprt/ctype.h>
146	# include <iprt/mem.h>
147	# ifdef VBOX_STRICT
148	# include <iprt/time.h>
149	# endif
150	#endif
151
152	#include <VBox/AssertGuest.h>
153	#include <VBox/VMMDev.h>
154	#include <VBoxVideo.h>
155	#include <VBox/bioslogo.h>
156
157	#ifdef LOG_ENABLED
158	#include "svgadump/svga_dump.h"
159	#endif
160
161	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
162	#include "DevVGA.h"
163
164	/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
165	#ifdef VBOX_WITH_VMSVGA3D
166	# include "DevVGA-SVGA3d.h"
167	# ifdef RT_OS_DARWIN
168	# include "DevVGA-SVGA3d-cocoa.h"
169	# endif
170	# ifdef RT_OS_LINUX
171	# ifdef IN_RING3
172	# include "DevVGA-SVGA3d-glLdr.h"
173	# endif
174	# endif
175	#endif
176	#ifdef IN_RING3
177	#include "DevVGA-SVGA-internal.h"
178	#endif
179
180
181	/*********************************************************************************************************************************
182	* Defined Constants And Macros *
183	*********************************************************************************************************************************/
184	/**
185	* Macro for checking if a fixed FIFO register is valid according to the
186	* current FIFO configuration.
187	*
188	* @returns true / false.
189	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
190	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
191	*/
192	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
193
194
195	/*********************************************************************************************************************************
196	* Structures and Typedefs *
197	*********************************************************************************************************************************/
198
199
200	/*********************************************************************************************************************************
201	* Internal Functions *
202	*********************************************************************************************************************************/
203	#ifdef IN_RING3
204	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
205	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
206	# endif
207	# ifdef DEBUG_GMR_ACCESS
208	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
209	# endif
210	#endif
211
212
213	/*********************************************************************************************************************************
214	* Global Variables *
215	*********************************************************************************************************************************/
216	#ifdef IN_RING3
217
218	/**
219	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
220	*/
221	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
222	{
223	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
224	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
225	SSMFIELD_ENTRY_TERM()
226	};
227
228	/**
229	* SSM descriptor table for the GMR structure.
230	*/
231	static SSMFIELD const g_aGMRFields[] =
232	{
233	SSMFIELD_ENTRY( GMR, cMaxPages),
234	SSMFIELD_ENTRY( GMR, cbTotal),
235	SSMFIELD_ENTRY( GMR, numDescriptors),
236	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
237	SSMFIELD_ENTRY_TERM()
238	};
239
240	/**
241	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
242	*/
243	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
244	{
245	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
246	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
247	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
248	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
249	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
250	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
251	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
252	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
253	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
254	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
255	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
256	SSMFIELD_ENTRY_VER( VMSVGASCREENOBJECT, cDpi, VGA_SAVEDSTATE_VERSION_VMSVGA_MIPLEVELS),
257	SSMFIELD_ENTRY_TERM()
258	};
259
260	/**
261	* SSM descriptor table for the VMSVGAR3STATE structure.
262	*/
263	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
264	{
265	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
266	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
267	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
268	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
269	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
270	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
271	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
272	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
273	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
274	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
275	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
276	#ifdef VMSVGA_USE_EMT_HALT_CODE
277	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
278	#else
279	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
280	#endif
281	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
282	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
283	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
284	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
285	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
286	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
287	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
288	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
289	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
290	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
291	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
292	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
293	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
294	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
295	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
296	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
297	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
298	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
299	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
300	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
301	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
302	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
303	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
304	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
305	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
306	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
307	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
308	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
309	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
310	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
311	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
312	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
313	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
314	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
315	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
316	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
317	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
318	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
319	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
320	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
321	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
322	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
323	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
324	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
325	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
326	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
327	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
328	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
329	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
330	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
331	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
332	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
333	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
334	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
335	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
336	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
337	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
338	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
339	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
340	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
341	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
342	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
343	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
344
345	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
346	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
347	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
348	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
349
350	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
351	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
352	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
353	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
354	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
355	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
356	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
357	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
358	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
359	# endif
360	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
361	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
362	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
363	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
364
365	SSMFIELD_ENTRY_TERM()
366	};
367
368	/**
369	* SSM descriptor table for the VGAState.svga structure.
370	*/
371	static SSMFIELD const g_aVGAStateSVGAFields[] =
372	{
373	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
374	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
375	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
376	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
377	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
378	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
379	SSMFIELD_ENTRY( VMSVGAState, fBusy),
380	SSMFIELD_ENTRY( VMSVGAState, fTraces),
381	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
382	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
383	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
384	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
385	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
386	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
387	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
388	SSMFIELD_ENTRY( VMSVGAState, u32DeviceCaps),
389	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
390	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
391	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
392	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
393	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
394	SSMFIELD_ENTRY( VMSVGAState, uWidth),
395	SSMFIELD_ENTRY( VMSVGAState, uHeight),
396	SSMFIELD_ENTRY( VMSVGAState, uBpp),
397	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
398	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
399	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
400	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
401	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
402	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
403	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
404	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
405	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
406	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
407	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
408	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
409	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
410	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
411	SSMFIELD_ENTRY_TERM()
412	};
413	#endif /* IN_RING3 */
414
415
416	/*********************************************************************************************************************************
417	* Internal Functions *
418	*********************************************************************************************************************************/
419	#ifdef IN_RING3
420	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
421	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
422	uint32_t uVersion, uint32_t uPass);
423	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
424	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx);
425	# ifdef VBOX_WITH_VMSVGA3D
426	static void vmsvga3dR3Free3dInterfaces(PVGASTATECC pThisCC);
427	# endif
428	#endif /* IN_RING3 */
429
430
431	#define SVGA_CASE_ID2STR(idx) case idx: return #idx
432	#if defined(LOG_ENABLED)
433	/**
434	* Index register string name lookup
435	*
436	* @returns Index register string or "UNKNOWN"
437	* @param pThis The shared VGA/VMSVGA state.
438	* @param idxReg The index register.
439	*/
440	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
441	{
442	AssertCompile(SVGA_REG_TOP == 77); /* Ensure that the correct headers are used. */
443	switch (idxReg)
444	{
445	SVGA_CASE_ID2STR(SVGA_REG_ID);
446	SVGA_CASE_ID2STR(SVGA_REG_ENABLE);
447	SVGA_CASE_ID2STR(SVGA_REG_WIDTH);
448	SVGA_CASE_ID2STR(SVGA_REG_HEIGHT);
449	SVGA_CASE_ID2STR(SVGA_REG_MAX_WIDTH);
450	SVGA_CASE_ID2STR(SVGA_REG_MAX_HEIGHT);
451	SVGA_CASE_ID2STR(SVGA_REG_DEPTH);
452	SVGA_CASE_ID2STR(SVGA_REG_BITS_PER_PIXEL); /* Current bpp in the guest */
453	SVGA_CASE_ID2STR(SVGA_REG_PSEUDOCOLOR);
454	SVGA_CASE_ID2STR(SVGA_REG_RED_MASK);
455	SVGA_CASE_ID2STR(SVGA_REG_GREEN_MASK);
456	SVGA_CASE_ID2STR(SVGA_REG_BLUE_MASK);
457	SVGA_CASE_ID2STR(SVGA_REG_BYTES_PER_LINE);
458	SVGA_CASE_ID2STR(SVGA_REG_FB_START); /* (Deprecated) */
459	SVGA_CASE_ID2STR(SVGA_REG_FB_OFFSET);
460	SVGA_CASE_ID2STR(SVGA_REG_VRAM_SIZE);
461	SVGA_CASE_ID2STR(SVGA_REG_FB_SIZE);
462
463	/* ID 0 implementation only had the above registers, then the palette */
464	SVGA_CASE_ID2STR(SVGA_REG_CAPABILITIES);
465	SVGA_CASE_ID2STR(SVGA_REG_MEM_START); /* (Deprecated) */
466	SVGA_CASE_ID2STR(SVGA_REG_MEM_SIZE);
467	SVGA_CASE_ID2STR(SVGA_REG_CONFIG_DONE); /* Set when memory area configured */
468	SVGA_CASE_ID2STR(SVGA_REG_SYNC); /* See "FIFO Synchronization Registers" */
469	SVGA_CASE_ID2STR(SVGA_REG_BUSY); /* See "FIFO Synchronization Registers" */
470	SVGA_CASE_ID2STR(SVGA_REG_GUEST_ID); /* Set guest OS identifier */
471	SVGA_CASE_ID2STR(SVGA_REG_DEAD); /* (Deprecated) SVGA_REG_CURSOR_ID. */
472	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_X); /* (Deprecated) */
473	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_Y); /* (Deprecated) */
474	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ON); /* (Deprecated) */
475	SVGA_CASE_ID2STR(SVGA_REG_HOST_BITS_PER_PIXEL); /* (Deprecated) */
476	SVGA_CASE_ID2STR(SVGA_REG_SCRATCH_SIZE); /* Number of scratch registers */
477	SVGA_CASE_ID2STR(SVGA_REG_MEM_REGS); /* Number of FIFO registers */
478	SVGA_CASE_ID2STR(SVGA_REG_NUM_DISPLAYS); /* (Deprecated) */
479	SVGA_CASE_ID2STR(SVGA_REG_PITCHLOCK); /* Fixed pitch for all modes */
480	SVGA_CASE_ID2STR(SVGA_REG_IRQMASK); /* Interrupt mask */
481
482	/* Legacy multi-monitor support */
483	SVGA_CASE_ID2STR(SVGA_REG_NUM_GUEST_DISPLAYS); /* Number of guest displays in X/Y direction */
484	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_ID); /* Display ID for the following display attributes */
485	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_IS_PRIMARY); /* Whether this is a primary display */
486	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_X); /* The display position x */
487	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_Y); /* The display position y */
488	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_WIDTH); /* The display's width */
489	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_HEIGHT); /* The display's height */
490
491	SVGA_CASE_ID2STR(SVGA_REG_GMR_ID);
492	SVGA_CASE_ID2STR(SVGA_REG_GMR_DESCRIPTOR);
493	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_IDS);
494	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
495
496	SVGA_CASE_ID2STR(SVGA_REG_TRACES); /* Enable trace-based updates even when FIFO is on */
497	SVGA_CASE_ID2STR(SVGA_REG_GMRS_MAX_PAGES); /* Maximum number of 4KB pages for all GMRs */
498	SVGA_CASE_ID2STR(SVGA_REG_MEMORY_SIZE); /* Total dedicated device memory excluding FIFO */
499	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_LOW); /* Lower 32 bits and submits commands */
500	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_HIGH); /* Upper 32 bits of command buffer PA */
501	SVGA_CASE_ID2STR(SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); /* Max primary memory */
502	SVGA_CASE_ID2STR(SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); /* Suggested limit on mob mem */
503	SVGA_CASE_ID2STR(SVGA_REG_DEV_CAP); /* Write dev cap index, read value */
504	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_LOW);
505	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_HIGH);
506	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_WIDTH);
507	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_HEIGHT);
508	SVGA_CASE_ID2STR(SVGA_REG_MOB_MAX_SIZE);
509	SVGA_CASE_ID2STR(SVGA_REG_BLANK_SCREEN_TARGETS);
510	SVGA_CASE_ID2STR(SVGA_REG_CAP2);
511	SVGA_CASE_ID2STR(SVGA_REG_DEVEL_CAP);
512	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_ID);
513	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION1);
514	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION2);
515	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION3);
516	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MOBID);
517	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_BYTE_SIZE);
518	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_DIMENSION);
519	SVGA_CASE_ID2STR(SVGA_REG_FIFO_CAPS);
520	SVGA_CASE_ID2STR(SVGA_REG_FENCE);
521	SVGA_CASE_ID2STR(SVGA_REG_RESERVED1);
522	SVGA_CASE_ID2STR(SVGA_REG_RESERVED2);
523	SVGA_CASE_ID2STR(SVGA_REG_RESERVED3);
524	SVGA_CASE_ID2STR(SVGA_REG_RESERVED4);
525	SVGA_CASE_ID2STR(SVGA_REG_RESERVED5);
526	SVGA_CASE_ID2STR(SVGA_REG_SCREENDMA);
527	SVGA_CASE_ID2STR(SVGA_REG_GBOBJECT_MEM_SIZE_KB);
528	SVGA_CASE_ID2STR(SVGA_REG_TOP); /* Must be 1 more than the last register */
529
530	default:
531	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
532	return "SVGA_SCRATCH_BASE reg";
533	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
534	return "SVGA_PALETTE_BASE reg";
535	return "UNKNOWN";
536	}
537	}
538	#endif /* LOG_ENABLED */
539
540	#if defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D))
541	static const char *vmsvgaDevCapIndexToString(SVGA3dDevCapIndex idxDevCap)
542	{
543	AssertCompile(SVGA3D_DEVCAP_MAX == 260);
544	switch (idxDevCap)
545	{
546	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_INVALID);
547	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_3D);
548	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LIGHTS);
549	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURES);
550	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CLIP_PLANES);
551	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER_VERSION);
552	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER);
553	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION);
554	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER);
555	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_RENDER_TARGETS);
556	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S23E8_TEXTURES);
557	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S10E5_TEXTURES);
558	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND);
559	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D16_BUFFER_FORMAT);
560	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT);
561	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT);
562	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_QUERY_TYPES);
563	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING);
564	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_POINT_SIZE);
565	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SHADER_TEXTURES);
566	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
567	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
568	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VOLUME_EXTENT);
569	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT);
570	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO);
571	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY);
572	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT);
573	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_INDEX);
574	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS);
575	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS);
576	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS);
577	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS);
578	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_OPS);
579	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);
580	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8);
581	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10);
582	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5);
583	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5);
584	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4);
585	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R5G6B5);
586	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16);
587	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8);
588	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ALPHA8);
589	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8);
590	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D16);
591	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8);
592	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8);
593	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT1);
594	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT2);
595	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT3);
596	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT4);
597	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT5);
598	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8);
599	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10);
600	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8);
601	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8);
602	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_CxV8U8);
603	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S10E5);
604	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S23E8);
605	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5);
606	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8);
607	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5);
608	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8);
609	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MISSING62);
610	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES);
611	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS);
612	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_V16U16);
613	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_G16R16);
614	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16);
615	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_UYVY);
616	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YUY2);
617	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD4); /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
618	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD5); /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
619	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD7); /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
620	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD6); /* SVGA3D_DEVCAP_SUPERSAMPLE */
621	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_AUTOGENMIPMAPS);
622	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_NV12);
623	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD10); /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
624	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CONTEXT_IDS);
625	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SURFACE_IDS);
626	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF16);
627	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF24);
628	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT);
629	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI1);
630	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI2);
631	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD1);
632	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD8); /* SVGA3D_DEVCAP_VIDEO_DECODE */
633	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD9); /* SVGA3D_DEVCAP_VIDEO_PROCESS */
634	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_AA);
635	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_STIPPLE);
636	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LINE_WIDTH);
637	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH);
638	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YV12);
639	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD3); /* Old SVGA3D_DEVCAP_LOGICOPS */
640	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TS_COLOR_KEY);
641	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD2);
642	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXCONTEXT);
643	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD11); /* SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE */
644	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS);
645	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS);
646	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_PROVOKING_VERTEX);
647	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8R8G8B8);
648	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8R8G8B8);
649	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R5G6B5);
650	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X1R5G5B5);
651	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A1R5G5B5);
652	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A4R4G4B4);
653	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D32);
654	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D16);
655	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8);
656	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D15S1);
657	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8);
658	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4);
659	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE16);
660	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8);
661	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT1);
662	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT2);
663	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT3);
664	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT4);
665	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT5);
666	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPU8V8);
667	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5);
668	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8);
669	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1);
670	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5);
671	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8);
672	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2R10G10B10);
673	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V8U8);
674	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8);
675	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_CxV8U8);
676	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8L8V8U8);
677	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2W10V10U10);
678	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ALPHA8);
679	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S10E5);
680	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S23E8);
681	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S10E5);
682	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S23E8);
683	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUFFER);
684	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24X8);
685	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V16U16);
686	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G16R16);
687	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A16B16G16R16);
688	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_UYVY);
689	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YUY2);
690	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_NV12);
691	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2); /* SVGA3D_DEVCAP_DXFMT_AYUV */
692	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS);
693	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT);
694	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT);
695	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS);
696	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT);
697	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT);
698	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT);
699	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS);
700	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT);
701	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM);
702	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT);
703	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS);
704	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_UINT);
705	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_SINT);
706	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS);
707	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT);
708	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24);
709	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT);
710	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS);
711	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT);
712	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT);
713	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS);
714	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM);
715	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB);
716	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT);
717	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT);
718	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS);
719	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UINT);
720	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SINT);
721	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS);
722	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT);
723	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_UINT);
724	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_SINT);
725	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS);
726	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT);
727	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8);
728	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X24_G8_UINT);
729	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS);
730	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM);
731	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UINT);
732	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SINT);
733	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS);
734	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UNORM);
735	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UINT);
736	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SNORM);
737	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SINT);
738	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS);
739	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UNORM);
740	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UINT);
741	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SNORM);
742	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SINT);
743	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_P8);
744	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP);
745	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM);
746	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM);
747	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS);
748	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB);
749	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS);
750	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB);
751	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS);
752	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB);
753	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS);
754	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI1);
755	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_SNORM);
756	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS);
757	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI2);
758	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_SNORM);
759	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM);
760	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS);
761	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB);
762	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS);
763	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB);
764	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF16);
765	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF24);
766	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT);
767	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YV12);
768	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT);
769	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT);
770	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM);
771	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT);
772	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM);
773	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM);
774	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT);
775	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM);
776	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM);
777	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT);
778	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM);
779	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_FLOAT);
780	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D16_UNORM);
781	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8_UNORM);
782	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM);
783	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM);
784	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM);
785	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM);
786	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM);
787	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM);
788	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM);
789	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_UNORM);
790	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_UNORM);
791	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM41);
792	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_2X);
793	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_4X);
794	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MS_FULL_QUALITY);
795	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGICOPS);
796	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGIC_BLENDOPS);
797	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_1);
798	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS);
799	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_UF16);
800	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_SF16);
801	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS);
802	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM);
803	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB);
804	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_2);
805	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM5);
806	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_8X);
807
808	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX);
809
810	default:
811	break;
812	}
813	return "UNKNOWN";
814	}
815	#endif /* defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D)) */
816	#undef SVGA_CASE_ID2STR
817
818
819	#ifdef IN_RING3
820
821	/**
822	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
823	*/
824	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
825	{
826	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
827	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
828
829	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
830	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
831
832	/** @todo Test how it interacts with multiple screen objects. */
833	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
834	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
835	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
836
837	if (x < uWidth)
838	{
839	pThis->svga.viewport.x = x;
840	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
841	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
842	}
843	else
844	{
845	pThis->svga.viewport.x = uWidth;
846	pThis->svga.viewport.cx = 0;
847	pThis->svga.viewport.xRight = uWidth;
848	}
849	if (y < uHeight)
850	{
851	pThis->svga.viewport.y = y;
852	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
853	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
854	pThis->svga.viewport.yHighWC = uHeight - y;
855	}
856	else
857	{
858	pThis->svga.viewport.y = uHeight;
859	pThis->svga.viewport.cy = 0;
860	pThis->svga.viewport.yLowWC = 0;
861	pThis->svga.viewport.yHighWC = 0;
862	}
863
864	# ifdef VBOX_WITH_VMSVGA3D
865	/*
866	* Now inform the 3D backend.
867	*/
868	if (pThis->svga.f3DEnabled)
869	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
870	# else
871	RT_NOREF(OldViewport);
872	# endif
873	}
874
875
876	/**
877	* Updating screen information in API
878	*
879	* @param pThis The The shared VGA/VMSVGA instance data.
880	* @param pThisCC The VGA/VMSVGA state for ring-3.
881	*/
882	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
883	{
884	int rc;
885
886	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
887
888	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
889	{
890	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
891	if (!pScreen->fModified)
892	continue;
893
894	pScreen->fModified = false;
895
896	VBVAINFOVIEW view;
897	RT_ZERO(view);
898	view.u32ViewIndex = pScreen->idScreen;
899	// view.u32ViewOffset = 0;
900	view.u32ViewSize = pThis->vram_size;
901	view.u32MaxScreenSize = pThis->vram_size;
902
903	VBVAINFOSCREEN screen;
904	RT_ZERO(screen);
905	screen.u32ViewIndex = pScreen->idScreen;
906
907	if (pScreen->fDefined)
908	{
909	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
910	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
911	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
912	{
913	Assert(pThis->svga.fGFBRegisters);
914	continue;
915	}
916
917	screen.i32OriginX = pScreen->xOrigin;
918	screen.i32OriginY = pScreen->yOrigin;
919	screen.u32StartOffset = pScreen->offVRAM;
920	screen.u32LineSize = pScreen->cbPitch;
921	screen.u32Width = pScreen->cWidth;
922	screen.u32Height = pScreen->cHeight;
923	screen.u16BitsPerPixel = pScreen->cBpp;
924	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
925	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
926	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
927	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
928	}
929	else
930	{
931	/* Screen is destroyed. */
932	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
933	}
934
935	void *pvVRAM = pScreen->pvScreenBitmap ? pScreen->pvScreenBitmap : pThisCC->pbVRam;
936	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pvVRAM, /fResetInputMapping=/ true);
937	AssertRC(rc);
938	}
939	}
940
941
942	/**
943	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
944	*
945	* Used to update screen offsets (positions) since appearently vmwgfx fails to
946	* pass correct offsets thru FIFO.
947	*/
948	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
949	{
950	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
951	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
952	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
953
954	AssertReturnVoid(pSVGAState);
955
956	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
957	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
958	for (uint32_t i = 0; i < cPositions; ++i)
959	{
960	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
961	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
962	continue;
963
964	if (pSVGAState->aScreens[i].xOrigin == -1)
965	continue;
966	if (pSVGAState->aScreens[i].yOrigin == -1)
967	continue;
968
969	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
970	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
971	pSVGAState->aScreens[i].fModified = true;
972	}
973
974	vmsvgaR3VBVAResize(pThis, pThisCC);
975	}
976
977	#endif /* IN_RING3 */
978
979	/**
980	* Read port register
981	*
982	* @returns VBox status code.
983	* @param pDevIns The device instance.
984	* @param pThis The shared VGA/VMSVGA state.
985	* @param pu32 Where to store the read value
986	*/
987	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
988	{
989	#ifdef IN_RING3
990	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
991	#endif
992	int rc = VINF_SUCCESS;
993	*pu32 = 0;
994
995	/* Rough index register validation. */
996	uint32_t idxReg = pThis->svga.u32IndexReg;
997	#if !defined(IN_RING3) && defined(VBOX_STRICT)
998	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
999	VINF_IOM_R3_IOPORT_READ);
1000	#else
1001	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1002	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
1003	VINF_SUCCESS);
1004	#endif
1005	RT_UNTRUSTED_VALIDATED_FENCE();
1006
1007	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1008	if ( idxReg >= SVGA_REG_ID_0_TOP
1009	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1010	{
1011	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1012	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1013	}
1014
1015	switch (idxReg)
1016	{
1017	case SVGA_REG_ID:
1018	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
1019	*pu32 = pThis->svga.u32SVGAId;
1020	break;
1021
1022	case SVGA_REG_ENABLE:
1023	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
1024	*pu32 = pThis->svga.fEnabled;
1025	break;
1026
1027	case SVGA_REG_WIDTH:
1028	{
1029	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
1030	if ( pThis->svga.fEnabled
1031	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
1032	*pu32 = pThis->svga.uWidth;
1033	else
1034	{
1035	#ifndef IN_RING3
1036	rc = VINF_IOM_R3_IOPORT_READ;
1037	#else
1038	*pu32 = pThisCC->pDrv->cx;
1039	#endif
1040	}
1041	break;
1042	}
1043
1044	case SVGA_REG_HEIGHT:
1045	{
1046	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
1047	if ( pThis->svga.fEnabled
1048	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1049	*pu32 = pThis->svga.uHeight;
1050	else
1051	{
1052	#ifndef IN_RING3
1053	rc = VINF_IOM_R3_IOPORT_READ;
1054	#else
1055	*pu32 = pThisCC->pDrv->cy;
1056	#endif
1057	}
1058	break;
1059	}
1060
1061	case SVGA_REG_MAX_WIDTH:
1062	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
1063	*pu32 = pThis->svga.u32MaxWidth;
1064	break;
1065
1066	case SVGA_REG_MAX_HEIGHT:
1067	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
1068	*pu32 = pThis->svga.u32MaxHeight;
1069	break;
1070
1071	case SVGA_REG_DEPTH:
1072	/* This returns the color depth of the current mode. */
1073	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
1074	switch (pThis->svga.uBpp)
1075	{
1076	case 15:
1077	case 16:
1078	case 24:
1079	*pu32 = pThis->svga.uBpp;
1080	break;
1081
1082	default:
1083	case 32:
1084	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
1085	break;
1086	}
1087	break;
1088
1089	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1090	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1091	*pu32 = pThis->svga.uHostBpp;
1092	break;
1093
1094	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1095	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1096	*pu32 = pThis->svga.uBpp;
1097	break;
1098
1099	case SVGA_REG_PSEUDOCOLOR:
1100	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1101	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1102	break;
1103
1104	case SVGA_REG_RED_MASK:
1105	case SVGA_REG_GREEN_MASK:
1106	case SVGA_REG_BLUE_MASK:
1107	{
1108	uint32_t uBpp;
1109
1110	if (pThis->svga.fEnabled)
1111	uBpp = pThis->svga.uBpp;
1112	else
1113	uBpp = pThis->svga.uHostBpp;
1114
1115	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1116	switch (uBpp)
1117	{
1118	case 8:
1119	u32RedMask = 0x07;
1120	u32GreenMask = 0x38;
1121	u32BlueMask = 0xc0;
1122	break;
1123
1124	case 15:
1125	u32RedMask = 0x0000001f;
1126	u32GreenMask = 0x000003e0;
1127	u32BlueMask = 0x00007c00;
1128	break;
1129
1130	case 16:
1131	u32RedMask = 0x0000001f;
1132	u32GreenMask = 0x000007e0;
1133	u32BlueMask = 0x0000f800;
1134	break;
1135
1136	case 24:
1137	case 32:
1138	default:
1139	u32RedMask = 0x00ff0000;
1140	u32GreenMask = 0x0000ff00;
1141	u32BlueMask = 0x000000ff;
1142	break;
1143	}
1144	switch (idxReg)
1145	{
1146	case SVGA_REG_RED_MASK:
1147	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1148	*pu32 = u32RedMask;
1149	break;
1150
1151	case SVGA_REG_GREEN_MASK:
1152	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1153	*pu32 = u32GreenMask;
1154	break;
1155
1156	case SVGA_REG_BLUE_MASK:
1157	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1158	*pu32 = u32BlueMask;
1159	break;
1160	}
1161	break;
1162	}
1163
1164	case SVGA_REG_BYTES_PER_LINE:
1165	{
1166	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1167	if ( pThis->svga.fEnabled
1168	&& pThis->svga.cbScanline)
1169	*pu32 = pThis->svga.cbScanline;
1170	else
1171	{
1172	#ifndef IN_RING3
1173	rc = VINF_IOM_R3_IOPORT_READ;
1174	#else
1175	*pu32 = pThisCC->pDrv->cbScanline;
1176	#endif
1177	}
1178	break;
1179	}
1180
1181	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1182	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1183	*pu32 = pThis->vram_size;
1184	break;
1185
1186	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1187	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1188	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1189	*pu32 = pThis->GCPhysVRAM;
1190	break;
1191
1192	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1193	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1194	/* Always zero in our case. */
1195	*pu32 = 0;
1196	break;
1197
1198	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1199	{
1200	#ifndef IN_RING3
1201	rc = VINF_IOM_R3_IOPORT_READ;
1202	#else
1203	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1204
1205	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1206	if ( pThis->svga.fEnabled
1207	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1208	{
1209	/* Hardware enabled; return real framebuffer size .*/
1210	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1211	}
1212	else
1213	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1214
1215	pu32 = RT_MIN(pThis->vram_size, pu32);
1216	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1217	#endif
1218	break;
1219	}
1220
1221	case SVGA_REG_CAPABILITIES:
1222	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1223	*pu32 = pThis->svga.u32DeviceCaps;
1224	break;
1225
1226	case SVGA_REG_MEM_START: /* FIFO start */
1227	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1228	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1229	*pu32 = pThis->svga.GCPhysFIFO;
1230	break;
1231
1232	case SVGA_REG_MEM_SIZE: /* FIFO size */
1233	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1234	*pu32 = pThis->svga.cbFIFO;
1235	break;
1236
1237	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1238	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1239	*pu32 = pThis->svga.fConfigured;
1240	break;
1241
1242	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1243	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1244	*pu32 = 0;
1245	break;
1246
1247	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1248	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1249	if (pThis->svga.fBusy)
1250	{
1251	#ifndef IN_RING3
1252	/* Go to ring-3 and halt the CPU. */
1253	rc = VINF_IOM_R3_IOPORT_READ;
1254	RT_NOREF(pDevIns);
1255	break;
1256	#else
1257	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1258	/* The guest is basically doing a HLT via the device here, but with
1259	a special wake up condition on FIFO completion. */
1260	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1261	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1262	PVM pVM = PDMDevHlpGetVM(pDevIns);
1263	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1264	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1265	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1266	if (pThis->svga.fBusy)
1267	{
1268	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1269	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1270	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1271	}
1272	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1273	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1274	# else
1275
1276	/* Delay the EMT a bit so the FIFO and others can get some work done.
1277	This used to be a crude 50 ms sleep. The current code tries to be
1278	more efficient, but the consept is still very crude. */
1279	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1280	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1281	RTThreadYield();
1282	if (pThis->svga.fBusy)
1283	{
1284	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1285
1286	if (pThis->svga.fBusy && cRefs == 1)
1287	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1288	if (pThis->svga.fBusy)
1289	{
1290	/** @todo If this code is going to stay, we need to call into the halt/wait
1291	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1292	* suffer when the guest is polling on a busy FIFO. */
1293	uint64_t uIgnored1, uIgnored2;
1294	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns), &uIgnored1, &uIgnored2);
1295	if (cNsMaxWait >= RT_NS_100US)
1296	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1297	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1298	RT_MIN(cNsMaxWait, RT_NS_10MS));
1299	}
1300
1301	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1302	}
1303	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1304	# endif
1305	*pu32 = pThis->svga.fBusy != 0;
1306	#endif
1307	}
1308	else
1309	*pu32 = false;
1310	break;
1311
1312	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1313	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1314	*pu32 = pThis->svga.u32GuestId;
1315	break;
1316
1317	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1318	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1319	*pu32 = pThis->svga.cScratchRegion;
1320	break;
1321
1322	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1323	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1324	*pu32 = SVGA_FIFO_NUM_REGS;
1325	break;
1326
1327	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1328	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1329	*pu32 = pThis->svga.u32PitchLock;
1330	break;
1331
1332	case SVGA_REG_IRQMASK: /* Interrupt mask */
1333	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1334	*pu32 = pThis->svga.u32IrqMask;
1335	break;
1336
1337	/* See "Guest memory regions" below. */
1338	case SVGA_REG_GMR_ID:
1339	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1340	*pu32 = pThis->svga.u32CurrentGMRId;
1341	break;
1342
1343	case SVGA_REG_GMR_DESCRIPTOR:
1344	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1345	/* Write only */
1346	*pu32 = 0;
1347	break;
1348
1349	case SVGA_REG_GMR_MAX_IDS:
1350	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1351	*pu32 = pThis->svga.cGMR;
1352	break;
1353
1354	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1355	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1356	*pu32 = VMSVGA_MAX_GMR_PAGES;
1357	break;
1358
1359	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1360	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1361	*pu32 = pThis->svga.fTraces;
1362	break;
1363
1364	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1365	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1366	*pu32 = VMSVGA_MAX_GMR_PAGES;
1367	break;
1368
1369	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1370	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1371	*pu32 = VMSVGA_SURFACE_SIZE;
1372	break;
1373
1374	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1375	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1376	break;
1377
1378	/* Mouse cursor support. */
1379	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
1380	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1381	*pu32 = pThis->svga.uCursorID;
1382	break;
1383
1384	case SVGA_REG_CURSOR_X:
1385	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1386	*pu32 = pThis->svga.uCursorX;
1387	break;
1388
1389	case SVGA_REG_CURSOR_Y:
1390	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1391	*pu32 = pThis->svga.uCursorY;
1392	break;
1393
1394	case SVGA_REG_CURSOR_ON:
1395	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1396	*pu32 = pThis->svga.uCursorOn;
1397	break;
1398
1399	/* Legacy multi-monitor support */
1400	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1401	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1402	*pu32 = 1;
1403	break;
1404
1405	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1406	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1407	*pu32 = 0;
1408	break;
1409
1410	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1411	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1412	*pu32 = 0;
1413	break;
1414
1415	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1416	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1417	*pu32 = 0;
1418	break;
1419
1420	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1421	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1422	*pu32 = 0;
1423	break;
1424
1425	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1426	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1427	*pu32 = pThis->svga.uWidth;
1428	break;
1429
1430	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1431	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1432	*pu32 = pThis->svga.uHeight;
1433	break;
1434
1435	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1436	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1437	/* We must return something sensible here otherwise the Linux driver
1438	will take a legacy code path without 3d support. This number also
1439	limits how many screens Linux guests will allow. */
1440	*pu32 = pThis->cMonitors;
1441	break;
1442
1443	/*
1444	* SVGA_CAP_GBOBJECTS+ registers.
1445	*/
1446	case SVGA_REG_COMMAND_LOW:
1447	/* Lower 32 bits of command buffer physical address. */
1448	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowRd);
1449	*pu32 = pThis->svga.u32RegCommandLow;
1450	break;
1451
1452	case SVGA_REG_COMMAND_HIGH:
1453	/* Upper 32 bits of command buffer PA. */
1454	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighRd);
1455	*pu32 = pThis->svga.u32RegCommandHigh;
1456	break;
1457
1458	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
1459	/* Max primary (screen) memory. */
1460	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxPrimBBMemRd);
1461	pu32 = pThis->vram_size; /* @todo Maybe half VRAM? */
1462	break;
1463
1464	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
1465	/* Suggested limit on mob mem (i.e. size of the guest mapped VRAM in KB) */
1466	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGBMemSizeRd);
1467	*pu32 = pThis->vram_size / 1024;
1468	break;
1469
1470	case SVGA_REG_DEV_CAP:
1471	/* Write dev cap index, read value */
1472	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapRd);
1473	if (pThis->svga.u32DevCapIndex < RT_ELEMENTS(pThis->svga.au32DevCaps))
1474	{
1475	RT_UNTRUSTED_VALIDATED_FENCE();
1476	*pu32 = pThis->svga.au32DevCaps[pThis->svga.u32DevCapIndex];
1477	}
1478	else
1479	*pu32 = 0;
1480	break;
1481
1482	case SVGA_REG_CMD_PREPEND_LOW:
1483	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowRd);
1484	pu32 = 0; / Not supported. */
1485	break;
1486
1487	case SVGA_REG_CMD_PREPEND_HIGH:
1488	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighRd);
1489	pu32 = 0; / Not supported. */
1490	break;
1491
1492	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
1493	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxWidthRd);
1494	*pu32 = pThis->svga.u32MaxWidth;
1495	break;
1496
1497	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
1498	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxHeightRd);
1499	*pu32 = pThis->svga.u32MaxHeight;
1500	break;
1501
1502	case SVGA_REG_MOB_MAX_SIZE:
1503	/* Essentially the max texture size */
1504	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMobMaxSizeRd);
1505	pu32 = _128M; /* @todo Some actual value. Probably the mapped VRAM size. */
1506	break;
1507
1508	default:
1509	{
1510	uint32_t offReg;
1511	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1512	{
1513	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1514	RT_UNTRUSTED_VALIDATED_FENCE();
1515	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1516	}
1517	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1518	{
1519	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1520	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1521	RT_UNTRUSTED_VALIDATED_FENCE();
1522	uint32_t u32 = pThis->last_palette[offReg / 3];
1523	switch (offReg % 3)
1524	{
1525	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1526	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1527	case 2: pu32 = u32 & 0xff; break; / blue */
1528	}
1529	}
1530	else
1531	{
1532	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1533	rc = VINF_IOM_R3_IOPORT_READ;
1534	#else
1535	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1536
1537	/* Do not assert. The guest might be reading all registers. */
1538	LogFunc(("Unknown reg=%#x\n", idxReg));
1539	#endif
1540	}
1541	break;
1542	}
1543	}
1544	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1545	return rc;
1546	}
1547
1548	#ifdef IN_RING3
1549	/**
1550	* Apply the current resolution settings to change the video mode.
1551	*
1552	* @returns VBox status code.
1553	* @param pThis The shared VGA state.
1554	* @param pThisCC The ring-3 VGA state.
1555	*/
1556	int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1557	{
1558	/* Always do changemode on FIFO thread. */
1559	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1560
1561	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1562
1563	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1564
1565	if (pThis->svga.fGFBRegisters)
1566	{
1567	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1568	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1569	* deletes all screens other than screen #0, and redefines screen
1570	* #0 according to the specified mode. Drivers that use
1571	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1572	*/
1573
1574	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1575	pScreen->fDefined = true;
1576	pScreen->fModified = true;
1577	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1578	pScreen->idScreen = 0;
1579	pScreen->xOrigin = 0;
1580	pScreen->yOrigin = 0;
1581	pScreen->offVRAM = 0;
1582	pScreen->cbPitch = pThis->svga.cbScanline;
1583	pScreen->cWidth = pThis->svga.uWidth;
1584	pScreen->cHeight = pThis->svga.uHeight;
1585	pScreen->cBpp = pThis->svga.uBpp;
1586
1587	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1588	{
1589	/* Delete screen. */
1590	pScreen = &pSVGAState->aScreens[iScreen];
1591	if (pScreen->fDefined)
1592	{
1593	pScreen->fModified = true;
1594	pScreen->fDefined = false;
1595	}
1596	}
1597	}
1598	else
1599	{
1600	/* "If Screen Objects are supported, they can be used to fully
1601	* replace the functionality provided by the framebuffer registers
1602	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1603	*/
1604	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1605	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1606	pThis->svga.uBpp = pThis->svga.uHostBpp;
1607	}
1608
1609	vmsvgaR3VBVAResize(pThis, pThisCC);
1610
1611	/* Last stuff. For the VGA device screenshot. */
1612	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1613	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1614	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1615	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1616	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1617
1618	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1619	if ( pThis->svga.viewport.cx == 0
1620	&& pThis->svga.viewport.cy == 0)
1621	{
1622	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1623	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1624	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1625	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1626	pThis->svga.viewport.yLowWC = 0;
1627	}
1628
1629	return VINF_SUCCESS;
1630	}
1631
1632	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1633	{
1634	VBVACMDHDR cmd;
1635	cmd.x = (int16_t)(pScreen->xOrigin + x);
1636	cmd.y = (int16_t)(pScreen->yOrigin + y);
1637	cmd.w = (uint16_t)w;
1638	cmd.h = (uint16_t)h;
1639
1640	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1641	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1642	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1643	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1644
1645	return VINF_SUCCESS;
1646	}
1647
1648	#endif /* IN_RING3 */
1649	#if defined(IN_RING0) \|\| defined(IN_RING3)
1650
1651	/**
1652	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1653	*
1654	* @param pThis The shared VGA/VMSVGA instance data.
1655	* @param pThisCC The VGA/VMSVGA state for the current context.
1656	* @param fState The busy state.
1657	*/
1658	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1659	{
1660	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1661
1662	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1663	{
1664	/* Race / unfortunately scheduling. Highly unlikly. */
1665	uint32_t cLoops = 64;
1666	do
1667	{
1668	ASMNopPause();
1669	fState = (pThis->svga.fBusy != 0);
1670	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1671	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1672	}
1673	}
1674
1675
1676	/**
1677	* Update the scanline pitch in response to the guest changing mode
1678	* width/bpp.
1679	*
1680	* @param pThis The shared VGA/VMSVGA state.
1681	* @param pThisCC The VGA/VMSVGA state for the current context.
1682	*/
1683	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1684	{
1685	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1686	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1687	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1688	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1689
1690	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1691	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1692	* location but it has a different meaning.
1693	*/
1694	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1695	uFifoPitchLock = 0;
1696
1697	/* Sanitize values. */
1698	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1699	uFifoPitchLock = 0;
1700	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1701	uRegPitchLock = 0;
1702
1703	/* Prefer the register value to the FIFO value.*/
1704	if (uRegPitchLock)
1705	pThis->svga.cbScanline = uRegPitchLock;
1706	else if (uFifoPitchLock)
1707	pThis->svga.cbScanline = uFifoPitchLock;
1708	else
1709	pThis->svga.cbScanline = (uint32_t)pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1710
1711	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1712	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1713	}
1714
1715	#endif /* IN_RING0 \|\| IN_RING3 */
1716
1717	#ifdef IN_RING3
1718
1719	/**
1720	* Sends cursor position and visibility information from legacy
1721	* SVGA registers to the front-end.
1722	*/
1723	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1724	{
1725	/*
1726	* Writing the X/Y/ID registers does not trigger changes; only writing the
1727	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1728	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1729	* register if they don't have to.
1730	*/
1731	uint32_t x, y, idScreen;
1732	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1733
1734	x = pThis->svga.uCursorX;
1735	y = pThis->svga.uCursorY;
1736	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1737
1738	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1739	* were extended as follows:
1740	*
1741	* SVGA_CURSOR_ON_HIDE 0
1742	* SVGA_CURSOR_ON_SHOW 1
1743	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1744	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1745	*
1746	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1747	* distinguish between the non-zero values but still remember them.
1748	*/
1749	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1750	{
1751	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1752	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1753	}
1754	pThis->svga.uCursorOn = uCursorOn;
1755	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1756	}
1757
1758	#endif /* IN_RING3 */
1759
1760
1761	/**
1762	* Write port register
1763	*
1764	* @returns Strict VBox status code.
1765	* @param pDevIns The device instance.
1766	* @param pThis The shared VGA/VMSVGA state.
1767	* @param pThisCC The VGA/VMSVGA state for the current context.
1768	* @param u32 Value to write
1769	*/
1770	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1771	{
1772	#ifdef IN_RING3
1773	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1774	#endif
1775	VBOXSTRICTRC rc = VINF_SUCCESS;
1776	RT_NOREF(pThisCC);
1777
1778	/* Rough index register validation. */
1779	uint32_t idxReg = pThis->svga.u32IndexReg;
1780	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1781	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1782	VINF_IOM_R3_IOPORT_WRITE);
1783	#else
1784	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1785	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1786	VINF_SUCCESS);
1787	#endif
1788	RT_UNTRUSTED_VALIDATED_FENCE();
1789
1790	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1791	if ( idxReg >= SVGA_REG_ID_0_TOP
1792	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1793	{
1794	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1795	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1796	}
1797	#ifdef LOG_ENABLED
1798	if (idxReg != SVGA_REG_DEV_CAP)
1799	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1800	else
1801	Log(("vmsvgaWritePort index=%s (%d) val=%s (%d)\n", vmsvgaIndexToString(pThis, idxReg), idxReg, vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)u32), u32));
1802	#endif
1803	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1804	switch (idxReg)
1805	{
1806	case SVGA_REG_WIDTH:
1807	case SVGA_REG_HEIGHT:
1808	case SVGA_REG_PITCHLOCK:
1809	case SVGA_REG_BITS_PER_PIXEL:
1810	pThis->svga.fGFBRegisters = true;
1811	break;
1812	default:
1813	break;
1814	}
1815
1816	switch (idxReg)
1817	{
1818	case SVGA_REG_ID:
1819	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1820	if ( u32 == SVGA_ID_0
1821	\|\| u32 == SVGA_ID_1
1822	\|\| u32 == SVGA_ID_2)
1823	pThis->svga.u32SVGAId = u32;
1824	else
1825	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1826	break;
1827
1828	case SVGA_REG_ENABLE:
1829	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1830	#ifdef IN_RING3
1831	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1832	&& pThis->svga.fEnabled == false)
1833	{
1834	/* Make a backup copy of the first 512kb in order to save font data etc. */
1835	/** @todo should probably swap here, rather than copy + zero */
1836	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1837	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1838	}
1839
1840	pThis->svga.fEnabled = u32;
1841	if (pThis->svga.fEnabled)
1842	{
1843	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1844	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1845	{
1846	/* Keep the current mode. */
1847	pThis->svga.uWidth = pThisCC->pDrv->cx;
1848	pThis->svga.uHeight = pThisCC->pDrv->cy;
1849	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1850	}
1851
1852	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1853	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1854	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1855	# ifdef LOG_ENABLED
1856	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1857	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1858	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1859	# endif
1860
1861	/* Disable or enable dirty page tracking according to the current fTraces value. */
1862	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1863
1864	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1865	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1866	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1867
1868	/* Make the cursor visible again as needed. */
1869	if (pSVGAState->Cursor.fActive)
1870	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, false, 0, 0, 0, 0, NULL);
1871	}
1872	else
1873	{
1874	/* Make sure the cursor is off. */
1875	if (pSVGAState->Cursor.fActive)
1876	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /fVisible/, false, 0, 0, 0, 0, NULL);
1877
1878	/* Restore the text mode backup. */
1879	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1880
1881	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1882
1883	/* Enable dirty page tracking again when going into legacy mode. */
1884	vmsvgaR3SetTraces(pDevIns, pThis, true);
1885
1886	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1887	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1888	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1889
1890	/* Clear the pitch lock. */
1891	pThis->svga.u32PitchLock = 0;
1892	}
1893	#else /* !IN_RING3 */
1894	rc = VINF_IOM_R3_IOPORT_WRITE;
1895	#endif /* !IN_RING3 */
1896	break;
1897
1898	case SVGA_REG_WIDTH:
1899	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1900	if (u32 != pThis->svga.uWidth)
1901	{
1902	if (u32 <= pThis->svga.u32MaxWidth)
1903	{
1904	#if defined(IN_RING3) \|\| defined(IN_RING0)
1905	pThis->svga.uWidth = u32;
1906	vmsvgaHCUpdatePitch(pThis, pThisCC);
1907	if (pThis->svga.fEnabled)
1908	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1909	#else
1910	rc = VINF_IOM_R3_IOPORT_WRITE;
1911	#endif
1912	}
1913	else
1914	Log(("SVGA_REG_WIDTH: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxWidth));
1915	}
1916	/* else: nop */
1917	break;
1918
1919	case SVGA_REG_HEIGHT:
1920	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1921	if (u32 != pThis->svga.uHeight)
1922	{
1923	if (u32 <= pThis->svga.u32MaxHeight)
1924	{
1925	pThis->svga.uHeight = u32;
1926	if (pThis->svga.fEnabled)
1927	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1928	}
1929	else
1930	Log(("SVGA_REG_HEIGHT: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxHeight));
1931	}
1932	/* else: nop */
1933	break;
1934
1935	case SVGA_REG_DEPTH:
1936	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1937	/** @todo read-only?? */
1938	break;
1939
1940	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1941	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1942	if (pThis->svga.uBpp != u32)
1943	{
1944	if (u32 <= 32)
1945	{
1946	#if defined(IN_RING3) \|\| defined(IN_RING0)
1947	pThis->svga.uBpp = u32;
1948	vmsvgaHCUpdatePitch(pThis, pThisCC);
1949	if (pThis->svga.fEnabled)
1950	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1951	#else
1952	rc = VINF_IOM_R3_IOPORT_WRITE;
1953	#endif
1954	}
1955	else
1956	Log(("SVGA_REG_BITS_PER_PIXEL: New value is out of bounds: %u, max 32\n", u32));
1957	}
1958	/* else: nop */
1959	break;
1960
1961	case SVGA_REG_PSEUDOCOLOR:
1962	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1963	break;
1964
1965	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1966	#ifdef IN_RING3
1967	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1968	pThis->svga.fConfigured = u32;
1969	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1970	if (!pThis->svga.fConfigured)
1971	pThis->svga.fTraces = true;
1972	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1973	#else
1974	rc = VINF_IOM_R3_IOPORT_WRITE;
1975	#endif
1976	break;
1977
1978	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1979	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1980	if ( pThis->svga.fEnabled
1981	&& pThis->svga.fConfigured)
1982	{
1983	#if defined(IN_RING3) \|\| defined(IN_RING0)
1984	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1985	/*
1986	* The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
1987	* at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
1988	*/
1989	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1990	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1991	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1992
1993	/* Kick the FIFO thread to start processing commands again. */
1994	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1995	#else
1996	rc = VINF_IOM_R3_IOPORT_WRITE;
1997	#endif
1998	}
1999	/* else nothing to do. */
2000	else
2001	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
2002
2003	break;
2004
2005	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
2006	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
2007	break;
2008
2009	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
2010	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
2011	pThis->svga.u32GuestId = u32;
2012	break;
2013
2014	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
2015	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
2016	pThis->svga.u32PitchLock = u32;
2017	/* Should this also update the FIFO pitch lock? Unclear. */
2018	break;
2019
2020	case SVGA_REG_IRQMASK: /* Interrupt mask */
2021	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
2022	pThis->svga.u32IrqMask = u32;
2023
2024	/* Irq pending after the above change? */
2025	if (pThis->svga.u32IrqStatus & u32)
2026	{
2027	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
2028	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
2029	}
2030	else
2031	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2032	break;
2033
2034	/* Mouse cursor support */
2035	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
2036	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
2037	pThis->svga.uCursorID = u32;
2038	break;
2039
2040	case SVGA_REG_CURSOR_X:
2041	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
2042	pThis->svga.uCursorX = u32;
2043	break;
2044
2045	case SVGA_REG_CURSOR_Y:
2046	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
2047	pThis->svga.uCursorY = u32;
2048	break;
2049
2050	case SVGA_REG_CURSOR_ON:
2051	#ifdef IN_RING3
2052	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
2053	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
2054	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
2055	#else
2056	rc = VINF_IOM_R3_IOPORT_WRITE;
2057	#endif
2058	break;
2059
2060	/* Legacy multi-monitor support */
2061	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
2062	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
2063	break;
2064	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
2065	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
2066	break;
2067	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
2068	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
2069	break;
2070	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
2071	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
2072	break;
2073	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
2074	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
2075	break;
2076	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
2077	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
2078	break;
2079	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
2080	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
2081	break;
2082	#ifdef VBOX_WITH_VMSVGA3D
2083	/* See "Guest memory regions" below. */
2084	case SVGA_REG_GMR_ID:
2085	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
2086	pThis->svga.u32CurrentGMRId = u32;
2087	break;
2088
2089	case SVGA_REG_GMR_DESCRIPTOR:
2090	# ifndef IN_RING3
2091	rc = VINF_IOM_R3_IOPORT_WRITE;
2092	break;
2093	# else /* IN_RING3 */
2094	{
2095	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
2096
2097	/* Validate current GMR id. */
2098	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
2099	AssertBreak(idGMR < pThis->svga.cGMR);
2100	RT_UNTRUSTED_VALIDATED_FENCE();
2101
2102	/* Free the old GMR if present. */
2103	vmsvgaR3GmrFree(pThisCC, idGMR);
2104
2105	/* Just undefine the GMR? */
2106	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
2107	if (GCPhys == 0)
2108	{
2109	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
2110	break;
2111	}
2112
2113
2114	/* Never cross a page boundary automatically. */
2115	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
2116	uint32_t cPagesTotal = 0;
2117	uint32_t iDesc = 0;
2118	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2119	uint32_t cLoops = 0;
2120	RTGCPHYS GCPhysBase = GCPhys;
2121	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
2122	{
2123	/* Read descriptor. */
2124	SVGAGuestMemDescriptor desc;
2125	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2126	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2127
2128	if (desc.numPages != 0)
2129	{
2130	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2131	cPagesTotal += desc.numPages;
2132	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2133
2134	if ((iDesc & 15) == 0)
2135	{
2136	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
2137	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2138	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2139	}
2140
2141	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2142	paDescs[iDesc++].numPages = desc.numPages;
2143
2144	/* Continue with the next descriptor. */
2145	GCPhys += sizeof(desc);
2146	}
2147	else if (desc.ppn == 0)
2148	break; /* terminator */
2149	else /* Pointer to the next physical page of descriptors. */
2150	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2151
2152	cLoops++;
2153	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2154	}
2155
2156	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2157	if (RT_SUCCESS(rc))
2158	{
2159	/* Commit the GMR. */
2160	pSVGAState->paGMR[idGMR].paDesc = paDescs;
2161	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2162	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2163	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
2164	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
2165	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2166	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2167	}
2168	else
2169	{
2170	RTMemFree(paDescs);
2171	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2172	}
2173	break;
2174	}
2175	# endif /* IN_RING3 */
2176	#endif // VBOX_WITH_VMSVGA3D
2177
2178	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2179	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2180	if (pThis->svga.fTraces == u32)
2181	break; /* nothing to do */
2182
2183	#ifdef IN_RING3
2184	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2185	#else
2186	rc = VINF_IOM_R3_IOPORT_WRITE;
2187	#endif
2188	break;
2189
2190	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2191	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2192	break;
2193
2194	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2195	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2196	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2197	break;
2198
2199	/*
2200	* SVGA_CAP_GBOBJECTS+ registers.
2201	*/
2202	case SVGA_REG_COMMAND_LOW:
2203	{
2204	/* Lower 32 bits of command buffer physical address and submit the command buffer. */
2205	#ifdef IN_RING3
2206	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowWr);
2207	pThis->svga.u32RegCommandLow = u32;
2208
2209	/* "lower 6 bits are used for the SVGACBContext" */
2210	RTGCPHYS GCPhysCB = pThis->svga.u32RegCommandHigh;
2211	GCPhysCB <<= 32;
2212	GCPhysCB \|= pThis->svga.u32RegCommandLow & ~SVGA_CB_CONTEXT_MASK;
2213	SVGACBContext const CBCtx = (SVGACBContext)(pThis->svga.u32RegCommandLow & SVGA_CB_CONTEXT_MASK);
2214	vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, GCPhysCB, CBCtx);
2215	#else
2216	rc = VINF_IOM_R3_IOPORT_WRITE;
2217	#endif
2218	break;
2219	}
2220
2221	case SVGA_REG_COMMAND_HIGH:
2222	/* Upper 32 bits of command buffer PA. */
2223	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighWr);
2224	pThis->svga.u32RegCommandHigh = u32;
2225	break;
2226
2227	case SVGA_REG_DEV_CAP:
2228	/* Write dev cap index, read value */
2229	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapWr);
2230	pThis->svga.u32DevCapIndex = u32;
2231	break;
2232
2233	case SVGA_REG_CMD_PREPEND_LOW:
2234	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowWr);
2235	/* Not supported. */
2236	break;
2237
2238	case SVGA_REG_CMD_PREPEND_HIGH:
2239	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighWr);
2240	/* Not supported. */
2241	break;
2242
2243	case SVGA_REG_FB_START:
2244	case SVGA_REG_MEM_START:
2245	case SVGA_REG_HOST_BITS_PER_PIXEL:
2246	case SVGA_REG_MAX_WIDTH:
2247	case SVGA_REG_MAX_HEIGHT:
2248	case SVGA_REG_VRAM_SIZE:
2249	case SVGA_REG_FB_SIZE:
2250	case SVGA_REG_CAPABILITIES:
2251	case SVGA_REG_MEM_SIZE:
2252	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2253	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2254	case SVGA_REG_BYTES_PER_LINE:
2255	case SVGA_REG_FB_OFFSET:
2256	case SVGA_REG_RED_MASK:
2257	case SVGA_REG_GREEN_MASK:
2258	case SVGA_REG_BLUE_MASK:
2259	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2260	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2261	case SVGA_REG_GMR_MAX_IDS:
2262	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2263	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
2264	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
2265	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
2266	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
2267	case SVGA_REG_MOB_MAX_SIZE:
2268	/* Read only - ignore. */
2269	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2270	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2271	break;
2272
2273	default:
2274	{
2275	uint32_t offReg;
2276	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2277	{
2278	RT_UNTRUSTED_VALIDATED_FENCE();
2279	pThis->svga.au32ScratchRegion[offReg] = u32;
2280	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2281	}
2282	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2283	{
2284	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2285	Btw, see rgb_to_pixel32. */
2286	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2287	u32 &= 0xff;
2288	RT_UNTRUSTED_VALIDATED_FENCE();
2289	uint32_t uRgb = pThis->last_palette[offReg / 3];
2290	switch (offReg % 3)
2291	{
2292	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2293	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2294	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2295	}
2296	pThis->last_palette[offReg / 3] = uRgb;
2297	}
2298	else
2299	{
2300	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2301	rc = VINF_IOM_R3_IOPORT_WRITE;
2302	#else
2303	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2304	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2305	#endif
2306	}
2307	break;
2308	}
2309	}
2310	return rc;
2311	}
2312
2313	/**
2314	* @callback_method_impl{FNIOMIOPORTNEWIN}
2315	*/
2316	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2317	{
2318	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2319	RT_NOREF_PV(pvUser);
2320
2321	/* Only dword accesses. */
2322	if (cb == 4)
2323	{
2324	switch (offPort)
2325	{
2326	case SVGA_INDEX_PORT:
2327	*pu32 = pThis->svga.u32IndexReg;
2328	break;
2329
2330	case SVGA_VALUE_PORT:
2331	return vmsvgaReadPort(pDevIns, pThis, pu32);
2332
2333	case SVGA_BIOS_PORT:
2334	Log(("Ignoring BIOS port read\n"));
2335	*pu32 = 0;
2336	break;
2337
2338	case SVGA_IRQSTATUS_PORT:
2339	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2340	*pu32 = pThis->svga.u32IrqStatus;
2341	break;
2342
2343	default:
2344	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2345	*pu32 = UINT32_MAX;
2346	break;
2347	}
2348	}
2349	else
2350	{
2351	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2352	*pu32 = UINT32_MAX;
2353	}
2354	return VINF_SUCCESS;
2355	}
2356
2357	/**
2358	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2359	*/
2360	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2361	{
2362	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2363	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2364	RT_NOREF_PV(pvUser);
2365
2366	/* Only dword accesses. */
2367	if (cb == 4)
2368	switch (offPort)
2369	{
2370	case SVGA_INDEX_PORT:
2371	pThis->svga.u32IndexReg = u32;
2372	break;
2373
2374	case SVGA_VALUE_PORT:
2375	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2376
2377	case SVGA_BIOS_PORT:
2378	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2379	break;
2380
2381	case SVGA_IRQSTATUS_PORT:
2382	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2383	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2384	/* Clear the irq in case all events have been cleared. */
2385	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2386	{
2387	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2388	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2389	}
2390	break;
2391
2392	default:
2393	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2394	break;
2395	}
2396	else
2397	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2398
2399	return VINF_SUCCESS;
2400	}
2401
2402	#ifdef IN_RING3
2403
2404	# ifdef DEBUG_FIFO_ACCESS
2405	/**
2406	* Handle FIFO memory access.
2407	* @returns VBox status code.
2408	* @param pVM VM handle.
2409	* @param pThis The shared VGA/VMSVGA instance data.
2410	* @param GCPhys The access physical address.
2411	* @param fWriteAccess Read or write access
2412	*/
2413	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2414	{
2415	RT_NOREF(pVM);
2416	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2417	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2418
2419	switch (GCPhysOffset >> 2)
2420	{
2421	case SVGA_FIFO_MIN:
2422	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2423	break;
2424	case SVGA_FIFO_MAX:
2425	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2426	break;
2427	case SVGA_FIFO_NEXT_CMD:
2428	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2429	break;
2430	case SVGA_FIFO_STOP:
2431	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2432	break;
2433	case SVGA_FIFO_CAPABILITIES:
2434	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2435	break;
2436	case SVGA_FIFO_FLAGS:
2437	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2438	break;
2439	case SVGA_FIFO_FENCE:
2440	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2441	break;
2442	case SVGA_FIFO_3D_HWVERSION:
2443	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2444	break;
2445	case SVGA_FIFO_PITCHLOCK:
2446	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2447	break;
2448	case SVGA_FIFO_CURSOR_ON:
2449	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2450	break;
2451	case SVGA_FIFO_CURSOR_X:
2452	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2453	break;
2454	case SVGA_FIFO_CURSOR_Y:
2455	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2456	break;
2457	case SVGA_FIFO_CURSOR_COUNT:
2458	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2459	break;
2460	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2461	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2462	break;
2463	case SVGA_FIFO_RESERVED:
2464	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2465	break;
2466	case SVGA_FIFO_CURSOR_SCREEN_ID:
2467	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2468	break;
2469	case SVGA_FIFO_DEAD:
2470	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2471	break;
2472	case SVGA_FIFO_3D_HWVERSION_REVISED:
2473	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2474	break;
2475	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2476	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2477	break;
2478	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2479	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2480	break;
2481	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2482	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2483	break;
2484	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2485	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2486	break;
2487	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2488	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2489	break;
2490	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2491	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2492	break;
2493	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2494	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2495	break;
2496	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2497	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2498	break;
2499	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2500	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2501	break;
2502	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2503	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2504	break;
2505	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2506	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2507	break;
2508	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2509	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2510	break;
2511	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2512	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2513	break;
2514	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2515	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2516	break;
2517	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2518	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2519	break;
2520	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2521	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2522	break;
2523	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2524	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2525	break;
2526	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2527	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2528	break;
2529	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2530	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2531	break;
2532	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2533	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2534	break;
2535	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2536	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2537	break;
2538	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2539	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2540	break;
2541	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2542	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2543	break;
2544	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2545	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2546	break;
2547	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2548	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2549	break;
2550	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2551	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2552	break;
2553	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2554	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2555	break;
2556	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2557	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2558	break;
2559	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2560	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2561	break;
2562	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2563	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2564	break;
2565	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2566	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2567	break;
2568	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2569	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2570	break;
2571	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2572	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2573	break;
2574	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2575	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2576	break;
2577	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2578	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2579	break;
2580	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2581	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2582	break;
2583	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2584	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2585	break;
2586	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2587	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2588	break;
2589	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2590	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2591	break;
2592	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2593	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2594	break;
2595	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2596	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2597	break;
2598	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2599	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2600	break;
2601	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2602	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2603	break;
2604	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2605	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2606	break;
2607	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2608	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2609	break;
2610	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2611	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2612	break;
2613	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2614	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2615	break;
2616	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2617	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2618	break;
2619	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2620	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2621	break;
2622	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2623	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2624	break;
2625	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2626	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2627	break;
2628	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2629	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2630	break;
2631	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2632	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2633	break;
2634	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2635	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2636	break;
2637	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2638	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2639	break;
2640	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2641	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2642	break;
2643	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2644	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2645	break;
2646	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2647	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2648	break;
2649	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2650	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2651	break;
2652	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2653	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2654	break;
2655	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2656	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2657	break;
2658	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2659	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2660	break;
2661	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2662	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2663	break;
2664	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2665	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2666	break;
2667	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2668	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2669	break;
2670	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2671	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2672	break;
2673	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2674	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2675	break;
2676	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2677	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2678	break;
2679	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2680	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2681	break;
2682	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD4: /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
2683	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD4 (SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2684	break;
2685	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD5: /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
2686	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD5 (SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2687	break;
2688	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD7: /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
2689	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD7 (SVGA3D_DEVCAP_ALPHATOCOVERAGE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2690	break;
2691	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD6: /* SVGA3D_DEVCAP_SUPERSAMPLE */
2692	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD6 (SVGA3D_DEVCAP_SUPERSAMPLE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2693	break;
2694	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2695	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2696	break;
2697	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2698	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2699	break;
2700	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
2701	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD10 (SVGA3D_DEVCAP_SURFACEFMT_AYUV) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2702	break;
2703	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2704	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2705	break;
2706	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2707	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2708	break;
2709	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2710	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2711	break;
2712	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2713	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2714	break;
2715	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2716	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2717	break;
2718	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI1:
2719	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2720	break;
2721	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI2:
2722	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2723	break;
2724	case SVGA_FIFO_3D_CAPS_LAST:
2725	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2726	break;
2727	case SVGA_FIFO_GUEST_3D_HWVERSION:
2728	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2729	break;
2730	case SVGA_FIFO_FENCE_GOAL:
2731	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2732	break;
2733	case SVGA_FIFO_BUSY:
2734	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2735	break;
2736	default:
2737	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2738	break;
2739	}
2740
2741	return VINF_EM_RAW_EMULATE_INSTR;
2742	}
2743	# endif /* DEBUG_FIFO_ACCESS */
2744
2745	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2746	/**
2747	* HC access handler for the FIFO.
2748	*
2749	* @returns VINF_SUCCESS if the handler have carried out the operation.
2750	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2751	* @param pVM VM Handle.
2752	* @param pVCpu The cross context CPU structure for the calling EMT.
2753	* @param GCPhys The physical address the guest is writing to.
2754	* @param pvPhys The HC mapping of that address.
2755	* @param pvBuf What the guest is reading/writing.
2756	* @param cbBuf How much it's reading/writing.
2757	* @param enmAccessType The access type.
2758	* @param enmOrigin Who is making the access.
2759	* @param pvUser User argument.
2760	*/
2761	static DECLCALLBACK(VBOXSTRICTRC)
2762	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2763	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2764	{
2765	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2766	PVGASTATE pThis = (PVGASTATE)pvUser;
2767	AssertPtr(pThis);
2768
2769	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2770	/*
2771	* Wake up the FIFO thread as it might have work to do now.
2772	*/
2773	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2774	AssertLogRelRC(rc);
2775	# endif
2776
2777	# ifdef DEBUG_FIFO_ACCESS
2778	/*
2779	* When in debug-fifo-access mode, we do not disable the access handler,
2780	* but leave it on as we wish to catch all access.
2781	*/
2782	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2783	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2784	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2785	/*
2786	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2787	*/
2788	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2789	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2790	# endif
2791	if (RT_SUCCESS(rc))
2792	return VINF_PGM_HANDLER_DO_DEFAULT;
2793	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2794	return rc;
2795	}
2796	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2797
2798	#endif /* IN_RING3 */
2799
2800	#ifdef DEBUG_GMR_ACCESS
2801	# ifdef IN_RING3
2802
2803	/**
2804	* HC access handler for GMRs.
2805	*
2806	* @returns VINF_SUCCESS if the handler have carried out the operation.
2807	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2808	* @param pVM VM Handle.
2809	* @param pVCpu The cross context CPU structure for the calling EMT.
2810	* @param GCPhys The physical address the guest is writing to.
2811	* @param pvPhys The HC mapping of that address.
2812	* @param pvBuf What the guest is reading/writing.
2813	* @param cbBuf How much it's reading/writing.
2814	* @param enmAccessType The access type.
2815	* @param enmOrigin Who is making the access.
2816	* @param pvUser User argument.
2817	*/
2818	static DECLCALLBACK(VBOXSTRICTRC)
2819	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2820	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2821	{
2822	PVGASTATE pThis = (PVGASTATE)pvUser;
2823	Assert(pThis);
2824	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2825	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2826
2827	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2828
2829	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2830	{
2831	PGMR pGMR = &pSVGAState->paGMR[i];
2832
2833	if (pGMR->numDescriptors)
2834	{
2835	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2836	{
2837	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2838	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2839	{
2840	/*
2841	* Turn off the write handler for this particular page and make it R/W.
2842	* Then return telling the caller to restart the guest instruction.
2843	*/
2844	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2845	AssertRC(rc);
2846	return VINF_PGM_HANDLER_DO_DEFAULT;
2847	}
2848	}
2849	}
2850	}
2851
2852	return VINF_PGM_HANDLER_DO_DEFAULT;
2853	}
2854
2855	/** Callback handler for VMR3ReqCallWaitU */
2856	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2857	{
2858	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2859	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2860	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2861	int rc;
2862
2863	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2864	{
2865	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2866	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2867	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2868	AssertRC(rc);
2869	}
2870	return VINF_SUCCESS;
2871	}
2872
2873	/** Callback handler for VMR3ReqCallWaitU */
2874	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2875	{
2876	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2877	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2878	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2879
2880	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2881	{
2882	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2883	AssertRC(rc);
2884	}
2885	return VINF_SUCCESS;
2886	}
2887
2888	/** Callback handler for VMR3ReqCallWaitU */
2889	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2890	{
2891	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2892
2893	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2894	{
2895	PGMR pGMR = &pSVGAState->paGMR[i];
2896
2897	if (pGMR->numDescriptors)
2898	{
2899	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2900	{
2901	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2902	AssertRC(rc);
2903	}
2904	}
2905	}
2906	return VINF_SUCCESS;
2907	}
2908
2909	# endif /* IN_RING3 */
2910	#endif /* DEBUG_GMR_ACCESS */
2911
2912	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2913
2914	#ifdef IN_RING3
2915
2916
2917	/*
2918	*
2919	* Command buffer submission.
2920	*
2921	* Guest submits a buffer by writing to SVGA_REG_COMMAND_LOW register.
2922	*
2923	* EMT thread appends a command buffer to the context queue (VMSVGACMDBUFCTX::listSubmitted)
2924	* and wakes up the FIFO thread.
2925	*
2926	* FIFO thread fetches the command buffer from the queue, processes the commands and writes
2927	* the buffer header back to the guest memory.
2928	*
2929	* If buffers are preempted, then the EMT thread removes all buffers from the context queue.
2930	*
2931	*/
2932
2933
2934	/** Update a command buffer header 'status' and 'errorOffset' fields in the guest memory.
2935	*
2936	* @param pDevIns The device instance.
2937	* @param GCPhysCB Guest physical address of the command buffer header.
2938	* @param status Command buffer status (SVGA_CB_STATUS_*).
2939	* @param errorOffset Offset to the first byte of the failing command for SVGA_CB_STATUS_COMMAND_ERROR.
2940	* errorOffset is ignored if the status is not SVGA_CB_STATUS_COMMAND_ERROR.
2941	* @thread FIFO or EMT.
2942	*/
2943	static void vmsvgaR3CmdBufWriteStatus(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCB, SVGACBStatus status, uint32_t errorOffset)
2944	{
2945	SVGACBHeader hdr;
2946	hdr.status = status;
2947	hdr.errorOffset = errorOffset;
2948	AssertCompile( RT_OFFSETOF(SVGACBHeader, status) == 0
2949	&& RT_OFFSETOF(SVGACBHeader, errorOffset) == 4
2950	&& RT_OFFSETOF(SVGACBHeader, id) == 8);
2951	size_t const cbWrite = status == SVGA_CB_STATUS_COMMAND_ERROR
2952	? RT_UOFFSET_AFTER(SVGACBHeader, errorOffset) /* Both 'status' and 'errorOffset' fields. */
2953	: RT_UOFFSET_AFTER(SVGACBHeader, status); /* Only 'status' field. */
2954	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysCB, &hdr, cbWrite);
2955	}
2956
2957
2958	/** Raise an IRQ.
2959	*
2960	* @param pDevIns The device instance.
2961	* @param pThis The shared VGA/VMSVGA state.
2962	* @param u32IrqStatus SVGA_IRQFLAG_* bits.
2963	* @thread FIFO or EMT.
2964	*/
2965	static void vmsvgaR3CmdBufRaiseIRQ(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t u32IrqStatus)
2966	{
2967	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
2968	AssertRC(rc);
2969
2970	if (pThis->svga.u32IrqMask & u32IrqStatus)
2971	{
2972	LogFunc(("Trigger interrupt with status %#x\n", u32IrqStatus));
2973	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
2974	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
2975	}
2976
2977	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
2978	}
2979
2980
2981	/** Allocate a command buffer structure.
2982	*
2983	* @param pCmdBufCtx The command buffer context which must allocate the buffer.
2984	* @return Pointer to the allocated command buffer structure.
2985	*/
2986	static PVMSVGACMDBUF vmsvgaR3CmdBufAlloc(PVMSVGACMDBUFCTX pCmdBufCtx)
2987	{
2988	if (!pCmdBufCtx)
2989	return NULL;
2990
2991	PVMSVGACMDBUF pCmdBuf = (PVMSVGACMDBUF)RTMemAllocZ(sizeof(*pCmdBuf));
2992	if (pCmdBuf)
2993	{
2994	// RT_ZERO(pCmdBuf->nodeBuffer);
2995	pCmdBuf->pCmdBufCtx = pCmdBufCtx;
2996	// pCmdBuf->GCPhysCB = 0;
2997	// RT_ZERO(pCmdBuf->hdr);
2998	// pCmdBuf->pvCommands = NULL;
2999	}
3000
3001	return pCmdBuf;
3002	}
3003
3004
3005	/** Free a command buffer structure.
3006	*
3007	* @param pCmdBuf The command buffer pointer.
3008	*/
3009	static void vmsvgaR3CmdBufFree(PVMSVGACMDBUF pCmdBuf)
3010	{
3011	if (pCmdBuf)
3012	RTMemFree(pCmdBuf->pvCommands);
3013	RTMemFree(pCmdBuf);
3014	}
3015
3016
3017	/** Initialize a command buffer context.
3018	*
3019	* @param pCmdBufCtx The command buffer context.
3020	*/
3021	static void vmsvgaR3CmdBufCtxInit(PVMSVGACMDBUFCTX pCmdBufCtx)
3022	{
3023	RTListInit(&pCmdBufCtx->listSubmitted);
3024	pCmdBufCtx->cSubmitted = 0;
3025	}
3026
3027
3028	/** Destroy a command buffer context.
3029	*
3030	* @param pCmdBufCtx The command buffer context pointer.
3031	*/
3032	static void vmsvgaR3CmdBufCtxTerm(PVMSVGACMDBUFCTX pCmdBufCtx)
3033	{
3034	if (!pCmdBufCtx)
3035	return;
3036
3037	if (pCmdBufCtx->listSubmitted.pNext)
3038	{
3039	/* If the list has been initialized. */
3040	PVMSVGACMDBUF pIter, pNext;
3041	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3042	{
3043	RTListNodeRemove(&pIter->nodeBuffer);
3044	--pCmdBufCtx->cSubmitted;
3045	vmsvgaR3CmdBufFree(pIter);
3046	}
3047	}
3048	Assert(pCmdBufCtx->cSubmitted == 0);
3049	pCmdBufCtx->cSubmitted = 0;
3050	}
3051
3052
3053	/** Handles SVGA_DC_CMD_START_STOP_CONTEXT command.
3054	*
3055	* @param pSvgaR3State VMSVGA R3 state.
3056	* @param pCmd The command data.
3057	* @return SVGACBStatus code.
3058	* @thread EMT
3059	*/
3060	static SVGACBStatus vmsvgaR3CmdBufDCStartStop(PVMSVGAR3STATE pSvgaR3State, SVGADCCmdStartStop const *pCmd)
3061	{
3062	/* Create or destroy a regular command buffer context. */
3063	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3064	return SVGA_CB_STATUS_COMMAND_ERROR;
3065	RT_UNTRUSTED_VALIDATED_FENCE();
3066
3067	SVGACBStatus CBStatus = SVGA_CB_STATUS_COMPLETED;
3068
3069	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3070	AssertRC(rc);
3071	if (pCmd->enable)
3072	{
3073	pSvgaR3State->apCmdBufCtxs[pCmd->context] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
3074	if (pSvgaR3State->apCmdBufCtxs[pCmd->context])
3075	vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3076	else
3077	CBStatus = SVGA_CB_STATUS_QUEUE_FULL;
3078	}
3079	else
3080	{
3081	vmsvgaR3CmdBufCtxTerm(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3082	pSvgaR3State->apCmdBufCtxs[pCmd->context] = NULL;
3083	}
3084	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3085
3086	return CBStatus;
3087	}
3088
3089
3090	/** Handles SVGA_DC_CMD_PREEMPT command.
3091	*
3092	* @param pDevIns The device instance.
3093	* @param pSvgaR3State VMSVGA R3 state.
3094	* @param pCmd The command data.
3095	* @return SVGACBStatus code.
3096	* @thread EMT
3097	*/
3098	static SVGACBStatus vmsvgaR3CmdBufDCPreempt(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, SVGADCCmdPreempt const *pCmd)
3099	{
3100	/* Remove buffers from the processing queue of the specified context. */
3101	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3102	return SVGA_CB_STATUS_COMMAND_ERROR;
3103	RT_UNTRUSTED_VALIDATED_FENCE();
3104
3105	PVMSVGACMDBUFCTX const pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[pCmd->context];
3106	RTLISTANCHOR listPreempted;
3107
3108	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3109	AssertRC(rc);
3110	if (pCmd->ignoreIDZero)
3111	{
3112	RTListInit(&listPreempted);
3113
3114	PVMSVGACMDBUF pIter, pNext;
3115	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3116	{
3117	if (pIter->hdr.id == 0)
3118	continue;
3119
3120	RTListNodeRemove(&pIter->nodeBuffer);
3121	--pCmdBufCtx->cSubmitted;
3122	RTListAppend(&listPreempted, &pIter->nodeBuffer);
3123	}
3124	}
3125	else
3126	{
3127	RTListMove(&listPreempted, &pCmdBufCtx->listSubmitted);
3128	}
3129	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3130
3131	PVMSVGACMDBUF pIter, pNext;
3132	RTListForEachSafe(&listPreempted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3133	{
3134	RTListNodeRemove(&pIter->nodeBuffer);
3135	vmsvgaR3CmdBufWriteStatus(pDevIns, pIter->GCPhysCB, SVGA_CB_STATUS_PREEMPTED, 0);
3136	vmsvgaR3CmdBufFree(pIter);
3137	}
3138
3139	return SVGA_CB_STATUS_COMPLETED;
3140	}
3141
3142
3143	/** @def VMSVGA_INC_CMD_SIZE_BREAK
3144	* Increments the size of the command cbCmd by a_cbMore.
3145	* Checks that the command buffer has at least cbCmd bytes. Will break out of the switch if it doesn't.
3146	* Used by vmsvgaR3CmdBufProcessDC and vmsvgaR3CmdBufProcessCommands.
3147	*/
3148	#define VMSVGA_INC_CMD_SIZE_BREAK(a_cbMore) \
3149	if (1) { \
3150	cbCmd += (a_cbMore); \
3151	ASSERT_GUEST_MSG_STMT_BREAK(cbRemain >= cbCmd, ("size=%#x remain=%#zx\n", cbCmd, (size_t)cbRemain), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR); \
3152	RT_UNTRUSTED_VALIDATED_FENCE(); \
3153	} else do {} while (0)
3154
3155
3156	/** Processes Device Context command buffer.
3157	*
3158	* @param pDevIns The device instance.
3159	* @param pSvgaR3State VMSVGA R3 state.
3160	* @param pvCommands Pointer to the command buffer.
3161	* @param cbCommands Size of the command buffer.
3162	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3163	* @return SVGACBStatus code.
3164	* @thread EMT
3165	*/
3166	static SVGACBStatus vmsvgaR3CmdBufProcessDC(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd)
3167	{
3168	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3169
3170	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3171	uint32_t cbRemain = cbCommands;
3172	while (cbRemain)
3173	{
3174	/* Command identifier is a 32 bit value. */
3175	if (cbRemain < sizeof(uint32_t))
3176	{
3177	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3178	break;
3179	}
3180
3181	/* Fetch the command id. */
3182	uint32_t const cmdId = (uint32_t )pu8Cmd;
3183	uint32_t cbCmd = sizeof(uint32_t);
3184	switch (cmdId)
3185	{
3186	case SVGA_DC_CMD_NOP:
3187	{
3188	/* NOP */
3189	break;
3190	}
3191
3192	case SVGA_DC_CMD_START_STOP_CONTEXT:
3193	{
3194	SVGADCCmdStartStop pCmd = (SVGADCCmdStartStop )&pu8Cmd[cbCmd];
3195	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3196	CBstatus = vmsvgaR3CmdBufDCStartStop(pSvgaR3State, pCmd);
3197	break;
3198	}
3199
3200	case SVGA_DC_CMD_PREEMPT:
3201	{
3202	SVGADCCmdPreempt pCmd = (SVGADCCmdPreempt )&pu8Cmd[cbCmd];
3203	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3204	CBstatus = vmsvgaR3CmdBufDCPreempt(pDevIns, pSvgaR3State, pCmd);
3205	break;
3206	}
3207
3208	default:
3209	{
3210	/* Unsupported command. */
3211	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3212	break;
3213	}
3214	}
3215
3216	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3217	break;
3218
3219	pu8Cmd += cbCmd;
3220	cbRemain -= cbCmd;
3221	}
3222
3223	Assert(cbRemain <= cbCommands);
3224	*poffNextCmd = cbCommands - cbRemain;
3225	return CBstatus;
3226	}
3227
3228
3229	/** Submits a device context command buffer for synchronous processing.
3230	*
3231	* @param pDevIns The device instance.
3232	* @param pThisCC The VGA/VMSVGA state for the current context.
3233	* @param ppCmdBuf Pointer to the command buffer pointer.
3234	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3235	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3236	* @return SVGACBStatus code.
3237	* @thread EMT
3238	*/
3239	static SVGACBStatus vmsvgaR3CmdBufSubmitDC(PPDMDEVINS pDevIns, PVGASTATECC pThisCC, PVMSVGACMDBUF ppCmdBuf, uint32_t poffNextCmd)
3240	{
3241	/* Synchronously process the device context commands. */
3242	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3243	return vmsvgaR3CmdBufProcessDC(pDevIns, pSvgaR3State, (ppCmdBuf)->pvCommands, (ppCmdBuf)->hdr.length, poffNextCmd);
3244	}
3245
3246	/** Submits a command buffer for asynchronous processing by the FIFO thread.
3247	*
3248	* @param pDevIns The device instance.
3249	* @param pThis The shared VGA/VMSVGA state.
3250	* @param pThisCC The VGA/VMSVGA state for the current context.
3251	* @param ppCmdBuf Pointer to the command buffer pointer.
3252	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3253	* @return SVGACBStatus code.
3254	* @thread EMT
3255	*/
3256	static SVGACBStatus vmsvgaR3CmdBufSubmitCtx(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf)
3257	{
3258	/* Command buffer submission. */
3259	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3260
3261	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3262
3263	PVMSVGACMDBUF const pCmdBuf = *ppCmdBuf;
3264	PVMSVGACMDBUFCTX const pCmdBufCtx = pCmdBuf->pCmdBufCtx;
3265
3266	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3267	AssertRC(rc);
3268
3269	if (RT_LIKELY(pCmdBufCtx->cSubmitted < SVGA_CB_MAX_QUEUED_PER_CONTEXT))
3270	{
3271	RTListAppend(&pCmdBufCtx->listSubmitted, &pCmdBuf->nodeBuffer);
3272	++pCmdBufCtx->cSubmitted;
3273	ppCmdBuf = NULL; / Consume the buffer. */
3274	ASMAtomicWriteU32(&pThisCC->svga.pSvgaR3State->fCmdBuf, 1);
3275	}
3276	else
3277	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3278
3279	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3280
3281	/* Inform the FIFO thread. */
3282	if (*ppCmdBuf == NULL)
3283	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3284
3285	return CBstatus;
3286	}
3287
3288
3289	/** SVGA_REG_COMMAND_LOW write handler.
3290	* Submits a command buffer to the FIFO thread or processes a device context command.
3291	*
3292	* @param pDevIns The device instance.
3293	* @param pThis The shared VGA/VMSVGA state.
3294	* @param pThisCC The VGA/VMSVGA state for the current context.
3295	* @param GCPhysCB Guest physical address of the command buffer header.
3296	* @param CBCtx Context the command buffer is submitted to.
3297	* @thread EMT
3298	*/
3299	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx)
3300	{
3301	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3302
3303	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3304	uint32_t offNextCmd = 0;
3305	uint32_t fIRQ = 0;
3306
3307	/* Get the context if the device has the capability. */
3308	PVMSVGACMDBUFCTX pCmdBufCtx = NULL;
3309	if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
3310	{
3311	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3312	pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[CBCtx];
3313	else if (CBCtx == SVGA_CB_CONTEXT_DEVICE)
3314	pCmdBufCtx = &pSvgaR3State->CmdBufCtxDC;
3315	RT_UNTRUSTED_VALIDATED_FENCE();
3316	}
3317
3318	/* Allocate a new command buffer. */
3319	PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pCmdBufCtx);
3320	if (RT_LIKELY(pCmdBuf))
3321	{
3322	pCmdBuf->GCPhysCB = GCPhysCB;
3323
3324	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCB, &pCmdBuf->hdr, sizeof(pCmdBuf->hdr));
3325	if (RT_SUCCESS(rc))
3326	{
3327	/* Verify the command buffer header. */
3328	if (RT_LIKELY( pCmdBuf->hdr.status == SVGA_CB_STATUS_NONE
3329	&& (pCmdBuf->hdr.flags & ~(SVGA_CB_FLAG_NO_IRQ \| SVGA_CB_FLAG_DX_CONTEXT)) == 0 /* No unexpected flags. */
3330	&& pCmdBuf->hdr.length <= SVGA_CB_MAX_SIZE))
3331	{
3332	RT_UNTRUSTED_VALIDATED_FENCE();
3333
3334	/* Read the command buffer content. */
3335	pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
3336	if (pCmdBuf->pvCommands)
3337	{
3338	RTGCPHYS const GCPhysCmd = (RTGCPHYS)pCmdBuf->hdr.ptr.pa;
3339	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
3340	if (RT_SUCCESS(rc))
3341	{
3342	/* Submit the buffer. Device context buffers will be processed synchronously. */
3343	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3344	/* This usually processes the CB async and sets pCmbBuf to NULL. */
3345	CBstatus = vmsvgaR3CmdBufSubmitCtx(pDevIns, pThis, pThisCC, &pCmdBuf);
3346	else
3347	CBstatus = vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
3348	}
3349	else
3350	{
3351	ASSERT_GUEST_MSG_FAILED(("Failed to read commands at %RGp\n", GCPhysCmd));
3352	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3353	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3354	}
3355	}
3356	else
3357	{
3358	/* No memory for commands. */
3359	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3360	}
3361	}
3362	else
3363	{
3364	ASSERT_GUEST_MSG_FAILED(("Invalid buffer header\n"));
3365	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3366	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3367	}
3368	}
3369	else
3370	{
3371	LogFunc(("Failed to read buffer header at %RGp\n", GCPhysCB));
3372	ASSERT_GUEST_FAILED();
3373	/* Do not attempt to write the status. */
3374	}
3375
3376	/* Free the buffer if pfnCmdBufSubmit did not consume it. */
3377	vmsvgaR3CmdBufFree(pCmdBuf);
3378	}
3379	else
3380	{
3381	LogFunc(("Can't allocate buffer for context id %#x\n", CBCtx));
3382	ASSERT_GUEST_FAILED();
3383	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3384	}
3385
3386	if (CBstatus != SVGA_CB_STATUS_NONE)
3387	{
3388	LogFunc(("Write status %#x, offNextCmd %#x (of %#x), fIRQ %#x\n", CBstatus, offNextCmd, pCmdBuf ? pCmdBuf->hdr.length : 0, fIRQ));
3389	vmsvgaR3CmdBufWriteStatus(pDevIns, GCPhysCB, CBstatus, offNextCmd);
3390	if (fIRQ)
3391	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, fIRQ);
3392	}
3393	}
3394
3395
3396	/** Checks if there are some buffers to be processed.
3397	*
3398	* @param pThisCC The VGA/VMSVGA state for the current context.
3399	* @return true if buffers must be processed.
3400	* @thread FIFO
3401	*/
3402	static bool vmsvgaR3CmdBufHasWork(PVGASTATECC pThisCC)
3403	{
3404	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3405	return RT_BOOL(ASMAtomicReadU32(&pSvgaR3State->fCmdBuf));
3406	}
3407
3408
3409	/** Processes a command buffer.
3410	*
3411	* @param pDevIns The device instance.
3412	* @param pThis The shared VGA/VMSVGA state.
3413	* @param pThisCC The VGA/VMSVGA state for the current context.
3414	* @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
3415	* @param pvCommands Pointer to the command buffer.
3416	* @param cbCommands Size of the command buffer.
3417	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3418	* @param pu32IrqStatus Where to store SVGA_IRQFLAG_ if the IRQ is generated by the last command in the buffer.
3419	* @return SVGACBStatus code.
3420	* @thread FIFO
3421	*/
3422	static SVGACBStatus vmsvgaR3CmdBufProcessCommands(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd, uint32_t *pu32IrqStatus)
3423	{
3424	# ifndef VBOX_WITH_VMSVGA3D
3425	RT_NOREF(idDXContext);
3426	# endif
3427	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3428	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3429
3430	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3431
3432	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3433	uint32_t cbRemain = cbCommands;
3434	while (cbRemain)
3435	{
3436	/* Command identifier is a 32 bit value. */
3437	if (cbRemain < sizeof(uint32_t))
3438	{
3439	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3440	break;
3441	}
3442
3443	/* Fetch the command id.
3444	* 'cmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
3445	* warning. Because we support some obsolete and deprecated commands, which are not included in
3446	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
3447	*/
3448	uint32_t const cmdId = (uint32_t )pu8Cmd;
3449	uint32_t cbCmd = sizeof(uint32_t);
3450
3451	LogFlowFunc(("[cid=%d] %s %d\n", (int32_t)idDXContext, vmsvgaR3FifoCmdToString(cmdId), cmdId));
3452	# ifdef LOG_ENABLED
3453	# ifdef VBOX_WITH_VMSVGA3D
3454	if (SVGA_3D_CMD_BASE <= cmdId && cmdId < SVGA_3D_CMD_MAX)
3455	{
3456	SVGA3dCmdHeader const header = (SVGA3dCmdHeader )pu8Cmd;
3457	svga_dump_command(cmdId, (uint8_t *)&header[1], header->size);
3458	}
3459	else if (cmdId == SVGA_CMD_FENCE)
3460	{
3461	Log7(("\tSVGA_CMD_FENCE\n"));
3462	Log7(("\t\t0x%08x\n", ((uint32_t *)pu8Cmd)[1]));
3463	}
3464	# endif
3465	# endif
3466
3467	/* At the end of the switch cbCmd is equal to the total length of the command including the cmdId.
3468	* I.e. pu8Cmd + cbCmd must point to the next command.
3469	* However if CBstatus is set to anything but SVGA_CB_STATUS_COMPLETED in the switch, then
3470	* the cbCmd value is ignored (and pu8Cmd still points to the failed command).
3471	*/
3472	/** @todo This code is very similar to the FIFO loop command processing. Think about merging. */
3473	switch (cmdId)
3474	{
3475	case SVGA_CMD_INVALID_CMD:
3476	{
3477	/* Nothing to do. */
3478	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdInvalidCmd);
3479	break;
3480	}
3481
3482	case SVGA_CMD_FENCE:
3483	{
3484	SVGAFifoCmdFence pCmd = (SVGAFifoCmdFence )&pu8Cmd[cbCmd];
3485	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3486	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdFence);
3487	Log(("SVGA_CMD_FENCE %#x\n", pCmd->fence));
3488
3489	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3490	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3491	{
3492	pFIFO[SVGA_FIFO_FENCE] = pCmd->fence;
3493
3494	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3495	{
3496	Log(("any fence irq\n"));
3497	*pu32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3498	}
3499	else if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3500	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3501	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmd->fence)
3502	{
3503	Log(("fence goal reached irq (fence=%#x)\n", pCmd->fence));
3504	*pu32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3505	}
3506	}
3507	else
3508	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3509	break;
3510	}
3511
3512	case SVGA_CMD_UPDATE:
3513	{
3514	SVGAFifoCmdUpdate pCmd = (SVGAFifoCmdUpdate )&pu8Cmd[cbCmd];
3515	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3516	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
3517	break;
3518	}
3519
3520	case SVGA_CMD_UPDATE_VERBOSE:
3521	{
3522	SVGAFifoCmdUpdateVerbose pCmd = (SVGAFifoCmdUpdateVerbose )&pu8Cmd[cbCmd];
3523	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3524	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
3525	break;
3526	}
3527
3528	case SVGA_CMD_DEFINE_CURSOR:
3529	{
3530	/* Followed by bitmap data. */
3531	SVGAFifoCmdDefineCursor pCmd = (SVGAFifoCmdDefineCursor )&pu8Cmd[cbCmd];
3532	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3533
3534	/* Figure out the size of the bitmap data. */
3535	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3536	ASSERT_GUEST_STMT_BREAK(pCmd->andMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3537	ASSERT_GUEST_STMT_BREAK(pCmd->xorMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3538	RT_UNTRUSTED_VALIDATED_FENCE();
3539
3540	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
3541	uint32_t const cbAndMask = cbAndLine * pCmd->height;
3542	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
3543	uint32_t const cbXorMask = cbXorLine * pCmd->height;
3544
3545	VMSVGA_INC_CMD_SIZE_BREAK(cbAndMask + cbXorMask);
3546	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
3547	break;
3548	}
3549
3550	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3551	{
3552	/* Followed by bitmap data. */
3553	SVGAFifoCmdDefineAlphaCursor pCmd = (SVGAFifoCmdDefineAlphaCursor )&pu8Cmd[cbCmd];
3554	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3555
3556	/* Figure out the size of the bitmap data. */
3557	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3558
3559	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->width * pCmd->height * sizeof(uint32_t)); /* 32-bit BRGA format */
3560	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
3561	break;
3562	}
3563
3564	case SVGA_CMD_MOVE_CURSOR:
3565	{
3566	/* Deprecated; there should be no driver which requires this command. However, if
3567	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3568	* alignment.
3569	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3570	*/
3571	SVGAFifoCmdMoveCursor pCmd = (SVGAFifoCmdMoveCursor )&pu8Cmd[cbCmd];
3572	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3573	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
3574	break;
3575	}
3576
3577	case SVGA_CMD_DISPLAY_CURSOR:
3578	{
3579	/* Deprecated; there should be no driver which requires this command. However, if
3580	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3581	* alignment.
3582	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3583	*/
3584	SVGAFifoCmdDisplayCursor pCmd = (SVGAFifoCmdDisplayCursor )&pu8Cmd[cbCmd];
3585	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3586	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
3587	break;
3588	}
3589
3590	case SVGA_CMD_RECT_FILL:
3591	{
3592	SVGAFifoCmdRectFill pCmd = (SVGAFifoCmdRectFill )&pu8Cmd[cbCmd];
3593	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3594	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
3595	break;
3596	}
3597
3598	case SVGA_CMD_RECT_COPY:
3599	{
3600	SVGAFifoCmdRectCopy pCmd = (SVGAFifoCmdRectCopy )&pu8Cmd[cbCmd];
3601	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3602	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
3603	break;
3604	}
3605
3606	case SVGA_CMD_RECT_ROP_COPY:
3607	{
3608	SVGAFifoCmdRectRopCopy pCmd = (SVGAFifoCmdRectRopCopy )&pu8Cmd[cbCmd];
3609	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3610	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
3611	break;
3612	}
3613
3614	case SVGA_CMD_ESCAPE:
3615	{
3616	/* Followed by 'size' bytes of data. */
3617	SVGAFifoCmdEscape pCmd = (SVGAFifoCmdEscape )&pu8Cmd[cbCmd];
3618	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3619
3620	ASSERT_GUEST_STMT_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3621	RT_UNTRUSTED_VALIDATED_FENCE();
3622
3623	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->size);
3624	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
3625	break;
3626	}
3627	# ifdef VBOX_WITH_VMSVGA3D
3628	case SVGA_CMD_DEFINE_GMR2:
3629	{
3630	SVGAFifoCmdDefineGMR2 pCmd = (SVGAFifoCmdDefineGMR2 )&pu8Cmd[cbCmd];
3631	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3632	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
3633	break;
3634	}
3635
3636	case SVGA_CMD_REMAP_GMR2:
3637	{
3638	/* Followed by page descriptors or guest ptr. */
3639	SVGAFifoCmdRemapGMR2 pCmd = (SVGAFifoCmdRemapGMR2 )&pu8Cmd[cbCmd];
3640	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3641
3642	/* Calculate the size of what comes after next and fetch it. */
3643	uint32_t cbMore = 0;
3644	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3645	cbMore = sizeof(SVGAGuestPtr);
3646	else
3647	{
3648	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3649	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3650	{
3651	cbMore = cbPageDesc;
3652	pCmd->numPages = 1;
3653	}
3654	else
3655	{
3656	ASSERT_GUEST_STMT_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3657	cbMore = cbPageDesc * pCmd->numPages;
3658	}
3659	}
3660	VMSVGA_INC_CMD_SIZE_BREAK(cbMore);
3661	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
3662	# ifdef DEBUG_GMR_ACCESS
3663	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
3664	# endif
3665	break;
3666	}
3667	# endif /* VBOX_WITH_VMSVGA3D */
3668	case SVGA_CMD_DEFINE_SCREEN:
3669	{
3670	/* The size of this command is specified by the guest and depends on capabilities. */
3671	SVGAFifoCmdDefineScreen pCmd = (SVGAFifoCmdDefineScreen )&pu8Cmd[cbCmd];
3672	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(pCmd->screen.structSize));
3673	ASSERT_GUEST_STMT_BREAK(pCmd->screen.structSize < pThis->svga.cbFIFO, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3674	RT_UNTRUSTED_VALIDATED_FENCE();
3675
3676	VMSVGA_INC_CMD_SIZE_BREAK(RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize) - sizeof(pCmd->screen.structSize));
3677	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
3678	break;
3679	}
3680
3681	case SVGA_CMD_DESTROY_SCREEN:
3682	{
3683	SVGAFifoCmdDestroyScreen pCmd = (SVGAFifoCmdDestroyScreen )&pu8Cmd[cbCmd];
3684	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3685	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
3686	break;
3687	}
3688
3689	case SVGA_CMD_DEFINE_GMRFB:
3690	{
3691	SVGAFifoCmdDefineGMRFB pCmd = (SVGAFifoCmdDefineGMRFB )&pu8Cmd[cbCmd];
3692	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3693	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
3694	break;
3695	}
3696
3697	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3698	{
3699	SVGAFifoCmdBlitGMRFBToScreen pCmd = (SVGAFifoCmdBlitGMRFBToScreen )&pu8Cmd[cbCmd];
3700	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3701	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
3702	break;
3703	}
3704
3705	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3706	{
3707	SVGAFifoCmdBlitScreenToGMRFB pCmd = (SVGAFifoCmdBlitScreenToGMRFB )&pu8Cmd[cbCmd];
3708	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3709	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
3710	break;
3711	}
3712
3713	case SVGA_CMD_ANNOTATION_FILL:
3714	{
3715	SVGAFifoCmdAnnotationFill pCmd = (SVGAFifoCmdAnnotationFill )&pu8Cmd[cbCmd];
3716	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3717	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
3718	break;
3719	}
3720
3721	case SVGA_CMD_ANNOTATION_COPY:
3722	{
3723	SVGAFifoCmdAnnotationCopy pCmd = (SVGAFifoCmdAnnotationCopy )&pu8Cmd[cbCmd];
3724	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3725	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
3726	break;
3727	}
3728
3729	default:
3730	{
3731	# ifdef VBOX_WITH_VMSVGA3D
3732	if ( cmdId >= SVGA_3D_CMD_BASE
3733	&& cmdId < SVGA_3D_CMD_MAX)
3734	{
3735	RT_UNTRUSTED_VALIDATED_FENCE();
3736
3737	/* All 3d commands start with a common header, which defines the identifier and the size
3738	* of the command. The identifier has been already read. Fetch the size.
3739	*/
3740	uint32_t const pcbMore = (uint32_t const )&pu8Cmd[cbCmd];
3741	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pcbMore));
3742	VMSVGA_INC_CMD_SIZE_BREAK(*pcbMore);
3743	if (RT_LIKELY(pThis->svga.f3DEnabled))
3744	{ /* likely */ }
3745	else
3746	{
3747	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", cmdId));
3748	break;
3749	}
3750
3751	/* Command data begins after the 32 bit command length. */
3752	int rc = vmsvgaR3Process3dCmd(pThis, pThisCC, idDXContext, (SVGAFifo3dCmdId)cmdId, *pcbMore, pcbMore + 1);
3753	if (RT_SUCCESS(rc))
3754	{ /* likely */ }
3755	else
3756	{
3757	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3758	break;
3759	}
3760	}
3761	else
3762	# endif /* VBOX_WITH_VMSVGA3D */
3763	{
3764	/* Unsupported command. */
3765	STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
3766	ASSERT_GUEST_MSG_FAILED(("cmdId=%d\n", cmdId));
3767	LogRelMax(16, ("VMSVGA: unsupported command %d\n", cmdId));
3768	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3769	break;
3770	}
3771	}
3772	}
3773
3774	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3775	break;
3776
3777	pu8Cmd += cbCmd;
3778	cbRemain -= cbCmd;
3779
3780	/* If this is not the last command in the buffer, then generate IRQ, if required.
3781	* This avoids a double call to vmsvgaR3CmdBufRaiseIRQ if FENCE is the last command
3782	* in the buffer (usually the case).
3783	*/
3784	if (RT_LIKELY(!(cbRemain && *pu32IrqStatus)))
3785	{ /* likely */ }
3786	else
3787	{
3788	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, *pu32IrqStatus);
3789	*pu32IrqStatus = 0;
3790	}
3791	}
3792
3793	Assert(cbRemain <= cbCommands);
3794	*poffNextCmd = cbCommands - cbRemain;
3795	return CBstatus;
3796	}
3797
3798
3799	/** Process command buffers.
3800	*
3801	* @param pDevIns The device instance.
3802	* @param pThis The shared VGA/VMSVGA state.
3803	* @param pThisCC The VGA/VMSVGA state for the current context.
3804	* @param pThread Handle of the FIFO thread.
3805	* @thread FIFO
3806	*/
3807	static void vmsvgaR3CmdBufProcessBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PPDMTHREAD pThread)
3808	{
3809	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3810
3811	for (;;)
3812	{
3813	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3814	break;
3815
3816	/* See if there is a submitted buffer. */
3817	PVMSVGACMDBUF pCmdBuf = NULL;
3818
3819	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3820	AssertRC(rc);
3821
3822	/* It seems that a higher queue index has a higher priority.
3823	* See SVGACBContext in svga_reg.h from latest vmwgfx Linux driver.
3824	*/
3825	for (unsigned i = RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs); i > 0; --i)
3826	{
3827	PVMSVGACMDBUFCTX pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[i - 1];
3828	if (pCmdBufCtx)
3829	{
3830	pCmdBuf = RTListRemoveFirst(&pCmdBufCtx->listSubmitted, VMSVGACMDBUF, nodeBuffer);
3831	if (pCmdBuf)
3832	{
3833	Assert(pCmdBufCtx->cSubmitted > 0);
3834	--pCmdBufCtx->cSubmitted;
3835	break;
3836	}
3837	}
3838	}
3839
3840	if (!pCmdBuf)
3841	{
3842	ASMAtomicWriteU32(&pSvgaR3State->fCmdBuf, 0);
3843	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3844	break;
3845	}
3846
3847	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3848
3849	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3850	uint32_t offNextCmd = 0;
3851	uint32_t u32IrqStatus = 0;
3852	uint32_t const idDXContext = RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_DX_CONTEXT)
3853	? pCmdBuf->hdr.dxContext
3854	: SVGA3D_INVALID_ID;
3855	/* Process one buffer. */
3856	CBstatus = vmsvgaR3CmdBufProcessCommands(pDevIns, pThis, pThisCC, idDXContext, pCmdBuf->pvCommands, pCmdBuf->hdr.length, &offNextCmd, &u32IrqStatus);
3857
3858	if (!RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_NO_IRQ))
3859	u32IrqStatus \|= SVGA_IRQFLAG_COMMAND_BUFFER;
3860	if (CBstatus == SVGA_CB_STATUS_COMMAND_ERROR)
3861	u32IrqStatus \|= SVGA_IRQFLAG_ERROR;
3862
3863	vmsvgaR3CmdBufWriteStatus(pDevIns, pCmdBuf->GCPhysCB, CBstatus, offNextCmd);
3864	if (u32IrqStatus)
3865	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, u32IrqStatus);
3866
3867	vmsvgaR3CmdBufFree(pCmdBuf);
3868	}
3869	}
3870
3871
3872	/**
3873	* Worker for vmsvgaR3FifoThread that handles an external command.
3874	*
3875	* @param pDevIns The device instance.
3876	* @param pThis The shared VGA/VMSVGA instance data.
3877	* @param pThisCC The VGA/VMSVGA state for ring-3.
3878	*/
3879	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3880	{
3881	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
3882	switch (pThis->svga.u8FIFOExtCommand)
3883	{
3884	case VMSVGA_FIFO_EXTCMD_RESET:
3885	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
3886	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3887
3888	vmsvgaR3ResetScreens(pThis, pThisCC);
3889	# ifdef VBOX_WITH_VMSVGA3D
3890	if (pThis->svga.f3DEnabled)
3891	{
3892	/* The 3d subsystem must be reset from the fifo thread. */
3893	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3894	pSVGAState->pFuncs3D->pfnReset(pThisCC);
3895	}
3896	# endif
3897	break;
3898
3899	case VMSVGA_FIFO_EXTCMD_POWEROFF:
3900	Log(("vmsvgaR3FifoLoop: power off.\n"));
3901	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3902
3903	/* The screens must be reset on the FIFO thread, because they may use 3D resources. */
3904	vmsvgaR3ResetScreens(pThis, pThisCC);
3905	break;
3906
3907	case VMSVGA_FIFO_EXTCMD_TERMINATE:
3908	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
3909	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3910	# ifdef VBOX_WITH_VMSVGA3D
3911	if (pThis->svga.f3DEnabled)
3912	{
3913	/* The 3d subsystem must be shut down from the fifo thread. */
3914	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3915	pSVGAState->pFuncs3D->pfnTerminate(pThisCC);
3916	}
3917	# endif
3918	break;
3919
3920	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
3921	{
3922	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
3923	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
3924	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
3925	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
3926	# ifdef VBOX_WITH_VMSVGA3D
3927	if (pThis->svga.f3DEnabled)
3928	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
3929	# endif
3930	break;
3931	}
3932
3933	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
3934	{
3935	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
3936	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
3937	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
3938	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3939	# ifdef VBOX_WITH_VMSVGA3D
3940	if (pThis->svga.f3DEnabled)
3941	{
3942	/* The following RT_OS_DARWIN code was in vmsvga3dLoadExec and therefore must be executed before each vmsvga3dLoadExec invocation. */
3943	# ifndef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA.cpp */
3944	/* Must initialize now as the recreation calls below rely on an initialized 3d subsystem. */
3945	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3946	pSVGAState->pFuncs3D->pfnPowerOn(pDevIns, pThis, pThisCC);
3947	# endif
3948
3949	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3950	}
3951	# endif
3952	break;
3953	}
3954
3955	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
3956	{
3957	# ifdef VBOX_WITH_VMSVGA3D
3958	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
3959	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
3960	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
3961	# endif
3962	break;
3963	}
3964
3965
3966	default:
3967	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
3968	break;
3969	}
3970
3971	/*
3972	* Signal the end of the external command.
3973	*/
3974	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3975	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
3976	ASMMemoryFence(); /* paranoia^2 */
3977	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
3978	AssertLogRelRC(rc);
3979	}
3980
3981	/**
3982	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
3983	* doing a job on the FIFO thread (even when it's officially suspended).
3984	*
3985	* @returns VBox status code (fully asserted).
3986	* @param pDevIns The device instance.
3987	* @param pThis The shared VGA/VMSVGA instance data.
3988	* @param pThisCC The VGA/VMSVGA state for ring-3.
3989	* @param uExtCmd The command to execute on the FIFO thread.
3990	* @param pvParam Pointer to command parameters.
3991	* @param cMsWait The time to wait for the command, given in
3992	* milliseconds.
3993	*/
3994	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
3995	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3996	{
3997	Assert(cMsWait >= RT_MS_1SEC * 5);
3998	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3999	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
4000
4001	int rc;
4002	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
4003	PDMTHREADSTATE enmState = pThread->enmState;
4004	if (enmState == PDMTHREADSTATE_SUSPENDED)
4005	{
4006	/*
4007	* The thread is suspended, we have to temporarily wake it up so it can
4008	* perform the task.
4009	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
4010	*/
4011	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
4012	/* Post the request. */
4013	pThis->svga.fFifoExtCommandWakeup = true;
4014	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4015	pThis->svga.u8FIFOExtCommand = uExtCmd;
4016	ASMMemoryFence(); /* paranoia^3 */
4017
4018	/* Resume the thread. */
4019	rc = PDMDevHlpThreadResume(pDevIns, pThread);
4020	AssertLogRelRC(rc);
4021	if (RT_SUCCESS(rc))
4022	{
4023	/* Wait. Take care in case the semaphore was already posted (same as below). */
4024	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4025	if ( rc == VINF_SUCCESS
4026	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4027	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4028	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4029	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4030
4031	/* suspend the thread */
4032	pThis->svga.fFifoExtCommandWakeup = false;
4033	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
4034	AssertLogRelRC(rc2);
4035	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
4036	rc = rc2;
4037	}
4038	pThis->svga.fFifoExtCommandWakeup = false;
4039	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4040	}
4041	else if (enmState == PDMTHREADSTATE_RUNNING)
4042	{
4043	/*
4044	* The thread is running, should only happen during reset and vmsvga3dsfc.
4045	* We ASSUME not racing code here, both wrt thread state and ext commands.
4046	*/
4047	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
4048	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_POWEROFF);
4049
4050	/* Post the request. */
4051	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4052	pThis->svga.u8FIFOExtCommand = uExtCmd;
4053	ASMMemoryFence(); /* paranoia^2 */
4054	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4055	AssertLogRelRC(rc);
4056
4057	/* Wait. Take care in case the semaphore was already posted (same as above). */
4058	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4059	if ( rc == VINF_SUCCESS
4060	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4061	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
4062	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4063	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4064
4065	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4066	}
4067	else
4068	{
4069	/*
4070	* Something is wrong with the thread!
4071	*/
4072	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
4073	rc = VERR_INVALID_STATE;
4074	}
4075	return rc;
4076	}
4077
4078
4079	/**
4080	* Marks the FIFO non-busy, notifying any waiting EMTs.
4081	*
4082	* @param pDevIns The device instance.
4083	* @param pThis The shared VGA/VMSVGA instance data.
4084	* @param pThisCC The VGA/VMSVGA state for ring-3.
4085	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
4086	* @param offFifoMin The start byte offset of the command FIFO.
4087	*/
4088	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
4089	{
4090	ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO \| VMSVGA_BUSY_F_EMT_FORCE));
4091	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4092	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
4093
4094	/* Wake up any waiting EMTs. */
4095	if (pSVGAState->cBusyDelayedEmts > 0)
4096	{
4097	# ifdef VMSVGA_USE_EMT_HALT_CODE
4098	PVM pVM = PDMDevHlpGetVM(pDevIns);
4099	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
4100	if (idCpu != NIL_VMCPUID)
4101	{
4102	VMR3NotifyCpuDeviceReady(pVM, idCpu);
4103	while (idCpu-- > 0)
4104	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
4105	VMR3NotifyCpuDeviceReady(pVM, idCpu);
4106	}
4107	# else
4108	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
4109	AssertRC(rc2);
4110	# endif
4111	}
4112	}
4113
4114	/**
4115	* Reads (more) payload into the command buffer.
4116	*
4117	* @returns pbBounceBuf on success
4118	* @retval (void *)1 if the thread was requested to stop.
4119	* @retval NULL on FIFO error.
4120	*
4121	* @param cbPayloadReq The number of bytes of payload requested.
4122	* @param pFIFO The FIFO.
4123	* @param offCurrentCmd The FIFO byte offset of the current command.
4124	* @param offFifoMin The start byte offset of the command FIFO.
4125	* @param offFifoMax The end byte offset of the command FIFO.
4126	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
4127	* always sufficient size.
4128	* @param pcbAlreadyRead How much payload we've already read into the bounce
4129	* buffer. (We will NEVER re-read anything.)
4130	* @param pThread The calling PDM thread handle.
4131	* @param pThis The shared VGA/VMSVGA instance data.
4132	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
4133	* statistics collection.
4134	* @param pDevIns The device instance.
4135	*/
4136	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
4137	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
4138	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
4139	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
4140	{
4141	Assert(pbBounceBuf);
4142	Assert(pcbAlreadyRead);
4143	Assert(offFifoMin < offFifoMax);
4144	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
4145	Assert(offFifoMax <= pThis->svga.cbFIFO);
4146
4147	/*
4148	* Check if the requested payload size has already been satisfied .
4149	* .
4150	* When called to read more, the caller is responsible for making sure the .
4151	* new command size (cbRequsted) never is smaller than what has already .
4152	* been read.
4153	*/
4154	uint32_t cbAlreadyRead = *pcbAlreadyRead;
4155	if (cbPayloadReq <= cbAlreadyRead)
4156	{
4157	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
4158	return pbBounceBuf;
4159	}
4160
4161	/*
4162	* Commands bigger than the fifo buffer are invalid.
4163	*/
4164	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
4165	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
4166	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
4167	NULL);
4168
4169	/*
4170	* Move offCurrentCmd past the command dword.
4171	*/
4172	offCurrentCmd += sizeof(uint32_t);
4173	if (offCurrentCmd >= offFifoMax)
4174	offCurrentCmd = offFifoMin;
4175
4176	/*
4177	* Do we have sufficient payload data available already?
4178	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
4179	*/
4180	uint32_t cbAfter, cbBefore;
4181	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4182	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4183	if (offNextCmd >= offCurrentCmd)
4184	{
4185	if (RT_LIKELY(offNextCmd < offFifoMax))
4186	cbAfter = offNextCmd - offCurrentCmd;
4187	else
4188	{
4189	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4190	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4191	offNextCmd, offFifoMin, offFifoMax));
4192	cbAfter = offFifoMax - offCurrentCmd;
4193	}
4194	cbBefore = 0;
4195	}
4196	else
4197	{
4198	cbAfter = offFifoMax - offCurrentCmd;
4199	if (offNextCmd >= offFifoMin)
4200	cbBefore = offNextCmd - offFifoMin;
4201	else
4202	{
4203	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4204	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4205	offNextCmd, offFifoMin, offFifoMax));
4206	cbBefore = 0;
4207	}
4208	}
4209	if (cbAfter + cbBefore < cbPayloadReq)
4210	{
4211	/*
4212	* Insufficient, must wait for it to arrive.
4213	*/
4214	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
4215	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
4216	for (uint32_t i = 0;; i++)
4217	{
4218	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4219	{
4220	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4221	return (void *)(uintptr_t)1;
4222	}
4223	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
4224	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
4225
4226	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
4227
4228	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4229	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4230	if (offNextCmd >= offCurrentCmd)
4231	{
4232	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
4233	cbBefore = 0;
4234	}
4235	else
4236	{
4237	cbAfter = offFifoMax - offCurrentCmd;
4238	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
4239	}
4240
4241	if (cbAfter + cbBefore >= cbPayloadReq)
4242	break;
4243	}
4244	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4245	}
4246
4247	/*
4248	* Copy out the memory and update what pcbAlreadyRead points to.
4249	*/
4250	if (cbAfter >= cbPayloadReq)
4251	memcpy(pbBounceBuf + cbAlreadyRead,
4252	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4253	cbPayloadReq - cbAlreadyRead);
4254	else
4255	{
4256	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
4257	if (cbAlreadyRead < cbAfter)
4258	{
4259	memcpy(pbBounceBuf + cbAlreadyRead,
4260	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4261	cbAfter - cbAlreadyRead);
4262	cbAlreadyRead = cbAfter;
4263	}
4264	memcpy(pbBounceBuf + cbAlreadyRead,
4265	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
4266	cbPayloadReq - cbAlreadyRead);
4267	}
4268	*pcbAlreadyRead = cbPayloadReq;
4269	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4270	return pbBounceBuf;
4271	}
4272
4273
4274	/**
4275	* Sends cursor position and visibility information from the FIFO to the front-end.
4276	* @returns SVGA_FIFO_CURSOR_COUNT value used.
4277	*/
4278	static uint32_t
4279	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
4280	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
4281	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
4282	{
4283	/*
4284	* Check if the cursor update counter has changed and try get a stable
4285	* set of values if it has. This is race-prone, especially consindering
4286	* the screen ID, but little we can do about that.
4287	*/
4288	uint32_t x, y, fVisible, idScreen;
4289	for (uint32_t i = 0; ; i++)
4290	{
4291	x = pFIFO[SVGA_FIFO_CURSOR_X];
4292	y = pFIFO[SVGA_FIFO_CURSOR_Y];
4293	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
4294	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
4295	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
4296	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
4297	\|\| i > 3)
4298	break;
4299	if (i == 0)
4300	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
4301	ASMNopPause();
4302	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4303	}
4304
4305	/*
4306	* Check if anything has changed, as calling into pDrv is not light-weight.
4307	*/
4308	if ( *pxLast == x
4309	&& *pyLast == y
4310	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
4311	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
4312	else
4313	{
4314	/*
4315	* Detected changes.
4316	*
4317	* We handle global, not per-screen visibility information by sending
4318	* pfnVBVAMousePointerShape without shape data.
4319	*/
4320	*pxLast = x;
4321	*pyLast = y;
4322	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
4323	if (idScreen != SVGA_ID_INVALID)
4324	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
4325	else if (*pfLastVisible != fVisible)
4326	{
4327	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
4328	*pfLastVisible = fVisible;
4329	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
4330	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
4331	}
4332	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
4333	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
4334	}
4335
4336	/*
4337	* Update done. Signal this to the guest.
4338	*/
4339	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
4340
4341	return uCursorUpdateCount;
4342	}
4343
4344
4345	/**
4346	* Checks if there is work to be done, either cursor updating or FIFO commands.
4347	*
4348	* @returns true if pending work, false if not.
4349	* @param pThisCC The VGA/VMSVGA state for ring-3.
4350	* @param uLastCursorCount The last cursor update counter value.
4351	*/
4352	DECLINLINE(bool) vmsvgaR3FifoHasWork(PVGASTATECC pThisCC, uint32_t uLastCursorCount)
4353	{
4354	/* If FIFO does not exist than there is nothing to do. Command buffers also require the enabled FIFO. */
4355	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4356	AssertReturn(pFIFO, false);
4357
4358	if (vmsvgaR3CmdBufHasWork(pThisCC))
4359	return true;
4360
4361	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
4362	return true;
4363
4364	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
4365	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
4366	return true;
4367
4368	return false;
4369	}
4370
4371
4372	/**
4373	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
4374	*
4375	* @param pDevIns The device instance.
4376	* @param pThis The shared VGA/VMSVGA instance data.
4377	* @param pThisCC The VGA/VMSVGA state for ring-3.
4378	*/
4379	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4380	{
4381	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
4382	to recheck it before doing the signalling. */
4383	if ( vmsvgaR3FifoHasWork(pThisCC, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
4384	&& pThis->svga.fFIFOThreadSleeping
4385	&& !ASMAtomicReadBool(&pThis->svga.fBadGuest))
4386	{
4387	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4388	AssertRC(rc);
4389	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
4390	}
4391	}
4392
4393
4394	/**
4395	* Called by the FIFO thread to process pending actions.
4396	*
4397	* @param pDevIns The device instance.
4398	* @param pThis The shared VGA/VMSVGA instance data.
4399	* @param pThisCC The VGA/VMSVGA state for ring-3.
4400	*/
4401	void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4402	{
4403	RT_NOREF(pDevIns);
4404
4405	/* Currently just mode changes. */
4406	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
4407	{
4408	vmsvgaR3ChangeMode(pThis, pThisCC);
4409	# ifdef VBOX_WITH_VMSVGA3D
4410	if (pThisCC->svga.p3dState != NULL)
4411	vmsvga3dChangeMode(pThisCC);
4412	# endif
4413	}
4414	}
4415
4416
4417	/*
4418	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
4419	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
4420	*/
4421	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4422	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
4423	*
4424	* Will break out of the switch on failure.
4425	* Will restart and quit the loop if the thread was requested to stop.
4426	*
4427	* @param a_PtrVar Request variable pointer.
4428	* @param a_Type Request typedef (not pointer) for casting.
4429	* @param a_cbPayloadReq How much payload to fetch.
4430	* @remarks Accesses a bunch of variables in the current scope!
4431	*/
4432	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4433	if (1) { \
4434	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
4435	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
4436	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
4437	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
4438	} else do {} while (0)
4439	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4440	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
4441	* buffer after figuring out the actual command size.
4442	*
4443	* Will break out of the switch on failure.
4444	*
4445	* @param a_PtrVar Request variable pointer.
4446	* @param a_Type Request typedef (not pointer) for casting.
4447	* @param a_cbPayloadReq How much payload to fetch.
4448	* @remarks Accesses a bunch of variables in the current scope!
4449	*/
4450	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4451	if (1) { \
4452	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
4453	} else do {} while (0)
4454
4455	/**
4456	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
4457	*/
4458	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4459	{
4460	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4461	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4462	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4463	int rc;
4464
4465	# if defined(VBOX_WITH_VMSVGA3D) && defined(RT_OS_LINUX)
4466	if (pThis->svga.f3DEnabled)
4467	{
4468	/* The FIFO thread may use X API for accelerated screen output. */
4469	XInitThreads();
4470	}
4471	# endif
4472
4473	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4474	return VINF_SUCCESS;
4475
4476	/*
4477	* Special mode where we only execute an external command and the go back
4478	* to being suspended. Currently, all ext cmds ends up here, with the reset
4479	* one also being eligble for runtime execution further down as well.
4480	*/
4481	if (pThis->svga.fFifoExtCommandWakeup)
4482	{
4483	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4484	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4485	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
4486	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
4487	else
4488	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4489	return VINF_SUCCESS;
4490	}
4491
4492
4493	/*
4494	* Signal the semaphore to make sure we don't wait for 250ms after a
4495	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
4496	*/
4497	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4498
4499	/*
4500	* Allocate a bounce buffer for command we get from the FIFO.
4501	* (All code must return via the end of the function to free this buffer.)
4502	*/
4503	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
4504	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
4505
4506	/*
4507	* Polling/sleep interval config.
4508	*
4509	* We wait for an a short interval if the guest has recently given us work
4510	* to do, but the interval increases the longer we're kept idle. Once we've
4511	* reached the refresh timer interval, we'll switch to extended waits,
4512	* depending on it or the guest to kick us into action when needed.
4513	*
4514	* Should the refresh time go fishing, we'll just continue increasing the
4515	* sleep length till we reaches the 250 ms max after about 16 seconds.
4516	*/
4517	RTMSINTERVAL const cMsMinSleep = 16;
4518	RTMSINTERVAL const cMsIncSleep = 2;
4519	RTMSINTERVAL const cMsMaxSleep = 250;
4520	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
4521	RTMSINTERVAL cMsSleep = cMsMaxSleep;
4522
4523	/*
4524	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
4525	*
4526	* Initialize with values that will detect an update from the guest.
4527	* Make sure that if the guest never updates the cursor position, then the device does not report it.
4528	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
4529	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
4530	*/
4531	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4532	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4533	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
4534	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
4535	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
4536
4537	/*
4538	* The FIFO loop.
4539	*/
4540	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
4541	bool fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4542	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4543	{
4544	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
4545	/*
4546	* Should service the run loop every so often.
4547	*/
4548	if (pThis->svga.f3DEnabled)
4549	vmsvga3dCocoaServiceRunLoop();
4550	# endif
4551
4552	/* First check any pending actions. */
4553	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4554
4555	/*
4556	* Unless there's already work pending, go to sleep for a short while.
4557	* (See polling/sleep interval config above.)
4558	*/
4559	if ( fBadOrDisabledFifo
4560	\|\| !vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4561	{
4562	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
4563	Assert(pThis->cMilliesRefreshInterval > 0);
4564	if (cMsSleep < pThis->cMilliesRefreshInterval)
4565	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
4566	else
4567	{
4568	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
4569	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
4570	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
4571	# endif
4572	if ( !fBadOrDisabledFifo
4573	&& vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4574	rc = VINF_SUCCESS;
4575	else
4576	{
4577	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
4578	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
4579	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
4580	}
4581	}
4582	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
4583	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
4584	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4585	{
4586	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
4587	break;
4588	}
4589	}
4590	else
4591	rc = VINF_SUCCESS;
4592	fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4593	if (rc == VERR_TIMEOUT)
4594	{
4595	if (!vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4596	{
4597	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
4598	continue;
4599	}
4600	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
4601
4602	Log(("vmsvgaR3FifoLoop: timeout\n"));
4603	}
4604	else if (vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4605	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
4606	cMsSleep = cMsMinSleep;
4607
4608	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
4609	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
4610	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
4611
4612	/*
4613	* Handle external commands (currently only reset).
4614	*/
4615	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4616	{
4617	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4618	continue;
4619	}
4620
4621	/*
4622	* If guest misbehaves, then do nothing.
4623	*/
4624	if (ASMAtomicReadBool(&pThis->svga.fBadGuest))
4625	{
4626	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4627	cMsSleep = cMsExtendedSleep;
4628	LogRelMax(1, ("VMSVGA: FIFO processing stopped because of the guest misbehavior\n"));
4629	continue;
4630	}
4631
4632	/*
4633	* The device must be enabled and configured.
4634	*/
4635	if ( !pThis->svga.fEnabled
4636	\|\| !pThis->svga.fConfigured)
4637	{
4638	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4639	fBadOrDisabledFifo = true;
4640	cMsSleep = cMsMaxSleep; /* cheat */
4641	continue;
4642	}
4643
4644	/*
4645	* Get and check the min/max values. We ASSUME that they will remain
4646	* unchanged while we process requests. A further ASSUMPTION is that
4647	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
4648	* we don't read it back while in the loop.
4649	*/
4650	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
4651	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
4652	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
4653	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4654	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
4655	\|\| offFifoMax <= offFifoMin
4656	\|\| offFifoMax > pThis->svga.cbFIFO
4657	\|\| (offFifoMax & 3) != 0
4658	\|\| (offFifoMin & 3) != 0
4659	\|\| offCurrentCmd < offFifoMin
4660	\|\| offCurrentCmd > offFifoMax))
4661	{
4662	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4663	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
4664	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4665	fBadOrDisabledFifo = true;
4666	continue;
4667	}
4668	RT_UNTRUSTED_VALIDATED_FENCE();
4669	if (RT_UNLIKELY(offCurrentCmd & 3))
4670	{
4671	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4672	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
4673	offCurrentCmd &= ~UINT32_C(3);
4674	}
4675
4676	/*
4677	* Update the cursor position before we start on the FIFO commands.
4678	*/
4679	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
4680	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
4681	{
4682	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4683	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
4684	{ /* halfways likely */ }
4685	else
4686	{
4687	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
4688	&xLastCursor, &yLastCursor, &fLastCursorVisible);
4689	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
4690	}
4691	}
4692
4693	/*
4694	* Mark the FIFO as busy.
4695	*/
4696	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
4697	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4698	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
4699
4700	/*
4701	* Process all submitted command buffers.
4702	*/
4703	vmsvgaR3CmdBufProcessBuffers(pDevIns, pThis, pThisCC, pThread);
4704
4705	/*
4706	* Execute all queued FIFO commands.
4707	* Quit if pending external command or changes in the thread state.
4708	*/
4709	bool fDone = false;
4710	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
4711	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
4712	{
4713	uint32_t cbPayload = 0;
4714	uint32_t u32IrqStatus = 0;
4715
4716	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
4717
4718	/* First check any pending actions. */
4719	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4720
4721	/* Check for pending external commands (reset). */
4722	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4723	break;
4724
4725	/*
4726	* Process the command.
4727	*/
4728	/* 'enmCmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
4729	* warning. Because we implement some obsolete and deprecated commands, which are not included in
4730	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
4731	*/
4732	uint32_t const enmCmdId = pFIFO[offCurrentCmd / sizeof(uint32_t)];
4733	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4734	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s %d\n",
4735	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
4736	switch (enmCmdId)
4737	{
4738	case SVGA_CMD_INVALID_CMD:
4739	/* Nothing to do. */
4740	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
4741	break;
4742
4743	case SVGA_CMD_FENCE:
4744	{
4745	SVGAFifoCmdFence *pCmdFence;
4746	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
4747	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
4748	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
4749	{
4750	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %#x\n", pCmdFence->fence));
4751	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
4752
4753	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
4754	{
4755	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
4756	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
4757	}
4758	else
4759	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
4760	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
4761	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
4762	{
4763	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%#x)\n", pCmdFence->fence));
4764	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
4765	}
4766	}
4767	else
4768	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
4769	break;
4770	}
4771
4772	case SVGA_CMD_UPDATE:
4773	{
4774	SVGAFifoCmdUpdate *pCmd;
4775	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdate, sizeof(*pCmd));
4776	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
4777	break;
4778	}
4779
4780	case SVGA_CMD_UPDATE_VERBOSE:
4781	{
4782	SVGAFifoCmdUpdateVerbose *pCmd;
4783	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdateVerbose, sizeof(*pCmd));
4784	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
4785	break;
4786	}
4787
4788	case SVGA_CMD_DEFINE_CURSOR:
4789	{
4790	/* Followed by bitmap data. */
4791	SVGAFifoCmdDefineCursor *pCmd;
4792	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, sizeof(*pCmd));
4793
4794	/* Figure out the size of the bitmap data. */
4795	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4796	ASSERT_GUEST_BREAK(pCmd->andMaskDepth <= 32);
4797	ASSERT_GUEST_BREAK(pCmd->xorMaskDepth <= 32);
4798	RT_UNTRUSTED_VALIDATED_FENCE();
4799
4800	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
4801	uint32_t const cbAndMask = cbAndLine * pCmd->height;
4802	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
4803	uint32_t const cbXorMask = cbXorLine * pCmd->height;
4804
4805	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineCursor) + cbAndMask + cbXorMask;
4806	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, cbCmd);
4807	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
4808	break;
4809	}
4810
4811	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
4812	{
4813	/* Followed by bitmap data. */
4814	SVGAFifoCmdDefineAlphaCursor *pCmd;
4815	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCmd));
4816
4817	/* Figure out the size of the bitmap data. */
4818	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4819
4820	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCmd->width * pCmd->height * sizeof(uint32_t) /* 32-bit BRGA format */;
4821	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, cbCmd);
4822	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
4823	break;
4824	}
4825
4826	case SVGA_CMD_MOVE_CURSOR:
4827	{
4828	/* Deprecated; there should be no driver which requires this command. However, if
4829	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4830	* alignment.
4831	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4832	*/
4833	SVGAFifoCmdMoveCursor *pCmd;
4834	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdMoveCursor, sizeof(*pCmd));
4835	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
4836	break;
4837	}
4838
4839	case SVGA_CMD_DISPLAY_CURSOR:
4840	{
4841	/* Deprecated; there should be no driver which requires this command. However, if
4842	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4843	* alignment.
4844	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4845	*/
4846	SVGAFifoCmdDisplayCursor *pCmd;
4847	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDisplayCursor, sizeof(*pCmd));
4848	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
4849	break;
4850	}
4851
4852	case SVGA_CMD_RECT_FILL:
4853	{
4854	SVGAFifoCmdRectFill *pCmd;
4855	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectFill, sizeof(*pCmd));
4856	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
4857	break;
4858	}
4859
4860	case SVGA_CMD_RECT_COPY:
4861	{
4862	SVGAFifoCmdRectCopy *pCmd;
4863	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectCopy, sizeof(*pCmd));
4864	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
4865	break;
4866	}
4867
4868	case SVGA_CMD_RECT_ROP_COPY:
4869	{
4870	SVGAFifoCmdRectRopCopy *pCmd;
4871	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectRopCopy, sizeof(*pCmd));
4872	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
4873	break;
4874	}
4875
4876	case SVGA_CMD_ESCAPE:
4877	{
4878	/* Followed by 'size' bytes of data. */
4879	SVGAFifoCmdEscape *pCmd;
4880	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, sizeof(*pCmd));
4881
4882	ASSERT_GUEST_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape));
4883	RT_UNTRUSTED_VALIDATED_FENCE();
4884
4885	uint32_t const cbCmd = sizeof(SVGAFifoCmdEscape) + pCmd->size;
4886	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, cbCmd);
4887	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
4888	break;
4889	}
4890	# ifdef VBOX_WITH_VMSVGA3D
4891	case SVGA_CMD_DEFINE_GMR2:
4892	{
4893	SVGAFifoCmdDefineGMR2 *pCmd;
4894	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
4895	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
4896	break;
4897	}
4898
4899	case SVGA_CMD_REMAP_GMR2:
4900	{
4901	/* Followed by page descriptors or guest ptr. */
4902	SVGAFifoCmdRemapGMR2 *pCmd;
4903	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
4904
4905	/* Calculate the size of what comes after next and fetch it. */
4906	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
4907	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4908	cbCmd += sizeof(SVGAGuestPtr);
4909	else
4910	{
4911	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
4912	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
4913	{
4914	cbCmd += cbPageDesc;
4915	pCmd->numPages = 1;
4916	}
4917	else
4918	{
4919	ASSERT_GUEST_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
4920	cbCmd += cbPageDesc * pCmd->numPages;
4921	}
4922	}
4923	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
4924	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
4925	# ifdef DEBUG_GMR_ACCESS
4926	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4927	# endif
4928	break;
4929	}
4930	# endif // VBOX_WITH_VMSVGA3D
4931	case SVGA_CMD_DEFINE_SCREEN:
4932	{
4933	/* The size of this command is specified by the guest and depends on capabilities. */
4934	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4935
4936	SVGAFifoCmdDefineScreen *pCmd;
4937	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4938	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4939	RT_UNTRUSTED_VALIDATED_FENCE();
4940
4941	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4942	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4943	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
4944	break;
4945	}
4946
4947	case SVGA_CMD_DESTROY_SCREEN:
4948	{
4949	SVGAFifoCmdDestroyScreen *pCmd;
4950	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4951	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
4952	break;
4953	}
4954
4955	case SVGA_CMD_DEFINE_GMRFB:
4956	{
4957	SVGAFifoCmdDefineGMRFB *pCmd;
4958	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4959	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
4960	break;
4961	}
4962
4963	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4964	{
4965	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4966	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4967	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
4968	break;
4969	}
4970
4971	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4972	{
4973	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4974	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4975	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
4976	break;
4977	}
4978
4979	case SVGA_CMD_ANNOTATION_FILL:
4980	{
4981	SVGAFifoCmdAnnotationFill *pCmd;
4982	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4983	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
4984	break;
4985	}
4986
4987	case SVGA_CMD_ANNOTATION_COPY:
4988	{
4989	SVGAFifoCmdAnnotationCopy *pCmd;
4990	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4991	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
4992	break;
4993	}
4994
4995	default:
4996	# ifdef VBOX_WITH_VMSVGA3D
4997	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4998	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4999	{
5000	RT_UNTRUSTED_VALIDATED_FENCE();
5001
5002	/* All 3d commands start with a common header, which defines the identifier and the size
5003	* of the command. The identifier has been already read from FIFO. Fetch the size.
5004	*/
5005	uint32_t *pcbCmd;
5006	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pcbCmd, uint32_t, sizeof(*pcbCmd));
5007	uint32_t const cbCmd = *pcbCmd;
5008	AssertBreak(cbCmd < pThis->svga.cbFIFO);
5009	uint32_t *pu32Cmd;
5010	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pu32Cmd, uint32_t, sizeof(*pcbCmd) + cbCmd);
5011	pu32Cmd++; /* Skip the command size. */
5012
5013	if (RT_LIKELY(pThis->svga.f3DEnabled))
5014	{ /* likely */ }
5015	else
5016	{
5017	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", enmCmdId));
5018	break;
5019	}
5020
5021	vmsvgaR3Process3dCmd(pThis, pThisCC, SVGA3D_INVALID_ID, (SVGAFifo3dCmdId)enmCmdId, cbCmd, pu32Cmd);
5022	}
5023	else
5024	# endif // VBOX_WITH_VMSVGA3D
5025	{
5026	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
5027	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
5028	LogRelMax(16, ("VMSVGA: unsupported command %d\n", enmCmdId));
5029	}
5030	}
5031
5032	/* Go to the next slot */
5033	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
5034	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
5035	if (offCurrentCmd >= offFifoMax)
5036	{
5037	offCurrentCmd -= offFifoMax - offFifoMin;
5038	Assert(offCurrentCmd >= offFifoMin);
5039	Assert(offCurrentCmd < offFifoMax);
5040	}
5041	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
5042	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
5043
5044	/*
5045	* Raise IRQ if required. Must enter the critical section here
5046	* before making final decisions here, otherwise cubebench and
5047	* others may end up waiting forever.
5048	*/
5049	if ( u32IrqStatus
5050	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
5051	{
5052	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
5053	AssertRC(rc2);
5054
5055	/* FIFO progress might trigger an interrupt. */
5056	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
5057	{
5058	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
5059	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
5060	}
5061
5062	/* Unmasked IRQ pending? */
5063	if (pThis->svga.u32IrqMask & u32IrqStatus)
5064	{
5065	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
5066	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
5067	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
5068	}
5069
5070	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5071	}
5072	}
5073
5074	/* If really done, clear the busy flag. */
5075	if (fDone)
5076	{
5077	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
5078	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
5079	}
5080	}
5081
5082	/*
5083	* Free the bounce buffer. (There are no returns above!)
5084	*/
5085	RTMemFree(pbBounceBuf);
5086
5087	return VINF_SUCCESS;
5088	}
5089
5090	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
5091	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
5092
5093	/**
5094	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5095	* Unblock the FIFO I/O thread so it can respond to a state change.}
5096	*/
5097	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5098	{
5099	RT_NOREF(pDevIns);
5100	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5101	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5102	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5103	}
5104
5105	/**
5106	* Enables or disables dirty page tracking for the framebuffer
5107	*
5108	* @param pDevIns The device instance.
5109	* @param pThis The shared VGA/VMSVGA instance data.
5110	* @param fTraces Enable/disable traces
5111	*/
5112	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5113	{
5114	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5115	&& !fTraces)
5116	{
5117	//Assert(pThis->svga.fTraces);
5118	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5119	return;
5120	}
5121
5122	pThis->svga.fTraces = fTraces;
5123	if (pThis->svga.fTraces)
5124	{
5125	unsigned cbFrameBuffer = pThis->vram_size;
5126
5127	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5128	/** @todo How does this work with screens? */
5129	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5130	{
5131	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5132	Assert(pThis->svga.cbScanline);
5133	# endif
5134	/* Hardware enabled; return real framebuffer size .*/
5135	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5136	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5137	}
5138
5139	if (!pThis->svga.fVRAMTracking)
5140	{
5141	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5142	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5143	pThis->svga.fVRAMTracking = true;
5144	}
5145	}
5146	else
5147	{
5148	if (pThis->svga.fVRAMTracking)
5149	{
5150	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5151	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5152	pThis->svga.fVRAMTracking = false;
5153	}
5154	}
5155	}
5156
5157	/**
5158	* @callback_method_impl{FNPCIIOREGIONMAP}
5159	*/
5160	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5161	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5162	{
5163	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5164	int rc;
5165	RT_NOREF(pPciDev);
5166	Assert(pPciDev == pDevIns->apPciDevs[0]);
5167
5168	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5169	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5170	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5171	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5172	, VERR_INTERNAL_ERROR);
5173	if (GCPhysAddress != NIL_RTGCPHYS)
5174	{
5175	/*
5176	* Mapping the FIFO RAM.
5177	*/
5178	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5179	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5180	AssertRC(rc);
5181
5182	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5183	if (RT_SUCCESS(rc))
5184	{
5185	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5186	# ifdef DEBUG_FIFO_ACCESS
5187	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5188	# else
5189	GCPhysAddress + PAGE_SIZE - 1,
5190	# endif
5191	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5192	"VMSVGA FIFO");
5193	AssertRC(rc);
5194	}
5195	# endif
5196	if (RT_SUCCESS(rc))
5197	{
5198	pThis->svga.GCPhysFIFO = GCPhysAddress;
5199	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5200	}
5201	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite errors here. */
5202	}
5203	else
5204	{
5205	Assert(pThis->svga.GCPhysFIFO);
5206	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5207	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5208	AssertRC(rc);
5209	# else
5210	rc = VINF_SUCCESS;
5211	# endif
5212	pThis->svga.GCPhysFIFO = 0;
5213	}
5214	return rc;
5215	}
5216
5217	# ifdef VBOX_WITH_VMSVGA3D
5218
5219	/**
5220	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5221	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5222	*
5223	* @param pDevIns The device instance.
5224	* @param pThis The The shared VGA/VMSVGA instance data.
5225	* @param pThisCC The VGA/VMSVGA state for ring-3.
5226	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5227	* UINT32_MAX is used, all surfaces are processed.
5228	*/
5229	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5230	{
5231	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5232	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5233	}
5234
5235
5236	/**
5237	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5238	*/
5239	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5240	{
5241	/* There might be a specific surface ID at the start of the
5242	arguments, if not show all surfaces. */
5243	uint32_t sid = UINT32_MAX;
5244	if (pszArgs)
5245	pszArgs = RTStrStripL(pszArgs);
5246	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5247	sid = RTStrToUInt32(pszArgs);
5248
5249	/* Verbose or terse display, we default to verbose. */
5250	bool fVerbose = true;
5251	if (RTStrIStr(pszArgs, "terse"))
5252	fVerbose = false;
5253
5254	/* The size of the ascii art (x direction, y is 3/4 of x). */
5255	uint32_t cxAscii = 80;
5256	if (RTStrIStr(pszArgs, "gigantic"))
5257	cxAscii = 300;
5258	else if (RTStrIStr(pszArgs, "huge"))
5259	cxAscii = 180;
5260	else if (RTStrIStr(pszArgs, "big"))
5261	cxAscii = 132;
5262	else if (RTStrIStr(pszArgs, "normal"))
5263	cxAscii = 80;
5264	else if (RTStrIStr(pszArgs, "medium"))
5265	cxAscii = 64;
5266	else if (RTStrIStr(pszArgs, "small"))
5267	cxAscii = 48;
5268	else if (RTStrIStr(pszArgs, "tiny"))
5269	cxAscii = 24;
5270
5271	/* Y invert the image when producing the ASCII art. */
5272	bool fInvY = false;
5273	if (RTStrIStr(pszArgs, "invy"))
5274	fInvY = true;
5275
5276	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5277	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5278	}
5279
5280
5281	/**
5282	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5283	*/
5284	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5285	{
5286	/* pszArg = "sid[>dir]"
5287	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5288	*/
5289	char *pszBitmapPath = NULL;
5290	uint32_t sid = UINT32_MAX;
5291	if (pszArgs)
5292	pszArgs = RTStrStripL(pszArgs);
5293	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5294	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5295	if ( pszBitmapPath
5296	&& *pszBitmapPath == '>')
5297	++pszBitmapPath;
5298
5299	const bool fVerbose = true;
5300	const uint32_t cxAscii = 0; /* No ASCII */
5301	const bool fInvY = false; /* Do not invert. */
5302	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5303	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5304	}
5305
5306	/**
5307	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5308	*/
5309	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5310	{
5311	/* There might be a specific surface ID at the start of the
5312	arguments, if not show all contexts. */
5313	uint32_t sid = UINT32_MAX;
5314	if (pszArgs)
5315	pszArgs = RTStrStripL(pszArgs);
5316	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5317	sid = RTStrToUInt32(pszArgs);
5318
5319	/* Verbose or terse display, we default to verbose. */
5320	bool fVerbose = true;
5321	if (RTStrIStr(pszArgs, "terse"))
5322	fVerbose = false;
5323
5324	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5325	}
5326	# endif /* VBOX_WITH_VMSVGA3D */
5327
5328	/**
5329	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5330	*/
5331	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5332	{
5333	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5334	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5335	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5336	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5337	RT_NOREF(pszArgs);
5338
5339	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5340	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5341	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5342	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5343	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5344	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5345	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5346	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5347	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5348	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5349	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5350	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5351	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5352	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5353	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5354	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5355	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5356	pHlp->pfnPrintf(pHlp, "Device Capabilites: %#x\n", pThis->svga.u32DeviceCaps);
5357	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5358	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5359	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5360	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5361	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5362	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5363	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5364
5365	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5366	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5367	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5368	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5369
5370	pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
5371	pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
5372
5373	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
5374	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
5375
5376	# ifdef VBOX_WITH_VMSVGA3D
5377	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5378	# endif
5379	if (pThisCC->pDrv)
5380	{
5381	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5382	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5383	}
5384
5385	/* Dump screen information. */
5386	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5387	{
5388	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5389	if (pScreen)
5390	{
5391	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5392	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5393	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5394	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5395	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5396	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5397	{
5398	pHlp->pfnPrintf(pHlp, " (");
5399	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5400	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5401	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5402	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5403	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5404	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5405	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5406	pHlp->pfnPrintf(pHlp, " BLANKING");
5407	pHlp->pfnPrintf(pHlp, " )");
5408	}
5409	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5410	}
5411	}
5412
5413	}
5414
5415	/**
5416	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5417	*/
5418	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5419	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5420	{
5421	RT_NOREF(uPass);
5422
5423	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5424	int rc;
5425
5426	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5427	{
5428	uint32_t cScreens = 0;
5429	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5430	AssertRCReturn(rc, rc);
5431	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5432	("cScreens=%#x\n", cScreens),
5433	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5434
5435	for (uint32_t i = 0; i < cScreens; ++i)
5436	{
5437	VMSVGASCREENOBJECT screen;
5438	RT_ZERO(screen);
5439
5440	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5441	AssertLogRelRCReturn(rc, rc);
5442
5443	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5444	{
5445	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5446	*pScreen = screen;
5447	pScreen->fModified = true;
5448	}
5449	else
5450	{
5451	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5452	}
5453	}
5454	}
5455	else
5456	{
5457	/* Try to setup at least the first screen. */
5458	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5459	pScreen->fDefined = true;
5460	pScreen->fModified = true;
5461	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5462	pScreen->idScreen = 0;
5463	pScreen->xOrigin = 0;
5464	pScreen->yOrigin = 0;
5465	pScreen->offVRAM = pThis->svga.uScreenOffset;
5466	pScreen->cbPitch = pThis->svga.cbScanline;
5467	pScreen->cWidth = pThis->svga.uWidth;
5468	pScreen->cHeight = pThis->svga.uHeight;
5469	pScreen->cBpp = pThis->svga.uBpp;
5470	}
5471
5472	return VINF_SUCCESS;
5473	}
5474
5475	/**
5476	* @copydoc FNSSMDEVLOADEXEC
5477	*/
5478	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5479	{
5480	RT_NOREF(uPass);
5481	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5482	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5483	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5484	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5485	int rc;
5486
5487	/* Load our part of the VGAState */
5488	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5489	AssertRCReturn(rc, rc);
5490
5491	/* Load the VGA framebuffer. */
5492	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5493	uint32_t cbVgaFramebuffer = _32K;
5494	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5495	{
5496	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5497	AssertRCReturn(rc, rc);
5498	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5499	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5500	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5501	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5502	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5503	}
5504	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5505	AssertRCReturn(rc, rc);
5506	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5507	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5508	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5509	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5510
5511	/* Load the VMSVGA state. */
5512	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5513	AssertRCReturn(rc, rc);
5514
5515	/* Load the active cursor bitmaps. */
5516	if (pSVGAState->Cursor.fActive)
5517	{
5518	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5519	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5520
5521	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5522	AssertRCReturn(rc, rc);
5523	}
5524
5525	/* Load the GMR state. */
5526	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5527	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5528	{
5529	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5530	AssertRCReturn(rc, rc);
5531	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5532	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5533	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5534	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5535	}
5536
5537	if (pThis->svga.cGMR != cGMR)
5538	{
5539	/* Reallocate GMR array. */
5540	Assert(pSVGAState->paGMR != NULL);
5541	RTMemFree(pSVGAState->paGMR);
5542	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5543	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5544	pThis->svga.cGMR = cGMR;
5545	}
5546
5547	for (uint32_t i = 0; i < cGMR; ++i)
5548	{
5549	PGMR pGMR = &pSVGAState->paGMR[i];
5550
5551	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5552	AssertRCReturn(rc, rc);
5553
5554	if (pGMR->numDescriptors)
5555	{
5556	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5557	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5558	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5559
5560	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5561	{
5562	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5563	AssertRCReturn(rc, rc);
5564	}
5565	}
5566	}
5567
5568	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5569	if (pThis->svga.f3DEnabled)
5570	pSVGAState->pFuncs3D->pfnPowerOn(pDevIns, pThis, pThisCC);
5571	# endif
5572
5573	VMSVGA_STATE_LOAD LoadState;
5574	LoadState.pSSM = pSSM;
5575	LoadState.uVersion = uVersion;
5576	LoadState.uPass = uPass;
5577	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5578	AssertLogRelRCReturn(rc, rc);
5579
5580	return VINF_SUCCESS;
5581	}
5582
5583	/**
5584	* Reinit the video mode after the state has been loaded.
5585	*/
5586	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5587	{
5588	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5589	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5590	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5591
5592	/* Set the active cursor. */
5593	if (pSVGAState->Cursor.fActive)
5594	{
5595	/* We don't store the alpha flag, but we can take a guess that if
5596	* the old register interface was used, the cursor was B&W.
5597	*/
5598	bool fAlpha = pThis->svga.uCursorOn ? false : true;
5599
5600	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
5601	true /fVisible/,
5602	fAlpha,
5603	pSVGAState->Cursor.xHotspot,
5604	pSVGAState->Cursor.yHotspot,
5605	pSVGAState->Cursor.width,
5606	pSVGAState->Cursor.height,
5607	pSVGAState->Cursor.pData);
5608	AssertRC(rc);
5609
5610	if (pThis->svga.uCursorOn)
5611	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
5612	}
5613
5614	/* If the VRAM handler should not be registered, we have to explicitly
5615	* unregister it here!
5616	*/
5617	if (!pThis->svga.fVRAMTracking)
5618	{
5619	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5620	}
5621
5622	/* Let the FIFO thread deal with changing the mode. */
5623	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5624
5625	return VINF_SUCCESS;
5626	}
5627
5628	/**
5629	* Portion of SVGA state which must be saved in the FIFO thread.
5630	*/
5631	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5632	{
5633	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5634	int rc;
5635
5636	/* Save the screen objects. */
5637	/* Count defined screen object. */
5638	uint32_t cScreens = 0;
5639	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5640	{
5641	if (pSVGAState->aScreens[i].fDefined)
5642	++cScreens;
5643	}
5644
5645	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5646	AssertLogRelRCReturn(rc, rc);
5647
5648	for (uint32_t i = 0; i < cScreens; ++i)
5649	{
5650	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5651
5652	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5653	AssertLogRelRCReturn(rc, rc);
5654	}
5655	return VINF_SUCCESS;
5656	}
5657
5658	/**
5659	* @copydoc FNSSMDEVSAVEEXEC
5660	*/
5661	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5662	{
5663	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5664	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5665	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5666	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5667	int rc;
5668
5669	/* Save our part of the VGAState */
5670	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5671	AssertLogRelRCReturn(rc, rc);
5672
5673	/* Save the framebuffer backup. */
5674	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5675	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5676	AssertLogRelRCReturn(rc, rc);
5677
5678	/* Save the VMSVGA state. */
5679	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5680	AssertLogRelRCReturn(rc, rc);
5681
5682	/* Save the active cursor bitmaps. */
5683	if (pSVGAState->Cursor.fActive)
5684	{
5685	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5686	AssertLogRelRCReturn(rc, rc);
5687	}
5688
5689	/* Save the GMR state */
5690	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5691	AssertLogRelRCReturn(rc, rc);
5692	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5693	{
5694	PGMR pGMR = &pSVGAState->paGMR[i];
5695
5696	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5697	AssertLogRelRCReturn(rc, rc);
5698
5699	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5700	{
5701	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5702	AssertLogRelRCReturn(rc, rc);
5703	}
5704	}
5705
5706	/*
5707	* Must save some state (3D in particular) in the FIFO thread.
5708	*/
5709	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5710	AssertLogRelRCReturn(rc, rc);
5711
5712	return VINF_SUCCESS;
5713	}
5714
5715	/**
5716	* Destructor for PVMSVGAR3STATE structure. The structure is not deallocated.
5717	*
5718	* @param pThis The shared VGA/VMSVGA instance data.
5719	* @param pThisCC The device context.
5720	*/
5721	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVGASTATECC pThisCC)
5722	{
5723	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5724
5725	# ifndef VMSVGA_USE_EMT_HALT_CODE
5726	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5727	{
5728	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5729	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5730	}
5731	# endif
5732
5733	if (pSVGAState->Cursor.fActive)
5734	{
5735	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5736	pSVGAState->Cursor.pData = NULL;
5737	pSVGAState->Cursor.fActive = false;
5738	}
5739
5740	if (pSVGAState->paGMR)
5741	{
5742	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5743	if (pSVGAState->paGMR[i].paDesc)
5744	RTMemFree(pSVGAState->paGMR[i].paDesc);
5745
5746	RTMemFree(pSVGAState->paGMR);
5747	pSVGAState->paGMR = NULL;
5748	}
5749
5750	if (RTCritSectIsInitialized(&pSVGAState->CritSectCmdBuf))
5751	{
5752	RTCritSectEnter(&pSVGAState->CritSectCmdBuf);
5753	for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->apCmdBufCtxs); ++i)
5754	{
5755	vmsvgaR3CmdBufCtxTerm(pSVGAState->apCmdBufCtxs[i]);
5756	pSVGAState->apCmdBufCtxs[i] = NULL;
5757	}
5758	vmsvgaR3CmdBufCtxTerm(&pSVGAState->CmdBufCtxDC);
5759	RTCritSectLeave(&pSVGAState->CritSectCmdBuf);
5760	RTCritSectDelete(&pSVGAState->CritSectCmdBuf);
5761	}
5762
5763	# ifdef VBOX_WITH_VMSVGA3D
5764	vmsvga3dR3Free3dInterfaces(pThisCC);
5765	# endif
5766	}
5767
5768	/**
5769	* Constructor for PVMSVGAR3STATE structure.
5770	*
5771	* @returns VBox status code.
5772	* @param pDevIns The PDM device instance.
5773	* @param pThis The shared VGA/VMSVGA instance data.
5774	* @param pSVGAState Pointer to the structure. It is already allocated.
5775	*/
5776	static int vmsvgaR3StateInit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5777	{
5778	int rc = VINF_SUCCESS;
5779
5780	pSVGAState->pDevIns = pDevIns;
5781
5782	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5783	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5784
5785	# ifndef VMSVGA_USE_EMT_HALT_CODE
5786	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5787	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5788	AssertRCReturn(rc, rc);
5789	# endif
5790
5791	rc = RTCritSectInit(&pSVGAState->CritSectCmdBuf);
5792	AssertRCReturn(rc, rc);
5793
5794	vmsvgaR3CmdBufCtxInit(&pSVGAState->CmdBufCtxDC);
5795
5796	RTListInit(&pSVGAState->MOBLRUList);
5797	return rc;
5798	}
5799
5800	# ifdef VBOX_WITH_VMSVGA3D
5801	static void vmsvga3dR3Free3dInterfaces(PVGASTATECC pThisCC)
5802	{
5803	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5804
5805	RTMemFree(pSVGAState->pFuncsMap);
5806	pSVGAState->pFuncsMap = NULL;
5807	RTMemFree(pSVGAState->pFuncsGBO);
5808	pSVGAState->pFuncsGBO = NULL;
5809	RTMemFree(pSVGAState->pFuncsDX);
5810	pSVGAState->pFuncsDX = NULL;
5811	RTMemFree(pSVGAState->pFuncsVGPU9);
5812	pSVGAState->pFuncsVGPU9 = NULL;
5813	RTMemFree(pSVGAState->pFuncs3D);
5814	pSVGAState->pFuncs3D = NULL;
5815	}
5816
5817	/* This structure is used only by vmsvgaR3Init3dInterfaces */
5818	typedef struct VMSVGA3DINTERFACE
5819	{
5820	char const *pcszName;
5821	uint32_t cbFuncs;
5822	void **ppvFuncs;
5823	} VMSVGA3DINTERFACE;
5824
5825	/**
5826	* Initializes the optional host 3D backend interfaces.
5827	*
5828	* @returns VBox status code.
5829	* @param pThisCC The VGA/VMSVGA state for ring-3.
5830	*/
5831	static int vmsvgaR3Init3dInterfaces(PVGASTATECC pThisCC)
5832	{
5833	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5834
5835	#define ENTRY_3D_INTERFACE(a_Name, a_Field) { VMSVGA3D_BACKEND_INTERFACE_NAME_##a_Name, sizeof(VMSVGA3DBACKENDFUNCS##a_Name), (void **)&pSVGAState->a_Field }
5836	VMSVGA3DINTERFACE a3dInterface[] =
5837	{
5838	ENTRY_3D_INTERFACE(3D, pFuncs3D),
5839	ENTRY_3D_INTERFACE(VGPU9, pFuncsVGPU9),
5840	ENTRY_3D_INTERFACE(DX, pFuncsDX),
5841	ENTRY_3D_INTERFACE(MAP, pFuncsMap),
5842	ENTRY_3D_INTERFACE(GBO, pFuncsGBO),
5843	};
5844	#undef ENTRY_3D_INTERFACE
5845
5846	int rc = VINF_SUCCESS;
5847	for (uint32_t i = 0; i < RT_ELEMENTS(a3dInterface); ++i)
5848	{
5849	VMSVGA3DINTERFACE *p = &a3dInterface[i];
5850
5851	int rc2 = vmsvga3dQueryInterface(pThisCC, p->pcszName, NULL, p->cbFuncs);
5852	if (RT_SUCCESS(rc2))
5853	{
5854	*p->ppvFuncs = RTMemAllocZ(p->cbFuncs);
5855	AssertBreakStmt(*p->ppvFuncs, rc = VERR_NO_MEMORY);
5856
5857	vmsvga3dQueryInterface(pThisCC, p->pcszName, *p->ppvFuncs, p->cbFuncs);
5858	}
5859	}
5860
5861	if (RT_SUCCESS(rc))
5862	{
5863	/* 3D interface is required. */
5864	if (pSVGAState->pFuncs3D)
5865	return VINF_SUCCESS;
5866
5867	rc = VERR_NOT_SUPPORTED;
5868	}
5869
5870	vmsvga3dR3Free3dInterfaces(pThisCC);
5871	return rc;
5872	}
5873	# endif /* VBOX_WITH_VMSVGA3D */
5874
5875	/**
5876	* Initializes the host capabilities: device and FIFO.
5877	*
5878	* @returns VBox status code.
5879	* @param pThis The shared VGA/VMSVGA instance data.
5880	* @param pThisCC The VGA/VMSVGA state for ring-3.
5881	*/
5882	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5883	{
5884	# ifdef VBOX_WITH_VMSVGA3D
5885	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5886	# endif
5887
5888	/* Device caps. */
5889	pThis->svga.u32DeviceCaps = SVGA_CAP_GMR
5890	\| SVGA_CAP_GMR2
5891	\| SVGA_CAP_CURSOR
5892	\| SVGA_CAP_CURSOR_BYPASS
5893	\| SVGA_CAP_CURSOR_BYPASS_2
5894	\| SVGA_CAP_EXTENDED_FIFO
5895	\| SVGA_CAP_IRQMASK
5896	\| SVGA_CAP_PITCHLOCK
5897	\| SVGA_CAP_RECT_COPY
5898	\| SVGA_CAP_TRACES
5899	\| SVGA_CAP_SCREEN_OBJECT_2
5900	\| SVGA_CAP_ALPHA_CURSOR;
5901
5902	/* VGPU10 capabilities. */
5903	if (pThis->fVMSVGA10)
5904	{
5905	pThis->svga.u32DeviceCaps \|= SVGA_CAP_COMMAND_BUFFERS /* Enable register based command buffer submission. */
5906	// \| SVGA_CAP_CMD_BUFFERS_2 /* Support for SVGA_REG_CMD_PREPEND_LOW/HIGH */
5907	;
5908
5909	# ifdef VBOX_WITH_VMSVGA3D
5910	if (pSVGAState->pFuncsGBO)
5911	pThis->svga.u32DeviceCaps \|= SVGA_CAP_GBOBJECTS; /* Enable guest-backed objects and surfaces. */
5912	if (pSVGAState->pFuncsDX)
5913	pThis->svga.u32DeviceCaps \|= SVGA_CAP_DX; /* Enable support for DX commands, and command buffers in a mob. */
5914	# endif
5915	}
5916
5917	# ifdef VBOX_WITH_VMSVGA3D
5918	if (pSVGAState->pFuncs3D)
5919	pThis->svga.u32DeviceCaps \|= SVGA_CAP_3D;
5920	# endif
5921
5922	/* Clear the FIFO. */
5923	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
5924
5925	/* Setup FIFO capabilities. */
5926	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5927	\| SVGA_FIFO_CAP_PITCHLOCK
5928	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5929	\| SVGA_FIFO_CAP_RESERVE
5930	\| SVGA_FIFO_CAP_GMR2
5931	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5932	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5933
5934	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5935	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5936	}
5937
5938	# ifdef VBOX_WITH_VMSVGA3D
5939	/**
5940	* Initializes the host 3D capabilities and writes them to FIFO memory.
5941	*
5942	* @returns VBox status code.
5943	* @param pThis The shared VGA/VMSVGA instance data.
5944	* @param pThisCC The VGA/VMSVGA state for ring-3.
5945	*/
5946	static void vmsvgaR3InitFifo3DCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5947	{
5948	/* Query the capabilities and store them in the pThis->svga.au32DevCaps array. */
5949	bool const fSavedBuffering = RTLogRelSetBuffering(true);
5950
5951	for (unsigned i = 0; i < RT_ELEMENTS(pThis->svga.au32DevCaps); ++i)
5952	{
5953	uint32_t val = 0;
5954	int rc = vmsvga3dQueryCaps(pThisCC, (SVGA3dDevCapIndex)i, &val);
5955	if (RT_SUCCESS(rc))
5956	pThis->svga.au32DevCaps[i] = val;
5957	else
5958	pThis->svga.au32DevCaps[i] = 0;
5959
5960	/* LogRel the capability value. */
5961	if (i < SVGA3D_DEVCAP_MAX)
5962	{
5963	char const *pszDevCapName = &vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)i)[sizeof("SVGA3D_DEVCAP")];
5964	if (RT_SUCCESS(rc))
5965	{
5966	if ( i == SVGA3D_DEVCAP_MAX_POINT_SIZE
5967	\|\| i == SVGA3D_DEVCAP_MAX_LINE_WIDTH
5968	\|\| i == SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH)
5969	{
5970	float const fval = (float )&val;
5971	LogRel(("VMSVGA3d: cap[%u]=" FLOAT_FMT_STR " {%s}\n", i, FLOAT_FMT_ARGS(fval), pszDevCapName));
5972	}
5973	else
5974	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, pszDevCapName));
5975	}
5976	else
5977	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc {%s}\n", i, rc, pszDevCapName));
5978	}
5979	else
5980	LogRel(("VMSVGA3d: new cap[%u]=%#010x rc=%Rrc\n", i, val, rc));
5981	}
5982
5983	RTLogRelSetBuffering(fSavedBuffering);
5984
5985	/* 3d hardware version; latest and greatest */
5986	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5987	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5988
5989	/* Fill out 3d capabilities up to SVGA3D_DEVCAP_SURFACEFMT_ATI2 in the FIFO memory.
5990	* SVGA3D_DEVCAP_SURFACEFMT_ATI2 is the last capabiltiy for pre-SVGA_CAP_GBOBJECTS hardware.
5991	* If the VMSVGA device supports SVGA_CAP_GBOBJECTS capability, then the guest has to use SVGA_REG_DEV_CAP
5992	* register to query the devcaps. Older guests will still try to read the devcaps from FIFO.
5993	*/
5994	SVGA3dCapsRecord *pCaps;
5995	SVGA3dCapPair *pData;
5996
5997	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
5998	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5999	pData = (SVGA3dCapPair *)&pCaps->data;
6000
6001	AssertCompile(SVGA3D_DEVCAP_DEAD1 == SVGA3D_DEVCAP_SURFACEFMT_ATI2 + 1);
6002	for (unsigned i = 0; i < SVGA3D_DEVCAP_DEAD1; ++i)
6003	{
6004	pData[i][0] = i;
6005	pData[i][1] = pThis->svga.au32DevCaps[i];
6006	}
6007	pCaps->header.length = (sizeof(pCaps->header) + SVGA3D_DEVCAP_DEAD1 * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6008	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6009
6010	/* Mark end of record array (a zero word). */
6011	pCaps->header.length = 0;
6012	}
6013
6014	# endif
6015
6016	/**
6017	* Resets the SVGA hardware state
6018	*
6019	* @returns VBox status code.
6020	* @param pDevIns The device instance.
6021	*/
6022	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6023	{
6024	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6025	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6026	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6027
6028	/* Reset before init? */
6029	if (!pSVGAState)
6030	return VINF_SUCCESS;
6031
6032	Log(("vmsvgaR3Reset\n"));
6033
6034	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6035	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6036	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6037
6038	/* Reset other stuff. */
6039	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6040	RT_ZERO(pThis->svga.au32ScratchRegion);
6041
6042	ASMAtomicWriteBool(&pThis->svga.fBadGuest, false);
6043
6044	vmsvgaR3StateTerm(pThis, pThisCC);
6045	vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
6046
6047	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6048
6049	/* Initialize FIFO and register capabilities. */
6050	vmsvgaR3InitCaps(pThis, pThisCC);
6051
6052	# ifdef VBOX_WITH_VMSVGA3D
6053	if (pThis->svga.f3DEnabled)
6054	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
6055	# endif
6056
6057	/* VRAM tracking is enabled by default during bootup. */
6058	pThis->svga.fVRAMTracking = true;
6059	pThis->svga.fEnabled = false;
6060
6061	/* Invalidate current settings. */
6062	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6063	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6064	pThis->svga.uBpp = pThis->svga.uHostBpp;
6065	pThis->svga.cbScanline = 0;
6066	pThis->svga.u32PitchLock = 0;
6067
6068	return rc;
6069	}
6070
6071	/**
6072	* Cleans up the SVGA hardware state
6073	*
6074	* @returns VBox status code.
6075	* @param pDevIns The device instance.
6076	*/
6077	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6078	{
6079	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6080	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6081
6082	/*
6083	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6084	*/
6085	if (pThisCC->svga.pFIFOIOThread)
6086	{
6087	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6088	NULL /pvParam/, 30000 /ms/);
6089	AssertLogRelRC(rc);
6090
6091	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6092	AssertLogRelRC(rc);
6093	pThisCC->svga.pFIFOIOThread = NULL;
6094	}
6095
6096	/*
6097	* Destroy the special SVGA state.
6098	*/
6099	if (pThisCC->svga.pSvgaR3State)
6100	{
6101	vmsvgaR3StateTerm(pThis, pThisCC);
6102
6103	RTMemFree(pThisCC->svga.pSvgaR3State);
6104	pThisCC->svga.pSvgaR3State = NULL;
6105	}
6106
6107	/*
6108	* Free our resources residing in the VGA state.
6109	*/
6110	if (pThisCC->svga.pbVgaFrameBufferR3)
6111	{
6112	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6113	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6114	}
6115	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6116	{
6117	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6118	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6119	}
6120	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6121	{
6122	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6123	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6124	}
6125
6126	return VINF_SUCCESS;
6127	}
6128
6129	static DECLCALLBACK(size_t) vmsvga3dFloatFormat(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
6130	const char pszType, void const pvValue,
6131	int cchWidth, int cchPrecision, unsigned fFlags, void *pvUser)
6132	{
6133	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
6134	double const v = (double )&pvValue;
6135	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, FLOAT_FMT_STR, FLOAT_FMT_ARGS(v));
6136	}
6137
6138	/**
6139	* Initialize the SVGA hardware state
6140	*
6141	* @returns VBox status code.
6142	* @param pDevIns The device instance.
6143	*/
6144	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6145	{
6146	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6147	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6148	PVMSVGAR3STATE pSVGAState;
6149	int rc;
6150
6151	rc = RTStrFormatTypeRegister("float", vmsvga3dFloatFormat, NULL);
6152	AssertMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_ALREADY_EXISTS, ("%Rrc\n", rc), rc);
6153
6154	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6155	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6156
6157	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6158
6159	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6160	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6161	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6162
6163	/* Create event semaphore. */
6164	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6165	AssertRCReturn(rc, rc);
6166
6167	/* Create event semaphore. */
6168	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6169	AssertRCReturn(rc, rc);
6170
6171	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
6172	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6173
6174	rc = vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
6175	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6176
6177	pSVGAState = pThisCC->svga.pSvgaR3State;
6178
6179	/* Register the write-protected GBO access handler type. */
6180	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6181	vmsvgaR3GboAccessHandler,
6182	NULL, NULL, NULL,
6183	NULL, NULL, NULL,
6184	"VMSVGA GBO", &pSVGAState->hGboAccessHandlerType);
6185	AssertRCReturn(rc, rc);
6186
6187	# ifdef VBOX_WITH_VMSVGA3D
6188	if (pThis->svga.f3DEnabled)
6189	{
6190	/* Load a 3D backend. */
6191	rc = vmsvgaR3Init3dInterfaces(pThisCC);
6192	if (RT_SUCCESS(rc))
6193	rc = pSVGAState->pFuncs3D->pfnInit(pDevIns, pThis, pThisCC);
6194
6195	if (RT_FAILURE(rc))
6196	{
6197	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6198	pThis->svga.f3DEnabled = false;
6199	}
6200	}
6201	# endif
6202
6203	/* Initialize FIFO and register capabilities. */
6204	vmsvgaR3InitCaps(pThis, pThisCC);
6205
6206	/* VRAM tracking is enabled by default during bootup. */
6207	pThis->svga.fVRAMTracking = true;
6208
6209	/* Set up the host bpp. This value is as a default for the programmable
6210	* bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
6211	* exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
6212	* separated as SVGA_REG_HOST_BITS_PER_PIXEL.
6213	*
6214	* NB: The driver cBits value is currently constant for the lifetime of the
6215	* VM. If that changes, the host bpp logic might need revisiting.
6216	*/
6217	pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
6218
6219	/* Invalidate current settings. */
6220	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6221	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6222	pThis->svga.uBpp = pThis->svga.uHostBpp;
6223	pThis->svga.cbScanline = 0;
6224
6225	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_XRES;
6226	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_YRES;
6227	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6228	{
6229	pThis->svga.u32MaxWidth -= 256;
6230	pThis->svga.u32MaxHeight -= 256;
6231	}
6232	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6233
6234	# ifdef DEBUG_GMR_ACCESS
6235	/* Register the GMR access handler type. */
6236	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6237	vmsvgaR3GmrAccessHandler,
6238	NULL, NULL, NULL,
6239	NULL, NULL, NULL,
6240	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6241	AssertRCReturn(rc, rc);
6242	# endif
6243
6244	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6245	/* Register the FIFO access handler type. In addition to
6246	debugging FIFO access, this is also used to facilitate
6247	extended fifo thread sleeps. */
6248	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6249	# ifdef DEBUG_FIFO_ACCESS
6250	PGMPHYSHANDLERKIND_ALL,
6251	# else
6252	PGMPHYSHANDLERKIND_WRITE,
6253	# endif
6254	vmsvgaR3FifoAccessHandler,
6255	NULL, NULL, NULL,
6256	NULL, NULL, NULL,
6257	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6258	AssertRCReturn(rc, rc);
6259	# endif
6260
6261	/* Create the async IO thread. */
6262	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6263	RTTHREADTYPE_IO, "VMSVGA FIFO");
6264	if (RT_FAILURE(rc))
6265	{
6266	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6267	return rc;
6268	}
6269
6270	/*
6271	* Statistics.
6272	*/
6273	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6274	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6275	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6276	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6277	# ifdef VBOX_WITH_STATISTICS
6278	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6279	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6280	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6281	# endif
6282	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6283	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6284	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6285	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6286	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6287	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6288	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6289	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6290	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6291	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6292	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6293	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6294	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6295	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6296	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6297	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6298	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6299	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6300	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6301	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6302	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6303	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6304	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6305	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6306	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6307	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6308	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6309	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6310	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6311	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6312	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6313	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6314	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6315	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6316	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6317	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6318	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6319	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6320	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6321	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6322	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6323	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
6324	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
6325	REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
6326	REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
6327	REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
6328	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6329	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6330	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6331	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6332	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6333	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6334	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6335	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6336	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6337	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6338	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6339	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6340	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6341
6342	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6343	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6344	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6345	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6346	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6347	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6348	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
6349	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
6350	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) writes.");
6351	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
6352	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6353	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6354	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6355	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6356	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6357	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6358	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6359	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6360	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6361	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6362	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6363	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6364	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6365	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6366	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6367	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6368	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6369	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6370	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6371	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6372	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6373	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6374	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6375	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6376	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6377	REG_CNT(&pThis->svga.StatRegCommandLowWr, "VMSVGA/Reg/CommandLowWrite", "SVGA_REG_COMMAND_LOW writes.");
6378	REG_CNT(&pThis->svga.StatRegCommandHighWr, "VMSVGA/Reg/CommandHighWrite", "SVGA_REG_COMMAND_HIGH writes.");
6379	REG_CNT(&pThis->svga.StatRegDevCapWr, "VMSVGA/Reg/DevCapWrite", "SVGA_REG_DEV_CAP writes.");
6380	REG_CNT(&pThis->svga.StatRegCmdPrependLowWr, "VMSVGA/Reg/CmdPrependLowWrite", "SVGA_REG_CMD_PREPEND_LOW writes.");
6381	REG_CNT(&pThis->svga.StatRegCmdPrependHighWr, "VMSVGA/Reg/CmdPrependHighWrite", "SVGA_REG_CMD_PREPEND_HIGH writes.");
6382
6383	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6384	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6385	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6386	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6387	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6388	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6389	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
6390	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
6391	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) reads.");
6392	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
6393	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6394	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6395	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6396	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6397	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6398	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6399	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6400	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6401	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6402	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6403	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6404	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6405	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6406	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6407	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6408	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6409	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6410	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6411	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6412	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6413	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6414	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6415	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6416	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6417	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6418	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6419	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6420	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6421	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6422	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6423	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6424	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6425	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6426	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6427	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6428	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6429	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6430	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6431	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6432	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6433	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6434	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6435	REG_CNT(&pThis->svga.StatRegCommandLowRd, "VMSVGA/Reg/CommandLowRead", "SVGA_REG_COMMAND_LOW reads.");
6436	REG_CNT(&pThis->svga.StatRegCommandHighRd, "VMSVGA/Reg/CommandHighRead", "SVGA_REG_COMMAND_HIGH reads.");
6437	REG_CNT(&pThis->svga.StatRegMaxPrimBBMemRd, "VMSVGA/Reg/MaxPrimBBMemRead", "SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM reads.");
6438	REG_CNT(&pThis->svga.StatRegGBMemSizeRd, "VMSVGA/Reg/GBMemSizeRead", "SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB reads.");
6439	REG_CNT(&pThis->svga.StatRegDevCapRd, "VMSVGA/Reg/DevCapRead", "SVGA_REG_DEV_CAP reads.");
6440	REG_CNT(&pThis->svga.StatRegCmdPrependLowRd, "VMSVGA/Reg/CmdPrependLowRead", "SVGA_REG_CMD_PREPEND_LOW reads.");
6441	REG_CNT(&pThis->svga.StatRegCmdPrependHighRd, "VMSVGA/Reg/CmdPrependHighRead", "SVGA_REG_CMD_PREPEND_HIGH reads.");
6442	REG_CNT(&pThis->svga.StatRegScrnTgtMaxWidthRd, "VMSVGA/Reg/ScrnTgtMaxWidthRead", "SVGA_REG_SCREENTARGET_MAX_WIDTH reads.");
6443	REG_CNT(&pThis->svga.StatRegScrnTgtMaxHeightRd, "VMSVGA/Reg/ScrnTgtMaxHeightRead", "SVGA_REG_SCREENTARGET_MAX_HEIGHT reads.");
6444	REG_CNT(&pThis->svga.StatRegMobMaxSizeRd, "VMSVGA/Reg/MobMaxSizeRead", "SVGA_REG_MOB_MAX_SIZE reads.");
6445
6446	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6447	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6448	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6449	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6450	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6451	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6452	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6453	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6454	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6455	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6456	# endif
6457	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6458	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6459	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6460	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6461	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6462
6463	# undef REG_CNT
6464	# undef REG_PRF
6465
6466	/*
6467	* Info handlers.
6468	*/
6469	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6470	# ifdef VBOX_WITH_VMSVGA3D
6471	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6472	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6473	"VMSVGA 3d surface details. "
6474	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6475	vmsvgaR3Info3dSurface);
6476	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6477	"VMSVGA 3d surface details and bitmap: "
6478	"sid[>dir]",
6479	vmsvgaR3Info3dSurfaceBmp);
6480	# endif
6481
6482	return VINF_SUCCESS;
6483	}
6484
6485	/**
6486	* Power On notification.
6487	*
6488	* @returns VBox status code.
6489	* @param pDevIns The device instance data.
6490	*
6491	* @remarks Caller enters the device critical section.
6492	*/
6493	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6494	{
6495	# ifdef VBOX_WITH_VMSVGA3D
6496	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6497	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6498	if (pThis->svga.f3DEnabled)
6499	{
6500	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6501	int rc = pSVGAState->pFuncs3D->pfnPowerOn(pDevIns, pThis, pThisCC);
6502	if (RT_SUCCESS(rc))
6503	{
6504	/* Initialize FIFO 3D capabilities. */
6505	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
6506	}
6507	else {
6508	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dPowerOn -> %Rrc)\n", rc));
6509	pThis->svga.f3DEnabled = false;
6510	}
6511	}
6512	# else /* !VBOX_WITH_VMSVGA3D */
6513	RT_NOREF(pDevIns);
6514	# endif /* !VBOX_WITH_VMSVGA3D */
6515	}
6516
6517	/**
6518	* Power Off notification.
6519	*
6520	* @param pDevIns The device instance data.
6521	*
6522	* @remarks Caller enters the device critical section.
6523	*/
6524	DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns)
6525	{
6526	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6527	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6528
6529	/*
6530	* Notify the FIFO thread.
6531	*/
6532	if (pThisCC->svga.pFIFOIOThread)
6533	{
6534	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_POWEROFF,
6535	NULL /pvParam/, 30000 /ms/);
6536	AssertLogRelRC(rc);
6537	}
6538	}
6539
6540	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 89153

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