DevVGA-SVGA.cpp@ 80651

Last change on this file since 80651 was 78347, checked in by vboxsync, 6 years ago
DevVGA-SVGA.cpp: attempt to fix breakage from last change.
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1	/* $Id: DevVGA-SVGA.cpp 78347 2019-04-29 12:35:29Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	*/
12
13	/*
14	* Copyright (C) 2013-2019 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.virtualbox.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25
26	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
27	*
28	* This device emulation was contributed by trivirt AG. It offers an
29	* alternative to our Bochs based VGA graphics and 3d emulations. This is
30	* valuable for Xorg based guests, as there is driver support shipping with Xorg
31	* since it forked from XFree86.
32	*
33	*
34	* @section sec_dev_vmsvga_sdk The VMware SDK
35	*
36	* This is officially deprecated now, however it's still quite useful,
37	* especially for getting the old features working:
38	* http://vmware-svga.sourceforge.net/
39	*
40	* They currently point developers at the following resources.
41	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
42	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
43	* - http://cgit.freedesktop.org/mesa/vmwgfx/
44	*
45	* @subsection subsec_dev_vmsvga_sdk_results Test results
46	*
47	* Test results:
48	* - 2dmark.img:
49	* + todo
50	* - backdoor-tclo.img:
51	* + todo
52	* - blit-cube.img:
53	* + todo
54	* - bunnies.img:
55	* + todo
56	* - cube.img:
57	* + todo
58	* - cubemark.img:
59	* + todo
60	* - dynamic-vertex-stress.img:
61	* + todo
62	* - dynamic-vertex.img:
63	* + todo
64	* - fence-stress.img:
65	* + todo
66	* - gmr-test.img:
67	* + todo
68	* - half-float-test.img:
69	* + todo
70	* - noscreen-cursor.img:
71	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
72	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
73	* visible though.)
74	* - Cursor animation via the palette doesn't work.
75	* - During debugging, it turns out that the framebuffer content seems to
76	* be halfways ignore or something (memset(fb, 0xcc, lots)).
77	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
78	* grow it 0x10 fold (128KB -> 2MB like in WS10).
79	* - null.img:
80	* + todo
81	* - pong.img:
82	* + todo
83	* - presentReadback.img:
84	* + todo
85	* - resolution-set.img:
86	* + todo
87	* - rt-gamma-test.img:
88	* + todo
89	* - screen-annotation.img:
90	* + todo
91	* - screen-cursor.img:
92	* + todo
93	* - screen-dma-coalesce.img:
94	* + todo
95	* - screen-gmr-discontig.img:
96	* + todo
97	* - screen-gmr-remap.img:
98	* + todo
99	* - screen-multimon.img:
100	* + todo
101	* - screen-present-clip.img:
102	* + todo
103	* - screen-render-test.img:
104	* + todo
105	* - screen-simple.img:
106	* + todo
107	* - screen-text.img:
108	* + todo
109	* - simple-shaders.img:
110	* + todo
111	* - simple_blit.img:
112	* + todo
113	* - tiny-2d-updates.img:
114	* + todo
115	* - video-formats.img:
116	* + todo
117	* - video-sync.img:
118	* + todo
119	*
120	*/
121
122
123	/*********************************************************************************************************************************
124	* Header Files *
125	*********************************************************************************************************************************/
126	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
127	#define VMSVGA_USE_EMT_HALT_CODE
128	#include <VBox/vmm/pdmdev.h>
129	#include <VBox/version.h>
130	#include <VBox/err.h>
131	#include <VBox/log.h>
132	#include <VBox/vmm/pgm.h>
133	#ifdef VMSVGA_USE_EMT_HALT_CODE
134	# include <VBox/vmm/vmapi.h>
135	# include <VBox/vmm/vmcpuset.h>
136	#endif
137	#include <VBox/sup.h>
138
139	#include <iprt/assert.h>
140	#include <iprt/semaphore.h>
141	#include <iprt/uuid.h>
142	#ifdef IN_RING3
143	# include <iprt/ctype.h>
144	# include <iprt/mem.h>
145	# ifdef VBOX_STRICT
146	# include <iprt/time.h>
147	# endif
148	#endif
149
150	#include <VBox/AssertGuest.h>
151	#include <VBox/VMMDev.h>
152	#include <VBoxVideo.h>
153	#include <VBox/bioslogo.h>
154
155	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
156	#include "DevVGA.h"
157
158	#include "DevVGA-SVGA.h"
159	#include "vmsvga/svga_escape.h"
160	#include "vmsvga/svga_overlay.h"
161	#include "vmsvga/svga3d_caps.h"
162	#ifdef VBOX_WITH_VMSVGA3D
163	# include "DevVGA-SVGA3d.h"
164	# ifdef RT_OS_DARWIN
165	# include "DevVGA-SVGA3d-cocoa.h"
166	# endif
167	#endif
168
169
170	/*********************************************************************************************************************************
171	* Defined Constants And Macros *
172	*********************************************************************************************************************************/
173	/**
174	* Macro for checking if a fixed FIFO register is valid according to the
175	* current FIFO configuration.
176	*
177	* @returns true / false.
178	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
179	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
180	*/
181	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
182
183
184	/*********************************************************************************************************************************
185	* Structures and Typedefs *
186	*********************************************************************************************************************************/
187	/**
188	* 64-bit GMR descriptor.
189	*/
190	typedef struct
191	{
192	RTGCPHYS GCPhys;
193	uint64_t numPages;
194	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
195
196	/**
197	* GMR slot
198	*/
199	typedef struct
200	{
201	uint32_t cMaxPages;
202	uint32_t cbTotal;
203	uint32_t numDescriptors;
204	PVMSVGAGMRDESCRIPTOR paDesc;
205	} GMR, *PGMR;
206
207	#ifdef IN_RING3
208	/**
209	* Internal SVGA ring-3 only state.
210	*/
211	typedef struct VMSVGAR3STATE
212	{
213	GMR *paGMR; // [VMSVGAState::cGMR]
214	struct
215	{
216	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
217	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
218	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
219	} GMRFB;
220	struct
221	{
222	bool fActive;
223	uint32_t xHotspot;
224	uint32_t yHotspot;
225	uint32_t width;
226	uint32_t height;
227	uint32_t cbData;
228	void *pData;
229	} Cursor;
230	SVGAColorBGRX colorAnnotation;
231
232	# ifdef VMSVGA_USE_EMT_HALT_CODE
233	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
234	uint32_t volatile cBusyDelayedEmts;
235	/** Set of EMTs that are */
236	VMCPUSET BusyDelayedEmts;
237	# else
238	/** Number of EMTs waiting on hBusyDelayedEmts. */
239	uint32_t volatile cBusyDelayedEmts;
240	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
241	* busy (ugly). */
242	RTSEMEVENTMULTI hBusyDelayedEmts;
243	# endif
244
245	/** Information obout screens. */
246	VMSVGASCREENOBJECT aScreens[64];
247
248	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
249	STAMPROFILE StatBusyDelayEmts;
250
251	STAMPROFILE StatR3Cmd3dPresentProf;
252	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
253	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
254	STAMCOUNTER StatR3CmdDefineGmr2;
255	STAMCOUNTER StatR3CmdDefineGmr2Free;
256	STAMCOUNTER StatR3CmdDefineGmr2Modify;
257	STAMCOUNTER StatR3CmdRemapGmr2;
258	STAMCOUNTER StatR3CmdRemapGmr2Modify;
259	STAMCOUNTER StatR3CmdInvalidCmd;
260	STAMCOUNTER StatR3CmdFence;
261	STAMCOUNTER StatR3CmdUpdate;
262	STAMCOUNTER StatR3CmdUpdateVerbose;
263	STAMCOUNTER StatR3CmdDefineCursor;
264	STAMCOUNTER StatR3CmdDefineAlphaCursor;
265	STAMCOUNTER StatR3CmdEscape;
266	STAMCOUNTER StatR3CmdDefineScreen;
267	STAMCOUNTER StatR3CmdDestroyScreen;
268	STAMCOUNTER StatR3CmdDefineGmrFb;
269	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
270	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
271	STAMCOUNTER StatR3CmdAnnotationFill;
272	STAMCOUNTER StatR3CmdAnnotationCopy;
273	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
274	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
275	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
276	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
277	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
278	STAMCOUNTER StatR3Cmd3dSurfaceDma;
279	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
280	STAMCOUNTER StatR3Cmd3dContextDefine;
281	STAMCOUNTER StatR3Cmd3dContextDestroy;
282	STAMCOUNTER StatR3Cmd3dSetTransform;
283	STAMCOUNTER StatR3Cmd3dSetZRange;
284	STAMCOUNTER StatR3Cmd3dSetRenderState;
285	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
286	STAMCOUNTER StatR3Cmd3dSetTextureState;
287	STAMCOUNTER StatR3Cmd3dSetMaterial;
288	STAMCOUNTER StatR3Cmd3dSetLightData;
289	STAMCOUNTER StatR3Cmd3dSetLightEnable;
290	STAMCOUNTER StatR3Cmd3dSetViewPort;
291	STAMCOUNTER StatR3Cmd3dSetClipPlane;
292	STAMCOUNTER StatR3Cmd3dClear;
293	STAMCOUNTER StatR3Cmd3dPresent;
294	STAMCOUNTER StatR3Cmd3dPresentReadBack;
295	STAMCOUNTER StatR3Cmd3dShaderDefine;
296	STAMCOUNTER StatR3Cmd3dShaderDestroy;
297	STAMCOUNTER StatR3Cmd3dSetShader;
298	STAMCOUNTER StatR3Cmd3dSetShaderConst;
299	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
300	STAMCOUNTER StatR3Cmd3dSetScissorRect;
301	STAMCOUNTER StatR3Cmd3dBeginQuery;
302	STAMCOUNTER StatR3Cmd3dEndQuery;
303	STAMCOUNTER StatR3Cmd3dWaitForQuery;
304	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
305	STAMCOUNTER StatR3Cmd3dActivateSurface;
306	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
307
308	STAMCOUNTER StatR3RegConfigDoneWr;
309	STAMCOUNTER StatR3RegGmrDescriptorWr;
310	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
311	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
312
313	STAMCOUNTER StatFifoCommands;
314	STAMCOUNTER StatFifoErrors;
315	STAMCOUNTER StatFifoUnkCmds;
316	STAMCOUNTER StatFifoTodoTimeout;
317	STAMCOUNTER StatFifoTodoWoken;
318	STAMPROFILE StatFifoStalls;
319	STAMPROFILE StatFifoExtendedSleep;
320	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
321	STAMCOUNTER StatFifoAccessHandler;
322	# endif
323	STAMCOUNTER StatFifoCursorFetchAgain;
324	STAMCOUNTER StatFifoCursorNoChange;
325	STAMCOUNTER StatFifoCursorPosition;
326	STAMCOUNTER StatFifoCursorVisiblity;
327	STAMCOUNTER StatFifoWatchdogWakeUps;
328	} VMSVGAR3STATE, *PVMSVGAR3STATE;
329	#endif /* IN_RING3 */
330
331
332	/*********************************************************************************************************************************
333	* Internal Functions *
334	*********************************************************************************************************************************/
335	#ifdef IN_RING3
336	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
337	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
338	# endif
339	# ifdef DEBUG_GMR_ACCESS
340	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
341	# endif
342	#endif
343
344
345	/*********************************************************************************************************************************
346	* Global Variables *
347	*********************************************************************************************************************************/
348	#ifdef IN_RING3
349
350	/**
351	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
352	*/
353	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
354	{
355	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
356	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
357	SSMFIELD_ENTRY_TERM()
358	};
359
360	/**
361	* SSM descriptor table for the GMR structure.
362	*/
363	static SSMFIELD const g_aGMRFields[] =
364	{
365	SSMFIELD_ENTRY( GMR, cMaxPages),
366	SSMFIELD_ENTRY( GMR, cbTotal),
367	SSMFIELD_ENTRY( GMR, numDescriptors),
368	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
369	SSMFIELD_ENTRY_TERM()
370	};
371
372	/**
373	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
374	*/
375	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
376	{
377	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
378	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
379	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
380	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
381	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
388	SSMFIELD_ENTRY_TERM()
389	};
390
391	/**
392	* SSM descriptor table for the VMSVGAR3STATE structure.
393	*/
394	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
395	{
396	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
397	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
398	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
399	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
400	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
401	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
404	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
405	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
406	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
407	#ifdef VMSVGA_USE_EMT_HALT_CODE
408	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
409	#else
410	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
411	#endif
412	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
469
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
474
475	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
482	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
484	# endif
485	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
489
490	SSMFIELD_ENTRY_TERM()
491	};
492
493	/**
494	* SSM descriptor table for the VGAState.svga structure.
495	*/
496	static SSMFIELD const g_aVGAStateSVGAFields[] =
497	{
498	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
499	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
500	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
501	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
502	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
503	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
504	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
505	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
507	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
508	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
509	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
510	SSMFIELD_ENTRY( VMSVGAState, fBusy),
511	SSMFIELD_ENTRY( VMSVGAState, fTraces),
512	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
513	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
514	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
515	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
516	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
517	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
518	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
519	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
520	SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
521	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
523	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
524	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
525	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
526	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
527	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
528	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
529	SSMFIELD_ENTRY( VMSVGAState, uWidth),
530	SSMFIELD_ENTRY( VMSVGAState, uHeight),
531	SSMFIELD_ENTRY( VMSVGAState, uBpp),
532	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
533	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
534	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
535	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
536	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
537	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
538	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
539	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
540	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
541	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
542	SSMFIELD_ENTRY_TERM()
543	};
544
545	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
546	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
547	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM);
548
549	VMSVGASCREENOBJECT *vmsvgaGetScreenObject(PVGASTATE pThis, uint32_t idScreen)
550	{
551	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
552	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
553	&& pSVGAState
554	&& pSVGAState->aScreens[idScreen].fDefined)
555	{
556	return &pSVGAState->aScreens[idScreen];
557	}
558	return NULL;
559	}
560
561	#endif /* IN_RING3 */
562
563	#ifdef LOG_ENABLED
564
565	/**
566	* Index register string name lookup
567	*
568	* @returns Index register string or "UNKNOWN"
569	* @param pThis VMSVGA State
570	* @param idxReg The index register.
571	*/
572	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
573	{
574	switch (idxReg)
575	{
576	case SVGA_REG_ID: return "SVGA_REG_ID";
577	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
578	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
579	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
580	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
581	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
582	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
583	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
584	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
585	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
586	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
587	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
588	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
589	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
590	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
591	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
592	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
593	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
594	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
595	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
596	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
597	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
598	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
599	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
600	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
601	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
602	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
603	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
604	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
605	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
606	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
607	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
608	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
609	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
610	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
611	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
612	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
613	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
614	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
615	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
616	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
617	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
618	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
619	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
620	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
621	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
622	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
623	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
624	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
625	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
626
627	default:
628	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
629	return "SVGA_SCRATCH_BASE reg";
630	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
631	return "SVGA_PALETTE_BASE reg";
632	return "UNKNOWN";
633	}
634	}
635
636	#ifdef IN_RING3
637	/**
638	* FIFO command name lookup
639	*
640	* @returns FIFO command string or "UNKNOWN"
641	* @param u32Cmd FIFO command
642	*/
643	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
644	{
645	switch (u32Cmd)
646	{
647	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
648	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
649	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
650	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
651	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
652	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
653	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
654	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
655	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
656	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
657	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
658	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
659	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
660	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
661	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
662	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
663	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
664	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
665	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
666	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
667	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
668	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
669	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
670	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
671	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
672	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
673	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
674	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
675	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
676	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
677	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
678	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
679	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
680	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
681	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
682	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
683	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
684	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
685	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
686	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
687	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
688	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
689	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
690	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
691	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
692	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
693	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
694	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
695	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
696	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
697	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
698	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
699	default: return "UNKNOWN";
700	}
701	}
702	# endif /* IN_RING3 */
703
704	#endif /* LOG_ENABLED */
705
706	#ifdef IN_RING3
707	/**
708	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
709	*/
710	DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
711	{
712	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
713
714	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
715	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
716
717	/** @todo Test how it interacts with multiple screen objects. */
718	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, idScreen);
719	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
720	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
721
722	if (x < uWidth)
723	{
724	pThis->svga.viewport.x = x;
725	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
726	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
727	}
728	else
729	{
730	pThis->svga.viewport.x = uWidth;
731	pThis->svga.viewport.cx = 0;
732	pThis->svga.viewport.xRight = uWidth;
733	}
734	if (y < uHeight)
735	{
736	pThis->svga.viewport.y = y;
737	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
738	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
739	pThis->svga.viewport.yHighWC = uHeight - y;
740	}
741	else
742	{
743	pThis->svga.viewport.y = uHeight;
744	pThis->svga.viewport.cy = 0;
745	pThis->svga.viewport.yLowWC = 0;
746	pThis->svga.viewport.yHighWC = 0;
747	}
748
749	# ifdef VBOX_WITH_VMSVGA3D
750	/*
751	* Now inform the 3D backend.
752	*/
753	if (pThis->svga.f3DEnabled)
754	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
755	# else
756	RT_NOREF(OldViewport);
757	# endif
758	}
759	#endif /* IN_RING3 */
760
761	/**
762	* Read port register
763	*
764	* @returns VBox status code.
765	* @param pThis VMSVGA State
766	* @param pu32 Where to store the read value
767	*/
768	PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
769	{
770	int rc = VINF_SUCCESS;
771	*pu32 = 0;
772
773	/* Rough index register validation. */
774	uint32_t idxReg = pThis->svga.u32IndexReg;
775	#if !defined(IN_RING3) && defined(VBOX_STRICT)
776	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
777	VINF_IOM_R3_IOPORT_READ);
778	#else
779	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
780	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
781	VINF_SUCCESS);
782	#endif
783	RT_UNTRUSTED_VALIDATED_FENCE();
784
785	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
786	if ( idxReg >= SVGA_REG_CAPABILITIES
787	&& pThis->svga.u32SVGAId == SVGA_ID_0)
788	{
789	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
790	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
791	}
792
793	switch (idxReg)
794	{
795	case SVGA_REG_ID:
796	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
797	*pu32 = pThis->svga.u32SVGAId;
798	break;
799
800	case SVGA_REG_ENABLE:
801	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
802	*pu32 = pThis->svga.fEnabled;
803	break;
804
805	case SVGA_REG_WIDTH:
806	{
807	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
808	if ( pThis->svga.fEnabled
809	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
810	{
811	*pu32 = pThis->svga.uWidth;
812	}
813	else
814	{
815	#ifndef IN_RING3
816	rc = VINF_IOM_R3_IOPORT_READ;
817	#else
818	*pu32 = pThis->pDrv->cx;
819	#endif
820	}
821	break;
822	}
823
824	case SVGA_REG_HEIGHT:
825	{
826	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
827	if ( pThis->svga.fEnabled
828	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
829	{
830	*pu32 = pThis->svga.uHeight;
831	}
832	else
833	{
834	#ifndef IN_RING3
835	rc = VINF_IOM_R3_IOPORT_READ;
836	#else
837	*pu32 = pThis->pDrv->cy;
838	#endif
839	}
840	break;
841	}
842
843	case SVGA_REG_MAX_WIDTH:
844	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
845	*pu32 = pThis->svga.u32MaxWidth;
846	break;
847
848	case SVGA_REG_MAX_HEIGHT:
849	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
850	*pu32 = pThis->svga.u32MaxHeight;
851	break;
852
853	case SVGA_REG_DEPTH:
854	/* This returns the color depth of the current mode. */
855	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
856	switch (pThis->svga.uBpp)
857	{
858	case 15:
859	case 16:
860	case 24:
861	*pu32 = pThis->svga.uBpp;
862	break;
863
864	default:
865	case 32:
866	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
867	break;
868	}
869	break;
870
871	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
872	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
873	if ( pThis->svga.fEnabled
874	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
875	{
876	*pu32 = pThis->svga.uBpp;
877	}
878	else
879	{
880	#ifndef IN_RING3
881	rc = VINF_IOM_R3_IOPORT_READ;
882	#else
883	*pu32 = pThis->pDrv->cBits;
884	#endif
885	}
886	break;
887
888	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
889	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
890	if ( pThis->svga.fEnabled
891	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
892	{
893	*pu32 = (pThis->svga.uBpp + 7) & ~7;
894	}
895	else
896	{
897	#ifndef IN_RING3
898	rc = VINF_IOM_R3_IOPORT_READ;
899	#else
900	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
901	#endif
902	}
903	break;
904
905	case SVGA_REG_PSEUDOCOLOR:
906	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
907	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
908	break;
909
910	case SVGA_REG_RED_MASK:
911	case SVGA_REG_GREEN_MASK:
912	case SVGA_REG_BLUE_MASK:
913	{
914	uint32_t uBpp;
915
916	if ( pThis->svga.fEnabled
917	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
918	{
919	uBpp = pThis->svga.uBpp;
920	}
921	else
922	{
923	#ifndef IN_RING3
924	rc = VINF_IOM_R3_IOPORT_READ;
925	break;
926	#else
927	uBpp = pThis->pDrv->cBits;
928	#endif
929	}
930	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
931	switch (uBpp)
932	{
933	case 8:
934	u32RedMask = 0x07;
935	u32GreenMask = 0x38;
936	u32BlueMask = 0xc0;
937	break;
938
939	case 15:
940	u32RedMask = 0x0000001f;
941	u32GreenMask = 0x000003e0;
942	u32BlueMask = 0x00007c00;
943	break;
944
945	case 16:
946	u32RedMask = 0x0000001f;
947	u32GreenMask = 0x000007e0;
948	u32BlueMask = 0x0000f800;
949	break;
950
951	case 24:
952	case 32:
953	default:
954	u32RedMask = 0x00ff0000;
955	u32GreenMask = 0x0000ff00;
956	u32BlueMask = 0x000000ff;
957	break;
958	}
959	switch (idxReg)
960	{
961	case SVGA_REG_RED_MASK:
962	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
963	*pu32 = u32RedMask;
964	break;
965
966	case SVGA_REG_GREEN_MASK:
967	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
968	*pu32 = u32GreenMask;
969	break;
970
971	case SVGA_REG_BLUE_MASK:
972	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
973	*pu32 = u32BlueMask;
974	break;
975	}
976	break;
977	}
978
979	case SVGA_REG_BYTES_PER_LINE:
980	{
981	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
982	if ( pThis->svga.fEnabled
983	&& pThis->svga.cbScanline)
984	{
985	*pu32 = pThis->svga.cbScanline;
986	}
987	else
988	{
989	#ifndef IN_RING3
990	rc = VINF_IOM_R3_IOPORT_READ;
991	#else
992	*pu32 = pThis->pDrv->cbScanline;
993	#endif
994	}
995	break;
996	}
997
998	case SVGA_REG_VRAM_SIZE: /* VRAM size */
999	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1000	*pu32 = pThis->vram_size;
1001	break;
1002
1003	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1004	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1005	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1006	*pu32 = pThis->GCPhysVRAM;
1007	break;
1008
1009	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1010	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1011	/* Always zero in our case. */
1012	*pu32 = 0;
1013	break;
1014
1015	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1016	{
1017	#ifndef IN_RING3
1018	rc = VINF_IOM_R3_IOPORT_READ;
1019	#else
1020	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1021
1022	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1023	if ( pThis->svga.fEnabled
1024	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1025	{
1026	/* Hardware enabled; return real framebuffer size .*/
1027	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1028	}
1029	else
1030	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
1031
1032	pu32 = RT_MIN(pThis->vram_size, pu32);
1033	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
1034	#endif
1035	break;
1036	}
1037
1038	case SVGA_REG_CAPABILITIES:
1039	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1040	*pu32 = pThis->svga.u32RegCaps;
1041	break;
1042
1043	case SVGA_REG_MEM_START: /* FIFO start */
1044	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1045	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1046	*pu32 = pThis->svga.GCPhysFIFO;
1047	break;
1048
1049	case SVGA_REG_MEM_SIZE: /* FIFO size */
1050	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1051	*pu32 = pThis->svga.cbFIFO;
1052	break;
1053
1054	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1055	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1056	*pu32 = pThis->svga.fConfigured;
1057	break;
1058
1059	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1060	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1061	*pu32 = 0;
1062	break;
1063
1064	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1065	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1066	if (pThis->svga.fBusy)
1067	{
1068	#ifndef IN_RING3
1069	/* Go to ring-3 and halt the CPU. */
1070	rc = VINF_IOM_R3_IOPORT_READ;
1071	break;
1072	#else
1073	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1074	/* The guest is basically doing a HLT via the device here, but with
1075	a special wake up condition on FIFO completion. */
1076	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1077	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1078	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1079	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1080	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1081	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1082	if (pThis->svga.fBusy)
1083	{
1084	PDMCritSectLeave(&pThis->CritSect); /* hack around lock order issue. */
1085	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1086	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1087	}
1088	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1089	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1090	# else
1091
1092	/* Delay the EMT a bit so the FIFO and others can get some work done.
1093	This used to be a crude 50 ms sleep. The current code tries to be
1094	more efficient, but the consept is still very crude. */
1095	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1096	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1097	RTThreadYield();
1098	if (pThis->svga.fBusy)
1099	{
1100	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1101
1102	if (pThis->svga.fBusy && cRefs == 1)
1103	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1104	if (pThis->svga.fBusy)
1105	{
1106	/** @todo If this code is going to stay, we need to call into the halt/wait
1107	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1108	* suffer when the guest is polling on a busy FIFO. */
1109	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1110	if (cNsMaxWait >= RT_NS_100US)
1111	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1112	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1113	RT_MIN(cNsMaxWait, RT_NS_10MS));
1114	}
1115
1116	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1117	}
1118	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1119	# endif
1120	*pu32 = pThis->svga.fBusy != 0;
1121	#endif
1122	}
1123	else
1124	*pu32 = false;
1125	break;
1126
1127	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1128	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1129	*pu32 = pThis->svga.u32GuestId;
1130	break;
1131
1132	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1133	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1134	*pu32 = pThis->svga.cScratchRegion;
1135	break;
1136
1137	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1138	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1139	*pu32 = SVGA_FIFO_NUM_REGS;
1140	break;
1141
1142	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1143	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1144	*pu32 = pThis->svga.u32PitchLock;
1145	break;
1146
1147	case SVGA_REG_IRQMASK: /* Interrupt mask */
1148	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1149	*pu32 = pThis->svga.u32IrqMask;
1150	break;
1151
1152	/* See "Guest memory regions" below. */
1153	case SVGA_REG_GMR_ID:
1154	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1155	*pu32 = pThis->svga.u32CurrentGMRId;
1156	break;
1157
1158	case SVGA_REG_GMR_DESCRIPTOR:
1159	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1160	/* Write only */
1161	*pu32 = 0;
1162	break;
1163
1164	case SVGA_REG_GMR_MAX_IDS:
1165	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1166	*pu32 = pThis->svga.cGMR;
1167	break;
1168
1169	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1170	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1171	*pu32 = VMSVGA_MAX_GMR_PAGES;
1172	break;
1173
1174	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1175	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1176	*pu32 = pThis->svga.fTraces;
1177	break;
1178
1179	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1180	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1181	*pu32 = VMSVGA_MAX_GMR_PAGES;
1182	break;
1183
1184	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1185	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1186	*pu32 = VMSVGA_SURFACE_SIZE;
1187	break;
1188
1189	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1190	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1191	break;
1192
1193	/* Mouse cursor support. */
1194	case SVGA_REG_CURSOR_ID:
1195	case SVGA_REG_CURSOR_X:
1196	case SVGA_REG_CURSOR_Y:
1197	case SVGA_REG_CURSOR_ON:
1198	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1199	break;
1200
1201	/* Legacy multi-monitor support */
1202	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1203	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1204	*pu32 = 1;
1205	break;
1206
1207	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1208	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1209	*pu32 = 0;
1210	break;
1211
1212	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1213	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1214	*pu32 = 0;
1215	break;
1216
1217	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1218	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1219	*pu32 = 0;
1220	break;
1221
1222	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1223	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1224	*pu32 = 0;
1225	break;
1226
1227	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1228	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1229	*pu32 = pThis->svga.uWidth;
1230	break;
1231
1232	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1233	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1234	*pu32 = pThis->svga.uHeight;
1235	break;
1236
1237	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1238	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1239	/* We must return something sensible here otherwise the Linux driver
1240	will take a legacy code path without 3d support. This number also
1241	limits how many screens Linux guests will allow. */
1242	*pu32 = pThis->cMonitors;
1243	break;
1244
1245	default:
1246	{
1247	uint32_t offReg;
1248	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1249	{
1250	RT_UNTRUSTED_VALIDATED_FENCE();
1251	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1252	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1253	}
1254	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1255	{
1256	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1257	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1258	RT_UNTRUSTED_VALIDATED_FENCE();
1259	uint32_t u32 = pThis->last_palette[offReg / 3];
1260	switch (offReg % 3)
1261	{
1262	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1263	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1264	case 2: pu32 = u32 & 0xff; break; / blue */
1265	}
1266	}
1267	else
1268	{
1269	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1270	rc = VINF_IOM_R3_IOPORT_READ;
1271	#else
1272	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1273
1274	/* Do not assert. The guest might be reading all registers. */
1275	LogFunc(("Unknown reg=%#x\n", idxReg));
1276	#endif
1277	}
1278	break;
1279	}
1280	}
1281	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1282	return rc;
1283	}
1284
1285	#ifdef IN_RING3
1286	/**
1287	* Apply the current resolution settings to change the video mode.
1288	*
1289	* @returns VBox status code.
1290	* @param pThis VMSVGA State
1291	*/
1292	static int vmsvgaChangeMode(PVGASTATE pThis)
1293	{
1294	int rc;
1295
1296	/* Always do changemode on FIFO thread. */
1297	Assert(RTThreadSelf() == pThis->svga.pFIFOIOThread->Thread);
1298
1299	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1300
1301	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1302
1303	if (pThis->svga.fGFBRegisters)
1304	{
1305	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1306	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1307	* deletes all screens other than screen #0, and redefines screen
1308	* #0 according to the specified mode. Drivers that use
1309	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1310	*/
1311
1312	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1313	pScreen->fDefined = true;
1314	pScreen->fModified = true;
1315	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1316	pScreen->idScreen = 0;
1317	pScreen->xOrigin = 0;
1318	pScreen->yOrigin = 0;
1319	pScreen->offVRAM = 0;
1320	pScreen->cbPitch = pThis->svga.cbScanline;
1321	pScreen->cWidth = pThis->svga.uWidth;
1322	pScreen->cHeight = pThis->svga.uHeight;
1323	pScreen->cBpp = pThis->svga.uBpp;
1324
1325	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1326	{
1327	/* Delete screen. */
1328	pScreen = &pSVGAState->aScreens[iScreen];
1329	if (pScreen->fDefined)
1330	{
1331	pScreen->fModified = true;
1332	pScreen->fDefined = false;
1333	}
1334	}
1335	}
1336	else
1337	{
1338	/* "If Screen Objects are supported, they can be used to fully
1339	* replace the functionality provided by the framebuffer registers
1340	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1341	*/
1342	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1343	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1344	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1345	}
1346
1347	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1348	{
1349	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1350	if (!pScreen->fModified)
1351	continue;
1352
1353	pScreen->fModified = false;
1354
1355	VBVAINFOVIEW view;
1356	RT_ZERO(view);
1357	view.u32ViewIndex = pScreen->idScreen;
1358	// view.u32ViewOffset = 0;
1359	view.u32ViewSize = pThis->vram_size;
1360	view.u32MaxScreenSize = pThis->vram_size;
1361
1362	VBVAINFOSCREEN screen;
1363	RT_ZERO(screen);
1364	screen.u32ViewIndex = pScreen->idScreen;
1365
1366	if (pScreen->fDefined)
1367	{
1368	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1369	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1370	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1371	{
1372	Assert(pThis->svga.fGFBRegisters);
1373	continue;
1374	}
1375
1376	screen.i32OriginX = pScreen->xOrigin;
1377	screen.i32OriginY = pScreen->yOrigin;
1378	screen.u32StartOffset = pScreen->offVRAM;
1379	screen.u32LineSize = pScreen->cbPitch;
1380	screen.u32Width = pScreen->cWidth;
1381	screen.u32Height = pScreen->cHeight;
1382	screen.u16BitsPerPixel = pScreen->cBpp;
1383	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1384	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1385	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1386	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1387	}
1388	else
1389	{
1390	/* Screen is destroyed. */
1391	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1392	}
1393
1394	rc = pThis->pDrv->pfnVBVAResize(pThis->pDrv, &view, &screen, pThis->CTX_SUFF(vram_ptr), /fResetInputMapping=/ true);
1395	AssertRC(rc);
1396	}
1397
1398	/* Last stuff. For the VGA device screenshot. */
1399	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1400	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1401	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1402	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1403	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1404
1405	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1406	if ( pThis->svga.viewport.cx == 0
1407	&& pThis->svga.viewport.cy == 0)
1408	{
1409	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1410	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1411	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1412	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1413	pThis->svga.viewport.yLowWC = 0;
1414	}
1415
1416	return VINF_SUCCESS;
1417	}
1418
1419	int vmsvgaUpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1420	{
1421	VBVACMDHDR cmd;
1422	cmd.x = (int16_t)(pScreen->xOrigin + x);
1423	cmd.y = (int16_t)(pScreen->yOrigin + y);
1424	cmd.w = (uint16_t)w;
1425	cmd.h = (uint16_t)h;
1426
1427	pThis->pDrv->pfnVBVAUpdateBegin(pThis->pDrv, pScreen->idScreen);
1428	pThis->pDrv->pfnVBVAUpdateProcess(pThis->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1429	pThis->pDrv->pfnVBVAUpdateEnd(pThis->pDrv, pScreen->idScreen,
1430	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1431
1432	return VINF_SUCCESS;
1433	}
1434
1435	#endif /* IN_RING3 */
1436
1437	#if defined(IN_RING0) \|\| defined(IN_RING3)
1438	/**
1439	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1440	*
1441	* @param pThis The VMSVGA state.
1442	* @param fState The busy state.
1443	*/
1444	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1445	{
1446	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1447
1448	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1449	{
1450	/* Race / unfortunately scheduling. Highly unlikly. */
1451	uint32_t cLoops = 64;
1452	do
1453	{
1454	ASMNopPause();
1455	fState = (pThis->svga.fBusy != 0);
1456	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1457	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1458	}
1459	}
1460
1461
1462	/**
1463	* Update the scanline pitch in response to the guest changing mode
1464	* width/bpp.
1465	*
1466	* @param pThis VMSVGA State
1467	*/
1468	DECLINLINE(void) vmsvgaUpdatePitch(PVGASTATE pThis)
1469	{
1470	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.CTX_SUFF(pFIFO);
1471	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1472	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1473	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1474
1475	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1476	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1477	* location but it has a different meaning.
1478	*/
1479	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1480	uFifoPitchLock = 0;
1481
1482	/* Sanitize values. */
1483	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1484	uFifoPitchLock = 0;
1485	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1486	uRegPitchLock = 0;
1487
1488	/* Prefer the register value to the FIFO value.*/
1489	if (uRegPitchLock)
1490	pThis->svga.cbScanline = uRegPitchLock;
1491	else if (uFifoPitchLock)
1492	pThis->svga.cbScanline = uFifoPitchLock;
1493	else
1494	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1495
1496	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1497	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1498	}
1499	#endif
1500
1501
1502	/**
1503	* Write port register
1504	*
1505	* @returns VBox status code.
1506	* @param pThis VMSVGA State
1507	* @param u32 Value to write
1508	*/
1509	PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1510	{
1511	#ifdef IN_RING3
1512	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1513	#endif
1514	int rc = VINF_SUCCESS;
1515
1516	/* Rough index register validation. */
1517	uint32_t idxReg = pThis->svga.u32IndexReg;
1518	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1519	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1520	VINF_IOM_R3_IOPORT_WRITE);
1521	#else
1522	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1523	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1524	VINF_SUCCESS);
1525	#endif
1526	RT_UNTRUSTED_VALIDATED_FENCE();
1527
1528	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1529	if ( idxReg >= SVGA_REG_CAPABILITIES
1530	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1531	{
1532	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1533	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1534	}
1535	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1536	/* Check if the guest uses legacy registers. See vmsvgaChangeMode */
1537	switch (idxReg)
1538	{
1539	case SVGA_REG_WIDTH:
1540	case SVGA_REG_HEIGHT:
1541	case SVGA_REG_PITCHLOCK:
1542	case SVGA_REG_BITS_PER_PIXEL:
1543	pThis->svga.fGFBRegisters = true;
1544	break;
1545	default:
1546	break;
1547	}
1548
1549	switch (idxReg)
1550	{
1551	case SVGA_REG_ID:
1552	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1553	if ( u32 == SVGA_ID_0
1554	\|\| u32 == SVGA_ID_1
1555	\|\| u32 == SVGA_ID_2)
1556	pThis->svga.u32SVGAId = u32;
1557	else
1558	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1559	break;
1560
1561	case SVGA_REG_ENABLE:
1562	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1563	#ifdef IN_RING3
1564	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1565	&& pThis->svga.fEnabled == false)
1566	{
1567	/* Make a backup copy of the first 512kb in order to save font data etc. */
1568	/** @todo should probably swap here, rather than copy + zero */
1569	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1570	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1571	}
1572
1573	pThis->svga.fEnabled = u32;
1574	if (pThis->svga.fEnabled)
1575	{
1576	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1577	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1578	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1579	{
1580	/* Keep the current mode. */
1581	pThis->svga.uWidth = pThis->pDrv->cx;
1582	pThis->svga.uHeight = pThis->pDrv->cy;
1583	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1584	}
1585
1586	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1587	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1588	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1589	{
1590	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1591	}
1592	# ifdef LOG_ENABLED
1593	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1594	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1595	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1596	# endif
1597
1598	/* Disable or enable dirty page tracking according to the current fTraces value. */
1599	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1600
1601	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1602	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1603	pThis->pDrv->pfnVBVAEnable(pThis->pDrv, idScreen, NULL /pHostFlags/, false /fRenderThreadMode/);
1604	}
1605	else
1606	{
1607	/* Restore the text mode backup. */
1608	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1609
1610	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1611
1612	/* Enable dirty page tracking again when going into legacy mode. */
1613	vmsvgaSetTraces(pThis, true);
1614
1615	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1616	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1617	pThis->pDrv->pfnVBVADisable(pThis->pDrv, idScreen);
1618
1619	/* Clear the pitch lock. */
1620	pThis->svga.u32PitchLock = 0;
1621	}
1622	#else /* !IN_RING3 */
1623	rc = VINF_IOM_R3_IOPORT_WRITE;
1624	#endif /* !IN_RING3 */
1625	break;
1626
1627	case SVGA_REG_WIDTH:
1628	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1629	if (pThis->svga.uWidth != u32)
1630	{
1631	#if defined(IN_RING3) \|\| defined(IN_RING0)
1632	pThis->svga.uWidth = u32;
1633	vmsvgaUpdatePitch(pThis);
1634	if (pThis->svga.fEnabled)
1635	{
1636	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1637	}
1638	#else
1639	rc = VINF_IOM_R3_IOPORT_WRITE;
1640	#endif
1641	}
1642	/* else: nop */
1643	break;
1644
1645	case SVGA_REG_HEIGHT:
1646	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1647	if (pThis->svga.uHeight != u32)
1648	{
1649	pThis->svga.uHeight = u32;
1650	if (pThis->svga.fEnabled)
1651	{
1652	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1653	}
1654	}
1655	/* else: nop */
1656	break;
1657
1658	case SVGA_REG_DEPTH:
1659	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1660	/** @todo read-only?? */
1661	break;
1662
1663	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1664	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1665	if (pThis->svga.uBpp != u32)
1666	{
1667	#if defined(IN_RING3) \|\| defined(IN_RING0)
1668	pThis->svga.uBpp = u32;
1669	vmsvgaUpdatePitch(pThis);
1670	if (pThis->svga.fEnabled)
1671	{
1672	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1673	}
1674	#else
1675	rc = VINF_IOM_R3_IOPORT_WRITE;
1676	#endif
1677	}
1678	/* else: nop */
1679	break;
1680
1681	case SVGA_REG_PSEUDOCOLOR:
1682	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1683	break;
1684
1685	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1686	#ifdef IN_RING3
1687	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1688	pThis->svga.fConfigured = u32;
1689	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1690	if (!pThis->svga.fConfigured)
1691	{
1692	pThis->svga.fTraces = true;
1693	}
1694	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1695	#else
1696	rc = VINF_IOM_R3_IOPORT_WRITE;
1697	#endif
1698	break;
1699
1700	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1701	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1702	if ( pThis->svga.fEnabled
1703	&& pThis->svga.fConfigured)
1704	{
1705	#if defined(IN_RING3) \|\| defined(IN_RING0)
1706	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1707	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1708	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1709	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1710
1711	/* Kick the FIFO thread to start processing commands again. */
1712	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1713	#else
1714	rc = VINF_IOM_R3_IOPORT_WRITE;
1715	#endif
1716	}
1717	/* else nothing to do. */
1718	else
1719	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1720
1721	break;
1722
1723	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1724	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1725	break;
1726
1727	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1728	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1729	pThis->svga.u32GuestId = u32;
1730	break;
1731
1732	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1733	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1734	pThis->svga.u32PitchLock = u32;
1735	/* Should this also update the FIFO pitch lock? Unclear. */
1736	break;
1737
1738	case SVGA_REG_IRQMASK: /* Interrupt mask */
1739	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1740	pThis->svga.u32IrqMask = u32;
1741
1742	/* Irq pending after the above change? */
1743	if (pThis->svga.u32IrqStatus & u32)
1744	{
1745	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1746	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1747	}
1748	else
1749	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1750	break;
1751
1752	/* Mouse cursor support */
1753	case SVGA_REG_CURSOR_ID:
1754	case SVGA_REG_CURSOR_X:
1755	case SVGA_REG_CURSOR_Y:
1756	case SVGA_REG_CURSOR_ON:
1757	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1758	break;
1759
1760	/* Legacy multi-monitor support */
1761	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1762	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1763	break;
1764	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1765	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1766	break;
1767	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1768	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1769	break;
1770	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1771	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1772	break;
1773	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1774	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1775	break;
1776	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1777	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1778	break;
1779	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1780	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1781	break;
1782	#ifdef VBOX_WITH_VMSVGA3D
1783	/* See "Guest memory regions" below. */
1784	case SVGA_REG_GMR_ID:
1785	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1786	pThis->svga.u32CurrentGMRId = u32;
1787	break;
1788
1789	case SVGA_REG_GMR_DESCRIPTOR:
1790	# ifndef IN_RING3
1791	rc = VINF_IOM_R3_IOPORT_WRITE;
1792	break;
1793	# else /* IN_RING3 */
1794	{
1795	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1796
1797	/* Validate current GMR id. */
1798	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1799	AssertBreak(idGMR < pThis->svga.cGMR);
1800	RT_UNTRUSTED_VALIDATED_FENCE();
1801
1802	/* Free the old GMR if present. */
1803	vmsvgaGMRFree(pThis, idGMR);
1804
1805	/* Just undefine the GMR? */
1806	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1807	if (GCPhys == 0)
1808	{
1809	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1810	break;
1811	}
1812
1813
1814	/* Never cross a page boundary automatically. */
1815	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1816	uint32_t cPagesTotal = 0;
1817	uint32_t iDesc = 0;
1818	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1819	uint32_t cLoops = 0;
1820	RTGCPHYS GCPhysBase = GCPhys;
1821	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1822	{
1823	/* Read descriptor. */
1824	SVGAGuestMemDescriptor desc;
1825	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1826	AssertRCBreak(rc);
1827
1828	if (desc.numPages != 0)
1829	{
1830	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1831	cPagesTotal += desc.numPages;
1832	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1833
1834	if ((iDesc & 15) == 0)
1835	{
1836	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1837	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1838	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1839	}
1840
1841	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1842	paDescs[iDesc++].numPages = desc.numPages;
1843
1844	/* Continue with the next descriptor. */
1845	GCPhys += sizeof(desc);
1846	}
1847	else if (desc.ppn == 0)
1848	break; /* terminator */
1849	else /* Pointer to the next physical page of descriptors. */
1850	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1851
1852	cLoops++;
1853	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1854	}
1855
1856	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1857	if (RT_SUCCESS(rc))
1858	{
1859	/* Commit the GMR. */
1860	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1861	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1862	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1863	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1864	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1865	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1866	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1867	}
1868	else
1869	{
1870	RTMemFree(paDescs);
1871	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1872	}
1873	break;
1874	}
1875	# endif /* IN_RING3 */
1876	#endif // VBOX_WITH_VMSVGA3D
1877
1878	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1879	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1880	if (pThis->svga.fTraces == u32)
1881	break; /* nothing to do */
1882
1883	#ifdef IN_RING3
1884	vmsvgaSetTraces(pThis, !!u32);
1885	#else
1886	rc = VINF_IOM_R3_IOPORT_WRITE;
1887	#endif
1888	break;
1889
1890	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1891	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1892	break;
1893
1894	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1895	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1896	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1897	break;
1898
1899	case SVGA_REG_FB_START:
1900	case SVGA_REG_MEM_START:
1901	case SVGA_REG_HOST_BITS_PER_PIXEL:
1902	case SVGA_REG_MAX_WIDTH:
1903	case SVGA_REG_MAX_HEIGHT:
1904	case SVGA_REG_VRAM_SIZE:
1905	case SVGA_REG_FB_SIZE:
1906	case SVGA_REG_CAPABILITIES:
1907	case SVGA_REG_MEM_SIZE:
1908	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1909	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1910	case SVGA_REG_BYTES_PER_LINE:
1911	case SVGA_REG_FB_OFFSET:
1912	case SVGA_REG_RED_MASK:
1913	case SVGA_REG_GREEN_MASK:
1914	case SVGA_REG_BLUE_MASK:
1915	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1916	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1917	case SVGA_REG_GMR_MAX_IDS:
1918	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1919	/* Read only - ignore. */
1920	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1921	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1922	break;
1923
1924	default:
1925	{
1926	uint32_t offReg;
1927	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1928	{
1929	RT_UNTRUSTED_VALIDATED_FENCE();
1930	pThis->svga.au32ScratchRegion[offReg] = u32;
1931	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1932	}
1933	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1934	{
1935	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1936	Btw, see rgb_to_pixel32. */
1937	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1938	u32 &= 0xff;
1939	RT_UNTRUSTED_VALIDATED_FENCE();
1940	uint32_t uRgb = pThis->last_palette[offReg / 3];
1941	switch (offReg % 3)
1942	{
1943	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1944	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1945	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1946	}
1947	pThis->last_palette[offReg / 3] = uRgb;
1948	}
1949	else
1950	{
1951	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1952	rc = VINF_IOM_R3_IOPORT_WRITE;
1953	#else
1954	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1955	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1956	#endif
1957	}
1958	break;
1959	}
1960	}
1961	return rc;
1962	}
1963
1964	/**
1965	* Port I/O Handler for IN operations.
1966	*
1967	* @returns VINF_SUCCESS or VINF_EM_*.
1968	* @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1969	*
1970	* @param pDevIns The device instance.
1971	* @param pvUser User argument.
1972	* @param uPort Port number used for the IN operation.
1973	* @param pu32 Where to store the result. This is always a 32-bit
1974	* variable regardless of what @a cb might say.
1975	* @param cb Number of bytes read.
1976	*/
1977	PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
1978	{
1979	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1980	RT_NOREF_PV(pvUser);
1981
1982	/* Ignore non-dword accesses. */
1983	if (cb != 4)
1984	{
1985	Log(("Ignoring non-dword read at %x cb=%d\n", uPort, cb));
1986	*pu32 = UINT32_MAX;
1987	return VINF_SUCCESS;
1988	}
1989
1990	switch (uPort - pThis->svga.BasePort)
1991	{
1992	case SVGA_INDEX_PORT:
1993	*pu32 = pThis->svga.u32IndexReg;
1994	break;
1995
1996	case SVGA_VALUE_PORT:
1997	return vmsvgaReadPort(pThis, pu32);
1998
1999	case SVGA_BIOS_PORT:
2000	Log(("Ignoring BIOS port read\n"));
2001	*pu32 = 0;
2002	break;
2003
2004	case SVGA_IRQSTATUS_PORT:
2005	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2006	*pu32 = pThis->svga.u32IrqStatus;
2007	break;
2008
2009	default:
2010	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u (%#x) was read from.\n", uPort - pThis->svga.BasePort, uPort));
2011	*pu32 = UINT32_MAX;
2012	break;
2013	}
2014
2015	return VINF_SUCCESS;
2016	}
2017
2018	/**
2019	* Port I/O Handler for OUT operations.
2020	*
2021	* @returns VINF_SUCCESS or VINF_EM_*.
2022	*
2023	* @param pDevIns The device instance.
2024	* @param pvUser User argument.
2025	* @param uPort Port number used for the OUT operation.
2026	* @param u32 The value to output.
2027	* @param cb The value size in bytes.
2028	*/
2029	PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
2030	{
2031	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2032	RT_NOREF_PV(pvUser);
2033
2034	/* Ignore non-dword accesses. */
2035	if (cb != 4)
2036	{
2037	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", uPort, u32, cb));
2038	return VINF_SUCCESS;
2039	}
2040
2041	switch (uPort - pThis->svga.BasePort)
2042	{
2043	case SVGA_INDEX_PORT:
2044	pThis->svga.u32IndexReg = u32;
2045	break;
2046
2047	case SVGA_VALUE_PORT:
2048	return vmsvgaWritePort(pThis, u32);
2049
2050	case SVGA_BIOS_PORT:
2051	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2052	break;
2053
2054	case SVGA_IRQSTATUS_PORT:
2055	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2056	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2057	/* Clear the irq in case all events have been cleared. */
2058	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2059	{
2060	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2061	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2062	}
2063	break;
2064
2065	default:
2066	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u (%#x) was written to, value %#x LB %u.\n",
2067	uPort - pThis->svga.BasePort, uPort, u32, cb));
2068	break;
2069	}
2070	return VINF_SUCCESS;
2071	}
2072
2073	#ifdef IN_RING3
2074
2075	# ifdef DEBUG_FIFO_ACCESS
2076	/**
2077	* Handle FIFO memory access.
2078	* @returns VBox status code.
2079	* @param pVM VM handle.
2080	* @param pThis VGA device instance data.
2081	* @param GCPhys The access physical address.
2082	* @param fWriteAccess Read or write access
2083	*/
2084	static int vmsvgaDebugFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2085	{
2086	RT_NOREF(pVM);
2087	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2088	uint32_t *pFIFO = pThis->svga.pFIFOR3;
2089
2090	switch (GCPhysOffset >> 2)
2091	{
2092	case SVGA_FIFO_MIN:
2093	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2094	break;
2095	case SVGA_FIFO_MAX:
2096	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2097	break;
2098	case SVGA_FIFO_NEXT_CMD:
2099	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2100	break;
2101	case SVGA_FIFO_STOP:
2102	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2103	break;
2104	case SVGA_FIFO_CAPABILITIES:
2105	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2106	break;
2107	case SVGA_FIFO_FLAGS:
2108	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2109	break;
2110	case SVGA_FIFO_FENCE:
2111	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2112	break;
2113	case SVGA_FIFO_3D_HWVERSION:
2114	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2115	break;
2116	case SVGA_FIFO_PITCHLOCK:
2117	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2118	break;
2119	case SVGA_FIFO_CURSOR_ON:
2120	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2121	break;
2122	case SVGA_FIFO_CURSOR_X:
2123	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2124	break;
2125	case SVGA_FIFO_CURSOR_Y:
2126	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2127	break;
2128	case SVGA_FIFO_CURSOR_COUNT:
2129	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2130	break;
2131	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2132	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2133	break;
2134	case SVGA_FIFO_RESERVED:
2135	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2136	break;
2137	case SVGA_FIFO_CURSOR_SCREEN_ID:
2138	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2139	break;
2140	case SVGA_FIFO_DEAD:
2141	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2142	break;
2143	case SVGA_FIFO_3D_HWVERSION_REVISED:
2144	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2145	break;
2146	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2147	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2148	break;
2149	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2150	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2151	break;
2152	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2153	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2154	break;
2155	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2156	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2157	break;
2158	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2159	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2160	break;
2161	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2162	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2163	break;
2164	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2165	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2166	break;
2167	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2168	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2169	break;
2170	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2171	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2172	break;
2173	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2174	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2175	break;
2176	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2177	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2178	break;
2179	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2180	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2181	break;
2182	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2183	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2184	break;
2185	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2186	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2187	break;
2188	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2189	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2190	break;
2191	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2192	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2193	break;
2194	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2195	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2196	break;
2197	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2198	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2199	break;
2200	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2201	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2202	break;
2203	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2204	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2205	break;
2206	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2207	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2208	break;
2209	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2210	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2211	break;
2212	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2213	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2214	break;
2215	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2216	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2217	break;
2218	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2219	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2220	break;
2221	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2222	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2223	break;
2224	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2225	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2226	break;
2227	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2228	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2229	break;
2230	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2231	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2232	break;
2233	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2234	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2235	break;
2236	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2237	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2238	break;
2239	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2240	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2241	break;
2242	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2243	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2244	break;
2245	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2246	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2247	break;
2248	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2249	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2250	break;
2251	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2252	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2253	break;
2254	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2255	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2256	break;
2257	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2258	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2259	break;
2260	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2261	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2262	break;
2263	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2264	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2265	break;
2266	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2267	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2268	break;
2269	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2270	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2271	break;
2272	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2273	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2274	break;
2275	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2276	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2277	break;
2278	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2279	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2280	break;
2281	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2282	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2283	break;
2284	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2285	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2286	break;
2287	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2288	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2289	break;
2290	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2291	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2292	break;
2293	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2294	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2295	break;
2296	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2297	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2298	break;
2299	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2300	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2301	break;
2302	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2303	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2304	break;
2305	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2306	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2307	break;
2308	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2309	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2310	break;
2311	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2312	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2313	break;
2314	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2315	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2316	break;
2317	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2318	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2319	break;
2320	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2321	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2322	break;
2323	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2324	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2325	break;
2326	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2327	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2328	break;
2329	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2330	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2331	break;
2332	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2333	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2334	break;
2335	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2336	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2337	break;
2338	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2339	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2340	break;
2341	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2342	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2343	break;
2344	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2345	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2346	break;
2347	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2348	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2349	break;
2350	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2351	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2352	break;
2353	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2354	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2355	break;
2356	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2357	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2358	break;
2359	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2360	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2361	break;
2362	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2363	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2364	break;
2365	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2366	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2367	break;
2368	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2369	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2370	break;
2371	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2372	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2373	break;
2374	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2375	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2376	break;
2377	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2378	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2379	break;
2380	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2381	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2382	break;
2383	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2384	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2385	break;
2386	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2387	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2388	break;
2389	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2390	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2391	break;
2392	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2393	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2394	break;
2395	case SVGA_FIFO_3D_CAPS_LAST:
2396	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2397	break;
2398	case SVGA_FIFO_GUEST_3D_HWVERSION:
2399	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2400	break;
2401	case SVGA_FIFO_FENCE_GOAL:
2402	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2403	break;
2404	case SVGA_FIFO_BUSY:
2405	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2406	break;
2407	default:
2408	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2409	break;
2410	}
2411
2412	return VINF_EM_RAW_EMULATE_INSTR;
2413	}
2414	# endif /* DEBUG_FIFO_ACCESS */
2415
2416	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2417	/**
2418	* HC access handler for the FIFO.
2419	*
2420	* @returns VINF_SUCCESS if the handler have carried out the operation.
2421	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2422	* @param pVM VM Handle.
2423	* @param pVCpu The cross context CPU structure for the calling EMT.
2424	* @param GCPhys The physical address the guest is writing to.
2425	* @param pvPhys The HC mapping of that address.
2426	* @param pvBuf What the guest is reading/writing.
2427	* @param cbBuf How much it's reading/writing.
2428	* @param enmAccessType The access type.
2429	* @param enmOrigin Who is making the access.
2430	* @param pvUser User argument.
2431	*/
2432	static DECLCALLBACK(VBOXSTRICTRC)
2433	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2434	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2435	{
2436	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2437	PVGASTATE pThis = (PVGASTATE)pvUser;
2438	AssertPtr(pThis);
2439
2440	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2441	/*
2442	* Wake up the FIFO thread as it might have work to do now.
2443	*/
2444	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2445	AssertLogRelRC(rc);
2446	# endif
2447
2448	# ifdef DEBUG_FIFO_ACCESS
2449	/*
2450	* When in debug-fifo-access mode, we do not disable the access handler,
2451	* but leave it on as we wish to catch all access.
2452	*/
2453	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2454	rc = vmsvgaDebugFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2455	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2456	/*
2457	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2458	*/
2459	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoAccessHandler);
2460	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2461	# endif
2462	if (RT_SUCCESS(rc))
2463	return VINF_PGM_HANDLER_DO_DEFAULT;
2464	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2465	return rc;
2466	}
2467	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2468
2469	#endif /* IN_RING3 */
2470
2471	#ifdef DEBUG_GMR_ACCESS
2472	# ifdef IN_RING3
2473
2474	/**
2475	* HC access handler for the FIFO.
2476	*
2477	* @returns VINF_SUCCESS if the handler have carried out the operation.
2478	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2479	* @param pVM VM Handle.
2480	* @param pVCpu The cross context CPU structure for the calling EMT.
2481	* @param GCPhys The physical address the guest is writing to.
2482	* @param pvPhys The HC mapping of that address.
2483	* @param pvBuf What the guest is reading/writing.
2484	* @param cbBuf How much it's reading/writing.
2485	* @param enmAccessType The access type.
2486	* @param enmOrigin Who is making the access.
2487	* @param pvUser User argument.
2488	*/
2489	static DECLCALLBACK(VBOXSTRICTRC)
2490	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2491	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2492	{
2493	PVGASTATE pThis = (PVGASTATE)pvUser;
2494	Assert(pThis);
2495	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2496	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2497
2498	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2499
2500	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2501	{
2502	PGMR pGMR = &pSVGAState->paGMR[i];
2503
2504	if (pGMR->numDescriptors)
2505	{
2506	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2507	{
2508	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2509	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2510	{
2511	/*
2512	* Turn off the write handler for this particular page and make it R/W.
2513	* Then return telling the caller to restart the guest instruction.
2514	*/
2515	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2516	AssertRC(rc);
2517	goto end;
2518	}
2519	}
2520	}
2521	}
2522	end:
2523	return VINF_PGM_HANDLER_DO_DEFAULT;
2524	}
2525
2526	/* Callback handler for VMR3ReqCallWaitU */
2527	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2528	{
2529	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2530	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2531	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2532	int rc;
2533
2534	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2535	{
2536	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2537	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2538	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2539	AssertRC(rc);
2540	}
2541	return VINF_SUCCESS;
2542	}
2543
2544	/* Callback handler for VMR3ReqCallWaitU */
2545	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2546	{
2547	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2548	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2549	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2550
2551	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2552	{
2553	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2554	AssertRC(rc);
2555	}
2556	return VINF_SUCCESS;
2557	}
2558
2559	/* Callback handler for VMR3ReqCallWaitU */
2560	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2561	{
2562	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2563
2564	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2565	{
2566	PGMR pGMR = &pSVGAState->paGMR[i];
2567
2568	if (pGMR->numDescriptors)
2569	{
2570	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2571	{
2572	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2573	AssertRC(rc);
2574	}
2575	}
2576	}
2577	return VINF_SUCCESS;
2578	}
2579
2580	# endif /* IN_RING3 */
2581	#endif /* DEBUG_GMR_ACCESS */
2582
2583	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2584
2585	#ifdef IN_RING3
2586
2587
2588	/**
2589	* Common worker for changing the pointer shape.
2590	*
2591	* @param pThis The VGA instance data.
2592	* @param pSVGAState The VMSVGA ring-3 instance data.
2593	* @param fAlpha Whether there is alpha or not.
2594	* @param xHot Hotspot x coordinate.
2595	* @param yHot Hotspot y coordinate.
2596	* @param cx Width.
2597	* @param cy Height.
2598	* @param pbData Heap copy of the cursor data. Consumed.
2599	* @param cbData The size of the data.
2600	*/
2601	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2602	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2603	{
2604	Log(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2605	#ifdef LOG_ENABLED
2606	if (LogIs2Enabled())
2607	{
2608	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2609	if (!fAlpha)
2610	{
2611	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2612	for (uint32_t y = 0; y < cy; y++)
2613	{
2614	Log2(("%3u:", y));
2615	uint8_t const pbLine = &pbData[y cbAndLine];
2616	for (uint32_t x = 0; x < cx; x += 8)
2617	{
2618	uint8_t b = pbLine[x / 8];
2619	char szByte[12];
2620	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2621	szByte[1] = b & 0x40 ? '*' : ' ';
2622	szByte[2] = b & 0x20 ? '*' : ' ';
2623	szByte[3] = b & 0x10 ? '*' : ' ';
2624	szByte[4] = b & 0x08 ? '*' : ' ';
2625	szByte[5] = b & 0x04 ? '*' : ' ';
2626	szByte[6] = b & 0x02 ? '*' : ' ';
2627	szByte[7] = b & 0x01 ? '*' : ' ';
2628	szByte[8] = '\0';
2629	Log2(("%s", szByte));
2630	}
2631	Log2(("\n"));
2632	}
2633	}
2634
2635	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2636	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2637	for (uint32_t y = 0; y < cy; y++)
2638	{
2639	Log2(("%3u:", y));
2640	uint32_t const pu32Line = &pu32Xor[y cx];
2641	for (uint32_t x = 0; x < cx; x++)
2642	Log2((" %08x", pu32Line[x]));
2643	Log2(("\n"));
2644	}
2645	}
2646	#endif
2647
2648	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2649	AssertRC(rc);
2650
2651	if (pSVGAState->Cursor.fActive)
2652	RTMemFree(pSVGAState->Cursor.pData);
2653
2654	pSVGAState->Cursor.fActive = true;
2655	pSVGAState->Cursor.xHotspot = xHot;
2656	pSVGAState->Cursor.yHotspot = yHot;
2657	pSVGAState->Cursor.width = cx;
2658	pSVGAState->Cursor.height = cy;
2659	pSVGAState->Cursor.cbData = cbData;
2660	pSVGAState->Cursor.pData = pbData;
2661	}
2662
2663
2664	/**
2665	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2666	*
2667	* @param pThis The VGA instance data.
2668	* @param pSVGAState The VMSVGA ring-3 instance data.
2669	* @param pCursor The cursor.
2670	* @param pbSrcAndMask The AND mask.
2671	* @param cbSrcAndLine The scanline length of the AND mask.
2672	* @param pbSrcXorMask The XOR mask.
2673	* @param cbSrcXorLine The scanline length of the XOR mask.
2674	*/
2675	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2676	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2677	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2678	{
2679	uint32_t const cx = pCursor->width;
2680	uint32_t const cy = pCursor->height;
2681
2682	/*
2683	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2684	* The AND data uses 8-bit aligned scanlines.
2685	* The XOR data must be starting on a 32-bit boundrary.
2686	*/
2687	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2688	uint32_t cbDstAndMask = cbDstAndLine * cy;
2689	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2690	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2691
2692	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2693	AssertReturnVoid(pbCopy);
2694
2695	/* Convert the AND mask. */
2696	uint8_t *pbDst = pbCopy;
2697	uint8_t const *pbSrc = pbSrcAndMask;
2698	switch (pCursor->andMaskDepth)
2699	{
2700	case 1:
2701	if (cbSrcAndLine == cbDstAndLine)
2702	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2703	else
2704	{
2705	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2706	for (uint32_t y = 0; y < cy; y++)
2707	{
2708	memcpy(pbDst, pbSrc, cbDstAndLine);
2709	pbDst += cbDstAndLine;
2710	pbSrc += cbSrcAndLine;
2711	}
2712	}
2713	break;
2714	/* Should take the XOR mask into account for the multi-bit AND mask. */
2715	case 8:
2716	for (uint32_t y = 0; y < cy; y++)
2717	{
2718	for (uint32_t x = 0; x < cx; )
2719	{
2720	uint8_t bDst = 0;
2721	uint8_t fBit = 1;
2722	do
2723	{
2724	uintptr_t const idxPal = pbSrc[x] * 3;
2725	if ((( pThis->last_palette[idxPal]
2726	\| (pThis->last_palette[idxPal] >> 8)
2727	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2728	bDst \|= fBit;
2729	fBit <<= 1;
2730	x++;
2731	} while (x < cx && (x & 7));
2732	pbDst[(x - 1) / 8] = bDst;
2733	}
2734	pbDst += cbDstAndLine;
2735	pbSrc += cbSrcAndLine;
2736	}
2737	break;
2738	case 15:
2739	for (uint32_t y = 0; y < cy; y++)
2740	{
2741	for (uint32_t x = 0; x < cx; )
2742	{
2743	uint8_t bDst = 0;
2744	uint8_t fBit = 1;
2745	do
2746	{
2747	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2748	bDst \|= fBit;
2749	fBit <<= 1;
2750	x++;
2751	} while (x < cx && (x & 7));
2752	pbDst[(x - 1) / 8] = bDst;
2753	}
2754	pbDst += cbDstAndLine;
2755	pbSrc += cbSrcAndLine;
2756	}
2757	break;
2758	case 16:
2759	for (uint32_t y = 0; y < cy; y++)
2760	{
2761	for (uint32_t x = 0; x < cx; )
2762	{
2763	uint8_t bDst = 0;
2764	uint8_t fBit = 1;
2765	do
2766	{
2767	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2768	bDst \|= fBit;
2769	fBit <<= 1;
2770	x++;
2771	} while (x < cx && (x & 7));
2772	pbDst[(x - 1) / 8] = bDst;
2773	}
2774	pbDst += cbDstAndLine;
2775	pbSrc += cbSrcAndLine;
2776	}
2777	break;
2778	case 24:
2779	for (uint32_t y = 0; y < cy; y++)
2780	{
2781	for (uint32_t x = 0; x < cx; )
2782	{
2783	uint8_t bDst = 0;
2784	uint8_t fBit = 1;
2785	do
2786	{
2787	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2788	bDst \|= fBit;
2789	fBit <<= 1;
2790	x++;
2791	} while (x < cx && (x & 7));
2792	pbDst[(x - 1) / 8] = bDst;
2793	}
2794	pbDst += cbDstAndLine;
2795	pbSrc += cbSrcAndLine;
2796	}
2797	break;
2798	case 32:
2799	for (uint32_t y = 0; y < cy; y++)
2800	{
2801	for (uint32_t x = 0; x < cx; )
2802	{
2803	uint8_t bDst = 0;
2804	uint8_t fBit = 1;
2805	do
2806	{
2807	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2808	bDst \|= fBit;
2809	fBit <<= 1;
2810	x++;
2811	} while (x < cx && (x & 7));
2812	pbDst[(x - 1) / 8] = bDst;
2813	}
2814	pbDst += cbDstAndLine;
2815	pbSrc += cbSrcAndLine;
2816	}
2817	break;
2818	default:
2819	RTMemFree(pbCopy);
2820	AssertFailedReturnVoid();
2821	}
2822
2823	/* Convert the XOR mask. */
2824	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2825	pbSrc = pbSrcXorMask;
2826	switch (pCursor->xorMaskDepth)
2827	{
2828	case 1:
2829	for (uint32_t y = 0; y < cy; y++)
2830	{
2831	for (uint32_t x = 0; x < cx; )
2832	{
2833	/* most significant bit is the left most one. */
2834	uint8_t bSrc = pbSrc[x / 8];
2835	do
2836	{
2837	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2838	bSrc <<= 1;
2839	x++;
2840	} while ((x & 7) && x < cx);
2841	}
2842	pbSrc += cbSrcXorLine;
2843	}
2844	break;
2845	case 8:
2846	for (uint32_t y = 0; y < cy; y++)
2847	{
2848	for (uint32_t x = 0; x < cx; x++)
2849	{
2850	uint32_t u = pThis->last_palette[pbSrc[x]];
2851	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2852	}
2853	pbSrc += cbSrcXorLine;
2854	}
2855	break;
2856	case 15: /* Src: RGB-5-5-5 */
2857	for (uint32_t y = 0; y < cy; y++)
2858	{
2859	for (uint32_t x = 0; x < cx; x++)
2860	{
2861	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2862	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2863	((uValue >> 5) & 0x1f) << 3,
2864	((uValue >> 10) & 0x1f) << 3, 0);
2865	}
2866	pbSrc += cbSrcXorLine;
2867	}
2868	break;
2869	case 16: /* Src: RGB-5-6-5 */
2870	for (uint32_t y = 0; y < cy; y++)
2871	{
2872	for (uint32_t x = 0; x < cx; x++)
2873	{
2874	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2875	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2876	((uValue >> 5) & 0x3f) << 2,
2877	((uValue >> 11) & 0x1f) << 3, 0);
2878	}
2879	pbSrc += cbSrcXorLine;
2880	}
2881	break;
2882	case 24:
2883	for (uint32_t y = 0; y < cy; y++)
2884	{
2885	for (uint32_t x = 0; x < cx; x++)
2886	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2887	pbSrc += cbSrcXorLine;
2888	}
2889	break;
2890	case 32:
2891	for (uint32_t y = 0; y < cy; y++)
2892	{
2893	for (uint32_t x = 0; x < cx; x++)
2894	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2895	pbSrc += cbSrcXorLine;
2896	}
2897	break;
2898	default:
2899	RTMemFree(pbCopy);
2900	AssertFailedReturnVoid();
2901	}
2902
2903	/*
2904	* Pass it to the frontend/whatever.
2905	*/
2906	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2907	}
2908
2909
2910	/**
2911	* Worker for vmsvgaR3FifoThread that handles an external command.
2912	*
2913	* @param pThis VGA device instance data.
2914	*/
2915	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2916	{
2917	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2918	switch (pThis->svga.u8FIFOExtCommand)
2919	{
2920	case VMSVGA_FIFO_EXTCMD_RESET:
2921	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2922	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2923	# ifdef VBOX_WITH_VMSVGA3D
2924	if (pThis->svga.f3DEnabled)
2925	{
2926	/* The 3d subsystem must be reset from the fifo thread. */
2927	vmsvga3dReset(pThis);
2928	}
2929	# endif
2930	break;
2931
2932	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2933	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2934	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2935	# ifdef VBOX_WITH_VMSVGA3D
2936	if (pThis->svga.f3DEnabled)
2937	{
2938	/* The 3d subsystem must be shut down from the fifo thread. */
2939	vmsvga3dTerminate(pThis);
2940	}
2941	# endif
2942	break;
2943
2944	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2945	{
2946	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2947	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2948	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2949	vmsvgaSaveExecFifo(pThis, pSSM);
2950	# ifdef VBOX_WITH_VMSVGA3D
2951	if (pThis->svga.f3DEnabled)
2952	vmsvga3dSaveExec(pThis, pSSM);
2953	# endif
2954	break;
2955	}
2956
2957	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2958	{
2959	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2960	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2961	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2962	vmsvgaLoadExecFifo(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2963	# ifdef VBOX_WITH_VMSVGA3D
2964	if (pThis->svga.f3DEnabled)
2965	vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2966	# endif
2967	break;
2968	}
2969
2970	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2971	{
2972	# ifdef VBOX_WITH_VMSVGA3D
2973	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2974	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2975	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2976	# endif
2977	break;
2978	}
2979
2980
2981	default:
2982	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2983	break;
2984	}
2985
2986	/*
2987	* Signal the end of the external command.
2988	*/
2989	pThis->svga.pvFIFOExtCmdParam = NULL;
2990	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2991	ASMMemoryFence(); /* paranoia^2 */
2992	int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2993	AssertLogRelRC(rc);
2994	}
2995
2996	/**
2997	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2998	* doing a job on the FIFO thread (even when it's officially suspended).
2999	*
3000	* @returns VBox status code (fully asserted).
3001	* @param pThis VGA device instance data.
3002	* @param uExtCmd The command to execute on the FIFO thread.
3003	* @param pvParam Pointer to command parameters.
3004	* @param cMsWait The time to wait for the command, given in
3005	* milliseconds.
3006	*/
3007	static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3008	{
3009	Assert(cMsWait >= RT_MS_1SEC * 5);
3010	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3011	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3012
3013	int rc;
3014	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
3015	PDMTHREADSTATE enmState = pThread->enmState;
3016	if (enmState == PDMTHREADSTATE_SUSPENDED)
3017	{
3018	/*
3019	* The thread is suspended, we have to temporarily wake it up so it can
3020	* perform the task.
3021	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3022	*/
3023	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3024	/* Post the request. */
3025	pThis->svga.fFifoExtCommandWakeup = true;
3026	pThis->svga.pvFIFOExtCmdParam = pvParam;
3027	pThis->svga.u8FIFOExtCommand = uExtCmd;
3028	ASMMemoryFence(); /* paranoia^3 */
3029
3030	/* Resume the thread. */
3031	rc = PDMR3ThreadResume(pThread);
3032	AssertLogRelRC(rc);
3033	if (RT_SUCCESS(rc))
3034	{
3035	/* Wait. Take care in case the semaphore was already posted (same as below). */
3036	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3037	if ( rc == VINF_SUCCESS
3038	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3039	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3040	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3041	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3042
3043	/* suspend the thread */
3044	pThis->svga.fFifoExtCommandWakeup = false;
3045	int rc2 = PDMR3ThreadSuspend(pThread);
3046	AssertLogRelRC(rc2);
3047	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3048	rc = rc2;
3049	}
3050	pThis->svga.fFifoExtCommandWakeup = false;
3051	pThis->svga.pvFIFOExtCmdParam = NULL;
3052	}
3053	else if (enmState == PDMTHREADSTATE_RUNNING)
3054	{
3055	/*
3056	* The thread is running, should only happen during reset and vmsvga3dsfc.
3057	* We ASSUME not racing code here, both wrt thread state and ext commands.
3058	*/
3059	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3060	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3061
3062	/* Post the request. */
3063	pThis->svga.pvFIFOExtCmdParam = pvParam;
3064	pThis->svga.u8FIFOExtCommand = uExtCmd;
3065	ASMMemoryFence(); /* paranoia^2 */
3066	rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3067	AssertLogRelRC(rc);
3068
3069	/* Wait. Take care in case the semaphore was already posted (same as above). */
3070	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3071	if ( rc == VINF_SUCCESS
3072	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3073	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3074	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3075	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3076
3077	pThis->svga.pvFIFOExtCmdParam = NULL;
3078	}
3079	else
3080	{
3081	/*
3082	* Something is wrong with the thread!
3083	*/
3084	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3085	rc = VERR_INVALID_STATE;
3086	}
3087	return rc;
3088	}
3089
3090
3091	/**
3092	* Marks the FIFO non-busy, notifying any waiting EMTs.
3093	*
3094	* @param pThis The VGA state.
3095	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3096	* @param offFifoMin The start byte offset of the command FIFO.
3097	*/
3098	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3099	{
3100	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3101	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3102	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
3103
3104	/* Wake up any waiting EMTs. */
3105	if (pSVGAState->cBusyDelayedEmts > 0)
3106	{
3107	#ifdef VMSVGA_USE_EMT_HALT_CODE
3108	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
3109	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3110	if (idCpu != NIL_VMCPUID)
3111	{
3112	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3113	while (idCpu-- > 0)
3114	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3115	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3116	}
3117	#else
3118	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3119	AssertRC(rc2);
3120	#endif
3121	}
3122	}
3123
3124	/**
3125	* Reads (more) payload into the command buffer.
3126	*
3127	* @returns pbBounceBuf on success
3128	* @retval (void *)1 if the thread was requested to stop.
3129	* @retval NULL on FIFO error.
3130	*
3131	* @param cbPayloadReq The number of bytes of payload requested.
3132	* @param pFIFO The FIFO.
3133	* @param offCurrentCmd The FIFO byte offset of the current command.
3134	* @param offFifoMin The start byte offset of the command FIFO.
3135	* @param offFifoMax The end byte offset of the command FIFO.
3136	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3137	* always sufficient size.
3138	* @param pcbAlreadyRead How much payload we've already read into the bounce
3139	* buffer. (We will NEVER re-read anything.)
3140	* @param pThread The calling PDM thread handle.
3141	* @param pThis The VGA state.
3142	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3143	* statistics collection.
3144	*/
3145	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3146	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3147	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3148	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
3149	{
3150	Assert(pbBounceBuf);
3151	Assert(pcbAlreadyRead);
3152	Assert(offFifoMin < offFifoMax);
3153	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3154	Assert(offFifoMax <= pThis->svga.cbFIFO);
3155
3156	/*
3157	* Check if the requested payload size has already been satisfied .
3158	* .
3159	* When called to read more, the caller is responsible for making sure the .
3160	* new command size (cbRequsted) never is smaller than what has already .
3161	* been read.
3162	*/
3163	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3164	if (cbPayloadReq <= cbAlreadyRead)
3165	{
3166	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3167	return pbBounceBuf;
3168	}
3169
3170	/*
3171	* Commands bigger than the fifo buffer are invalid.
3172	*/
3173	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3174	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3175	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3176	NULL);
3177
3178	/*
3179	* Move offCurrentCmd past the command dword.
3180	*/
3181	offCurrentCmd += sizeof(uint32_t);
3182	if (offCurrentCmd >= offFifoMax)
3183	offCurrentCmd = offFifoMin;
3184
3185	/*
3186	* Do we have sufficient payload data available already?
3187	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3188	*/
3189	uint32_t cbAfter, cbBefore;
3190	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3191	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3192	if (offNextCmd >= offCurrentCmd)
3193	{
3194	if (RT_LIKELY(offNextCmd < offFifoMax))
3195	cbAfter = offNextCmd - offCurrentCmd;
3196	else
3197	{
3198	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3199	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3200	offNextCmd, offFifoMin, offFifoMax));
3201	cbAfter = offFifoMax - offCurrentCmd;
3202	}
3203	cbBefore = 0;
3204	}
3205	else
3206	{
3207	cbAfter = offFifoMax - offCurrentCmd;
3208	if (offNextCmd >= offFifoMin)
3209	cbBefore = offNextCmd - offFifoMin;
3210	else
3211	{
3212	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3213	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3214	offNextCmd, offFifoMin, offFifoMax));
3215	cbBefore = 0;
3216	}
3217	}
3218	if (cbAfter + cbBefore < cbPayloadReq)
3219	{
3220	/*
3221	* Insufficient, must wait for it to arrive.
3222	*/
3223	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3224	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3225	for (uint32_t i = 0;; i++)
3226	{
3227	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3228	{
3229	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3230	return (void *)(uintptr_t)1;
3231	}
3232	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3233	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3234
3235	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
3236
3237	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3238	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3239	if (offNextCmd >= offCurrentCmd)
3240	{
3241	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3242	cbBefore = 0;
3243	}
3244	else
3245	{
3246	cbAfter = offFifoMax - offCurrentCmd;
3247	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3248	}
3249
3250	if (cbAfter + cbBefore >= cbPayloadReq)
3251	break;
3252	}
3253	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3254	}
3255
3256	/*
3257	* Copy out the memory and update what pcbAlreadyRead points to.
3258	*/
3259	if (cbAfter >= cbPayloadReq)
3260	memcpy(pbBounceBuf + cbAlreadyRead,
3261	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3262	cbPayloadReq - cbAlreadyRead);
3263	else
3264	{
3265	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3266	if (cbAlreadyRead < cbAfter)
3267	{
3268	memcpy(pbBounceBuf + cbAlreadyRead,
3269	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3270	cbAfter - cbAlreadyRead);
3271	cbAlreadyRead = cbAfter;
3272	}
3273	memcpy(pbBounceBuf + cbAlreadyRead,
3274	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3275	cbPayloadReq - cbAlreadyRead);
3276	}
3277	*pcbAlreadyRead = cbPayloadReq;
3278	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3279	return pbBounceBuf;
3280	}
3281
3282
3283	/**
3284	* Sends cursor position and visibility information from the FIFO to the front-end.
3285	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3286	*/
3287	static uint32_t
3288	vmsvgaFIFOUpdateCursor(PVGASTATE pVGAState, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3289	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3290	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3291	{
3292	/*
3293	* Check if the cursor update counter has changed and try get a stable
3294	* set of values if it has. This is race-prone, especially consindering
3295	* the screen ID, but little we can do about that.
3296	*/
3297	uint32_t x, y, fVisible, idScreen;
3298	for (uint32_t i = 0; ; i++)
3299	{
3300	x = pFIFO[SVGA_FIFO_CURSOR_X];
3301	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3302	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3303	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3304	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3305	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3306	\|\| i > 3)
3307	break;
3308	if (i == 0)
3309	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3310	ASMNopPause();
3311	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3312	}
3313
3314	/*
3315	* Check if anything has changed, as calling into pDrv is not light-weight.
3316	*/
3317	if ( *pxLast == x
3318	&& *pyLast == y
3319	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3320	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3321	else
3322	{
3323	/*
3324	* Detected changes.
3325	*
3326	* We handle global, not per-screen visibility information by sending
3327	* pfnVBVAMousePointerShape without shape data.
3328	*/
3329	*pxLast = x;
3330	*pyLast = y;
3331	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3332	if (idScreen != SVGA_ID_INVALID)
3333	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3334	else if (*pfLastVisible != fVisible)
3335	{
3336	*pfLastVisible = fVisible;
3337	pVGAState->pDrv->pfnVBVAMousePointerShape(pVGAState->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3338	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3339	}
3340	pVGAState->pDrv->pfnVBVAReportCursorPosition(pVGAState->pDrv, fFlags, idScreen, x, y);
3341	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3342	}
3343
3344	/*
3345	* Update done. Signal this to the guest.
3346	*/
3347	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3348
3349	return uCursorUpdateCount;
3350	}
3351
3352
3353	/**
3354	* Checks if there is work to be done, either cursor updating or FIFO commands.
3355	*
3356	* @returns true if pending work, false if not.
3357	* @param pFIFO The FIFO to examine.
3358	* @param uLastCursorCount The last cursor update counter value.
3359	*/
3360	DECLINLINE(bool) vmsvgaFIFOHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3361	{
3362	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3363	return true;
3364
3365	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3366	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3367	return true;
3368
3369	return false;
3370	}
3371
3372
3373	/**
3374	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3375	*
3376	* @param pThis The VGA state.
3377	*/
3378	void vmsvgaFIFOWatchdogTimer(PVGASTATE pThis)
3379	{
3380	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3381	to recheck it before doing the signalling. */
3382	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3383	AssertReturnVoid(pFIFO);
3384	if ( vmsvgaFIFOHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3385	&& pThis->svga.fFIFOThreadSleeping)
3386	{
3387	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3388	AssertRC(rc);
3389	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3390	}
3391	}
3392
3393
3394	/* The async FIFO handling thread. */
3395	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3396	{
3397	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3398	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3399	int rc;
3400
3401	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3402	return VINF_SUCCESS;
3403
3404	/*
3405	* Special mode where we only execute an external command and the go back
3406	* to being suspended. Currently, all ext cmds ends up here, with the reset
3407	* one also being eligble for runtime execution further down as well.
3408	*/
3409	if (pThis->svga.fFifoExtCommandWakeup)
3410	{
3411	vmsvgaR3FifoHandleExtCmd(pThis);
3412	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3413	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3414	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
3415	else
3416	vmsvgaR3FifoHandleExtCmd(pThis);
3417	return VINF_SUCCESS;
3418	}
3419
3420
3421	/*
3422	* Signal the semaphore to make sure we don't wait for 250ms after a
3423	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3424	*/
3425	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3426
3427	/*
3428	* Allocate a bounce buffer for command we get from the FIFO.
3429	* (All code must return via the end of the function to free this buffer.)
3430	*/
3431	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3432	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3433
3434	/*
3435	* Polling/sleep interval config.
3436	*
3437	* We wait for an a short interval if the guest has recently given us work
3438	* to do, but the interval increases the longer we're kept idle. Once we've
3439	* reached the refresh timer interval, we'll switch to extended waits,
3440	* depending on it or the guest to kick us into action when needed.
3441	*
3442	* Should the refresh time go fishing, we'll just continue increasing the
3443	* sleep length till we reaches the 250 ms max after about 16 seconds.
3444	*/
3445	RTMSINTERVAL const cMsMinSleep = 16;
3446	RTMSINTERVAL const cMsIncSleep = 2;
3447	RTMSINTERVAL const cMsMaxSleep = 250;
3448	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3449	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3450
3451	/*
3452	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3453	*
3454	* Initialize with values that will detect an update from the guest.
3455	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3456	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3457	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3458	*/
3459	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3460	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3461	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3462	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3463	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3464
3465	/*
3466	* The FIFO loop.
3467	*/
3468	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3469	bool fBadOrDisabledFifo = false;
3470	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3471	{
3472	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3473	/*
3474	* Should service the run loop every so often.
3475	*/
3476	if (pThis->svga.f3DEnabled)
3477	vmsvga3dCocoaServiceRunLoop();
3478	# endif
3479
3480	/*
3481	* Unless there's already work pending, go to sleep for a short while.
3482	* (See polling/sleep interval config above.)
3483	*/
3484	if ( fBadOrDisabledFifo
3485	\|\| !vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3486	{
3487	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3488	Assert(pThis->cMilliesRefreshInterval > 0);
3489	if (cMsSleep < pThis->cMilliesRefreshInterval)
3490	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
3491	else
3492	{
3493	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3494	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3495	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3496	# endif
3497	if ( !fBadOrDisabledFifo
3498	&& vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3499	rc = VINF_SUCCESS;
3500	else
3501	{
3502	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3503	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsExtendedSleep);
3504	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3505	}
3506	}
3507	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3508	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3509	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3510	{
3511	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3512	break;
3513	}
3514	}
3515	else
3516	rc = VINF_SUCCESS;
3517	fBadOrDisabledFifo = false;
3518	if (rc == VERR_TIMEOUT)
3519	{
3520	if (!vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3521	{
3522	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3523	continue;
3524	}
3525	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3526
3527	Log(("vmsvgaFIFOLoop: timeout\n"));
3528	}
3529	else if (vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3530	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3531	cMsSleep = cMsMinSleep;
3532
3533	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3534	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3535	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3536
3537	/*
3538	* Handle external commands (currently only reset).
3539	*/
3540	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3541	{
3542	vmsvgaR3FifoHandleExtCmd(pThis);
3543	continue;
3544	}
3545
3546	/*
3547	* The device must be enabled and configured.
3548	*/
3549	if ( !pThis->svga.fEnabled
3550	\|\| !pThis->svga.fConfigured)
3551	{
3552	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3553	fBadOrDisabledFifo = true;
3554	cMsSleep = cMsMaxSleep; /* cheat */
3555	continue;
3556	}
3557
3558	/*
3559	* Get and check the min/max values. We ASSUME that they will remain
3560	* unchanged while we process requests. A further ASSUMPTION is that
3561	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3562	* we don't read it back while in the loop.
3563	*/
3564	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3565	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3566	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3567	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3568	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3569	\|\| offFifoMax <= offFifoMin
3570	\|\| offFifoMax > pThis->svga.cbFIFO
3571	\|\| (offFifoMax & 3) != 0
3572	\|\| (offFifoMin & 3) != 0
3573	\|\| offCurrentCmd < offFifoMin
3574	\|\| offCurrentCmd > offFifoMax))
3575	{
3576	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3577	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3578	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3579	fBadOrDisabledFifo = true;
3580	continue;
3581	}
3582	RT_UNTRUSTED_VALIDATED_FENCE();
3583	if (RT_UNLIKELY(offCurrentCmd & 3))
3584	{
3585	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3586	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3587	offCurrentCmd = ~UINT32_C(3);
3588	}
3589
3590	/*
3591	* Update the cursor position before we start on the FIFO commands.
3592	*/
3593	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3594	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3595	{
3596	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3597	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3598	{ /* halfways likely */ }
3599	else
3600	{
3601	uint32_t const uLastCursorCount = vmsvgaFIFOUpdateCursor(pThis, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3602	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3603	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uLastCursorCount);
3604	}
3605	}
3606
3607	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3608	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3609	*
3610	* Will break out of the switch on failure.
3611	* Will restart and quit the loop if the thread was requested to stop.
3612	*
3613	* @param a_PtrVar Request variable pointer.
3614	* @param a_Type Request typedef (not pointer) for casting.
3615	* @param a_cbPayloadReq How much payload to fetch.
3616	* @remarks Accesses a bunch of variables in the current scope!
3617	*/
3618	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3619	if (1) { \
3620	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3621	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
3622	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3623	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3624	} else do {} while (0)
3625	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3626	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3627	* buffer after figuring out the actual command size.
3628	*
3629	* Will break out of the switch on failure.
3630	*
3631	* @param a_PtrVar Request variable pointer.
3632	* @param a_Type Request typedef (not pointer) for casting.
3633	* @param a_cbPayloadReq How much payload to fetch.
3634	* @remarks Accesses a bunch of variables in the current scope!
3635	*/
3636	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3637	if (1) { \
3638	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3639	} else do {} while (0)
3640
3641	/*
3642	* Mark the FIFO as busy.
3643	*/
3644	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3645	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3646	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3647
3648	/*
3649	* Execute all queued FIFO commands.
3650	* Quit if pending external command or changes in the thread state.
3651	*/
3652	bool fDone = false;
3653	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3654	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3655	{
3656	uint32_t cbPayload = 0;
3657	uint32_t u32IrqStatus = 0;
3658
3659	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3660
3661	/* First check any pending actions. */
3662	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3663	{
3664	vmsvgaChangeMode(pThis);
3665	# ifdef VBOX_WITH_VMSVGA3D
3666	if (pThis->svga.p3dState != NULL)
3667	vmsvga3dChangeMode(pThis);
3668	# endif
3669	}
3670
3671	/* Check for pending external commands (reset). */
3672	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3673	break;
3674
3675	/*
3676	* Process the command.
3677	*/
3678	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3679	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3680	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3681	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3682	switch (enmCmdId)
3683	{
3684	case SVGA_CMD_INVALID_CMD:
3685	/* Nothing to do. */
3686	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3687	break;
3688
3689	case SVGA_CMD_FENCE:
3690	{
3691	SVGAFifoCmdFence *pCmdFence;
3692	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3693	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3694	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3695	{
3696	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3697	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3698
3699	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3700	{
3701	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3702	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3703	}
3704	else
3705	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3706	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3707	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3708	{
3709	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3710	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3711	}
3712	}
3713	else
3714	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3715	break;
3716	}
3717	case SVGA_CMD_UPDATE:
3718	case SVGA_CMD_UPDATE_VERBOSE:
3719	{
3720	SVGAFifoCmdUpdate *pUpdate;
3721	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3722	if (enmCmdId == SVGA_CMD_UPDATE)
3723	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3724	else
3725	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3726	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3727	/** @todo Multiple screens? */
3728	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, 0);
3729	AssertBreak(pScreen);
3730	vmsvgaUpdateScreen(pThis, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3731	break;
3732	}
3733
3734	case SVGA_CMD_DEFINE_CURSOR:
3735	{
3736	/* Followed by bitmap data. */
3737	SVGAFifoCmdDefineCursor *pCursor;
3738	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3739	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3740
3741	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3742	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3743	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3744	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3745	AssertBreak(pCursor->andMaskDepth <= 32);
3746	AssertBreak(pCursor->xorMaskDepth <= 32);
3747	RT_UNTRUSTED_VALIDATED_FENCE();
3748
3749	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3750	uint32_t cbAndMask = cbAndLine * pCursor->height;
3751	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3752	uint32_t cbXorMask = cbXorLine * pCursor->height;
3753	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3754
3755	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3756	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3757	break;
3758	}
3759
3760	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3761	{
3762	/* Followed by bitmap data. */
3763	uint32_t cbCursorShape, cbAndMask;
3764	uint8_t *pCursorCopy;
3765	uint32_t cbCmd;
3766
3767	SVGAFifoCmdDefineAlphaCursor *pCursor;
3768	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3769	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3770
3771	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3772
3773	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3774	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3775	RT_UNTRUSTED_VALIDATED_FENCE();
3776
3777	/* Refetch the bitmap data as well. */
3778	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3779	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3780	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3781
3782	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3783	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3784	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3785	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3786
3787	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3788	AssertBreak(pCursorCopy);
3789
3790	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3791	memset(pCursorCopy, 0xff, cbAndMask);
3792	/* Colour data */
3793	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3794
3795	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3796	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3797	break;
3798	}
3799
3800	case SVGA_CMD_ESCAPE:
3801	{
3802	/* Followed by nsize bytes of data. */
3803	SVGAFifoCmdEscape *pEscape;
3804	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3805	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3806
3807	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3808	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3809	RT_UNTRUSTED_VALIDATED_FENCE();
3810	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3811	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3812
3813	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3814	{
3815	AssertBreak(pEscape->size >= sizeof(uint32_t));
3816	RT_UNTRUSTED_VALIDATED_FENCE();
3817	uint32_t cmd = (uint32_t )(pEscape + 1);
3818	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3819
3820	switch (cmd)
3821	{
3822	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3823	{
3824	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3825	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3826	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3827
3828	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3829	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3830	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3831
3832	RT_NOREF_PV(pVideoCmd);
3833	break;
3834
3835	}
3836
3837	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3838	{
3839	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3840	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3841	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3842	RT_NOREF_PV(pVideoCmd);
3843	break;
3844	}
3845
3846	default:
3847	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3848	break;
3849	}
3850	}
3851	else
3852	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3853
3854	break;
3855	}
3856	# ifdef VBOX_WITH_VMSVGA3D
3857	case SVGA_CMD_DEFINE_GMR2:
3858	{
3859	SVGAFifoCmdDefineGMR2 *pCmd;
3860	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3861	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3862	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3863
3864	/* Validate current GMR id. */
3865	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3866	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3867	RT_UNTRUSTED_VALIDATED_FENCE();
3868
3869	if (!pCmd->numPages)
3870	{
3871	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3872	vmsvgaGMRFree(pThis, pCmd->gmrId);
3873	}
3874	else
3875	{
3876	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3877	if (pGMR->cMaxPages)
3878	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3879
3880	/* Not sure if we should always free the descriptor, but for simplicity
3881	we do so if the new size is smaller than the current. */
3882	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3883	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3884	vmsvgaGMRFree(pThis, pCmd->gmrId);
3885
3886	pGMR->cMaxPages = pCmd->numPages;
3887	/* The rest is done by the REMAP_GMR2 command. */
3888	}
3889	break;
3890	}
3891
3892	case SVGA_CMD_REMAP_GMR2:
3893	{
3894	/* Followed by page descriptors or guest ptr. */
3895	SVGAFifoCmdRemapGMR2 *pCmd;
3896	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3897	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3898
3899	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3900	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3901	RT_UNTRUSTED_VALIDATED_FENCE();
3902
3903	/* Calculate the size of what comes after next and fetch it. */
3904	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3905	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3906	cbCmd += sizeof(SVGAGuestPtr);
3907	else
3908	{
3909	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3910	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3911	{
3912	cbCmd += cbPageDesc;
3913	pCmd->numPages = 1;
3914	}
3915	else
3916	{
3917	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3918	cbCmd += cbPageDesc * pCmd->numPages;
3919	}
3920	}
3921	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3922
3923	/* Validate current GMR id and size. */
3924	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3925	RT_UNTRUSTED_VALIDATED_FENCE();
3926	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3927	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3928	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3929	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3930
3931	if (pCmd->numPages == 0)
3932	break;
3933
3934	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3935	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3936
3937	/*
3938	* We flatten the existing descriptors into a page array, overwrite the
3939	* pages specified in this command and then recompress the descriptor.
3940	*/
3941	/** @todo Optimize the GMR remap algorithm! */
3942
3943	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3944	uint64_t *paNewPage64 = NULL;
3945	if (pGMR->paDesc)
3946	{
3947	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3948
3949	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3950	AssertBreak(paNewPage64);
3951
3952	uint32_t idxPage = 0;
3953	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3954	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3955	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3956	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3957	RT_UNTRUSTED_VALIDATED_FENCE();
3958	}
3959
3960	/* Free the old GMR if present. */
3961	if (pGMR->paDesc)
3962	RTMemFree(pGMR->paDesc);
3963
3964	/* Allocate the maximum amount possible (everything non-continuous) */
3965	PVMSVGAGMRDESCRIPTOR paDescs;
3966	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3967	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3968
3969	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3970	{
3971	/** @todo */
3972	AssertFailed();
3973	pGMR->numDescriptors = 0;
3974	}
3975	else
3976	{
3977	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3978	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3979	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3980
3981	if (paNewPage64)
3982	{
3983	/* Overwrite the old page array with the new page values. */
3984	if (fGCPhys64)
3985	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3986	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3987	else
3988	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3989	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3990
3991	/* Use the updated page array instead of the command data. */
3992	fGCPhys64 = true;
3993	paPages64 = paNewPage64;
3994	pCmd->numPages = cNewTotalPages;
3995	}
3996
3997	/* The first page. */
3998	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3999	* applied to paNewPage64. */
4000	RTGCPHYS GCPhys;
4001	if (fGCPhys64)
4002	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4003	else
4004	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4005	paDescs[0].GCPhys = GCPhys;
4006	paDescs[0].numPages = 1;
4007
4008	/* Subsequent pages. */
4009	uint32_t iDescriptor = 0;
4010	for (uint32_t i = 1; i < pCmd->numPages; i++)
4011	{
4012	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4013	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4014	else
4015	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4016
4017	/* Continuous physical memory? */
4018	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4019	{
4020	Assert(paDescs[iDescriptor].numPages);
4021	paDescs[iDescriptor].numPages++;
4022	LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4023	}
4024	else
4025	{
4026	iDescriptor++;
4027	paDescs[iDescriptor].GCPhys = GCPhys;
4028	paDescs[iDescriptor].numPages = 1;
4029	LogFlow(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4030	}
4031	}
4032
4033	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4034	LogFlow(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4035	pGMR->numDescriptors = iDescriptor + 1;
4036	}
4037
4038	if (paNewPage64)
4039	RTMemFree(paNewPage64);
4040
4041	# ifdef DEBUG_GMR_ACCESS
4042	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
4043	# endif
4044	break;
4045	}
4046	# endif // VBOX_WITH_VMSVGA3D
4047	case SVGA_CMD_DEFINE_SCREEN:
4048	{
4049	/* The size of this command is specified by the guest and depends on capabilities. */
4050	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4051
4052	SVGAFifoCmdDefineScreen *pCmd;
4053	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4054	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4055	RT_UNTRUSTED_VALIDATED_FENCE();
4056
4057	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4058	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4059	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4060
4061	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4062	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4063	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4064
4065	uint32_t const idScreen = pCmd->screen.id;
4066	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4067
4068	uint32_t const uWidth = pCmd->screen.size.width;
4069	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4070
4071	uint32_t const uHeight = pCmd->screen.size.height;
4072	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4073
4074	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4075	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4076	AssertBreak(cbWidth <= cbPitch);
4077
4078	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4079	AssertBreak(uScreenOffset < pThis->vram_size);
4080
4081	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4082	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4083	AssertBreak( (uHeight == 0 && cbPitch == 0)
4084	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4085	RT_UNTRUSTED_VALIDATED_FENCE();
4086
4087	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4088
4089	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4090
4091	pScreen->fDefined = true;
4092	pScreen->fModified = true;
4093	pScreen->fuScreen = pCmd->screen.flags;
4094	pScreen->idScreen = idScreen;
4095	if (!fBlank)
4096	{
4097	AssertBreak(uWidth > 0 && uHeight > 0);
4098
4099	pScreen->xOrigin = pCmd->screen.root.x;
4100	pScreen->yOrigin = pCmd->screen.root.y;
4101	pScreen->cWidth = uWidth;
4102	pScreen->cHeight = uHeight;
4103	pScreen->offVRAM = uScreenOffset;
4104	pScreen->cbPitch = cbPitch;
4105	pScreen->cBpp = 32;
4106	}
4107	else
4108	{
4109	/* Keep old values. */
4110	}
4111
4112	pThis->svga.fGFBRegisters = false;
4113	vmsvgaChangeMode(pThis);
4114	break;
4115	}
4116
4117	case SVGA_CMD_DESTROY_SCREEN:
4118	{
4119	SVGAFifoCmdDestroyScreen *pCmd;
4120	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4121	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4122
4123	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4124
4125	uint32_t const idScreen = pCmd->screenId;
4126	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4127	RT_UNTRUSTED_VALIDATED_FENCE();
4128
4129	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4130	pScreen->fModified = true;
4131	pScreen->fDefined = false;
4132	pScreen->idScreen = idScreen;
4133
4134	vmsvgaChangeMode(pThis);
4135	break;
4136	}
4137
4138	case SVGA_CMD_DEFINE_GMRFB:
4139	{
4140	SVGAFifoCmdDefineGMRFB *pCmd;
4141	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4142	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4143
4144	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4145	pSVGAState->GMRFB.ptr = pCmd->ptr;
4146	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4147	pSVGAState->GMRFB.format = pCmd->format;
4148	break;
4149	}
4150
4151	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4152	{
4153	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4154	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4155	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4156
4157	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4158	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4159
4160	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4161	RT_UNTRUSTED_VALIDATED_FENCE();
4162
4163	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->destScreenId);
4164	AssertBreak(pScreen);
4165
4166	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4167	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4168
4169	/* Clip destRect to the screen dimensions. */
4170	SVGASignedRect screenRect;
4171	screenRect.left = 0;
4172	screenRect.top = 0;
4173	screenRect.right = pScreen->cWidth;
4174	screenRect.bottom = pScreen->cHeight;
4175	SVGASignedRect clipRect = pCmd->destRect;
4176	vmsvgaClipRect(&screenRect, &clipRect);
4177	RT_UNTRUSTED_VALIDATED_FENCE();
4178
4179	uint32_t const width = clipRect.right - clipRect.left;
4180	uint32_t const height = clipRect.bottom - clipRect.top;
4181
4182	if ( width == 0
4183	\|\| height == 0)
4184	break; /* Nothing to do. */
4185
4186	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4187	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4188
4189	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4190	* Prepare parameters for vmsvgaGMRTransfer.
4191	*/
4192	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4193
4194	/* Destination: host buffer which describes the screen 0 VRAM.
4195	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4196	*/
4197	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4198	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4199	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4200	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4201	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4202	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4203	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4204	+ cbScanline * clipRect.top;
4205	int32_t const cbHstPitch = cbScanline;
4206
4207	/* Source: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4208	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4209	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4210	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4211	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4212
4213	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM,
4214	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4215	gstPtr, offGst, cbGstPitch,
4216	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4217	AssertRC(rc);
4218	vmsvgaUpdateScreen(pThis, pScreen, clipRect.left, clipRect.top, width, height);
4219	break;
4220	}
4221
4222	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4223	{
4224	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4225	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4226	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4227
4228	/* Note! This can fetch 3d render results as well!! */
4229	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4230	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4231
4232	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4233	RT_UNTRUSTED_VALIDATED_FENCE();
4234
4235	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->srcScreenId);
4236	AssertBreak(pScreen);
4237
4238	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4239	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4240
4241	/* Clip destRect to the screen dimensions. */
4242	SVGASignedRect screenRect;
4243	screenRect.left = 0;
4244	screenRect.top = 0;
4245	screenRect.right = pScreen->cWidth;
4246	screenRect.bottom = pScreen->cHeight;
4247	SVGASignedRect clipRect = pCmd->srcRect;
4248	vmsvgaClipRect(&screenRect, &clipRect);
4249	RT_UNTRUSTED_VALIDATED_FENCE();
4250
4251	uint32_t const width = clipRect.right - clipRect.left;
4252	uint32_t const height = clipRect.bottom - clipRect.top;
4253
4254	if ( width == 0
4255	\|\| height == 0)
4256	break; /* Nothing to do. */
4257
4258	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4259	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4260
4261	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4262	* Prepare parameters for vmsvgaGMRTransfer.
4263	*/
4264	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4265
4266	/* Source: host buffer which describes the screen 0 VRAM.
4267	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4268	*/
4269	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4270	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4271	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4272	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4273	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4274	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4275	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4276	+ cbScanline * clipRect.top;
4277	int32_t const cbHstPitch = cbScanline;
4278
4279	/* Destination: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4280	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4281	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4282	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4283	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4284
4285	rc = vmsvgaGMRTransfer(pThis, SVGA3D_READ_HOST_VRAM,
4286	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4287	gstPtr, offGst, cbGstPitch,
4288	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4289	AssertRC(rc);
4290	break;
4291	}
4292
4293	case SVGA_CMD_ANNOTATION_FILL:
4294	{
4295	SVGAFifoCmdAnnotationFill *pCmd;
4296	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4297	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4298
4299	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4300	pSVGAState->colorAnnotation = pCmd->color;
4301	break;
4302	}
4303
4304	case SVGA_CMD_ANNOTATION_COPY:
4305	{
4306	SVGAFifoCmdAnnotationCopy *pCmd;
4307	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4308	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4309
4310	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4311	AssertFailed();
4312	break;
4313	}
4314
4315	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4316
4317	default:
4318	# ifdef VBOX_WITH_VMSVGA3D
4319	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4320	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4321	{
4322	RT_UNTRUSTED_VALIDATED_FENCE();
4323
4324	/* All 3d commands start with a common header, which defines the size of the command. */
4325	SVGA3dCmdHeader *pHdr;
4326	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4327	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4328	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4329	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4330
4331	if (RT_LIKELY(pThis->svga.f3DEnabled))
4332	{ /* likely */ }
4333	else
4334	{
4335	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4336	break;
4337	}
4338
4339	/**
4340	* Check that the 3D command has at least a_cbMin of payload bytes after the
4341	* header. Will break out of the switch if it doesn't.
4342	*/
4343	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4344	do { AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4345	RT_UNTRUSTED_VALIDATED_FENCE(); \
4346	} while (0)
4347	switch ((int)enmCmdId)
4348	{
4349	case SVGA_3D_CMD_SURFACE_DEFINE:
4350	{
4351	uint32_t cMipLevels;
4352	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4353	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4354	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4355
4356	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4357	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4358	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4359	# ifdef DEBUG_GMR_ACCESS
4360	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
4361	# endif
4362	break;
4363	}
4364
4365	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4366	{
4367	uint32_t cMipLevels;
4368	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4369	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4370	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4371
4372	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4373	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4374	pCmd->multisampleCount, pCmd->autogenFilter,
4375	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4376	break;
4377	}
4378
4379	case SVGA_3D_CMD_SURFACE_DESTROY:
4380	{
4381	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4382	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4383	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4384	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
4385	break;
4386	}
4387
4388	case SVGA_3D_CMD_SURFACE_COPY:
4389	{
4390	uint32_t cCopyBoxes;
4391	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4392	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4393	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4394
4395	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4396	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4397	break;
4398	}
4399
4400	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4401	{
4402	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4403	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4404	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4405
4406	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4407	break;
4408	}
4409
4410	case SVGA_3D_CMD_SURFACE_DMA:
4411	{
4412	uint32_t cCopyBoxes;
4413	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4414	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4415	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4416
4417	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4418	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4419	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4420	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4421	break;
4422	}
4423
4424	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4425	{
4426	uint32_t cRects;
4427	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4428	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4429	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4430
4431	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4432	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4433	break;
4434	}
4435
4436	case SVGA_3D_CMD_CONTEXT_DEFINE:
4437	{
4438	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4439	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4440	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4441
4442	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
4443	break;
4444	}
4445
4446	case SVGA_3D_CMD_CONTEXT_DESTROY:
4447	{
4448	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4449	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4450	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4451
4452	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
4453	break;
4454	}
4455
4456	case SVGA_3D_CMD_SETTRANSFORM:
4457	{
4458	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4459	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4460	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4461
4462	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
4463	break;
4464	}
4465
4466	case SVGA_3D_CMD_SETZRANGE:
4467	{
4468	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4469	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4470	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4471
4472	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
4473	break;
4474	}
4475
4476	case SVGA_3D_CMD_SETRENDERSTATE:
4477	{
4478	uint32_t cRenderStates;
4479	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4480	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4481	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4482
4483	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4484	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4485	break;
4486	}
4487
4488	case SVGA_3D_CMD_SETRENDERTARGET:
4489	{
4490	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4491	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4492	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4493
4494	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
4495	break;
4496	}
4497
4498	case SVGA_3D_CMD_SETTEXTURESTATE:
4499	{
4500	uint32_t cTextureStates;
4501	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4502	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4503	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4504
4505	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4506	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4507	break;
4508	}
4509
4510	case SVGA_3D_CMD_SETMATERIAL:
4511	{
4512	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4513	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4514	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4515
4516	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
4517	break;
4518	}
4519
4520	case SVGA_3D_CMD_SETLIGHTDATA:
4521	{
4522	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4523	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4524	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4525
4526	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
4527	break;
4528	}
4529
4530	case SVGA_3D_CMD_SETLIGHTENABLED:
4531	{
4532	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4533	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4534	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4535
4536	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
4537	break;
4538	}
4539
4540	case SVGA_3D_CMD_SETVIEWPORT:
4541	{
4542	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4543	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4544	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4545
4546	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
4547	break;
4548	}
4549
4550	case SVGA_3D_CMD_SETCLIPPLANE:
4551	{
4552	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4553	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4554	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4555
4556	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
4557	break;
4558	}
4559
4560	case SVGA_3D_CMD_CLEAR:
4561	{
4562	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4563	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4564	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4565
4566	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4567	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4568	break;
4569	}
4570
4571	case SVGA_3D_CMD_PRESENT:
4572	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4573	{
4574	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4575	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4576	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4577	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4578	else
4579	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4580
4581	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4582
4583	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4584	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4585	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4586	break;
4587	}
4588
4589	case SVGA_3D_CMD_SHADER_DEFINE:
4590	{
4591	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4592	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4593	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4594
4595	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4596	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4597	break;
4598	}
4599
4600	case SVGA_3D_CMD_SHADER_DESTROY:
4601	{
4602	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4603	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4604	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4605
4606	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4607	break;
4608	}
4609
4610	case SVGA_3D_CMD_SET_SHADER:
4611	{
4612	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4613	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4614	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4615
4616	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4617	break;
4618	}
4619
4620	case SVGA_3D_CMD_SET_SHADER_CONST:
4621	{
4622	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4623	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4624	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4625
4626	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4627	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4628	break;
4629	}
4630
4631	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4632	{
4633	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4634	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4635	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4636
4637	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4638	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4639	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4640	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4641	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4642
4643	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4644	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4645
4646	RT_UNTRUSTED_VALIDATED_FENCE();
4647
4648	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4649	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4650	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4651
4652	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4653	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4654	pNumRange, cVertexDivisor, pVertexDivisor);
4655	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4656	break;
4657	}
4658
4659	case SVGA_3D_CMD_SETSCISSORRECT:
4660	{
4661	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4662	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4663	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4664
4665	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4666	break;
4667	}
4668
4669	case SVGA_3D_CMD_BEGIN_QUERY:
4670	{
4671	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4672	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4673	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4674
4675	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4676	break;
4677	}
4678
4679	case SVGA_3D_CMD_END_QUERY:
4680	{
4681	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4682	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4683	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4684
4685	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4686	break;
4687	}
4688
4689	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4690	{
4691	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4692	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4693	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4694
4695	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4696	break;
4697	}
4698
4699	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4700	{
4701	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4702	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4703	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4704
4705	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4706	break;
4707	}
4708
4709	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4710	/* context id + surface id? */
4711	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4712	break;
4713	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4714	/* context id + surface id? */
4715	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4716	break;
4717
4718	default:
4719	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4720	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4721	break;
4722	}
4723	}
4724	else
4725	# endif // VBOX_WITH_VMSVGA3D
4726	{
4727	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4728	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4729	}
4730	}
4731
4732	/* Go to the next slot */
4733	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4734	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4735	if (offCurrentCmd >= offFifoMax)
4736	{
4737	offCurrentCmd -= offFifoMax - offFifoMin;
4738	Assert(offCurrentCmd >= offFifoMin);
4739	Assert(offCurrentCmd < offFifoMax);
4740	}
4741	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4742	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4743
4744	/*
4745	* Raise IRQ if required. Must enter the critical section here
4746	* before making final decisions here, otherwise cubebench and
4747	* others may end up waiting forever.
4748	*/
4749	if ( u32IrqStatus
4750	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4751	{
4752	int rc2 = PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
4753	AssertRC(rc2);
4754
4755	/* FIFO progress might trigger an interrupt. */
4756	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4757	{
4758	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4759	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4760	}
4761
4762	/* Unmasked IRQ pending? */
4763	if (pThis->svga.u32IrqMask & u32IrqStatus)
4764	{
4765	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4766	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4767	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4768	}
4769
4770	PDMCritSectLeave(&pThis->CritSect);
4771	}
4772	}
4773
4774	/* If really done, clear the busy flag. */
4775	if (fDone)
4776	{
4777	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4778	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4779	}
4780	}
4781
4782	/*
4783	* Free the bounce buffer. (There are no returns above!)
4784	*/
4785	RTMemFree(pbBounceBuf);
4786
4787	return VINF_SUCCESS;
4788	}
4789
4790	/**
4791	* Free the specified GMR
4792	*
4793	* @param pThis VGA device instance data.
4794	* @param idGMR GMR id
4795	*/
4796	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4797	{
4798	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4799
4800	/* Free the old descriptor if present. */
4801	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4802	if ( pGMR->numDescriptors
4803	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4804	{
4805	# ifdef DEBUG_GMR_ACCESS
4806	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4807	# endif
4808
4809	Assert(pGMR->paDesc);
4810	RTMemFree(pGMR->paDesc);
4811	pGMR->paDesc = NULL;
4812	pGMR->numDescriptors = 0;
4813	pGMR->cbTotal = 0;
4814	pGMR->cMaxPages = 0;
4815	}
4816	Assert(!pGMR->cMaxPages);
4817	Assert(!pGMR->cbTotal);
4818	}
4819
4820	/**
4821	* Copy between a GMR and a host memory buffer.
4822	*
4823	* @returns VBox status code.
4824	* @param pThis VGA device instance data.
4825	* @param enmTransferType Transfer type (read/write)
4826	* @param pbHstBuf Host buffer pointer (valid)
4827	* @param cbHstBuf Size of host buffer (valid)
4828	* @param offHst Host buffer offset of the first scanline
4829	* @param cbHstPitch Destination buffer pitch
4830	* @param gstPtr GMR description
4831	* @param offGst Guest buffer offset of the first scanline
4832	* @param cbGstPitch Guest buffer pitch
4833	* @param cbWidth Width in bytes to copy
4834	* @param cHeight Number of scanllines to copy
4835	*/
4836	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType,
4837	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4838	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4839	uint32_t cbWidth, uint32_t cHeight)
4840	{
4841	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4842	int rc;
4843
4844	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4845	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4846	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4847	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4848	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4849
4850	PGMR pGMR;
4851	uint32_t cbGmr; /* The GMR size in bytes. */
4852	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4853	{
4854	pGMR = NULL;
4855	cbGmr = pThis->vram_size;
4856	}
4857	else
4858	{
4859	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4860	RT_UNTRUSTED_VALIDATED_FENCE();
4861	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4862	cbGmr = pGMR->cbTotal;
4863	}
4864
4865	/*
4866	* GMR
4867	*/
4868	/* Calculate GMR offset of the data to be copied. */
4869	AssertMsgReturn(gstPtr.offset < cbGmr,
4870	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4871	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4872	VERR_INVALID_PARAMETER);
4873	RT_UNTRUSTED_VALIDATED_FENCE();
4874	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4875	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4876	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4877	VERR_INVALID_PARAMETER);
4878	RT_UNTRUSTED_VALIDATED_FENCE();
4879	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4880
4881	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4882	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4883	AssertMsgReturn(cbGmrScanline != 0,
4884	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4885	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4886	VERR_INVALID_PARAMETER);
4887	RT_UNTRUSTED_VALIDATED_FENCE();
4888	AssertMsgReturn(cbWidth <= cbGmrScanline,
4889	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4890	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4891	VERR_INVALID_PARAMETER);
4892	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4893	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4894	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4895	VERR_INVALID_PARAMETER);
4896	RT_UNTRUSTED_VALIDATED_FENCE();
4897
4898	/* How many bytes are available for the data in the GMR. */
4899	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4900
4901	/* How many scanlines would fit into the available data. */
4902	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4903	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4904	if (cbWidth <= cbGmrLastScanline)
4905	++cGmrScanlines;
4906
4907	if (cHeight > cGmrScanlines)
4908	cHeight = cGmrScanlines;
4909
4910	AssertMsgReturn(cHeight > 0,
4911	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4912	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4913	VERR_INVALID_PARAMETER);
4914	RT_UNTRUSTED_VALIDATED_FENCE();
4915
4916	/*
4917	* Host buffer.
4918	*/
4919	AssertMsgReturn(offHst < cbHstBuf,
4920	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4921	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4922	VERR_INVALID_PARAMETER);
4923
4924	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4925	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4926	AssertMsgReturn(cbHstScanline != 0,
4927	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4928	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4929	VERR_INVALID_PARAMETER);
4930	AssertMsgReturn(cbWidth <= cbHstScanline,
4931	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4932	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4933	VERR_INVALID_PARAMETER);
4934	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4935	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4936	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4937	VERR_INVALID_PARAMETER);
4938
4939	/* How many bytes are available for the data in the buffer. */
4940	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4941
4942	/* How many scanlines would fit into the available data. */
4943	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4944	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4945	if (cbWidth <= cbHstLastScanline)
4946	++cHstScanlines;
4947
4948	if (cHeight > cHstScanlines)
4949	cHeight = cHstScanlines;
4950
4951	AssertMsgReturn(cHeight > 0,
4952	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4953	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4954	VERR_INVALID_PARAMETER);
4955
4956	uint8_t *pbHst = pbHstBuf + offHst;
4957
4958	/* Shortcut for the framebuffer. */
4959	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4960	{
4961	uint8_t *pbGst = pThis->CTX_SUFF(vram_ptr) + offGmr;
4962
4963	uint8_t const *pbSrc;
4964	int32_t cbSrcPitch;
4965	uint8_t *pbDst;
4966	int32_t cbDstPitch;
4967
4968	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4969	{
4970	pbSrc = pbHst;
4971	cbSrcPitch = cbHstPitch;
4972	pbDst = pbGst;
4973	cbDstPitch = cbGstPitch;
4974	}
4975	else
4976	{
4977	pbSrc = pbGst;
4978	cbSrcPitch = cbGstPitch;
4979	pbDst = pbHst;
4980	cbDstPitch = cbHstPitch;
4981	}
4982
4983	if ( cbWidth == (uint32_t)cbGstPitch
4984	&& cbGstPitch == cbHstPitch)
4985	{
4986	/* Entire scanlines, positive pitch. */
4987	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4988	}
4989	else
4990	{
4991	for (uint32_t i = 0; i < cHeight; ++i)
4992	{
4993	memcpy(pbDst, pbSrc, cbWidth);
4994
4995	pbDst += cbDstPitch;
4996	pbSrc += cbSrcPitch;
4997	}
4998	}
4999	return VINF_SUCCESS;
5000	}
5001
5002	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
5003	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
5004
5005	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
5006	uint32_t iDesc = 0; /* Index in the descriptor array. */
5007	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
5008	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
5009	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
5010	for (uint32_t i = 0; i < cHeight; ++i)
5011	{
5012	uint32_t cbCurrentWidth = cbWidth;
5013	uint32_t offGmrCurrent = offGmrScanline;
5014	uint8_t *pbCurrentHost = pbHstScanline;
5015
5016	/* Find the right descriptor */
5017	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5018	{
5019	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5020	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5021	++iDesc;
5022	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5023	}
5024
5025	while (cbCurrentWidth)
5026	{
5027	uint32_t cbToCopy;
5028
5029	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5030	{
5031	cbToCopy = cbCurrentWidth;
5032	}
5033	else
5034	{
5035	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5036	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5037	}
5038
5039	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5040
5041	LogFlowFunc(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5042
5043	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5044	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5045	else
5046	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5047	AssertRCBreak(rc);
5048
5049	cbCurrentWidth -= cbToCopy;
5050	offGmrCurrent += cbToCopy;
5051	pbCurrentHost += cbToCopy;
5052
5053	/* Go to the next descriptor if there's anything left. */
5054	if (cbCurrentWidth)
5055	{
5056	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5057	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5058	++iDesc;
5059	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5060	}
5061	}
5062
5063	offGmrScanline += cbGstPitch;
5064	pbHstScanline += cbHstPitch;
5065	}
5066
5067	return VINF_SUCCESS;
5068	}
5069
5070
5071	/**
5072	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5073	*
5074	* @param pSizeSrc Source surface dimensions.
5075	* @param pSizeDest Destination surface dimensions.
5076	* @param pBox Coordinates to be clipped.
5077	*/
5078	void vmsvgaClipCopyBox(const SVGA3dSize *pSizeSrc,
5079	const SVGA3dSize *pSizeDest,
5080	SVGA3dCopyBox *pBox)
5081	{
5082	/* Src x, w */
5083	if (pBox->srcx > pSizeSrc->width)
5084	pBox->srcx = pSizeSrc->width;
5085	if (pBox->w > pSizeSrc->width - pBox->srcx)
5086	pBox->w = pSizeSrc->width - pBox->srcx;
5087
5088	/* Src y, h */
5089	if (pBox->srcy > pSizeSrc->height)
5090	pBox->srcy = pSizeSrc->height;
5091	if (pBox->h > pSizeSrc->height - pBox->srcy)
5092	pBox->h = pSizeSrc->height - pBox->srcy;
5093
5094	/* Src z, d */
5095	if (pBox->srcz > pSizeSrc->depth)
5096	pBox->srcz = pSizeSrc->depth;
5097	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5098	pBox->d = pSizeSrc->depth - pBox->srcz;
5099
5100	/* Dest x, w */
5101	if (pBox->x > pSizeDest->width)
5102	pBox->x = pSizeDest->width;
5103	if (pBox->w > pSizeDest->width - pBox->x)
5104	pBox->w = pSizeDest->width - pBox->x;
5105
5106	/* Dest y, h */
5107	if (pBox->y > pSizeDest->height)
5108	pBox->y = pSizeDest->height;
5109	if (pBox->h > pSizeDest->height - pBox->y)
5110	pBox->h = pSizeDest->height - pBox->y;
5111
5112	/* Dest z, d */
5113	if (pBox->z > pSizeDest->depth)
5114	pBox->z = pSizeDest->depth;
5115	if (pBox->d > pSizeDest->depth - pBox->z)
5116	pBox->d = pSizeDest->depth - pBox->z;
5117	}
5118
5119	/**
5120	* Unsigned coordinates in pBox. Clip to [0; pSize).
5121	*
5122	* @param pSize Source surface dimensions.
5123	* @param pBox Coordinates to be clipped.
5124	*/
5125	void vmsvgaClipBox(const SVGA3dSize *pSize,
5126	SVGA3dBox *pBox)
5127	{
5128	/* x, w */
5129	if (pBox->x > pSize->width)
5130	pBox->x = pSize->width;
5131	if (pBox->w > pSize->width - pBox->x)
5132	pBox->w = pSize->width - pBox->x;
5133
5134	/* y, h */
5135	if (pBox->y > pSize->height)
5136	pBox->y = pSize->height;
5137	if (pBox->h > pSize->height - pBox->y)
5138	pBox->h = pSize->height - pBox->y;
5139
5140	/* z, d */
5141	if (pBox->z > pSize->depth)
5142	pBox->z = pSize->depth;
5143	if (pBox->d > pSize->depth - pBox->z)
5144	pBox->d = pSize->depth - pBox->z;
5145	}
5146
5147	/**
5148	* Clip.
5149	*
5150	* @param pBound Bounding rectangle.
5151	* @param pRect Rectangle to be clipped.
5152	*/
5153	void vmsvgaClipRect(SVGASignedRect const *pBound,
5154	SVGASignedRect *pRect)
5155	{
5156	int32_t left;
5157	int32_t top;
5158	int32_t right;
5159	int32_t bottom;
5160
5161	/* Right order. */
5162	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5163	if (pRect->left < pRect->right)
5164	{
5165	left = pRect->left;
5166	right = pRect->right;
5167	}
5168	else
5169	{
5170	left = pRect->right;
5171	right = pRect->left;
5172	}
5173	if (pRect->top < pRect->bottom)
5174	{
5175	top = pRect->top;
5176	bottom = pRect->bottom;
5177	}
5178	else
5179	{
5180	top = pRect->bottom;
5181	bottom = pRect->top;
5182	}
5183
5184	if (left < pBound->left)
5185	left = pBound->left;
5186	if (right < pBound->left)
5187	right = pBound->left;
5188
5189	if (left > pBound->right)
5190	left = pBound->right;
5191	if (right > pBound->right)
5192	right = pBound->right;
5193
5194	if (top < pBound->top)
5195	top = pBound->top;
5196	if (bottom < pBound->top)
5197	bottom = pBound->top;
5198
5199	if (top > pBound->bottom)
5200	top = pBound->bottom;
5201	if (bottom > pBound->bottom)
5202	bottom = pBound->bottom;
5203
5204	pRect->left = left;
5205	pRect->right = right;
5206	pRect->top = top;
5207	pRect->bottom = bottom;
5208	}
5209
5210	/**
5211	* Unblock the FIFO I/O thread so it can respond to a state change.
5212	*
5213	* @returns VBox status code.
5214	* @param pDevIns The VGA device instance.
5215	* @param pThread The send thread.
5216	*/
5217	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5218	{
5219	RT_NOREF(pDevIns);
5220	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5221	Log(("vmsvgaFIFOLoopWakeUp\n"));
5222	return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5223	}
5224
5225	/**
5226	* Enables or disables dirty page tracking for the framebuffer
5227	*
5228	* @param pThis VGA device instance data.
5229	* @param fTraces Enable/disable traces
5230	*/
5231	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
5232	{
5233	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5234	&& !fTraces)
5235	{
5236	//Assert(pThis->svga.fTraces);
5237	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5238	return;
5239	}
5240
5241	pThis->svga.fTraces = fTraces;
5242	if (pThis->svga.fTraces)
5243	{
5244	unsigned cbFrameBuffer = pThis->vram_size;
5245
5246	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5247	/** @todo How does this work with screens? */
5248	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5249	{
5250	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5251	Assert(pThis->svga.cbScanline);
5252	#endif
5253	/* Hardware enabled; return real framebuffer size .*/
5254	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5255	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5256	}
5257
5258	if (!pThis->svga.fVRAMTracking)
5259	{
5260	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5261	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
5262	pThis->svga.fVRAMTracking = true;
5263	}
5264	}
5265	else
5266	{
5267	if (pThis->svga.fVRAMTracking)
5268	{
5269	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
5270	vgaR3UnregisterVRAMHandler(pThis);
5271	pThis->svga.fVRAMTracking = false;
5272	}
5273	}
5274	}
5275
5276	/**
5277	* @callback_method_impl{FNPCIIOREGIONMAP}
5278	*/
5279	DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5280	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5281	{
5282	int rc;
5283	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5284
5285	Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5286	if (enmType == PCI_ADDRESS_SPACE_IO)
5287	{
5288	AssertReturn(iRegion == pThis->pciRegions.iIO, VERR_INTERNAL_ERROR);
5289	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5290	vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr /, NULL / InStr */, "VMSVGA");
5291	if (RT_FAILURE(rc))
5292	return rc;
5293	if (pThis->fR0Enabled)
5294	{
5295	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5296	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5297	if (RT_FAILURE(rc))
5298	return rc;
5299	}
5300	if (pThis->fGCEnabled)
5301	{
5302	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5303	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5304	if (RT_FAILURE(rc))
5305	return rc;
5306	}
5307
5308	pThis->svga.BasePort = GCPhysAddress;
5309	Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
5310	}
5311	else
5312	{
5313	AssertReturn(iRegion == pThis->pciRegions.iFIFO && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
5314	if (GCPhysAddress != NIL_RTGCPHYS)
5315	{
5316	/*
5317	* Mapping the FIFO RAM.
5318	*/
5319	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5320	rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
5321	AssertRC(rc);
5322
5323	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5324	if (RT_SUCCESS(rc))
5325	{
5326	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5327	# ifdef DEBUG_FIFO_ACCESS
5328	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5329	# else
5330	GCPhysAddress + PAGE_SIZE - 1,
5331	# endif
5332	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5333	"VMSVGA FIFO");
5334	AssertRC(rc);
5335	}
5336	# endif
5337	if (RT_SUCCESS(rc))
5338	{
5339	pThis->svga.GCPhysFIFO = GCPhysAddress;
5340	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5341	}
5342	}
5343	else
5344	{
5345	Assert(pThis->svga.GCPhysFIFO);
5346	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5347	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5348	AssertRC(rc);
5349	# endif
5350	pThis->svga.GCPhysFIFO = 0;
5351	}
5352	}
5353	return VINF_SUCCESS;
5354	}
5355
5356	# ifdef VBOX_WITH_VMSVGA3D
5357
5358	/**
5359	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5360	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5361	*
5362	* @param pThis The VGA device instance data.
5363	* @param sid Either UINT32_MAX or the ID of a specific
5364	* surface. If UINT32_MAX is used, all surfaces
5365	* are processed.
5366	*/
5367	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
5368	{
5369	vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5370	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5371	}
5372
5373
5374	/**
5375	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5376	*/
5377	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5378	{
5379	/* There might be a specific surface ID at the start of the
5380	arguments, if not show all surfaces. */
5381	uint32_t sid = UINT32_MAX;
5382	if (pszArgs)
5383	pszArgs = RTStrStripL(pszArgs);
5384	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5385	sid = RTStrToUInt32(pszArgs);
5386
5387	/* Verbose or terse display, we default to verbose. */
5388	bool fVerbose = true;
5389	if (RTStrIStr(pszArgs, "terse"))
5390	fVerbose = false;
5391
5392	/* The size of the ascii art (x direction, y is 3/4 of x). */
5393	uint32_t cxAscii = 80;
5394	if (RTStrIStr(pszArgs, "gigantic"))
5395	cxAscii = 300;
5396	else if (RTStrIStr(pszArgs, "huge"))
5397	cxAscii = 180;
5398	else if (RTStrIStr(pszArgs, "big"))
5399	cxAscii = 132;
5400	else if (RTStrIStr(pszArgs, "normal"))
5401	cxAscii = 80;
5402	else if (RTStrIStr(pszArgs, "medium"))
5403	cxAscii = 64;
5404	else if (RTStrIStr(pszArgs, "small"))
5405	cxAscii = 48;
5406	else if (RTStrIStr(pszArgs, "tiny"))
5407	cxAscii = 24;
5408
5409	/* Y invert the image when producing the ASCII art. */
5410	bool fInvY = false;
5411	if (RTStrIStr(pszArgs, "invy"))
5412	fInvY = true;
5413
5414	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5415	}
5416
5417
5418	/**
5419	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5420	*/
5421	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5422	{
5423	/* pszArg = "sid[>dir]"
5424	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5425	*/
5426	char *pszBitmapPath = NULL;
5427	uint32_t sid = UINT32_MAX;
5428	if (pszArgs)
5429	pszArgs = RTStrStripL(pszArgs);
5430	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5431	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5432	if ( pszBitmapPath
5433	&& *pszBitmapPath == '>')
5434	++pszBitmapPath;
5435
5436	const bool fVerbose = true;
5437	const uint32_t cxAscii = 0; /* No ASCII */
5438	const bool fInvY = false; /* Do not invert. */
5439	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5440	}
5441
5442
5443	/**
5444	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5445	*/
5446	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5447	{
5448	/* There might be a specific surface ID at the start of the
5449	arguments, if not show all contexts. */
5450	uint32_t sid = UINT32_MAX;
5451	if (pszArgs)
5452	pszArgs = RTStrStripL(pszArgs);
5453	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5454	sid = RTStrToUInt32(pszArgs);
5455
5456	/* Verbose or terse display, we default to verbose. */
5457	bool fVerbose = true;
5458	if (RTStrIStr(pszArgs, "terse"))
5459	fVerbose = false;
5460
5461	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
5462	}
5463
5464	# endif /* VBOX_WITH_VMSVGA3D */
5465
5466	/**
5467	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5468	*/
5469	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5470	{
5471	RT_NOREF(pszArgs);
5472	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5473	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5474	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.pFIFOR3;
5475
5476	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5477	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5478	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
5479	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5480	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5481	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5482	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5483	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5484	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5485	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5486	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5487	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5488	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5489	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5490	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5491	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5492	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5493	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5494	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5495	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5496	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5497	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5498	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5499
5500	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5501	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5502	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5503	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5504
5505	# ifdef VBOX_WITH_VMSVGA3D
5506	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5507	# endif
5508	if (pThis->pDrv)
5509	{
5510	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThis->pDrv->cx, pThis->pDrv->cy, pThis->pDrv->cBits);
5511	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThis->pDrv->cbScanline, pThis->pDrv->cbScanline);
5512	}
5513	}
5514
5515	/** Portion of VMSVGA state which must be loaded oin the FIFO thread.
5516	*/
5517	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5518	{
5519	RT_NOREF(uPass);
5520
5521	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5522	int rc;
5523
5524	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5525	{
5526	uint32_t cScreens = 0;
5527	rc = SSMR3GetU32(pSSM, &cScreens);
5528	AssertRCReturn(rc, rc);
5529	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5530	("cScreens=%#x\n", cScreens),
5531	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5532
5533	for (uint32_t i = 0; i < cScreens; ++i)
5534	{
5535	VMSVGASCREENOBJECT screen;
5536	RT_ZERO(screen);
5537
5538	rc = SSMR3GetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5539	AssertLogRelRCReturn(rc, rc);
5540
5541	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5542	{
5543	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5544	*pScreen = screen;
5545	pScreen->fModified = true;
5546	}
5547	else
5548	{
5549	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5550	}
5551	}
5552	}
5553	else
5554	{
5555	/* Try to setup at least the first screen. */
5556	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5557	pScreen->fDefined = true;
5558	pScreen->fModified = true;
5559	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5560	pScreen->idScreen = 0;
5561	pScreen->xOrigin = 0;
5562	pScreen->yOrigin = 0;
5563	pScreen->offVRAM = pThis->svga.uScreenOffset;
5564	pScreen->cbPitch = pThis->svga.cbScanline;
5565	pScreen->cWidth = pThis->svga.uWidth;
5566	pScreen->cHeight = pThis->svga.uHeight;
5567	pScreen->cBpp = pThis->svga.uBpp;
5568	}
5569
5570	return VINF_SUCCESS;
5571	}
5572
5573	/**
5574	* @copydoc FNSSMDEVLOADEXEC
5575	*/
5576	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5577	{
5578	RT_NOREF(uPass);
5579	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5580	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5581	int rc;
5582
5583	/* Load our part of the VGAState */
5584	rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5585	AssertRCReturn(rc, rc);
5586
5587	/* Load the VGA framebuffer. */
5588	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5589	uint32_t cbVgaFramebuffer = _32K;
5590	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5591	{
5592	rc = SSMR3GetU32(pSSM, &cbVgaFramebuffer);
5593	AssertRCReturn(rc, rc);
5594	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5595	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5596	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5597	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5598	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5599	}
5600	rc = SSMR3GetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5601	AssertRCReturn(rc, rc);
5602	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5603	SSMR3Skip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5604	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5605	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5606
5607	/* Load the VMSVGA state. */
5608	rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5609	AssertRCReturn(rc, rc);
5610
5611	/* Load the active cursor bitmaps. */
5612	if (pSVGAState->Cursor.fActive)
5613	{
5614	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5615	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5616
5617	rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5618	AssertRCReturn(rc, rc);
5619	}
5620
5621	/* Load the GMR state. */
5622	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5623	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5624	{
5625	rc = SSMR3GetU32(pSSM, &cGMR);
5626	AssertRCReturn(rc, rc);
5627	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5628	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5629	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5630	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5631	}
5632
5633	if (pThis->svga.cGMR != cGMR)
5634	{
5635	/* Reallocate GMR array. */
5636	Assert(pSVGAState->paGMR != NULL);
5637	RTMemFree(pSVGAState->paGMR);
5638	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5639	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5640	pThis->svga.cGMR = cGMR;
5641	}
5642
5643	for (uint32_t i = 0; i < cGMR; ++i)
5644	{
5645	PGMR pGMR = &pSVGAState->paGMR[i];
5646
5647	rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5648	AssertRCReturn(rc, rc);
5649
5650	if (pGMR->numDescriptors)
5651	{
5652	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5653	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5654	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5655
5656	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5657	{
5658	rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5659	AssertRCReturn(rc, rc);
5660	}
5661	}
5662	}
5663
5664	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5665	vmsvga3dPowerOn(pThis);
5666	# endif
5667
5668	VMSVGA_STATE_LOAD LoadState;
5669	LoadState.pSSM = pSSM;
5670	LoadState.uVersion = uVersion;
5671	LoadState.uPass = uPass;
5672	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5673	AssertLogRelRCReturn(rc, rc);
5674
5675	return VINF_SUCCESS;
5676	}
5677
5678	/**
5679	* Reinit the video mode after the state has been loaded.
5680	*/
5681	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
5682	{
5683	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5684	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5685
5686	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5687
5688	/* Set the active cursor. */
5689	if (pSVGAState->Cursor.fActive)
5690	{
5691	int rc;
5692
5693	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
5694	true,
5695	true,
5696	pSVGAState->Cursor.xHotspot,
5697	pSVGAState->Cursor.yHotspot,
5698	pSVGAState->Cursor.width,
5699	pSVGAState->Cursor.height,
5700	pSVGAState->Cursor.pData);
5701	AssertRC(rc);
5702	}
5703	return VINF_SUCCESS;
5704	}
5705
5706	/**
5707	* Portion of SVGA state which must be saved in the FIFO thread.
5708	*/
5709	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM)
5710	{
5711	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5712	int rc;
5713
5714	/* Save the screen objects. */
5715	/* Count defined screen object. */
5716	uint32_t cScreens = 0;
5717	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5718	{
5719	if (pSVGAState->aScreens[i].fDefined)
5720	++cScreens;
5721	}
5722
5723	rc = SSMR3PutU32(pSSM, cScreens);
5724	AssertLogRelRCReturn(rc, rc);
5725
5726	for (uint32_t i = 0; i < cScreens; ++i)
5727	{
5728	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5729
5730	rc = SSMR3PutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5731	AssertLogRelRCReturn(rc, rc);
5732	}
5733	return VINF_SUCCESS;
5734	}
5735
5736	/**
5737	* @copydoc FNSSMDEVSAVEEXEC
5738	*/
5739	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5740	{
5741	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5742	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5743	int rc;
5744
5745	/* Save our part of the VGAState */
5746	rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5747	AssertLogRelRCReturn(rc, rc);
5748
5749	/* Save the framebuffer backup. */
5750	rc = SSMR3PutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5751	rc = SSMR3PutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5752	AssertLogRelRCReturn(rc, rc);
5753
5754	/* Save the VMSVGA state. */
5755	rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5756	AssertLogRelRCReturn(rc, rc);
5757
5758	/* Save the active cursor bitmaps. */
5759	if (pSVGAState->Cursor.fActive)
5760	{
5761	rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5762	AssertLogRelRCReturn(rc, rc);
5763	}
5764
5765	/* Save the GMR state */
5766	rc = SSMR3PutU32(pSSM, pThis->svga.cGMR);
5767	AssertLogRelRCReturn(rc, rc);
5768	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5769	{
5770	PGMR pGMR = &pSVGAState->paGMR[i];
5771
5772	rc = SSMR3PutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5773	AssertLogRelRCReturn(rc, rc);
5774
5775	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5776	{
5777	rc = SSMR3PutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5778	AssertLogRelRCReturn(rc, rc);
5779	}
5780	}
5781
5782	/*
5783	* Must save some state (3D in particular) in the FIFO thread.
5784	*/
5785	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5786	AssertLogRelRCReturn(rc, rc);
5787
5788	return VINF_SUCCESS;
5789	}
5790
5791	/**
5792	* Destructor for PVMSVGAR3STATE structure.
5793	*
5794	* @param pThis The VGA instance.
5795	* @param pSVGAState Pointer to the structure. It is not deallocated.
5796	*/
5797	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5798	{
5799	#ifndef VMSVGA_USE_EMT_HALT_CODE
5800	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5801	{
5802	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5803	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5804	}
5805	#endif
5806
5807	if (pSVGAState->Cursor.fActive)
5808	{
5809	RTMemFree(pSVGAState->Cursor.pData);
5810	pSVGAState->Cursor.pData = NULL;
5811	pSVGAState->Cursor.fActive = false;
5812	}
5813
5814	if (pSVGAState->paGMR)
5815	{
5816	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5817	if (pSVGAState->paGMR[i].paDesc)
5818	RTMemFree(pSVGAState->paGMR[i].paDesc);
5819
5820	RTMemFree(pSVGAState->paGMR);
5821	pSVGAState->paGMR = NULL;
5822	}
5823	}
5824
5825	/**
5826	* Constructor for PVMSVGAR3STATE structure.
5827	*
5828	* @returns VBox status code.
5829	* @param pThis The VGA instance.
5830	* @param pSVGAState Pointer to the structure. It is already allocated.
5831	*/
5832	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5833	{
5834	int rc = VINF_SUCCESS;
5835	RT_ZERO(*pSVGAState);
5836
5837	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5838	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5839
5840	#ifndef VMSVGA_USE_EMT_HALT_CODE
5841	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5842	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5843	AssertRCReturn(rc, rc);
5844	#endif
5845
5846	return rc;
5847	}
5848
5849	/**
5850	* Initializes the host capabilities: registers and FIFO.
5851	*
5852	* @returns VBox status code.
5853	* @param pThis The VGA instance.
5854	*/
5855	static void vmsvgaInitCaps(PVGASTATE pThis)
5856	{
5857	/* Register caps. */
5858	pThis->svga.u32RegCaps = SVGA_CAP_GMR
5859	\| SVGA_CAP_GMR2
5860	\| SVGA_CAP_CURSOR
5861	\| SVGA_CAP_CURSOR_BYPASS_2
5862	\| SVGA_CAP_EXTENDED_FIFO
5863	\| SVGA_CAP_IRQMASK
5864	\| SVGA_CAP_PITCHLOCK
5865	\| SVGA_CAP_TRACES
5866	\| SVGA_CAP_SCREEN_OBJECT_2
5867	\| SVGA_CAP_ALPHA_CURSOR;
5868	# ifdef VBOX_WITH_VMSVGA3D
5869	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5870	# endif
5871
5872	/* Clear the FIFO. */
5873	RT_BZERO(pThis->svga.pFIFOR3, pThis->svga.cbFIFO);
5874
5875	/* Setup FIFO capabilities. */
5876	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5877	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5878	\| SVGA_FIFO_CAP_GMR2
5879	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5880	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
5881	\| SVGA_FIFO_CAP_RESERVE
5882	\| SVGA_FIFO_CAP_PITCHLOCK;
5883
5884	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5885	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5886	}
5887
5888	# ifdef VBOX_WITH_VMSVGA3D
5889	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5890	static const char * const g_apszVmSvgaDevCapNames[] =
5891	{
5892	"x3D", /* = 0 */
5893	"xMAX_LIGHTS",
5894	"xMAX_TEXTURES",
5895	"xMAX_CLIP_PLANES",
5896	"xVERTEX_SHADER_VERSION",
5897	"xVERTEX_SHADER",
5898	"xFRAGMENT_SHADER_VERSION",
5899	"xFRAGMENT_SHADER",
5900	"xMAX_RENDER_TARGETS",
5901	"xS23E8_TEXTURES",
5902	"xS10E5_TEXTURES",
5903	"xMAX_FIXED_VERTEXBLEND",
5904	"xD16_BUFFER_FORMAT",
5905	"xD24S8_BUFFER_FORMAT",
5906	"xD24X8_BUFFER_FORMAT",
5907	"xQUERY_TYPES",
5908	"xTEXTURE_GRADIENT_SAMPLING",
5909	"rMAX_POINT_SIZE",
5910	"xMAX_SHADER_TEXTURES",
5911	"xMAX_TEXTURE_WIDTH",
5912	"xMAX_TEXTURE_HEIGHT",
5913	"xMAX_VOLUME_EXTENT",
5914	"xMAX_TEXTURE_REPEAT",
5915	"xMAX_TEXTURE_ASPECT_RATIO",
5916	"xMAX_TEXTURE_ANISOTROPY",
5917	"xMAX_PRIMITIVE_COUNT",
5918	"xMAX_VERTEX_INDEX",
5919	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5920	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5921	"xMAX_VERTEX_SHADER_TEMPS",
5922	"xMAX_FRAGMENT_SHADER_TEMPS",
5923	"xTEXTURE_OPS",
5924	"xSURFACEFMT_X8R8G8B8",
5925	"xSURFACEFMT_A8R8G8B8",
5926	"xSURFACEFMT_A2R10G10B10",
5927	"xSURFACEFMT_X1R5G5B5",
5928	"xSURFACEFMT_A1R5G5B5",
5929	"xSURFACEFMT_A4R4G4B4",
5930	"xSURFACEFMT_R5G6B5",
5931	"xSURFACEFMT_LUMINANCE16",
5932	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5933	"xSURFACEFMT_ALPHA8",
5934	"xSURFACEFMT_LUMINANCE8",
5935	"xSURFACEFMT_Z_D16",
5936	"xSURFACEFMT_Z_D24S8",
5937	"xSURFACEFMT_Z_D24X8",
5938	"xSURFACEFMT_DXT1",
5939	"xSURFACEFMT_DXT2",
5940	"xSURFACEFMT_DXT3",
5941	"xSURFACEFMT_DXT4",
5942	"xSURFACEFMT_DXT5",
5943	"xSURFACEFMT_BUMPX8L8V8U8",
5944	"xSURFACEFMT_A2W10V10U10",
5945	"xSURFACEFMT_BUMPU8V8",
5946	"xSURFACEFMT_Q8W8V8U8",
5947	"xSURFACEFMT_CxV8U8",
5948	"xSURFACEFMT_R_S10E5",
5949	"xSURFACEFMT_R_S23E8",
5950	"xSURFACEFMT_RG_S10E5",
5951	"xSURFACEFMT_RG_S23E8",
5952	"xSURFACEFMT_ARGB_S10E5",
5953	"xSURFACEFMT_ARGB_S23E8",
5954	"xMISSING62",
5955	"xMAX_VERTEX_SHADER_TEXTURES",
5956	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
5957	"xSURFACEFMT_V16U16",
5958	"xSURFACEFMT_G16R16",
5959	"xSURFACEFMT_A16B16G16R16",
5960	"xSURFACEFMT_UYVY",
5961	"xSURFACEFMT_YUY2",
5962	"xMULTISAMPLE_NONMASKABLESAMPLES",
5963	"xMULTISAMPLE_MASKABLESAMPLES",
5964	"xALPHATOCOVERAGE",
5965	"xSUPERSAMPLE",
5966	"xAUTOGENMIPMAPS",
5967	"xSURFACEFMT_NV12",
5968	"xSURFACEFMT_AYUV",
5969	"xMAX_CONTEXT_IDS",
5970	"xMAX_SURFACE_IDS",
5971	"xSURFACEFMT_Z_DF16",
5972	"xSURFACEFMT_Z_DF24",
5973	"xSURFACEFMT_Z_D24S8_INT",
5974	"xSURFACEFMT_BC4_UNORM",
5975	"xSURFACEFMT_BC5_UNORM", /* 83 */
5976	};
5977
5978	/**
5979	* Initializes the host 3D capabilities in FIFO.
5980	*
5981	* @returns VBox status code.
5982	* @param pThis The VGA instance.
5983	*/
5984	static void vmsvgaInitFifo3DCaps(PVGASTATE pThis)
5985	{
5986	/** @todo Probably query the capabilities once and cache in a memory buffer. */
5987	bool fSavedBuffering = RTLogRelSetBuffering(true);
5988	SVGA3dCapsRecord *pCaps;
5989	SVGA3dCapPair *pData;
5990	uint32_t idxCap = 0;
5991
5992	/* 3d hardware version; latest and greatest */
5993	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5994	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5995
5996	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
5997	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5998	pData = (SVGA3dCapPair *)&pCaps->data;
5999
6000	/* Fill out all 3d capabilities. */
6001	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6002	{
6003	uint32_t val = 0;
6004
6005	int rc = vmsvga3dQueryCaps(pThis, i, &val);
6006	if (RT_SUCCESS(rc))
6007	{
6008	pData[idxCap][0] = i;
6009	pData[idxCap][1] = val;
6010	idxCap++;
6011	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6012	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6013	else
6014	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6015	&g_apszVmSvgaDevCapNames[i][1]));
6016	}
6017	else
6018	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6019	}
6020	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6021	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6022
6023	/* Mark end of record array. */
6024	pCaps->header.length = 0;
6025
6026	RTLogRelSetBuffering(fSavedBuffering);
6027	}
6028
6029	# endif
6030
6031	/**
6032	* Resets the SVGA hardware state
6033	*
6034	* @returns VBox status code.
6035	* @param pDevIns The device instance.
6036	*/
6037	int vmsvgaReset(PPDMDEVINS pDevIns)
6038	{
6039	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6040	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
6041
6042	/* Reset before init? */
6043	if (!pSVGAState)
6044	return VINF_SUCCESS;
6045
6046	Log(("vmsvgaReset\n"));
6047
6048	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6049	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6050	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6051
6052	/* Reset other stuff. */
6053	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6054	RT_ZERO(pThis->svga.au32ScratchRegion);
6055
6056	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
6057	vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6058
6059	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6060
6061	/* Initialize FIFO and register capabilities. */
6062	vmsvgaInitCaps(pThis);
6063
6064	# ifdef VBOX_WITH_VMSVGA3D
6065	if (pThis->svga.f3DEnabled)
6066	vmsvgaInitFifo3DCaps(pThis);
6067	# endif
6068
6069	/* VRAM tracking is enabled by default during bootup. */
6070	pThis->svga.fVRAMTracking = true;
6071	pThis->svga.fEnabled = false;
6072
6073	/* Invalidate current settings. */
6074	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6075	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6076	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6077	pThis->svga.cbScanline = 0;
6078	pThis->svga.u32PitchLock = 0;
6079
6080	return rc;
6081	}
6082
6083	/**
6084	* Cleans up the SVGA hardware state
6085	*
6086	* @returns VBox status code.
6087	* @param pDevIns The device instance.
6088	*/
6089	int vmsvgaDestruct(PPDMDEVINS pDevIns)
6090	{
6091	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6092
6093	/*
6094	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6095	*/
6096	if (pThis->svga.pFIFOIOThread)
6097	{
6098	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
6099	AssertLogRelRC(rc);
6100
6101	rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
6102	AssertLogRelRC(rc);
6103	pThis->svga.pFIFOIOThread = NULL;
6104	}
6105
6106	/*
6107	* Destroy the special SVGA state.
6108	*/
6109	if (pThis->svga.pSvgaR3State)
6110	{
6111	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
6112
6113	RTMemFree(pThis->svga.pSvgaR3State);
6114	pThis->svga.pSvgaR3State = NULL;
6115	}
6116
6117	/*
6118	* Free our resources residing in the VGA state.
6119	*/
6120	if (pThis->svga.pbVgaFrameBufferR3)
6121	{
6122	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
6123	pThis->svga.pbVgaFrameBufferR3 = NULL;
6124	}
6125	if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
6126	{
6127	RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
6128	pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
6129	}
6130	if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
6131	{
6132	SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
6133	pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
6134	}
6135
6136	return VINF_SUCCESS;
6137	}
6138
6139	/**
6140	* Initialize the SVGA hardware state
6141	*
6142	* @returns VBox status code.
6143	* @param pDevIns The device instance.
6144	*/
6145	int vmsvgaInit(PPDMDEVINS pDevIns)
6146	{
6147	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6148	PVMSVGAR3STATE pSVGAState;
6149	PVM pVM = PDMDevHlpGetVM(pDevIns);
6150	int rc;
6151
6152	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6153	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6154
6155	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6156
6157	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6158	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6159	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6160
6161	/* Create event semaphore. */
6162	pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
6163
6164	rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
6165	if (RT_FAILURE(rc))
6166	{
6167	Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
6168	return rc;
6169	}
6170
6171	/* Create event semaphore. */
6172	rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
6173	if (RT_FAILURE(rc))
6174	{
6175	Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
6176	return rc;
6177	}
6178
6179	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6180	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
6181
6182	rc = vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6183	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6184
6185	pSVGAState = pThis->svga.pSvgaR3State;
6186
6187	/* Initialize FIFO and register capabilities. */
6188	vmsvgaInitCaps(pThis);
6189
6190	# ifdef VBOX_WITH_VMSVGA3D
6191	if (pThis->svga.f3DEnabled)
6192	{
6193	rc = vmsvga3dInit(pThis);
6194	if (RT_FAILURE(rc))
6195	{
6196	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6197	pThis->svga.f3DEnabled = false;
6198	}
6199	}
6200	# endif
6201	/* VRAM tracking is enabled by default during bootup. */
6202	pThis->svga.fVRAMTracking = true;
6203
6204	/* Invalidate current settings. */
6205	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6206	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6207	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6208	pThis->svga.cbScanline = 0;
6209
6210	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6211	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6212	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6213	{
6214	pThis->svga.u32MaxWidth -= 256;
6215	pThis->svga.u32MaxHeight -= 256;
6216	}
6217	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6218
6219	# ifdef DEBUG_GMR_ACCESS
6220	/* Register the GMR access handler type. */
6221	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
6222	vmsvgaR3GMRAccessHandler,
6223	NULL, NULL, NULL,
6224	NULL, NULL, NULL,
6225	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6226	AssertRCReturn(rc, rc);
6227	# endif
6228
6229	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6230	/* Register the FIFO access handler type. In addition to
6231	debugging FIFO access, this is also used to facilitate
6232	extended fifo thread sleeps. */
6233	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
6234	# ifdef DEBUG_FIFO_ACCESS
6235	PGMPHYSHANDLERKIND_ALL,
6236	# else
6237	PGMPHYSHANDLERKIND_WRITE,
6238	# endif
6239	vmsvgaR3FIFOAccessHandler,
6240	NULL, NULL, NULL,
6241	NULL, NULL, NULL,
6242	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6243	AssertRCReturn(rc, rc);
6244	# endif
6245
6246	/* Create the async IO thread. */
6247	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
6248	RTTHREADTYPE_IO, "VMSVGA FIFO");
6249	if (RT_FAILURE(rc))
6250	{
6251	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6252	return rc;
6253	}
6254
6255	/*
6256	* Statistics.
6257	*/
6258	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dActivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dActivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_ACTIVATE_SURFACE");
6259	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dBeginQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dBeginQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_BEGIN_QUERY");
6260	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dClear, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dClear", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CLEAR");
6261	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DEFINE");
6262	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DESTROY");
6263	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDeactivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDeactivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6264	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitives, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDrawPrimitives", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DRAW_PRIMITIVES");
6265	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitivesProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dDrawPrimitivesProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6266	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dEndQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dEndQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_END_QUERY");
6267	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dGenerateMipmaps, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dGenerateMipmaps", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_GENERATE_MIPMAPS");
6268	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresent, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresent", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT");
6269	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresentReadBack, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresentReadBack", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT_READBACK");
6270	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dPresentProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dPresentProfBoth", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6271	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetClipPlane, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetClipPlane", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETCLIPPLANE");
6272	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightData, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightData", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTDATA");
6273	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightEnable, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightEnable", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTENABLE");
6274	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetMaterial, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetMaterial", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETMATERIAL");
6275	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERSTATE");
6276	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderTarget, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderTarget", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERTARGET");
6277	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetScissorRect, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetScissorRect", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETSCISSORRECT");
6278	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShader, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShader", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER");
6279	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShaderConst, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShaderConst", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER_CONST");
6280	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTextureState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTextureState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTEXTURESTATE");
6281	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTransform, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTransform", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTRANSFORM");
6282	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetViewPort, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetViewPort", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETVIEWPORT");
6283	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetZRange, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetZRange", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETZRANGE");
6284	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DEFINE");
6285	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DESTROY");
6286	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceCopy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_COPY");
6287	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE");
6288	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefineV2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefineV2", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6289	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DESTROY");
6290	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDma, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDma", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DMA");
6291	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDmaProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dSurfaceDmaProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6292	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceScreen", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_SCREEN");
6293	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceStretchBlt, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceStretchBlt", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6294	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dWaitForQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dWaitForQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_WAIT_FOR_QUERY");
6295	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationCopy", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_COPY");
6296	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationFill, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationFill", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_FILL");
6297	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitGmrFbToScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitGmrFbToScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6298	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitScreentoGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitScreentoGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6299	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineAlphaCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineAlphaCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6300	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_CURSOR");
6301	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMR2");
6302	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Free, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Free", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6303	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6304	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMRFB");
6305	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_SCREEN");
6306	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDestroyScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DestroyScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DESTROY_SCREEN");
6307	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdEscape, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Escape", STAMUNIT_OCCURENCES, "SVGA_CMD_ESCAPE");
6308	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdFence, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Fence", STAMUNIT_OCCURENCES, "SVGA_CMD_FENCE");
6309	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdInvalidCmd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/InvalidCmd", STAMUNIT_OCCURENCES, "SVGA_CMD_INVALID_CMD");
6310	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_REMAP_GMR2");
6311	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6312	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdate, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Update", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE");
6313	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdateVerbose, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/UpdateVerbose", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE_VERBOSE");
6314
6315	STAM_REL_REG(pVM, &pSVGAState->StatR3RegConfigDoneWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE writes");
6316	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_DESCRIPTOR writes");
6317	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Errors", STAMUNIT_OCCURENCES, "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6318	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrFree, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Free", STAMUNIT_OCCURENCES, "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6319	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL writes.");
6320	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY writes.");
6321	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX writes.");
6322	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH writes.");
6323	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT writes.");
6324	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID writes.");
6325	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6326	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X writes.");
6327	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y writes.");
6328	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH writes.");
6329	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE writes.");
6330	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID writes.");
6331	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID writes.");
6332	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT writes.");
6333	STAM_REL_REG(pVM, &pThis->svga.StatRegIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ID writes.");
6334	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskWrite", STAMUNIT_OCCURENCES, "SVGA_REG_IRQMASK writes.");
6335	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS writes.");
6336	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6337	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteWrite", STAMUNIT_OCCURENCES, "SVGA_PALETTE_XXXX writes.");
6338	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK writes.");
6339	STAM_REL_REG(pVM, &pThis->svga.StatRegPseudoColorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PseudoColorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR writes.");
6340	STAM_REL_REG(pVM, &pThis->svga.StatRegReadOnlyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ReadOnlyWrite", STAMUNIT_OCCURENCES, "Read-only SVGA_REG_XXXX writes.");
6341	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_XXXX writes.");
6342	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC writes.");
6343	STAM_REL_REG(pVM, &pThis->svga.StatRegTopWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TOP writes.");
6344	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES writes.");
6345	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownWrite", STAMUNIT_OCCURENCES, "Writes to unknown register.");
6346	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH writes.");
6347
6348	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL reads.");
6349	STAM_REL_REG(pVM, &pThis->svga.StatRegBlueMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BlueMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_BLUE_MASK reads.");
6350	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyRead", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY reads.");
6351	STAM_REL_REG(pVM, &pThis->svga.StatRegBytesPerLineRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BytesPerLineRead", STAMUNIT_OCCURENCES, "SVGA_REG_BYTES_PER_LINE reads.");
6352	STAM_REL_REG(pVM, &pThis->svga.StatRegCapabilitesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CapabilitesRead", STAMUNIT_OCCURENCES, "SVGA_REG_CAPABILITIES reads.");
6353	STAM_REL_REG(pVM, &pThis->svga.StatRegConfigDoneRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneRead", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE reads.");
6354	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxRead", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX reads.");
6355	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH reads.");
6356	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT reads.");
6357	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID reads.");
6358	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6359	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X reads.");
6360	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y reads.");
6361	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH reads.");
6362	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableRead", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE reads.");
6363	STAM_REL_REG(pVM, &pThis->svga.StatRegFbOffsetRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbOffsetRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_OFFSET reads.");
6364	STAM_REL_REG(pVM, &pThis->svga.StatRegFbSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_SIZE reads.");
6365	STAM_REL_REG(pVM, &pThis->svga.StatRegFbStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_START reads.");
6366	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID reads.");
6367	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxDescriptorLengthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxDescriptorLengthRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6368	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxIdsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxIdsRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_IDS reads.");
6369	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrsMaxPagesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrsMaxPagesRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMRS_MAX_PAGES reads.");
6370	STAM_REL_REG(pVM, &pThis->svga.StatRegGreenMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GreenMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_GREEN_MASK reads.");
6371	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID reads.");
6372	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT reads.");
6373	STAM_REL_REG(pVM, &pThis->svga.StatRegHostBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HostBitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6374	STAM_REL_REG(pVM, &pThis->svga.StatRegIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdRead", STAMUNIT_OCCURENCES, "SVGA_REG_ID reads.");
6375	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_IRQ_MASK reads.");
6376	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_HEIGHT reads.");
6377	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_WIDTH reads.");
6378	STAM_REL_REG(pVM, &pThis->svga.StatRegMemorySizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemorySizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEMORY_SIZE reads.");
6379	STAM_REL_REG(pVM, &pThis->svga.StatRegMemRegsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemRegsRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_REGS reads.");
6380	STAM_REL_REG(pVM, &pThis->svga.StatRegMemSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_SIZE reads.");
6381	STAM_REL_REG(pVM, &pThis->svga.StatRegMemStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_START reads.");
6382	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS reads.");
6383	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6384	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteRead", STAMUNIT_OCCURENCES, "SVGA_REG_PLAETTE_XXXX reads.");
6385	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockRead", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK reads.");
6386	STAM_REL_REG(pVM, &pThis->svga.StatRegPsuedoColorRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PsuedoColorRead", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR reads.");
6387	STAM_REL_REG(pVM, &pThis->svga.StatRegRedMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/RedMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_RED_MASK reads.");
6388	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH reads.");
6389	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_SIZE reads.");
6390	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncRead", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC reads.");
6391	STAM_REL_REG(pVM, &pThis->svga.StatRegTopRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopRead", STAMUNIT_OCCURENCES, "SVGA_REG_TOP reads.");
6392	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesRead", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES reads.");
6393	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownRead", STAMUNIT_OCCURENCES, "SVGA_REG_UNKNOWN reads.");
6394	STAM_REL_REG(pVM, &pThis->svga.StatRegVramSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/VramSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_VRAM_SIZE reads.");
6395	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH reads.");
6396	STAM_REL_REG(pVM, &pThis->svga.StatRegWriteOnlyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WriteOnlyRead", STAMUNIT_OCCURENCES, "Write-only SVGA_REG_XXXX reads.");
6397
6398	STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
6399	STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
6400	STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
6401	STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
6402	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
6403	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
6404	STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6405	STAM_REL_REG(pVM, &pSVGAState->StatFifoExtendedSleep, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoExtendedSleep", STAMUNIT_TICKS_PER_CALL, "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6406	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6407	STAM_REL_REG(pVM, &pSVGAState->StatFifoAccessHandler, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoAccessHandler", STAMUNIT_OCCURENCES, "Number of times the FIFO access handler triggered.");
6408	# endif
6409	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorFetchAgain, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorFetchAgain", STAMUNIT_OCCURENCES, "Times the cursor update counter changed while reading.");
6410	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorNoChange, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorNoChange", STAMUNIT_OCCURENCES, "No cursor position change event though the update counter was modified.");
6411	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorPosition, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorPosition", STAMUNIT_OCCURENCES, "Cursor position and visibility changes.");
6412	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorVisiblity, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorVisiblity", STAMUNIT_OCCURENCES, "Cursor visibility changes.");
6413	STAM_REL_REG(pVM, &pSVGAState->StatFifoWatchdogWakeUps, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoWatchdogWakeUps", STAMUNIT_OCCURENCES, "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6414
6415	/*
6416	* Info handlers.
6417	*/
6418	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6419	# ifdef VBOX_WITH_VMSVGA3D
6420	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6421	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6422	"VMSVGA 3d surface details. "
6423	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6424	vmsvgaR3Info3dSurface);
6425	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6426	"VMSVGA 3d surface details and bitmap: "
6427	"sid[>dir]",
6428	vmsvgaR3Info3dSurfaceBmp);
6429	# endif
6430
6431	return VINF_SUCCESS;
6432	}
6433
6434	/**
6435	* Power On notification.
6436	*
6437	* @returns VBox status code.
6438	* @param pDevIns The device instance data.
6439	*
6440	* @remarks Caller enters the device critical section.
6441	*/
6442	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6443	{
6444	# ifdef VBOX_WITH_VMSVGA3D
6445	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6446	if (pThis->svga.f3DEnabled)
6447	{
6448	int rc = vmsvga3dPowerOn(pThis);
6449
6450	if (RT_SUCCESS(rc))
6451	{
6452	/* Initialize FIFO 3D capabilities. */
6453	vmsvgaInitFifo3DCaps(pThis);
6454	}
6455	}
6456	# else /* !VBOX_WITH_VMSVGA3D */
6457	RT_NOREF(pDevIns);
6458	# endif /* !VBOX_WITH_VMSVGA3D */
6459	}
6460
6461	#endif /* IN_RING3 */
6462

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 80651

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