DevVGA-SVGA-cmd.cpp@ 98049

Last change on this file since 98049 was 98049, checked in by vboxsync, 22 months ago
Devices/Graphics: logging. bugref:9830
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 272.3 KB

Line
1	/* $Id: DevVGA-SVGA-cmd.cpp 98049 2023-01-11 05:40:22Z vboxsync $ */
2	/** @file
3	* VMware SVGA device - implementation of VMSVGA commands.
4	*/
5
6	/*
7	* Copyright (C) 2013-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef IN_RING3
29	# error "DevVGA-SVGA-cmd.cpp is only for ring-3 code"
30	#endif
31
32
33	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
34	#include <iprt/mem.h>
35	#include <VBox/AssertGuest.h>
36	#include <VBox/log.h>
37	#include <VBox/vmm/pdmdev.h>
38	#include <VBoxVideo.h>
39
40	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
41	#include "DevVGA.h"
42
43	/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
44	#ifdef VBOX_WITH_VMSVGA3D
45	# include "DevVGA-SVGA3d.h"
46	#endif
47	#include "DevVGA-SVGA-internal.h"
48
49	#include <iprt/formats/bmp.h>
50	#include <stdio.h>
51
52	#if defined(LOG_ENABLED) \|\| defined(VBOX_STRICT)
53	# define SVGA_CASE_ID2STR(idx) case idx: return #idx
54
55	static const char *vmsvgaFifo3dCmdToString(SVGAFifo3dCmdId enmCmdId)
56	{
57	switch (enmCmdId)
58	{
59	SVGA_CASE_ID2STR(SVGA_3D_CMD_LEGACY_BASE);
60	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
61	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
62	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
63	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
64	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
65	SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
66	SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
67	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
68	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
69	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
70	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
71	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
72	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
73	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
74	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
75	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
76	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
77	SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
78	SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
79	SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
80	SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
81	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
82	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
83	SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
84	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
85	SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
86	SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
87	SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
88	SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
89	SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
90	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
91	SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
92	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD4); /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
93	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD5); /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
94	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD6); /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
95	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD7); /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
96	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD8); /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
97	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD9); /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
98	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD10); /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
99	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD11); /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
100	SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
101	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
102	SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
103	SVGA_CASE_ID2STR(SVGA_3D_CMD_VB_DX_CLEAR_RENDERTARGET_VIEW_REGION); /* SVGA_3D_CMD_DEAD1 */
104	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
105	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD12); /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
106	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD13); /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
107	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD14); /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
108	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD15); /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
109	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD16); /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
110	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD17); /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
111	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
112	SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
113	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
114	SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
115	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
116	SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
117	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
118	SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
119	SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
120	SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
121	SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
122	SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
123	SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
124	SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
125	SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
126	SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
127	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
128	SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
129	SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
130	SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
131	SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
132	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
133	SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
134	SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
135	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
136	SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
137	SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
138	SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
139	SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
140	SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
141	SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
142	SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
143	SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
144	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
145	SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
146	SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
147	SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
148	SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
149	SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
150	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
151	SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
152	SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
153	SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
154	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
155	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
156	SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
157	SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
158	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
159	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
160	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
161	SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
162	SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
163	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
164	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
165	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
166	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
167	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
168	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
169	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
170	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
171	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
172	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
173	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
174	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
175	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
176	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
177	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
178	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
179	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
180	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
181	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
182	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
183	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
184	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
185	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
186	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
187	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
188	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
189	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
190	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
191	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
192	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
193	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
194	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
195	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
196	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
197	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
198	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
199	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
200	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRESENTBLT);
201	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
202	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
203	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
204	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
205	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
206	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
207	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
208	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
209	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
210	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
211	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
212	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
213	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
214	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
215	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
216	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
217	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
218	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
219	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
220	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
221	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
222	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
223	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
224	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
225	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
226	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
227	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
228	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
229	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
230	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
231	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
232	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
233	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
234	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
235	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
236	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
237	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
238	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
239	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
240	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
241	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
242	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
243	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET);
244	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET);
245	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET);
246	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
247	SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_COPY);
248	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED1);
249	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2);
250	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED3);
251	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED4);
252	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED5);
253	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED6);
254	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED7);
255	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED8);
256	SVGA_CASE_ID2STR(SVGA_3D_CMD_GROW_OTABLE);
257	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GROW_COTABLE);
258	SVGA_CASE_ID2STR(SVGA_3D_CMD_INTRA_SURFACE_COPY);
259	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V3);
260	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESOLVE_COPY);
261	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_RESOLVE_COPY);
262	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT_REGION);
263	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT);
264	SVGA_CASE_ID2STR(SVGA_3D_CMD_WHOLE_SURFACE_COPY);
265	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_UA_VIEW);
266	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_UA_VIEW);
267	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT);
268	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT);
269	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT);
270	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_UA_VIEWS);
271	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT);
272	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT);
273	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH);
274	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH_INDIRECT);
275	SVGA_CASE_ID2STR(SVGA_3D_CMD_WRITE_ZERO_SURFACE);
276	SVGA_CASE_ID2STR(SVGA_3D_CMD_HINT_ZERO_SURFACE);
277	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER);
278	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT);
279	SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
280	SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
281	SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
282	SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
283	SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
284	SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
285	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_1);
286	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_2);
287	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4);
288	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS);
289	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_MIN_LOD);
290	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_3);
291	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_4);
292	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2);
293	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB);
294	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_IFACE);
295	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT);
296	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS);
297	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER_IFACE);
298	SVGA_CASE_ID2STR(SVGA_3D_CMD_MAX);
299	SVGA_CASE_ID2STR(SVGA_3D_CMD_FUTURE_MAX);
300	}
301	return "UNKNOWN_3D";
302	}
303
304	/**
305	* FIFO command name lookup
306	*
307	* @returns FIFO command string or "UNKNOWN"
308	* @param u32Cmd FIFO command
309	*/
310	const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
311	{
312	switch (u32Cmd)
313	{
314	SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
315	SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
316	SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
317	SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
318	SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
319	SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
320	SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
321	SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
322	SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
323	SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
324	SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
325	SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
326	SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
327	SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
328	SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
329	SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
330	SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
331	SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
332	SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
333	SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
334	SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
335	SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
336	SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
337	SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
338	SVGA_CASE_ID2STR(SVGA_CMD_NOP);
339	SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
340	SVGA_CASE_ID2STR(SVGA_CMD_MAX);
341	default:
342	if ( u32Cmd >= SVGA_3D_CMD_BASE
343	&& u32Cmd < SVGA_3D_CMD_MAX)
344	return vmsvgaFifo3dCmdToString((SVGAFifo3dCmdId)u32Cmd);
345	}
346	return "UNKNOWN";
347	}
348	# undef SVGA_CASE_ID2STR
349	#endif /* LOG_ENABLED \|\| VBOX_STRICT */
350
351
352	/*
353	*
354	* Guest-Backed Objects (GBO).
355	*
356	*/
357
358	#ifdef VBOX_WITH_VMSVGA3D
359
360	static int vmsvgaR3GboCreate(PVMSVGAR3STATE pSvgaR3State, SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, PVMSVGAGBO pGbo)
361	{
362	ASSERT_GUEST_RETURN(sizeInBytes <= _128M, VERR_INVALID_PARAMETER); /** @todo Less than SVGA_REG_MOB_MAX_SIZE */
363
364	/*
365	* The 'baseAddress' is a page number and points to the 'root page' of the GBO.
366	* Content of the root page depends on the ptDepth value:
367	* SVGA3D_MOBFMT_PTDEPTH[64]_0 - the only data page;
368	* SVGA3D_MOBFMT_PTDEPTH[64]_1 - array of page numbers for data pages;
369	* SVGA3D_MOBFMT_PTDEPTH[64]_2 - array of page numbers for SVGA3D_MOBFMT_PTDEPTH[64]_1 pages.
370	* The code below extracts the page addresses of the GBO.
371	*/
372
373	/* Verify and normalize the ptDepth value. */
374	bool fGCPhys64; /* Whether the page table contains 64 bit page numbers. */
375	if (RT_LIKELY( ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0
376	\|\| ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1
377	\|\| ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2))
378	fGCPhys64 = true;
379	else if ( ptDepth == SVGA3D_MOBFMT_PTDEPTH_0
380	\|\| ptDepth == SVGA3D_MOBFMT_PTDEPTH_1
381	\|\| ptDepth == SVGA3D_MOBFMT_PTDEPTH_2)
382	{
383	fGCPhys64 = false;
384	/* Shift ptDepth to the SVGA3D_MOBFMT_PTDEPTH64_x range. */
385	ptDepth = (SVGAMobFormat)(ptDepth + SVGA3D_MOBFMT_PTDEPTH64_0 - SVGA3D_MOBFMT_PTDEPTH_0);
386	}
387	else if (ptDepth == SVGA3D_MOBFMT_RANGE)
388	fGCPhys64 = false; /* Does not matter, there is no page table. */
389	else
390	ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
391
392	uint32_t const cPPNsPerPage = X86_PAGE_SIZE / (fGCPhys64 ? sizeof(PPN64) : sizeof(PPN));
393
394	pGbo->cbTotal = sizeInBytes;
395	pGbo->cTotalPages = (sizeInBytes + X86_PAGE_SIZE - 1) >> X86_PAGE_SHIFT;
396
397	/* Allocate the maximum amount possible (everything non-continuous) */
398	PVMSVGAGBODESCRIPTOR paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAlloc(pGbo->cTotalPages * sizeof(VMSVGAGBODESCRIPTOR));
399	AssertReturn(paDescriptors, VERR_NO_MEMORY);
400
401	int rc = VINF_SUCCESS;
402	if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0)
403	{
404	ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages == 1,
405	RTMemFree(paDescriptors),
406	VERR_INVALID_PARAMETER);
407
408	RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
409	GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
410	paDescriptors[0].GCPhys = GCPhys;
411	paDescriptors[0].cPages = 1;
412	}
413	else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1)
414	{
415	ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage,
416	RTMemFree(paDescriptors),
417	VERR_INVALID_PARAMETER);
418
419	/* Read the root page. */
420	uint8_t au8RootPage[X86_PAGE_SIZE];
421	RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
422	rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPage, sizeof(au8RootPage));
423	if (RT_SUCCESS(rc))
424	{
425	PPN64 paPPN64 = (PPN64 )&au8RootPage[0];
426	PPN paPPN32 = (PPN )&au8RootPage[0];
427	for (uint32_t iPPN = 0; iPPN < pGbo->cTotalPages; ++iPPN)
428	{
429	GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
430	GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
431	paDescriptors[iPPN].GCPhys = GCPhys;
432	paDescriptors[iPPN].cPages = 1;
433	}
434	}
435	}
436	else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2)
437	{
438	ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage * cPPNsPerPage,
439	RTMemFree(paDescriptors),
440	VERR_INVALID_PARAMETER);
441
442	/* Read the Level2 root page. */
443	uint8_t au8RootPageLevel2[X86_PAGE_SIZE];
444	RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
445	rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPageLevel2, sizeof(au8RootPageLevel2));
446	if (RT_SUCCESS(rc))
447	{
448	uint32_t cPagesLeft = pGbo->cTotalPages;
449
450	PPN64 paPPN64Level2 = (PPN64 )&au8RootPageLevel2[0];
451	PPN paPPN32Level2 = (PPN )&au8RootPageLevel2[0];
452
453	uint32_t const cPPNsLevel2 = (pGbo->cTotalPages + cPPNsPerPage - 1) / cPPNsPerPage;
454	for (uint32_t iPPNLevel2 = 0; iPPNLevel2 < cPPNsLevel2; ++iPPNLevel2)
455	{
456	/* Read the Level1 root page. */
457	uint8_t au8RootPage[X86_PAGE_SIZE];
458	RTGCPHYS GCPhysLevel1 = (RTGCPHYS)(fGCPhys64 ? paPPN64Level2[iPPNLevel2] : paPPN32Level2[iPPNLevel2]) << X86_PAGE_SHIFT;
459	GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
460	rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhysLevel1, &au8RootPage, sizeof(au8RootPage));
461	if (RT_SUCCESS(rc))
462	{
463	PPN64 paPPN64 = (PPN64 )&au8RootPage[0];
464	PPN paPPN32 = (PPN )&au8RootPage[0];
465
466	uint32_t const cPPNs = RT_MIN(cPagesLeft, cPPNsPerPage);
467	for (uint32_t iPPN = 0; iPPN < cPPNs; ++iPPN)
468	{
469	GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
470	GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
471	paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].GCPhys = GCPhys;
472	paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].cPages = 1;
473	}
474	cPagesLeft -= cPPNs;
475	}
476	}
477	}
478	}
479	else if (ptDepth == SVGA3D_MOBFMT_RANGE)
480	{
481	RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
482	GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
483	paDescriptors[0].GCPhys = GCPhys;
484	paDescriptors[0].cPages = pGbo->cTotalPages;
485	}
486	else
487	{
488	AssertFailed();
489	return VERR_INTERNAL_ERROR; /* ptDepth should be already verified. */
490	}
491
492	/* Compress the descriptors. */
493	if (ptDepth != SVGA3D_MOBFMT_RANGE)
494	{
495	uint32_t iDescriptor = 0;
496	for (uint32_t i = 1; i < pGbo->cTotalPages; ++i)
497	{
498	/* Continuous physical memory? */
499	if (paDescriptors[i].GCPhys == paDescriptors[iDescriptor].GCPhys + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
500	{
501	Assert(paDescriptors[iDescriptor].cPages);
502	paDescriptors[iDescriptor].cPages++;
503	Log5Func(("Page %x GCPhys=%RGp successor\n", i, paDescriptors[i].GCPhys));
504	}
505	else
506	{
507	iDescriptor++;
508	paDescriptors[iDescriptor].GCPhys = paDescriptors[i].GCPhys;
509	paDescriptors[iDescriptor].cPages = 1;
510	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescriptors[iDescriptor].GCPhys));
511	}
512	}
513
514	pGbo->cDescriptors = iDescriptor + 1;
515	Log5Func(("Nr of descriptors %d\n", pGbo->cDescriptors));
516	}
517	else
518	pGbo->cDescriptors = 1;
519
520	if (RT_LIKELY(pGbo->cDescriptors < pGbo->cTotalPages))
521	{
522	pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemRealloc(paDescriptors, pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
523	AssertReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
524	}
525	else
526	pGbo->paDescriptors = paDescriptors;
527
528	pGbo->fGboFlags = 0;
529	pGbo->pvHost = NULL;
530
531	return VINF_SUCCESS;
532	}
533
534
535	static void vmsvgaR3GboDestroy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
536	{
537	RT_NOREF(pSvgaR3State);
538
539	if (RT_LIKELY(VMSVGA_IS_GBO_CREATED(pGbo)))
540	{
541	RTMemFree(pGbo->paDescriptors);
542	RT_ZERO(*pGbo);
543	}
544	}
545
546	/** @todo static void vmsvgaR3GboWriteProtect(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, bool fWriteProtect) */
547
548	typedef enum VMSVGAGboTransferDirection
549	{
550	VMSVGAGboTransferDirection_Read,
551	VMSVGAGboTransferDirection_Write,
552	} VMSVGAGboTransferDirection;
553
554	static int vmsvgaR3GboTransfer(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
555	uint32_t off, void *pvData, uint32_t cbData,
556	VMSVGAGboTransferDirection enmDirection)
557	{
558	//DEBUG_BREAKPOINT_TEST();
559	int rc = VINF_SUCCESS;
560	uint8_t pu8CurrentHost = (uint8_t )pvData;
561
562	/* Find the right descriptor */
563	PCVMSVGAGBODESCRIPTOR const paDescriptors = pGbo->paDescriptors;
564	uint32_t iDescriptor = 0; /* Index in the descriptor array. */
565	uint32_t offDescriptor = 0; /* GMR offset of the current descriptor. */
566	while (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE <= off)
567	{
568	offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
569	AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
570	++iDescriptor;
571	AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
572	}
573
574	while (cbData)
575	{
576	uint32_t cbToCopy;
577	if (off + cbData <= offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
578	cbToCopy = cbData;
579	else
580	{
581	cbToCopy = (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE - off);
582	AssertReturn(cbToCopy <= cbData, VERR_INVALID_PARAMETER);
583	}
584
585	RTGCPHYS const GCPhys = paDescriptors[iDescriptor].GCPhys + off - offDescriptor;
586	Log5Func(("%s phys=%RGp\n", (enmDirection == VMSVGAGboTransferDirection_Read) ? "READ" : "WRITE", GCPhys));
587
588	/*
589	* We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read\|Write] as the
590	* guest-side VMSVGA driver seems to allocate non-DMA (regular physical) addresses,
591	* see @bugref{9654#c75}.
592	*/
593	if (enmDirection == VMSVGAGboTransferDirection_Read)
594	rc = PDMDevHlpPhysRead(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
595	else
596	rc = PDMDevHlpPhysWrite(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
597	AssertRCBreak(rc);
598
599	cbData -= cbToCopy;
600	off += cbToCopy;
601	pu8CurrentHost += cbToCopy;
602
603	/* Go to the next descriptor if there's anything left. */
604	if (cbData)
605	{
606	offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
607	AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR);
608	++iDescriptor;
609	AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
610	}
611	}
612	return rc;
613	}
614
615
616	static int vmsvgaR3GboWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
617	uint32_t off, void const *pvData, uint32_t cbData)
618	{
619	return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
620	off, (void *)pvData, cbData,
621	VMSVGAGboTransferDirection_Write);
622	}
623
624
625	static int vmsvgaR3GboRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
626	uint32_t off, void *pvData, uint32_t cbData)
627	{
628	return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
629	off, pvData, cbData,
630	VMSVGAGboTransferDirection_Read);
631	}
632
633
634	static int vmsvgaR3GboBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, uint32_t cbValid)
635	{
636	int rc;
637
638	/* Just reread the data if pvHost has been allocated already. */
639	if (!(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED))
640	pGbo->pvHost = RTMemAllocZ(pGbo->cbTotal);
641
642	if (pGbo->pvHost)
643	{
644	cbValid = RT_MIN(cbValid, pGbo->cbTotal);
645	rc = vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, cbValid);
646	}
647	else
648	rc = VERR_NO_MEMORY;
649
650	if (RT_SUCCESS(rc))
651	pGbo->fGboFlags \|= VMSVGAGBO_F_HOST_BACKED;
652	else
653	{
654	RTMemFree(pGbo->pvHost);
655	pGbo->pvHost = NULL;
656	}
657	return rc;
658	}
659
660
661	static void vmsvgaR3GboBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
662	{
663	RT_NOREF(pSvgaR3State);
664	AssertReturnVoid(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED);
665	RTMemFree(pGbo->pvHost);
666	pGbo->pvHost = NULL;
667	pGbo->fGboFlags &= ~VMSVGAGBO_F_HOST_BACKED;
668	}
669
670
671	static int vmsvgaR3GboBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
672	{
673	AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
674	return vmsvgaR3GboWrite(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
675	}
676
677
678	static int vmsvgaR3GboBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
679	{
680	AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
681	return vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
682	}
683
684	static int vmsvgaR3GboCopy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboDst, uint32_t offDst,
685	PVMSVGAGBO pGboSrc, uint32_t offSrc, uint32_t cbCopy)
686	{
687	uint32_t const cbTmpBuf = GUEST_PAGE_SIZE;
688	void *pvTmpBuf = RTMemTmpAlloc(cbTmpBuf);
689	AssertPtrReturn(pvTmpBuf, VERR_NO_MEMORY);
690
691	int rc = VINF_SUCCESS;
692	while (cbCopy > 0)
693	{
694	uint32_t const cbToCopy = RT_MIN(cbTmpBuf, cbCopy);
695
696	rc = vmsvgaR3GboRead(pSvgaR3State, pGboSrc, offSrc, pvTmpBuf, cbToCopy);
697	AssertRCBreak(rc);
698
699	rc = vmsvgaR3GboWrite(pSvgaR3State, pGboDst, offDst, pvTmpBuf, cbToCopy);
700	AssertRCBreak(rc);
701
702	offSrc += cbToCopy;
703	offDst += cbToCopy;
704	cbCopy -= cbToCopy;
705	}
706
707	RTMemTmpFree(pvTmpBuf);
708	return rc;
709	}
710
711
712	/*
713	*
714	* Object Tables.
715	*
716	*/
717
718	static int vmsvgaR3OTableSetOrGrow(PVMSVGAR3STATE pSvgaR3State, SVGAOTableType type, PPN64 baseAddress,
719	uint32_t sizeInBytes, uint32 validSizeInBytes, SVGAMobFormat ptDepth, bool fGrow)
720	{
721	ASSERT_GUEST_RETURN(type <= RT_ELEMENTS(pSvgaR3State->aGboOTables), VERR_INVALID_PARAMETER);
722	ASSERT_GUEST_RETURN(sizeInBytes >= validSizeInBytes, VERR_INVALID_PARAMETER);
723	RT_UNTRUSTED_VALIDATED_FENCE();
724
725	ASSERT_GUEST_RETURN(pSvgaR3State->aGboOTables[type].cbTotal >= validSizeInBytes, VERR_INVALID_PARAMETER);
726
727	if (sizeInBytes > 0)
728	{
729	/* Create a new guest backed object for the object table. */
730	VMSVGAGBO gbo;
731	int rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, &gbo);
732	AssertRCReturn(rc, rc);
733
734	/* If the guest sets a new OTable (fGrow == false), then it has already copied the valid data to the new GBO. */
735	if (fGrow && validSizeInBytes)
736	{
737	/* Copy data from old gbo to the new one. */
738	rc = vmsvgaR3GboCopy(pSvgaR3State, &gbo, 0, &pSvgaR3State->aGboOTables[type], 0, validSizeInBytes);
739	AssertRCReturnStmt(rc, vmsvgaR3GboDestroy(pSvgaR3State, &gbo), rc);
740	}
741
742	vmsvgaR3GboDestroy(pSvgaR3State, &pSvgaR3State->aGboOTables[type]);
743	pSvgaR3State->aGboOTables[type] = gbo;
744
745	}
746	else
747	vmsvgaR3GboDestroy(pSvgaR3State, &pSvgaR3State->aGboOTables[type]);
748
749	return VINF_SUCCESS;
750	}
751
752
753	static int vmsvgaR3OTableVerifyIndex(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
754	uint32_t idx, uint32_t cbEntry)
755	{
756	RT_NOREF(pSvgaR3State);
757
758	/* The table must exist and the index must be within the table. */
759	ASSERT_GUEST_RETURN(VMSVGA_IS_GBO_CREATED(pGboOTable), VERR_INVALID_PARAMETER);
760	ASSERT_GUEST_RETURN(idx < pGboOTable->cbTotal / cbEntry, VERR_INVALID_PARAMETER);
761	RT_UNTRUSTED_VALIDATED_FENCE();
762	return VINF_SUCCESS;
763	}
764
765
766	static int vmsvgaR3OTableRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
767	uint32_t idx, uint32_t cbEntry,
768	void *pvData, uint32_t cbData)
769	{
770	AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
771
772	int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
773	if (RT_SUCCESS(rc))
774	{
775	uint32_t const off = idx * cbEntry;
776	rc = vmsvgaR3GboRead(pSvgaR3State, pGboOTable, off, pvData, cbData);
777	}
778	return rc;
779	}
780
781	static int vmsvgaR3OTableWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
782	uint32_t idx, uint32_t cbEntry,
783	void const *pvData, uint32_t cbData)
784	{
785	AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
786
787	int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
788	if (RT_SUCCESS(rc))
789	{
790	uint32_t const off = idx * cbEntry;
791	rc = vmsvgaR3GboWrite(pSvgaR3State, pGboOTable, off, pvData, cbData);
792	}
793	return rc;
794	}
795
796
797	int vmsvgaR3OTableReadSurface(PVMSVGAR3STATE pSvgaR3State, uint32_t sid, SVGAOTableSurfaceEntry *pEntrySurface)
798	{
799	return vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
800	sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, pEntrySurface, sizeof(SVGAOTableSurfaceEntry));
801	}
802
803
804	/*
805	*
806	* The guest's Memory OBjects (MOB).
807	*
808	*/
809
810	static int vmsvgaR3MobCreate(PVMSVGAR3STATE pSvgaR3State,
811	SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, SVGAMobId mobid,
812	PVMSVGAMOB pMob)
813	{
814	RT_ZERO(*pMob);
815
816	/* Update the entry in the pSvgaR3State->pGboOTableMob. */
817	SVGAOTableMobEntry entry;
818	entry.ptDepth = ptDepth;
819	entry.sizeInBytes = sizeInBytes;
820	entry.base = baseAddress;
821	int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
822	mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
823	if (RT_SUCCESS(rc))
824	{
825	/* Create the corresponding GBO. */
826	rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, &pMob->Gbo);
827	if (RT_SUCCESS(rc))
828	{
829	/* If a mob with this id already exists, then delete it. */
830	PVMSVGAMOB pOldMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
831	if (pOldMob)
832	{
833	/* This should not happen. */
834	ASSERT_GUEST_FAILED();
835	RTListNodeRemove(&pOldMob->nodeLRU);
836	vmsvgaR3GboDestroy(pSvgaR3State, &pOldMob->Gbo);
837	RTMemFree(pOldMob);
838	}
839
840	/* Add to the tree of known MOBs and the LRU list. */
841	pMob->Core.Key = mobid;
842	if (RTAvlU32Insert(&pSvgaR3State->MOBTree, &pMob->Core))
843	{
844	RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
845	return VINF_SUCCESS;
846	}
847
848	AssertFailedStmt(rc = VERR_INVALID_STATE);
849	vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
850	}
851	}
852
853	return rc;
854	}
855
856
857	static int vmsvgaR3MobDestroy(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
858	{
859	/* Update the entry in the pSvgaR3State->pGboOTableMob. */
860	SVGAOTableMobEntry entry;
861	RT_ZERO(entry);
862	vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
863	mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
864
865	PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
866	if (pMob)
867	{
868	RTListNodeRemove(&pMob->nodeLRU);
869	vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
870	RTMemFree(pMob);
871	return VINF_SUCCESS;
872	}
873
874	return VERR_INVALID_PARAMETER;
875	}
876
877
878	PVMSVGAMOB vmsvgaR3MobGet(PVMSVGAR3STATE pSvgaR3State, SVGAMobId RT_UNTRUSTED_GUEST mobid)
879	{
880	if (mobid == SVGA_ID_INVALID)
881	return NULL;
882
883	PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Get(&pSvgaR3State->MOBTree, mobid);
884	if (pMob)
885	{
886	/* Move to the head of the LRU list. */
887	RTListNodeRemove(&pMob->nodeLRU);
888	RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
889	}
890	else
891	ASSERT_GUEST_FAILED();
892
893	return pMob;
894	}
895
896
897	int vmsvgaR3MobWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob,
898	uint32_t off, void const *pvData, uint32_t cbData)
899	{
900	return vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, off, pvData, cbData);
901	}
902
903
904	int vmsvgaR3MobRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob,
905	uint32_t off, void *pvData, uint32_t cbData)
906	{
907	return vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, off, pvData, cbData);
908	}
909
910
911	/** Create a host ring-3 pointer to the MOB data.
912	* Current approach is to allocate a host memory buffer and copy the guest MOB data if necessary.
913	* @param pSvgaR3State R3 device state.
914	* @param pMob The MOB.
915	* @param cbValid How many bytes of the guest backing memory contain valid data.
916	* @return VBox status.
917	*/
918	/** @todo uint32_t cbValid -> uint32_t offStart, uint32_t cbData */
919	int vmsvgaR3MobBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob, uint32_t cbValid)
920	{
921	AssertReturn(pMob, VERR_INVALID_PARAMETER);
922	return vmsvgaR3GboBackingStoreCreate(pSvgaR3State, &pMob->Gbo, cbValid);
923	}
924
925
926	void vmsvgaR3MobBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
927	{
928	if (pMob)
929	vmsvgaR3GboBackingStoreDelete(pSvgaR3State, &pMob->Gbo);
930	}
931
932
933	int vmsvgaR3MobBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
934	{
935	if (pMob)
936	return vmsvgaR3GboBackingStoreWriteToGuest(pSvgaR3State, &pMob->Gbo);
937	return VERR_INVALID_PARAMETER;
938	}
939
940
941	int vmsvgaR3MobBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
942	{
943	if (pMob)
944	return vmsvgaR3GboBackingStoreReadFromGuest(pSvgaR3State, &pMob->Gbo);
945	return VERR_INVALID_PARAMETER;
946	}
947
948
949	void *vmsvgaR3MobBackingStorePtr(PVMSVGAMOB pMob, uint32_t off)
950	{
951	if (pMob && (pMob->Gbo.fGboFlags & VMSVGAGBO_F_HOST_BACKED))
952	{
953	if (off <= pMob->Gbo.cbTotal)
954	return (uint8_t *)pMob->Gbo.pvHost + off;
955	}
956	return NULL;
957	}
958
959	#endif /* VBOX_WITH_VMSVGA3D */
960
961	/*
962	* Screen objects.
963	*/
964	VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
965	{
966	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
967	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
968	&& pSVGAState
969	&& pSVGAState->aScreens[idScreen].fDefined)
970	{
971	return &pSVGAState->aScreens[idScreen];
972	}
973	return NULL;
974	}
975
976	void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
977	{
978	#ifdef VBOX_WITH_VMSVGA3D
979	if (pThis->svga.f3DEnabled)
980	{
981	for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
982	{
983	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
984	if (pScreen)
985	vmsvga3dDestroyScreen(pThisCC, pScreen);
986	}
987	}
988	#else
989	RT_NOREF(pThis, pThisCC);
990	#endif
991	}
992
993
994	/**
995	* Copy a rectangle of pixels within guest VRAM.
996	*/
997	static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
998	uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
999	{
1000	if (!width \|\| !height)
1001	return; /* Nothing to do, don't even bother. */
1002
1003	/*
1004	* The guest VRAM (aka GFB) is considered to be a bitmap in the format
1005	* corresponding to the current display mode.
1006	*/
1007	uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1008	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1009	uint8_t const *pSrc;
1010	uint8_t *pDst;
1011	unsigned const cbRectWidth = width * cbPixel;
1012	unsigned uMaxOffset;
1013
1014	uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1015	if (uMaxOffset >= cbFrameBuffer)
1016	{
1017	Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1018	return; /* Just don't listen to a bad guest. */
1019	}
1020
1021	pSrc = pDst = pThisCC->pbVRam;
1022	pSrc += srcY * cbScanline + srcX * cbPixel;
1023	pDst += dstY * cbScanline + dstX * cbPixel;
1024
1025	if (srcY >= dstY)
1026	{
1027	/* Source below destination, copy top to bottom. */
1028	for (; height > 0; height--)
1029	{
1030	memmove(pDst, pSrc, cbRectWidth);
1031	pSrc += cbScanline;
1032	pDst += cbScanline;
1033	}
1034	}
1035	else
1036	{
1037	/* Source above destination, copy bottom to top. */
1038	pSrc += cbScanline * (height - 1);
1039	pDst += cbScanline * (height - 1);
1040	for (; height > 0; height--)
1041	{
1042	memmove(pDst, pSrc, cbRectWidth);
1043	pSrc -= cbScanline;
1044	pDst -= cbScanline;
1045	}
1046	}
1047	}
1048
1049
1050	/**
1051	* Common worker for changing the pointer shape.
1052	*
1053	* @param pThisCC The VGA/VMSVGA state for ring-3.
1054	* @param pSVGAState The VMSVGA ring-3 instance data.
1055	* @param fAlpha Whether there is alpha or not.
1056	* @param xHot Hotspot x coordinate.
1057	* @param yHot Hotspot y coordinate.
1058	* @param cx Width.
1059	* @param cy Height.
1060	* @param pbData Heap copy of the cursor data. Consumed.
1061	* @param cbData The size of the data.
1062	*/
1063	static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
1064	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
1065	{
1066	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
1067	#ifdef LOG_ENABLED
1068	if (LogIs2Enabled())
1069	{
1070	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
1071	if (!fAlpha)
1072	{
1073	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
1074	for (uint32_t y = 0; y < cy; y++)
1075	{
1076	Log2(("%3u:", y));
1077	uint8_t const pbLine = &pbData[y cbAndLine];
1078	for (uint32_t x = 0; x < cx; x += 8)
1079	{
1080	uint8_t b = pbLine[x / 8];
1081	char szByte[12];
1082	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
1083	szByte[1] = b & 0x40 ? '*' : ' ';
1084	szByte[2] = b & 0x20 ? '*' : ' ';
1085	szByte[3] = b & 0x10 ? '*' : ' ';
1086	szByte[4] = b & 0x08 ? '*' : ' ';
1087	szByte[5] = b & 0x04 ? '*' : ' ';
1088	szByte[6] = b & 0x02 ? '*' : ' ';
1089	szByte[7] = b & 0x01 ? '*' : ' ';
1090	szByte[8] = '\0';
1091	Log2(("%s", szByte));
1092	}
1093	Log2(("\n"));
1094	}
1095	}
1096
1097	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
1098	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
1099	for (uint32_t y = 0; y < cy; y++)
1100	{
1101	Log2(("%3u:", y));
1102	uint32_t const pu32Line = &pu32Xor[y cx];
1103	for (uint32_t x = 0; x < cx; x++)
1104	Log2((" %08x", pu32Line[x]));
1105	Log2(("\n"));
1106	}
1107	}
1108	#endif
1109
1110	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
1111	AssertRC(rc);
1112
1113	if (pSVGAState->Cursor.fActive)
1114	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
1115
1116	pSVGAState->Cursor.fActive = true;
1117	pSVGAState->Cursor.xHotspot = xHot;
1118	pSVGAState->Cursor.yHotspot = yHot;
1119	pSVGAState->Cursor.width = cx;
1120	pSVGAState->Cursor.height = cy;
1121	pSVGAState->Cursor.cbData = cbData;
1122	pSVGAState->Cursor.pData = pbData;
1123	}
1124
1125
1126	#ifdef VBOX_WITH_VMSVGA3D
1127
1128	/*
1129	* SVGA_3D_CMD_* handlers.
1130	*/
1131
1132
1133	/** SVGA_3D_CMD_SURFACE_DEFINE 1040, SVGA_3D_CMD_SURFACE_DEFINE_V2 1070
1134	*
1135	* @param pThisCC The VGA/VMSVGA state for the current context.
1136	* @param pCmd The VMSVGA command.
1137	* @param cMipLevelSizes Number of elements in the paMipLevelSizes array.
1138	* @param paMipLevelSizes Arrays of surface sizes for each face and miplevel.
1139	*/
1140	static void vmsvga3dCmdDefineSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineSurface_v2 const *pCmd,
1141	uint32_t cMipLevelSizes, SVGA3dSize *paMipLevelSizes)
1142	{
1143	ASSERT_GUEST_RETURN_VOID(pCmd->sid < SVGA3D_MAX_SURFACE_IDS);
1144	ASSERT_GUEST_RETURN_VOID(cMipLevelSizes >= 1);
1145	RT_UNTRUSTED_VALIDATED_FENCE();
1146
1147	/* Number of faces (cFaces) is specified as the number of the first non-zero elements in the 'face' array.
1148	* Since only plain surfaces (cFaces == 1) and cubemaps (cFaces == 6) are supported
1149	* (see also SVGA3dCmdDefineSurface definition in svga3d_reg.h), we ignore anything else.
1150	*/
1151	uint32_t cRemainingMipLevels = cMipLevelSizes;
1152	uint32_t cFaces = 0;
1153	for (uint32_t i = 0; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1154	{
1155	if (pCmd->face[i].numMipLevels == 0)
1156	break;
1157
1158	/* All SVGA3dSurfaceFace structures must have the same value of numMipLevels field */
1159	ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == pCmd->face[0].numMipLevels);
1160
1161	/* numMipLevels value can't be greater than the number of remaining elements in the paMipLevelSizes array. */
1162	ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels <= cRemainingMipLevels);
1163	cRemainingMipLevels -= pCmd->face[i].numMipLevels;
1164
1165	++cFaces;
1166	}
1167	for (uint32_t i = cFaces; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1168	ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == 0);
1169
1170	/* cFaces must be 6 for a cubemap and 1 otherwise. */
1171	ASSERT_GUEST_RETURN_VOID(cFaces == (uint32_t)((pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP) ? 6 : 1));
1172
1173	/* Sum of face[i].numMipLevels must be equal to cMipLevels. */
1174	ASSERT_GUEST_RETURN_VOID(cRemainingMipLevels == 0);
1175	RT_UNTRUSTED_VALIDATED_FENCE();
1176
1177	/* Verify paMipLevelSizes */
1178	uint32_t cWidth = paMipLevelSizes[0].width;
1179	uint32_t cHeight = paMipLevelSizes[0].height;
1180	uint32_t cDepth = paMipLevelSizes[0].depth;
1181	for (uint32_t i = 1; i < pCmd->face[0].numMipLevels; ++i)
1182	{
1183	cWidth >>= 1;
1184	if (cWidth == 0) cWidth = 1;
1185	cHeight >>= 1;
1186	if (cHeight == 0) cHeight = 1;
1187	cDepth >>= 1;
1188	if (cDepth == 0) cDepth = 1;
1189	for (uint32_t iFace = 0; iFace < cFaces; ++iFace)
1190	{
1191	uint32_t const iMipLevelSize = iFace * pCmd->face[0].numMipLevels + i;
1192	ASSERT_GUEST_RETURN_VOID( cWidth == paMipLevelSizes[iMipLevelSize].width
1193	&& cHeight == paMipLevelSizes[iMipLevelSize].height
1194	&& cDepth == paMipLevelSizes[iMipLevelSize].depth);
1195	}
1196	}
1197	RT_UNTRUSTED_VALIDATED_FENCE();
1198
1199	/* Create the surface. */
1200	vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1201	pCmd->multisampleCount, pCmd->autogenFilter,
1202	pCmd->face[0].numMipLevels, &paMipLevelSizes[0], /* arraySize = / 0, / fAllocMipLevels = */ true);
1203	}
1204
1205
1206	/* SVGA_3D_CMD_SET_OTABLE_BASE 1091 */
1207	static void vmsvga3dCmdSetOTableBase(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase const *pCmd)
1208	{
1209	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1210	vmsvgaR3OTableSetOrGrow(pSvgaR3State, pCmd->type, pCmd->baseAddress,
1211	pCmd->sizeInBytes, pCmd->validSizeInBytes, pCmd->ptDepth, /fGrow/ false);
1212	}
1213
1214
1215	/* SVGA_3D_CMD_DEFINE_GB_MOB 1093 */
1216	static void vmsvga3dCmdDefineGBMob(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob const *pCmd)
1217	{
1218	DEBUG_BREAKPOINT_TEST();
1219	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1220
1221	ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1222
1223	/* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1224	/* Allocate a structure for the MOB. */
1225	PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1226	AssertPtrReturnVoid(pMob);
1227
1228	int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, pMob);
1229	if (RT_SUCCESS(rc))
1230	{
1231	return;
1232	}
1233
1234	AssertFailed();
1235
1236	RTMemFree(pMob);
1237	}
1238
1239
1240	/* SVGA_3D_CMD_DESTROY_GB_MOB 1094 */
1241	static void vmsvga3dCmdDestroyGBMob(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBMob const *pCmd)
1242	{
1243	//DEBUG_BREAKPOINT_TEST();
1244	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1245
1246	ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1247
1248	int rc = vmsvgaR3MobDestroy(pSvgaR3State, pCmd->mobid);
1249	if (RT_SUCCESS(rc))
1250	{
1251	return;
1252	}
1253
1254	AssertFailed();
1255	}
1256
1257
1258	/* SVGA_3D_CMD_DEFINE_GB_SURFACE 1097 */
1259	static void vmsvga3dCmdDefineGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface const *pCmd)
1260	{
1261	//DEBUG_BREAKPOINT_TEST();
1262	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1263
1264	/* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1265	SVGAOTableSurfaceEntry entry;
1266	RT_ZERO(entry);
1267	entry.format = pCmd->format;
1268	entry.surface1Flags = pCmd->surfaceFlags;
1269	entry.numMipLevels = pCmd->numMipLevels;
1270	entry.multisampleCount = pCmd->multisampleCount;
1271	entry.autogenFilter = pCmd->autogenFilter;
1272	entry.size = pCmd->size;
1273	entry.mobid = SVGA_ID_INVALID;
1274	// entry.arraySize = 0;
1275	// entry.mobPitch = 0;
1276	int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1277	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1278	if (RT_SUCCESS(rc))
1279	{
1280	/* Create the host surface. */
1281	vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1282	pCmd->multisampleCount, pCmd->autogenFilter,
1283	pCmd->numMipLevels, &pCmd->size, /* arraySize = / 0, / fAllocMipLevels = */ false);
1284	}
1285	}
1286
1287
1288	/* SVGA_3D_CMD_DESTROY_GB_SURFACE 1098 */
1289	static void vmsvga3dCmdDestroyGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBSurface const *pCmd)
1290	{
1291	//DEBUG_BREAKPOINT_TEST();
1292	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1293
1294	/* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1295	SVGAOTableSurfaceEntry entry;
1296	RT_ZERO(entry);
1297	entry.mobid = SVGA_ID_INVALID;
1298	vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1299	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1300
1301	vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
1302	}
1303
1304
1305	/* SVGA_3D_CMD_BIND_GB_SURFACE 1099 */
1306	static void vmsvga3dCmdBindGBSurface(PVGASTATECC pThisCC, SVGA3dCmdBindGBSurface const *pCmd)
1307	{
1308	//DEBUG_BREAKPOINT_TEST();
1309	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1310
1311	/* Assign the mobid to the surface. */
1312	int rc = VINF_SUCCESS;
1313	if (pCmd->mobid != SVGA_ID_INVALID)
1314	rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1315	pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1316	if (RT_SUCCESS(rc))
1317	{
1318	SVGAOTableSurfaceEntry entry;
1319	rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1320	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1321	if (RT_SUCCESS(rc))
1322	{
1323	entry.mobid = pCmd->mobid;
1324	rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1325	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1326	if (RT_SUCCESS(rc))
1327	{
1328	/* */
1329	}
1330	}
1331	}
1332	}
1333
1334
1335	typedef union
1336	{
1337	float f;
1338	uint32_t u;
1339	} Unsigned2Float;
1340
1341	float float16ToFloat(uint16_t f16)
1342	{
1343	/* Format specs from Wiki: [15] = sign, [14:10] = exponent, [9:0] = fraction */
1344	uint16_t const f = f16 & 0x3FF;
1345	uint16_t const e = (f16 >> 10) & 0x1F;
1346	uint16_t const s = (f16 >> 15) & 0x1;
1347	Unsigned2Float u2f;
1348
1349	if (e == 0)
1350	{
1351	if (f == 0)
1352	{
1353	/* zero, -0 */
1354	u2f.u = (s << 31) \| (0 << 23) \| 0;
1355	return u2f.f;
1356	}
1357
1358	/* subnormal numbers: (-1)^signbit * 2^-14 * 0.significantbits */
1359	float const k = 1.0f / 16384.0f; /* 2^-14 */
1360	return (s ? -1.0f : 1.0f) * k * (float)f / 1024.0f;
1361	}
1362
1363	if (e == 31)
1364	{
1365	if (f == 0)
1366	{
1367	/* +-infinity */
1368	u2f.u = (s << 31) \| (0xFF << 23) \| 0;
1369	return u2f.f;
1370	}
1371
1372	/* NaN */
1373	u2f.u = (s << 31) \| (0xFF << 23) \| 1;
1374	return u2f.f;
1375	}
1376
1377	/* normalized value: (-1)^signbit * 2^(exponent - 15) * 1.significantbits */
1378	/* Build the float, adjusting for exponent bias (float32 bias is 127, float16 is 15)
1379	* and number of bits in the fraction (float32 has 23, float16 has 10). */
1380	u2f.u = (s << 31) \| ((e + 127 - 15) << 23) \| (f << (23 - 10));
1381	return u2f.f;
1382	}
1383
1384
1385	static int vmsvga3dBmpWrite(const char pszFilename, VMSVGA3D_MAPPED_SURFACE const pMap)
1386	{
1387	if ( pMap->cbBlock != 4 && pMap->cbBlock != 1
1388	&& pMap->format != SVGA3D_R16G16B16A16_FLOAT
1389	&& pMap->format != SVGA3D_R32G32B32A32_FLOAT)
1390	return VERR_NOT_SUPPORTED;
1391
1392	int const w = pMap->cbRow / pMap->cbBlock;
1393	int const h = pMap->cRows;
1394
1395	const int cbBitmap = pMap->cbRow * pMap->cRows * 4;
1396
1397	FILE *f = fopen(pszFilename, "wb");
1398	if (!f)
1399	return VERR_FILE_NOT_FOUND;
1400
1401	{
1402	BMPFILEHDR fileHdr;
1403	RT_ZERO(fileHdr);
1404	fileHdr.uType = BMP_HDR_MAGIC;
1405	fileHdr.cbFileSize = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR) + cbBitmap;
1406	fileHdr.offBits = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR);
1407
1408	BMPWIN3XINFOHDR coreHdr;
1409	RT_ZERO(coreHdr);
1410	coreHdr.cbSize = sizeof(coreHdr);
1411	coreHdr.uWidth = w;
1412	coreHdr.uHeight = -h;
1413	coreHdr.cPlanes = 1;
1414	coreHdr.cBits = 32;
1415	coreHdr.cbSizeImage = cbBitmap;
1416
1417	fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1418	fwrite(&coreHdr, 1, sizeof(coreHdr), f);
1419	}
1420
1421	if (pMap->format == SVGA3D_R16G16B16A16_FLOAT)
1422	{
1423	const uint8_t s = (uint8_t )pMap->pvData;
1424	for (int32_t y = 0; y < h; ++y)
1425	{
1426	for (int32_t x = 0; x < w; ++x)
1427	{
1428	uint16_t const pu16Pixel = (uint16_t )(s + x * 8);
1429	uint8_t r = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[0]));
1430	uint8_t g = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[1]));
1431	uint8_t b = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[2]));
1432	uint8_t a = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[3]));
1433	uint32_t u32Pixel = b + (g << 8) + (r << 16) + (a << 24);
1434	fwrite(&u32Pixel, 1, 4, f);
1435	}
1436
1437	s += pMap->cbRowPitch;
1438	}
1439	}
1440	else if (pMap->format == SVGA3D_R32G32B32A32_FLOAT)
1441	{
1442	const uint8_t s = (uint8_t )pMap->pvData;
1443	for (int32_t y = 0; y < h; ++y)
1444	{
1445	for (int32_t x = 0; x < w; ++x)
1446	{
1447	float const pPixel = (float )(s + x * 8);
1448	uint8_t r = (uint8_t)(255.0 * pPixel[0]);
1449	uint8_t g = (uint8_t)(255.0 * pPixel[1]);
1450	uint8_t b = (uint8_t)(255.0 * pPixel[2]);
1451	uint8_t a = (uint8_t)(255.0 * pPixel[3]);
1452	uint32_t u32Pixel = b + (g << 8) + (r << 16) + (a << 24);
1453	fwrite(&u32Pixel, 1, 4, f);
1454	}
1455
1456	s += pMap->cbRowPitch;
1457	}
1458	}
1459	else if (pMap->cbBlock == 4)
1460	{
1461	const uint8_t s = (uint8_t )pMap->pvData;
1462	for (uint32_t iRow = 0; iRow < pMap->cRows; ++iRow)
1463	{
1464	fwrite(s, 1, pMap->cbRow, f);
1465
1466	s += pMap->cbRowPitch;
1467	}
1468	}
1469	else if (pMap->cbBlock == 1)
1470	{
1471	const uint8_t s = (uint8_t )pMap->pvData;
1472	for (uint32_t iRow = 0; iRow < pMap->cRows; ++iRow)
1473	{
1474	for (int32_t x = 0; x < w; ++x)
1475	{
1476	uint32_t u32Pixel = s[x];
1477	fwrite(&u32Pixel, 1, 4, f);
1478	}
1479
1480	s += pMap->cbRowPitch;
1481	}
1482	}
1483
1484	fclose(f);
1485
1486	return VINF_SUCCESS;
1487	}
1488
1489
1490	void vmsvga3dMapWriteBmpFile(VMSVGA3D_MAPPED_SURFACE const pMap, char const pszPrefix)
1491	{
1492	static int idxBitmap = 0;
1493	char *pszFilename = RTStrAPrintf2("bmp\\%s%d.bmp", pszPrefix, idxBitmap++);
1494	int rc = vmsvga3dBmpWrite(pszFilename, pMap);
1495	Log(("WriteBmpFile %s format %d %Rrc\n", pszFilename, pMap->format, rc)); RT_NOREF(rc);
1496	RTStrFree(pszFilename);
1497	}
1498
1499
1500	static int vmsvgaR3TransferSurfaceLevel(PVGASTATECC pThisCC,
1501	PVMSVGAMOB pMob,
1502	SVGA3dSurfaceImageId const *pImage,
1503	SVGA3dBox const *pBox,
1504	SVGA3dTransferType enmTransfer)
1505	{
1506	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1507
1508	VMSVGA3D_SURFACE_MAP enmMapType;
1509	if (enmTransfer == SVGA3D_WRITE_HOST_VRAM)
1510	enmMapType = pBox
1511	? VMSVGA3D_SURFACE_MAP_WRITE
1512	: VMSVGA3D_SURFACE_MAP_WRITE_DISCARD;
1513	else if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1514	enmMapType = VMSVGA3D_SURFACE_MAP_READ;
1515	else
1516	AssertFailedReturn(VERR_INVALID_PARAMETER);
1517
1518	VMSVGA3D_MAPPED_SURFACE map;
1519	int rc = vmsvga3dSurfaceMap(pThisCC, pImage, pBox, enmMapType, &map);
1520	if (RT_SUCCESS(rc))
1521	{
1522	/* Copy mapped surface <-> MOB. */
1523	VMSGA3D_BOX_DIMENSIONS dims;
1524	rc = vmsvga3dGetBoxDimensions(pThisCC, pImage, pBox, &dims);
1525	if (RT_SUCCESS(rc))
1526	{
1527	for (uint32_t z = 0; z < map.box.d; ++z)
1528	{
1529	uint8_t pu8Map = (uint8_t )map.pvData + z * map.cbDepthPitch;
1530	uint32_t offMob = dims.offSubresource + dims.offBox + z * dims.cbDepthPitch;
1531
1532	for (uint32_t iRow = 0; iRow < map.cRows; ++iRow)
1533	{
1534	if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1535	rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1536	else
1537	rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1538	AssertRCBreak(rc);
1539
1540	pu8Map += map.cbRowPitch;
1541	offMob += dims.cbPitch;
1542	}
1543	}
1544	}
1545
1546	// vmsvga3dMapWriteBmpFile(&map, "Dynamic");
1547
1548	bool const fWritten = (enmTransfer == SVGA3D_WRITE_HOST_VRAM);
1549	vmsvga3dSurfaceUnmap(pThisCC, pImage, &map, fWritten);
1550	}
1551
1552	return rc;
1553	}
1554
1555
1556	/* SVGA_3D_CMD_UPDATE_GB_IMAGE 1101 */
1557	static void vmsvga3dCmdUpdateGBImage(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBImage const *pCmd)
1558	{
1559	//DEBUG_BREAKPOINT_TEST();
1560	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1561
1562	LogFlowFunc(("sid=%u @%u,%u,%u %ux%ux%u\n",
1563	pCmd->image.sid, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
1564
1565	/*
1566	SVGA3dSurfaceFormat format;
1567	SVGA3dSurface1Flags surface1Flags;
1568	uint32 numMipLevels;
1569	uint32 multisampleCount;
1570	SVGA3dTextureFilter autogenFilter;
1571	SVGA3dSize size;
1572	SVGAMobId mobid;
1573	uint32 arraySize;
1574	uint32 mobPitch;
1575	SVGA3dSurface2Flags surface2Flags;
1576	uint8 multisamplePattern;
1577	uint8 qualityLevel;
1578	uint16 bufferByteStride;
1579	float minLOD;
1580	*/
1581
1582	/* "update a surface from its backing MOB." */
1583	SVGAOTableSurfaceEntry entrySurface;
1584	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1585	pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1586	if (RT_SUCCESS(rc))
1587	{
1588	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1589	if (pMob)
1590	{
1591	rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
1592	AssertRC(rc);
1593	}
1594	}
1595	}
1596
1597
1598	/* SVGA_3D_CMD_UPDATE_GB_SURFACE 1102 */
1599	static void vmsvga3dCmdUpdateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBSurface const *pCmd)
1600	{
1601	//DEBUG_BREAKPOINT_TEST();
1602	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1603
1604	LogFlowFunc(("sid=%u\n",
1605	pCmd->sid));
1606
1607	/* "update a surface from its backing MOB." */
1608	SVGAOTableSurfaceEntry entrySurface;
1609	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1610	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1611	if (RT_SUCCESS(rc))
1612	{
1613	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1614	if (pMob)
1615	{
1616	uint32 const arraySize = vmsvga3dGetArrayElements(pThisCC, pCmd->sid);
1617	for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1618	{
1619	for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1620	{
1621	SVGA3dSurfaceImageId image;
1622	image.sid = pCmd->sid;
1623	image.face = iArray;
1624	image.mipmap = iMipmap;
1625
1626	rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_WRITE_HOST_VRAM);
1627	AssertRCBreak(rc);
1628	}
1629	}
1630	}
1631	}
1632	}
1633
1634
1635	/* SVGA_3D_CMD_READBACK_GB_IMAGE 1103 */
1636	static void vmsvga3dCmdReadbackGBImage(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBImage const *pCmd)
1637	{
1638	//DEBUG_BREAKPOINT_TEST();
1639	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1640
1641	LogFlowFunc(("sid=%u, face=%u, mipmap=%u\n",
1642	pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap));
1643
1644	/* Read a surface to its backing MOB. */
1645	SVGAOTableSurfaceEntry entrySurface;
1646	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1647	pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1648	if (RT_SUCCESS(rc))
1649	{
1650	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1651	if (pMob)
1652	{
1653	rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1654	AssertRC(rc);
1655	}
1656	}
1657	}
1658
1659
1660	/* SVGA_3D_CMD_READBACK_GB_SURFACE 1104 */
1661	static void vmsvga3dCmdReadbackGBSurface(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBSurface const *pCmd)
1662	{
1663	//DEBUG_BREAKPOINT_TEST();
1664	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1665
1666	LogFlowFunc(("sid=%u\n",
1667	pCmd->sid));
1668
1669	/* Read a surface to its backing MOB. */
1670	SVGAOTableSurfaceEntry entrySurface;
1671	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1672	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1673	if (RT_SUCCESS(rc))
1674	{
1675	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1676	if (pMob)
1677	{
1678	uint32 const arraySize = vmsvga3dGetArrayElements(pThisCC, pCmd->sid);
1679	for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1680	{
1681	for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1682	{
1683	SVGA3dSurfaceImageId image;
1684	image.sid = pCmd->sid;
1685	image.face = iArray;
1686	image.mipmap = iMipmap;
1687
1688	rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1689	AssertRCBreak(rc);
1690	}
1691	}
1692	}
1693	}
1694	}
1695
1696
1697	/* SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105 */
1698	static void vmsvga3dCmdInvalidateGBImage(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBImage const *pCmd)
1699	{
1700	//DEBUG_BREAKPOINT_TEST();
1701	vmsvga3dSurfaceInvalidate(pThisCC, pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap);
1702	}
1703
1704
1705	/* SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106 */
1706	static void vmsvga3dCmdInvalidateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBSurface const *pCmd)
1707	{
1708	//DEBUG_BREAKPOINT_TEST();
1709	vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, SVGA_ID_INVALID, SVGA_ID_INVALID);
1710	}
1711
1712
1713	/* SVGA_3D_CMD_SET_OTABLE_BASE64 1115 */
1714	static void vmsvga3dCmdSetOTableBase64(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase64 const *pCmd)
1715	{
1716	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1717	vmsvgaR3OTableSetOrGrow(pSvgaR3State, pCmd->type, pCmd->baseAddress,
1718	pCmd->sizeInBytes, pCmd->validSizeInBytes, pCmd->ptDepth, /fGrow/ false);
1719	}
1720
1721
1722	/* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124 */
1723	static void vmsvga3dCmdDefineGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDefineGBScreenTarget const *pCmd)
1724	{
1725	//DEBUG_BREAKPOINT_TEST();
1726	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1727
1728	ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1729	ASSERT_GUEST_RETURN_VOID(pCmd->width > 0 && pCmd->width <= pThis->svga.u32MaxWidth); /* SVGA_REG_SCREENTARGET_MAX_WIDTH */
1730	ASSERT_GUEST_RETURN_VOID(pCmd->height > 0 && pCmd->height <= pThis->svga.u32MaxHeight); /* SVGA_REG_SCREENTARGET_MAX_HEIGHT */
1731	RT_UNTRUSTED_VALIDATED_FENCE();
1732
1733	/* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1734	SVGAOTableScreenTargetEntry entry;
1735	RT_ZERO(entry);
1736	entry.image.sid = SVGA_ID_INVALID;
1737	// entry.image.face = 0;
1738	// entry.image.mipmap = 0;
1739	entry.width = pCmd->width;
1740	entry.height = pCmd->height;
1741	entry.xRoot = pCmd->xRoot;
1742	entry.yRoot = pCmd->yRoot;
1743	entry.flags = pCmd->flags;
1744	entry.dpi = pCmd->dpi;
1745
1746	int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1747	pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1748	if (RT_SUCCESS(rc))
1749	{
1750	/* Screen objects and screen targets are similar, therefore we will use the same for both. */
1751	/** @todo Generic screen object/target interface. */
1752	VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1753	pScreen->fDefined = true;
1754	pScreen->fModified = true;
1755	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET
1756	\| (RT_BOOL(pCmd->flags & SVGA_STFLAG_PRIMARY) ? SVGA_SCREEN_IS_PRIMARY : 0);
1757	pScreen->idScreen = pCmd->stid;
1758
1759	pScreen->xOrigin = pCmd->xRoot;
1760	pScreen->yOrigin = pCmd->yRoot;
1761	pScreen->cWidth = pCmd->width;
1762	pScreen->cHeight = pCmd->height;
1763	pScreen->offVRAM = 0; /* Not applicable for screen targets, they use either a separate memory buffer or a host window. */
1764	pScreen->cbPitch = pCmd->width * 4;
1765	pScreen->cBpp = 32;
1766
1767	if (RT_LIKELY(pThis->svga.f3DEnabled))
1768	vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
1769
1770	if (!pScreen->pHwScreen)
1771	{
1772	/* System memory buffer. */
1773	pScreen->pvScreenBitmap = RTMemAllocZ(pScreen->cHeight * pScreen->cbPitch);
1774	}
1775
1776	pThis->svga.fGFBRegisters = false;
1777	vmsvgaR3ChangeMode(pThis, pThisCC);
1778	}
1779	}
1780
1781
1782	/* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125 */
1783	static void vmsvga3dCmdDestroyGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDestroyGBScreenTarget const *pCmd)
1784	{
1785	//DEBUG_BREAKPOINT_TEST();
1786	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1787
1788	ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1789	RT_UNTRUSTED_VALIDATED_FENCE();
1790
1791	/* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1792	SVGAOTableScreenTargetEntry entry;
1793	RT_ZERO(entry);
1794	int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1795	pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1796	if (RT_SUCCESS(rc))
1797	{
1798	/* Screen objects and screen targets are similar, therefore we will use the same for both. */
1799	/** @todo Generic screen object/target interface. */
1800	VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1801	pScreen->fModified = true;
1802	pScreen->fDefined = false;
1803	pScreen->idScreen = pCmd->stid;
1804
1805	if (RT_LIKELY(pThis->svga.f3DEnabled))
1806	vmsvga3dDestroyScreen(pThisCC, pScreen);
1807
1808	vmsvgaR3ChangeMode(pThis, pThisCC);
1809
1810	RTMemFree(pScreen->pvScreenBitmap);
1811	pScreen->pvScreenBitmap = NULL;
1812	}
1813	}
1814
1815
1816	/* SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126 */
1817	static void vmsvga3dCmdBindGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdBindGBScreenTarget const *pCmd)
1818	{
1819	//DEBUG_BREAKPOINT_TEST();
1820	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1821
1822	/* "Binding a surface to a Screen Target the same as flipping" */
1823
1824	ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1825	ASSERT_GUEST_RETURN_VOID(pCmd->image.face == 0 && pCmd->image.mipmap == 0);
1826	RT_UNTRUSTED_VALIDATED_FENCE();
1827
1828	/* Assign the surface to the screen target. */
1829	int rc = VINF_SUCCESS;
1830	if (pCmd->image.sid != SVGA_ID_INVALID)
1831	rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1832	pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE);
1833	if (RT_SUCCESS(rc))
1834	{
1835	SVGAOTableScreenTargetEntry entry;
1836	rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1837	pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1838	if (RT_SUCCESS(rc))
1839	{
1840	entry.image = pCmd->image;
1841	rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1842	pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1843	if (RT_SUCCESS(rc))
1844	{
1845	VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1846	rc = pSvgaR3State->pFuncsGBO->pfnScreenTargetBind(pThisCC, pScreen, pCmd->image.sid);
1847	AssertRC(rc);
1848	}
1849	}
1850	}
1851	}
1852
1853
1854	/* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127 */
1855	static void vmsvga3dCmdUpdateGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBScreenTarget const *pCmd)
1856	{
1857	//DEBUG_BREAKPOINT_TEST();
1858	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1859
1860	/* Update the screen target from its backing surface. */
1861	ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1862	RT_UNTRUSTED_VALIDATED_FENCE();
1863
1864	/* Get the screen target info. */
1865	SVGAOTableScreenTargetEntry entryScreenTarget;
1866	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1867	pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entryScreenTarget, sizeof(entryScreenTarget));
1868	if (RT_SUCCESS(rc))
1869	{
1870	ASSERT_GUEST_RETURN_VOID(entryScreenTarget.image.face == 0 && entryScreenTarget.image.mipmap == 0);
1871	RT_UNTRUSTED_VALIDATED_FENCE();
1872
1873	if (entryScreenTarget.image.sid != SVGA_ID_INVALID)
1874	{
1875	SVGAOTableSurfaceEntry entrySurface;
1876	rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1877	entryScreenTarget.image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1878	if (RT_SUCCESS(rc))
1879	{
1880	/* Copy entrySurface.mobid content to the screen target. */
1881	if (entrySurface.mobid != SVGA_ID_INVALID)
1882	{
1883	RT_UNTRUSTED_VALIDATED_FENCE();
1884	SVGA3dRect targetRect = pCmd->rect;
1885
1886	VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1887	if (pScreen->pHwScreen)
1888	{
1889	/* Copy the screen target surface to the backend's screen. */
1890	pSvgaR3State->pFuncsGBO->pfnScreenTargetUpdate(pThisCC, pScreen, &targetRect);
1891	}
1892	else
1893	{
1894	SVGASignedRect r;
1895	r.left = pCmd->rect.x;
1896	r.top = pCmd->rect.y;
1897	r.right = pCmd->rect.x + pCmd->rect.w;
1898	r.bottom = pCmd->rect.y + pCmd->rect.h;
1899	vmsvga3dScreenUpdate(pThisCC, pCmd->stid, r, entryScreenTarget.image, r, 0, NULL);
1900	}
1901	}
1902	}
1903	}
1904	}
1905	}
1906
1907
1908	/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134 */
1909	static void vmsvga3dCmdDefineGBSurface_v2(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v2 const *pCmd)
1910	{
1911	//DEBUG_BREAKPOINT_TEST();
1912	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1913
1914	/* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1915	SVGAOTableSurfaceEntry entry;
1916	RT_ZERO(entry);
1917	entry.format = pCmd->format;
1918	entry.surface1Flags = pCmd->surfaceFlags;
1919	entry.numMipLevels = pCmd->numMipLevels;
1920	entry.multisampleCount = pCmd->multisampleCount;
1921	entry.autogenFilter = pCmd->autogenFilter;
1922	entry.size = pCmd->size;
1923	entry.mobid = SVGA_ID_INVALID;
1924	entry.arraySize = pCmd->arraySize;
1925	// entry.mobPitch = 0;
1926	// entry.mobPitch = 0;
1927	// entry.surface2Flags = 0;
1928	// entry.multisamplePattern = 0;
1929	// entry.qualityLevel = 0;
1930	// entry.bufferByteStride = 0;
1931	// entry.minLOD = 0;
1932
1933	int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1934	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1935	if (RT_SUCCESS(rc))
1936	{
1937	/* Create the host surface. */
1938	/** @todo SVGAOTableSurfaceEntry as input parameter? */
1939	vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1940	pCmd->multisampleCount, pCmd->autogenFilter,
1941	pCmd->numMipLevels, &pCmd->size, pCmd->arraySize, /* fAllocMipLevels = */ false);
1942	}
1943	}
1944
1945
1946	/* SVGA_3D_CMD_DEFINE_GB_MOB64 1135 */
1947	static void vmsvga3dCmdDefineGBMob64(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob64 const *pCmd)
1948	{
1949	//DEBUG_BREAKPOINT_TEST();
1950	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1951
1952	ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1953
1954	/* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1955	/* Allocate a structure for the MOB. */
1956	PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1957	AssertPtrReturnVoid(pMob);
1958
1959	int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, pMob);
1960	if (RT_SUCCESS(rc))
1961	{
1962	return;
1963	}
1964
1965	RTMemFree(pMob);
1966	}
1967
1968
1969	/* SVGA_3D_CMD_DX_DEFINE_CONTEXT 1143 */
1970	static int vmsvga3dCmdDXDefineContext(PVGASTATECC pThisCC, SVGA3dCmdDXDefineContext const *pCmd, uint32_t cbCmd)
1971	{
1972	#ifdef VMSVGA3D_DX
1973	//DEBUG_BREAKPOINT_TEST();
1974	RT_NOREF(cbCmd);
1975
1976	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1977
1978	/* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
1979	SVGAOTableDXContextEntry entry;
1980	RT_ZERO(entry);
1981	entry.cid = pCmd->cid;
1982	entry.mobid = SVGA_ID_INVALID;
1983	int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1984	pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1985	if (RT_SUCCESS(rc))
1986	{
1987	/* Create the host context. */
1988	rc = vmsvga3dDXDefineContext(pThisCC, pCmd->cid);
1989	}
1990
1991	return rc;
1992	#else
1993	RT_NOREF(pThisCC, pCmd, cbCmd);
1994	return VERR_NOT_SUPPORTED;
1995	#endif
1996	}
1997
1998
1999	/* SVGA_3D_CMD_DX_DESTROY_CONTEXT 1144 */
2000	static int vmsvga3dCmdDXDestroyContext(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyContext const *pCmd, uint32_t cbCmd)
2001	{
2002	#ifdef VMSVGA3D_DX
2003	//DEBUG_BREAKPOINT_TEST();
2004	RT_NOREF(cbCmd);
2005
2006	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2007
2008	/* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
2009	SVGAOTableDXContextEntry entry;
2010	RT_ZERO(entry);
2011	vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2012	pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2013
2014	return vmsvga3dDXDestroyContext(pThisCC, pCmd->cid);
2015	#else
2016	RT_NOREF(pThisCC, pCmd, cbCmd);
2017	return VERR_NOT_SUPPORTED;
2018	#endif
2019	}
2020
2021
2022	/* SVGA_3D_CMD_DX_BIND_CONTEXT 1145 */
2023	static int vmsvga3dCmdDXBindContext(PVGASTATECC pThisCC, SVGA3dCmdDXBindContext const *pCmd, uint32_t cbCmd)
2024	{
2025	#ifdef VMSVGA3D_DX
2026	//DEBUG_BREAKPOINT_TEST();
2027	RT_NOREF(cbCmd);
2028
2029	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2030
2031	/* Assign a mobid to a cid. */
2032	int rc = VINF_SUCCESS;
2033	if (pCmd->mobid != SVGA_ID_INVALID)
2034	rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
2035	pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
2036	if (RT_SUCCESS(rc))
2037	{
2038	SVGAOTableDXContextEntry entry;
2039	rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2040	pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2041	if (RT_SUCCESS(rc))
2042	{
2043	SVGADXContextMobFormat *pSvgaDXContext = NULL;
2044	if (pCmd->mobid != entry.mobid && entry.mobid != SVGA_ID_INVALID)
2045	{
2046	/* Unbind notification to the DX backend. Copy the context data to the guest backing memory. */
2047	pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2048	if (pSvgaDXContext)
2049	{
2050	rc = vmsvga3dDXUnbindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2051	if (RT_SUCCESS(rc))
2052	{
2053	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2054	if (pMob)
2055	{
2056	rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2057	}
2058	}
2059
2060	RTMemFree(pSvgaDXContext);
2061	pSvgaDXContext = NULL;
2062	}
2063	}
2064
2065	if (pCmd->mobid != SVGA_ID_INVALID)
2066	{
2067	/* Bind a new context. Copy existing data from the guest backing memory. */
2068	if (pCmd->validContents)
2069	{
2070	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2071	if (pMob)
2072	{
2073	pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2074	if (pSvgaDXContext)
2075	{
2076	rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2077	if (RT_FAILURE(rc))
2078	{
2079	RTMemFree(pSvgaDXContext);
2080	pSvgaDXContext = NULL;
2081	}
2082	}
2083	}
2084	}
2085
2086	rc = vmsvga3dDXBindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2087
2088	RTMemFree(pSvgaDXContext);
2089	}
2090
2091	/* Update the object table. */
2092	entry.mobid = pCmd->mobid;
2093	rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2094	pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2095	}
2096	}
2097
2098	return rc;
2099	#else
2100	RT_NOREF(pThisCC, pCmd, cbCmd);
2101	return VERR_NOT_SUPPORTED;
2102	#endif
2103	}
2104
2105
2106	/* SVGA_3D_CMD_DX_READBACK_CONTEXT 1146 */
2107	static int vmsvga3dCmdDXReadbackContext(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackContext const *pCmd, uint32_t cbCmd)
2108	{
2109	#ifdef VMSVGA3D_DX
2110	//DEBUG_BREAKPOINT_TEST();
2111	RT_NOREF(cbCmd);
2112
2113	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2114
2115	/* "Request that the device flush the contents back into guest memory." */
2116	SVGAOTableDXContextEntry entry;
2117	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2118	pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2119	if (RT_SUCCESS(rc))
2120	{
2121	if (entry.mobid != SVGA_ID_INVALID)
2122	{
2123	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2124	if (pMob)
2125	{
2126	/* Get the content. */
2127	SVGADXContextMobFormat pSvgaDXContext = (SVGADXContextMobFormat )RTMemAlloc(sizeof(SVGADXContextMobFormat));
2128	if (pSvgaDXContext)
2129	{
2130	rc = vmsvga3dDXReadbackContext(pThisCC, pCmd->cid, pSvgaDXContext);
2131	if (RT_SUCCESS(rc))
2132	rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2133
2134	RTMemFree(pSvgaDXContext);
2135	}
2136	else
2137	rc = VERR_NO_MEMORY;
2138	}
2139	}
2140	}
2141
2142	return rc;
2143	#else
2144	RT_NOREF(pThisCC, pCmd, cbCmd);
2145	return VERR_NOT_SUPPORTED;
2146	#endif
2147	}
2148
2149
2150	/* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT 1147 */
2151	static int vmsvga3dCmdDXInvalidateContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateContext const *pCmd, uint32_t cbCmd)
2152	{
2153	#ifdef VMSVGA3D_DX
2154	DEBUG_BREAKPOINT_TEST();
2155	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2156	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2157	return vmsvga3dDXInvalidateContext(pThisCC, idDXContext);
2158	#else
2159	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2160	return VERR_NOT_SUPPORTED;
2161	#endif
2162	}
2163
2164
2165	/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER 1148 */
2166	static int vmsvga3dCmdDXSetSingleConstantBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSingleConstantBuffer const *pCmd, uint32_t cbCmd)
2167	{
2168	#ifdef VMSVGA3D_DX
2169	//DEBUG_BREAKPOINT_TEST();
2170	RT_NOREF(cbCmd);
2171	return vmsvga3dDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd);
2172	#else
2173	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2174	return VERR_NOT_SUPPORTED;
2175	#endif
2176	}
2177
2178
2179	/* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES 1149 */
2180	static int vmsvga3dCmdDXSetShaderResources(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderResources const *pCmd, uint32_t cbCmd)
2181	{
2182	#ifdef VMSVGA3D_DX
2183	//DEBUG_BREAKPOINT_TEST();
2184	SVGA3dShaderResourceViewId const paShaderResourceViewId = (SVGA3dShaderResourceViewId )&pCmd[1];
2185	uint32_t const cShaderResourceViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dShaderResourceViewId);
2186	return vmsvga3dDXSetShaderResources(pThisCC, idDXContext, pCmd, cShaderResourceViewId, paShaderResourceViewId);
2187	#else
2188	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2189	return VERR_NOT_SUPPORTED;
2190	#endif
2191	}
2192
2193
2194	/* SVGA_3D_CMD_DX_SET_SHADER 1150 */
2195	static int vmsvga3dCmdDXSetShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShader const *pCmd, uint32_t cbCmd)
2196	{
2197	#ifdef VMSVGA3D_DX
2198	//DEBUG_BREAKPOINT_TEST();
2199	RT_NOREF(cbCmd);
2200	return vmsvga3dDXSetShader(pThisCC, idDXContext, pCmd);
2201	#else
2202	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2203	return VERR_NOT_SUPPORTED;
2204	#endif
2205	}
2206
2207
2208	/* SVGA_3D_CMD_DX_SET_SAMPLERS 1151 */
2209	static int vmsvga3dCmdDXSetSamplers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSamplers const *pCmd, uint32_t cbCmd)
2210	{
2211	#ifdef VMSVGA3D_DX
2212	//DEBUG_BREAKPOINT_TEST();
2213	SVGA3dSamplerId const paSamplerId = (SVGA3dSamplerId )&pCmd[1];
2214	uint32_t const cSamplerId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSamplerId);
2215	return vmsvga3dDXSetSamplers(pThisCC, idDXContext, pCmd, cSamplerId, paSamplerId);
2216	#else
2217	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2218	return VERR_NOT_SUPPORTED;
2219	#endif
2220	}
2221
2222
2223	/* SVGA_3D_CMD_DX_DRAW 1152 */
2224	static int vmsvga3dCmdDXDraw(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDraw const *pCmd, uint32_t cbCmd)
2225	{
2226	#ifdef VMSVGA3D_DX
2227	//DEBUG_BREAKPOINT_TEST();
2228	RT_NOREF(cbCmd);
2229	return vmsvga3dDXDraw(pThisCC, idDXContext, pCmd);
2230	#else
2231	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2232	return VERR_NOT_SUPPORTED;
2233	#endif
2234	}
2235
2236
2237	/* SVGA_3D_CMD_DX_DRAW_INDEXED 1153 */
2238	static int vmsvga3dCmdDXDrawIndexed(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexed const *pCmd, uint32_t cbCmd)
2239	{
2240	#ifdef VMSVGA3D_DX
2241	//DEBUG_BREAKPOINT_TEST();
2242	RT_NOREF(cbCmd);
2243	return vmsvga3dDXDrawIndexed(pThisCC, idDXContext, pCmd);
2244	#else
2245	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2246	return VERR_NOT_SUPPORTED;
2247	#endif
2248	}
2249
2250
2251	/* SVGA_3D_CMD_DX_DRAW_INSTANCED 1154 */
2252	static int vmsvga3dCmdDXDrawInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstanced const *pCmd, uint32_t cbCmd)
2253	{
2254	#ifdef VMSVGA3D_DX
2255	//DEBUG_BREAKPOINT_TEST();
2256	RT_NOREF(cbCmd);
2257	return vmsvga3dDXDrawInstanced(pThisCC, idDXContext, pCmd);
2258	#else
2259	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2260	return VERR_NOT_SUPPORTED;
2261	#endif
2262	}
2263
2264
2265	/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED 1155 */
2266	static int vmsvga3dCmdDXDrawIndexedInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstanced const *pCmd, uint32_t cbCmd)
2267	{
2268	#ifdef VMSVGA3D_DX
2269	//DEBUG_BREAKPOINT_TEST();
2270	RT_NOREF(cbCmd);
2271	return vmsvga3dDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd);
2272	#else
2273	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2274	return VERR_NOT_SUPPORTED;
2275	#endif
2276	}
2277
2278
2279	/* SVGA_3D_CMD_DX_DRAW_AUTO 1156 */
2280	static int vmsvga3dCmdDXDrawAuto(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawAuto const *pCmd, uint32_t cbCmd)
2281	{
2282	#ifdef VMSVGA3D_DX
2283	//DEBUG_BREAKPOINT_TEST();
2284	RT_NOREF(pCmd, cbCmd);
2285	return vmsvga3dDXDrawAuto(pThisCC, idDXContext);
2286	#else
2287	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2288	return VERR_NOT_SUPPORTED;
2289	#endif
2290	}
2291
2292
2293	/* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT 1157 */
2294	static int vmsvga3dCmdDXSetInputLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetInputLayout const *pCmd, uint32_t cbCmd)
2295	{
2296	#ifdef VMSVGA3D_DX
2297	//DEBUG_BREAKPOINT_TEST();
2298	RT_NOREF(cbCmd);
2299	return vmsvga3dDXSetInputLayout(pThisCC, idDXContext, pCmd->elementLayoutId);
2300	#else
2301	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2302	return VERR_NOT_SUPPORTED;
2303	#endif
2304	}
2305
2306
2307	/* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS 1158 */
2308	static int vmsvga3dCmdDXSetVertexBuffers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVertexBuffers const *pCmd, uint32_t cbCmd)
2309	{
2310	#ifdef VMSVGA3D_DX
2311	//DEBUG_BREAKPOINT_TEST();
2312	SVGA3dVertexBuffer const paVertexBuffer = (SVGA3dVertexBuffer )&pCmd[1];
2313	uint32_t const cVertexBuffer = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dVertexBuffer);
2314	return vmsvga3dDXSetVertexBuffers(pThisCC, idDXContext, pCmd->startBuffer, cVertexBuffer, paVertexBuffer);
2315	#else
2316	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2317	return VERR_NOT_SUPPORTED;
2318	#endif
2319	}
2320
2321
2322	/* SVGA_3D_CMD_DX_SET_INDEX_BUFFER 1159 */
2323	static int vmsvga3dCmdDXSetIndexBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetIndexBuffer const *pCmd, uint32_t cbCmd)
2324	{
2325	#ifdef VMSVGA3D_DX
2326	//DEBUG_BREAKPOINT_TEST();
2327	RT_NOREF(cbCmd);
2328	return vmsvga3dDXSetIndexBuffer(pThisCC, idDXContext, pCmd);
2329	#else
2330	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2331	return VERR_NOT_SUPPORTED;
2332	#endif
2333	}
2334
2335
2336	/* SVGA_3D_CMD_DX_SET_TOPOLOGY 1160 */
2337	static int vmsvga3dCmdDXSetTopology(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetTopology const *pCmd, uint32_t cbCmd)
2338	{
2339	#ifdef VMSVGA3D_DX
2340	//DEBUG_BREAKPOINT_TEST();
2341	RT_NOREF(cbCmd);
2342	return vmsvga3dDXSetTopology(pThisCC, idDXContext, pCmd->topology);
2343	#else
2344	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2345	return VERR_NOT_SUPPORTED;
2346	#endif
2347	}
2348
2349
2350	/* SVGA_3D_CMD_DX_SET_RENDERTARGETS 1161 */
2351	static int vmsvga3dCmdDXSetRenderTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRenderTargets const *pCmd, uint32_t cbCmd)
2352	{
2353	#ifdef VMSVGA3D_DX
2354	//DEBUG_BREAKPOINT_TEST();
2355	SVGA3dRenderTargetViewId const paRenderTargetViewId = (SVGA3dRenderTargetViewId )&pCmd[1];
2356	uint32_t const cRenderTargetViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderTargetViewId);
2357	return vmsvga3dDXSetRenderTargets(pThisCC, idDXContext, pCmd->depthStencilViewId, cRenderTargetViewId, paRenderTargetViewId);
2358	#else
2359	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2360	return VERR_NOT_SUPPORTED;
2361	#endif
2362	}
2363
2364
2365	/* SVGA_3D_CMD_DX_SET_BLEND_STATE 1162 */
2366	static int vmsvga3dCmdDXSetBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetBlendState const *pCmd, uint32_t cbCmd)
2367	{
2368	#ifdef VMSVGA3D_DX
2369	//DEBUG_BREAKPOINT_TEST();
2370	RT_NOREF(cbCmd);
2371	return vmsvga3dDXSetBlendState(pThisCC, idDXContext, pCmd);
2372	#else
2373	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2374	return VERR_NOT_SUPPORTED;
2375	#endif
2376	}
2377
2378
2379	/* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE 1163 */
2380	static int vmsvga3dCmdDXSetDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDepthStencilState const *pCmd, uint32_t cbCmd)
2381	{
2382	#ifdef VMSVGA3D_DX
2383	//DEBUG_BREAKPOINT_TEST();
2384	RT_NOREF(cbCmd);
2385	return vmsvga3dDXSetDepthStencilState(pThisCC, idDXContext, pCmd);
2386	#else
2387	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2388	return VERR_NOT_SUPPORTED;
2389	#endif
2390	}
2391
2392
2393	/* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE 1164 */
2394	static int vmsvga3dCmdDXSetRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRasterizerState const *pCmd, uint32_t cbCmd)
2395	{
2396	#ifdef VMSVGA3D_DX
2397	//DEBUG_BREAKPOINT_TEST();
2398	RT_NOREF(cbCmd);
2399	return vmsvga3dDXSetRasterizerState(pThisCC, idDXContext, pCmd->rasterizerId);
2400	#else
2401	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2402	return VERR_NOT_SUPPORTED;
2403	#endif
2404	}
2405
2406
2407	/* SVGA_3D_CMD_DX_DEFINE_QUERY 1165 */
2408	static int vmsvga3dCmdDXDefineQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineQuery const *pCmd, uint32_t cbCmd)
2409	{
2410	#ifdef VMSVGA3D_DX
2411	//DEBUG_BREAKPOINT_TEST();
2412	RT_NOREF(cbCmd);
2413	return vmsvga3dDXDefineQuery(pThisCC, idDXContext, pCmd);
2414	#else
2415	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2416	return VERR_NOT_SUPPORTED;
2417	#endif
2418	}
2419
2420
2421	/* SVGA_3D_CMD_DX_DESTROY_QUERY 1166 */
2422	static int vmsvga3dCmdDXDestroyQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyQuery const *pCmd, uint32_t cbCmd)
2423	{
2424	#ifdef VMSVGA3D_DX
2425	//DEBUG_BREAKPOINT_TEST();
2426	RT_NOREF(cbCmd);
2427	return vmsvga3dDXDestroyQuery(pThisCC, idDXContext, pCmd);
2428	#else
2429	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2430	return VERR_NOT_SUPPORTED;
2431	#endif
2432	}
2433
2434
2435	/* SVGA_3D_CMD_DX_BIND_QUERY 1167 */
2436	static int vmsvga3dCmdDXBindQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindQuery const *pCmd, uint32_t cbCmd)
2437	{
2438	#ifdef VMSVGA3D_DX
2439	//DEBUG_BREAKPOINT_TEST();
2440	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2441	RT_NOREF(cbCmd);
2442	/* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
2443	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2444	return vmsvga3dDXBindQuery(pThisCC, idDXContext, pCmd, pMob);
2445	#else
2446	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2447	return VERR_NOT_SUPPORTED;
2448	#endif
2449	}
2450
2451
2452	/* SVGA_3D_CMD_DX_SET_QUERY_OFFSET 1168 */
2453	static int vmsvga3dCmdDXSetQueryOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetQueryOffset const *pCmd, uint32_t cbCmd)
2454	{
2455	#ifdef VMSVGA3D_DX
2456	//DEBUG_BREAKPOINT_TEST();
2457	RT_NOREF(cbCmd);
2458	return vmsvga3dDXSetQueryOffset(pThisCC, idDXContext, pCmd);
2459	#else
2460	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2461	return VERR_NOT_SUPPORTED;
2462	#endif
2463	}
2464
2465
2466	/* SVGA_3D_CMD_DX_BEGIN_QUERY 1169 */
2467	static int vmsvga3dCmdDXBeginQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBeginQuery const *pCmd, uint32_t cbCmd)
2468	{
2469	#ifdef VMSVGA3D_DX
2470	//DEBUG_BREAKPOINT_TEST();
2471	RT_NOREF(cbCmd);
2472	return vmsvga3dDXBeginQuery(pThisCC, idDXContext, pCmd);
2473	#else
2474	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2475	return VERR_NOT_SUPPORTED;
2476	#endif
2477	}
2478
2479
2480	/* SVGA_3D_CMD_DX_END_QUERY 1170 */
2481	static int vmsvga3dCmdDXEndQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXEndQuery const *pCmd, uint32_t cbCmd)
2482	{
2483	#ifdef VMSVGA3D_DX
2484	//DEBUG_BREAKPOINT_TEST();
2485	RT_NOREF(cbCmd);
2486	return vmsvga3dDXEndQuery(pThisCC, idDXContext, pCmd);
2487	#else
2488	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2489	return VERR_NOT_SUPPORTED;
2490	#endif
2491	}
2492
2493
2494	/* SVGA_3D_CMD_DX_READBACK_QUERY 1171 */
2495	static int vmsvga3dCmdDXReadbackQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackQuery const *pCmd, uint32_t cbCmd)
2496	{
2497	#ifdef VMSVGA3D_DX
2498	//DEBUG_BREAKPOINT_TEST();
2499	RT_NOREF(cbCmd);
2500	return vmsvga3dDXReadbackQuery(pThisCC, idDXContext, pCmd);
2501	#else
2502	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2503	return VERR_NOT_SUPPORTED;
2504	#endif
2505	}
2506
2507
2508	/* SVGA_3D_CMD_DX_SET_PREDICATION 1172 */
2509	static int vmsvga3dCmdDXSetPredication(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPredication const *pCmd, uint32_t cbCmd)
2510	{
2511	#ifdef VMSVGA3D_DX
2512	//DEBUG_BREAKPOINT_TEST();
2513	RT_NOREF(cbCmd);
2514	return vmsvga3dDXSetPredication(pThisCC, idDXContext, pCmd);
2515	#else
2516	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2517	return VERR_NOT_SUPPORTED;
2518	#endif
2519	}
2520
2521
2522	/* SVGA_3D_CMD_DX_SET_SOTARGETS 1173 */
2523	static int vmsvga3dCmdDXSetSOTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSOTargets const *pCmd, uint32_t cbCmd)
2524	{
2525	#ifdef VMSVGA3D_DX
2526	//DEBUG_BREAKPOINT_TEST();
2527	SVGA3dSoTarget const paSoTarget = (SVGA3dSoTarget )&pCmd[1];
2528	uint32_t const cSoTarget = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSoTarget);
2529	return vmsvga3dDXSetSOTargets(pThisCC, idDXContext, cSoTarget, paSoTarget);
2530	#else
2531	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2532	return VERR_NOT_SUPPORTED;
2533	#endif
2534	}
2535
2536
2537	/* SVGA_3D_CMD_DX_SET_VIEWPORTS 1174 */
2538	static int vmsvga3dCmdDXSetViewports(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetViewports const *pCmd, uint32_t cbCmd)
2539	{
2540	#ifdef VMSVGA3D_DX
2541	//DEBUG_BREAKPOINT_TEST();
2542	SVGA3dViewport const paViewport = (SVGA3dViewport )&pCmd[1];
2543	uint32_t const cViewport = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dViewport);
2544	return vmsvga3dDXSetViewports(pThisCC, idDXContext, cViewport, paViewport);
2545	#else
2546	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2547	return VERR_NOT_SUPPORTED;
2548	#endif
2549	}
2550
2551
2552	/* SVGA_3D_CMD_DX_SET_SCISSORRECTS 1175 */
2553	static int vmsvga3dCmdDXSetScissorRects(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetScissorRects const *pCmd, uint32_t cbCmd)
2554	{
2555	#ifdef VMSVGA3D_DX
2556	//DEBUG_BREAKPOINT_TEST();
2557	SVGASignedRect const paRect = (SVGASignedRect )&pCmd[1];
2558	uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
2559	return vmsvga3dDXSetScissorRects(pThisCC, idDXContext, cRect, paRect);
2560	#else
2561	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2562	return VERR_NOT_SUPPORTED;
2563	#endif
2564	}
2565
2566
2567	/* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW 1176 */
2568	static int vmsvga3dCmdDXClearRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearRenderTargetView const *pCmd, uint32_t cbCmd)
2569	{
2570	#ifdef VMSVGA3D_DX
2571	//DEBUG_BREAKPOINT_TEST();
2572	RT_NOREF(cbCmd);
2573	return vmsvga3dDXClearRenderTargetView(pThisCC, idDXContext, pCmd);
2574	#else
2575	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2576	return VERR_NOT_SUPPORTED;
2577	#endif
2578	}
2579
2580
2581	/* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW 1177 */
2582	static int vmsvga3dCmdDXClearDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearDepthStencilView const *pCmd, uint32_t cbCmd)
2583	{
2584	#ifdef VMSVGA3D_DX
2585	//DEBUG_BREAKPOINT_TEST();
2586	RT_NOREF(cbCmd);
2587	return vmsvga3dDXClearDepthStencilView(pThisCC, idDXContext, pCmd);
2588	#else
2589	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2590	return VERR_NOT_SUPPORTED;
2591	#endif
2592	}
2593
2594
2595	/* SVGA_3D_CMD_DX_PRED_COPY_REGION 1178 */
2596	static int vmsvga3dCmdDXPredCopyRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopyRegion const *pCmd, uint32_t cbCmd)
2597	{
2598	#ifdef VMSVGA3D_DX
2599	//DEBUG_BREAKPOINT_TEST();
2600	RT_NOREF(cbCmd);
2601	return vmsvga3dDXPredCopyRegion(pThisCC, idDXContext, pCmd);
2602	#else
2603	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2604	return VERR_NOT_SUPPORTED;
2605	#endif
2606	}
2607
2608
2609	/* SVGA_3D_CMD_DX_PRED_COPY 1179 */
2610	static int vmsvga3dCmdDXPredCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopy const *pCmd, uint32_t cbCmd)
2611	{
2612	#ifdef VMSVGA3D_DX
2613	//DEBUG_BREAKPOINT_TEST();
2614	RT_NOREF(cbCmd);
2615	return vmsvga3dDXPredCopy(pThisCC, idDXContext, pCmd);
2616	#else
2617	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2618	return VERR_NOT_SUPPORTED;
2619	#endif
2620	}
2621
2622
2623	/* SVGA_3D_CMD_DX_PRESENTBLT 1180 */
2624	static int vmsvga3dCmdDXPresentBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPresentBlt const *pCmd, uint32_t cbCmd)
2625	{
2626	#ifdef VMSVGA3D_DX
2627	//DEBUG_BREAKPOINT_TEST();
2628	RT_NOREF(cbCmd);
2629	return vmsvga3dDXPresentBlt(pThisCC, idDXContext, pCmd);
2630	#else
2631	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2632	return VERR_NOT_SUPPORTED;
2633	#endif
2634	}
2635
2636
2637	/* SVGA_3D_CMD_DX_GENMIPS 1181 */
2638	static int vmsvga3dCmdDXGenMips(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGenMips const *pCmd, uint32_t cbCmd)
2639	{
2640	#ifdef VMSVGA3D_DX
2641	//DEBUG_BREAKPOINT_TEST();
2642	RT_NOREF(cbCmd);
2643	return vmsvga3dDXGenMips(pThisCC, idDXContext, pCmd);
2644	#else
2645	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2646	return VERR_NOT_SUPPORTED;
2647	#endif
2648	}
2649
2650
2651	/* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE 1182 */
2652	static int vmsvga3dCmdDXUpdateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXUpdateSubResource const *pCmd, uint32_t cbCmd)
2653	{
2654	#ifdef VMSVGA3D_DX
2655	//DEBUG_BREAKPOINT_TEST();
2656	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2657	RT_NOREF(cbCmd);
2658
2659	LogFlowFunc(("sid=%u, subResource=%u, box=%d,%d,%d %ux%ux%u\n",
2660	pCmd->sid, pCmd->subResource, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
2661
2662	/* "Inform the device that the guest-contents have been updated." */
2663	SVGAOTableSurfaceEntry entrySurface;
2664	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2665	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2666	if (RT_SUCCESS(rc))
2667	{
2668	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2669	if (pMob)
2670	{
2671	uint32 const cSubresource = vmsvga3dGetSubresourceCount(pThisCC, pCmd->sid);
2672	ASSERT_GUEST_RETURN(pCmd->subResource < cSubresource, VERR_INVALID_PARAMETER);
2673	/* pCmd->box will be verified by the mapping function. */
2674	RT_UNTRUSTED_VALIDATED_FENCE();
2675
2676	/** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2677	SVGA3dSurfaceImageId image;
2678	image.sid = pCmd->sid;
2679	vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2680
2681	rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
2682	AssertRC(rc);
2683	}
2684	}
2685
2686	return rc;
2687	#else
2688	RT_NOREF(pThisCC, pCmd, cbCmd);
2689	return VERR_NOT_SUPPORTED;
2690	#endif
2691	}
2692
2693
2694	/* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE 1183 */
2695	static int vmsvga3dCmdDXReadbackSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackSubResource const *pCmd, uint32_t cbCmd)
2696	{
2697	#ifdef VMSVGA3D_DX
2698	//DEBUG_BREAKPOINT_TEST();
2699	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2700	RT_NOREF(cbCmd);
2701
2702	LogFlowFunc(("sid=%u, subResource=%u\n",
2703	pCmd->sid, pCmd->subResource));
2704
2705	/* "Request the device to flush the dirty contents into the guest." */
2706	SVGAOTableSurfaceEntry entrySurface;
2707	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2708	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2709	if (RT_SUCCESS(rc))
2710	{
2711	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2712	if (pMob)
2713	{
2714	uint32 const cSubresource = vmsvga3dGetSubresourceCount(pThisCC, pCmd->sid);
2715	ASSERT_GUEST_RETURN(pCmd->subResource < cSubresource, VERR_INVALID_PARAMETER);
2716	RT_UNTRUSTED_VALIDATED_FENCE();
2717
2718	/** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2719	SVGA3dSurfaceImageId image;
2720	image.sid = pCmd->sid;
2721	vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2722
2723	rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
2724	AssertRC(rc);
2725	}
2726	}
2727
2728	return rc;
2729	#else
2730	RT_NOREF(pThisCC, pCmd, cbCmd);
2731	return VERR_NOT_SUPPORTED;
2732	#endif
2733	}
2734
2735
2736	/* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE 1184 */
2737	static int vmsvga3dCmdDXInvalidateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXInvalidateSubResource const *pCmd, uint32_t cbCmd)
2738	{
2739	#ifdef VMSVGA3D_DX
2740	DEBUG_BREAKPOINT_TEST();
2741	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2742	RT_NOREF(cbCmd);
2743
2744	LogFlowFunc(("sid=%u, subResource=%u\n",
2745	pCmd->sid, pCmd->subResource));
2746
2747	/* "Notify the device that the contents can be lost." */
2748	SVGAOTableSurfaceEntry entrySurface;
2749	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2750	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2751	if (RT_SUCCESS(rc))
2752	{
2753	uint32_t iFace;
2754	uint32_t iMipmap;
2755	vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &iMipmap, &iFace);
2756	vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, iFace, iMipmap);
2757	}
2758
2759	return rc;
2760	#else
2761	RT_NOREF(pThisCC, pCmd, cbCmd);
2762	return VERR_NOT_SUPPORTED;
2763	#endif
2764	}
2765
2766
2767	/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW 1185 */
2768	static int vmsvga3dCmdDXDefineShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShaderResourceView const *pCmd, uint32_t cbCmd)
2769	{
2770	#ifdef VMSVGA3D_DX
2771	//DEBUG_BREAKPOINT_TEST();
2772	RT_NOREF(cbCmd);
2773	return vmsvga3dDXDefineShaderResourceView(pThisCC, idDXContext, pCmd);
2774	#else
2775	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2776	return VERR_NOT_SUPPORTED;
2777	#endif
2778	}
2779
2780
2781	/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW 1186 */
2782	static int vmsvga3dCmdDXDestroyShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShaderResourceView const *pCmd, uint32_t cbCmd)
2783	{
2784	#ifdef VMSVGA3D_DX
2785	//DEBUG_BREAKPOINT_TEST();
2786	RT_NOREF(cbCmd);
2787	return vmsvga3dDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd);
2788	#else
2789	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2790	return VERR_NOT_SUPPORTED;
2791	#endif
2792	}
2793
2794
2795	/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW 1187 */
2796	static int vmsvga3dCmdDXDefineRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRenderTargetView const *pCmd, uint32_t cbCmd)
2797	{
2798	#ifdef VMSVGA3D_DX
2799	//DEBUG_BREAKPOINT_TEST();
2800	RT_NOREF(cbCmd);
2801	return vmsvga3dDXDefineRenderTargetView(pThisCC, idDXContext, pCmd);
2802	#else
2803	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2804	return VERR_NOT_SUPPORTED;
2805	#endif
2806	}
2807
2808
2809	/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW 1188 */
2810	static int vmsvga3dCmdDXDestroyRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRenderTargetView const *pCmd, uint32_t cbCmd)
2811	{
2812	#ifdef VMSVGA3D_DX
2813	//DEBUG_BREAKPOINT_TEST();
2814	RT_NOREF(cbCmd);
2815	return vmsvga3dDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd);
2816	#else
2817	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2818	return VERR_NOT_SUPPORTED;
2819	#endif
2820	}
2821
2822
2823	/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW 1189 */
2824	static int vmsvga3dCmdDXDefineDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView const *pCmd, uint32_t cbCmd)
2825	{
2826	#ifdef VMSVGA3D_DX
2827	//DEBUG_BREAKPOINT_TEST();
2828	RT_NOREF(cbCmd);
2829	SVGA3dCmdDXDefineDepthStencilView_v2 cmd;
2830	cmd.depthStencilViewId = pCmd->depthStencilViewId;
2831	cmd.sid = pCmd->sid;
2832	cmd.format = pCmd->format;
2833	cmd.resourceDimension = pCmd->resourceDimension;
2834	cmd.mipSlice = pCmd->mipSlice;
2835	cmd.firstArraySlice = pCmd->firstArraySlice;
2836	cmd.arraySize = pCmd->arraySize;
2837	cmd.flags = 0;
2838	return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, &cmd);
2839	#else
2840	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2841	return VERR_NOT_SUPPORTED;
2842	#endif
2843	}
2844
2845
2846	/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW 1190 */
2847	static int vmsvga3dCmdDXDestroyDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilView const *pCmd, uint32_t cbCmd)
2848	{
2849	#ifdef VMSVGA3D_DX
2850	//DEBUG_BREAKPOINT_TEST();
2851	RT_NOREF(cbCmd);
2852	return vmsvga3dDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd);
2853	#else
2854	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2855	return VERR_NOT_SUPPORTED;
2856	#endif
2857	}
2858
2859
2860	/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT 1191 */
2861	static int vmsvga3dCmdDXDefineElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineElementLayout const *pCmd, uint32_t cbCmd)
2862	{
2863	#ifdef VMSVGA3D_DX
2864	//DEBUG_BREAKPOINT_TEST();
2865	SVGA3dInputElementDesc const paDesc = (SVGA3dInputElementDesc )&pCmd[1];
2866	uint32_t const cDesc = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dInputElementDesc);
2867	return vmsvga3dDXDefineElementLayout(pThisCC, idDXContext, pCmd->elementLayoutId, cDesc, paDesc);
2868	#else
2869	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2870	return VERR_NOT_SUPPORTED;
2871	#endif
2872	}
2873
2874
2875	/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT 1192 */
2876	static int vmsvga3dCmdDXDestroyElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyElementLayout const *pCmd, uint32_t cbCmd)
2877	{
2878	#ifdef VMSVGA3D_DX
2879	//DEBUG_BREAKPOINT_TEST();
2880	RT_NOREF(cbCmd);
2881	return vmsvga3dDXDestroyElementLayout(pThisCC, idDXContext, pCmd);
2882	#else
2883	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2884	return VERR_NOT_SUPPORTED;
2885	#endif
2886	}
2887
2888
2889	/* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE 1193 */
2890	static int vmsvga3dCmdDXDefineBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineBlendState const *pCmd, uint32_t cbCmd)
2891	{
2892	#ifdef VMSVGA3D_DX
2893	//DEBUG_BREAKPOINT_TEST();
2894	RT_NOREF(cbCmd);
2895	return vmsvga3dDXDefineBlendState(pThisCC, idDXContext, pCmd);
2896	#else
2897	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2898	return VERR_NOT_SUPPORTED;
2899	#endif
2900	}
2901
2902
2903	/* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE 1194 */
2904	static int vmsvga3dCmdDXDestroyBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyBlendState const *pCmd, uint32_t cbCmd)
2905	{
2906	#ifdef VMSVGA3D_DX
2907	//DEBUG_BREAKPOINT_TEST();
2908	RT_NOREF(cbCmd);
2909	return vmsvga3dDXDestroyBlendState(pThisCC, idDXContext, pCmd);
2910	#else
2911	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2912	return VERR_NOT_SUPPORTED;
2913	#endif
2914	}
2915
2916
2917	/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE 1195 */
2918	static int vmsvga3dCmdDXDefineDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilState const *pCmd, uint32_t cbCmd)
2919	{
2920	#ifdef VMSVGA3D_DX
2921	//DEBUG_BREAKPOINT_TEST();
2922	RT_NOREF(cbCmd);
2923	return vmsvga3dDXDefineDepthStencilState(pThisCC, idDXContext, pCmd);
2924	#else
2925	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2926	return VERR_NOT_SUPPORTED;
2927	#endif
2928	}
2929
2930
2931	/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE 1196 */
2932	static int vmsvga3dCmdDXDestroyDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilState const *pCmd, uint32_t cbCmd)
2933	{
2934	#ifdef VMSVGA3D_DX
2935	//DEBUG_BREAKPOINT_TEST();
2936	RT_NOREF(cbCmd);
2937	return vmsvga3dDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd);
2938	#else
2939	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2940	return VERR_NOT_SUPPORTED;
2941	#endif
2942	}
2943
2944
2945	/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE 1197 */
2946	static int vmsvga3dCmdDXDefineRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRasterizerState const *pCmd, uint32_t cbCmd)
2947	{
2948	#ifdef VMSVGA3D_DX
2949	//DEBUG_BREAKPOINT_TEST();
2950	RT_NOREF(cbCmd);
2951	return vmsvga3dDXDefineRasterizerState(pThisCC, idDXContext, pCmd);
2952	#else
2953	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2954	return VERR_NOT_SUPPORTED;
2955	#endif
2956	}
2957
2958
2959	/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE 1198 */
2960	static int vmsvga3dCmdDXDestroyRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRasterizerState const *pCmd, uint32_t cbCmd)
2961	{
2962	#ifdef VMSVGA3D_DX
2963	//DEBUG_BREAKPOINT_TEST();
2964	RT_NOREF(cbCmd);
2965	return vmsvga3dDXDestroyRasterizerState(pThisCC, idDXContext, pCmd);
2966	#else
2967	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2968	return VERR_NOT_SUPPORTED;
2969	#endif
2970	}
2971
2972
2973	/* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE 1199 */
2974	static int vmsvga3dCmdDXDefineSamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineSamplerState const *pCmd, uint32_t cbCmd)
2975	{
2976	#ifdef VMSVGA3D_DX
2977	//DEBUG_BREAKPOINT_TEST();
2978	RT_NOREF(cbCmd);
2979	return vmsvga3dDXDefineSamplerState(pThisCC, idDXContext, pCmd);
2980	#else
2981	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2982	return VERR_NOT_SUPPORTED;
2983	#endif
2984	}
2985
2986
2987	/* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE 1200 */
2988	static int vmsvga3dCmdDXDestroySamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroySamplerState const *pCmd, uint32_t cbCmd)
2989	{
2990	#ifdef VMSVGA3D_DX
2991	//DEBUG_BREAKPOINT_TEST();
2992	RT_NOREF(cbCmd);
2993	return vmsvga3dDXDestroySamplerState(pThisCC, idDXContext, pCmd);
2994	#else
2995	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2996	return VERR_NOT_SUPPORTED;
2997	#endif
2998	}
2999
3000
3001	/* SVGA_3D_CMD_DX_DEFINE_SHADER 1201 */
3002	static int vmsvga3dCmdDXDefineShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShader const *pCmd, uint32_t cbCmd)
3003	{
3004	#ifdef VMSVGA3D_DX
3005	//DEBUG_BREAKPOINT_TEST();
3006	RT_NOREF(cbCmd);
3007	return vmsvga3dDXDefineShader(pThisCC, idDXContext, pCmd);
3008	#else
3009	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3010	return VERR_NOT_SUPPORTED;
3011	#endif
3012	}
3013
3014
3015	/* SVGA_3D_CMD_DX_DESTROY_SHADER 1202 */
3016	static int vmsvga3dCmdDXDestroyShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShader const *pCmd, uint32_t cbCmd)
3017	{
3018	#ifdef VMSVGA3D_DX
3019	//DEBUG_BREAKPOINT_TEST();
3020	RT_NOREF(cbCmd);
3021	return vmsvga3dDXDestroyShader(pThisCC, idDXContext, pCmd);
3022	#else
3023	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3024	return VERR_NOT_SUPPORTED;
3025	#endif
3026	}
3027
3028
3029	/* SVGA_3D_CMD_DX_BIND_SHADER 1203 */
3030	static int vmsvga3dCmdDXBindShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShader const *pCmd, uint32_t cbCmd)
3031	{
3032	#ifdef VMSVGA3D_DX
3033	//DEBUG_BREAKPOINT_TEST();
3034	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3035	RT_NOREF(idDXContext, cbCmd);
3036	/* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3037	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3038	return vmsvga3dDXBindShader(pThisCC, pCmd, pMob);
3039	#else
3040	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3041	return VERR_NOT_SUPPORTED;
3042	#endif
3043	}
3044
3045
3046	/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT 1204 */
3047	static int vmsvga3dCmdDXDefineStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutput const *pCmd, uint32_t cbCmd)
3048	{
3049	#ifdef VMSVGA3D_DX
3050	//DEBUG_BREAKPOINT_TEST();
3051	RT_NOREF(cbCmd);
3052	return vmsvga3dDXDefineStreamOutput(pThisCC, idDXContext, pCmd);
3053	#else
3054	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3055	return VERR_NOT_SUPPORTED;
3056	#endif
3057	}
3058
3059
3060	/* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT 1205 */
3061	static int vmsvga3dCmdDXDestroyStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyStreamOutput const *pCmd, uint32_t cbCmd)
3062	{
3063	#ifdef VMSVGA3D_DX
3064	//DEBUG_BREAKPOINT_TEST();
3065	RT_NOREF(cbCmd);
3066	return vmsvga3dDXDestroyStreamOutput(pThisCC, idDXContext, pCmd);
3067	#else
3068	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3069	return VERR_NOT_SUPPORTED;
3070	#endif
3071	}
3072
3073
3074	/* SVGA_3D_CMD_DX_SET_STREAMOUTPUT 1206 */
3075	static int vmsvga3dCmdDXSetStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStreamOutput const *pCmd, uint32_t cbCmd)
3076	{
3077	#ifdef VMSVGA3D_DX
3078	//DEBUG_BREAKPOINT_TEST();
3079	RT_NOREF(cbCmd);
3080	return vmsvga3dDXSetStreamOutput(pThisCC, idDXContext, pCmd);
3081	#else
3082	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3083	return VERR_NOT_SUPPORTED;
3084	#endif
3085	}
3086
3087
3088	/* SVGA_3D_CMD_DX_SET_COTABLE 1207 */
3089	static int vmsvga3dCmdDXSetCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXSetCOTable const *pCmd, uint32_t cbCmd)
3090	{
3091	#ifdef VMSVGA3D_DX
3092	//DEBUG_BREAKPOINT_TEST();
3093	RT_NOREF(cbCmd);
3094	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3095	/* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3096	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3097	return vmsvga3dDXSetCOTable(pThisCC, pCmd, pMob);
3098	#else
3099	RT_NOREF(pThisCC, pCmd, cbCmd);
3100	return VERR_NOT_SUPPORTED;
3101	#endif
3102	}
3103
3104
3105	/* SVGA_3D_CMD_DX_READBACK_COTABLE 1208 */
3106	static int vmsvga3dCmdDXReadbackCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackCOTable const *pCmd, uint32_t cbCmd)
3107	{
3108	#ifdef VMSVGA3D_DX
3109	//DEBUG_BREAKPOINT_TEST();
3110	RT_NOREF(idDXContext, cbCmd);
3111	return vmsvga3dDXReadbackCOTable(pThisCC, pCmd);
3112	#else
3113	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3114	return VERR_NOT_SUPPORTED;
3115	#endif
3116	}
3117
3118
3119	/* SVGA_3D_CMD_DX_BUFFER_COPY 1209 */
3120	static int vmsvga3dCmdDXBufferCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferCopy const *pCmd, uint32_t cbCmd)
3121	{
3122	#ifdef VMSVGA3D_DX
3123	//DEBUG_BREAKPOINT_TEST();
3124	RT_NOREF(idDXContext, cbCmd);
3125
3126	int rc;
3127
3128	/** @todo Backend should o the copy is both buffers have a hardware resource. */
3129	SVGA3dSurfaceImageId imageBufferSrc;
3130	imageBufferSrc.sid = pCmd->src;
3131	imageBufferSrc.face = 0;
3132	imageBufferSrc.mipmap = 0;
3133
3134	SVGA3dSurfaceImageId imageBufferDest;
3135	imageBufferDest.sid = pCmd->dest;
3136	imageBufferDest.face = 0;
3137	imageBufferDest.mipmap = 0;
3138
3139	/*
3140	* Map the source buffer.
3141	*/
3142	VMSVGA3D_MAPPED_SURFACE mapBufferSrc;
3143	rc = vmsvga3dSurfaceMap(pThisCC, &imageBufferSrc, NULL, VMSVGA3D_SURFACE_MAP_READ, &mapBufferSrc);
3144	if (RT_SUCCESS(rc))
3145	{
3146	/*
3147	* Map the destination buffer.
3148	*/
3149	VMSVGA3D_MAPPED_SURFACE mapBufferDest;
3150	rc = vmsvga3dSurfaceMap(pThisCC, &imageBufferDest, NULL, VMSVGA3D_SURFACE_MAP_WRITE, &mapBufferDest);
3151	if (RT_SUCCESS(rc))
3152	{
3153	/*
3154	* Copy the source buffer to the destination.
3155	*/
3156	uint8_t const pu8BufferSrc = (uint8_t )mapBufferSrc.pvData;
3157	uint32_t const cbBufferSrc = mapBufferSrc.cbRow;
3158
3159	uint8_t pu8BufferDest = (uint8_t )mapBufferDest.pvData;
3160	uint32_t const cbBufferDest = mapBufferDest.cbRow;
3161
3162	if ( pCmd->srcX < cbBufferSrc
3163	&& pCmd->width <= cbBufferSrc- pCmd->srcX
3164	&& pCmd->destX < cbBufferDest
3165	&& pCmd->width <= cbBufferDest - pCmd->destX)
3166	{
3167	RT_UNTRUSTED_VALIDATED_FENCE();
3168
3169	memcpy(&pu8BufferDest[pCmd->destX], &pu8BufferSrc[pCmd->srcX], pCmd->width);
3170	}
3171	else
3172	ASSERT_GUEST_FAILED_STMT(rc = VERR_INVALID_PARAMETER);
3173
3174	vmsvga3dSurfaceUnmap(pThisCC, &imageBufferDest, &mapBufferDest, true);
3175	}
3176
3177	vmsvga3dSurfaceUnmap(pThisCC, &imageBufferSrc, &mapBufferSrc, false);
3178	}
3179
3180	return rc;
3181	#else
3182	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3183	return VERR_NOT_SUPPORTED;
3184	#endif
3185	}
3186
3187
3188	/* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER 1210 */
3189	static int vmsvga3dCmdDXTransferFromBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXTransferFromBuffer const *pCmd, uint32_t cbCmd)
3190	{
3191	#ifdef VMSVGA3D_DX
3192	//DEBUG_BREAKPOINT_TEST();
3193	RT_NOREF(cbCmd);
3194
3195	/* Plan:
3196	* - map the buffer;
3197	* - map the surface;
3198	* - copy from buffer map to the surface map.
3199	*/
3200
3201	int rc;
3202
3203	SVGA3dSurfaceImageId imageBuffer;
3204	imageBuffer.sid = pCmd->srcSid;
3205	imageBuffer.face = 0;
3206	imageBuffer.mipmap = 0;
3207
3208	SVGA3dSurfaceImageId imageSurface;
3209	imageSurface.sid = pCmd->destSid;
3210	rc = vmsvga3dCalcSurfaceMipmapAndFace(pThisCC, pCmd->destSid, pCmd->destSubResource, &imageSurface.mipmap, &imageSurface.face);
3211	AssertRCReturn(rc, rc);
3212
3213	/*
3214	* Map the buffer.
3215	*/
3216	VMSVGA3D_MAPPED_SURFACE mapBuffer;
3217	rc = vmsvga3dSurfaceMap(pThisCC, &imageBuffer, NULL, VMSVGA3D_SURFACE_MAP_READ, &mapBuffer);
3218	if (RT_SUCCESS(rc))
3219	{
3220	/*
3221	* Map the surface.
3222	*/
3223	VMSVGA3D_MAPPED_SURFACE mapSurface;
3224	rc = vmsvga3dSurfaceMap(pThisCC, &imageSurface, &pCmd->destBox, VMSVGA3D_SURFACE_MAP_WRITE, &mapSurface);
3225	if (RT_SUCCESS(rc))
3226	{
3227	/*
3228	* Copy the mapped buffer to the surface. "Raw byte wise transfer"
3229	*/
3230	uint8_t const pu8Buffer = (uint8_t )mapBuffer.pvData;
3231	uint32_t const cbBuffer = mapBuffer.cbRow;
3232
3233	if (pCmd->srcOffset <= cbBuffer)
3234	{
3235	RT_UNTRUSTED_VALIDATED_FENCE();
3236	uint8_t const *pu8BufferBegin = pu8Buffer;
3237	uint8_t const *pu8BufferEnd = pu8Buffer + cbBuffer;
3238
3239	pu8Buffer += pCmd->srcOffset;
3240
3241	uint8_t pu8Surface = (uint8_t )mapSurface.pvData;
3242
3243	uint32_t const cbRowCopy = RT_MIN(pCmd->srcPitch, mapSurface.cbRow);
3244	for (uint32_t z = 0; z < mapSurface.box.d && RT_SUCCESS(rc); ++z)
3245	{
3246	uint8_t const *pu8BufferRow = pu8Buffer;
3247	uint8_t *pu8SurfaceRow = pu8Surface;
3248	for (uint32_t iRow = 0; iRow < mapSurface.cRows; ++iRow)
3249	{
3250	ASSERT_GUEST_STMT_BREAK( (uintptr_t)pu8BufferRow >= (uintptr_t)pu8BufferBegin
3251	&& (uintptr_t)pu8BufferRow < (uintptr_t)pu8BufferEnd
3252	&& (uintptr_t)pu8BufferRow < (uintptr_t)(pu8BufferRow + cbRowCopy)
3253	&& (uintptr_t)(pu8BufferRow + cbRowCopy) > (uintptr_t)pu8BufferBegin
3254	&& (uintptr_t)(pu8BufferRow + cbRowCopy) <= (uintptr_t)pu8BufferEnd,
3255	rc = VERR_INVALID_PARAMETER);
3256
3257	memcpy(pu8SurfaceRow, pu8BufferRow, cbRowCopy);
3258
3259	pu8SurfaceRow += mapSurface.cbRowPitch;
3260	pu8BufferRow += pCmd->srcPitch;
3261	}
3262
3263	pu8Buffer += pCmd->srcSlicePitch;
3264	pu8Surface += mapSurface.cbDepthPitch;
3265	}
3266	}
3267	else
3268	ASSERT_GUEST_FAILED_STMT(rc = VERR_INVALID_PARAMETER);
3269
3270	vmsvga3dSurfaceUnmap(pThisCC, &imageSurface, &mapSurface, true);
3271	}
3272
3273	vmsvga3dSurfaceUnmap(pThisCC, &imageBuffer, &mapBuffer, false);
3274	}
3275
3276	return rc;
3277	#else
3278	RT_NOREF(pThisCC, pCmd, cbCmd);
3279	return VERR_NOT_SUPPORTED;
3280	#endif
3281	}
3282
3283
3284	/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK 1211 */
3285	static int vmsvga3dCmdDXSurfaceCopyAndReadback(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSurfaceCopyAndReadback const *pCmd, uint32_t cbCmd)
3286	{
3287	#ifdef VMSVGA3D_DX
3288	DEBUG_BREAKPOINT_TEST();
3289	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3290	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3291	return vmsvga3dDXSurfaceCopyAndReadback(pThisCC, idDXContext);
3292	#else
3293	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3294	return VERR_NOT_SUPPORTED;
3295	#endif
3296	}
3297
3298
3299	/* SVGA_3D_CMD_DX_MOVE_QUERY 1212 */
3300	static int vmsvga3dCmdDXMoveQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMoveQuery const *pCmd, uint32_t cbCmd)
3301	{
3302	#ifdef VMSVGA3D_DX
3303	DEBUG_BREAKPOINT_TEST();
3304	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3305	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3306	return vmsvga3dDXMoveQuery(pThisCC, idDXContext);
3307	#else
3308	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3309	return VERR_NOT_SUPPORTED;
3310	#endif
3311	}
3312
3313
3314	/* SVGA_3D_CMD_DX_BIND_ALL_QUERY 1213 */
3315	static int vmsvga3dCmdDXBindAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllQuery const *pCmd, uint32_t cbCmd)
3316	{
3317	#ifdef VMSVGA3D_DX
3318	//DEBUG_BREAKPOINT_TEST();
3319	RT_NOREF(cbCmd);
3320	return vmsvga3dDXBindAllQuery(pThisCC, idDXContext, pCmd);
3321	#else
3322	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3323	return VERR_NOT_SUPPORTED;
3324	#endif
3325	}
3326
3327
3328	/* SVGA_3D_CMD_DX_READBACK_ALL_QUERY 1214 */
3329	static int vmsvga3dCmdDXReadbackAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackAllQuery const *pCmd, uint32_t cbCmd)
3330	{
3331	#ifdef VMSVGA3D_DX
3332	//DEBUG_BREAKPOINT_TEST();
3333	RT_NOREF(cbCmd);
3334	return vmsvga3dDXReadbackAllQuery(pThisCC, idDXContext, pCmd);
3335	#else
3336	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3337	return VERR_NOT_SUPPORTED;
3338	#endif
3339	}
3340
3341
3342	/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER 1215 */
3343	static int vmsvga3dCmdDXPredTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredTransferFromBuffer const *pCmd, uint32_t cbCmd)
3344	{
3345	#ifdef VMSVGA3D_DX
3346	//DEBUG_BREAKPOINT_TEST();
3347	RT_NOREF(idDXContext, cbCmd);
3348
3349	/* This command is executed in a context: "The context is implied from the command buffer header."
3350	* However the device design allows to do the transfer without a context, so re-use context-less command handler.
3351	*/
3352	SVGA3dCmdDXTransferFromBuffer cmd;
3353	cmd.srcSid = pCmd->srcSid;
3354	cmd.srcOffset = pCmd->srcOffset;
3355	cmd.srcPitch = pCmd->srcPitch;
3356	cmd.srcSlicePitch = pCmd->srcSlicePitch;
3357	cmd.destSid = pCmd->destSid;
3358	cmd.destSubResource = pCmd->destSubResource;
3359	cmd.destBox = pCmd->destBox;
3360	return vmsvga3dCmdDXTransferFromBuffer(pThisCC, &cmd, sizeof(cmd));
3361	#else
3362	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3363	return VERR_NOT_SUPPORTED;
3364	#endif
3365	}
3366
3367
3368	/* SVGA_3D_CMD_DX_MOB_FENCE_64 1216 */
3369	static int vmsvga3dCmdDXMobFence64(PVGASTATECC pThisCC, SVGA3dCmdDXMobFence64 const *pCmd, uint32_t cbCmd)
3370	{
3371	#ifdef VMSVGA3D_DX
3372	//DEBUG_BREAKPOINT_TEST();
3373	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3374	RT_NOREF(cbCmd);
3375
3376	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobId);
3377	ASSERT_GUEST_RETURN(pMob, VERR_INVALID_PARAMETER);
3378
3379	int rc = vmsvgaR3MobWrite(pSvgaR3State, pMob, pCmd->mobOffset, &pCmd->value, sizeof(pCmd->value));
3380	ASSERT_GUEST_RETURN(RT_SUCCESS(rc), rc);
3381
3382	return VINF_SUCCESS;
3383	#else
3384	RT_NOREF(pThisCC, pCmd, cbCmd);
3385	return VERR_NOT_SUPPORTED;
3386	#endif
3387	}
3388
3389
3390	/* SVGA_3D_CMD_DX_BIND_ALL_SHADER 1217 */
3391	static int vmsvga3dCmdDXBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllShader const *pCmd, uint32_t cbCmd)
3392	{
3393	#ifdef VMSVGA3D_DX
3394	DEBUG_BREAKPOINT_TEST();
3395	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3396	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3397	return vmsvga3dDXBindAllShader(pThisCC, idDXContext);
3398	#else
3399	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3400	return VERR_NOT_SUPPORTED;
3401	#endif
3402	}
3403
3404
3405	/* SVGA_3D_CMD_DX_HINT 1218 */
3406	static int vmsvga3dCmdDXHint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXHint const *pCmd, uint32_t cbCmd)
3407	{
3408	#ifdef VMSVGA3D_DX
3409	DEBUG_BREAKPOINT_TEST();
3410	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3411	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3412	return vmsvga3dDXHint(pThisCC, idDXContext);
3413	#else
3414	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3415	return VERR_NOT_SUPPORTED;
3416	#endif
3417	}
3418
3419
3420	/* SVGA_3D_CMD_DX_BUFFER_UPDATE 1219 */
3421	static int vmsvga3dCmdDXBufferUpdate(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferUpdate const *pCmd, uint32_t cbCmd)
3422	{
3423	#ifdef VMSVGA3D_DX
3424	DEBUG_BREAKPOINT_TEST();
3425	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3426	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3427	return vmsvga3dDXBufferUpdate(pThisCC, idDXContext);
3428	#else
3429	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3430	return VERR_NOT_SUPPORTED;
3431	#endif
3432	}
3433
3434
3435	/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET 1220 */
3436	static int vmsvga3dCmdDXSetVSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3437	{
3438	#ifdef VMSVGA3D_DX
3439	DEBUG_BREAKPOINT_TEST();
3440	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3441	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3442	return vmsvga3dDXSetVSConstantBufferOffset(pThisCC, idDXContext);
3443	#else
3444	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3445	return VERR_NOT_SUPPORTED;
3446	#endif
3447	}
3448
3449
3450	/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET 1221 */
3451	static int vmsvga3dCmdDXSetPSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3452	{
3453	#ifdef VMSVGA3D_DX
3454	DEBUG_BREAKPOINT_TEST();
3455	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3456	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3457	return vmsvga3dDXSetPSConstantBufferOffset(pThisCC, idDXContext);
3458	#else
3459	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3460	return VERR_NOT_SUPPORTED;
3461	#endif
3462	}
3463
3464
3465	/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET 1222 */
3466	static int vmsvga3dCmdDXSetGSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetGSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3467	{
3468	#ifdef VMSVGA3D_DX
3469	DEBUG_BREAKPOINT_TEST();
3470	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3471	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3472	return vmsvga3dDXSetGSConstantBufferOffset(pThisCC, idDXContext);
3473	#else
3474	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3475	return VERR_NOT_SUPPORTED;
3476	#endif
3477	}
3478
3479
3480	/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET 1223 */
3481	static int vmsvga3dCmdDXSetHSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetHSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3482	{
3483	#ifdef VMSVGA3D_DX
3484	DEBUG_BREAKPOINT_TEST();
3485	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3486	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3487	return vmsvga3dDXSetHSConstantBufferOffset(pThisCC, idDXContext);
3488	#else
3489	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3490	return VERR_NOT_SUPPORTED;
3491	#endif
3492	}
3493
3494
3495	/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET 1224 */
3496	static int vmsvga3dCmdDXSetDSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3497	{
3498	#ifdef VMSVGA3D_DX
3499	DEBUG_BREAKPOINT_TEST();
3500	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3501	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3502	return vmsvga3dDXSetDSConstantBufferOffset(pThisCC, idDXContext);
3503	#else
3504	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3505	return VERR_NOT_SUPPORTED;
3506	#endif
3507	}
3508
3509
3510	/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET 1225 */
3511	static int vmsvga3dCmdDXSetCSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3512	{
3513	#ifdef VMSVGA3D_DX
3514	DEBUG_BREAKPOINT_TEST();
3515	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3516	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3517	return vmsvga3dDXSetCSConstantBufferOffset(pThisCC, idDXContext);
3518	#else
3519	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3520	return VERR_NOT_SUPPORTED;
3521	#endif
3522	}
3523
3524
3525	/* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER 1226 */
3526	static int vmsvga3dCmdDXCondBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCondBindAllShader const *pCmd, uint32_t cbCmd)
3527	{
3528	#ifdef VMSVGA3D_DX
3529	DEBUG_BREAKPOINT_TEST();
3530	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3531	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3532	return vmsvga3dDXCondBindAllShader(pThisCC, idDXContext);
3533	#else
3534	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3535	return VERR_NOT_SUPPORTED;
3536	#endif
3537	}
3538
3539
3540	/* SVGA_3D_CMD_SCREEN_COPY 1227 */
3541	static int vmsvga3dCmdScreenCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdScreenCopy const *pCmd, uint32_t cbCmd)
3542	{
3543	#ifdef VMSVGA3D_DX
3544	DEBUG_BREAKPOINT_TEST();
3545	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3546	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3547	return vmsvga3dScreenCopy(pThisCC, idDXContext);
3548	#else
3549	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3550	return VERR_NOT_SUPPORTED;
3551	#endif
3552	}
3553
3554
3555	/* SVGA_3D_CMD_GROW_OTABLE 1236 */
3556	static int vmsvga3dCmdGrowOTable(PVGASTATECC pThisCC, SVGA3dCmdGrowOTable const *pCmd, uint32_t cbCmd)
3557	{
3558	#ifdef VMSVGA3D_DX
3559	//DEBUG_BREAKPOINT_TEST();
3560	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3561	RT_NOREF(cbCmd);
3562	return vmsvgaR3OTableSetOrGrow(pSvgaR3State, pCmd->type, pCmd->baseAddress,
3563	pCmd->sizeInBytes, pCmd->validSizeInBytes, pCmd->ptDepth, /fGrow/ true);
3564	#else
3565	RT_NOREF(pThisCC, pCmd, cbCmd);
3566	return VERR_NOT_SUPPORTED;
3567	#endif
3568	}
3569
3570
3571	/* SVGA_3D_CMD_DX_GROW_COTABLE 1237 */
3572	static int vmsvga3dCmdDXGrowCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXGrowCOTable const *pCmd, uint32_t cbCmd)
3573	{
3574	#ifdef VMSVGA3D_DX
3575	//DEBUG_BREAKPOINT_TEST();
3576	RT_NOREF(cbCmd);
3577	return vmsvga3dDXGrowCOTable(pThisCC, pCmd);
3578	#else
3579	RT_NOREF(pThisCC, pCmd, cbCmd);
3580	return VERR_NOT_SUPPORTED;
3581	#endif
3582	}
3583
3584
3585	/* SVGA_3D_CMD_INTRA_SURFACE_COPY 1238 */
3586	static int vmsvga3dCmdIntraSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdIntraSurfaceCopy const *pCmd, uint32_t cbCmd)
3587	{
3588	#ifdef VMSVGA3D_DX
3589	DEBUG_BREAKPOINT_TEST();
3590	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3591	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3592	return vmsvga3dIntraSurfaceCopy(pThisCC, idDXContext);
3593	#else
3594	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3595	return VERR_NOT_SUPPORTED;
3596	#endif
3597	}
3598
3599
3600	/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 1239 */
3601	static int vmsvga3dCmdDefineGBSurface_v3(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v3 const *pCmd)
3602	{
3603	#ifdef VMSVGA3D_DX
3604	DEBUG_BREAKPOINT_TEST();
3605	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3606
3607	/* Update the entry in the pSvgaR3State->pGboOTableSurface. */
3608	SVGAOTableSurfaceEntry entry;
3609	RT_ZERO(entry);
3610	entry.format = pCmd->format;
3611	entry.surface1Flags = (uint32_t)(pCmd->surfaceFlags);
3612	entry.numMipLevels = pCmd->numMipLevels;
3613	entry.multisampleCount = pCmd->multisampleCount;
3614	entry.autogenFilter = pCmd->autogenFilter;
3615	entry.size = pCmd->size;
3616	entry.mobid = SVGA_ID_INVALID;
3617	entry.arraySize = pCmd->arraySize;
3618	// entry.mobPitch = 0;
3619	// entry.mobPitch = 0;
3620	entry.surface2Flags = (uint32_t)(pCmd->surfaceFlags >> UINT64_C(32));
3621	// entry.multisamplePattern = 0;
3622	// entry.qualityLevel = 0;
3623	// entry.bufferByteStride = 0;
3624	// entry.minLOD = 0;
3625
3626	int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
3627	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
3628	if (RT_SUCCESS(rc))
3629	{
3630	/* Create the host surface. */
3631	/** @todo SVGAOTableSurfaceEntry as input parameter? */
3632	vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
3633	pCmd->multisampleCount, pCmd->autogenFilter,
3634	pCmd->numMipLevels, &pCmd->size, pCmd->arraySize, /* fAllocMipLevels = */ false);
3635	}
3636	return rc;
3637	#else
3638	RT_NOREF(pThisCC, pCmd);
3639	return VERR_NOT_SUPPORTED;
3640	#endif
3641	}
3642
3643
3644	/* SVGA_3D_CMD_DX_RESOLVE_COPY 1240 */
3645	static int vmsvga3dCmdDXResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXResolveCopy const *pCmd, uint32_t cbCmd)
3646	{
3647	#ifdef VMSVGA3D_DX
3648	DEBUG_BREAKPOINT_TEST();
3649	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3650	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3651	return vmsvga3dDXResolveCopy(pThisCC, idDXContext);
3652	#else
3653	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3654	return VERR_NOT_SUPPORTED;
3655	#endif
3656	}
3657
3658
3659	/* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY 1241 */
3660	static int vmsvga3dCmdDXPredResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredResolveCopy const *pCmd, uint32_t cbCmd)
3661	{
3662	#ifdef VMSVGA3D_DX
3663	DEBUG_BREAKPOINT_TEST();
3664	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3665	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3666	return vmsvga3dDXPredResolveCopy(pThisCC, idDXContext);
3667	#else
3668	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3669	return VERR_NOT_SUPPORTED;
3670	#endif
3671	}
3672
3673
3674	/* SVGA_3D_CMD_DX_PRED_CONVERT_REGION 1242 */
3675	static int vmsvga3dCmdDXPredConvertRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvertRegion const *pCmd, uint32_t cbCmd)
3676	{
3677	#ifdef VMSVGA3D_DX
3678	DEBUG_BREAKPOINT_TEST();
3679	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3680	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3681	return vmsvga3dDXPredConvertRegion(pThisCC, idDXContext);
3682	#else
3683	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3684	return VERR_NOT_SUPPORTED;
3685	#endif
3686	}
3687
3688
3689	/* SVGA_3D_CMD_DX_PRED_CONVERT 1243 */
3690	static int vmsvga3dCmdDXPredConvert(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvert const *pCmd, uint32_t cbCmd)
3691	{
3692	#ifdef VMSVGA3D_DX
3693	DEBUG_BREAKPOINT_TEST();
3694	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3695	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3696	return vmsvga3dDXPredConvert(pThisCC, idDXContext);
3697	#else
3698	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3699	return VERR_NOT_SUPPORTED;
3700	#endif
3701	}
3702
3703
3704	/* SVGA_3D_CMD_WHOLE_SURFACE_COPY 1244 */
3705	static int vmsvga3dCmdWholeSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWholeSurfaceCopy const *pCmd, uint32_t cbCmd)
3706	{
3707	#ifdef VMSVGA3D_DX
3708	DEBUG_BREAKPOINT_TEST();
3709	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3710	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3711	return vmsvga3dWholeSurfaceCopy(pThisCC, idDXContext);
3712	#else
3713	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3714	return VERR_NOT_SUPPORTED;
3715	#endif
3716	}
3717
3718
3719	/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW 1245 */
3720	static int vmsvga3dCmdDXDefineUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineUAView const *pCmd, uint32_t cbCmd)
3721	{
3722	#ifdef VMSVGA3D_DX
3723	//DEBUG_BREAKPOINT_TEST();
3724	RT_NOREF(cbCmd);
3725	return vmsvga3dDXDefineUAView(pThisCC, idDXContext, pCmd);
3726	#else
3727	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3728	return VERR_NOT_SUPPORTED;
3729	#endif
3730	}
3731
3732
3733	/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW 1246 */
3734	static int vmsvga3dCmdDXDestroyUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyUAView const *pCmd, uint32_t cbCmd)
3735	{
3736	#ifdef VMSVGA3D_DX
3737	//DEBUG_BREAKPOINT_TEST();
3738	RT_NOREF(cbCmd);
3739	return vmsvga3dDXDestroyUAView(pThisCC, idDXContext, pCmd);
3740	#else
3741	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3742	return VERR_NOT_SUPPORTED;
3743	#endif
3744	}
3745
3746
3747	/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT 1247 */
3748	static int vmsvga3dCmdDXClearUAViewUint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewUint const *pCmd, uint32_t cbCmd)
3749	{
3750	#ifdef VMSVGA3D_DX
3751	DEBUG_BREAKPOINT_TEST();
3752	RT_NOREF(cbCmd);
3753	return vmsvga3dDXClearUAViewUint(pThisCC, idDXContext, pCmd);
3754	#else
3755	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3756	return VERR_NOT_SUPPORTED;
3757	#endif
3758	}
3759
3760
3761	/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT 1248 */
3762	static int vmsvga3dCmdDXClearUAViewFloat(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewFloat const *pCmd, uint32_t cbCmd)
3763	{
3764	#ifdef VMSVGA3D_DX
3765	DEBUG_BREAKPOINT_TEST();
3766	RT_NOREF(cbCmd);
3767	return vmsvga3dDXClearUAViewFloat(pThisCC, idDXContext, pCmd);
3768	#else
3769	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3770	return VERR_NOT_SUPPORTED;
3771	#endif
3772	}
3773
3774
3775	/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT 1249 */
3776	static int vmsvga3dCmdDXCopyStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCopyStructureCount const *pCmd, uint32_t cbCmd)
3777	{
3778	#ifdef VMSVGA3D_DX
3779	//DEBUG_BREAKPOINT_TEST();
3780	RT_NOREF(cbCmd);
3781	return vmsvga3dDXCopyStructureCount(pThisCC, idDXContext, pCmd);
3782	#else
3783	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3784	return VERR_NOT_SUPPORTED;
3785	#endif
3786	}
3787
3788
3789	/* SVGA_3D_CMD_DX_SET_UA_VIEWS 1250 */
3790	static int vmsvga3dCmdDXSetUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetUAViews const *pCmd, uint32_t cbCmd)
3791	{
3792	#ifdef VMSVGA3D_DX
3793	//DEBUG_BREAKPOINT_TEST();
3794	SVGA3dUAViewId const paUAViewId = (SVGA3dUAViewId )&pCmd[1];
3795	uint32_t const cUAViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dUAViewId);
3796	return vmsvga3dDXSetUAViews(pThisCC, idDXContext, pCmd, cUAViewId, paUAViewId);
3797	#else
3798	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3799	return VERR_NOT_SUPPORTED;
3800	#endif
3801	}
3802
3803
3804	/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT 1251 */
3805	static int vmsvga3dCmdDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd, uint32_t cbCmd)
3806	{
3807	#ifdef VMSVGA3D_DX
3808	//DEBUG_BREAKPOINT_TEST();
3809	RT_NOREF(cbCmd);
3810	return vmsvga3dDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd);
3811	#else
3812	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3813	return VERR_NOT_SUPPORTED;
3814	#endif
3815	}
3816
3817
3818	/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT 1252 */
3819	static int vmsvga3dCmdDXDrawInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstancedIndirect const *pCmd, uint32_t cbCmd)
3820	{
3821	#ifdef VMSVGA3D_DX
3822	//DEBUG_BREAKPOINT_TEST();
3823	RT_NOREF(cbCmd);
3824	return vmsvga3dDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd);
3825	#else
3826	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3827	return VERR_NOT_SUPPORTED;
3828	#endif
3829	}
3830
3831
3832	/* SVGA_3D_CMD_DX_DISPATCH 1253 */
3833	static int vmsvga3dCmdDXDispatch(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatch const *pCmd, uint32_t cbCmd)
3834	{
3835	#ifdef VMSVGA3D_DX
3836	//DEBUG_BREAKPOINT_TEST();
3837	RT_NOREF(cbCmd);
3838	return vmsvga3dDXDispatch(pThisCC, idDXContext, pCmd);
3839	#else
3840	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3841	return VERR_NOT_SUPPORTED;
3842	#endif
3843	}
3844
3845
3846	/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT 1254 */
3847	static int vmsvga3dCmdDXDispatchIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatchIndirect const *pCmd, uint32_t cbCmd)
3848	{
3849	#ifdef VMSVGA3D_DX
3850	DEBUG_BREAKPOINT_TEST();
3851	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3852	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3853	return vmsvga3dDXDispatchIndirect(pThisCC, idDXContext);
3854	#else
3855	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3856	return VERR_NOT_SUPPORTED;
3857	#endif
3858	}
3859
3860
3861	/* SVGA_3D_CMD_WRITE_ZERO_SURFACE 1255 */
3862	static int vmsvga3dCmdWriteZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWriteZeroSurface const *pCmd, uint32_t cbCmd)
3863	{
3864	#ifdef VMSVGA3D_DX
3865	DEBUG_BREAKPOINT_TEST();
3866	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3867	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3868	return vmsvga3dWriteZeroSurface(pThisCC, idDXContext);
3869	#else
3870	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3871	return VERR_NOT_SUPPORTED;
3872	#endif
3873	}
3874
3875
3876	/* SVGA_3D_CMD_HINT_ZERO_SURFACE 1256 */
3877	static int vmsvga3dCmdHintZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdHintZeroSurface const *pCmd, uint32_t cbCmd)
3878	{
3879	#ifdef VMSVGA3D_DX
3880	DEBUG_BREAKPOINT_TEST();
3881	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3882	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3883	return vmsvga3dHintZeroSurface(pThisCC, idDXContext);
3884	#else
3885	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3886	return VERR_NOT_SUPPORTED;
3887	#endif
3888	}
3889
3890
3891	/* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER 1257 */
3892	static int vmsvga3dCmdDXTransferToBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferToBuffer const *pCmd, uint32_t cbCmd)
3893	{
3894	#ifdef VMSVGA3D_DX
3895	DEBUG_BREAKPOINT_TEST();
3896	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3897	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3898	return vmsvga3dDXTransferToBuffer(pThisCC, idDXContext);
3899	#else
3900	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3901	return VERR_NOT_SUPPORTED;
3902	#endif
3903	}
3904
3905
3906	/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT 1258 */
3907	static int vmsvga3dCmdDXSetStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStructureCount const *pCmd, uint32_t cbCmd)
3908	{
3909	#ifdef VMSVGA3D_DX
3910	//DEBUG_BREAKPOINT_TEST();
3911	RT_NOREF(cbCmd);
3912	return vmsvga3dDXSetStructureCount(pThisCC, idDXContext, pCmd);
3913	#else
3914	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3915	return VERR_NOT_SUPPORTED;
3916	#endif
3917	}
3918
3919
3920	/* SVGA_3D_CMD_LOGICOPS_BITBLT 1259 */
3921	static int vmsvga3dCmdLogicOpsBitBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsBitBlt const *pCmd, uint32_t cbCmd)
3922	{
3923	#ifdef VMSVGA3D_DX
3924	DEBUG_BREAKPOINT_TEST();
3925	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3926	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3927	return vmsvga3dLogicOpsBitBlt(pThisCC, idDXContext);
3928	#else
3929	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3930	return VERR_NOT_SUPPORTED;
3931	#endif
3932	}
3933
3934
3935	/* SVGA_3D_CMD_LOGICOPS_TRANSBLT 1260 */
3936	static int vmsvga3dCmdLogicOpsTransBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsTransBlt const *pCmd, uint32_t cbCmd)
3937	{
3938	#ifdef VMSVGA3D_DX
3939	DEBUG_BREAKPOINT_TEST();
3940	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3941	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3942	return vmsvga3dLogicOpsTransBlt(pThisCC, idDXContext);
3943	#else
3944	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3945	return VERR_NOT_SUPPORTED;
3946	#endif
3947	}
3948
3949
3950	/* SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1261 */
3951	static int vmsvga3dCmdLogicOpsStretchBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsStretchBlt const *pCmd, uint32_t cbCmd)
3952	{
3953	#ifdef VMSVGA3D_DX
3954	DEBUG_BREAKPOINT_TEST();
3955	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3956	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3957	return vmsvga3dLogicOpsStretchBlt(pThisCC, idDXContext);
3958	#else
3959	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3960	return VERR_NOT_SUPPORTED;
3961	#endif
3962	}
3963
3964
3965	/* SVGA_3D_CMD_LOGICOPS_COLORFILL 1262 */
3966	static int vmsvga3dCmdLogicOpsColorFill(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsColorFill const *pCmd, uint32_t cbCmd)
3967	{
3968	#ifdef VMSVGA3D_DX
3969	DEBUG_BREAKPOINT_TEST();
3970	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3971	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3972	return vmsvga3dLogicOpsColorFill(pThisCC, idDXContext);
3973	#else
3974	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3975	return VERR_NOT_SUPPORTED;
3976	#endif
3977	}
3978
3979
3980	/* SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1263 */
3981	static int vmsvga3dCmdLogicOpsAlphaBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsAlphaBlend const *pCmd, uint32_t cbCmd)
3982	{
3983	#ifdef VMSVGA3D_DX
3984	DEBUG_BREAKPOINT_TEST();
3985	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3986	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3987	return vmsvga3dLogicOpsAlphaBlend(pThisCC, idDXContext);
3988	#else
3989	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3990	return VERR_NOT_SUPPORTED;
3991	#endif
3992	}
3993
3994
3995	/* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1264 */
3996	static int vmsvga3dCmdLogicOpsClearTypeBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsClearTypeBlend const *pCmd, uint32_t cbCmd)
3997	{
3998	#ifdef VMSVGA3D_DX
3999	DEBUG_BREAKPOINT_TEST();
4000	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4001	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4002	return vmsvga3dLogicOpsClearTypeBlend(pThisCC, idDXContext);
4003	#else
4004	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4005	return VERR_NOT_SUPPORTED;
4006	#endif
4007	}
4008
4009
4010	/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 1267 */
4011	static int vmsvga3dCmdDefineGBSurface_v4(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v4 const *pCmd)
4012	{
4013	#ifdef VMSVGA3D_DX
4014	//DEBUG_BREAKPOINT_TEST();
4015	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4016
4017	/* Update the entry in the pSvgaR3State->pGboOTableSurface. */
4018	SVGAOTableSurfaceEntry entry;
4019	RT_ZERO(entry);
4020	entry.format = pCmd->format;
4021	entry.surface1Flags = (uint32_t)(pCmd->surfaceFlags);
4022	entry.numMipLevels = pCmd->numMipLevels;
4023	entry.multisampleCount = pCmd->multisampleCount;
4024	entry.autogenFilter = pCmd->autogenFilter;
4025	entry.size = pCmd->size;
4026	entry.mobid = SVGA_ID_INVALID;
4027	entry.arraySize = pCmd->arraySize;
4028	// entry.mobPitch = 0;
4029	// entry.mobPitch = 0;
4030	entry.surface2Flags = (uint32_t)(pCmd->surfaceFlags >> UINT64_C(32));
4031	// entry.multisamplePattern = 0;
4032	// entry.qualityLevel = 0;
4033	entry.bufferByteStride = pCmd->bufferByteStride;
4034	// entry.minLOD = 0;
4035
4036	int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
4037	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
4038	if (RT_SUCCESS(rc))
4039	{
4040	/* Create the host surface. */
4041	/** @todo SVGAOTableSurfaceEntry as input parameter? */
4042	vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
4043	pCmd->multisampleCount, pCmd->autogenFilter,
4044	pCmd->numMipLevels, &pCmd->size, pCmd->arraySize, /* fAllocMipLevels = */ false);
4045	}
4046	return rc;
4047	#else
4048	RT_NOREF(pThisCC, pCmd);
4049	return VERR_NOT_SUPPORTED;
4050	#endif
4051	}
4052
4053
4054	/* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS 1268 */
4055	static int vmsvga3dCmdDXSetCSUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSUAViews const *pCmd, uint32_t cbCmd)
4056	{
4057	#ifdef VMSVGA3D_DX
4058	//DEBUG_BREAKPOINT_TEST();
4059	SVGA3dUAViewId const paUAViewId = (SVGA3dUAViewId )&pCmd[1];
4060	uint32_t const cUAViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dUAViewId);
4061	return vmsvga3dDXSetCSUAViews(pThisCC, idDXContext, pCmd, cUAViewId, paUAViewId);
4062	#else
4063	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4064	return VERR_NOT_SUPPORTED;
4065	#endif
4066	}
4067
4068
4069	/* SVGA_3D_CMD_DX_SET_MIN_LOD 1269 */
4070	static int vmsvga3dCmdDXSetMinLOD(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetMinLOD const *pCmd, uint32_t cbCmd)
4071	{
4072	#ifdef VMSVGA3D_DX
4073	DEBUG_BREAKPOINT_TEST();
4074	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4075	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4076	return vmsvga3dDXSetMinLOD(pThisCC, idDXContext);
4077	#else
4078	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4079	return VERR_NOT_SUPPORTED;
4080	#endif
4081	}
4082
4083
4084	/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 1272 */
4085	static int vmsvga3dCmdDXDefineDepthStencilView_v2(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd, uint32_t cbCmd)
4086	{
4087	#ifdef VMSVGA3D_DX
4088	//DEBUG_BREAKPOINT_TEST();
4089	RT_NOREF(cbCmd);
4090	return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, pCmd);
4091	#else
4092	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4093	return VERR_NOT_SUPPORTED;
4094	#endif
4095	}
4096
4097
4098	/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB 1273 */
4099	static int vmsvga3dCmdDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd, uint32_t cbCmd)
4100	{
4101	#ifdef VMSVGA3D_DX
4102	//DEBUG_BREAKPOINT_TEST();
4103	RT_NOREF(cbCmd);
4104	return vmsvga3dDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd);
4105	#else
4106	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4107	return VERR_NOT_SUPPORTED;
4108	#endif
4109	}
4110
4111
4112	/* SVGA_3D_CMD_DX_SET_SHADER_IFACE 1274 */
4113	static int vmsvga3dCmdDXSetShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderIface const *pCmd, uint32_t cbCmd)
4114	{
4115	#ifdef VMSVGA3D_DX
4116	DEBUG_BREAKPOINT_TEST();
4117	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4118	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4119	return vmsvga3dDXSetShaderIface(pThisCC, idDXContext);
4120	#else
4121	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4122	return VERR_NOT_SUPPORTED;
4123	#endif
4124	}
4125
4126
4127	/* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT 1275 */
4128	static int vmsvga3dCmdDXBindStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindStreamOutput const *pCmd, uint32_t cbCmd)
4129	{
4130	#ifdef VMSVGA3D_DX
4131	//DEBUG_BREAKPOINT_TEST();
4132	RT_NOREF(cbCmd);
4133	return vmsvga3dDXBindStreamOutput(pThisCC, idDXContext, pCmd);
4134	#else
4135	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4136	return VERR_NOT_SUPPORTED;
4137	#endif
4138	}
4139
4140
4141	/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS 1276 */
4142	static int vmsvga3dCmdSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdSurfaceStretchBltNonMSToMS const *pCmd, uint32_t cbCmd)
4143	{
4144	#ifdef VMSVGA3D_DX
4145	DEBUG_BREAKPOINT_TEST();
4146	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4147	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4148	return vmsvga3dSurfaceStretchBltNonMSToMS(pThisCC, idDXContext);
4149	#else
4150	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4151	return VERR_NOT_SUPPORTED;
4152	#endif
4153	}
4154
4155
4156	/* SVGA_3D_CMD_DX_BIND_SHADER_IFACE 1277 */
4157	static int vmsvga3dCmdDXBindShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShaderIface const *pCmd, uint32_t cbCmd)
4158	{
4159	#ifdef VMSVGA3D_DX
4160	DEBUG_BREAKPOINT_TEST();
4161	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4162	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4163	return vmsvga3dDXBindShaderIface(pThisCC, idDXContext);
4164	#else
4165	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4166	return VERR_NOT_SUPPORTED;
4167	#endif
4168	}
4169
4170
4171	/* SVGA_3D_CMD_VB_DX_CLEAR_RENDERTARGET_VIEW_REGION 1083 */
4172	static int vmsvga3dCmdVBDXClearRenderTargetViewRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdVBDXClearRenderTargetViewRegion *pCmd, uint32_t cbCmd)
4173	{
4174	#ifdef VMSVGA3D_DX
4175	//DEBUG_BREAKPOINT_TEST();
4176	SVGASignedRect const paRect = (SVGASignedRect )&pCmd[1];
4177	uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4178	return vmsvga3dVBDXClearRenderTargetViewRegion(pThisCC, idDXContext, pCmd, cRect, paRect);
4179	#else
4180	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4181	return VERR_NOT_SUPPORTED;
4182	#endif
4183	}
4184
4185
4186	/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4187	* Check that the 3D command has at least a_cbMin of payload bytes after the
4188	* header. Will break out of the switch if it doesn't.
4189	*/
4190	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4191	if (1) { \
4192	AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
4193	RT_UNTRUSTED_VALIDATED_FENCE(); \
4194	} else do {} while (0)
4195
4196	# define VMSVGA_3D_CMD_NOTIMPL() \
4197	if (1) { \
4198	AssertMsgFailed(("Not implemented %d %s\n", enmCmdId, vmsvgaR3FifoCmdToString(enmCmdId))); \
4199	} else do {} while (0)
4200
4201	/** SVGA_3D_CMD_* handler.
4202	* This function parses the command and calls the corresponding command handler.
4203	*
4204	* @param pThis The shared VGA/VMSVGA state.
4205	* @param pThisCC The VGA/VMSVGA state for the current context.
4206	* @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
4207	* @param enmCmdId SVGA_3D_CMD_* command identifier.
4208	* @param cbCmd Size of the command in bytes.
4209	* @param pvCmd Pointer to the command.
4210	* @returns VBox status code if an error was detected parsing a command.
4211	*/
4212	int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, SVGAFifo3dCmdId enmCmdId, uint32_t cbCmd, void const *pvCmd)
4213	{
4214	if (enmCmdId > SVGA_3D_CMD_MAX)
4215	{
4216	LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
4217	ASSERT_GUEST_FAILED_RETURN(VERR_NOT_IMPLEMENTED);
4218	}
4219
4220	int rcParse = VINF_SUCCESS;
4221	PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
4222
4223	switch (enmCmdId)
4224	{
4225	case SVGA_3D_CMD_SURFACE_DEFINE:
4226	{
4227	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )pvCmd;
4228	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4229	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefine);
4230
4231	SVGA3dCmdDefineSurface_v2 cmd;
4232	cmd.sid = pCmd->sid;
4233	cmd.surfaceFlags = pCmd->surfaceFlags;
4234	cmd.format = pCmd->format;
4235	memcpy(cmd.face, pCmd->face, sizeof(cmd.face));
4236	cmd.multisampleCount = 0;
4237	cmd.autogenFilter = SVGA3D_TEX_FILTER_NONE;
4238
4239	uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4240	vmsvga3dCmdDefineSurface(pThisCC, &cmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4241	# ifdef DEBUG_GMR_ACCESS
4242	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4243	# endif
4244	break;
4245	}
4246
4247	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4248	{
4249	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )pvCmd;
4250	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4251	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefineV2);
4252
4253	uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4254	vmsvga3dCmdDefineSurface(pThisCC, pCmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4255	# ifdef DEBUG_GMR_ACCESS
4256	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4257	# endif
4258	break;
4259	}
4260
4261	case SVGA_3D_CMD_SURFACE_DESTROY:
4262	{
4263	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )pvCmd;
4264	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4265	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDestroy);
4266
4267	vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4268	break;
4269	}
4270
4271	case SVGA_3D_CMD_SURFACE_COPY:
4272	{
4273	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )pvCmd;
4274	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4275	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceCopy);
4276
4277	uint32_t const cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4278	vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4279	break;
4280	}
4281
4282	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4283	{
4284	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )pvCmd;
4285	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4286	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceStretchBlt);
4287
4288	vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4289	&pCmd->src, &pCmd->boxSrc, pCmd->mode);
4290	break;
4291	}
4292
4293	case SVGA_3D_CMD_SURFACE_DMA:
4294	{
4295	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )pvCmd;
4296	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4297	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDma);
4298
4299	uint64_t u64NanoTS = 0;
4300	if (LogRelIs3Enabled())
4301	u64NanoTS = RTTimeNanoTS();
4302	uint32_t const cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4303	STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4304	vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4305	cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4306	STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4307	if (LogRelIs3Enabled())
4308	{
4309	if (cCopyBoxes)
4310	{
4311	SVGA3dCopyBox pFirstBox = (SVGA3dCopyBox )(pCmd + 1);
4312	LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4313	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4314	pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4315	pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4316	}
4317	}
4318	break;
4319	}
4320
4321	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4322	{
4323	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )pvCmd;
4324	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4325	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceScreen);
4326
4327	static uint64_t u64FrameStartNanoTS = 0;
4328	static uint64_t u64ElapsedPerSecNano = 0;
4329	static int cFrames = 0;
4330	uint64_t u64NanoTS = 0;
4331	if (LogRelIs3Enabled())
4332	u64NanoTS = RTTimeNanoTS();
4333	uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4334	STAM_REL_PROFILE_START(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4335	vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4336	pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4337	STAM_REL_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4338	if (LogRelIs3Enabled())
4339	{
4340	uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
4341	u64ElapsedPerSecNano += u64ElapsedNano;
4342
4343	SVGASignedRect pFirstRect = cRects ? (SVGASignedRect )(pCmd + 1) : &pCmd->destRect;
4344	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4345	(u64ElapsedNano) / 1000ULL, cRects,
4346	pFirstRect->left, pFirstRect->top,
4347	pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4348
4349	++cFrames;
4350	if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
4351	{
4352	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
4353	cFrames, u64ElapsedPerSecNano / 1000ULL));
4354	u64FrameStartNanoTS = u64NanoTS;
4355	cFrames = 0;
4356	u64ElapsedPerSecNano = 0;
4357	}
4358	}
4359	break;
4360	}
4361
4362	case SVGA_3D_CMD_CONTEXT_DEFINE:
4363	{
4364	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )pvCmd;
4365	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4366	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDefine);
4367
4368	vmsvga3dContextDefine(pThisCC, pCmd->cid);
4369	break;
4370	}
4371
4372	case SVGA_3D_CMD_CONTEXT_DESTROY:
4373	{
4374	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )pvCmd;
4375	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4376	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDestroy);
4377
4378	vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4379	break;
4380	}
4381
4382	case SVGA_3D_CMD_SETTRANSFORM:
4383	{
4384	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )pvCmd;
4385	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4386	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTransform);
4387
4388	vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4389	break;
4390	}
4391
4392	case SVGA_3D_CMD_SETZRANGE:
4393	{
4394	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )pvCmd;
4395	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4396	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetZRange);
4397
4398	vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4399	break;
4400	}
4401
4402	case SVGA_3D_CMD_SETRENDERSTATE:
4403	{
4404	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )pvCmd;
4405	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4406	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderState);
4407
4408	uint32_t const cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4409	vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4410	break;
4411	}
4412
4413	case SVGA_3D_CMD_SETRENDERTARGET:
4414	{
4415	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )pvCmd;
4416	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4417	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderTarget);
4418
4419	vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4420	break;
4421	}
4422
4423	case SVGA_3D_CMD_SETTEXTURESTATE:
4424	{
4425	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )pvCmd;
4426	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4427	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTextureState);
4428
4429	uint32_t const cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4430	vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4431	break;
4432	}
4433
4434	case SVGA_3D_CMD_SETMATERIAL:
4435	{
4436	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )pvCmd;
4437	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4438	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetMaterial);
4439
4440	vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4441	break;
4442	}
4443
4444	case SVGA_3D_CMD_SETLIGHTDATA:
4445	{
4446	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )pvCmd;
4447	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4448	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightData);
4449
4450	vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4451	break;
4452	}
4453
4454	case SVGA_3D_CMD_SETLIGHTENABLED:
4455	{
4456	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )pvCmd;
4457	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4458	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightEnable);
4459
4460	vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4461	break;
4462	}
4463
4464	case SVGA_3D_CMD_SETVIEWPORT:
4465	{
4466	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )pvCmd;
4467	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4468	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetViewPort);
4469
4470	vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4471	break;
4472	}
4473
4474	case SVGA_3D_CMD_SETCLIPPLANE:
4475	{
4476	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )pvCmd;
4477	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4478	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetClipPlane);
4479
4480	vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4481	break;
4482	}
4483
4484	case SVGA_3D_CMD_CLEAR:
4485	{
4486	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )pvCmd;
4487	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4488	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dClear);
4489
4490	uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4491	vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4492	break;
4493	}
4494
4495	case SVGA_3D_CMD_PRESENT:
4496	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4497	{
4498	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )pvCmd;
4499	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4500	if (enmCmdId == SVGA_3D_CMD_PRESENT)
4501	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent);
4502	else
4503	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresentReadBack);
4504
4505	uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4506	STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4507	vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4508	STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4509	break;
4510	}
4511
4512	case SVGA_3D_CMD_SHADER_DEFINE:
4513	{
4514	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )pvCmd;
4515	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4516	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDefine);
4517
4518	uint32_t const cbData = (cbCmd - sizeof(*pCmd));
4519	vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4520	break;
4521	}
4522
4523	case SVGA_3D_CMD_SHADER_DESTROY:
4524	{
4525	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )pvCmd;
4526	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4527	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDestroy);
4528
4529	vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4530	break;
4531	}
4532
4533	case SVGA_3D_CMD_SET_SHADER:
4534	{
4535	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )pvCmd;
4536	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4537	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShader);
4538
4539	vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4540	break;
4541	}
4542
4543	case SVGA_3D_CMD_SET_SHADER_CONST:
4544	{
4545	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )pvCmd;
4546	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4547	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShaderConst);
4548
4549	uint32_t const cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4550	vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4551	break;
4552	}
4553
4554	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4555	{
4556	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )pvCmd;
4557	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4558	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDrawPrimitives);
4559
4560	ASSERT_GUEST_STMT_BREAK(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES, rcParse = VERR_INVALID_PARAMETER);
4561	ASSERT_GUEST_STMT_BREAK(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS, rcParse = VERR_INVALID_PARAMETER);
4562	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4563	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4564	ASSERT_GUEST_STMT_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd), rcParse = VERR_INVALID_PARAMETER);
4565
4566	uint32_t const cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4567	ASSERT_GUEST_STMT_BREAK(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls, rcParse = VERR_INVALID_PARAMETER);
4568	RT_UNTRUSTED_VALIDATED_FENCE();
4569
4570	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4571	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4572	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4573
4574	STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4575	vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4576	pNumRange, cVertexDivisor, pVertexDivisor);
4577	STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4578	break;
4579	}
4580
4581	case SVGA_3D_CMD_SETSCISSORRECT:
4582	{
4583	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )pvCmd;
4584	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4585	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetScissorRect);
4586
4587	vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4588	break;
4589	}
4590
4591	case SVGA_3D_CMD_BEGIN_QUERY:
4592	{
4593	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )pvCmd;
4594	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4595	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dBeginQuery);
4596
4597	vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4598	break;
4599	}
4600
4601	case SVGA_3D_CMD_END_QUERY:
4602	{
4603	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )pvCmd;
4604	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4605	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dEndQuery);
4606
4607	vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type);
4608	break;
4609	}
4610
4611	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4612	{
4613	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )pvCmd;
4614	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4615	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dWaitForQuery);
4616
4617	vmsvga3dQueryWait(pThisCC, pCmd->cid, pCmd->type, pThis, &pCmd->guestResult);
4618	break;
4619	}
4620
4621	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4622	{
4623	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )pvCmd;
4624	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4625	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dGenerateMipmaps);
4626
4627	vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4628	break;
4629	}
4630
4631	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4632	/* context id + surface id? */
4633	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dActivateSurface);
4634	break;
4635
4636	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4637	/* context id + surface id? */
4638	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDeactivateSurface);
4639	break;
4640
4641	/*
4642	*
4643	* VPGU10: SVGA_CAP_GBOBJECTS+ commands.
4644	*
4645	*/
4646	case SVGA_3D_CMD_SCREEN_DMA:
4647	{
4648	SVGA3dCmdScreenDMA pCmd = (SVGA3dCmdScreenDMA )pvCmd;
4649	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4650	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4651	break;
4652	}
4653
4654	/* case SVGA_3D_CMD_DEAD1: New SVGA_3D_CMD_VB_DX_CLEAR_RENDERTARGET_VIEW_REGION */
4655	case SVGA_3D_CMD_DEAD2:
4656	case SVGA_3D_CMD_DEAD12: /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
4657	case SVGA_3D_CMD_DEAD13: /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
4658	case SVGA_3D_CMD_DEAD14: /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
4659	case SVGA_3D_CMD_DEAD15: /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
4660	case SVGA_3D_CMD_DEAD16: /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
4661	case SVGA_3D_CMD_DEAD17: /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
4662	{
4663	VMSVGA_3D_CMD_NOTIMPL();
4664	break;
4665	}
4666
4667	case SVGA_3D_CMD_SET_OTABLE_BASE:
4668	{
4669	SVGA3dCmdSetOTableBase pCmd = (SVGA3dCmdSetOTableBase )pvCmd;
4670	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4671	vmsvga3dCmdSetOTableBase(pThisCC, pCmd);
4672	break;
4673	}
4674
4675	case SVGA_3D_CMD_READBACK_OTABLE:
4676	{
4677	SVGA3dCmdReadbackOTable pCmd = (SVGA3dCmdReadbackOTable )pvCmd;
4678	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4679	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4680	break;
4681	}
4682
4683	case SVGA_3D_CMD_DEFINE_GB_MOB:
4684	{
4685	SVGA3dCmdDefineGBMob pCmd = (SVGA3dCmdDefineGBMob )pvCmd;
4686	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4687	vmsvga3dCmdDefineGBMob(pThisCC, pCmd);
4688	break;
4689	}
4690
4691	case SVGA_3D_CMD_DESTROY_GB_MOB:
4692	{
4693	SVGA3dCmdDestroyGBMob pCmd = (SVGA3dCmdDestroyGBMob )pvCmd;
4694	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4695	vmsvga3dCmdDestroyGBMob(pThisCC, pCmd);
4696	break;
4697	}
4698
4699	case SVGA_3D_CMD_DEAD3:
4700	{
4701	VMSVGA_3D_CMD_NOTIMPL();
4702	break;
4703	}
4704
4705	case SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING:
4706	{
4707	SVGA3dCmdUpdateGBMobMapping pCmd = (SVGA3dCmdUpdateGBMobMapping )pvCmd;
4708	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4709	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4710	break;
4711	}
4712
4713	case SVGA_3D_CMD_DEFINE_GB_SURFACE:
4714	{
4715	SVGA3dCmdDefineGBSurface pCmd = (SVGA3dCmdDefineGBSurface )pvCmd;
4716	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4717	vmsvga3dCmdDefineGBSurface(pThisCC, pCmd);
4718	break;
4719	}
4720
4721	case SVGA_3D_CMD_DESTROY_GB_SURFACE:
4722	{
4723	SVGA3dCmdDestroyGBSurface pCmd = (SVGA3dCmdDestroyGBSurface )pvCmd;
4724	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4725	vmsvga3dCmdDestroyGBSurface(pThisCC, pCmd);
4726	break;
4727	}
4728
4729	case SVGA_3D_CMD_BIND_GB_SURFACE:
4730	{
4731	SVGA3dCmdBindGBSurface pCmd = (SVGA3dCmdBindGBSurface )pvCmd;
4732	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4733	vmsvga3dCmdBindGBSurface(pThisCC, pCmd);
4734	break;
4735	}
4736
4737	case SVGA_3D_CMD_COND_BIND_GB_SURFACE:
4738	{
4739	SVGA3dCmdCondBindGBSurface pCmd = (SVGA3dCmdCondBindGBSurface )pvCmd;
4740	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4741	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4742	break;
4743	}
4744
4745	case SVGA_3D_CMD_UPDATE_GB_IMAGE:
4746	{
4747	SVGA3dCmdUpdateGBImage pCmd = (SVGA3dCmdUpdateGBImage )pvCmd;
4748	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4749	vmsvga3dCmdUpdateGBImage(pThisCC, pCmd);
4750	break;
4751	}
4752
4753	case SVGA_3D_CMD_UPDATE_GB_SURFACE:
4754	{
4755	SVGA3dCmdUpdateGBSurface pCmd = (SVGA3dCmdUpdateGBSurface )pvCmd;
4756	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4757	vmsvga3dCmdUpdateGBSurface(pThisCC, pCmd);
4758	break;
4759	}
4760
4761	case SVGA_3D_CMD_READBACK_GB_IMAGE:
4762	{
4763	SVGA3dCmdReadbackGBImage pCmd = (SVGA3dCmdReadbackGBImage )pvCmd;
4764	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4765	vmsvga3dCmdReadbackGBImage(pThisCC, pCmd);
4766	break;
4767	}
4768
4769	case SVGA_3D_CMD_READBACK_GB_SURFACE:
4770	{
4771	SVGA3dCmdReadbackGBSurface pCmd = (SVGA3dCmdReadbackGBSurface )pvCmd;
4772	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4773	vmsvga3dCmdReadbackGBSurface(pThisCC, pCmd);
4774	break;
4775	}
4776
4777	case SVGA_3D_CMD_INVALIDATE_GB_IMAGE:
4778	{
4779	SVGA3dCmdInvalidateGBImage pCmd = (SVGA3dCmdInvalidateGBImage )pvCmd;
4780	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4781	vmsvga3dCmdInvalidateGBImage(pThisCC, pCmd);
4782	break;
4783	}
4784
4785	case SVGA_3D_CMD_INVALIDATE_GB_SURFACE:
4786	{
4787	SVGA3dCmdInvalidateGBSurface pCmd = (SVGA3dCmdInvalidateGBSurface )pvCmd;
4788	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4789	vmsvga3dCmdInvalidateGBSurface(pThisCC, pCmd);
4790	break;
4791	}
4792
4793	case SVGA_3D_CMD_DEFINE_GB_CONTEXT:
4794	{
4795	SVGA3dCmdDefineGBContext pCmd = (SVGA3dCmdDefineGBContext )pvCmd;
4796	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4797	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4798	break;
4799	}
4800
4801	case SVGA_3D_CMD_DESTROY_GB_CONTEXT:
4802	{
4803	SVGA3dCmdDestroyGBContext pCmd = (SVGA3dCmdDestroyGBContext )pvCmd;
4804	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4805	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4806	break;
4807	}
4808
4809	case SVGA_3D_CMD_BIND_GB_CONTEXT:
4810	{
4811	SVGA3dCmdBindGBContext pCmd = (SVGA3dCmdBindGBContext )pvCmd;
4812	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4813	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4814	break;
4815	}
4816
4817	case SVGA_3D_CMD_READBACK_GB_CONTEXT:
4818	{
4819	SVGA3dCmdReadbackGBContext pCmd = (SVGA3dCmdReadbackGBContext )pvCmd;
4820	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4821	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4822	break;
4823	}
4824
4825	case SVGA_3D_CMD_INVALIDATE_GB_CONTEXT:
4826	{
4827	SVGA3dCmdInvalidateGBContext pCmd = (SVGA3dCmdInvalidateGBContext )pvCmd;
4828	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4829	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4830	break;
4831	}
4832
4833	case SVGA_3D_CMD_DEFINE_GB_SHADER:
4834	{
4835	SVGA3dCmdDefineGBShader pCmd = (SVGA3dCmdDefineGBShader )pvCmd;
4836	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4837	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4838	break;
4839	}
4840
4841	case SVGA_3D_CMD_DESTROY_GB_SHADER:
4842	{
4843	SVGA3dCmdDestroyGBShader pCmd = (SVGA3dCmdDestroyGBShader )pvCmd;
4844	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4845	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4846	break;
4847	}
4848
4849	case SVGA_3D_CMD_BIND_GB_SHADER:
4850	{
4851	SVGA3dCmdBindGBShader pCmd = (SVGA3dCmdBindGBShader )pvCmd;
4852	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4853	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4854	break;
4855	}
4856
4857	case SVGA_3D_CMD_SET_OTABLE_BASE64:
4858	{
4859	SVGA3dCmdSetOTableBase64 pCmd = (SVGA3dCmdSetOTableBase64 )pvCmd;
4860	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4861	vmsvga3dCmdSetOTableBase64(pThisCC, pCmd);
4862	break;
4863	}
4864
4865	case SVGA_3D_CMD_BEGIN_GB_QUERY:
4866	{
4867	SVGA3dCmdBeginGBQuery pCmd = (SVGA3dCmdBeginGBQuery )pvCmd;
4868	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4869	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4870	break;
4871	}
4872
4873	case SVGA_3D_CMD_END_GB_QUERY:
4874	{
4875	SVGA3dCmdEndGBQuery pCmd = (SVGA3dCmdEndGBQuery )pvCmd;
4876	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4877	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4878	break;
4879	}
4880
4881	case SVGA_3D_CMD_WAIT_FOR_GB_QUERY:
4882	{
4883	SVGA3dCmdWaitForGBQuery pCmd = (SVGA3dCmdWaitForGBQuery )pvCmd;
4884	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4885	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4886	break;
4887	}
4888
4889	case SVGA_3D_CMD_NOP:
4890	{
4891	/* Apparently there is nothing to do. */
4892	break;
4893	}
4894
4895	case SVGA_3D_CMD_ENABLE_GART:
4896	{
4897	SVGA3dCmdEnableGart pCmd = (SVGA3dCmdEnableGart )pvCmd;
4898	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4899	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4900	break;
4901	}
4902
4903	case SVGA_3D_CMD_DISABLE_GART:
4904	{
4905	/* No corresponding SVGA3dCmd structure. */
4906	VMSVGA_3D_CMD_NOTIMPL();
4907	break;
4908	}
4909
4910	case SVGA_3D_CMD_MAP_MOB_INTO_GART:
4911	{
4912	SVGA3dCmdMapMobIntoGart pCmd = (SVGA3dCmdMapMobIntoGart )pvCmd;
4913	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4914	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4915	break;
4916	}
4917
4918	case SVGA_3D_CMD_UNMAP_GART_RANGE:
4919	{
4920	SVGA3dCmdUnmapGartRange pCmd = (SVGA3dCmdUnmapGartRange )pvCmd;
4921	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4922	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4923	break;
4924	}
4925
4926	case SVGA_3D_CMD_DEFINE_GB_SCREENTARGET:
4927	{
4928	SVGA3dCmdDefineGBScreenTarget pCmd = (SVGA3dCmdDefineGBScreenTarget )pvCmd;
4929	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4930	vmsvga3dCmdDefineGBScreenTarget(pThis, pThisCC, pCmd);
4931	break;
4932	}
4933
4934	case SVGA_3D_CMD_DESTROY_GB_SCREENTARGET:
4935	{
4936	SVGA3dCmdDestroyGBScreenTarget pCmd = (SVGA3dCmdDestroyGBScreenTarget )pvCmd;
4937	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4938	vmsvga3dCmdDestroyGBScreenTarget(pThis, pThisCC, pCmd);
4939	break;
4940	}
4941
4942	case SVGA_3D_CMD_BIND_GB_SCREENTARGET:
4943	{
4944	SVGA3dCmdBindGBScreenTarget pCmd = (SVGA3dCmdBindGBScreenTarget )pvCmd;
4945	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4946	vmsvga3dCmdBindGBScreenTarget(pThisCC, pCmd);
4947	break;
4948	}
4949
4950	case SVGA_3D_CMD_UPDATE_GB_SCREENTARGET:
4951	{
4952	SVGA3dCmdUpdateGBScreenTarget pCmd = (SVGA3dCmdUpdateGBScreenTarget )pvCmd;
4953	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4954	vmsvga3dCmdUpdateGBScreenTarget(pThisCC, pCmd);
4955	break;
4956	}
4957
4958	case SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL:
4959	{
4960	SVGA3dCmdReadbackGBImagePartial pCmd = (SVGA3dCmdReadbackGBImagePartial )pvCmd;
4961	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4962	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4963	break;
4964	}
4965
4966	case SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL:
4967	{
4968	SVGA3dCmdInvalidateGBImagePartial pCmd = (SVGA3dCmdInvalidateGBImagePartial )pvCmd;
4969	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4970	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4971	break;
4972	}
4973
4974	case SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE:
4975	{
4976	SVGA3dCmdSetGBShaderConstInline pCmd = (SVGA3dCmdSetGBShaderConstInline )pvCmd;
4977	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4978	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4979	break;
4980	}
4981
4982	case SVGA_3D_CMD_GB_SCREEN_DMA:
4983	{
4984	SVGA3dCmdGBScreenDMA pCmd = (SVGA3dCmdGBScreenDMA )pvCmd;
4985	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4986	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4987	break;
4988	}
4989
4990	case SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH:
4991	{
4992	SVGA3dCmdBindGBSurfaceWithPitch pCmd = (SVGA3dCmdBindGBSurfaceWithPitch )pvCmd;
4993	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4994	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4995	break;
4996	}
4997
4998	case SVGA_3D_CMD_GB_MOB_FENCE:
4999	{
5000	SVGA3dCmdGBMobFence pCmd = (SVGA3dCmdGBMobFence )pvCmd;
5001	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5002	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5003	break;
5004	}
5005
5006	case SVGA_3D_CMD_DEFINE_GB_SURFACE_V2:
5007	{
5008	SVGA3dCmdDefineGBSurface_v2 pCmd = (SVGA3dCmdDefineGBSurface_v2 )pvCmd;
5009	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5010	vmsvga3dCmdDefineGBSurface_v2(pThisCC, pCmd);
5011	break;
5012	}
5013
5014	case SVGA_3D_CMD_DEFINE_GB_MOB64:
5015	{
5016	SVGA3dCmdDefineGBMob64 pCmd = (SVGA3dCmdDefineGBMob64 )pvCmd;
5017	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5018	vmsvga3dCmdDefineGBMob64(pThisCC, pCmd);
5019	break;
5020	}
5021
5022	case SVGA_3D_CMD_REDEFINE_GB_MOB64:
5023	{
5024	SVGA3dCmdRedefineGBMob64 pCmd = (SVGA3dCmdRedefineGBMob64 )pvCmd;
5025	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5026	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5027	break;
5028	}
5029
5030	case SVGA_3D_CMD_NOP_ERROR:
5031	{
5032	/* Apparently there is nothing to do. */
5033	break;
5034	}
5035
5036	case SVGA_3D_CMD_SET_VERTEX_STREAMS:
5037	{
5038	SVGA3dCmdSetVertexStreams pCmd = (SVGA3dCmdSetVertexStreams )pvCmd;
5039	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5040	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5041	break;
5042	}
5043
5044	case SVGA_3D_CMD_SET_VERTEX_DECLS:
5045	{
5046	SVGA3dCmdSetVertexDecls pCmd = (SVGA3dCmdSetVertexDecls )pvCmd;
5047	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5048	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5049	break;
5050	}
5051
5052	case SVGA_3D_CMD_SET_VERTEX_DIVISORS:
5053	{
5054	SVGA3dCmdSetVertexDivisors pCmd = (SVGA3dCmdSetVertexDivisors )pvCmd;
5055	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5056	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5057	break;
5058	}
5059
5060	case SVGA_3D_CMD_DRAW:
5061	{
5062	/* No corresponding SVGA3dCmd structure. */
5063	VMSVGA_3D_CMD_NOTIMPL();
5064	break;
5065	}
5066
5067	case SVGA_3D_CMD_DRAW_INDEXED:
5068	{
5069	/* No corresponding SVGA3dCmd structure. */
5070	VMSVGA_3D_CMD_NOTIMPL();
5071	break;
5072	}
5073
5074	case SVGA_3D_CMD_DX_DEFINE_CONTEXT:
5075	{
5076	SVGA3dCmdDXDefineContext pCmd = (SVGA3dCmdDXDefineContext )pvCmd;
5077	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5078	rcParse = vmsvga3dCmdDXDefineContext(pThisCC, pCmd, cbCmd);
5079	break;
5080	}
5081
5082	case SVGA_3D_CMD_DX_DESTROY_CONTEXT:
5083	{
5084	SVGA3dCmdDXDestroyContext pCmd = (SVGA3dCmdDXDestroyContext )pvCmd;
5085	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5086	rcParse = vmsvga3dCmdDXDestroyContext(pThisCC, pCmd, cbCmd);
5087	break;
5088	}
5089
5090	case SVGA_3D_CMD_DX_BIND_CONTEXT:
5091	{
5092	SVGA3dCmdDXBindContext pCmd = (SVGA3dCmdDXBindContext )pvCmd;
5093	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5094	rcParse = vmsvga3dCmdDXBindContext(pThisCC, pCmd, cbCmd);
5095	break;
5096	}
5097
5098	case SVGA_3D_CMD_DX_READBACK_CONTEXT:
5099	{
5100	SVGA3dCmdDXReadbackContext pCmd = (SVGA3dCmdDXReadbackContext )pvCmd;
5101	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5102	rcParse = vmsvga3dCmdDXReadbackContext(pThisCC, pCmd, cbCmd);
5103	break;
5104	}
5105
5106	case SVGA_3D_CMD_DX_INVALIDATE_CONTEXT:
5107	{
5108	SVGA3dCmdDXInvalidateContext pCmd = (SVGA3dCmdDXInvalidateContext )pvCmd;
5109	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5110	rcParse = vmsvga3dCmdDXInvalidateContext(pThisCC, idDXContext, pCmd, cbCmd);
5111	break;
5112	}
5113
5114	case SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER:
5115	{
5116	SVGA3dCmdDXSetSingleConstantBuffer pCmd = (SVGA3dCmdDXSetSingleConstantBuffer )pvCmd;
5117	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5118	rcParse = vmsvga3dCmdDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5119	break;
5120	}
5121
5122	case SVGA_3D_CMD_DX_SET_SHADER_RESOURCES:
5123	{
5124	SVGA3dCmdDXSetShaderResources pCmd = (SVGA3dCmdDXSetShaderResources )pvCmd;
5125	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5126	rcParse = vmsvga3dCmdDXSetShaderResources(pThisCC, idDXContext, pCmd, cbCmd);
5127	break;
5128	}
5129
5130	case SVGA_3D_CMD_DX_SET_SHADER:
5131	{
5132	SVGA3dCmdDXSetShader pCmd = (SVGA3dCmdDXSetShader )pvCmd;
5133	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5134	rcParse = vmsvga3dCmdDXSetShader(pThisCC, idDXContext, pCmd, cbCmd);
5135	break;
5136	}
5137
5138	case SVGA_3D_CMD_DX_SET_SAMPLERS:
5139	{
5140	SVGA3dCmdDXSetSamplers pCmd = (SVGA3dCmdDXSetSamplers )pvCmd;
5141	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5142	rcParse = vmsvga3dCmdDXSetSamplers(pThisCC, idDXContext, pCmd, cbCmd);
5143	break;
5144	}
5145
5146	case SVGA_3D_CMD_DX_DRAW:
5147	{
5148	SVGA3dCmdDXDraw pCmd = (SVGA3dCmdDXDraw )pvCmd;
5149	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5150	rcParse = vmsvga3dCmdDXDraw(pThisCC, idDXContext, pCmd, cbCmd);
5151	break;
5152	}
5153
5154	case SVGA_3D_CMD_DX_DRAW_INDEXED:
5155	{
5156	SVGA3dCmdDXDrawIndexed pCmd = (SVGA3dCmdDXDrawIndexed )pvCmd;
5157	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5158	rcParse = vmsvga3dCmdDXDrawIndexed(pThisCC, idDXContext, pCmd, cbCmd);
5159	break;
5160	}
5161
5162	case SVGA_3D_CMD_DX_DRAW_INSTANCED:
5163	{
5164	SVGA3dCmdDXDrawInstanced pCmd = (SVGA3dCmdDXDrawInstanced )pvCmd;
5165	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5166	rcParse = vmsvga3dCmdDXDrawInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5167	break;
5168	}
5169
5170	case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED:
5171	{
5172	SVGA3dCmdDXDrawIndexedInstanced pCmd = (SVGA3dCmdDXDrawIndexedInstanced )pvCmd;
5173	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5174	rcParse = vmsvga3dCmdDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5175	break;
5176	}
5177
5178	case SVGA_3D_CMD_DX_DRAW_AUTO:
5179	{
5180	SVGA3dCmdDXDrawAuto pCmd = (SVGA3dCmdDXDrawAuto )pvCmd;
5181	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5182	rcParse = vmsvga3dCmdDXDrawAuto(pThisCC, idDXContext, pCmd, cbCmd);
5183	break;
5184	}
5185
5186	case SVGA_3D_CMD_DX_SET_INPUT_LAYOUT:
5187	{
5188	SVGA3dCmdDXSetInputLayout pCmd = (SVGA3dCmdDXSetInputLayout )pvCmd;
5189	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5190	rcParse = vmsvga3dCmdDXSetInputLayout(pThisCC, idDXContext, pCmd, cbCmd);
5191	break;
5192	}
5193
5194	case SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS:
5195	{
5196	SVGA3dCmdDXSetVertexBuffers pCmd = (SVGA3dCmdDXSetVertexBuffers )pvCmd;
5197	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5198	rcParse = vmsvga3dCmdDXSetVertexBuffers(pThisCC, idDXContext, pCmd, cbCmd);
5199	break;
5200	}
5201
5202	case SVGA_3D_CMD_DX_SET_INDEX_BUFFER:
5203	{
5204	SVGA3dCmdDXSetIndexBuffer pCmd = (SVGA3dCmdDXSetIndexBuffer )pvCmd;
5205	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5206	rcParse = vmsvga3dCmdDXSetIndexBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5207	break;
5208	}
5209
5210	case SVGA_3D_CMD_DX_SET_TOPOLOGY:
5211	{
5212	SVGA3dCmdDXSetTopology pCmd = (SVGA3dCmdDXSetTopology )pvCmd;
5213	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5214	rcParse = vmsvga3dCmdDXSetTopology(pThisCC, idDXContext, pCmd, cbCmd);
5215	break;
5216	}
5217
5218	case SVGA_3D_CMD_DX_SET_RENDERTARGETS:
5219	{
5220	SVGA3dCmdDXSetRenderTargets pCmd = (SVGA3dCmdDXSetRenderTargets )pvCmd;
5221	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5222	rcParse = vmsvga3dCmdDXSetRenderTargets(pThisCC, idDXContext, pCmd, cbCmd);
5223	break;
5224	}
5225
5226	case SVGA_3D_CMD_DX_SET_BLEND_STATE:
5227	{
5228	SVGA3dCmdDXSetBlendState pCmd = (SVGA3dCmdDXSetBlendState )pvCmd;
5229	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5230	rcParse = vmsvga3dCmdDXSetBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5231	break;
5232	}
5233
5234	case SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE:
5235	{
5236	SVGA3dCmdDXSetDepthStencilState pCmd = (SVGA3dCmdDXSetDepthStencilState )pvCmd;
5237	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5238	rcParse = vmsvga3dCmdDXSetDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5239	break;
5240	}
5241
5242	case SVGA_3D_CMD_DX_SET_RASTERIZER_STATE:
5243	{
5244	SVGA3dCmdDXSetRasterizerState pCmd = (SVGA3dCmdDXSetRasterizerState )pvCmd;
5245	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5246	rcParse = vmsvga3dCmdDXSetRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5247	break;
5248	}
5249
5250	case SVGA_3D_CMD_DX_DEFINE_QUERY:
5251	{
5252	SVGA3dCmdDXDefineQuery pCmd = (SVGA3dCmdDXDefineQuery )pvCmd;
5253	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5254	rcParse = vmsvga3dCmdDXDefineQuery(pThisCC, idDXContext, pCmd, cbCmd);
5255	break;
5256	}
5257
5258	case SVGA_3D_CMD_DX_DESTROY_QUERY:
5259	{
5260	SVGA3dCmdDXDestroyQuery pCmd = (SVGA3dCmdDXDestroyQuery )pvCmd;
5261	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5262	rcParse = vmsvga3dCmdDXDestroyQuery(pThisCC, idDXContext, pCmd, cbCmd);
5263	break;
5264	}
5265
5266	case SVGA_3D_CMD_DX_BIND_QUERY:
5267	{
5268	SVGA3dCmdDXBindQuery pCmd = (SVGA3dCmdDXBindQuery )pvCmd;
5269	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5270	rcParse = vmsvga3dCmdDXBindQuery(pThisCC, idDXContext, pCmd, cbCmd);
5271	break;
5272	}
5273
5274	case SVGA_3D_CMD_DX_SET_QUERY_OFFSET:
5275	{
5276	SVGA3dCmdDXSetQueryOffset pCmd = (SVGA3dCmdDXSetQueryOffset )pvCmd;
5277	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5278	rcParse = vmsvga3dCmdDXSetQueryOffset(pThisCC, idDXContext, pCmd, cbCmd);
5279	break;
5280	}
5281
5282	case SVGA_3D_CMD_DX_BEGIN_QUERY:
5283	{
5284	SVGA3dCmdDXBeginQuery pCmd = (SVGA3dCmdDXBeginQuery )pvCmd;
5285	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5286	rcParse = vmsvga3dCmdDXBeginQuery(pThisCC, idDXContext, pCmd, cbCmd);
5287	break;
5288	}
5289
5290	case SVGA_3D_CMD_DX_END_QUERY:
5291	{
5292	SVGA3dCmdDXEndQuery pCmd = (SVGA3dCmdDXEndQuery )pvCmd;
5293	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5294	rcParse = vmsvga3dCmdDXEndQuery(pThisCC, idDXContext, pCmd, cbCmd);
5295	break;
5296	}
5297
5298	case SVGA_3D_CMD_DX_READBACK_QUERY:
5299	{
5300	SVGA3dCmdDXReadbackQuery pCmd = (SVGA3dCmdDXReadbackQuery )pvCmd;
5301	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5302	rcParse = vmsvga3dCmdDXReadbackQuery(pThisCC, idDXContext, pCmd, cbCmd);
5303	break;
5304	}
5305
5306	case SVGA_3D_CMD_DX_SET_PREDICATION:
5307	{
5308	SVGA3dCmdDXSetPredication pCmd = (SVGA3dCmdDXSetPredication )pvCmd;
5309	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5310	rcParse = vmsvga3dCmdDXSetPredication(pThisCC, idDXContext, pCmd, cbCmd);
5311	break;
5312	}
5313
5314	case SVGA_3D_CMD_DX_SET_SOTARGETS:
5315	{
5316	SVGA3dCmdDXSetSOTargets pCmd = (SVGA3dCmdDXSetSOTargets )pvCmd;
5317	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5318	rcParse = vmsvga3dCmdDXSetSOTargets(pThisCC, idDXContext, pCmd, cbCmd);
5319	break;
5320	}
5321
5322	case SVGA_3D_CMD_DX_SET_VIEWPORTS:
5323	{
5324	SVGA3dCmdDXSetViewports pCmd = (SVGA3dCmdDXSetViewports )pvCmd;
5325	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5326	rcParse = vmsvga3dCmdDXSetViewports(pThisCC, idDXContext, pCmd, cbCmd);
5327	break;
5328	}
5329
5330	case SVGA_3D_CMD_DX_SET_SCISSORRECTS:
5331	{
5332	SVGA3dCmdDXSetScissorRects pCmd = (SVGA3dCmdDXSetScissorRects )pvCmd;
5333	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5334	rcParse = vmsvga3dCmdDXSetScissorRects(pThisCC, idDXContext, pCmd, cbCmd);
5335	break;
5336	}
5337
5338	case SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW:
5339	{
5340	SVGA3dCmdDXClearRenderTargetView pCmd = (SVGA3dCmdDXClearRenderTargetView )pvCmd;
5341	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5342	rcParse = vmsvga3dCmdDXClearRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5343	break;
5344	}
5345
5346	case SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW:
5347	{
5348	SVGA3dCmdDXClearDepthStencilView pCmd = (SVGA3dCmdDXClearDepthStencilView )pvCmd;
5349	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5350	rcParse = vmsvga3dCmdDXClearDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5351	break;
5352	}
5353
5354	case SVGA_3D_CMD_DX_PRED_COPY_REGION:
5355	{
5356	SVGA3dCmdDXPredCopyRegion pCmd = (SVGA3dCmdDXPredCopyRegion )pvCmd;
5357	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5358	rcParse = vmsvga3dCmdDXPredCopyRegion(pThisCC, idDXContext, pCmd, cbCmd);
5359	break;
5360	}
5361
5362	case SVGA_3D_CMD_DX_PRED_COPY:
5363	{
5364	SVGA3dCmdDXPredCopy pCmd = (SVGA3dCmdDXPredCopy )pvCmd;
5365	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5366	rcParse = vmsvga3dCmdDXPredCopy(pThisCC, idDXContext, pCmd, cbCmd);
5367	break;
5368	}
5369
5370	case SVGA_3D_CMD_DX_PRESENTBLT:
5371	{
5372	SVGA3dCmdDXPresentBlt pCmd = (SVGA3dCmdDXPresentBlt )pvCmd;
5373	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5374	rcParse = vmsvga3dCmdDXPresentBlt(pThisCC, idDXContext, pCmd, cbCmd);
5375	break;
5376	}
5377
5378	case SVGA_3D_CMD_DX_GENMIPS:
5379	{
5380	SVGA3dCmdDXGenMips pCmd = (SVGA3dCmdDXGenMips )pvCmd;
5381	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5382	rcParse = vmsvga3dCmdDXGenMips(pThisCC, idDXContext, pCmd, cbCmd);
5383	break;
5384	}
5385
5386	case SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE:
5387	{
5388	SVGA3dCmdDXUpdateSubResource pCmd = (SVGA3dCmdDXUpdateSubResource )pvCmd;
5389	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5390	rcParse = vmsvga3dCmdDXUpdateSubResource(pThisCC, pCmd, cbCmd);
5391	break;
5392	}
5393
5394	case SVGA_3D_CMD_DX_READBACK_SUBRESOURCE:
5395	{
5396	SVGA3dCmdDXReadbackSubResource pCmd = (SVGA3dCmdDXReadbackSubResource )pvCmd;
5397	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5398	rcParse = vmsvga3dCmdDXReadbackSubResource(pThisCC, pCmd, cbCmd);
5399	break;
5400	}
5401
5402	case SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE:
5403	{
5404	SVGA3dCmdDXInvalidateSubResource pCmd = (SVGA3dCmdDXInvalidateSubResource )pvCmd;
5405	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5406	rcParse = vmsvga3dCmdDXInvalidateSubResource(pThisCC, pCmd, cbCmd);
5407	break;
5408	}
5409
5410	case SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW:
5411	{
5412	SVGA3dCmdDXDefineShaderResourceView pCmd = (SVGA3dCmdDXDefineShaderResourceView )pvCmd;
5413	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5414	rcParse = vmsvga3dCmdDXDefineShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5415	break;
5416	}
5417
5418	case SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW:
5419	{
5420	SVGA3dCmdDXDestroyShaderResourceView pCmd = (SVGA3dCmdDXDestroyShaderResourceView )pvCmd;
5421	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5422	rcParse = vmsvga3dCmdDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5423	break;
5424	}
5425
5426	case SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW:
5427	{
5428	SVGA3dCmdDXDefineRenderTargetView pCmd = (SVGA3dCmdDXDefineRenderTargetView )pvCmd;
5429	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5430	rcParse = vmsvga3dCmdDXDefineRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5431	break;
5432	}
5433
5434	case SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW:
5435	{
5436	SVGA3dCmdDXDestroyRenderTargetView pCmd = (SVGA3dCmdDXDestroyRenderTargetView )pvCmd;
5437	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5438	rcParse = vmsvga3dCmdDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5439	break;
5440	}
5441
5442	case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW:
5443	{
5444	SVGA3dCmdDXDefineDepthStencilView pCmd = (SVGA3dCmdDXDefineDepthStencilView )pvCmd;
5445	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5446	rcParse = vmsvga3dCmdDXDefineDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5447	break;
5448	}
5449
5450	case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW:
5451	{
5452	SVGA3dCmdDXDestroyDepthStencilView pCmd = (SVGA3dCmdDXDestroyDepthStencilView )pvCmd;
5453	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5454	rcParse = vmsvga3dCmdDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5455	break;
5456	}
5457
5458	case SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT:
5459	{
5460	SVGA3dCmdDXDefineElementLayout pCmd = (SVGA3dCmdDXDefineElementLayout )pvCmd;
5461	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5462	rcParse = vmsvga3dCmdDXDefineElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5463	break;
5464	}
5465
5466	case SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT:
5467	{
5468	SVGA3dCmdDXDestroyElementLayout pCmd = (SVGA3dCmdDXDestroyElementLayout )pvCmd;
5469	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5470	rcParse = vmsvga3dCmdDXDestroyElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5471	break;
5472	}
5473
5474	case SVGA_3D_CMD_DX_DEFINE_BLEND_STATE:
5475	{
5476	SVGA3dCmdDXDefineBlendState pCmd = (SVGA3dCmdDXDefineBlendState )pvCmd;
5477	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5478	rcParse = vmsvga3dCmdDXDefineBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5479	break;
5480	}
5481
5482	case SVGA_3D_CMD_DX_DESTROY_BLEND_STATE:
5483	{
5484	SVGA3dCmdDXDestroyBlendState pCmd = (SVGA3dCmdDXDestroyBlendState )pvCmd;
5485	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5486	rcParse = vmsvga3dCmdDXDestroyBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5487	break;
5488	}
5489
5490	case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE:
5491	{
5492	SVGA3dCmdDXDefineDepthStencilState pCmd = (SVGA3dCmdDXDefineDepthStencilState )pvCmd;
5493	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5494	rcParse = vmsvga3dCmdDXDefineDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5495	break;
5496	}
5497
5498	case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE:
5499	{
5500	SVGA3dCmdDXDestroyDepthStencilState pCmd = (SVGA3dCmdDXDestroyDepthStencilState )pvCmd;
5501	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5502	rcParse = vmsvga3dCmdDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5503	break;
5504	}
5505
5506	case SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE:
5507	{
5508	SVGA3dCmdDXDefineRasterizerState pCmd = (SVGA3dCmdDXDefineRasterizerState )pvCmd;
5509	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5510	rcParse = vmsvga3dCmdDXDefineRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5511	break;
5512	}
5513
5514	case SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE:
5515	{
5516	SVGA3dCmdDXDestroyRasterizerState pCmd = (SVGA3dCmdDXDestroyRasterizerState )pvCmd;
5517	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5518	rcParse = vmsvga3dCmdDXDestroyRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5519	break;
5520	}
5521
5522	case SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE:
5523	{
5524	SVGA3dCmdDXDefineSamplerState pCmd = (SVGA3dCmdDXDefineSamplerState )pvCmd;
5525	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5526	rcParse = vmsvga3dCmdDXDefineSamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5527	break;
5528	}
5529
5530	case SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE:
5531	{
5532	SVGA3dCmdDXDestroySamplerState pCmd = (SVGA3dCmdDXDestroySamplerState )pvCmd;
5533	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5534	rcParse = vmsvga3dCmdDXDestroySamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5535	break;
5536	}
5537
5538	case SVGA_3D_CMD_DX_DEFINE_SHADER:
5539	{
5540	SVGA3dCmdDXDefineShader pCmd = (SVGA3dCmdDXDefineShader )pvCmd;
5541	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5542	rcParse = vmsvga3dCmdDXDefineShader(pThisCC, idDXContext, pCmd, cbCmd);
5543	break;
5544	}
5545
5546	case SVGA_3D_CMD_DX_DESTROY_SHADER:
5547	{
5548	SVGA3dCmdDXDestroyShader pCmd = (SVGA3dCmdDXDestroyShader )pvCmd;
5549	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5550	rcParse = vmsvga3dCmdDXDestroyShader(pThisCC, idDXContext, pCmd, cbCmd);
5551	break;
5552	}
5553
5554	case SVGA_3D_CMD_DX_BIND_SHADER:
5555	{
5556	SVGA3dCmdDXBindShader pCmd = (SVGA3dCmdDXBindShader )pvCmd;
5557	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5558	rcParse = vmsvga3dCmdDXBindShader(pThisCC, idDXContext, pCmd, cbCmd);
5559	break;
5560	}
5561
5562	case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT:
5563	{
5564	SVGA3dCmdDXDefineStreamOutput pCmd = (SVGA3dCmdDXDefineStreamOutput )pvCmd;
5565	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5566	rcParse = vmsvga3dCmdDXDefineStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5567	break;
5568	}
5569
5570	case SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT:
5571	{
5572	SVGA3dCmdDXDestroyStreamOutput pCmd = (SVGA3dCmdDXDestroyStreamOutput )pvCmd;
5573	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5574	rcParse = vmsvga3dCmdDXDestroyStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5575	break;
5576	}
5577
5578	case SVGA_3D_CMD_DX_SET_STREAMOUTPUT:
5579	{
5580	SVGA3dCmdDXSetStreamOutput pCmd = (SVGA3dCmdDXSetStreamOutput )pvCmd;
5581	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5582	rcParse = vmsvga3dCmdDXSetStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5583	break;
5584	}
5585
5586	case SVGA_3D_CMD_DX_SET_COTABLE:
5587	{
5588	SVGA3dCmdDXSetCOTable pCmd = (SVGA3dCmdDXSetCOTable )pvCmd;
5589	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5590	rcParse = vmsvga3dCmdDXSetCOTable(pThisCC, pCmd, cbCmd);
5591	break;
5592	}
5593
5594	case SVGA_3D_CMD_DX_READBACK_COTABLE:
5595	{
5596	SVGA3dCmdDXReadbackCOTable pCmd = (SVGA3dCmdDXReadbackCOTable )pvCmd;
5597	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5598	rcParse = vmsvga3dCmdDXReadbackCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5599	break;
5600	}
5601
5602	case SVGA_3D_CMD_DX_BUFFER_COPY:
5603	{
5604	SVGA3dCmdDXBufferCopy pCmd = (SVGA3dCmdDXBufferCopy )pvCmd;
5605	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5606	rcParse = vmsvga3dCmdDXBufferCopy(pThisCC, idDXContext, pCmd, cbCmd);
5607	break;
5608	}
5609
5610	case SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER:
5611	{
5612	SVGA3dCmdDXTransferFromBuffer pCmd = (SVGA3dCmdDXTransferFromBuffer )pvCmd;
5613	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5614	rcParse = vmsvga3dCmdDXTransferFromBuffer(pThisCC, pCmd, cbCmd);
5615	break;
5616	}
5617
5618	case SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK:
5619	{
5620	SVGA3dCmdDXSurfaceCopyAndReadback pCmd = (SVGA3dCmdDXSurfaceCopyAndReadback )pvCmd;
5621	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5622	rcParse = vmsvga3dCmdDXSurfaceCopyAndReadback(pThisCC, idDXContext, pCmd, cbCmd);
5623	break;
5624	}
5625
5626	case SVGA_3D_CMD_DX_MOVE_QUERY:
5627	{
5628	SVGA3dCmdDXMoveQuery pCmd = (SVGA3dCmdDXMoveQuery )pvCmd;
5629	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5630	rcParse = vmsvga3dCmdDXMoveQuery(pThisCC, idDXContext, pCmd, cbCmd);
5631	break;
5632	}
5633
5634	case SVGA_3D_CMD_DX_BIND_ALL_QUERY:
5635	{
5636	SVGA3dCmdDXBindAllQuery pCmd = (SVGA3dCmdDXBindAllQuery )pvCmd;
5637	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5638	rcParse = vmsvga3dCmdDXBindAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5639	break;
5640	}
5641
5642	case SVGA_3D_CMD_DX_READBACK_ALL_QUERY:
5643	{
5644	SVGA3dCmdDXReadbackAllQuery pCmd = (SVGA3dCmdDXReadbackAllQuery )pvCmd;
5645	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5646	rcParse = vmsvga3dCmdDXReadbackAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5647	break;
5648	}
5649
5650	case SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER:
5651	{
5652	SVGA3dCmdDXPredTransferFromBuffer pCmd = (SVGA3dCmdDXPredTransferFromBuffer )pvCmd;
5653	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5654	rcParse = vmsvga3dCmdDXPredTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5655	break;
5656	}
5657
5658	case SVGA_3D_CMD_DX_MOB_FENCE_64:
5659	{
5660	SVGA3dCmdDXMobFence64 pCmd = (SVGA3dCmdDXMobFence64 )pvCmd;
5661	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5662	rcParse = vmsvga3dCmdDXMobFence64(pThisCC, pCmd, cbCmd);
5663	break;
5664	}
5665
5666	case SVGA_3D_CMD_DX_BIND_ALL_SHADER:
5667	{
5668	SVGA3dCmdDXBindAllShader pCmd = (SVGA3dCmdDXBindAllShader )pvCmd;
5669	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5670	rcParse = vmsvga3dCmdDXBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5671	break;
5672	}
5673
5674	case SVGA_3D_CMD_DX_HINT:
5675	{
5676	SVGA3dCmdDXHint pCmd = (SVGA3dCmdDXHint )pvCmd;
5677	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5678	rcParse = vmsvga3dCmdDXHint(pThisCC, idDXContext, pCmd, cbCmd);
5679	break;
5680	}
5681
5682	case SVGA_3D_CMD_DX_BUFFER_UPDATE:
5683	{
5684	SVGA3dCmdDXBufferUpdate pCmd = (SVGA3dCmdDXBufferUpdate )pvCmd;
5685	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5686	rcParse = vmsvga3dCmdDXBufferUpdate(pThisCC, idDXContext, pCmd, cbCmd);
5687	break;
5688	}
5689
5690	case SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET:
5691	{
5692	SVGA3dCmdDXSetVSConstantBufferOffset pCmd = (SVGA3dCmdDXSetVSConstantBufferOffset )pvCmd;
5693	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5694	rcParse = vmsvga3dCmdDXSetVSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5695	break;
5696	}
5697
5698	case SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET:
5699	{
5700	SVGA3dCmdDXSetPSConstantBufferOffset pCmd = (SVGA3dCmdDXSetPSConstantBufferOffset )pvCmd;
5701	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5702	rcParse = vmsvga3dCmdDXSetPSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5703	break;
5704	}
5705
5706	case SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET:
5707	{
5708	SVGA3dCmdDXSetGSConstantBufferOffset pCmd = (SVGA3dCmdDXSetGSConstantBufferOffset )pvCmd;
5709	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5710	rcParse = vmsvga3dCmdDXSetGSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5711	break;
5712	}
5713
5714	case SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET:
5715	{
5716	SVGA3dCmdDXSetHSConstantBufferOffset pCmd = (SVGA3dCmdDXSetHSConstantBufferOffset )pvCmd;
5717	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5718	rcParse = vmsvga3dCmdDXSetHSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5719	break;
5720	}
5721
5722	case SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET:
5723	{
5724	SVGA3dCmdDXSetDSConstantBufferOffset pCmd = (SVGA3dCmdDXSetDSConstantBufferOffset )pvCmd;
5725	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5726	rcParse = vmsvga3dCmdDXSetDSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5727	break;
5728	}
5729
5730	case SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET:
5731	{
5732	SVGA3dCmdDXSetCSConstantBufferOffset pCmd = (SVGA3dCmdDXSetCSConstantBufferOffset )pvCmd;
5733	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5734	rcParse = vmsvga3dCmdDXSetCSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5735	break;
5736	}
5737
5738	case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER:
5739	{
5740	SVGA3dCmdDXCondBindAllShader pCmd = (SVGA3dCmdDXCondBindAllShader )pvCmd;
5741	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5742	rcParse = vmsvga3dCmdDXCondBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5743	break;
5744	}
5745
5746	case SVGA_3D_CMD_SCREEN_COPY:
5747	{
5748	SVGA3dCmdScreenCopy pCmd = (SVGA3dCmdScreenCopy )pvCmd;
5749	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5750	rcParse = vmsvga3dCmdScreenCopy(pThisCC, idDXContext, pCmd, cbCmd);
5751	break;
5752	}
5753
5754	case SVGA_3D_CMD_RESERVED1:
5755	{
5756	VMSVGA_3D_CMD_NOTIMPL();
5757	break;
5758	}
5759
5760	case SVGA_3D_CMD_RESERVED2:
5761	{
5762	VMSVGA_3D_CMD_NOTIMPL();
5763	break;
5764	}
5765
5766	case SVGA_3D_CMD_RESERVED3:
5767	{
5768	VMSVGA_3D_CMD_NOTIMPL();
5769	break;
5770	}
5771
5772	case SVGA_3D_CMD_RESERVED4:
5773	{
5774	VMSVGA_3D_CMD_NOTIMPL();
5775	break;
5776	}
5777
5778	case SVGA_3D_CMD_RESERVED5:
5779	{
5780	VMSVGA_3D_CMD_NOTIMPL();
5781	break;
5782	}
5783
5784	case SVGA_3D_CMD_RESERVED6:
5785	{
5786	VMSVGA_3D_CMD_NOTIMPL();
5787	break;
5788	}
5789
5790	case SVGA_3D_CMD_RESERVED7:
5791	{
5792	VMSVGA_3D_CMD_NOTIMPL();
5793	break;
5794	}
5795
5796	case SVGA_3D_CMD_RESERVED8:
5797	{
5798	VMSVGA_3D_CMD_NOTIMPL();
5799	break;
5800	}
5801
5802	case SVGA_3D_CMD_GROW_OTABLE:
5803	{
5804	SVGA3dCmdGrowOTable pCmd = (SVGA3dCmdGrowOTable )pvCmd;
5805	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5806	rcParse = vmsvga3dCmdGrowOTable(pThisCC, pCmd, cbCmd);
5807	break;
5808	}
5809
5810	case SVGA_3D_CMD_DX_GROW_COTABLE:
5811	{
5812	SVGA3dCmdDXGrowCOTable pCmd = (SVGA3dCmdDXGrowCOTable )pvCmd;
5813	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5814	rcParse = vmsvga3dCmdDXGrowCOTable(pThisCC, pCmd, cbCmd);
5815	break;
5816	}
5817
5818	case SVGA_3D_CMD_INTRA_SURFACE_COPY:
5819	{
5820	SVGA3dCmdIntraSurfaceCopy pCmd = (SVGA3dCmdIntraSurfaceCopy )pvCmd;
5821	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5822	rcParse = vmsvga3dCmdIntraSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5823	break;
5824	}
5825
5826	case SVGA_3D_CMD_DEFINE_GB_SURFACE_V3:
5827	{
5828	SVGA3dCmdDefineGBSurface_v3 pCmd = (SVGA3dCmdDefineGBSurface_v3 )pvCmd;
5829	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5830	rcParse = vmsvga3dCmdDefineGBSurface_v3(pThisCC, pCmd);
5831	break;
5832	}
5833
5834	case SVGA_3D_CMD_DX_RESOLVE_COPY:
5835	{
5836	SVGA3dCmdDXResolveCopy pCmd = (SVGA3dCmdDXResolveCopy )pvCmd;
5837	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5838	rcParse = vmsvga3dCmdDXResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5839	break;
5840	}
5841
5842	case SVGA_3D_CMD_DX_PRED_RESOLVE_COPY:
5843	{
5844	SVGA3dCmdDXPredResolveCopy pCmd = (SVGA3dCmdDXPredResolveCopy )pvCmd;
5845	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5846	rcParse = vmsvga3dCmdDXPredResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5847	break;
5848	}
5849
5850	case SVGA_3D_CMD_DX_PRED_CONVERT_REGION:
5851	{
5852	SVGA3dCmdDXPredConvertRegion pCmd = (SVGA3dCmdDXPredConvertRegion )pvCmd;
5853	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5854	rcParse = vmsvga3dCmdDXPredConvertRegion(pThisCC, idDXContext, pCmd, cbCmd);
5855	break;
5856	}
5857
5858	case SVGA_3D_CMD_DX_PRED_CONVERT:
5859	{
5860	SVGA3dCmdDXPredConvert pCmd = (SVGA3dCmdDXPredConvert )pvCmd;
5861	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5862	rcParse = vmsvga3dCmdDXPredConvert(pThisCC, idDXContext, pCmd, cbCmd);
5863	break;
5864	}
5865
5866	case SVGA_3D_CMD_WHOLE_SURFACE_COPY:
5867	{
5868	SVGA3dCmdWholeSurfaceCopy pCmd = (SVGA3dCmdWholeSurfaceCopy )pvCmd;
5869	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5870	rcParse = vmsvga3dCmdWholeSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5871	break;
5872	}
5873
5874	case SVGA_3D_CMD_DX_DEFINE_UA_VIEW:
5875	{
5876	SVGA3dCmdDXDefineUAView pCmd = (SVGA3dCmdDXDefineUAView )pvCmd;
5877	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5878	rcParse = vmsvga3dCmdDXDefineUAView(pThisCC, idDXContext, pCmd, cbCmd);
5879	break;
5880	}
5881
5882	case SVGA_3D_CMD_DX_DESTROY_UA_VIEW:
5883	{
5884	SVGA3dCmdDXDestroyUAView pCmd = (SVGA3dCmdDXDestroyUAView )pvCmd;
5885	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5886	rcParse = vmsvga3dCmdDXDestroyUAView(pThisCC, idDXContext, pCmd, cbCmd);
5887	break;
5888	}
5889
5890	case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT:
5891	{
5892	SVGA3dCmdDXClearUAViewUint pCmd = (SVGA3dCmdDXClearUAViewUint )pvCmd;
5893	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5894	rcParse = vmsvga3dCmdDXClearUAViewUint(pThisCC, idDXContext, pCmd, cbCmd);
5895	break;
5896	}
5897
5898	case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT:
5899	{
5900	SVGA3dCmdDXClearUAViewFloat pCmd = (SVGA3dCmdDXClearUAViewFloat )pvCmd;
5901	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5902	rcParse = vmsvga3dCmdDXClearUAViewFloat(pThisCC, idDXContext, pCmd, cbCmd);
5903	break;
5904	}
5905
5906	case SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT:
5907	{
5908	SVGA3dCmdDXCopyStructureCount pCmd = (SVGA3dCmdDXCopyStructureCount )pvCmd;
5909	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5910	rcParse = vmsvga3dCmdDXCopyStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5911	break;
5912	}
5913
5914	case SVGA_3D_CMD_DX_SET_UA_VIEWS:
5915	{
5916	SVGA3dCmdDXSetUAViews pCmd = (SVGA3dCmdDXSetUAViews )pvCmd;
5917	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5918	rcParse = vmsvga3dCmdDXSetUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5919	break;
5920	}
5921
5922	case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT:
5923	{
5924	SVGA3dCmdDXDrawIndexedInstancedIndirect pCmd = (SVGA3dCmdDXDrawIndexedInstancedIndirect )pvCmd;
5925	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5926	rcParse = vmsvga3dCmdDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5927	break;
5928	}
5929
5930	case SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT:
5931	{
5932	SVGA3dCmdDXDrawInstancedIndirect pCmd = (SVGA3dCmdDXDrawInstancedIndirect )pvCmd;
5933	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5934	rcParse = vmsvga3dCmdDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5935	break;
5936	}
5937
5938	case SVGA_3D_CMD_DX_DISPATCH:
5939	{
5940	SVGA3dCmdDXDispatch pCmd = (SVGA3dCmdDXDispatch )pvCmd;
5941	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5942	rcParse = vmsvga3dCmdDXDispatch(pThisCC, idDXContext, pCmd, cbCmd);
5943	break;
5944	}
5945
5946	case SVGA_3D_CMD_DX_DISPATCH_INDIRECT:
5947	{
5948	SVGA3dCmdDXDispatchIndirect pCmd = (SVGA3dCmdDXDispatchIndirect )pvCmd;
5949	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5950	rcParse = vmsvga3dCmdDXDispatchIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5951	break;
5952	}
5953
5954	case SVGA_3D_CMD_WRITE_ZERO_SURFACE:
5955	{
5956	SVGA3dCmdWriteZeroSurface pCmd = (SVGA3dCmdWriteZeroSurface )pvCmd;
5957	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5958	rcParse = vmsvga3dCmdWriteZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5959	break;
5960	}
5961
5962	case SVGA_3D_CMD_HINT_ZERO_SURFACE:
5963	{
5964	SVGA3dCmdHintZeroSurface pCmd = (SVGA3dCmdHintZeroSurface )pvCmd;
5965	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5966	rcParse = vmsvga3dCmdHintZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5967	break;
5968	}
5969
5970	case SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER:
5971	{
5972	SVGA3dCmdDXTransferToBuffer pCmd = (SVGA3dCmdDXTransferToBuffer )pvCmd;
5973	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5974	rcParse = vmsvga3dCmdDXTransferToBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5975	break;
5976	}
5977
5978	case SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT:
5979	{
5980	SVGA3dCmdDXSetStructureCount pCmd = (SVGA3dCmdDXSetStructureCount )pvCmd;
5981	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5982	rcParse = vmsvga3dCmdDXSetStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5983	break;
5984	}
5985
5986	case SVGA_3D_CMD_LOGICOPS_BITBLT:
5987	{
5988	SVGA3dCmdLogicOpsBitBlt pCmd = (SVGA3dCmdLogicOpsBitBlt )pvCmd;
5989	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5990	rcParse = vmsvga3dCmdLogicOpsBitBlt(pThisCC, idDXContext, pCmd, cbCmd);
5991	break;
5992	}
5993
5994	case SVGA_3D_CMD_LOGICOPS_TRANSBLT:
5995	{
5996	SVGA3dCmdLogicOpsTransBlt pCmd = (SVGA3dCmdLogicOpsTransBlt )pvCmd;
5997	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5998	rcParse = vmsvga3dCmdLogicOpsTransBlt(pThisCC, idDXContext, pCmd, cbCmd);
5999	break;
6000	}
6001
6002	case SVGA_3D_CMD_LOGICOPS_STRETCHBLT:
6003	{
6004	SVGA3dCmdLogicOpsStretchBlt pCmd = (SVGA3dCmdLogicOpsStretchBlt )pvCmd;
6005	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6006	rcParse = vmsvga3dCmdLogicOpsStretchBlt(pThisCC, idDXContext, pCmd, cbCmd);
6007	break;
6008	}
6009
6010	case SVGA_3D_CMD_LOGICOPS_COLORFILL:
6011	{
6012	SVGA3dCmdLogicOpsColorFill pCmd = (SVGA3dCmdLogicOpsColorFill )pvCmd;
6013	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6014	rcParse = vmsvga3dCmdLogicOpsColorFill(pThisCC, idDXContext, pCmd, cbCmd);
6015	break;
6016	}
6017
6018	case SVGA_3D_CMD_LOGICOPS_ALPHABLEND:
6019	{
6020	SVGA3dCmdLogicOpsAlphaBlend pCmd = (SVGA3dCmdLogicOpsAlphaBlend )pvCmd;
6021	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6022	rcParse = vmsvga3dCmdLogicOpsAlphaBlend(pThisCC, idDXContext, pCmd, cbCmd);
6023	break;
6024	}
6025
6026	case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND:
6027	{
6028	SVGA3dCmdLogicOpsClearTypeBlend pCmd = (SVGA3dCmdLogicOpsClearTypeBlend )pvCmd;
6029	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6030	rcParse = vmsvga3dCmdLogicOpsClearTypeBlend(pThisCC, idDXContext, pCmd, cbCmd);
6031	break;
6032	}
6033
6034	case SVGA_3D_CMD_RESERVED2_1:
6035	{
6036	VMSVGA_3D_CMD_NOTIMPL();
6037	break;
6038	}
6039
6040	case SVGA_3D_CMD_RESERVED2_2:
6041	{
6042	VMSVGA_3D_CMD_NOTIMPL();
6043	break;
6044	}
6045
6046	case SVGA_3D_CMD_DEFINE_GB_SURFACE_V4:
6047	{
6048	SVGA3dCmdDefineGBSurface_v4 pCmd = (SVGA3dCmdDefineGBSurface_v4 )pvCmd;
6049	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6050	rcParse = vmsvga3dCmdDefineGBSurface_v4(pThisCC, pCmd);
6051	break;
6052	}
6053
6054	case SVGA_3D_CMD_DX_SET_CS_UA_VIEWS:
6055	{
6056	SVGA3dCmdDXSetCSUAViews pCmd = (SVGA3dCmdDXSetCSUAViews )pvCmd;
6057	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6058	rcParse = vmsvga3dCmdDXSetCSUAViews(pThisCC, idDXContext, pCmd, cbCmd);
6059	break;
6060	}
6061
6062	case SVGA_3D_CMD_DX_SET_MIN_LOD:
6063	{
6064	SVGA3dCmdDXSetMinLOD pCmd = (SVGA3dCmdDXSetMinLOD )pvCmd;
6065	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6066	rcParse = vmsvga3dCmdDXSetMinLOD(pThisCC, idDXContext, pCmd, cbCmd);
6067	break;
6068	}
6069
6070	case SVGA_3D_CMD_RESERVED2_3:
6071	{
6072	VMSVGA_3D_CMD_NOTIMPL();
6073	break;
6074	}
6075
6076	case SVGA_3D_CMD_RESERVED2_4:
6077	{
6078	VMSVGA_3D_CMD_NOTIMPL();
6079	break;
6080	}
6081
6082	case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2:
6083	{
6084	SVGA3dCmdDXDefineDepthStencilView_v2 pCmd = (SVGA3dCmdDXDefineDepthStencilView_v2 )pvCmd;
6085	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6086	rcParse = vmsvga3dCmdDXDefineDepthStencilView_v2(pThisCC, idDXContext, pCmd, cbCmd);
6087	break;
6088	}
6089
6090	case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB:
6091	{
6092	SVGA3dCmdDXDefineStreamOutputWithMob pCmd = (SVGA3dCmdDXDefineStreamOutputWithMob )pvCmd;
6093	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6094	rcParse = vmsvga3dCmdDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd, cbCmd);
6095	break;
6096	}
6097
6098	case SVGA_3D_CMD_DX_SET_SHADER_IFACE:
6099	{
6100	SVGA3dCmdDXSetShaderIface pCmd = (SVGA3dCmdDXSetShaderIface )pvCmd;
6101	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6102	rcParse = vmsvga3dCmdDXSetShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6103	break;
6104	}
6105
6106	case SVGA_3D_CMD_DX_BIND_STREAMOUTPUT:
6107	{
6108	SVGA3dCmdDXBindStreamOutput pCmd = (SVGA3dCmdDXBindStreamOutput )pvCmd;
6109	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6110	rcParse = vmsvga3dCmdDXBindStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
6111	break;
6112	}
6113
6114	case SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS:
6115	{
6116	SVGA3dCmdSurfaceStretchBltNonMSToMS pCmd = (SVGA3dCmdSurfaceStretchBltNonMSToMS )pvCmd;
6117	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6118	rcParse = vmsvga3dCmdSurfaceStretchBltNonMSToMS(pThisCC, idDXContext, pCmd, cbCmd);
6119	break;
6120	}
6121
6122	case SVGA_3D_CMD_DX_BIND_SHADER_IFACE:
6123	{
6124	SVGA3dCmdDXBindShaderIface pCmd = (SVGA3dCmdDXBindShaderIface )pvCmd;
6125	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6126	rcParse = vmsvga3dCmdDXBindShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6127	break;
6128	}
6129
6130	case SVGA_3D_CMD_VB_DX_CLEAR_RENDERTARGET_VIEW_REGION:
6131	{
6132	SVGA3dCmdVBDXClearRenderTargetViewRegion pCmd = (SVGA3dCmdVBDXClearRenderTargetViewRegion )pvCmd;
6133	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6134	rcParse = vmsvga3dCmdVBDXClearRenderTargetViewRegion(pThisCC, idDXContext, pCmd, cbCmd);
6135	break;
6136	}
6137
6138	/* Unsupported commands. */
6139	case SVGA_3D_CMD_DEAD4: /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
6140	case SVGA_3D_CMD_DEAD5: /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
6141	case SVGA_3D_CMD_DEAD6: /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
6142	case SVGA_3D_CMD_DEAD7: /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
6143	case SVGA_3D_CMD_DEAD8: /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
6144	case SVGA_3D_CMD_DEAD9: /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
6145	case SVGA_3D_CMD_DEAD10: /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
6146	case SVGA_3D_CMD_DEAD11: /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
6147	/* Prevent the compiler warning. */
6148	case SVGA_3D_CMD_LEGACY_BASE:
6149	case SVGA_3D_CMD_MAX:
6150	case SVGA_3D_CMD_FUTURE_MAX:
6151	/* No 'default' case */
6152	STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
6153	ASSERT_GUEST_MSG_FAILED(("enmCmdId=%d\n", enmCmdId));
6154	LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
6155	rcParse = VERR_NOT_IMPLEMENTED;
6156	break;
6157	}
6158
6159	return VINF_SUCCESS;
6160	// return rcParse;
6161	}
6162	# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
6163	#endif /* VBOX_WITH_VMSVGA3D */
6164
6165
6166	/*
6167	*
6168	* Handlers for FIFO commands.
6169	*
6170	* Every handler takes the following parameters:
6171	*
6172	* pThis The shared VGA/VMSVGA state.
6173	* pThisCC The VGA/VMSVGA state for ring-3.
6174	* pCmd The command data.
6175	*/
6176
6177
6178	/* SVGA_CMD_UPDATE */
6179	void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
6180	{
6181	RT_NOREF(pThis);
6182	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6183
6184	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
6185	Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
6186
6187	/** @todo Multiple screens? */
6188	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6189	if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6190	return;
6191
6192	vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6193	}
6194
6195
6196	/* SVGA_CMD_UPDATE_VERBOSE */
6197	void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
6198	{
6199	RT_NOREF(pThis);
6200	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6201
6202	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
6203	Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
6204
6205	/** @todo Multiple screens? */
6206	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6207	if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6208	return;
6209
6210	vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6211	}
6212
6213
6214	/* SVGA_CMD_RECT_FILL */
6215	void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
6216	{
6217	RT_NOREF(pThis, pCmd);
6218	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6219
6220	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
6221	Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6222	LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
6223	}
6224
6225
6226	/* SVGA_CMD_RECT_COPY */
6227	void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
6228	{
6229	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6230
6231	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
6232	Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6233
6234	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6235	AssertPtrReturnVoid(pScreen);
6236
6237	/* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6238	ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6239	ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6240	ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6241	ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6242	ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6243	ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6244
6245	vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6246	pCmd->width, pCmd->height, pThis->vram_size);
6247	vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6248	}
6249
6250
6251	/* SVGA_CMD_RECT_ROP_COPY */
6252	void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
6253	{
6254	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6255
6256	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
6257	Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6258
6259	if (pCmd->rop != SVGA_ROP_COPY)
6260	{
6261	/* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
6262	* as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
6263	* respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
6264	* SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
6265	*/
6266	LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
6267	pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6268	return;
6269	}
6270
6271	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6272	AssertPtrReturnVoid(pScreen);
6273
6274	/* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6275	ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6276	ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6277	ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6278	ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6279	ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6280	ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6281
6282	vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6283	pCmd->width, pCmd->height, pThis->vram_size);
6284	vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6285	}
6286
6287
6288	/* SVGA_CMD_DISPLAY_CURSOR */
6289	void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
6290	{
6291	RT_NOREF(pThis, pCmd);
6292	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6293
6294	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
6295	Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
6296	LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
6297	}
6298
6299
6300	/* SVGA_CMD_MOVE_CURSOR */
6301	void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
6302	{
6303	RT_NOREF(pThis, pCmd);
6304	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6305
6306	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
6307	Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
6308	LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
6309	}
6310
6311
6312	/* SVGA_CMD_DEFINE_CURSOR */
6313	void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
6314	{
6315	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6316
6317	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
6318	Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
6319	pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
6320
6321	ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6322	ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
6323	ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
6324	RT_UNTRUSTED_VALIDATED_FENCE();
6325
6326	uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
6327	uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
6328	uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
6329
6330	uint8_t const pbSrcAndMask = (uint8_t const )(pCmd + 1);
6331	uint8_t const pbSrcXorMask = (uint8_t const )(pCmd + 1) + cbSrcAndMask;
6332
6333	uint32_t const cx = pCmd->width;
6334	uint32_t const cy = pCmd->height;
6335
6336	/*
6337	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
6338	* The AND data uses 8-bit aligned scanlines.
6339	* The XOR data must be starting on a 32-bit boundrary.
6340	*/
6341	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
6342	uint32_t cbDstAndMask = cbDstAndLine * cy;
6343	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
6344	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
6345
6346	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
6347	AssertReturnVoid(pbCopy);
6348
6349	/* Convert the AND mask. */
6350	uint8_t *pbDst = pbCopy;
6351	uint8_t const *pbSrc = pbSrcAndMask;
6352	switch (pCmd->andMaskDepth)
6353	{
6354	case 1:
6355	if (cbSrcAndLine == cbDstAndLine)
6356	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
6357	else
6358	{
6359	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
6360	for (uint32_t y = 0; y < cy; y++)
6361	{
6362	memcpy(pbDst, pbSrc, cbDstAndLine);
6363	pbDst += cbDstAndLine;
6364	pbSrc += cbSrcAndLine;
6365	}
6366	}
6367	break;
6368	/* Should take the XOR mask into account for the multi-bit AND mask. */
6369	case 8:
6370	for (uint32_t y = 0; y < cy; y++)
6371	{
6372	for (uint32_t x = 0; x < cx; )
6373	{
6374	uint8_t bDst = 0;
6375	uint8_t fBit = 0x80;
6376	do
6377	{
6378	uintptr_t const idxPal = pbSrc[x] * 3;
6379	if ((( pThis->last_palette[idxPal]
6380	\| (pThis->last_palette[idxPal] >> 8)
6381	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
6382	bDst \|= fBit;
6383	fBit >>= 1;
6384	x++;
6385	} while (x < cx && (x & 7));
6386	pbDst[(x - 1) / 8] = bDst;
6387	}
6388	pbDst += cbDstAndLine;
6389	pbSrc += cbSrcAndLine;
6390	}
6391	break;
6392	case 15:
6393	for (uint32_t y = 0; y < cy; y++)
6394	{
6395	for (uint32_t x = 0; x < cx; )
6396	{
6397	uint8_t bDst = 0;
6398	uint8_t fBit = 0x80;
6399	do
6400	{
6401	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
6402	bDst \|= fBit;
6403	fBit >>= 1;
6404	x++;
6405	} while (x < cx && (x & 7));
6406	pbDst[(x - 1) / 8] = bDst;
6407	}
6408	pbDst += cbDstAndLine;
6409	pbSrc += cbSrcAndLine;
6410	}
6411	break;
6412	case 16:
6413	for (uint32_t y = 0; y < cy; y++)
6414	{
6415	for (uint32_t x = 0; x < cx; )
6416	{
6417	uint8_t bDst = 0;
6418	uint8_t fBit = 0x80;
6419	do
6420	{
6421	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
6422	bDst \|= fBit;
6423	fBit >>= 1;
6424	x++;
6425	} while (x < cx && (x & 7));
6426	pbDst[(x - 1) / 8] = bDst;
6427	}
6428	pbDst += cbDstAndLine;
6429	pbSrc += cbSrcAndLine;
6430	}
6431	break;
6432	case 24:
6433	for (uint32_t y = 0; y < cy; y++)
6434	{
6435	for (uint32_t x = 0; x < cx; )
6436	{
6437	uint8_t bDst = 0;
6438	uint8_t fBit = 0x80;
6439	do
6440	{
6441	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
6442	bDst \|= fBit;
6443	fBit >>= 1;
6444	x++;
6445	} while (x < cx && (x & 7));
6446	pbDst[(x - 1) / 8] = bDst;
6447	}
6448	pbDst += cbDstAndLine;
6449	pbSrc += cbSrcAndLine;
6450	}
6451	break;
6452	case 32:
6453	for (uint32_t y = 0; y < cy; y++)
6454	{
6455	for (uint32_t x = 0; x < cx; )
6456	{
6457	uint8_t bDst = 0;
6458	uint8_t fBit = 0x80;
6459	do
6460	{
6461	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
6462	bDst \|= fBit;
6463	fBit >>= 1;
6464	x++;
6465	} while (x < cx && (x & 7));
6466	pbDst[(x - 1) / 8] = bDst;
6467	}
6468	pbDst += cbDstAndLine;
6469	pbSrc += cbSrcAndLine;
6470	}
6471	break;
6472	default:
6473	RTMemFreeZ(pbCopy, cbCopy);
6474	AssertFailedReturnVoid();
6475	}
6476
6477	/* Convert the XOR mask. */
6478	uint32_t pu32Dst = (uint32_t )(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
6479	pbSrc = pbSrcXorMask;
6480	switch (pCmd->xorMaskDepth)
6481	{
6482	case 1:
6483	for (uint32_t y = 0; y < cy; y++)
6484	{
6485	for (uint32_t x = 0; x < cx; )
6486	{
6487	/* most significant bit is the left most one. */
6488	uint8_t bSrc = pbSrc[x / 8];
6489	do
6490	{
6491	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
6492	bSrc <<= 1;
6493	x++;
6494	} while ((x & 7) && x < cx);
6495	}
6496	pbSrc += cbSrcXorLine;
6497	}
6498	break;
6499	case 8:
6500	for (uint32_t y = 0; y < cy; y++)
6501	{
6502	for (uint32_t x = 0; x < cx; x++)
6503	{
6504	uint32_t u = pThis->last_palette[pbSrc[x]];
6505	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
6506	}
6507	pbSrc += cbSrcXorLine;
6508	}
6509	break;
6510	case 15: /* Src: RGB-5-5-5 */
6511	for (uint32_t y = 0; y < cy; y++)
6512	{
6513	for (uint32_t x = 0; x < cx; x++)
6514	{
6515	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6516	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6517	((uValue >> 5) & 0x1f) << 3,
6518	((uValue >> 10) & 0x1f) << 3, 0);
6519	}
6520	pbSrc += cbSrcXorLine;
6521	}
6522	break;
6523	case 16: /* Src: RGB-5-6-5 */
6524	for (uint32_t y = 0; y < cy; y++)
6525	{
6526	for (uint32_t x = 0; x < cx; x++)
6527	{
6528	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6529	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6530	((uValue >> 5) & 0x3f) << 2,
6531	((uValue >> 11) & 0x1f) << 3, 0);
6532	}
6533	pbSrc += cbSrcXorLine;
6534	}
6535	break;
6536	case 24:
6537	for (uint32_t y = 0; y < cy; y++)
6538	{
6539	for (uint32_t x = 0; x < cx; x++)
6540	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
6541	pbSrc += cbSrcXorLine;
6542	}
6543	break;
6544	case 32:
6545	for (uint32_t y = 0; y < cy; y++)
6546	{
6547	for (uint32_t x = 0; x < cx; x++)
6548	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
6549	pbSrc += cbSrcXorLine;
6550	}
6551	break;
6552	default:
6553	RTMemFreeZ(pbCopy, cbCopy);
6554	AssertFailedReturnVoid();
6555	}
6556
6557	/*
6558	* Pass it to the frontend/whatever.
6559	*/
6560	vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /fAlpha/, pCmd->hotspotX, pCmd->hotspotY,
6561	cx, cy, pbCopy, cbCopy);
6562	}
6563
6564
6565	/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
6566	void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
6567	{
6568	RT_NOREF(pThis);
6569	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6570
6571	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
6572	Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
6573
6574	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
6575	ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6576	RT_UNTRUSTED_VALIDATED_FENCE();
6577
6578	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
6579	uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
6580	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
6581	uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
6582	uint32_t cbCursorShape = cbAndMask + cbXorMask;
6583
6584	uint8_t pCursorCopy = (uint8_t )RTMemAlloc(cbCursorShape);
6585	AssertPtrReturnVoid(pCursorCopy);
6586
6587	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
6588	memset(pCursorCopy, 0xff, cbAndMask);
6589	/* Colour data */
6590	memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
6591
6592	vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /fAlpha/, pCmd->hotspotX, pCmd->hotspotY,
6593	pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
6594	}
6595
6596
6597	/* SVGA_CMD_ESCAPE */
6598	void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
6599	{
6600	RT_NOREF(pThis);
6601	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6602
6603	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
6604
6605	if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
6606	{
6607	ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
6608	RT_UNTRUSTED_VALIDATED_FENCE();
6609
6610	uint32_t const cmd = (uint32_t )(pCmd + 1);
6611	Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
6612
6613	switch (cmd)
6614	{
6615	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
6616	{
6617	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pCmd + 1);
6618	ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
6619	RT_UNTRUSTED_VALIDATED_FENCE();
6620
6621	uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
6622
6623	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
6624	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
6625	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
6626	RT_NOREF_PV(pVideoCmd);
6627	break;
6628	}
6629
6630	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
6631	{
6632	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pCmd + 1);
6633	ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
6634	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
6635	RT_NOREF_PV(pVideoCmd);
6636	break;
6637	}
6638
6639	default:
6640	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
6641	break;
6642	}
6643	}
6644	else
6645	Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
6646	}
6647
6648
6649	/* SVGA_CMD_DEFINE_SCREEN */
6650	void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
6651	{
6652	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6653
6654	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
6655	Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
6656	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
6657	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
6658
6659	uint32_t const idScreen = pCmd->screen.id;
6660	ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6661
6662	uint32_t const uWidth = pCmd->screen.size.width;
6663	ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
6664
6665	uint32_t const uHeight = pCmd->screen.size.height;
6666	ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
6667
6668	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
6669	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
6670	ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
6671
6672	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
6673	ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
6674
6675	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
6676	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
6677	ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
6678	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
6679	RT_UNTRUSTED_VALIDATED_FENCE();
6680
6681	VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6682	pScreen->fDefined = true;
6683	pScreen->fModified = true;
6684	pScreen->fuScreen = pCmd->screen.flags;
6685	pScreen->idScreen = idScreen;
6686	if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING)))
6687	{
6688	/* Not blanked. */
6689	ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
6690	RT_UNTRUSTED_VALIDATED_FENCE();
6691
6692	pScreen->xOrigin = pCmd->screen.root.x;
6693	pScreen->yOrigin = pCmd->screen.root.y;
6694	pScreen->cWidth = uWidth;
6695	pScreen->cHeight = uHeight;
6696	pScreen->offVRAM = uScreenOffset;
6697	pScreen->cbPitch = cbPitch;
6698	pScreen->cBpp = 32;
6699	}
6700	else
6701	{
6702	/* Screen blanked. Keep old values. */
6703	}
6704
6705	pThis->svga.fGFBRegisters = false;
6706	vmsvgaR3ChangeMode(pThis, pThisCC);
6707
6708	#ifdef VBOX_WITH_VMSVGA3D
6709	if (RT_LIKELY(pThis->svga.f3DEnabled))
6710	vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
6711	#endif
6712	}
6713
6714
6715	/* SVGA_CMD_DESTROY_SCREEN */
6716	void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
6717	{
6718	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6719
6720	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
6721	Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
6722
6723	uint32_t const idScreen = pCmd->screenId;
6724	ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6725	RT_UNTRUSTED_VALIDATED_FENCE();
6726
6727	VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6728	pScreen->fModified = true;
6729	pScreen->fDefined = false;
6730	pScreen->idScreen = idScreen;
6731
6732	#ifdef VBOX_WITH_VMSVGA3D
6733	if (RT_LIKELY(pThis->svga.f3DEnabled))
6734	vmsvga3dDestroyScreen(pThisCC, pScreen);
6735	#endif
6736	vmsvgaR3ChangeMode(pThis, pThisCC);
6737	}
6738
6739
6740	/* SVGA_CMD_DEFINE_GMRFB */
6741	void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
6742	{
6743	RT_NOREF(pThis);
6744	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6745
6746	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
6747	Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
6748	pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
6749
6750	pSvgaR3State->GMRFB.ptr = pCmd->ptr;
6751	pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
6752	pSvgaR3State->GMRFB.format = pCmd->format;
6753	}
6754
6755
6756	/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
6757	void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
6758	{
6759	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6760
6761	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
6762	Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
6763	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
6764
6765	ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6766	RT_UNTRUSTED_VALIDATED_FENCE();
6767
6768	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
6769	AssertPtrReturnVoid(pScreen);
6770
6771	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
6772	AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6773
6774	/* Clip destRect to the screen dimensions. */
6775	SVGASignedRect screenRect;
6776	screenRect.left = 0;
6777	screenRect.top = 0;
6778	screenRect.right = pScreen->cWidth;
6779	screenRect.bottom = pScreen->cHeight;
6780	SVGASignedRect clipRect = pCmd->destRect;
6781	vmsvgaR3ClipRect(&screenRect, &clipRect);
6782	RT_UNTRUSTED_VALIDATED_FENCE();
6783
6784	uint32_t const width = clipRect.right - clipRect.left;
6785	uint32_t const height = clipRect.bottom - clipRect.top;
6786
6787	if ( width == 0
6788	\|\| height == 0)
6789	return; /* Nothing to do. */
6790
6791	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
6792	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
6793
6794	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
6795	* Prepare parameters for vmsvgaR3GmrTransfer.
6796	*/
6797	AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6798
6799	/* Destination: host buffer which describes the screen 0 VRAM.
6800	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6801	*/
6802	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6803	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6804	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6805	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6806	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6807	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6808	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6809	+ cbScanline * clipRect.top;
6810	int32_t const cbHstPitch = cbScanline;
6811
6812	/* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6813	SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6814	uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6815	+ pSvgaR3State->GMRFB.bytesPerLine * srcy;
6816	int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6817
6818	int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
6819	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6820	gstPtr, offGst, cbGstPitch,
6821	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6822	AssertRC(rc);
6823	vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
6824	}
6825
6826
6827	/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
6828	void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
6829	{
6830	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6831
6832	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
6833	/* Note! This can fetch 3d render results as well!! */
6834	Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
6835	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
6836
6837	ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6838	RT_UNTRUSTED_VALIDATED_FENCE();
6839
6840	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
6841	AssertPtrReturnVoid(pScreen);
6842
6843	/** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
6844	AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6845
6846	/* Clip destRect to the screen dimensions. */
6847	SVGASignedRect screenRect;
6848	screenRect.left = 0;
6849	screenRect.top = 0;
6850	screenRect.right = pScreen->cWidth;
6851	screenRect.bottom = pScreen->cHeight;
6852	SVGASignedRect clipRect = pCmd->srcRect;
6853	vmsvgaR3ClipRect(&screenRect, &clipRect);
6854	RT_UNTRUSTED_VALIDATED_FENCE();
6855
6856	uint32_t const width = clipRect.right - clipRect.left;
6857	uint32_t const height = clipRect.bottom - clipRect.top;
6858
6859	if ( width == 0
6860	\|\| height == 0)
6861	return; /* Nothing to do. */
6862
6863	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
6864	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
6865
6866	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
6867	* Prepare parameters for vmsvgaR3GmrTransfer.
6868	*/
6869	AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6870
6871	/* Source: host buffer which describes the screen 0 VRAM.
6872	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6873	*/
6874	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6875	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6876	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6877	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6878	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6879	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6880	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6881	+ cbScanline * clipRect.top;
6882	int32_t const cbHstPitch = cbScanline;
6883
6884	/* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6885	SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6886	uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6887	+ pSvgaR3State->GMRFB.bytesPerLine * dsty;
6888	int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6889
6890	int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
6891	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6892	gstPtr, offGst, cbGstPitch,
6893	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6894	AssertRC(rc);
6895	}
6896
6897
6898	/* SVGA_CMD_ANNOTATION_FILL */
6899	void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
6900	{
6901	RT_NOREF(pThis);
6902	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6903
6904	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
6905	Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
6906
6907	pSvgaR3State->colorAnnotation = pCmd->color;
6908	}
6909
6910
6911	/* SVGA_CMD_ANNOTATION_COPY */
6912	void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
6913	{
6914	RT_NOREF(pThis, pCmd);
6915	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6916
6917	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
6918	Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
6919
6920	AssertFailed();
6921	}
6922
6923
6924	#ifdef VBOX_WITH_VMSVGA3D
6925	/* SVGA_CMD_DEFINE_GMR2 */
6926	void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
6927	{
6928	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6929
6930	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
6931	Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
6932
6933	/* Validate current GMR id. */
6934	ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6935	ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
6936	RT_UNTRUSTED_VALIDATED_FENCE();
6937
6938	if (!pCmd->numPages)
6939	{
6940	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
6941	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6942	}
6943	else
6944	{
6945	PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6946	if (pGMR->cMaxPages)
6947	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
6948
6949	/* Not sure if we should always free the descriptor, but for simplicity
6950	we do so if the new size is smaller than the current. */
6951	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
6952	if (pGMR->cbTotal / X86_PAGE_SIZE > pCmd->numPages)
6953	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6954
6955	pGMR->cMaxPages = pCmd->numPages;
6956	/* The rest is done by the REMAP_GMR2 command. */
6957	}
6958	}
6959
6960
6961	/* SVGA_CMD_REMAP_GMR2 */
6962	void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
6963	{
6964	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6965
6966	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
6967	Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
6968
6969	/* Validate current GMR id and size. */
6970	ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6971	RT_UNTRUSTED_VALIDATED_FENCE();
6972	PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6973	ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
6974	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
6975	ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
6976
6977	if (pCmd->numPages == 0)
6978	return;
6979	RT_UNTRUSTED_VALIDATED_FENCE();
6980
6981	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
6982	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
6983
6984	/*
6985	* We flatten the existing descriptors into a page array, overwrite the
6986	* pages specified in this command and then recompress the descriptor.
6987	*/
6988	/** @todo Optimize the GMR remap algorithm! */
6989
6990	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
6991	uint64_t *paNewPage64 = NULL;
6992	if (pGMR->paDesc)
6993	{
6994	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
6995
6996	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
6997	AssertPtrReturnVoid(paNewPage64);
6998
6999	uint32_t idxPage = 0;
7000	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
7001	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
7002	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
7003	AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
7004	RT_UNTRUSTED_VALIDATED_FENCE();
7005	}
7006
7007	/* Free the old GMR if present. */
7008	if (pGMR->paDesc)
7009	RTMemFree(pGMR->paDesc);
7010
7011	/* Allocate the maximum amount possible (everything non-continuous) */
7012	PVMSVGAGMRDESCRIPTOR paDescs;
7013	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
7014	AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
7015
7016	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
7017	{
7018	/** @todo */
7019	AssertFailed();
7020	pGMR->numDescriptors = 0;
7021	}
7022	else
7023	{
7024	uint32_t paPages32 = (uint32_t )(pCmd + 1);
7025	uint64_t paPages64 = (uint64_t )(pCmd + 1);
7026	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
7027
7028	uint32_t cPages;
7029	if (paNewPage64)
7030	{
7031	/* Overwrite the old page array with the new page values. */
7032	if (fGCPhys64)
7033	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
7034	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
7035	else
7036	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
7037	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
7038
7039	/* Use the updated page array instead of the command data. */
7040	fGCPhys64 = true;
7041	paPages64 = paNewPage64;
7042	cPages = cNewTotalPages;
7043	}
7044	else
7045	cPages = pCmd->numPages;
7046
7047	/* The first page. */
7048	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
7049	* applied to paNewPage64. */
7050	RTGCPHYS GCPhys;
7051	if (fGCPhys64)
7052	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
7053	else
7054	GCPhys = (RTGCPHYS)paPages32[0] << GUEST_PAGE_SHIFT;
7055	paDescs[0].GCPhys = GCPhys;
7056	paDescs[0].numPages = 1;
7057
7058	/* Subsequent pages. */
7059	uint32_t iDescriptor = 0;
7060	for (uint32_t i = 1; i < cPages; i++)
7061	{
7062	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
7063	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
7064	else
7065	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
7066
7067	/* Continuous physical memory? */
7068	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
7069	{
7070	Assert(paDescs[iDescriptor].numPages);
7071	paDescs[iDescriptor].numPages++;
7072	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
7073	}
7074	else
7075	{
7076	iDescriptor++;
7077	paDescs[iDescriptor].GCPhys = GCPhys;
7078	paDescs[iDescriptor].numPages = 1;
7079	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
7080	}
7081	}
7082
7083	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
7084	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
7085	pGMR->numDescriptors = iDescriptor + 1;
7086	}
7087
7088	if (paNewPage64)
7089	RTMemFree(paNewPage64);
7090	}
7091
7092
7093	/**
7094	* Free the specified GMR
7095	*
7096	* @param pThisCC The VGA/VMSVGA state for ring-3.
7097	* @param idGMR GMR id
7098	*/
7099	void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
7100	{
7101	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7102
7103	/* Free the old descriptor if present. */
7104	PGMR pGMR = &pSVGAState->paGMR[idGMR];
7105	if ( pGMR->numDescriptors
7106	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
7107	{
7108	# ifdef DEBUG_GMR_ACCESS
7109	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
7110	# endif
7111
7112	Assert(pGMR->paDesc);
7113	RTMemFree(pGMR->paDesc);
7114	pGMR->paDesc = NULL;
7115	pGMR->numDescriptors = 0;
7116	pGMR->cbTotal = 0;
7117	pGMR->cMaxPages = 0;
7118	}
7119	Assert(!pGMR->cMaxPages);
7120	Assert(!pGMR->cbTotal);
7121	}
7122	#endif /* VBOX_WITH_VMSVGA3D */
7123
7124
7125	/**
7126	* Copy between a GMR and a host memory buffer.
7127	*
7128	* @returns VBox status code.
7129	* @param pThis The shared VGA/VMSVGA instance data.
7130	* @param pThisCC The VGA/VMSVGA state for ring-3.
7131	* @param enmTransferType Transfer type (read/write)
7132	* @param pbHstBuf Host buffer pointer (valid)
7133	* @param cbHstBuf Size of host buffer (valid)
7134	* @param offHst Host buffer offset of the first scanline
7135	* @param cbHstPitch Destination buffer pitch
7136	* @param gstPtr GMR description
7137	* @param offGst Guest buffer offset of the first scanline
7138	* @param cbGstPitch Guest buffer pitch
7139	* @param cbWidth Width in bytes to copy
7140	* @param cHeight Number of scanllines to copy
7141	*/
7142	int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
7143	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
7144	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
7145	uint32_t cbWidth, uint32_t cHeight)
7146	{
7147	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7148	PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
7149	int rc;
7150
7151	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
7152	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
7153	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
7154	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
7155	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
7156
7157	PGMR pGMR;
7158	uint32_t cbGmr; /* The GMR size in bytes. */
7159	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7160	{
7161	pGMR = NULL;
7162	cbGmr = pThis->vram_size;
7163	}
7164	else
7165	{
7166	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
7167	RT_UNTRUSTED_VALIDATED_FENCE();
7168	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
7169	cbGmr = pGMR->cbTotal;
7170	}
7171
7172	/*
7173	* GMR
7174	*/
7175	/* Calculate GMR offset of the data to be copied. */
7176	AssertMsgReturn(gstPtr.offset < cbGmr,
7177	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7178	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7179	VERR_INVALID_PARAMETER);
7180	RT_UNTRUSTED_VALIDATED_FENCE();
7181	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
7182	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7183	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7184	VERR_INVALID_PARAMETER);
7185	RT_UNTRUSTED_VALIDATED_FENCE();
7186	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
7187
7188	/* Verify that cbWidth is less than scanline and fits into the GMR. */
7189	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
7190	AssertMsgReturn(cbGmrScanline != 0,
7191	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7192	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7193	VERR_INVALID_PARAMETER);
7194	RT_UNTRUSTED_VALIDATED_FENCE();
7195	AssertMsgReturn(cbWidth <= cbGmrScanline,
7196	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7197	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7198	VERR_INVALID_PARAMETER);
7199	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
7200	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7201	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7202	VERR_INVALID_PARAMETER);
7203	RT_UNTRUSTED_VALIDATED_FENCE();
7204
7205	/* How many bytes are available for the data in the GMR. */
7206	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
7207
7208	/* How many scanlines would fit into the available data. */
7209	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
7210	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
7211	if (cbWidth <= cbGmrLastScanline)
7212	++cGmrScanlines;
7213
7214	if (cHeight > cGmrScanlines)
7215	cHeight = cGmrScanlines;
7216
7217	AssertMsgReturn(cHeight > 0,
7218	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7219	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7220	VERR_INVALID_PARAMETER);
7221	RT_UNTRUSTED_VALIDATED_FENCE();
7222
7223	/*
7224	* Host buffer.
7225	*/
7226	AssertMsgReturn(offHst < cbHstBuf,
7227	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7228	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7229	VERR_INVALID_PARAMETER);
7230
7231	/* Verify that cbWidth is less than scanline and fits into the buffer. */
7232	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
7233	AssertMsgReturn(cbHstScanline != 0,
7234	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7235	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7236	VERR_INVALID_PARAMETER);
7237	AssertMsgReturn(cbWidth <= cbHstScanline,
7238	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7239	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7240	VERR_INVALID_PARAMETER);
7241	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
7242	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7243	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7244	VERR_INVALID_PARAMETER);
7245
7246	/* How many bytes are available for the data in the buffer. */
7247	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
7248
7249	/* How many scanlines would fit into the available data. */
7250	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
7251	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
7252	if (cbWidth <= cbHstLastScanline)
7253	++cHstScanlines;
7254
7255	if (cHeight > cHstScanlines)
7256	cHeight = cHstScanlines;
7257
7258	AssertMsgReturn(cHeight > 0,
7259	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7260	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7261	VERR_INVALID_PARAMETER);
7262
7263	uint8_t *pbHst = pbHstBuf + offHst;
7264
7265	/* Shortcut for the framebuffer. */
7266	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7267	{
7268	uint8_t *pbGst = pThisCC->pbVRam + offGmr;
7269
7270	uint8_t const *pbSrc;
7271	int32_t cbSrcPitch;
7272	uint8_t *pbDst;
7273	int32_t cbDstPitch;
7274
7275	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
7276	{
7277	pbSrc = pbHst;
7278	cbSrcPitch = cbHstPitch;
7279	pbDst = pbGst;
7280	cbDstPitch = cbGstPitch;
7281	}
7282	else
7283	{
7284	pbSrc = pbGst;
7285	cbSrcPitch = cbGstPitch;
7286	pbDst = pbHst;
7287	cbDstPitch = cbHstPitch;
7288	}
7289
7290	if ( cbWidth == (uint32_t)cbGstPitch
7291	&& cbGstPitch == cbHstPitch)
7292	{
7293	/* Entire scanlines, positive pitch. */
7294	memcpy(pbDst, pbSrc, cbWidth * cHeight);
7295	}
7296	else
7297	{
7298	for (uint32_t i = 0; i < cHeight; ++i)
7299	{
7300	memcpy(pbDst, pbSrc, cbWidth);
7301
7302	pbDst += cbDstPitch;
7303	pbSrc += cbSrcPitch;
7304	}
7305	}
7306	return VINF_SUCCESS;
7307	}
7308
7309	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
7310	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
7311
7312	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
7313	uint32_t iDesc = 0; /* Index in the descriptor array. */
7314	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
7315	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
7316	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
7317	for (uint32_t i = 0; i < cHeight; ++i)
7318	{
7319	uint32_t cbCurrentWidth = cbWidth;
7320	uint32_t offGmrCurrent = offGmrScanline;
7321	uint8_t *pbCurrentHost = pbHstScanline;
7322
7323	/* Find the right descriptor */
7324	while (offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE <= offGmrCurrent)
7325	{
7326	offDesc += paDesc[iDesc].numPages * GUEST_PAGE_SIZE;
7327	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
7328	++iDesc;
7329	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7330	}
7331
7332	while (cbCurrentWidth)
7333	{
7334	uint32_t cbToCopy;
7335
7336	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE)
7337	cbToCopy = cbCurrentWidth;
7338	else
7339	{
7340	cbToCopy = (offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE - offGmrCurrent);
7341	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
7342	}
7343
7344	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
7345
7346	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
7347
7348	/*
7349	* We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read\|Write] as the
7350	* guest-side VMSVGA driver seems to allocate non-DMA (physical memory) addresses,
7351	* see @bugref{9654#c75}.
7352	*/
7353	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
7354	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7355	else
7356	rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7357	AssertRCBreak(rc);
7358
7359	cbCurrentWidth -= cbToCopy;
7360	offGmrCurrent += cbToCopy;
7361	pbCurrentHost += cbToCopy;
7362
7363	/* Go to the next descriptor if there's anything left. */
7364	if (cbCurrentWidth)
7365	{
7366	offDesc += paDesc[iDesc].numPages * GUEST_PAGE_SIZE;
7367	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
7368	++iDesc;
7369	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7370	}
7371	}
7372
7373	offGmrScanline += cbGstPitch;
7374	pbHstScanline += cbHstPitch;
7375	}
7376
7377	return VINF_SUCCESS;
7378	}
7379
7380
7381	/**
7382	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
7383	*
7384	* @param pSizeSrc Source surface dimensions.
7385	* @param pSizeDest Destination surface dimensions.
7386	* @param pBox Coordinates to be clipped.
7387	*/
7388	void vmsvgaR3ClipCopyBox(const SVGA3dSize pSizeSrc, const SVGA3dSize pSizeDest, SVGA3dCopyBox *pBox)
7389	{
7390	/* Src x, w */
7391	if (pBox->srcx > pSizeSrc->width)
7392	pBox->srcx = pSizeSrc->width;
7393	if (pBox->w > pSizeSrc->width - pBox->srcx)
7394	pBox->w = pSizeSrc->width - pBox->srcx;
7395
7396	/* Src y, h */
7397	if (pBox->srcy > pSizeSrc->height)
7398	pBox->srcy = pSizeSrc->height;
7399	if (pBox->h > pSizeSrc->height - pBox->srcy)
7400	pBox->h = pSizeSrc->height - pBox->srcy;
7401
7402	/* Src z, d */
7403	if (pBox->srcz > pSizeSrc->depth)
7404	pBox->srcz = pSizeSrc->depth;
7405	if (pBox->d > pSizeSrc->depth - pBox->srcz)
7406	pBox->d = pSizeSrc->depth - pBox->srcz;
7407
7408	/* Dest x, w */
7409	if (pBox->x > pSizeDest->width)
7410	pBox->x = pSizeDest->width;
7411	if (pBox->w > pSizeDest->width - pBox->x)
7412	pBox->w = pSizeDest->width - pBox->x;
7413
7414	/* Dest y, h */
7415	if (pBox->y > pSizeDest->height)
7416	pBox->y = pSizeDest->height;
7417	if (pBox->h > pSizeDest->height - pBox->y)
7418	pBox->h = pSizeDest->height - pBox->y;
7419
7420	/* Dest z, d */
7421	if (pBox->z > pSizeDest->depth)
7422	pBox->z = pSizeDest->depth;
7423	if (pBox->d > pSizeDest->depth - pBox->z)
7424	pBox->d = pSizeDest->depth - pBox->z;
7425	}
7426
7427
7428	/**
7429	* Unsigned coordinates in pBox. Clip to [0; pSize).
7430	*
7431	* @param pSize Source surface dimensions.
7432	* @param pBox Coordinates to be clipped.
7433	*/
7434	void vmsvgaR3ClipBox(const SVGA3dSize pSize, SVGA3dBox pBox)
7435	{
7436	/* x, w */
7437	if (pBox->x > pSize->width)
7438	pBox->x = pSize->width;
7439	if (pBox->w > pSize->width - pBox->x)
7440	pBox->w = pSize->width - pBox->x;
7441
7442	/* y, h */
7443	if (pBox->y > pSize->height)
7444	pBox->y = pSize->height;
7445	if (pBox->h > pSize->height - pBox->y)
7446	pBox->h = pSize->height - pBox->y;
7447
7448	/* z, d */
7449	if (pBox->z > pSize->depth)
7450	pBox->z = pSize->depth;
7451	if (pBox->d > pSize->depth - pBox->z)
7452	pBox->d = pSize->depth - pBox->z;
7453	}
7454
7455
7456	/**
7457	* Clip.
7458	*
7459	* @param pBound Bounding rectangle.
7460	* @param pRect Rectangle to be clipped.
7461	*/
7462	void vmsvgaR3ClipRect(SVGASignedRect const pBound, SVGASignedRect pRect)
7463	{
7464	int32_t left;
7465	int32_t top;
7466	int32_t right;
7467	int32_t bottom;
7468
7469	/* Right order. */
7470	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
7471	if (pRect->left < pRect->right)
7472	{
7473	left = pRect->left;
7474	right = pRect->right;
7475	}
7476	else
7477	{
7478	left = pRect->right;
7479	right = pRect->left;
7480	}
7481	if (pRect->top < pRect->bottom)
7482	{
7483	top = pRect->top;
7484	bottom = pRect->bottom;
7485	}
7486	else
7487	{
7488	top = pRect->bottom;
7489	bottom = pRect->top;
7490	}
7491
7492	if (left < pBound->left)
7493	left = pBound->left;
7494	if (right < pBound->left)
7495	right = pBound->left;
7496
7497	if (left > pBound->right)
7498	left = pBound->right;
7499	if (right > pBound->right)
7500	right = pBound->right;
7501
7502	if (top < pBound->top)
7503	top = pBound->top;
7504	if (bottom < pBound->top)
7505	bottom = pBound->top;
7506
7507	if (top > pBound->bottom)
7508	top = pBound->bottom;
7509	if (bottom > pBound->bottom)
7510	bottom = pBound->bottom;
7511
7512	pRect->left = left;
7513	pRect->right = right;
7514	pRect->top = top;
7515	pRect->bottom = bottom;
7516	}
7517
7518
7519	/**
7520	* Clip.
7521	*
7522	* @param pBound Bounding rectangle.
7523	* @param pRect Rectangle to be clipped.
7524	*/
7525	void vmsvgaR3Clip3dRect(SVGA3dRect const pBound, SVGA3dRect RT_UNTRUSTED_GUEST pRect)
7526	{
7527	uint32_t const leftBound = pBound->x;
7528	uint32_t const rightBound = pBound->x + pBound->w;
7529	uint32_t const topBound = pBound->y;
7530	uint32_t const bottomBound = pBound->y + pBound->h;
7531
7532	uint32_t x = pRect->x;
7533	uint32_t y = pRect->y;
7534	uint32_t w = pRect->w;
7535	uint32_t h = pRect->h;
7536
7537	/* Make sure that right and bottom coordinates can be safely computed. */
7538	if (x > rightBound)
7539	x = rightBound;
7540	if (w > rightBound - x)
7541	w = rightBound - x;
7542	if (y > bottomBound)
7543	y = bottomBound;
7544	if (h > bottomBound - y)
7545	h = bottomBound - y;
7546
7547	/* Switch from x, y, w, h to left, top, right, bottom. */
7548	uint32_t left = x;
7549	uint32_t right = x + w;
7550	uint32_t top = y;
7551	uint32_t bottom = y + h;
7552
7553	/* A standard left, right, bottom, top clipping. */
7554	if (left < leftBound)
7555	left = leftBound;
7556	if (right < leftBound)
7557	right = leftBound;
7558
7559	if (left > rightBound)
7560	left = rightBound;
7561	if (right > rightBound)
7562	right = rightBound;
7563
7564	if (top < topBound)
7565	top = topBound;
7566	if (bottom < topBound)
7567	bottom = topBound;
7568
7569	if (top > bottomBound)
7570	top = bottomBound;
7571	if (bottom > bottomBound)
7572	bottom = bottomBound;
7573
7574	/* Back to x, y, w, h representation. */
7575	pRect->x = left;
7576	pRect->y = top;
7577	pRect->w = right - left;
7578	pRect->h = bottom - top;
7579	}
7580

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp@ 98049

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