VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp@ 94377

Last change on this file since 94377 was 94377, checked in by vboxsync, 3 years ago

Devices/Graphics: surface mapping cleanup and fixes: bugref:9830
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 271.0 KB
Line 
1/* $Id: DevVGA-SVGA-cmd.cpp 94377 2022-03-25 18:26:29Z vboxsync $ */
2/** @file
3 * VMware SVGA device - implementation of VMSVGA commands.
4 */
5
6/*
7 * Copyright (C) 2013-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef IN_RING3
19# error "DevVGA-SVGA-cmd.cpp is only for ring-3 code"
20#endif
21
22
23#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
24#include <iprt/mem.h>
25#include <VBox/AssertGuest.h>
26#include <VBox/log.h>
27#include <VBox/vmm/pdmdev.h>
28#include <VBoxVideo.h>
29
30/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
31#include "DevVGA.h"
32
33/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
34#ifdef VBOX_WITH_VMSVGA3D
35# include "DevVGA-SVGA3d.h"
36#endif
37#include "DevVGA-SVGA-internal.h"
38
39#include <iprt/formats/bmp.h>
40#include <stdio.h>
41
42#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
43# define SVGA_CASE_ID2STR(idx) case idx: return #idx
44
45static const char *vmsvgaFifo3dCmdToString(SVGAFifo3dCmdId enmCmdId)
46{
47 switch (enmCmdId)
48 {
49 SVGA_CASE_ID2STR(SVGA_3D_CMD_LEGACY_BASE);
50 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
51 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
52 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
53 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
54 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
55 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
56 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
57 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
58 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
59 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
60 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
61 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
62 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
63 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
64 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
65 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
66 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
67 SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
68 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
69 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
70 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
71 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
72 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
73 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
74 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
75 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
76 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
77 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
78 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
79 SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
80 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
81 SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
82 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD4); /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
83 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD5); /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
84 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD6); /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
85 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD7); /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
86 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD8); /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
87 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD9); /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
88 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD10); /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
89 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD11); /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
90 SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
91 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
92 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
93 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD1);
94 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
95 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD12); /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
96 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD13); /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
97 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD14); /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
98 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD15); /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
99 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD16); /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
100 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD17); /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
101 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
102 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
103 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
104 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
105 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
106 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
107 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
108 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
109 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
110 SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
111 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
112 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
113 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
114 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
115 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
116 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
117 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
118 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
119 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
120 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
121 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
122 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
123 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
124 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
125 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
126 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
127 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
128 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
129 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
130 SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
131 SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
132 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
133 SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
134 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
135 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
136 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
137 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
138 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
139 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
140 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
141 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
142 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
143 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
144 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
145 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
146 SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
147 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
148 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
149 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
150 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
151 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
152 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
153 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
154 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
155 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
156 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
157 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
158 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
159 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
160 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
161 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
162 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
163 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
164 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
165 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
166 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
167 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
168 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
169 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
170 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
171 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
172 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
173 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
174 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
175 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
176 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
177 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
178 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
179 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
180 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
181 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
182 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
183 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
184 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
185 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
186 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
187 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
188 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
189 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
190 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRESENTBLT);
191 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
192 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
193 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
194 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
195 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
196 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
197 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
198 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
199 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
200 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
201 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
202 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
203 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
204 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
205 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
206 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
207 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
208 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
209 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
210 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
211 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
212 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
213 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
214 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
215 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
216 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
217 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
218 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
219 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
220 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
221 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
222 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
223 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
224 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
225 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
226 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
227 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
228 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
229 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
230 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
231 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
232 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
233 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET);
234 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET);
235 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET);
236 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
237 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_COPY);
238 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED1);
239 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2);
240 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED3);
241 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED4);
242 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED5);
243 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED6);
244 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED7);
245 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED8);
246 SVGA_CASE_ID2STR(SVGA_3D_CMD_GROW_OTABLE);
247 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GROW_COTABLE);
248 SVGA_CASE_ID2STR(SVGA_3D_CMD_INTRA_SURFACE_COPY);
249 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V3);
250 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESOLVE_COPY);
251 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_RESOLVE_COPY);
252 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT_REGION);
253 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT);
254 SVGA_CASE_ID2STR(SVGA_3D_CMD_WHOLE_SURFACE_COPY);
255 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_UA_VIEW);
256 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_UA_VIEW);
257 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT);
258 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT);
259 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT);
260 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_UA_VIEWS);
261 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT);
262 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT);
263 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH);
264 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH_INDIRECT);
265 SVGA_CASE_ID2STR(SVGA_3D_CMD_WRITE_ZERO_SURFACE);
266 SVGA_CASE_ID2STR(SVGA_3D_CMD_HINT_ZERO_SURFACE);
267 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER);
268 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT);
269 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
270 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
271 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
272 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
273 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
274 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
275 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_1);
276 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_2);
277 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4);
278 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS);
279 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_MIN_LOD);
280 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_3);
281 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_4);
282 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2);
283 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB);
284 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_IFACE);
285 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT);
286 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS);
287 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER_IFACE);
288 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAX);
289 SVGA_CASE_ID2STR(SVGA_3D_CMD_FUTURE_MAX);
290 }
291 return "UNKNOWN_3D";
292}
293
294/**
295 * FIFO command name lookup
296 *
297 * @returns FIFO command string or "UNKNOWN"
298 * @param u32Cmd FIFO command
299 */
300const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
301{
302 switch (u32Cmd)
303 {
304 SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
305 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
306 SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
307 SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
308 SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
309 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
310 SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
311 SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
312 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
313 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
314 SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
315 SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
316 SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
317 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
318 SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
319 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
320 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
321 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
322 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
323 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
324 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
325 SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
326 SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
327 SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
328 SVGA_CASE_ID2STR(SVGA_CMD_NOP);
329 SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
330 SVGA_CASE_ID2STR(SVGA_CMD_MAX);
331 default:
332 if ( u32Cmd >= SVGA_3D_CMD_BASE
333 && u32Cmd < SVGA_3D_CMD_MAX)
334 return vmsvgaFifo3dCmdToString((SVGAFifo3dCmdId)u32Cmd);
335 }
336 return "UNKNOWN";
337}
338# undef SVGA_CASE_ID2STR
339#endif /* LOG_ENABLED || VBOX_STRICT */
340
341
342/*
343 *
344 * Guest-Backed Objects (GBO).
345 *
346 */
347
348/**
349 * HC access handler for GBOs which require write protection, i.e. OTables, etc.
350 *
351 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
352 * @param pVM VM Handle.
353 * @param pVCpu The cross context CPU structure for the calling EMT.
354 * @param GCPhys The physical address the guest is writing to.
355 * @param pvPhys The HC mapping of that address.
356 * @param pvBuf What the guest is reading/writing.
357 * @param cbBuf How much it's reading/writing.
358 * @param enmAccessType The access type.
359 * @param enmOrigin Who is making the access.
360 * @param uUser The VMM automatically sets this to the address of
361 * the device instance.
362 */
363DECLCALLBACK(VBOXSTRICTRC)
364vmsvgaR3GboAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
365 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, uint64_t uUser)
366{
367 RT_NOREF(pVM, pVCpu, pvPhys, enmAccessType);
368
369 if (RT_LIKELY(enmOrigin == PGMACCESSORIGIN_DEVICE || enmOrigin == PGMACCESSORIGIN_DEBUGGER))
370 return VINF_PGM_HANDLER_DO_DEFAULT;
371
372 PPDMDEVINS pDevIns = (PPDMDEVINS)uUser;
373 AssertPtrReturn(pDevIns, VERR_INTERNAL_ERROR_4);
374 AssertReturn(pDevIns->u32Version == PDM_DEVINSR3_VERSION, VERR_INTERNAL_ERROR_5);
375 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
376 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
377 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
378
379 /*
380 * The guest is not allowed to access the memory.
381 * Set the error condition.
382 */
383 ASMAtomicWriteBool(&pThis->svga.fBadGuest, true);
384
385 /* Try to find the GBO which the guest is accessing. */
386 char const *pszTarget = NULL;
387 for (uint32_t i = 0; i < RT_ELEMENTS(pSvgaR3State->aGboOTables) && !pszTarget; ++i)
388 {
389 PVMSVGAGBO pGbo = &pSvgaR3State->aGboOTables[i];
390 if (pGbo->cDescriptors)
391 {
392 for (uint32_t j = 0; j < pGbo->cDescriptors; ++j)
393 {
394 if ( GCPhys >= pGbo->paDescriptors[j].GCPhys
395 && GCPhys < pGbo->paDescriptors[j].GCPhys + pGbo->paDescriptors[j].cPages * GUEST_PAGE_SIZE)
396 {
397 switch (i)
398 {
399 case SVGA_OTABLE_MOB: pszTarget = "SVGA_OTABLE_MOB"; break;
400 case SVGA_OTABLE_SURFACE: pszTarget = "SVGA_OTABLE_SURFACE"; break;
401 case SVGA_OTABLE_CONTEXT: pszTarget = "SVGA_OTABLE_CONTEXT"; break;
402 case SVGA_OTABLE_SHADER: pszTarget = "SVGA_OTABLE_SHADER"; break;
403 case SVGA_OTABLE_SCREENTARGET: pszTarget = "SVGA_OTABLE_SCREENTARGET"; break;
404 case SVGA_OTABLE_DXCONTEXT: pszTarget = "SVGA_OTABLE_DXCONTEXT"; break;
405 default: pszTarget = "Unknown OTABLE"; break;
406 }
407 break;
408 }
409 }
410 }
411 }
412
413 LogRelMax(8, ("VMSVGA: invalid guest access to page %RGp, target %s:\n"
414 "%.*Rhxd\n",
415 GCPhys, pszTarget ? pszTarget : "unknown", RT_MIN(cbBuf, 256), pvBuf));
416
417 return VINF_PGM_HANDLER_DO_DEFAULT;
418}
419
420#ifdef VBOX_WITH_VMSVGA3D
421
422static int vmsvgaR3GboCreate(PVMSVGAR3STATE pSvgaR3State, SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, bool fGCPhys64, bool fWriteProtected, PVMSVGAGBO pGbo)
423{
424 ASSERT_GUEST_RETURN(sizeInBytes <= _128M, VERR_INVALID_PARAMETER); /** @todo Less than SVGA_REG_MOB_MAX_SIZE */
425
426 /*
427 * The 'baseAddress' is a page number and points to the 'root page' of the GBO.
428 * Content of the root page depends on the ptDepth value:
429 * SVGA3D_MOBFMT_PTDEPTH[64]_0 - the only data page;
430 * SVGA3D_MOBFMT_PTDEPTH[64]_1 - array of page numbers for data pages;
431 * SVGA3D_MOBFMT_PTDEPTH[64]_2 - array of page numbers for SVGA3D_MOBFMT_PTDEPTH[64]_1 pages.
432 * The code below extracts the page addresses of the GBO.
433 */
434
435 /* Verify and normalize the ptDepth value. */
436 if (RT_LIKELY( ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0
437 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1
438 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2))
439 ASSERT_GUEST_RETURN(fGCPhys64, VERR_INVALID_PARAMETER);
440 else if ( ptDepth == SVGA3D_MOBFMT_PTDEPTH_0
441 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_1
442 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_2)
443 {
444 ASSERT_GUEST_RETURN(!fGCPhys64, VERR_INVALID_PARAMETER);
445 /* Shift ptDepth to the SVGA3D_MOBFMT_PTDEPTH64_x range. */
446 ptDepth = (SVGAMobFormat)(ptDepth + SVGA3D_MOBFMT_PTDEPTH64_0 - SVGA3D_MOBFMT_PTDEPTH_0);
447 }
448 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
449 { }
450 else
451 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
452
453 uint32_t const cPPNsPerPage = X86_PAGE_SIZE / (fGCPhys64 ? sizeof(PPN64) : sizeof(PPN));
454
455 pGbo->cbTotal = sizeInBytes;
456 pGbo->cTotalPages = (sizeInBytes + X86_PAGE_SIZE - 1) >> X86_PAGE_SHIFT;
457
458 /* Allocate the maximum amount possible (everything non-continuous) */
459 PVMSVGAGBODESCRIPTOR paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAlloc(pGbo->cTotalPages * sizeof(VMSVGAGBODESCRIPTOR));
460 AssertReturn(paDescriptors, VERR_NO_MEMORY);
461
462 int rc = VINF_SUCCESS;
463 if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0)
464 {
465 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages == 1,
466 RTMemFree(paDescriptors),
467 VERR_INVALID_PARAMETER);
468
469 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
470 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
471 paDescriptors[0].GCPhys = GCPhys;
472 paDescriptors[0].cPages = 1;
473 }
474 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1)
475 {
476 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage,
477 RTMemFree(paDescriptors),
478 VERR_INVALID_PARAMETER);
479
480 /* Read the root page. */
481 uint8_t au8RootPage[X86_PAGE_SIZE];
482 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
483 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPage, sizeof(au8RootPage));
484 if (RT_SUCCESS(rc))
485 {
486 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
487 PPN *paPPN32 = (PPN *)&au8RootPage[0];
488 for (uint32_t iPPN = 0; iPPN < pGbo->cTotalPages; ++iPPN)
489 {
490 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
491 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
492 paDescriptors[iPPN].GCPhys = GCPhys;
493 paDescriptors[iPPN].cPages = 1;
494 }
495 }
496 }
497 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2)
498 {
499 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage * cPPNsPerPage,
500 RTMemFree(paDescriptors),
501 VERR_INVALID_PARAMETER);
502
503 /* Read the Level2 root page. */
504 uint8_t au8RootPageLevel2[X86_PAGE_SIZE];
505 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
506 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPageLevel2, sizeof(au8RootPageLevel2));
507 if (RT_SUCCESS(rc))
508 {
509 uint32_t cPagesLeft = pGbo->cTotalPages;
510
511 PPN64 *paPPN64Level2 = (PPN64 *)&au8RootPageLevel2[0];
512 PPN *paPPN32Level2 = (PPN *)&au8RootPageLevel2[0];
513
514 uint32_t const cPPNsLevel2 = (pGbo->cTotalPages + cPPNsPerPage - 1) / cPPNsPerPage;
515 for (uint32_t iPPNLevel2 = 0; iPPNLevel2 < cPPNsLevel2; ++iPPNLevel2)
516 {
517 /* Read the Level1 root page. */
518 uint8_t au8RootPage[X86_PAGE_SIZE];
519 RTGCPHYS GCPhysLevel1 = (RTGCPHYS)(fGCPhys64 ? paPPN64Level2[iPPNLevel2] : paPPN32Level2[iPPNLevel2]) << X86_PAGE_SHIFT;
520 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
521 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhysLevel1, &au8RootPage, sizeof(au8RootPage));
522 if (RT_SUCCESS(rc))
523 {
524 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
525 PPN *paPPN32 = (PPN *)&au8RootPage[0];
526
527 uint32_t const cPPNs = RT_MIN(cPagesLeft, cPPNsPerPage);
528 for (uint32_t iPPN = 0; iPPN < cPPNs; ++iPPN)
529 {
530 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
531 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
532 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].GCPhys = GCPhys;
533 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].cPages = 1;
534 }
535 cPagesLeft -= cPPNs;
536 }
537 }
538 }
539 }
540 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
541 {
542 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
543 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
544 paDescriptors[0].GCPhys = GCPhys;
545 paDescriptors[0].cPages = pGbo->cTotalPages;
546 }
547 else
548 {
549 AssertFailed();
550 return VERR_INTERNAL_ERROR; /* ptDepth should be already verified. */
551 }
552
553 /* Compress the descriptors. */
554 if (ptDepth != SVGA3D_MOBFMT_RANGE)
555 {
556 uint32_t iDescriptor = 0;
557 for (uint32_t i = 1; i < pGbo->cTotalPages; ++i)
558 {
559 /* Continuous physical memory? */
560 if (paDescriptors[i].GCPhys == paDescriptors[iDescriptor].GCPhys + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
561 {
562 Assert(paDescriptors[iDescriptor].cPages);
563 paDescriptors[iDescriptor].cPages++;
564 Log5Func(("Page %x GCPhys=%RGp successor\n", i, paDescriptors[i].GCPhys));
565 }
566 else
567 {
568 iDescriptor++;
569 paDescriptors[iDescriptor].GCPhys = paDescriptors[i].GCPhys;
570 paDescriptors[iDescriptor].cPages = 1;
571 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescriptors[iDescriptor].GCPhys));
572 }
573 }
574
575 pGbo->cDescriptors = iDescriptor + 1;
576 Log5Func(("Nr of descriptors %d\n", pGbo->cDescriptors));
577 }
578 else
579 pGbo->cDescriptors = 1;
580
581 if (RT_LIKELY(pGbo->cDescriptors < pGbo->cTotalPages))
582 {
583 pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemRealloc(paDescriptors, pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
584 AssertReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
585 }
586 else
587 pGbo->paDescriptors = paDescriptors;
588
589#if 1 /// @todo PGMHandlerPhysicalRegister asserts deep in PGM code with enmKind of a page being out of range.
590fWriteProtected = false;
591#endif
592 if (fWriteProtected)
593 {
594 pGbo->fGboFlags |= VMSVGAGBO_F_WRITE_PROTECTED;
595 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
596 {
597 rc = PDMDevHlpPGMHandlerPhysicalRegister(pSvgaR3State->pDevIns,
598 pGbo->paDescriptors[i].GCPhys,
599 pGbo->paDescriptors[i].GCPhys
600 + pGbo->paDescriptors[i].cPages * GUEST_PAGE_SIZE - 1,
601 pSvgaR3State->hGboAccessHandlerType, "VMSVGA GBO");
602 AssertRC(rc);
603 }
604 }
605
606 return VINF_SUCCESS;
607}
608
609
610static void vmsvgaR3GboDestroy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
611{
612 if (RT_LIKELY(VMSVGA_IS_GBO_CREATED(pGbo)))
613 {
614 if (pGbo->fGboFlags & VMSVGAGBO_F_WRITE_PROTECTED)
615 {
616 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
617 {
618 int rc = PDMDevHlpPGMHandlerPhysicalDeregister(pSvgaR3State->pDevIns, pGbo->paDescriptors[i].GCPhys);
619 AssertRC(rc);
620 }
621 }
622 RTMemFree(pGbo->paDescriptors);
623 RT_ZERO(pGbo);
624 }
625}
626
627/** @todo static void vmsvgaR3GboWriteProtect(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, bool fWriteProtect) */
628
629typedef enum VMSVGAGboTransferDirection
630{
631 VMSVGAGboTransferDirection_Read,
632 VMSVGAGboTransferDirection_Write,
633} VMSVGAGboTransferDirection;
634
635static int vmsvgaR3GboTransfer(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
636 uint32_t off, void *pvData, uint32_t cbData,
637 VMSVGAGboTransferDirection enmDirection)
638{
639 //DEBUG_BREAKPOINT_TEST();
640 int rc = VINF_SUCCESS;
641 uint8_t *pu8CurrentHost = (uint8_t *)pvData;
642
643 /* Find the right descriptor */
644 PCVMSVGAGBODESCRIPTOR const paDescriptors = pGbo->paDescriptors;
645 uint32_t iDescriptor = 0; /* Index in the descriptor array. */
646 uint32_t offDescriptor = 0; /* GMR offset of the current descriptor. */
647 while (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE <= off)
648 {
649 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
650 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
651 ++iDescriptor;
652 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
653 }
654
655 while (cbData)
656 {
657 uint32_t cbToCopy;
658 if (off + cbData <= offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
659 cbToCopy = cbData;
660 else
661 {
662 cbToCopy = (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE - off);
663 AssertReturn(cbToCopy <= cbData, VERR_INVALID_PARAMETER);
664 }
665
666 RTGCPHYS const GCPhys = paDescriptors[iDescriptor].GCPhys + off - offDescriptor;
667 Log5Func(("%s phys=%RGp\n", (enmDirection == VMSVGAGboTransferDirection_Read) ? "READ" : "WRITE", GCPhys));
668
669 /*
670 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
671 * guest-side VMSVGA driver seems to allocate non-DMA (regular physical) addresses,
672 * see @bugref{9654#c75}.
673 */
674 if (enmDirection == VMSVGAGboTransferDirection_Read)
675 rc = PDMDevHlpPhysRead(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
676 else
677 rc = PDMDevHlpPhysWrite(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
678 AssertRCBreak(rc);
679
680 cbData -= cbToCopy;
681 off += cbToCopy;
682 pu8CurrentHost += cbToCopy;
683
684 /* Go to the next descriptor if there's anything left. */
685 if (cbData)
686 {
687 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
688 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR);
689 ++iDescriptor;
690 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
691 }
692 }
693 return rc;
694}
695
696
697static int vmsvgaR3GboWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
698 uint32_t off, void const *pvData, uint32_t cbData)
699{
700 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
701 off, (void *)pvData, cbData,
702 VMSVGAGboTransferDirection_Write);
703}
704
705
706static int vmsvgaR3GboRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
707 uint32_t off, void *pvData, uint32_t cbData)
708{
709 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
710 off, pvData, cbData,
711 VMSVGAGboTransferDirection_Read);
712}
713
714
715static int vmsvgaR3GboBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, uint32_t cbValid)
716{
717 int rc;
718
719 /* Just reread the data if pvHost has been allocated already. */
720 if (!(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED))
721 pGbo->pvHost = RTMemAllocZ(pGbo->cbTotal);
722
723 if (pGbo->pvHost)
724 {
725 cbValid = RT_MIN(cbValid, pGbo->cbTotal);
726 rc = vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, cbValid);
727 }
728 else
729 rc = VERR_NO_MEMORY;
730
731 if (RT_SUCCESS(rc))
732 pGbo->fGboFlags |= VMSVGAGBO_F_HOST_BACKED;
733 else
734 {
735 RTMemFree(pGbo->pvHost);
736 pGbo->pvHost = NULL;
737 }
738 return rc;
739}
740
741
742static void vmsvgaR3GboBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
743{
744 RT_NOREF(pSvgaR3State);
745 AssertReturnVoid(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED);
746 RTMemFree(pGbo->pvHost);
747 pGbo->pvHost = NULL;
748 pGbo->fGboFlags &= ~VMSVGAGBO_F_HOST_BACKED;
749}
750
751
752static int vmsvgaR3GboBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
753{
754 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
755 return vmsvgaR3GboWrite(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
756}
757
758
759static int vmsvgaR3GboBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
760{
761 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
762 return vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
763}
764
765
766
767/*
768 *
769 * Object Tables.
770 *
771 */
772
773static int vmsvgaR3OTableVerifyIndex(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
774 uint32_t idx, uint32_t cbEntry)
775{
776 RT_NOREF(pSvgaR3State);
777
778 /* The table must exist and the index must be within the table. */
779 ASSERT_GUEST_RETURN(VMSVGA_IS_GBO_CREATED(pGboOTable), VERR_INVALID_PARAMETER);
780 ASSERT_GUEST_RETURN(idx < pGboOTable->cbTotal / cbEntry, VERR_INVALID_PARAMETER);
781 RT_UNTRUSTED_VALIDATED_FENCE();
782 return VINF_SUCCESS;
783}
784
785
786static int vmsvgaR3OTableRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
787 uint32_t idx, uint32_t cbEntry,
788 void *pvData, uint32_t cbData)
789{
790 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
791
792 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
793 if (RT_SUCCESS(rc))
794 {
795 uint32_t const off = idx * cbEntry;
796 rc = vmsvgaR3GboRead(pSvgaR3State, pGboOTable, off, pvData, cbData);
797 }
798 return rc;
799}
800
801static int vmsvgaR3OTableWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
802 uint32_t idx, uint32_t cbEntry,
803 void const *pvData, uint32_t cbData)
804{
805 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
806
807 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
808 if (RT_SUCCESS(rc))
809 {
810 uint32_t const off = idx * cbEntry;
811 rc = vmsvgaR3GboWrite(pSvgaR3State, pGboOTable, off, pvData, cbData);
812 }
813 return rc;
814}
815
816
817int vmsvgaR3OTableReadSurface(PVMSVGAR3STATE pSvgaR3State, uint32_t sid, SVGAOTableSurfaceEntry *pEntrySurface)
818{
819 return vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
820 sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, pEntrySurface, sizeof(SVGAOTableSurfaceEntry));
821}
822
823
824/*
825 *
826 * The guest's Memory OBjects (MOB).
827 *
828 */
829
830static int vmsvgaR3MobCreate(PVMSVGAR3STATE pSvgaR3State,
831 SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, SVGAMobId mobid,
832 bool fGCPhys64, PVMSVGAMOB pMob)
833{
834 RT_ZERO(*pMob);
835
836 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
837 SVGAOTableMobEntry entry;
838 entry.ptDepth = ptDepth;
839 entry.sizeInBytes = sizeInBytes;
840 entry.base = baseAddress;
841 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
842 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
843 if (RT_SUCCESS(rc))
844 {
845 /* Create the corresponding GBO. */
846 rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, fGCPhys64, /* fWriteProtected = */ false, &pMob->Gbo);
847 if (RT_SUCCESS(rc))
848 {
849 /* Add to the tree of known GBOs and the LRU list. */
850 pMob->Core.Key = mobid;
851 if (RTAvlU32Insert(&pSvgaR3State->MOBTree, &pMob->Core))
852 {
853 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
854 return VINF_SUCCESS;
855 }
856
857 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
858 }
859 }
860
861 return rc;
862}
863
864
865static int vmsvgaR3MobDestroy(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
866{
867 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
868 SVGAOTableMobEntry entry;
869 RT_ZERO(entry);
870 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
871 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
872
873 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
874 if (pMob)
875 {
876 RTListNodeRemove(&pMob->nodeLRU);
877 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
878 RTMemFree(pMob);
879 return VINF_SUCCESS;
880 }
881
882 return VERR_INVALID_PARAMETER;
883}
884
885
886PVMSVGAMOB vmsvgaR3MobGet(PVMSVGAR3STATE pSvgaR3State, SVGAMobId RT_UNTRUSTED_GUEST mobid)
887{
888 if (mobid == SVGA_ID_INVALID)
889 return NULL;
890
891 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Get(&pSvgaR3State->MOBTree, mobid);
892 if (pMob)
893 {
894 /* Move to the head of the LRU list. */
895 RTListNodeRemove(&pMob->nodeLRU);
896 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
897 }
898 else
899 ASSERT_GUEST_FAILED();
900
901 return pMob;
902}
903
904
905/** Create a host ring-3 pointer to the MOB data.
906 * Current approach is to allocate a host memory buffer and copy the guest MOB data if necessary.
907 * @param pSvgaR3State R3 device state.
908 * @param pMob The MOB.
909 * @param cbValid How many bytes of the guest backing memory contain valid data.
910 * @return VBox status.
911 */
912/** @todo uint32_t cbValid -> uint32_t offStart, uint32_t cbData */
913int vmsvgaR3MobBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob, uint32_t cbValid)
914{
915 AssertReturn(pMob, VERR_INVALID_PARAMETER);
916 return vmsvgaR3GboBackingStoreCreate(pSvgaR3State, &pMob->Gbo, cbValid);
917}
918
919
920void vmsvgaR3MobBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
921{
922 if (pMob)
923 vmsvgaR3GboBackingStoreDelete(pSvgaR3State, &pMob->Gbo);
924}
925
926
927int vmsvgaR3MobBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
928{
929 if (pMob)
930 return vmsvgaR3GboBackingStoreWriteToGuest(pSvgaR3State, &pMob->Gbo);
931 return VERR_INVALID_PARAMETER;
932}
933
934
935int vmsvgaR3MobBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
936{
937 if (pMob)
938 return vmsvgaR3GboBackingStoreReadFromGuest(pSvgaR3State, &pMob->Gbo);
939 return VERR_INVALID_PARAMETER;
940}
941
942
943void *vmsvgaR3MobBackingStorePtr(PVMSVGAMOB pMob, uint32_t off)
944{
945 if (pMob && (pMob->Gbo.fGboFlags & VMSVGAGBO_F_HOST_BACKED))
946 {
947 if (off <= pMob->Gbo.cbTotal)
948 return (uint8_t *)pMob->Gbo.pvHost + off;
949 }
950 return NULL;
951}
952
953#endif /* VBOX_WITH_VMSVGA3D */
954
955/*
956 * Screen objects.
957 */
958VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
959{
960 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
961 if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
962 && pSVGAState
963 && pSVGAState->aScreens[idScreen].fDefined)
964 {
965 return &pSVGAState->aScreens[idScreen];
966 }
967 return NULL;
968}
969
970void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
971{
972#ifdef VBOX_WITH_VMSVGA3D
973 if (pThis->svga.f3DEnabled)
974 {
975 for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
976 {
977 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
978 if (pScreen)
979 vmsvga3dDestroyScreen(pThisCC, pScreen);
980 }
981 }
982#else
983 RT_NOREF(pThis, pThisCC);
984#endif
985}
986
987
988/**
989 * Copy a rectangle of pixels within guest VRAM.
990 */
991static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
992 uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
993{
994 if (!width || !height)
995 return; /* Nothing to do, don't even bother. */
996
997 /*
998 * The guest VRAM (aka GFB) is considered to be a bitmap in the format
999 * corresponding to the current display mode.
1000 */
1001 uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1002 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1003 uint8_t const *pSrc;
1004 uint8_t *pDst;
1005 unsigned const cbRectWidth = width * cbPixel;
1006 unsigned uMaxOffset;
1007
1008 uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1009 if (uMaxOffset >= cbFrameBuffer)
1010 {
1011 Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1012 return; /* Just don't listen to a bad guest. */
1013 }
1014
1015 pSrc = pDst = pThisCC->pbVRam;
1016 pSrc += srcY * cbScanline + srcX * cbPixel;
1017 pDst += dstY * cbScanline + dstX * cbPixel;
1018
1019 if (srcY >= dstY)
1020 {
1021 /* Source below destination, copy top to bottom. */
1022 for (; height > 0; height--)
1023 {
1024 memmove(pDst, pSrc, cbRectWidth);
1025 pSrc += cbScanline;
1026 pDst += cbScanline;
1027 }
1028 }
1029 else
1030 {
1031 /* Source above destination, copy bottom to top. */
1032 pSrc += cbScanline * (height - 1);
1033 pDst += cbScanline * (height - 1);
1034 for (; height > 0; height--)
1035 {
1036 memmove(pDst, pSrc, cbRectWidth);
1037 pSrc -= cbScanline;
1038 pDst -= cbScanline;
1039 }
1040 }
1041}
1042
1043
1044/**
1045 * Common worker for changing the pointer shape.
1046 *
1047 * @param pThisCC The VGA/VMSVGA state for ring-3.
1048 * @param pSVGAState The VMSVGA ring-3 instance data.
1049 * @param fAlpha Whether there is alpha or not.
1050 * @param xHot Hotspot x coordinate.
1051 * @param yHot Hotspot y coordinate.
1052 * @param cx Width.
1053 * @param cy Height.
1054 * @param pbData Heap copy of the cursor data. Consumed.
1055 * @param cbData The size of the data.
1056 */
1057static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
1058 uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
1059{
1060 LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
1061#ifdef LOG_ENABLED
1062 if (LogIs2Enabled())
1063 {
1064 uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
1065 if (!fAlpha)
1066 {
1067 Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
1068 for (uint32_t y = 0; y < cy; y++)
1069 {
1070 Log2(("%3u:", y));
1071 uint8_t const *pbLine = &pbData[y * cbAndLine];
1072 for (uint32_t x = 0; x < cx; x += 8)
1073 {
1074 uint8_t b = pbLine[x / 8];
1075 char szByte[12];
1076 szByte[0] = b & 0x80 ? '*' : ' '; /* most significant bit first */
1077 szByte[1] = b & 0x40 ? '*' : ' ';
1078 szByte[2] = b & 0x20 ? '*' : ' ';
1079 szByte[3] = b & 0x10 ? '*' : ' ';
1080 szByte[4] = b & 0x08 ? '*' : ' ';
1081 szByte[5] = b & 0x04 ? '*' : ' ';
1082 szByte[6] = b & 0x02 ? '*' : ' ';
1083 szByte[7] = b & 0x01 ? '*' : ' ';
1084 szByte[8] = '\0';
1085 Log2(("%s", szByte));
1086 }
1087 Log2(("\n"));
1088 }
1089 }
1090
1091 Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
1092 uint32_t const *pu32Xor = (uint32_t const *)&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
1093 for (uint32_t y = 0; y < cy; y++)
1094 {
1095 Log2(("%3u:", y));
1096 uint32_t const *pu32Line = &pu32Xor[y * cx];
1097 for (uint32_t x = 0; x < cx; x++)
1098 Log2((" %08x", pu32Line[x]));
1099 Log2(("\n"));
1100 }
1101 }
1102#endif
1103
1104 int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, fAlpha, xHot, yHot, cx, cy, pbData);
1105 AssertRC(rc);
1106
1107 if (pSVGAState->Cursor.fActive)
1108 RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
1109
1110 pSVGAState->Cursor.fActive = true;
1111 pSVGAState->Cursor.xHotspot = xHot;
1112 pSVGAState->Cursor.yHotspot = yHot;
1113 pSVGAState->Cursor.width = cx;
1114 pSVGAState->Cursor.height = cy;
1115 pSVGAState->Cursor.cbData = cbData;
1116 pSVGAState->Cursor.pData = pbData;
1117}
1118
1119
1120#ifdef VBOX_WITH_VMSVGA3D
1121
1122/*
1123 * SVGA_3D_CMD_* handlers.
1124 */
1125
1126
1127/** SVGA_3D_CMD_SURFACE_DEFINE 1040, SVGA_3D_CMD_SURFACE_DEFINE_V2 1070
1128 *
1129 * @param pThisCC The VGA/VMSVGA state for the current context.
1130 * @param pCmd The VMSVGA command.
1131 * @param cMipLevelSizes Number of elements in the paMipLevelSizes array.
1132 * @param paMipLevelSizes Arrays of surface sizes for each face and miplevel.
1133 */
1134static void vmsvga3dCmdDefineSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineSurface_v2 const *pCmd,
1135 uint32_t cMipLevelSizes, SVGA3dSize *paMipLevelSizes)
1136{
1137 ASSERT_GUEST_RETURN_VOID(pCmd->sid < SVGA3D_MAX_SURFACE_IDS);
1138 ASSERT_GUEST_RETURN_VOID(cMipLevelSizes >= 1);
1139 RT_UNTRUSTED_VALIDATED_FENCE();
1140
1141 /* Number of faces (cFaces) is specified as the number of the first non-zero elements in the 'face' array.
1142 * Since only plain surfaces (cFaces == 1) and cubemaps (cFaces == 6) are supported
1143 * (see also SVGA3dCmdDefineSurface definition in svga3d_reg.h), we ignore anything else.
1144 */
1145 uint32_t cRemainingMipLevels = cMipLevelSizes;
1146 uint32_t cFaces = 0;
1147 for (uint32_t i = 0; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1148 {
1149 if (pCmd->face[i].numMipLevels == 0)
1150 break;
1151
1152 /* All SVGA3dSurfaceFace structures must have the same value of numMipLevels field */
1153 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == pCmd->face[0].numMipLevels);
1154
1155 /* numMipLevels value can't be greater than the number of remaining elements in the paMipLevelSizes array. */
1156 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels <= cRemainingMipLevels);
1157 cRemainingMipLevels -= pCmd->face[i].numMipLevels;
1158
1159 ++cFaces;
1160 }
1161 for (uint32_t i = cFaces; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1162 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == 0);
1163
1164 /* cFaces must be 6 for a cubemap and 1 otherwise. */
1165 ASSERT_GUEST_RETURN_VOID(cFaces == (uint32_t)((pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP) ? 6 : 1));
1166
1167 /* Sum of face[i].numMipLevels must be equal to cMipLevels. */
1168 ASSERT_GUEST_RETURN_VOID(cRemainingMipLevels == 0);
1169 RT_UNTRUSTED_VALIDATED_FENCE();
1170
1171 /* Verify paMipLevelSizes */
1172 uint32_t cWidth = paMipLevelSizes[0].width;
1173 uint32_t cHeight = paMipLevelSizes[0].height;
1174 uint32_t cDepth = paMipLevelSizes[0].depth;
1175 for (uint32_t i = 1; i < pCmd->face[0].numMipLevels; ++i)
1176 {
1177 cWidth >>= 1;
1178 if (cWidth == 0) cWidth = 1;
1179 cHeight >>= 1;
1180 if (cHeight == 0) cHeight = 1;
1181 cDepth >>= 1;
1182 if (cDepth == 0) cDepth = 1;
1183 for (uint32_t iFace = 0; iFace < cFaces; ++iFace)
1184 {
1185 uint32_t const iMipLevelSize = iFace * pCmd->face[0].numMipLevels + i;
1186 ASSERT_GUEST_RETURN_VOID( cWidth == paMipLevelSizes[iMipLevelSize].width
1187 && cHeight == paMipLevelSizes[iMipLevelSize].height
1188 && cDepth == paMipLevelSizes[iMipLevelSize].depth);
1189 }
1190 }
1191 RT_UNTRUSTED_VALIDATED_FENCE();
1192
1193 /* Create the surface. */
1194 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1195 pCmd->multisampleCount, pCmd->autogenFilter,
1196 pCmd->face[0].numMipLevels, &paMipLevelSizes[0], /* arraySize = */ 0, /* fAllocMipLevels = */ true);
1197}
1198
1199
1200/* SVGA_3D_CMD_DEFINE_GB_MOB 1093 */
1201static void vmsvga3dCmdDefineGBMob(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob const *pCmd)
1202{
1203 DEBUG_BREAKPOINT_TEST();
1204 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1205
1206 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1207
1208 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1209 /* Allocate a structure for the MOB. */
1210 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1211 AssertPtrReturnVoid(pMob);
1212
1213 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ false, pMob);
1214 if (RT_SUCCESS(rc))
1215 {
1216 return;
1217 }
1218
1219 AssertFailed();
1220
1221 RTMemFree(pMob);
1222}
1223
1224
1225/* SVGA_3D_CMD_DESTROY_GB_MOB 1094 */
1226static void vmsvga3dCmdDestroyGBMob(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBMob const *pCmd)
1227{
1228 //DEBUG_BREAKPOINT_TEST();
1229 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1230
1231 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1232
1233 int rc = vmsvgaR3MobDestroy(pSvgaR3State, pCmd->mobid);
1234 if (RT_SUCCESS(rc))
1235 {
1236 return;
1237 }
1238
1239 AssertFailed();
1240}
1241
1242
1243/* SVGA_3D_CMD_DEFINE_GB_SURFACE 1097 */
1244static void vmsvga3dCmdDefineGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface const *pCmd)
1245{
1246 //DEBUG_BREAKPOINT_TEST();
1247 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1248
1249 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1250 SVGAOTableSurfaceEntry entry;
1251 RT_ZERO(entry);
1252 entry.format = pCmd->format;
1253 entry.surface1Flags = pCmd->surfaceFlags;
1254 entry.numMipLevels = pCmd->numMipLevels;
1255 entry.multisampleCount = pCmd->multisampleCount;
1256 entry.autogenFilter = pCmd->autogenFilter;
1257 entry.size = pCmd->size;
1258 entry.mobid = SVGA_ID_INVALID;
1259 // entry.arraySize = 0;
1260 // entry.mobPitch = 0;
1261 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1262 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1263 if (RT_SUCCESS(rc))
1264 {
1265 /* Create the host surface. */
1266 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1267 pCmd->multisampleCount, pCmd->autogenFilter,
1268 pCmd->numMipLevels, &pCmd->size, /* arraySize = */ 0, /* fAllocMipLevels = */ false);
1269 }
1270}
1271
1272
1273/* SVGA_3D_CMD_DESTROY_GB_SURFACE 1098 */
1274static void vmsvga3dCmdDestroyGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBSurface const *pCmd)
1275{
1276 //DEBUG_BREAKPOINT_TEST();
1277 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1278
1279 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1280 SVGAOTableSurfaceEntry entry;
1281 RT_ZERO(entry);
1282 entry.mobid = SVGA_ID_INVALID;
1283 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1284 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1285
1286 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
1287}
1288
1289
1290/* SVGA_3D_CMD_BIND_GB_SURFACE 1099 */
1291static void vmsvga3dCmdBindGBSurface(PVGASTATECC pThisCC, SVGA3dCmdBindGBSurface const *pCmd)
1292{
1293 //DEBUG_BREAKPOINT_TEST();
1294 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1295
1296 /* Assign the mobid to the surface. */
1297 int rc = VINF_SUCCESS;
1298 if (pCmd->mobid != SVGA_ID_INVALID)
1299 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1300 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1301 if (RT_SUCCESS(rc))
1302 {
1303 SVGAOTableSurfaceEntry entry;
1304 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1305 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1306 if (RT_SUCCESS(rc))
1307 {
1308 entry.mobid = pCmd->mobid;
1309 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1310 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1311 if (RT_SUCCESS(rc))
1312 {
1313 /* */
1314 }
1315 }
1316 }
1317}
1318
1319
1320typedef union
1321{
1322 float f;
1323 uint32_t u;
1324} Unsigned2Float;
1325
1326float float16ToFloat(uint16_t f16)
1327{
1328 /* Format specs from Wiki: [15] = sign, [14:10] = exponent, [9:0] = fraction */
1329 uint16_t const f = f16 & 0x3FF;
1330 uint16_t const e = (f16 >> 10) & 0x1F;
1331 uint16_t const s = (f16 >> 15) & 0x1;
1332 Unsigned2Float u2f;
1333
1334 if (e == 0)
1335 {
1336 if (f == 0)
1337 {
1338 /* zero, -0 */
1339 u2f.u = (s << 31) | (0 << 23) | 0;
1340 return u2f.f;
1341 }
1342
1343 /* subnormal numbers: (-1)^signbit * 2^-14 * 0.significantbits */
1344 float const k = 1.0f / 16384.0f; /* 2^-14 */
1345 return (s ? -1.0f : 1.0f) * k * (float)f / 1024.0f;
1346 }
1347
1348 if (e == 31)
1349 {
1350 if (f == 0)
1351 {
1352 /* +-infinity */
1353 u2f.u = (s << 31) | (0xFF << 23) | 0;
1354 return u2f.f;
1355 }
1356
1357 /* NaN */
1358 u2f.u = (s << 31) | (0xFF << 23) | 1;
1359 return u2f.f;
1360 }
1361
1362 /* normalized value: (-1)^signbit * 2^(exponent - 15) * 1.significantbits */
1363 /* Build the float, adjusting for exponent bias (float32 bias is 127, float16 is 15)
1364 * and number of bits in the fraction (float32 has 23, float16 has 10). */
1365 u2f.u = (s << 31) | ((e + 127 - 15) << 23) | (f << (23 - 10));
1366 return u2f.f;
1367}
1368
1369
1370static int vmsvga3dBmpWrite(const char *pszFilename, VMSVGA3D_MAPPED_SURFACE const *pMap)
1371{
1372 if (pMap->cbBlock != 4 && pMap->format != SVGA3D_R16G16B16A16_FLOAT)
1373 return VERR_NOT_SUPPORTED;
1374
1375 int const w = pMap->cbRow / pMap->cbBlock;
1376 int const h = pMap->cRows;
1377
1378 const int cbBitmap = pMap->cbRow * pMap->cRows * 4;
1379
1380 FILE *f = fopen(pszFilename, "wb");
1381 if (!f)
1382 return VERR_FILE_NOT_FOUND;
1383
1384 {
1385 BMPFILEHDR fileHdr;
1386 RT_ZERO(fileHdr);
1387 fileHdr.uType = BMP_HDR_MAGIC;
1388 fileHdr.cbFileSize = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR) + cbBitmap;
1389 fileHdr.offBits = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR);
1390
1391 BMPWIN3XINFOHDR coreHdr;
1392 RT_ZERO(coreHdr);
1393 coreHdr.cbSize = sizeof(coreHdr);
1394 coreHdr.uWidth = w;
1395 coreHdr.uHeight = -h;
1396 coreHdr.cPlanes = 1;
1397 coreHdr.cBits = 32;
1398 coreHdr.cbSizeImage = cbBitmap;
1399
1400 fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1401 fwrite(&coreHdr, 1, sizeof(coreHdr), f);
1402 }
1403
1404 if (pMap->cbBlock == 4)
1405 {
1406 const uint8_t *s = (uint8_t *)pMap->pvData;
1407 for (uint32_t iRow = 0; iRow < pMap->cRows; ++iRow)
1408 {
1409 fwrite(s, 1, pMap->cbRow, f);
1410
1411 s += pMap->cbRowPitch;
1412 }
1413 }
1414 else if (pMap->format == SVGA3D_R16G16B16A16_FLOAT)
1415 {
1416 const uint8_t *s = (uint8_t *)pMap->pvData;
1417 for (int32_t y = 0; y < h; ++y)
1418 {
1419 for (int32_t x = 0; x < w; ++x)
1420 {
1421 uint16_t const *pu16Pixel = (uint16_t *)(s + x * 8);
1422 uint8_t r = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[0]));
1423 uint8_t g = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[1]));
1424 uint8_t b = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[2]));
1425 uint8_t a = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[3]));
1426 uint32_t u32Pixel = b + (g << 8) + (r << 16) + (a << 24);
1427 fwrite(&u32Pixel, 1, 4, f);
1428 }
1429
1430 s += pMap->cbRowPitch;
1431 }
1432 }
1433
1434 fclose(f);
1435
1436 return VINF_SUCCESS;
1437}
1438
1439
1440void vmsvga3dMapWriteBmpFile(VMSVGA3D_MAPPED_SURFACE const *pMap, char const *pszPrefix)
1441{
1442 static int idxBitmap = 0;
1443 char *pszFilename = RTStrAPrintf2("bmp\\%s%d.bmp", pszPrefix, idxBitmap++);
1444 int rc = vmsvga3dBmpWrite(pszFilename, pMap);
1445 Log(("WriteBmpFile %s %Rrc\n", pszFilename, rc)); RT_NOREF(rc);
1446 RTStrFree(pszFilename);
1447}
1448
1449
1450static int vmsvgaR3TransferSurfaceLevel(PVGASTATECC pThisCC,
1451 PVMSVGAMOB pMob,
1452 SVGA3dSurfaceImageId const *pImage,
1453 SVGA3dBox const *pBox,
1454 SVGA3dTransferType enmTransfer)
1455{
1456 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1457
1458 VMSVGA3D_SURFACE_MAP enmMapType;
1459 if (enmTransfer == SVGA3D_WRITE_HOST_VRAM)
1460 enmMapType = pBox
1461 ? VMSVGA3D_SURFACE_MAP_WRITE
1462 : VMSVGA3D_SURFACE_MAP_WRITE_DISCARD;
1463 else if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1464 enmMapType = VMSVGA3D_SURFACE_MAP_READ;
1465 else
1466 AssertFailedReturn(VERR_INVALID_PARAMETER);
1467
1468 VMSVGA3D_MAPPED_SURFACE map;
1469 int rc = vmsvga3dSurfaceMap(pThisCC, pImage, pBox, enmMapType, &map);
1470 if (RT_SUCCESS(rc))
1471 {
1472 /* Copy mapped surface <-> MOB. */
1473 VMSGA3D_BOX_DIMENSIONS dims;
1474 rc = vmsvga3dGetBoxDimensions(pThisCC, pImage, pBox, &dims);
1475 if (RT_SUCCESS(rc))
1476 {
1477 for (uint32_t z = 0; z < map.box.d; ++z)
1478 {
1479 uint8_t *pu8Map = (uint8_t *)map.pvData + z * map.cbDepthPitch;
1480 uint32_t offMob = dims.offSubresource + dims.offBox + z * dims.cbDepthPitch;
1481
1482 for (uint32_t iRow = 0; iRow < map.cRows; ++iRow)
1483 {
1484 if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1485 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1486 else
1487 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1488 AssertRCBreak(rc);
1489
1490 pu8Map += map.cbRowPitch;
1491 offMob += dims.cbPitch;
1492 }
1493 }
1494 }
1495
1496 // vmsvga3dMapWriteBmpFile(&map, "Dynamic");
1497
1498 bool const fWritten = (enmTransfer == SVGA3D_WRITE_HOST_VRAM);
1499 vmsvga3dSurfaceUnmap(pThisCC, pImage, &map, fWritten);
1500 }
1501
1502 return rc;
1503}
1504
1505
1506/* SVGA_3D_CMD_UPDATE_GB_IMAGE 1101 */
1507static void vmsvga3dCmdUpdateGBImage(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBImage const *pCmd)
1508{
1509 //DEBUG_BREAKPOINT_TEST();
1510 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1511
1512 LogFlowFunc(("sid=%u @%u,%u,%u %ux%ux%u\n",
1513 pCmd->image.sid, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
1514
1515/*
1516 SVGA3dSurfaceFormat format;
1517 SVGA3dSurface1Flags surface1Flags;
1518 uint32 numMipLevels;
1519 uint32 multisampleCount;
1520 SVGA3dTextureFilter autogenFilter;
1521 SVGA3dSize size;
1522 SVGAMobId mobid;
1523 uint32 arraySize;
1524 uint32 mobPitch;
1525 SVGA3dSurface2Flags surface2Flags;
1526 uint8 multisamplePattern;
1527 uint8 qualityLevel;
1528 uint16 bufferByteStride;
1529 float minLOD;
1530*/
1531
1532 /* "update a surface from its backing MOB." */
1533 SVGAOTableSurfaceEntry entrySurface;
1534 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1535 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1536 if (RT_SUCCESS(rc))
1537 {
1538 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1539 if (pMob)
1540 {
1541 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
1542 AssertRC(rc);
1543 }
1544 }
1545}
1546
1547
1548/* SVGA_3D_CMD_UPDATE_GB_SURFACE 1102 */
1549static void vmsvga3dCmdUpdateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBSurface const *pCmd)
1550{
1551 //DEBUG_BREAKPOINT_TEST();
1552 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1553
1554 LogFlowFunc(("sid=%u\n",
1555 pCmd->sid));
1556
1557 /* "update a surface from its backing MOB." */
1558 SVGAOTableSurfaceEntry entrySurface;
1559 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1560 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1561 if (RT_SUCCESS(rc))
1562 {
1563 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1564 if (pMob)
1565 {
1566 uint32 const arraySize = vmsvga3dGetArrayElements(pThisCC, pCmd->sid);
1567 for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1568 {
1569 for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1570 {
1571 SVGA3dSurfaceImageId image;
1572 image.sid = pCmd->sid;
1573 image.face = iArray;
1574 image.mipmap = iMipmap;
1575
1576 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_WRITE_HOST_VRAM);
1577 AssertRCBreak(rc);
1578 }
1579 }
1580 }
1581 }
1582}
1583
1584
1585/* SVGA_3D_CMD_READBACK_GB_IMAGE 1103 */
1586static void vmsvga3dCmdReadbackGBImage(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBImage const *pCmd)
1587{
1588 //DEBUG_BREAKPOINT_TEST();
1589 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1590
1591 LogFlowFunc(("sid=%u, face=%u, mipmap=%u\n",
1592 pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap));
1593
1594 /* Read a surface to its backing MOB. */
1595 SVGAOTableSurfaceEntry entrySurface;
1596 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1597 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1598 if (RT_SUCCESS(rc))
1599 {
1600 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1601 if (pMob)
1602 {
1603 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1604 AssertRC(rc);
1605 }
1606 }
1607}
1608
1609
1610/* SVGA_3D_CMD_READBACK_GB_SURFACE 1104 */
1611static void vmsvga3dCmdReadbackGBSurface(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBSurface const *pCmd)
1612{
1613 //DEBUG_BREAKPOINT_TEST();
1614 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1615
1616 LogFlowFunc(("sid=%u\n",
1617 pCmd->sid));
1618
1619 /* Read a surface to its backing MOB. */
1620 SVGAOTableSurfaceEntry entrySurface;
1621 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1622 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1623 if (RT_SUCCESS(rc))
1624 {
1625 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1626 if (pMob)
1627 {
1628 uint32 const arraySize = vmsvga3dGetArrayElements(pThisCC, pCmd->sid);
1629 for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1630 {
1631 for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1632 {
1633 SVGA3dSurfaceImageId image;
1634 image.sid = pCmd->sid;
1635 image.face = iArray;
1636 image.mipmap = iMipmap;
1637
1638 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1639 AssertRCBreak(rc);
1640 }
1641 }
1642 }
1643 }
1644}
1645
1646
1647/* SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105 */
1648static void vmsvga3dCmdInvalidateGBImage(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBImage const *pCmd)
1649{
1650 //DEBUG_BREAKPOINT_TEST();
1651 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap);
1652}
1653
1654
1655/* SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106 */
1656static void vmsvga3dCmdInvalidateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBSurface const *pCmd)
1657{
1658 //DEBUG_BREAKPOINT_TEST();
1659 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, SVGA_ID_INVALID, SVGA_ID_INVALID);
1660}
1661
1662
1663/* SVGA_3D_CMD_SET_OTABLE_BASE64 1115 */
1664static void vmsvga3dCmdSetOTableBase64(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase64 const *pCmd)
1665{
1666 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1667
1668 /*
1669 * Create a GBO for the table.
1670 */
1671 PVMSVGAGBO pGbo;
1672 if (pCmd->type <= RT_ELEMENTS(pSvgaR3State->aGboOTables))
1673 {
1674 RT_UNTRUSTED_VALIDATED_FENCE();
1675 pGbo = &pSvgaR3State->aGboOTables[pCmd->type];
1676 }
1677 else
1678 {
1679 ASSERT_GUEST_FAILED();
1680 pGbo = NULL;
1681 }
1682
1683 if (pGbo)
1684 {
1685 /* Recreate. */
1686 vmsvgaR3GboDestroy(pSvgaR3State, pGbo);
1687 int rc = vmsvgaR3GboCreate(pSvgaR3State, pCmd->ptDepth, pCmd->baseAddress, pCmd->sizeInBytes, /*fGCPhys64=*/ true, /* fWriteProtected = */ true, pGbo);
1688 AssertRC(rc);
1689 }
1690}
1691
1692
1693/* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124 */
1694static void vmsvga3dCmdDefineGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDefineGBScreenTarget const *pCmd)
1695{
1696 //DEBUG_BREAKPOINT_TEST();
1697 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1698
1699 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1700 ASSERT_GUEST_RETURN_VOID(pCmd->width > 0 && pCmd->width <= pThis->svga.u32MaxWidth); /* SVGA_REG_SCREENTARGET_MAX_WIDTH */
1701 ASSERT_GUEST_RETURN_VOID(pCmd->height > 0 && pCmd->height <= pThis->svga.u32MaxHeight); /* SVGA_REG_SCREENTARGET_MAX_HEIGHT */
1702 RT_UNTRUSTED_VALIDATED_FENCE();
1703
1704 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1705 SVGAOTableScreenTargetEntry entry;
1706 RT_ZERO(entry);
1707 entry.image.sid = SVGA_ID_INVALID;
1708 // entry.image.face = 0;
1709 // entry.image.mipmap = 0;
1710 entry.width = pCmd->width;
1711 entry.height = pCmd->height;
1712 entry.xRoot = pCmd->xRoot;
1713 entry.yRoot = pCmd->yRoot;
1714 entry.flags = pCmd->flags;
1715 entry.dpi = pCmd->dpi;
1716
1717 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1718 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1719 if (RT_SUCCESS(rc))
1720 {
1721 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1722 /** @todo Generic screen object/target interface. */
1723 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1724 pScreen->fDefined = true;
1725 pScreen->fModified = true;
1726 pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET
1727 | (RT_BOOL(pCmd->flags & SVGA_STFLAG_PRIMARY) ? SVGA_SCREEN_IS_PRIMARY : 0);
1728 pScreen->idScreen = pCmd->stid;
1729
1730 pScreen->xOrigin = pCmd->xRoot;
1731 pScreen->yOrigin = pCmd->yRoot;
1732 pScreen->cWidth = pCmd->width;
1733 pScreen->cHeight = pCmd->height;
1734 pScreen->offVRAM = 0; /* Not applicable for screen targets, they use either a separate memory buffer or a host window. */
1735 pScreen->cbPitch = pCmd->width * 4;
1736 pScreen->cBpp = 32;
1737
1738 if (RT_LIKELY(pThis->svga.f3DEnabled))
1739 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
1740
1741 if (!pScreen->pHwScreen)
1742 {
1743 /* System memory buffer. */
1744 pScreen->pvScreenBitmap = RTMemAllocZ(pScreen->cHeight * pScreen->cbPitch);
1745 }
1746
1747 pThis->svga.fGFBRegisters = false;
1748 vmsvgaR3ChangeMode(pThis, pThisCC);
1749 }
1750}
1751
1752
1753/* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125 */
1754static void vmsvga3dCmdDestroyGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDestroyGBScreenTarget const *pCmd)
1755{
1756 //DEBUG_BREAKPOINT_TEST();
1757 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1758
1759 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1760 RT_UNTRUSTED_VALIDATED_FENCE();
1761
1762 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1763 SVGAOTableScreenTargetEntry entry;
1764 RT_ZERO(entry);
1765 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1766 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1767 if (RT_SUCCESS(rc))
1768 {
1769 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1770 /** @todo Generic screen object/target interface. */
1771 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1772 pScreen->fModified = true;
1773 pScreen->fDefined = false;
1774 pScreen->idScreen = pCmd->stid;
1775
1776 if (RT_LIKELY(pThis->svga.f3DEnabled))
1777 vmsvga3dDestroyScreen(pThisCC, pScreen);
1778
1779 vmsvgaR3ChangeMode(pThis, pThisCC);
1780
1781 RTMemFree(pScreen->pvScreenBitmap);
1782 pScreen->pvScreenBitmap = NULL;
1783 }
1784}
1785
1786
1787/* SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126 */
1788static void vmsvga3dCmdBindGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdBindGBScreenTarget const *pCmd)
1789{
1790 //DEBUG_BREAKPOINT_TEST();
1791 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1792
1793 /* "Binding a surface to a Screen Target the same as flipping" */
1794
1795 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1796 ASSERT_GUEST_RETURN_VOID(pCmd->image.face == 0 && pCmd->image.mipmap == 0);
1797 RT_UNTRUSTED_VALIDATED_FENCE();
1798
1799 /* Assign the surface to the screen target. */
1800 int rc = VINF_SUCCESS;
1801 if (pCmd->image.sid != SVGA_ID_INVALID)
1802 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1803 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE);
1804 if (RT_SUCCESS(rc))
1805 {
1806 SVGAOTableScreenTargetEntry entry;
1807 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1808 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1809 if (RT_SUCCESS(rc))
1810 {
1811 entry.image = pCmd->image;
1812 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1813 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1814 if (RT_SUCCESS(rc))
1815 {
1816 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1817 rc = pSvgaR3State->pFuncsGBO->pfnScreenTargetBind(pThisCC, pScreen, pCmd->image.sid);
1818 AssertRC(rc);
1819 }
1820 }
1821 }
1822}
1823
1824
1825/* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127 */
1826static void vmsvga3dCmdUpdateGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBScreenTarget const *pCmd)
1827{
1828 //DEBUG_BREAKPOINT_TEST();
1829 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1830
1831 /* Update the screen target from its backing surface. */
1832 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1833 RT_UNTRUSTED_VALIDATED_FENCE();
1834
1835 /* Get the screen target info. */
1836 SVGAOTableScreenTargetEntry entryScreenTarget;
1837 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1838 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entryScreenTarget, sizeof(entryScreenTarget));
1839 if (RT_SUCCESS(rc))
1840 {
1841 ASSERT_GUEST_RETURN_VOID(entryScreenTarget.image.face == 0 && entryScreenTarget.image.mipmap == 0);
1842 RT_UNTRUSTED_VALIDATED_FENCE();
1843
1844 if (entryScreenTarget.image.sid != SVGA_ID_INVALID)
1845 {
1846 SVGAOTableSurfaceEntry entrySurface;
1847 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1848 entryScreenTarget.image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1849 if (RT_SUCCESS(rc))
1850 {
1851 /* Copy entrySurface.mobid content to the screen target. */
1852 if (entrySurface.mobid != SVGA_ID_INVALID)
1853 {
1854 RT_UNTRUSTED_VALIDATED_FENCE();
1855 SVGA3dRect targetRect = pCmd->rect;
1856
1857 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1858 if (pScreen->pHwScreen)
1859 {
1860 /* Copy the screen target surface to the backend's screen. */
1861 pSvgaR3State->pFuncsGBO->pfnScreenTargetUpdate(pThisCC, pScreen, &targetRect);
1862 }
1863 else if (pScreen->pvScreenBitmap)
1864 {
1865 /* Copy the screen target surface to the memory buffer. */
1866 SVGA3dBox box; /* SurfaceMap will clip the box as necessary. */
1867 box.x = pCmd->rect.x;
1868 box.y = pCmd->rect.y;
1869 box.z = 0;
1870 box.w = pCmd->rect.w;
1871 box.h = pCmd->rect.h;
1872 box.d = 1;
1873
1874 VMSVGA3D_MAPPED_SURFACE map;
1875 rc = vmsvga3dSurfaceMap(pThisCC, &entryScreenTarget.image, &box, VMSVGA3D_SURFACE_MAP_READ, &map);
1876 if (RT_SUCCESS(rc))
1877 {
1878 VMSGA3D_BOX_DIMENSIONS dims;
1879 rc = vmsvga3dGetBoxDimensions(pThisCC, &entryScreenTarget.image, &map.box, &dims);
1880 if (RT_SUCCESS(rc))
1881 {
1882 uint8_t const *pu8Src = (uint8_t *)map.pvData;
1883 uint8_t *pu8Dst = (uint8_t *)pScreen->pvScreenBitmap + dims.offSubresource + dims.offBox;
1884 for (uint32_t iRow = 0; iRow < map.cRows; ++iRow)
1885 {
1886 memcpy(pu8Dst, pu8Src, dims.cbRow);
1887
1888 pu8Src += map.cbRowPitch;
1889 pu8Dst += dims.cbPitch;
1890 }
1891 }
1892
1893 vmsvga3dSurfaceUnmap(pThisCC, &entryScreenTarget.image, &map, /* fWritten = */ false);
1894
1895 vmsvgaR3UpdateScreen(pThisCC, pScreen, map.box.x, map.box.y, map.box.w, map.box.h);
1896 }
1897 else
1898 AssertFailed();
1899 }
1900 }
1901 }
1902 }
1903 }
1904}
1905
1906
1907/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134 */
1908static void vmsvga3dCmdDefineGBSurface_v2(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v2 const *pCmd)
1909{
1910 //DEBUG_BREAKPOINT_TEST();
1911 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1912
1913 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1914 SVGAOTableSurfaceEntry entry;
1915 RT_ZERO(entry);
1916 entry.format = pCmd->format;
1917 entry.surface1Flags = pCmd->surfaceFlags;
1918 entry.numMipLevels = pCmd->numMipLevels;
1919 entry.multisampleCount = pCmd->multisampleCount;
1920 entry.autogenFilter = pCmd->autogenFilter;
1921 entry.size = pCmd->size;
1922 entry.mobid = SVGA_ID_INVALID;
1923 entry.arraySize = pCmd->arraySize;
1924 // entry.mobPitch = 0;
1925 // ...
1926
1927 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1928 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1929 if (RT_SUCCESS(rc))
1930 {
1931 /* Create the host surface. */
1932 /** @todo SVGAOTableSurfaceEntry as input parameter? */
1933 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1934 pCmd->multisampleCount, pCmd->autogenFilter,
1935 pCmd->numMipLevels, &pCmd->size, pCmd->arraySize, /* fAllocMipLevels = */ false);
1936 }
1937}
1938
1939
1940/* SVGA_3D_CMD_DEFINE_GB_MOB64 1135 */
1941static void vmsvga3dCmdDefineGBMob64(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob64 const *pCmd)
1942{
1943 //DEBUG_BREAKPOINT_TEST();
1944 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1945
1946 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1947
1948 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1949 /* Allocate a structure for the MOB. */
1950 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1951 AssertPtrReturnVoid(pMob);
1952
1953 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ true, pMob);
1954 if (RT_SUCCESS(rc))
1955 {
1956 return;
1957 }
1958
1959 RTMemFree(pMob);
1960}
1961
1962
1963/* SVGA_3D_CMD_DX_DEFINE_CONTEXT 1143 */
1964static int vmsvga3dCmdDXDefineContext(PVGASTATECC pThisCC, SVGA3dCmdDXDefineContext const *pCmd, uint32_t cbCmd)
1965{
1966#ifdef VMSVGA3D_DX
1967 //DEBUG_BREAKPOINT_TEST();
1968 RT_NOREF(cbCmd);
1969
1970 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1971
1972 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
1973 SVGAOTableDXContextEntry entry;
1974 RT_ZERO(entry);
1975 entry.cid = pCmd->cid;
1976 entry.mobid = SVGA_ID_INVALID;
1977 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1978 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1979 if (RT_SUCCESS(rc))
1980 {
1981 /* Create the host context. */
1982 rc = vmsvga3dDXDefineContext(pThisCC, pCmd->cid);
1983 }
1984
1985 return rc;
1986#else
1987 RT_NOREF(pThisCC, pCmd, cbCmd);
1988 return VERR_NOT_SUPPORTED;
1989#endif
1990}
1991
1992
1993/* SVGA_3D_CMD_DX_DESTROY_CONTEXT 1144 */
1994static int vmsvga3dCmdDXDestroyContext(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyContext const *pCmd, uint32_t cbCmd)
1995{
1996#ifdef VMSVGA3D_DX
1997 //DEBUG_BREAKPOINT_TEST();
1998 RT_NOREF(cbCmd);
1999
2000 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2001
2002 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
2003 SVGAOTableDXContextEntry entry;
2004 RT_ZERO(entry);
2005 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2006 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2007
2008 return vmsvga3dDXDestroyContext(pThisCC, pCmd->cid);
2009#else
2010 RT_NOREF(pThisCC, pCmd, cbCmd);
2011 return VERR_NOT_SUPPORTED;
2012#endif
2013}
2014
2015
2016/* SVGA_3D_CMD_DX_BIND_CONTEXT 1145 */
2017static int vmsvga3dCmdDXBindContext(PVGASTATECC pThisCC, SVGA3dCmdDXBindContext const *pCmd, uint32_t cbCmd)
2018{
2019#ifdef VMSVGA3D_DX
2020 //DEBUG_BREAKPOINT_TEST();
2021 RT_NOREF(cbCmd);
2022
2023 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2024
2025 /* Assign a mobid to a cid. */
2026 int rc = VINF_SUCCESS;
2027 if (pCmd->mobid != SVGA_ID_INVALID)
2028 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
2029 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
2030 if (RT_SUCCESS(rc))
2031 {
2032 SVGAOTableDXContextEntry entry;
2033 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2034 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2035 if (RT_SUCCESS(rc))
2036 {
2037 SVGADXContextMobFormat *pSvgaDXContext = NULL;
2038 if (pCmd->mobid != entry.mobid && entry.mobid != SVGA_ID_INVALID)
2039 {
2040 /* Unbind notification to the DX backend. Copy the context data to the guest backing memory. */
2041 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2042 if (pSvgaDXContext)
2043 {
2044 rc = vmsvga3dDXUnbindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2045 if (RT_SUCCESS(rc))
2046 {
2047 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2048 if (pMob)
2049 {
2050 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2051 }
2052 }
2053
2054 RTMemFree(pSvgaDXContext);
2055 pSvgaDXContext = NULL;
2056 }
2057 }
2058
2059 if (pCmd->mobid != SVGA_ID_INVALID)
2060 {
2061 /* Bind a new context. Copy existing data from the guest backing memory. */
2062 if (pCmd->validContents)
2063 {
2064 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2065 if (pMob)
2066 {
2067 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2068 if (pSvgaDXContext)
2069 {
2070 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2071 if (RT_FAILURE(rc))
2072 {
2073 RTMemFree(pSvgaDXContext);
2074 pSvgaDXContext = NULL;
2075 }
2076 }
2077 }
2078 }
2079
2080 rc = vmsvga3dDXBindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2081
2082 RTMemFree(pSvgaDXContext);
2083 }
2084
2085 /* Update the object table. */
2086 entry.mobid = pCmd->mobid;
2087 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2088 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2089 }
2090 }
2091
2092 return rc;
2093#else
2094 RT_NOREF(pThisCC, pCmd, cbCmd);
2095 return VERR_NOT_SUPPORTED;
2096#endif
2097}
2098
2099
2100/* SVGA_3D_CMD_DX_READBACK_CONTEXT 1146 */
2101static int vmsvga3dCmdDXReadbackContext(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackContext const *pCmd, uint32_t cbCmd)
2102{
2103#ifdef VMSVGA3D_DX
2104 //DEBUG_BREAKPOINT_TEST();
2105 RT_NOREF(cbCmd);
2106
2107 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2108
2109 /* "Request that the device flush the contents back into guest memory." */
2110 SVGAOTableDXContextEntry entry;
2111 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2112 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2113 if (RT_SUCCESS(rc))
2114 {
2115 if (entry.mobid != SVGA_ID_INVALID)
2116 {
2117 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2118 if (pMob)
2119 {
2120 /* Get the content. */
2121 SVGADXContextMobFormat *pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2122 if (pSvgaDXContext)
2123 {
2124 rc = vmsvga3dDXReadbackContext(pThisCC, pCmd->cid, pSvgaDXContext);
2125 if (RT_SUCCESS(rc))
2126 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2127
2128 RTMemFree(pSvgaDXContext);
2129 }
2130 else
2131 rc = VERR_NO_MEMORY;
2132 }
2133 }
2134 }
2135
2136 return rc;
2137#else
2138 RT_NOREF(pThisCC, pCmd, cbCmd);
2139 return VERR_NOT_SUPPORTED;
2140#endif
2141}
2142
2143
2144/* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT 1147 */
2145static int vmsvga3dCmdDXInvalidateContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateContext const *pCmd, uint32_t cbCmd)
2146{
2147#ifdef VMSVGA3D_DX
2148 DEBUG_BREAKPOINT_TEST();
2149 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2150 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2151 return vmsvga3dDXInvalidateContext(pThisCC, idDXContext);
2152#else
2153 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2154 return VERR_NOT_SUPPORTED;
2155#endif
2156}
2157
2158
2159/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER 1148 */
2160static int vmsvga3dCmdDXSetSingleConstantBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSingleConstantBuffer const *pCmd, uint32_t cbCmd)
2161{
2162#ifdef VMSVGA3D_DX
2163 //DEBUG_BREAKPOINT_TEST();
2164 RT_NOREF(cbCmd);
2165 return vmsvga3dDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd);
2166#else
2167 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2168 return VERR_NOT_SUPPORTED;
2169#endif
2170}
2171
2172
2173/* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES 1149 */
2174static int vmsvga3dCmdDXSetShaderResources(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderResources const *pCmd, uint32_t cbCmd)
2175{
2176#ifdef VMSVGA3D_DX
2177 //DEBUG_BREAKPOINT_TEST();
2178 SVGA3dShaderResourceViewId const *paShaderResourceViewId = (SVGA3dShaderResourceViewId *)&pCmd[1];
2179 uint32_t const cShaderResourceViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dShaderResourceViewId);
2180 return vmsvga3dDXSetShaderResources(pThisCC, idDXContext, pCmd, cShaderResourceViewId, paShaderResourceViewId);
2181#else
2182 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2183 return VERR_NOT_SUPPORTED;
2184#endif
2185}
2186
2187
2188/* SVGA_3D_CMD_DX_SET_SHADER 1150 */
2189static int vmsvga3dCmdDXSetShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShader const *pCmd, uint32_t cbCmd)
2190{
2191#ifdef VMSVGA3D_DX
2192 //DEBUG_BREAKPOINT_TEST();
2193 RT_NOREF(cbCmd);
2194 return vmsvga3dDXSetShader(pThisCC, idDXContext, pCmd);
2195#else
2196 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2197 return VERR_NOT_SUPPORTED;
2198#endif
2199}
2200
2201
2202/* SVGA_3D_CMD_DX_SET_SAMPLERS 1151 */
2203static int vmsvga3dCmdDXSetSamplers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSamplers const *pCmd, uint32_t cbCmd)
2204{
2205#ifdef VMSVGA3D_DX
2206 //DEBUG_BREAKPOINT_TEST();
2207 SVGA3dSamplerId const *paSamplerId = (SVGA3dSamplerId *)&pCmd[1];
2208 uint32_t const cSamplerId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSamplerId);
2209 return vmsvga3dDXSetSamplers(pThisCC, idDXContext, pCmd, cSamplerId, paSamplerId);
2210#else
2211 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2212 return VERR_NOT_SUPPORTED;
2213#endif
2214}
2215
2216
2217/* SVGA_3D_CMD_DX_DRAW 1152 */
2218static int vmsvga3dCmdDXDraw(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDraw const *pCmd, uint32_t cbCmd)
2219{
2220#ifdef VMSVGA3D_DX
2221 //DEBUG_BREAKPOINT_TEST();
2222 RT_NOREF(cbCmd);
2223 return vmsvga3dDXDraw(pThisCC, idDXContext, pCmd);
2224#else
2225 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2226 return VERR_NOT_SUPPORTED;
2227#endif
2228}
2229
2230
2231/* SVGA_3D_CMD_DX_DRAW_INDEXED 1153 */
2232static int vmsvga3dCmdDXDrawIndexed(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexed const *pCmd, uint32_t cbCmd)
2233{
2234#ifdef VMSVGA3D_DX
2235 //DEBUG_BREAKPOINT_TEST();
2236 RT_NOREF(cbCmd);
2237 return vmsvga3dDXDrawIndexed(pThisCC, idDXContext, pCmd);
2238#else
2239 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2240 return VERR_NOT_SUPPORTED;
2241#endif
2242}
2243
2244
2245/* SVGA_3D_CMD_DX_DRAW_INSTANCED 1154 */
2246static int vmsvga3dCmdDXDrawInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstanced const *pCmd, uint32_t cbCmd)
2247{
2248#ifdef VMSVGA3D_DX
2249 //DEBUG_BREAKPOINT_TEST();
2250 RT_NOREF(cbCmd);
2251 return vmsvga3dDXDrawInstanced(pThisCC, idDXContext, pCmd);
2252#else
2253 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2254 return VERR_NOT_SUPPORTED;
2255#endif
2256}
2257
2258
2259/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED 1155 */
2260static int vmsvga3dCmdDXDrawIndexedInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstanced const *pCmd, uint32_t cbCmd)
2261{
2262#ifdef VMSVGA3D_DX
2263 //DEBUG_BREAKPOINT_TEST();
2264 RT_NOREF(cbCmd);
2265 return vmsvga3dDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd);
2266#else
2267 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2268 return VERR_NOT_SUPPORTED;
2269#endif
2270}
2271
2272
2273/* SVGA_3D_CMD_DX_DRAW_AUTO 1156 */
2274static int vmsvga3dCmdDXDrawAuto(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawAuto const *pCmd, uint32_t cbCmd)
2275{
2276#ifdef VMSVGA3D_DX
2277 DEBUG_BREAKPOINT_TEST();
2278 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2279 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2280 return vmsvga3dDXDrawAuto(pThisCC, idDXContext);
2281#else
2282 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2283 return VERR_NOT_SUPPORTED;
2284#endif
2285}
2286
2287
2288/* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT 1157 */
2289static int vmsvga3dCmdDXSetInputLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetInputLayout const *pCmd, uint32_t cbCmd)
2290{
2291#ifdef VMSVGA3D_DX
2292 //DEBUG_BREAKPOINT_TEST();
2293 RT_NOREF(cbCmd);
2294 return vmsvga3dDXSetInputLayout(pThisCC, idDXContext, pCmd->elementLayoutId);
2295#else
2296 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2297 return VERR_NOT_SUPPORTED;
2298#endif
2299}
2300
2301
2302/* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS 1158 */
2303static int vmsvga3dCmdDXSetVertexBuffers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVertexBuffers const *pCmd, uint32_t cbCmd)
2304{
2305#ifdef VMSVGA3D_DX
2306 //DEBUG_BREAKPOINT_TEST();
2307 SVGA3dVertexBuffer const *paVertexBuffer = (SVGA3dVertexBuffer *)&pCmd[1];
2308 uint32_t const cVertexBuffer = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dVertexBuffer);
2309 return vmsvga3dDXSetVertexBuffers(pThisCC, idDXContext, pCmd->startBuffer, cVertexBuffer, paVertexBuffer);
2310#else
2311 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2312 return VERR_NOT_SUPPORTED;
2313#endif
2314}
2315
2316
2317/* SVGA_3D_CMD_DX_SET_INDEX_BUFFER 1159 */
2318static int vmsvga3dCmdDXSetIndexBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetIndexBuffer const *pCmd, uint32_t cbCmd)
2319{
2320#ifdef VMSVGA3D_DX
2321 //DEBUG_BREAKPOINT_TEST();
2322 RT_NOREF(cbCmd);
2323 return vmsvga3dDXSetIndexBuffer(pThisCC, idDXContext, pCmd);
2324#else
2325 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2326 return VERR_NOT_SUPPORTED;
2327#endif
2328}
2329
2330
2331/* SVGA_3D_CMD_DX_SET_TOPOLOGY 1160 */
2332static int vmsvga3dCmdDXSetTopology(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetTopology const *pCmd, uint32_t cbCmd)
2333{
2334#ifdef VMSVGA3D_DX
2335 //DEBUG_BREAKPOINT_TEST();
2336 RT_NOREF(cbCmd);
2337 return vmsvga3dDXSetTopology(pThisCC, idDXContext, pCmd->topology);
2338#else
2339 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2340 return VERR_NOT_SUPPORTED;
2341#endif
2342}
2343
2344
2345/* SVGA_3D_CMD_DX_SET_RENDERTARGETS 1161 */
2346static int vmsvga3dCmdDXSetRenderTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRenderTargets const *pCmd, uint32_t cbCmd)
2347{
2348#ifdef VMSVGA3D_DX
2349 //DEBUG_BREAKPOINT_TEST();
2350 SVGA3dRenderTargetViewId const *paRenderTargetViewId = (SVGA3dRenderTargetViewId *)&pCmd[1];
2351 uint32_t const cRenderTargetViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderTargetViewId);
2352 return vmsvga3dDXSetRenderTargets(pThisCC, idDXContext, pCmd->depthStencilViewId, cRenderTargetViewId, paRenderTargetViewId);
2353#else
2354 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2355 return VERR_NOT_SUPPORTED;
2356#endif
2357}
2358
2359
2360/* SVGA_3D_CMD_DX_SET_BLEND_STATE 1162 */
2361static int vmsvga3dCmdDXSetBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetBlendState const *pCmd, uint32_t cbCmd)
2362{
2363#ifdef VMSVGA3D_DX
2364 //DEBUG_BREAKPOINT_TEST();
2365 RT_NOREF(cbCmd);
2366 return vmsvga3dDXSetBlendState(pThisCC, idDXContext, pCmd);
2367#else
2368 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2369 return VERR_NOT_SUPPORTED;
2370#endif
2371}
2372
2373
2374/* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE 1163 */
2375static int vmsvga3dCmdDXSetDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDepthStencilState const *pCmd, uint32_t cbCmd)
2376{
2377#ifdef VMSVGA3D_DX
2378 //DEBUG_BREAKPOINT_TEST();
2379 RT_NOREF(cbCmd);
2380 return vmsvga3dDXSetDepthStencilState(pThisCC, idDXContext, pCmd);
2381#else
2382 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2383 return VERR_NOT_SUPPORTED;
2384#endif
2385}
2386
2387
2388/* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE 1164 */
2389static int vmsvga3dCmdDXSetRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRasterizerState const *pCmd, uint32_t cbCmd)
2390{
2391#ifdef VMSVGA3D_DX
2392 //DEBUG_BREAKPOINT_TEST();
2393 RT_NOREF(cbCmd);
2394 return vmsvga3dDXSetRasterizerState(pThisCC, idDXContext, pCmd->rasterizerId);
2395#else
2396 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2397 return VERR_NOT_SUPPORTED;
2398#endif
2399}
2400
2401
2402/* SVGA_3D_CMD_DX_DEFINE_QUERY 1165 */
2403static int vmsvga3dCmdDXDefineQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineQuery const *pCmd, uint32_t cbCmd)
2404{
2405#ifdef VMSVGA3D_DX
2406 //DEBUG_BREAKPOINT_TEST();
2407 RT_NOREF(cbCmd);
2408 return vmsvga3dDXDefineQuery(pThisCC, idDXContext, pCmd);
2409#else
2410 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2411 return VERR_NOT_SUPPORTED;
2412#endif
2413}
2414
2415
2416/* SVGA_3D_CMD_DX_DESTROY_QUERY 1166 */
2417static int vmsvga3dCmdDXDestroyQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyQuery const *pCmd, uint32_t cbCmd)
2418{
2419#ifdef VMSVGA3D_DX
2420 //DEBUG_BREAKPOINT_TEST();
2421 RT_NOREF(cbCmd);
2422 return vmsvga3dDXDestroyQuery(pThisCC, idDXContext, pCmd);
2423#else
2424 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2425 return VERR_NOT_SUPPORTED;
2426#endif
2427}
2428
2429
2430/* SVGA_3D_CMD_DX_BIND_QUERY 1167 */
2431static int vmsvga3dCmdDXBindQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindQuery const *pCmd, uint32_t cbCmd)
2432{
2433#ifdef VMSVGA3D_DX
2434 //DEBUG_BREAKPOINT_TEST();
2435 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2436 RT_NOREF(cbCmd);
2437 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
2438 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2439 return vmsvga3dDXBindQuery(pThisCC, idDXContext, pCmd, pMob);
2440#else
2441 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2442 return VERR_NOT_SUPPORTED;
2443#endif
2444}
2445
2446
2447/* SVGA_3D_CMD_DX_SET_QUERY_OFFSET 1168 */
2448static int vmsvga3dCmdDXSetQueryOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetQueryOffset const *pCmd, uint32_t cbCmd)
2449{
2450#ifdef VMSVGA3D_DX
2451 //DEBUG_BREAKPOINT_TEST();
2452 RT_NOREF(cbCmd);
2453 return vmsvga3dDXSetQueryOffset(pThisCC, idDXContext, pCmd);
2454#else
2455 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2456 return VERR_NOT_SUPPORTED;
2457#endif
2458}
2459
2460
2461/* SVGA_3D_CMD_DX_BEGIN_QUERY 1169 */
2462static int vmsvga3dCmdDXBeginQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBeginQuery const *pCmd, uint32_t cbCmd)
2463{
2464#ifdef VMSVGA3D_DX
2465 //DEBUG_BREAKPOINT_TEST();
2466 RT_NOREF(cbCmd);
2467 return vmsvga3dDXBeginQuery(pThisCC, idDXContext, pCmd);
2468#else
2469 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2470 return VERR_NOT_SUPPORTED;
2471#endif
2472}
2473
2474
2475/* SVGA_3D_CMD_DX_END_QUERY 1170 */
2476static int vmsvga3dCmdDXEndQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXEndQuery const *pCmd, uint32_t cbCmd)
2477{
2478#ifdef VMSVGA3D_DX
2479 //DEBUG_BREAKPOINT_TEST();
2480 RT_NOREF(cbCmd);
2481 return vmsvga3dDXEndQuery(pThisCC, idDXContext, pCmd);
2482#else
2483 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2484 return VERR_NOT_SUPPORTED;
2485#endif
2486}
2487
2488
2489/* SVGA_3D_CMD_DX_READBACK_QUERY 1171 */
2490static int vmsvga3dCmdDXReadbackQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackQuery const *pCmd, uint32_t cbCmd)
2491{
2492#ifdef VMSVGA3D_DX
2493 //DEBUG_BREAKPOINT_TEST();
2494 RT_NOREF(cbCmd);
2495 return vmsvga3dDXReadbackQuery(pThisCC, idDXContext, pCmd);
2496#else
2497 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2498 return VERR_NOT_SUPPORTED;
2499#endif
2500}
2501
2502
2503/* SVGA_3D_CMD_DX_SET_PREDICATION 1172 */
2504static int vmsvga3dCmdDXSetPredication(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPredication const *pCmd, uint32_t cbCmd)
2505{
2506#ifdef VMSVGA3D_DX
2507 DEBUG_BREAKPOINT_TEST();
2508 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2509 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2510 return vmsvga3dDXSetPredication(pThisCC, idDXContext);
2511#else
2512 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2513 return VERR_NOT_SUPPORTED;
2514#endif
2515}
2516
2517
2518/* SVGA_3D_CMD_DX_SET_SOTARGETS 1173 */
2519static int vmsvga3dCmdDXSetSOTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSOTargets const *pCmd, uint32_t cbCmd)
2520{
2521#ifdef VMSVGA3D_DX
2522 //DEBUG_BREAKPOINT_TEST();
2523 SVGA3dSoTarget const *paSoTarget = (SVGA3dSoTarget *)&pCmd[1];
2524 uint32_t const cSoTarget = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSoTarget);
2525 return vmsvga3dDXSetSOTargets(pThisCC, idDXContext, cSoTarget, paSoTarget);
2526#else
2527 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2528 return VERR_NOT_SUPPORTED;
2529#endif
2530}
2531
2532
2533/* SVGA_3D_CMD_DX_SET_VIEWPORTS 1174 */
2534static int vmsvga3dCmdDXSetViewports(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetViewports const *pCmd, uint32_t cbCmd)
2535{
2536#ifdef VMSVGA3D_DX
2537 //DEBUG_BREAKPOINT_TEST();
2538 SVGA3dViewport const *paViewport = (SVGA3dViewport *)&pCmd[1];
2539 uint32_t const cViewport = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dViewport);
2540 return vmsvga3dDXSetViewports(pThisCC, idDXContext, cViewport, paViewport);
2541#else
2542 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2543 return VERR_NOT_SUPPORTED;
2544#endif
2545}
2546
2547
2548/* SVGA_3D_CMD_DX_SET_SCISSORRECTS 1175 */
2549static int vmsvga3dCmdDXSetScissorRects(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetScissorRects const *pCmd, uint32_t cbCmd)
2550{
2551#ifdef VMSVGA3D_DX
2552 //DEBUG_BREAKPOINT_TEST();
2553 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
2554 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
2555 return vmsvga3dDXSetScissorRects(pThisCC, idDXContext, cRect, paRect);
2556#else
2557 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2558 return VERR_NOT_SUPPORTED;
2559#endif
2560}
2561
2562
2563/* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW 1176 */
2564static int vmsvga3dCmdDXClearRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearRenderTargetView const *pCmd, uint32_t cbCmd)
2565{
2566#ifdef VMSVGA3D_DX
2567 //DEBUG_BREAKPOINT_TEST();
2568 RT_NOREF(cbCmd);
2569 return vmsvga3dDXClearRenderTargetView(pThisCC, idDXContext, pCmd);
2570#else
2571 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2572 return VERR_NOT_SUPPORTED;
2573#endif
2574}
2575
2576
2577/* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW 1177 */
2578static int vmsvga3dCmdDXClearDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearDepthStencilView const *pCmd, uint32_t cbCmd)
2579{
2580#ifdef VMSVGA3D_DX
2581 //DEBUG_BREAKPOINT_TEST();
2582 RT_NOREF(cbCmd);
2583 return vmsvga3dDXClearDepthStencilView(pThisCC, idDXContext, pCmd);
2584#else
2585 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2586 return VERR_NOT_SUPPORTED;
2587#endif
2588}
2589
2590
2591/* SVGA_3D_CMD_DX_PRED_COPY_REGION 1178 */
2592static int vmsvga3dCmdDXPredCopyRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopyRegion const *pCmd, uint32_t cbCmd)
2593{
2594#ifdef VMSVGA3D_DX
2595 //DEBUG_BREAKPOINT_TEST();
2596 RT_NOREF(cbCmd);
2597 return vmsvga3dDXPredCopyRegion(pThisCC, idDXContext, pCmd);
2598#else
2599 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2600 return VERR_NOT_SUPPORTED;
2601#endif
2602}
2603
2604
2605/* SVGA_3D_CMD_DX_PRED_COPY 1179 */
2606static int vmsvga3dCmdDXPredCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopy const *pCmd, uint32_t cbCmd)
2607{
2608#ifdef VMSVGA3D_DX
2609 DEBUG_BREAKPOINT_TEST();
2610 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2611 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2612 return vmsvga3dDXPredCopy(pThisCC, idDXContext);
2613#else
2614 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2615 return VERR_NOT_SUPPORTED;
2616#endif
2617}
2618
2619
2620/* SVGA_3D_CMD_DX_PRESENTBLT 1180 */
2621static int vmsvga3dCmdDXPresentBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPresentBlt const *pCmd, uint32_t cbCmd)
2622{
2623#ifdef VMSVGA3D_DX
2624 DEBUG_BREAKPOINT_TEST();
2625 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2626 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2627 return vmsvga3dDXPresentBlt(pThisCC, idDXContext);
2628#else
2629 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2630 return VERR_NOT_SUPPORTED;
2631#endif
2632}
2633
2634
2635/* SVGA_3D_CMD_DX_GENMIPS 1181 */
2636static int vmsvga3dCmdDXGenMips(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGenMips const *pCmd, uint32_t cbCmd)
2637{
2638#ifdef VMSVGA3D_DX
2639 //DEBUG_BREAKPOINT_TEST();
2640 RT_NOREF(cbCmd);
2641 return vmsvga3dDXGenMips(pThisCC, idDXContext, pCmd);
2642#else
2643 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2644 return VERR_NOT_SUPPORTED;
2645#endif
2646}
2647
2648
2649/* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE 1182 */
2650static int vmsvga3dCmdDXUpdateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXUpdateSubResource const *pCmd, uint32_t cbCmd)
2651{
2652#ifdef VMSVGA3D_DX
2653 //DEBUG_BREAKPOINT_TEST();
2654 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2655 RT_NOREF(cbCmd);
2656
2657 LogFlowFunc(("sid=%u, subResource=%u, box=%d,%d,%d %ux%ux%u\n",
2658 pCmd->sid, pCmd->subResource, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.z));
2659
2660 /* "Inform the device that the guest-contents have been updated." */
2661 SVGAOTableSurfaceEntry entrySurface;
2662 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2663 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2664 if (RT_SUCCESS(rc))
2665 {
2666 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2667 if (pMob)
2668 {
2669 uint32 const cSubresource = vmsvga3dGetSubresourceCount(pThisCC, pCmd->sid);
2670 ASSERT_GUEST_RETURN(pCmd->subResource < cSubresource, VERR_INVALID_PARAMETER);
2671 /* pCmd->box will be verified by the mapping function. */
2672 RT_UNTRUSTED_VALIDATED_FENCE();
2673
2674 /** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2675 SVGA3dSurfaceImageId image;
2676 image.sid = pCmd->sid;
2677 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2678
2679 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
2680 AssertRC(rc);
2681 }
2682 }
2683
2684 return rc;
2685#else
2686 RT_NOREF(pThisCC, pCmd, cbCmd);
2687 return VERR_NOT_SUPPORTED;
2688#endif
2689}
2690
2691
2692/* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE 1183 */
2693static int vmsvga3dCmdDXReadbackSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackSubResource const *pCmd, uint32_t cbCmd)
2694{
2695#ifdef VMSVGA3D_DX
2696 //DEBUG_BREAKPOINT_TEST();
2697 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2698 RT_NOREF(cbCmd);
2699
2700 LogFlowFunc(("sid=%u, subResource=%u\n",
2701 pCmd->sid, pCmd->subResource));
2702
2703 /* "Request the device to flush the dirty contents into the guest." */
2704 SVGAOTableSurfaceEntry entrySurface;
2705 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2706 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2707 if (RT_SUCCESS(rc))
2708 {
2709 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2710 if (pMob)
2711 {
2712 uint32 const cSubresource = vmsvga3dGetSubresourceCount(pThisCC, pCmd->sid);
2713 ASSERT_GUEST_RETURN(pCmd->subResource < cSubresource, VERR_INVALID_PARAMETER);
2714 RT_UNTRUSTED_VALIDATED_FENCE();
2715
2716 /** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2717 SVGA3dSurfaceImageId image;
2718 image.sid = pCmd->sid;
2719 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2720
2721 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
2722 AssertRC(rc);
2723 }
2724 }
2725
2726 return rc;
2727#else
2728 RT_NOREF(pThisCC, pCmd, cbCmd);
2729 return VERR_NOT_SUPPORTED;
2730#endif
2731}
2732
2733
2734/* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE 1184 */
2735static int vmsvga3dCmdDXInvalidateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXInvalidateSubResource const *pCmd, uint32_t cbCmd)
2736{
2737#ifdef VMSVGA3D_DX
2738 DEBUG_BREAKPOINT_TEST();
2739 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2740 RT_NOREF(cbCmd);
2741
2742 LogFlowFunc(("sid=%u, subResource=%u\n",
2743 pCmd->sid, pCmd->subResource));
2744
2745 /* "Notify the device that the contents can be lost." */
2746 SVGAOTableSurfaceEntry entrySurface;
2747 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2748 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2749 if (RT_SUCCESS(rc))
2750 {
2751 uint32_t iFace;
2752 uint32_t iMipmap;
2753 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &iMipmap, &iFace);
2754 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, iFace, iMipmap);
2755 }
2756
2757 return rc;
2758#else
2759 RT_NOREF(pThisCC, pCmd, cbCmd);
2760 return VERR_NOT_SUPPORTED;
2761#endif
2762}
2763
2764
2765/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW 1185 */
2766static int vmsvga3dCmdDXDefineShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShaderResourceView const *pCmd, uint32_t cbCmd)
2767{
2768#ifdef VMSVGA3D_DX
2769 //DEBUG_BREAKPOINT_TEST();
2770 RT_NOREF(cbCmd);
2771 return vmsvga3dDXDefineShaderResourceView(pThisCC, idDXContext, pCmd);
2772#else
2773 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2774 return VERR_NOT_SUPPORTED;
2775#endif
2776}
2777
2778
2779/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW 1186 */
2780static int vmsvga3dCmdDXDestroyShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShaderResourceView const *pCmd, uint32_t cbCmd)
2781{
2782#ifdef VMSVGA3D_DX
2783 //DEBUG_BREAKPOINT_TEST();
2784 RT_NOREF(cbCmd);
2785 return vmsvga3dDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd);
2786#else
2787 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2788 return VERR_NOT_SUPPORTED;
2789#endif
2790}
2791
2792
2793/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW 1187 */
2794static int vmsvga3dCmdDXDefineRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRenderTargetView const *pCmd, uint32_t cbCmd)
2795{
2796#ifdef VMSVGA3D_DX
2797 //DEBUG_BREAKPOINT_TEST();
2798 RT_NOREF(cbCmd);
2799 return vmsvga3dDXDefineRenderTargetView(pThisCC, idDXContext, pCmd);
2800#else
2801 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2802 return VERR_NOT_SUPPORTED;
2803#endif
2804}
2805
2806
2807/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW 1188 */
2808static int vmsvga3dCmdDXDestroyRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRenderTargetView const *pCmd, uint32_t cbCmd)
2809{
2810#ifdef VMSVGA3D_DX
2811 //DEBUG_BREAKPOINT_TEST();
2812 RT_NOREF(cbCmd);
2813 return vmsvga3dDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd);
2814#else
2815 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2816 return VERR_NOT_SUPPORTED;
2817#endif
2818}
2819
2820
2821/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW 1189 */
2822static int vmsvga3dCmdDXDefineDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView const *pCmd, uint32_t cbCmd)
2823{
2824#ifdef VMSVGA3D_DX
2825 //DEBUG_BREAKPOINT_TEST();
2826 RT_NOREF(cbCmd);
2827 SVGA3dCmdDXDefineDepthStencilView_v2 cmd;
2828 cmd.depthStencilViewId = pCmd->depthStencilViewId;
2829 cmd.sid = pCmd->sid;
2830 cmd.format = pCmd->format;
2831 cmd.resourceDimension = pCmd->resourceDimension;
2832 cmd.mipSlice = pCmd->mipSlice;
2833 cmd.firstArraySlice = pCmd->firstArraySlice;
2834 cmd.arraySize = pCmd->arraySize;
2835 cmd.flags = 0;
2836 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, &cmd);
2837#else
2838 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2839 return VERR_NOT_SUPPORTED;
2840#endif
2841}
2842
2843
2844/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW 1190 */
2845static int vmsvga3dCmdDXDestroyDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilView const *pCmd, uint32_t cbCmd)
2846{
2847#ifdef VMSVGA3D_DX
2848 //DEBUG_BREAKPOINT_TEST();
2849 RT_NOREF(cbCmd);
2850 return vmsvga3dDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd);
2851#else
2852 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2853 return VERR_NOT_SUPPORTED;
2854#endif
2855}
2856
2857
2858/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT 1191 */
2859static int vmsvga3dCmdDXDefineElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineElementLayout const *pCmd, uint32_t cbCmd)
2860{
2861#ifdef VMSVGA3D_DX
2862 //DEBUG_BREAKPOINT_TEST();
2863 SVGA3dInputElementDesc const *paDesc = (SVGA3dInputElementDesc *)&pCmd[1];
2864 uint32_t const cDesc = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dInputElementDesc);
2865 return vmsvga3dDXDefineElementLayout(pThisCC, idDXContext, pCmd->elementLayoutId, cDesc, paDesc);
2866#else
2867 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2868 return VERR_NOT_SUPPORTED;
2869#endif
2870}
2871
2872
2873/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT 1192 */
2874static int vmsvga3dCmdDXDestroyElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyElementLayout const *pCmd, uint32_t cbCmd)
2875{
2876#ifdef VMSVGA3D_DX
2877 //DEBUG_BREAKPOINT_TEST();
2878 RT_NOREF(cbCmd);
2879 return vmsvga3dDXDestroyElementLayout(pThisCC, idDXContext, pCmd);
2880#else
2881 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2882 return VERR_NOT_SUPPORTED;
2883#endif
2884}
2885
2886
2887/* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE 1193 */
2888static int vmsvga3dCmdDXDefineBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineBlendState const *pCmd, uint32_t cbCmd)
2889{
2890#ifdef VMSVGA3D_DX
2891 //DEBUG_BREAKPOINT_TEST();
2892 RT_NOREF(cbCmd);
2893 return vmsvga3dDXDefineBlendState(pThisCC, idDXContext, pCmd);
2894#else
2895 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2896 return VERR_NOT_SUPPORTED;
2897#endif
2898}
2899
2900
2901/* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE 1194 */
2902static int vmsvga3dCmdDXDestroyBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyBlendState const *pCmd, uint32_t cbCmd)
2903{
2904#ifdef VMSVGA3D_DX
2905 DEBUG_BREAKPOINT_TEST();
2906 RT_NOREF(cbCmd);
2907 return vmsvga3dDXDestroyBlendState(pThisCC, idDXContext, pCmd);
2908#else
2909 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2910 return VERR_NOT_SUPPORTED;
2911#endif
2912}
2913
2914
2915/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE 1195 */
2916static int vmsvga3dCmdDXDefineDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilState const *pCmd, uint32_t cbCmd)
2917{
2918#ifdef VMSVGA3D_DX
2919 //DEBUG_BREAKPOINT_TEST();
2920 RT_NOREF(cbCmd);
2921 return vmsvga3dDXDefineDepthStencilState(pThisCC, idDXContext, pCmd);
2922#else
2923 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2924 return VERR_NOT_SUPPORTED;
2925#endif
2926}
2927
2928
2929/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE 1196 */
2930static int vmsvga3dCmdDXDestroyDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilState const *pCmd, uint32_t cbCmd)
2931{
2932#ifdef VMSVGA3D_DX
2933 DEBUG_BREAKPOINT_TEST();
2934 RT_NOREF(cbCmd);
2935 return vmsvga3dDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd);
2936#else
2937 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2938 return VERR_NOT_SUPPORTED;
2939#endif
2940}
2941
2942
2943/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE 1197 */
2944static int vmsvga3dCmdDXDefineRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRasterizerState const *pCmd, uint32_t cbCmd)
2945{
2946#ifdef VMSVGA3D_DX
2947 //DEBUG_BREAKPOINT_TEST();
2948 RT_NOREF(cbCmd);
2949 return vmsvga3dDXDefineRasterizerState(pThisCC, idDXContext, pCmd);
2950#else
2951 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2952 return VERR_NOT_SUPPORTED;
2953#endif
2954}
2955
2956
2957/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE 1198 */
2958static int vmsvga3dCmdDXDestroyRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRasterizerState const *pCmd, uint32_t cbCmd)
2959{
2960#ifdef VMSVGA3D_DX
2961 DEBUG_BREAKPOINT_TEST();
2962 RT_NOREF(cbCmd);
2963 return vmsvga3dDXDestroyRasterizerState(pThisCC, idDXContext, pCmd);
2964#else
2965 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2966 return VERR_NOT_SUPPORTED;
2967#endif
2968}
2969
2970
2971/* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE 1199 */
2972static int vmsvga3dCmdDXDefineSamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineSamplerState const *pCmd, uint32_t cbCmd)
2973{
2974#ifdef VMSVGA3D_DX
2975 //DEBUG_BREAKPOINT_TEST();
2976 RT_NOREF(cbCmd);
2977 return vmsvga3dDXDefineSamplerState(pThisCC, idDXContext, pCmd);
2978#else
2979 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2980 return VERR_NOT_SUPPORTED;
2981#endif
2982}
2983
2984
2985/* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE 1200 */
2986static int vmsvga3dCmdDXDestroySamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroySamplerState const *pCmd, uint32_t cbCmd)
2987{
2988#ifdef VMSVGA3D_DX
2989 DEBUG_BREAKPOINT_TEST();
2990 RT_NOREF(cbCmd);
2991 return vmsvga3dDXDestroySamplerState(pThisCC, idDXContext, pCmd);
2992#else
2993 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2994 return VERR_NOT_SUPPORTED;
2995#endif
2996}
2997
2998
2999/* SVGA_3D_CMD_DX_DEFINE_SHADER 1201 */
3000static int vmsvga3dCmdDXDefineShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShader const *pCmd, uint32_t cbCmd)
3001{
3002#ifdef VMSVGA3D_DX
3003 //DEBUG_BREAKPOINT_TEST();
3004 RT_NOREF(cbCmd);
3005 return vmsvga3dDXDefineShader(pThisCC, idDXContext, pCmd);
3006#else
3007 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3008 return VERR_NOT_SUPPORTED;
3009#endif
3010}
3011
3012
3013/* SVGA_3D_CMD_DX_DESTROY_SHADER 1202 */
3014static int vmsvga3dCmdDXDestroyShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShader const *pCmd, uint32_t cbCmd)
3015{
3016#ifdef VMSVGA3D_DX
3017 //DEBUG_BREAKPOINT_TEST();
3018 RT_NOREF(cbCmd);
3019 return vmsvga3dDXDestroyShader(pThisCC, idDXContext, pCmd);
3020#else
3021 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3022 return VERR_NOT_SUPPORTED;
3023#endif
3024}
3025
3026
3027/* SVGA_3D_CMD_DX_BIND_SHADER 1203 */
3028static int vmsvga3dCmdDXBindShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShader const *pCmd, uint32_t cbCmd)
3029{
3030#ifdef VMSVGA3D_DX
3031 //DEBUG_BREAKPOINT_TEST();
3032 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3033 RT_NOREF(idDXContext, cbCmd);
3034 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3035 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3036 return vmsvga3dDXBindShader(pThisCC, pCmd, pMob);
3037#else
3038 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3039 return VERR_NOT_SUPPORTED;
3040#endif
3041}
3042
3043
3044/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT 1204 */
3045static int vmsvga3dCmdDXDefineStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutput const *pCmd, uint32_t cbCmd)
3046{
3047#ifdef VMSVGA3D_DX
3048 //DEBUG_BREAKPOINT_TEST();
3049 RT_NOREF(cbCmd);
3050 return vmsvga3dDXDefineStreamOutput(pThisCC, idDXContext, pCmd);
3051#else
3052 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3053 return VERR_NOT_SUPPORTED;
3054#endif
3055}
3056
3057
3058/* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT 1205 */
3059static int vmsvga3dCmdDXDestroyStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyStreamOutput const *pCmd, uint32_t cbCmd)
3060{
3061#ifdef VMSVGA3D_DX
3062 //DEBUG_BREAKPOINT_TEST();
3063 RT_NOREF(cbCmd);
3064 return vmsvga3dDXDestroyStreamOutput(pThisCC, idDXContext, pCmd);
3065#else
3066 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3067 return VERR_NOT_SUPPORTED;
3068#endif
3069}
3070
3071
3072/* SVGA_3D_CMD_DX_SET_STREAMOUTPUT 1206 */
3073static int vmsvga3dCmdDXSetStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStreamOutput const *pCmd, uint32_t cbCmd)
3074{
3075#ifdef VMSVGA3D_DX
3076 //DEBUG_BREAKPOINT_TEST();
3077 RT_NOREF(cbCmd);
3078 return vmsvga3dDXSetStreamOutput(pThisCC, idDXContext, pCmd);
3079#else
3080 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3081 return VERR_NOT_SUPPORTED;
3082#endif
3083}
3084
3085
3086/* SVGA_3D_CMD_DX_SET_COTABLE 1207 */
3087static int vmsvga3dCmdDXSetCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXSetCOTable const *pCmd, uint32_t cbCmd)
3088{
3089#ifdef VMSVGA3D_DX
3090 //DEBUG_BREAKPOINT_TEST();
3091 RT_NOREF(cbCmd);
3092 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3093 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3094 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3095 return vmsvga3dDXSetCOTable(pThisCC, pCmd, pMob);
3096#else
3097 RT_NOREF(pThisCC, pCmd, cbCmd);
3098 return VERR_NOT_SUPPORTED;
3099#endif
3100}
3101
3102
3103/* SVGA_3D_CMD_DX_READBACK_COTABLE 1208 */
3104static int vmsvga3dCmdDXReadbackCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackCOTable const *pCmd, uint32_t cbCmd)
3105{
3106#ifdef VMSVGA3D_DX
3107 //DEBUG_BREAKPOINT_TEST();
3108 RT_NOREF(idDXContext, cbCmd);
3109 return vmsvga3dDXReadbackCOTable(pThisCC, pCmd);
3110#else
3111 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3112 return VERR_NOT_SUPPORTED;
3113#endif
3114}
3115
3116
3117/* SVGA_3D_CMD_DX_BUFFER_COPY 1209 */
3118static int vmsvga3dCmdDXBufferCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferCopy const *pCmd, uint32_t cbCmd)
3119{
3120#ifdef VMSVGA3D_DX
3121 //DEBUG_BREAKPOINT_TEST();
3122 RT_NOREF(idDXContext, cbCmd);
3123
3124 int rc;
3125
3126 /** @todo Backend should o the copy is both buffers have a hardware resource. */
3127 SVGA3dSurfaceImageId imageBufferSrc;
3128 imageBufferSrc.sid = pCmd->src;
3129 imageBufferSrc.face = 0;
3130 imageBufferSrc.mipmap = 0;
3131
3132 SVGA3dSurfaceImageId imageBufferDest;
3133 imageBufferDest.sid = pCmd->dest;
3134 imageBufferDest.face = 0;
3135 imageBufferDest.mipmap = 0;
3136
3137 /*
3138 * Map the source buffer.
3139 */
3140 VMSVGA3D_MAPPED_SURFACE mapBufferSrc;
3141 rc = vmsvga3dSurfaceMap(pThisCC, &imageBufferSrc, NULL, VMSVGA3D_SURFACE_MAP_READ, &mapBufferSrc);
3142 if (RT_SUCCESS(rc))
3143 {
3144 /*
3145 * Map the destination buffer.
3146 */
3147 VMSVGA3D_MAPPED_SURFACE mapBufferDest;
3148 rc = vmsvga3dSurfaceMap(pThisCC, &imageBufferDest, NULL, VMSVGA3D_SURFACE_MAP_WRITE, &mapBufferDest);
3149 if (RT_SUCCESS(rc))
3150 {
3151 /*
3152 * Copy the source buffer to the destination.
3153 */
3154 uint8_t const *pu8BufferSrc = (uint8_t *)mapBufferSrc.pvData;
3155 uint32_t const cbBufferSrc = mapBufferSrc.cbRow;
3156
3157 uint8_t *pu8BufferDest = (uint8_t *)mapBufferDest.pvData;
3158 uint32_t const cbBufferDest = mapBufferDest.cbRow;
3159
3160 if ( pCmd->srcX < cbBufferSrc
3161 && pCmd->width <= cbBufferSrc- pCmd->srcX
3162 && pCmd->destX < cbBufferDest
3163 && pCmd->width <= cbBufferDest - pCmd->destX)
3164 {
3165 RT_UNTRUSTED_VALIDATED_FENCE();
3166
3167 memcpy(&pu8BufferDest[pCmd->destX], &pu8BufferSrc[pCmd->srcX], pCmd->width);
3168 }
3169 else
3170 ASSERT_GUEST_FAILED_STMT(rc = VERR_INVALID_PARAMETER);
3171
3172 vmsvga3dSurfaceUnmap(pThisCC, &imageBufferDest, &mapBufferDest, true);
3173 }
3174
3175 vmsvga3dSurfaceUnmap(pThisCC, &imageBufferSrc, &mapBufferSrc, false);
3176 }
3177
3178 return rc;
3179#else
3180 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3181 return VERR_NOT_SUPPORTED;
3182#endif
3183}
3184
3185
3186/* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER 1210 */
3187static int vmsvga3dCmdDXTransferFromBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXTransferFromBuffer const *pCmd, uint32_t cbCmd)
3188{
3189#ifdef VMSVGA3D_DX
3190 //DEBUG_BREAKPOINT_TEST();
3191 RT_NOREF(cbCmd);
3192
3193 /* Plan:
3194 * - map the buffer;
3195 * - map the surface;
3196 * - copy from buffer map to the surface map.
3197 */
3198
3199 int rc;
3200
3201 SVGA3dSurfaceImageId imageBuffer;
3202 imageBuffer.sid = pCmd->srcSid;
3203 imageBuffer.face = 0;
3204 imageBuffer.mipmap = 0;
3205
3206 SVGA3dSurfaceImageId imageSurface;
3207 imageSurface.sid = pCmd->destSid;
3208 rc = vmsvga3dCalcSurfaceMipmapAndFace(pThisCC, pCmd->destSid, pCmd->destSubResource, &imageSurface.mipmap, &imageSurface.face);
3209 AssertRCReturn(rc, rc);
3210
3211 /*
3212 * Map the buffer.
3213 */
3214 VMSVGA3D_MAPPED_SURFACE mapBuffer;
3215 rc = vmsvga3dSurfaceMap(pThisCC, &imageBuffer, NULL, VMSVGA3D_SURFACE_MAP_READ, &mapBuffer);
3216 if (RT_SUCCESS(rc))
3217 {
3218 /*
3219 * Map the surface.
3220 */
3221 VMSVGA3D_MAPPED_SURFACE mapSurface;
3222 rc = vmsvga3dSurfaceMap(pThisCC, &imageSurface, &pCmd->destBox, VMSVGA3D_SURFACE_MAP_WRITE, &mapSurface);
3223 if (RT_SUCCESS(rc))
3224 {
3225 /*
3226 * Copy the mapped buffer to the surface. "Raw byte wise transfer"
3227 */
3228 uint8_t const *pu8Buffer = (uint8_t *)mapBuffer.pvData;
3229 uint32_t const cbBuffer = mapBuffer.cbRow;
3230
3231 if (pCmd->srcOffset <= cbBuffer)
3232 {
3233 RT_UNTRUSTED_VALIDATED_FENCE();
3234 uint8_t const *pu8BufferBegin = pu8Buffer;
3235 uint8_t const *pu8BufferEnd = pu8Buffer + cbBuffer;
3236
3237 pu8Buffer += pCmd->srcOffset;
3238
3239 uint8_t *pu8Surface = (uint8_t *)mapSurface.pvData;
3240
3241 uint32_t const cbRowCopy = RT_MIN(pCmd->srcPitch, mapSurface.cbRow);
3242 for (uint32_t z = 0; z < mapSurface.box.d && RT_SUCCESS(rc); ++z)
3243 {
3244 uint8_t const *pu8BufferRow = pu8Buffer;
3245 uint8_t *pu8SurfaceRow = pu8Surface;
3246 for (uint32_t iRow = 0; iRow < mapSurface.cRows; ++iRow)
3247 {
3248 ASSERT_GUEST_STMT_BREAK( (uintptr_t)pu8BufferRow >= (uintptr_t)pu8BufferBegin
3249 && (uintptr_t)pu8BufferRow < (uintptr_t)pu8BufferEnd
3250 && (uintptr_t)pu8BufferRow < (uintptr_t)(pu8BufferRow + cbRowCopy)
3251 && (uintptr_t)(pu8BufferRow + cbRowCopy) > (uintptr_t)pu8BufferBegin
3252 && (uintptr_t)(pu8BufferRow + cbRowCopy) <= (uintptr_t)pu8BufferEnd,
3253 rc = VERR_INVALID_PARAMETER);
3254
3255 memcpy(pu8SurfaceRow, pu8BufferRow, cbRowCopy);
3256
3257 pu8SurfaceRow += mapSurface.cbRowPitch;
3258 pu8BufferRow += pCmd->srcPitch;
3259 }
3260
3261 pu8Buffer += pCmd->srcSlicePitch;
3262 pu8Surface += mapSurface.cbDepthPitch;
3263 }
3264 }
3265 else
3266 ASSERT_GUEST_FAILED_STMT(rc = VERR_INVALID_PARAMETER);
3267
3268 vmsvga3dSurfaceUnmap(pThisCC, &imageSurface, &mapSurface, true);
3269 }
3270
3271 vmsvga3dSurfaceUnmap(pThisCC, &imageBuffer, &mapBuffer, false);
3272 }
3273
3274 return rc;
3275#else
3276 RT_NOREF(pThisCC, pCmd, cbCmd);
3277 return VERR_NOT_SUPPORTED;
3278#endif
3279}
3280
3281
3282/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK 1211 */
3283static int vmsvga3dCmdDXSurfaceCopyAndReadback(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSurfaceCopyAndReadback const *pCmd, uint32_t cbCmd)
3284{
3285#ifdef VMSVGA3D_DX
3286 DEBUG_BREAKPOINT_TEST();
3287 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3288 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3289 return vmsvga3dDXSurfaceCopyAndReadback(pThisCC, idDXContext);
3290#else
3291 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3292 return VERR_NOT_SUPPORTED;
3293#endif
3294}
3295
3296
3297/* SVGA_3D_CMD_DX_MOVE_QUERY 1212 */
3298static int vmsvga3dCmdDXMoveQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMoveQuery const *pCmd, uint32_t cbCmd)
3299{
3300#ifdef VMSVGA3D_DX
3301 DEBUG_BREAKPOINT_TEST();
3302 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3303 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3304 return vmsvga3dDXMoveQuery(pThisCC, idDXContext);
3305#else
3306 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3307 return VERR_NOT_SUPPORTED;
3308#endif
3309}
3310
3311
3312/* SVGA_3D_CMD_DX_BIND_ALL_QUERY 1213 */
3313static int vmsvga3dCmdDXBindAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllQuery const *pCmd, uint32_t cbCmd)
3314{
3315#ifdef VMSVGA3D_DX
3316 //DEBUG_BREAKPOINT_TEST();
3317 RT_NOREF(cbCmd);
3318 return vmsvga3dDXBindAllQuery(pThisCC, idDXContext, pCmd);
3319#else
3320 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3321 return VERR_NOT_SUPPORTED;
3322#endif
3323}
3324
3325
3326/* SVGA_3D_CMD_DX_READBACK_ALL_QUERY 1214 */
3327static int vmsvga3dCmdDXReadbackAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackAllQuery const *pCmd, uint32_t cbCmd)
3328{
3329#ifdef VMSVGA3D_DX
3330 //DEBUG_BREAKPOINT_TEST();
3331 RT_NOREF(cbCmd);
3332 return vmsvga3dDXReadbackAllQuery(pThisCC, idDXContext, pCmd);
3333#else
3334 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3335 return VERR_NOT_SUPPORTED;
3336#endif
3337}
3338
3339
3340/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER 1215 */
3341static int vmsvga3dCmdDXPredTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredTransferFromBuffer const *pCmd, uint32_t cbCmd)
3342{
3343#ifdef VMSVGA3D_DX
3344 //DEBUG_BREAKPOINT_TEST();
3345 RT_NOREF(idDXContext, cbCmd);
3346
3347 /* This command is executed in a context: "The context is implied from the command buffer header."
3348 * However the device design allows to do the transfer without a context, so re-use context-less command handler.
3349 */
3350 SVGA3dCmdDXTransferFromBuffer cmd;
3351 cmd.srcSid = pCmd->srcSid;
3352 cmd.srcOffset = pCmd->srcOffset;
3353 cmd.srcPitch = pCmd->srcPitch;
3354 cmd.srcSlicePitch = pCmd->srcSlicePitch;
3355 cmd.destSid = pCmd->destSid;
3356 cmd.destSubResource = pCmd->destSubResource;
3357 cmd.destBox = pCmd->destBox;
3358 return vmsvga3dCmdDXTransferFromBuffer(pThisCC, &cmd, sizeof(cmd));
3359#else
3360 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3361 return VERR_NOT_SUPPORTED;
3362#endif
3363}
3364
3365
3366/* SVGA_3D_CMD_DX_MOB_FENCE_64 1216 */
3367static int vmsvga3dCmdDXMobFence64(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMobFence64 const *pCmd, uint32_t cbCmd)
3368{
3369#ifdef VMSVGA3D_DX
3370 DEBUG_BREAKPOINT_TEST();
3371 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3372 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3373 return vmsvga3dDXMobFence64(pThisCC, idDXContext);
3374#else
3375 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3376 return VERR_NOT_SUPPORTED;
3377#endif
3378}
3379
3380
3381/* SVGA_3D_CMD_DX_BIND_ALL_SHADER 1217 */
3382static int vmsvga3dCmdDXBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllShader const *pCmd, uint32_t cbCmd)
3383{
3384#ifdef VMSVGA3D_DX
3385 DEBUG_BREAKPOINT_TEST();
3386 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3387 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3388 return vmsvga3dDXBindAllShader(pThisCC, idDXContext);
3389#else
3390 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3391 return VERR_NOT_SUPPORTED;
3392#endif
3393}
3394
3395
3396/* SVGA_3D_CMD_DX_HINT 1218 */
3397static int vmsvga3dCmdDXHint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXHint const *pCmd, uint32_t cbCmd)
3398{
3399#ifdef VMSVGA3D_DX
3400 DEBUG_BREAKPOINT_TEST();
3401 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3402 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3403 return vmsvga3dDXHint(pThisCC, idDXContext);
3404#else
3405 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3406 return VERR_NOT_SUPPORTED;
3407#endif
3408}
3409
3410
3411/* SVGA_3D_CMD_DX_BUFFER_UPDATE 1219 */
3412static int vmsvga3dCmdDXBufferUpdate(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferUpdate const *pCmd, uint32_t cbCmd)
3413{
3414#ifdef VMSVGA3D_DX
3415 DEBUG_BREAKPOINT_TEST();
3416 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3417 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3418 return vmsvga3dDXBufferUpdate(pThisCC, idDXContext);
3419#else
3420 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3421 return VERR_NOT_SUPPORTED;
3422#endif
3423}
3424
3425
3426/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET 1220 */
3427static int vmsvga3dCmdDXSetVSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3428{
3429#ifdef VMSVGA3D_DX
3430 DEBUG_BREAKPOINT_TEST();
3431 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3432 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3433 return vmsvga3dDXSetVSConstantBufferOffset(pThisCC, idDXContext);
3434#else
3435 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3436 return VERR_NOT_SUPPORTED;
3437#endif
3438}
3439
3440
3441/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET 1221 */
3442static int vmsvga3dCmdDXSetPSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3443{
3444#ifdef VMSVGA3D_DX
3445 DEBUG_BREAKPOINT_TEST();
3446 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3447 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3448 return vmsvga3dDXSetPSConstantBufferOffset(pThisCC, idDXContext);
3449#else
3450 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3451 return VERR_NOT_SUPPORTED;
3452#endif
3453}
3454
3455
3456/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET 1222 */
3457static int vmsvga3dCmdDXSetGSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetGSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3458{
3459#ifdef VMSVGA3D_DX
3460 DEBUG_BREAKPOINT_TEST();
3461 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3462 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3463 return vmsvga3dDXSetGSConstantBufferOffset(pThisCC, idDXContext);
3464#else
3465 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3466 return VERR_NOT_SUPPORTED;
3467#endif
3468}
3469
3470
3471/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET 1223 */
3472static int vmsvga3dCmdDXSetHSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetHSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3473{
3474#ifdef VMSVGA3D_DX
3475 DEBUG_BREAKPOINT_TEST();
3476 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3477 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3478 return vmsvga3dDXSetHSConstantBufferOffset(pThisCC, idDXContext);
3479#else
3480 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3481 return VERR_NOT_SUPPORTED;
3482#endif
3483}
3484
3485
3486/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET 1224 */
3487static int vmsvga3dCmdDXSetDSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3488{
3489#ifdef VMSVGA3D_DX
3490 DEBUG_BREAKPOINT_TEST();
3491 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3492 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3493 return vmsvga3dDXSetDSConstantBufferOffset(pThisCC, idDXContext);
3494#else
3495 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3496 return VERR_NOT_SUPPORTED;
3497#endif
3498}
3499
3500
3501/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET 1225 */
3502static int vmsvga3dCmdDXSetCSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3503{
3504#ifdef VMSVGA3D_DX
3505 DEBUG_BREAKPOINT_TEST();
3506 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3507 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3508 return vmsvga3dDXSetCSConstantBufferOffset(pThisCC, idDXContext);
3509#else
3510 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3511 return VERR_NOT_SUPPORTED;
3512#endif
3513}
3514
3515
3516/* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER 1226 */
3517static int vmsvga3dCmdDXCondBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCondBindAllShader const *pCmd, uint32_t cbCmd)
3518{
3519#ifdef VMSVGA3D_DX
3520 DEBUG_BREAKPOINT_TEST();
3521 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3522 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3523 return vmsvga3dDXCondBindAllShader(pThisCC, idDXContext);
3524#else
3525 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3526 return VERR_NOT_SUPPORTED;
3527#endif
3528}
3529
3530
3531/* SVGA_3D_CMD_SCREEN_COPY 1227 */
3532static int vmsvga3dCmdScreenCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdScreenCopy const *pCmd, uint32_t cbCmd)
3533{
3534#ifdef VMSVGA3D_DX
3535 DEBUG_BREAKPOINT_TEST();
3536 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3537 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3538 return vmsvga3dScreenCopy(pThisCC, idDXContext);
3539#else
3540 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3541 return VERR_NOT_SUPPORTED;
3542#endif
3543}
3544
3545
3546/* SVGA_3D_CMD_GROW_OTABLE 1236 */
3547static int vmsvga3dCmdGrowOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdGrowOTable const *pCmd, uint32_t cbCmd)
3548{
3549#ifdef VMSVGA3D_DX
3550 DEBUG_BREAKPOINT_TEST();
3551 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3552 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3553 return vmsvga3dGrowOTable(pThisCC, idDXContext);
3554#else
3555 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3556 return VERR_NOT_SUPPORTED;
3557#endif
3558}
3559
3560
3561/* SVGA_3D_CMD_DX_GROW_COTABLE 1237 */
3562static int vmsvga3dCmdDXGrowCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGrowCOTable const *pCmd, uint32_t cbCmd)
3563{
3564#ifdef VMSVGA3D_DX
3565 DEBUG_BREAKPOINT_TEST();
3566 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3567 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3568 return vmsvga3dDXGrowCOTable(pThisCC, idDXContext);
3569#else
3570 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3571 return VERR_NOT_SUPPORTED;
3572#endif
3573}
3574
3575
3576/* SVGA_3D_CMD_INTRA_SURFACE_COPY 1238 */
3577static int vmsvga3dCmdIntraSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdIntraSurfaceCopy const *pCmd, uint32_t cbCmd)
3578{
3579#ifdef VMSVGA3D_DX
3580 DEBUG_BREAKPOINT_TEST();
3581 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3582 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3583 return vmsvga3dIntraSurfaceCopy(pThisCC, idDXContext);
3584#else
3585 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3586 return VERR_NOT_SUPPORTED;
3587#endif
3588}
3589
3590
3591/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 1239 */
3592static int vmsvga3dCmdDefineGBSurface_v3(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v3 const *pCmd, uint32_t cbCmd)
3593{
3594#ifdef VMSVGA3D_DX
3595 DEBUG_BREAKPOINT_TEST();
3596 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3597 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3598 return vmsvga3dDefineGBSurface_v3(pThisCC, idDXContext);
3599#else
3600 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3601 return VERR_NOT_SUPPORTED;
3602#endif
3603}
3604
3605
3606/* SVGA_3D_CMD_DX_RESOLVE_COPY 1240 */
3607static int vmsvga3dCmdDXResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXResolveCopy const *pCmd, uint32_t cbCmd)
3608{
3609#ifdef VMSVGA3D_DX
3610 DEBUG_BREAKPOINT_TEST();
3611 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3612 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3613 return vmsvga3dDXResolveCopy(pThisCC, idDXContext);
3614#else
3615 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3616 return VERR_NOT_SUPPORTED;
3617#endif
3618}
3619
3620
3621/* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY 1241 */
3622static int vmsvga3dCmdDXPredResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredResolveCopy const *pCmd, uint32_t cbCmd)
3623{
3624#ifdef VMSVGA3D_DX
3625 DEBUG_BREAKPOINT_TEST();
3626 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3627 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3628 return vmsvga3dDXPredResolveCopy(pThisCC, idDXContext);
3629#else
3630 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3631 return VERR_NOT_SUPPORTED;
3632#endif
3633}
3634
3635
3636/* SVGA_3D_CMD_DX_PRED_CONVERT_REGION 1242 */
3637static int vmsvga3dCmdDXPredConvertRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvertRegion const *pCmd, uint32_t cbCmd)
3638{
3639#ifdef VMSVGA3D_DX
3640 DEBUG_BREAKPOINT_TEST();
3641 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3642 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3643 return vmsvga3dDXPredConvertRegion(pThisCC, idDXContext);
3644#else
3645 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3646 return VERR_NOT_SUPPORTED;
3647#endif
3648}
3649
3650
3651/* SVGA_3D_CMD_DX_PRED_CONVERT 1243 */
3652static int vmsvga3dCmdDXPredConvert(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvert const *pCmd, uint32_t cbCmd)
3653{
3654#ifdef VMSVGA3D_DX
3655 DEBUG_BREAKPOINT_TEST();
3656 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3657 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3658 return vmsvga3dDXPredConvert(pThisCC, idDXContext);
3659#else
3660 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3661 return VERR_NOT_SUPPORTED;
3662#endif
3663}
3664
3665
3666/* SVGA_3D_CMD_WHOLE_SURFACE_COPY 1244 */
3667static int vmsvga3dCmdWholeSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWholeSurfaceCopy const *pCmd, uint32_t cbCmd)
3668{
3669#ifdef VMSVGA3D_DX
3670 DEBUG_BREAKPOINT_TEST();
3671 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3672 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3673 return vmsvga3dWholeSurfaceCopy(pThisCC, idDXContext);
3674#else
3675 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3676 return VERR_NOT_SUPPORTED;
3677#endif
3678}
3679
3680
3681/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW 1245 */
3682static int vmsvga3dCmdDXDefineUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineUAView const *pCmd, uint32_t cbCmd)
3683{
3684#ifdef VMSVGA3D_DX
3685 DEBUG_BREAKPOINT_TEST();
3686 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3687 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3688 return vmsvga3dDXDefineUAView(pThisCC, idDXContext);
3689#else
3690 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3691 return VERR_NOT_SUPPORTED;
3692#endif
3693}
3694
3695
3696/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW 1246 */
3697static int vmsvga3dCmdDXDestroyUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyUAView const *pCmd, uint32_t cbCmd)
3698{
3699#ifdef VMSVGA3D_DX
3700 DEBUG_BREAKPOINT_TEST();
3701 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3702 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3703 return vmsvga3dDXDestroyUAView(pThisCC, idDXContext);
3704#else
3705 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3706 return VERR_NOT_SUPPORTED;
3707#endif
3708}
3709
3710
3711/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT 1247 */
3712static int vmsvga3dCmdDXClearUAViewUint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewUint const *pCmd, uint32_t cbCmd)
3713{
3714#ifdef VMSVGA3D_DX
3715 DEBUG_BREAKPOINT_TEST();
3716 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3717 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3718 return vmsvga3dDXClearUAViewUint(pThisCC, idDXContext);
3719#else
3720 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3721 return VERR_NOT_SUPPORTED;
3722#endif
3723}
3724
3725
3726/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT 1248 */
3727static int vmsvga3dCmdDXClearUAViewFloat(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewFloat const *pCmd, uint32_t cbCmd)
3728{
3729#ifdef VMSVGA3D_DX
3730 DEBUG_BREAKPOINT_TEST();
3731 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3732 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3733 return vmsvga3dDXClearUAViewFloat(pThisCC, idDXContext);
3734#else
3735 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3736 return VERR_NOT_SUPPORTED;
3737#endif
3738}
3739
3740
3741/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT 1249 */
3742static int vmsvga3dCmdDXCopyStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCopyStructureCount const *pCmd, uint32_t cbCmd)
3743{
3744#ifdef VMSVGA3D_DX
3745 DEBUG_BREAKPOINT_TEST();
3746 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3747 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3748 return vmsvga3dDXCopyStructureCount(pThisCC, idDXContext);
3749#else
3750 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3751 return VERR_NOT_SUPPORTED;
3752#endif
3753}
3754
3755
3756/* SVGA_3D_CMD_DX_SET_UA_VIEWS 1250 */
3757static int vmsvga3dCmdDXSetUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetUAViews const *pCmd, uint32_t cbCmd)
3758{
3759#ifdef VMSVGA3D_DX
3760 DEBUG_BREAKPOINT_TEST();
3761 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3762 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3763 return vmsvga3dDXSetUAViews(pThisCC, idDXContext);
3764#else
3765 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3766 return VERR_NOT_SUPPORTED;
3767#endif
3768}
3769
3770
3771/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT 1251 */
3772static int vmsvga3dCmdDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd, uint32_t cbCmd)
3773{
3774#ifdef VMSVGA3D_DX
3775 DEBUG_BREAKPOINT_TEST();
3776 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3777 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3778 return vmsvga3dDXDrawIndexedInstancedIndirect(pThisCC, idDXContext);
3779#else
3780 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3781 return VERR_NOT_SUPPORTED;
3782#endif
3783}
3784
3785
3786/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT 1252 */
3787static int vmsvga3dCmdDXDrawInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstancedIndirect const *pCmd, uint32_t cbCmd)
3788{
3789#ifdef VMSVGA3D_DX
3790 DEBUG_BREAKPOINT_TEST();
3791 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3792 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3793 return vmsvga3dDXDrawInstancedIndirect(pThisCC, idDXContext);
3794#else
3795 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3796 return VERR_NOT_SUPPORTED;
3797#endif
3798}
3799
3800
3801/* SVGA_3D_CMD_DX_DISPATCH 1253 */
3802static int vmsvga3dCmdDXDispatch(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatch const *pCmd, uint32_t cbCmd)
3803{
3804#ifdef VMSVGA3D_DX
3805 DEBUG_BREAKPOINT_TEST();
3806 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3807 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3808 return vmsvga3dDXDispatch(pThisCC, idDXContext);
3809#else
3810 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3811 return VERR_NOT_SUPPORTED;
3812#endif
3813}
3814
3815
3816/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT 1254 */
3817static int vmsvga3dCmdDXDispatchIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatchIndirect const *pCmd, uint32_t cbCmd)
3818{
3819#ifdef VMSVGA3D_DX
3820 DEBUG_BREAKPOINT_TEST();
3821 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3822 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3823 return vmsvga3dDXDispatchIndirect(pThisCC, idDXContext);
3824#else
3825 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3826 return VERR_NOT_SUPPORTED;
3827#endif
3828}
3829
3830
3831/* SVGA_3D_CMD_WRITE_ZERO_SURFACE 1255 */
3832static int vmsvga3dCmdWriteZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWriteZeroSurface const *pCmd, uint32_t cbCmd)
3833{
3834#ifdef VMSVGA3D_DX
3835 DEBUG_BREAKPOINT_TEST();
3836 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3837 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3838 return vmsvga3dWriteZeroSurface(pThisCC, idDXContext);
3839#else
3840 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3841 return VERR_NOT_SUPPORTED;
3842#endif
3843}
3844
3845
3846/* SVGA_3D_CMD_HINT_ZERO_SURFACE 1256 */
3847static int vmsvga3dCmdHintZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdHintZeroSurface const *pCmd, uint32_t cbCmd)
3848{
3849#ifdef VMSVGA3D_DX
3850 DEBUG_BREAKPOINT_TEST();
3851 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3852 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3853 return vmsvga3dHintZeroSurface(pThisCC, idDXContext);
3854#else
3855 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3856 return VERR_NOT_SUPPORTED;
3857#endif
3858}
3859
3860
3861/* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER 1257 */
3862static int vmsvga3dCmdDXTransferToBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferToBuffer const *pCmd, uint32_t cbCmd)
3863{
3864#ifdef VMSVGA3D_DX
3865 DEBUG_BREAKPOINT_TEST();
3866 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3867 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3868 return vmsvga3dDXTransferToBuffer(pThisCC, idDXContext);
3869#else
3870 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3871 return VERR_NOT_SUPPORTED;
3872#endif
3873}
3874
3875
3876/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT 1258 */
3877static int vmsvga3dCmdDXSetStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStructureCount const *pCmd, uint32_t cbCmd)
3878{
3879#ifdef VMSVGA3D_DX
3880 DEBUG_BREAKPOINT_TEST();
3881 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3882 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3883 return vmsvga3dDXSetStructureCount(pThisCC, idDXContext);
3884#else
3885 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3886 return VERR_NOT_SUPPORTED;
3887#endif
3888}
3889
3890
3891/* SVGA_3D_CMD_LOGICOPS_BITBLT 1259 */
3892static int vmsvga3dCmdLogicOpsBitBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsBitBlt const *pCmd, uint32_t cbCmd)
3893{
3894#ifdef VMSVGA3D_DX
3895 DEBUG_BREAKPOINT_TEST();
3896 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3897 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3898 return vmsvga3dLogicOpsBitBlt(pThisCC, idDXContext);
3899#else
3900 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3901 return VERR_NOT_SUPPORTED;
3902#endif
3903}
3904
3905
3906/* SVGA_3D_CMD_LOGICOPS_TRANSBLT 1260 */
3907static int vmsvga3dCmdLogicOpsTransBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsTransBlt const *pCmd, uint32_t cbCmd)
3908{
3909#ifdef VMSVGA3D_DX
3910 DEBUG_BREAKPOINT_TEST();
3911 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3912 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3913 return vmsvga3dLogicOpsTransBlt(pThisCC, idDXContext);
3914#else
3915 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3916 return VERR_NOT_SUPPORTED;
3917#endif
3918}
3919
3920
3921/* SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1261 */
3922static int vmsvga3dCmdLogicOpsStretchBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsStretchBlt const *pCmd, uint32_t cbCmd)
3923{
3924#ifdef VMSVGA3D_DX
3925 DEBUG_BREAKPOINT_TEST();
3926 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3927 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3928 return vmsvga3dLogicOpsStretchBlt(pThisCC, idDXContext);
3929#else
3930 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3931 return VERR_NOT_SUPPORTED;
3932#endif
3933}
3934
3935
3936/* SVGA_3D_CMD_LOGICOPS_COLORFILL 1262 */
3937static int vmsvga3dCmdLogicOpsColorFill(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsColorFill const *pCmd, uint32_t cbCmd)
3938{
3939#ifdef VMSVGA3D_DX
3940 DEBUG_BREAKPOINT_TEST();
3941 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3942 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3943 return vmsvga3dLogicOpsColorFill(pThisCC, idDXContext);
3944#else
3945 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3946 return VERR_NOT_SUPPORTED;
3947#endif
3948}
3949
3950
3951/* SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1263 */
3952static int vmsvga3dCmdLogicOpsAlphaBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsAlphaBlend const *pCmd, uint32_t cbCmd)
3953{
3954#ifdef VMSVGA3D_DX
3955 DEBUG_BREAKPOINT_TEST();
3956 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3957 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3958 return vmsvga3dLogicOpsAlphaBlend(pThisCC, idDXContext);
3959#else
3960 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3961 return VERR_NOT_SUPPORTED;
3962#endif
3963}
3964
3965
3966/* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1264 */
3967static int vmsvga3dCmdLogicOpsClearTypeBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsClearTypeBlend const *pCmd, uint32_t cbCmd)
3968{
3969#ifdef VMSVGA3D_DX
3970 DEBUG_BREAKPOINT_TEST();
3971 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3972 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3973 return vmsvga3dLogicOpsClearTypeBlend(pThisCC, idDXContext);
3974#else
3975 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3976 return VERR_NOT_SUPPORTED;
3977#endif
3978}
3979
3980
3981/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 1267 */
3982static int vmsvga3dCmdDefineGBSurface_v4(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v4 const *pCmd, uint32_t cbCmd)
3983{
3984#ifdef VMSVGA3D_DX
3985 DEBUG_BREAKPOINT_TEST();
3986 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3987 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3988 return vmsvga3dDefineGBSurface_v4(pThisCC, idDXContext);
3989#else
3990 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3991 return VERR_NOT_SUPPORTED;
3992#endif
3993}
3994
3995
3996/* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS 1268 */
3997static int vmsvga3dCmdDXSetCSUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSUAViews const *pCmd, uint32_t cbCmd)
3998{
3999#ifdef VMSVGA3D_DX
4000 DEBUG_BREAKPOINT_TEST();
4001 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4002 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4003 return vmsvga3dDXSetCSUAViews(pThisCC, idDXContext);
4004#else
4005 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4006 return VERR_NOT_SUPPORTED;
4007#endif
4008}
4009
4010
4011/* SVGA_3D_CMD_DX_SET_MIN_LOD 1269 */
4012static int vmsvga3dCmdDXSetMinLOD(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetMinLOD const *pCmd, uint32_t cbCmd)
4013{
4014#ifdef VMSVGA3D_DX
4015 DEBUG_BREAKPOINT_TEST();
4016 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4017 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4018 return vmsvga3dDXSetMinLOD(pThisCC, idDXContext);
4019#else
4020 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4021 return VERR_NOT_SUPPORTED;
4022#endif
4023}
4024
4025
4026/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 1272 */
4027static int vmsvga3dCmdDXDefineDepthStencilView_v2(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd, uint32_t cbCmd)
4028{
4029#ifdef VMSVGA3D_DX
4030 //DEBUG_BREAKPOINT_TEST();
4031 RT_NOREF(cbCmd);
4032 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, pCmd);
4033#else
4034 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4035 return VERR_NOT_SUPPORTED;
4036#endif
4037}
4038
4039
4040/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB 1273 */
4041static int vmsvga3dCmdDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd, uint32_t cbCmd)
4042{
4043#ifdef VMSVGA3D_DX
4044 DEBUG_BREAKPOINT_TEST();
4045 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4046 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4047 return vmsvga3dDXDefineStreamOutputWithMob(pThisCC, idDXContext);
4048#else
4049 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4050 return VERR_NOT_SUPPORTED;
4051#endif
4052}
4053
4054
4055/* SVGA_3D_CMD_DX_SET_SHADER_IFACE 1274 */
4056static int vmsvga3dCmdDXSetShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderIface const *pCmd, uint32_t cbCmd)
4057{
4058#ifdef VMSVGA3D_DX
4059 DEBUG_BREAKPOINT_TEST();
4060 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4061 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4062 return vmsvga3dDXSetShaderIface(pThisCC, idDXContext);
4063#else
4064 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4065 return VERR_NOT_SUPPORTED;
4066#endif
4067}
4068
4069
4070/* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT 1275 */
4071static int vmsvga3dCmdDXBindStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindStreamOutput const *pCmd, uint32_t cbCmd)
4072{
4073#ifdef VMSVGA3D_DX
4074 DEBUG_BREAKPOINT_TEST();
4075 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4076 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4077 return vmsvga3dDXBindStreamOutput(pThisCC, idDXContext);
4078#else
4079 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4080 return VERR_NOT_SUPPORTED;
4081#endif
4082}
4083
4084
4085/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS 1276 */
4086static int vmsvga3dCmdSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdSurfaceStretchBltNonMSToMS const *pCmd, uint32_t cbCmd)
4087{
4088#ifdef VMSVGA3D_DX
4089 DEBUG_BREAKPOINT_TEST();
4090 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4091 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4092 return vmsvga3dSurfaceStretchBltNonMSToMS(pThisCC, idDXContext);
4093#else
4094 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4095 return VERR_NOT_SUPPORTED;
4096#endif
4097}
4098
4099
4100/* SVGA_3D_CMD_DX_BIND_SHADER_IFACE 1277 */
4101static int vmsvga3dCmdDXBindShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShaderIface const *pCmd, uint32_t cbCmd)
4102{
4103#ifdef VMSVGA3D_DX
4104 DEBUG_BREAKPOINT_TEST();
4105 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4106 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4107 return vmsvga3dDXBindShaderIface(pThisCC, idDXContext);
4108#else
4109 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4110 return VERR_NOT_SUPPORTED;
4111#endif
4112}
4113
4114
4115/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4116 * Check that the 3D command has at least a_cbMin of payload bytes after the
4117 * header. Will break out of the switch if it doesn't.
4118 */
4119# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4120 if (1) { \
4121 AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
4122 RT_UNTRUSTED_VALIDATED_FENCE(); \
4123 } else do {} while (0)
4124
4125# define VMSVGA_3D_CMD_NOTIMPL() \
4126 if (1) { \
4127 AssertMsgFailed(("Not implemented %d %s\n", enmCmdId, vmsvgaR3FifoCmdToString(enmCmdId))); \
4128 } else do {} while (0)
4129
4130/** SVGA_3D_CMD_* handler.
4131 * This function parses the command and calls the corresponding command handler.
4132 *
4133 * @param pThis The shared VGA/VMSVGA state.
4134 * @param pThisCC The VGA/VMSVGA state for the current context.
4135 * @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
4136 * @param enmCmdId SVGA_3D_CMD_* command identifier.
4137 * @param cbCmd Size of the command in bytes.
4138 * @param pvCmd Pointer to the command.
4139 * @returns VBox status code if an error was detected parsing a command.
4140 */
4141int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, SVGAFifo3dCmdId enmCmdId, uint32_t cbCmd, void const *pvCmd)
4142{
4143 if (enmCmdId > SVGA_3D_CMD_MAX)
4144 {
4145 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
4146 ASSERT_GUEST_FAILED_RETURN(VERR_NOT_IMPLEMENTED);
4147 }
4148
4149 int rcParse = VINF_SUCCESS;
4150 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
4151
4152 switch (enmCmdId)
4153 {
4154 case SVGA_3D_CMD_SURFACE_DEFINE:
4155 {
4156 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)pvCmd;
4157 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4158 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefine);
4159
4160 SVGA3dCmdDefineSurface_v2 cmd;
4161 cmd.sid = pCmd->sid;
4162 cmd.surfaceFlags = pCmd->surfaceFlags;
4163 cmd.format = pCmd->format;
4164 memcpy(cmd.face, pCmd->face, sizeof(cmd.face));
4165 cmd.multisampleCount = 0;
4166 cmd.autogenFilter = SVGA3D_TEX_FILTER_NONE;
4167
4168 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4169 vmsvga3dCmdDefineSurface(pThisCC, &cmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4170# ifdef DEBUG_GMR_ACCESS
4171 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4172# endif
4173 break;
4174 }
4175
4176 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4177 {
4178 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)pvCmd;
4179 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4180 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefineV2);
4181
4182 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4183 vmsvga3dCmdDefineSurface(pThisCC, pCmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4184# ifdef DEBUG_GMR_ACCESS
4185 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4186# endif
4187 break;
4188 }
4189
4190 case SVGA_3D_CMD_SURFACE_DESTROY:
4191 {
4192 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)pvCmd;
4193 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4194 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDestroy);
4195
4196 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4197 break;
4198 }
4199
4200 case SVGA_3D_CMD_SURFACE_COPY:
4201 {
4202 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)pvCmd;
4203 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4204 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceCopy);
4205
4206 uint32_t const cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4207 vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4208 break;
4209 }
4210
4211 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4212 {
4213 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)pvCmd;
4214 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4215 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceStretchBlt);
4216
4217 vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4218 &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4219 break;
4220 }
4221
4222 case SVGA_3D_CMD_SURFACE_DMA:
4223 {
4224 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)pvCmd;
4225 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4226 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDma);
4227
4228 uint64_t u64NanoTS = 0;
4229 if (LogRelIs3Enabled())
4230 u64NanoTS = RTTimeNanoTS();
4231 uint32_t const cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4232 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4233 vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4234 cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4235 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4236 if (LogRelIs3Enabled())
4237 {
4238 if (cCopyBoxes)
4239 {
4240 SVGA3dCopyBox *pFirstBox = (SVGA3dCopyBox *)(pCmd + 1);
4241 LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4242 (RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4243 pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4244 pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4245 }
4246 }
4247 break;
4248 }
4249
4250 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4251 {
4252 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)pvCmd;
4253 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4254 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceScreen);
4255
4256 static uint64_t u64FrameStartNanoTS = 0;
4257 static uint64_t u64ElapsedPerSecNano = 0;
4258 static int cFrames = 0;
4259 uint64_t u64NanoTS = 0;
4260 if (LogRelIs3Enabled())
4261 u64NanoTS = RTTimeNanoTS();
4262 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4263 STAM_REL_PROFILE_START(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4264 vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4265 pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4266 STAM_REL_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4267 if (LogRelIs3Enabled())
4268 {
4269 uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
4270 u64ElapsedPerSecNano += u64ElapsedNano;
4271
4272 SVGASignedRect *pFirstRect = cRects ? (SVGASignedRect *)(pCmd + 1) : &pCmd->destRect;
4273 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4274 (u64ElapsedNano) / 1000ULL, cRects,
4275 pFirstRect->left, pFirstRect->top,
4276 pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4277
4278 ++cFrames;
4279 if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
4280 {
4281 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
4282 cFrames, u64ElapsedPerSecNano / 1000ULL));
4283 u64FrameStartNanoTS = u64NanoTS;
4284 cFrames = 0;
4285 u64ElapsedPerSecNano = 0;
4286 }
4287 }
4288 break;
4289 }
4290
4291 case SVGA_3D_CMD_CONTEXT_DEFINE:
4292 {
4293 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)pvCmd;
4294 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4295 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDefine);
4296
4297 vmsvga3dContextDefine(pThisCC, pCmd->cid);
4298 break;
4299 }
4300
4301 case SVGA_3D_CMD_CONTEXT_DESTROY:
4302 {
4303 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)pvCmd;
4304 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4305 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDestroy);
4306
4307 vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4308 break;
4309 }
4310
4311 case SVGA_3D_CMD_SETTRANSFORM:
4312 {
4313 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)pvCmd;
4314 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4315 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTransform);
4316
4317 vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4318 break;
4319 }
4320
4321 case SVGA_3D_CMD_SETZRANGE:
4322 {
4323 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)pvCmd;
4324 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4325 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetZRange);
4326
4327 vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4328 break;
4329 }
4330
4331 case SVGA_3D_CMD_SETRENDERSTATE:
4332 {
4333 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)pvCmd;
4334 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4335 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderState);
4336
4337 uint32_t const cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4338 vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4339 break;
4340 }
4341
4342 case SVGA_3D_CMD_SETRENDERTARGET:
4343 {
4344 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)pvCmd;
4345 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4346 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderTarget);
4347
4348 vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4349 break;
4350 }
4351
4352 case SVGA_3D_CMD_SETTEXTURESTATE:
4353 {
4354 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)pvCmd;
4355 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4356 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTextureState);
4357
4358 uint32_t const cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4359 vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4360 break;
4361 }
4362
4363 case SVGA_3D_CMD_SETMATERIAL:
4364 {
4365 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)pvCmd;
4366 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4367 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetMaterial);
4368
4369 vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4370 break;
4371 }
4372
4373 case SVGA_3D_CMD_SETLIGHTDATA:
4374 {
4375 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)pvCmd;
4376 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4377 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightData);
4378
4379 vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4380 break;
4381 }
4382
4383 case SVGA_3D_CMD_SETLIGHTENABLED:
4384 {
4385 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)pvCmd;
4386 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4387 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightEnable);
4388
4389 vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4390 break;
4391 }
4392
4393 case SVGA_3D_CMD_SETVIEWPORT:
4394 {
4395 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)pvCmd;
4396 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4397 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetViewPort);
4398
4399 vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4400 break;
4401 }
4402
4403 case SVGA_3D_CMD_SETCLIPPLANE:
4404 {
4405 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)pvCmd;
4406 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4407 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetClipPlane);
4408
4409 vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4410 break;
4411 }
4412
4413 case SVGA_3D_CMD_CLEAR:
4414 {
4415 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)pvCmd;
4416 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4417 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dClear);
4418
4419 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4420 vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4421 break;
4422 }
4423
4424 case SVGA_3D_CMD_PRESENT:
4425 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4426 {
4427 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)pvCmd;
4428 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4429 if (enmCmdId == SVGA_3D_CMD_PRESENT)
4430 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent);
4431 else
4432 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresentReadBack);
4433
4434 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4435 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4436 vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4437 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4438 break;
4439 }
4440
4441 case SVGA_3D_CMD_SHADER_DEFINE:
4442 {
4443 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)pvCmd;
4444 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4445 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDefine);
4446
4447 uint32_t const cbData = (cbCmd - sizeof(*pCmd));
4448 vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4449 break;
4450 }
4451
4452 case SVGA_3D_CMD_SHADER_DESTROY:
4453 {
4454 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)pvCmd;
4455 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4456 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDestroy);
4457
4458 vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4459 break;
4460 }
4461
4462 case SVGA_3D_CMD_SET_SHADER:
4463 {
4464 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)pvCmd;
4465 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4466 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShader);
4467
4468 vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4469 break;
4470 }
4471
4472 case SVGA_3D_CMD_SET_SHADER_CONST:
4473 {
4474 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)pvCmd;
4475 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4476 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShaderConst);
4477
4478 uint32_t const cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4479 vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4480 break;
4481 }
4482
4483 case SVGA_3D_CMD_DRAW_PRIMITIVES:
4484 {
4485 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)pvCmd;
4486 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4487 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDrawPrimitives);
4488
4489 ASSERT_GUEST_STMT_BREAK(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES, rcParse = VERR_INVALID_PARAMETER);
4490 ASSERT_GUEST_STMT_BREAK(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS, rcParse = VERR_INVALID_PARAMETER);
4491 uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4492 + pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4493 ASSERT_GUEST_STMT_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd), rcParse = VERR_INVALID_PARAMETER);
4494
4495 uint32_t const cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4496 ASSERT_GUEST_STMT_BREAK(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls, rcParse = VERR_INVALID_PARAMETER);
4497 RT_UNTRUSTED_VALIDATED_FENCE();
4498
4499 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
4500 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *)&pVertexDecl[pCmd->numVertexDecls];
4501 SVGA3dVertexDivisor *pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor *)&pNumRange[pCmd->numRanges] : NULL;
4502
4503 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4504 vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4505 pNumRange, cVertexDivisor, pVertexDivisor);
4506 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4507 break;
4508 }
4509
4510 case SVGA_3D_CMD_SETSCISSORRECT:
4511 {
4512 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)pvCmd;
4513 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4514 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetScissorRect);
4515
4516 vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4517 break;
4518 }
4519
4520 case SVGA_3D_CMD_BEGIN_QUERY:
4521 {
4522 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)pvCmd;
4523 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4524 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dBeginQuery);
4525
4526 vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4527 break;
4528 }
4529
4530 case SVGA_3D_CMD_END_QUERY:
4531 {
4532 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)pvCmd;
4533 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4534 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dEndQuery);
4535
4536 vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type);
4537 break;
4538 }
4539
4540 case SVGA_3D_CMD_WAIT_FOR_QUERY:
4541 {
4542 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)pvCmd;
4543 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4544 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dWaitForQuery);
4545
4546 vmsvga3dQueryWait(pThisCC, pCmd->cid, pCmd->type, pThis, &pCmd->guestResult);
4547 break;
4548 }
4549
4550 case SVGA_3D_CMD_GENERATE_MIPMAPS:
4551 {
4552 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)pvCmd;
4553 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4554 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dGenerateMipmaps);
4555
4556 vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4557 break;
4558 }
4559
4560 case SVGA_3D_CMD_ACTIVATE_SURFACE:
4561 /* context id + surface id? */
4562 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dActivateSurface);
4563 break;
4564
4565 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4566 /* context id + surface id? */
4567 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDeactivateSurface);
4568 break;
4569
4570 /*
4571 *
4572 * VPGU10: SVGA_CAP_GBOBJECTS+ commands.
4573 *
4574 */
4575 case SVGA_3D_CMD_SCREEN_DMA:
4576 {
4577 SVGA3dCmdScreenDMA *pCmd = (SVGA3dCmdScreenDMA *)pvCmd;
4578 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4579 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4580 break;
4581 }
4582
4583 case SVGA_3D_CMD_DEAD1:
4584 case SVGA_3D_CMD_DEAD2:
4585 case SVGA_3D_CMD_DEAD12: /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
4586 case SVGA_3D_CMD_DEAD13: /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
4587 case SVGA_3D_CMD_DEAD14: /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
4588 case SVGA_3D_CMD_DEAD15: /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
4589 case SVGA_3D_CMD_DEAD16: /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
4590 case SVGA_3D_CMD_DEAD17: /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
4591 {
4592 VMSVGA_3D_CMD_NOTIMPL();
4593 break;
4594 }
4595
4596 case SVGA_3D_CMD_SET_OTABLE_BASE:
4597 {
4598 SVGA3dCmdSetOTableBase *pCmd = (SVGA3dCmdSetOTableBase *)pvCmd;
4599 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4600 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4601 break;
4602 }
4603
4604 case SVGA_3D_CMD_READBACK_OTABLE:
4605 {
4606 SVGA3dCmdReadbackOTable *pCmd = (SVGA3dCmdReadbackOTable *)pvCmd;
4607 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4608 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4609 break;
4610 }
4611
4612 case SVGA_3D_CMD_DEFINE_GB_MOB:
4613 {
4614 SVGA3dCmdDefineGBMob *pCmd = (SVGA3dCmdDefineGBMob *)pvCmd;
4615 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4616 vmsvga3dCmdDefineGBMob(pThisCC, pCmd);
4617 break;
4618 }
4619
4620 case SVGA_3D_CMD_DESTROY_GB_MOB:
4621 {
4622 SVGA3dCmdDestroyGBMob *pCmd = (SVGA3dCmdDestroyGBMob *)pvCmd;
4623 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4624 vmsvga3dCmdDestroyGBMob(pThisCC, pCmd);
4625 break;
4626 }
4627
4628 case SVGA_3D_CMD_DEAD3:
4629 {
4630 VMSVGA_3D_CMD_NOTIMPL();
4631 break;
4632 }
4633
4634 case SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING:
4635 {
4636 SVGA3dCmdUpdateGBMobMapping *pCmd = (SVGA3dCmdUpdateGBMobMapping *)pvCmd;
4637 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4638 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4639 break;
4640 }
4641
4642 case SVGA_3D_CMD_DEFINE_GB_SURFACE:
4643 {
4644 SVGA3dCmdDefineGBSurface *pCmd = (SVGA3dCmdDefineGBSurface *)pvCmd;
4645 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4646 vmsvga3dCmdDefineGBSurface(pThisCC, pCmd);
4647 break;
4648 }
4649
4650 case SVGA_3D_CMD_DESTROY_GB_SURFACE:
4651 {
4652 SVGA3dCmdDestroyGBSurface *pCmd = (SVGA3dCmdDestroyGBSurface *)pvCmd;
4653 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4654 vmsvga3dCmdDestroyGBSurface(pThisCC, pCmd);
4655 break;
4656 }
4657
4658 case SVGA_3D_CMD_BIND_GB_SURFACE:
4659 {
4660 SVGA3dCmdBindGBSurface *pCmd = (SVGA3dCmdBindGBSurface *)pvCmd;
4661 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4662 vmsvga3dCmdBindGBSurface(pThisCC, pCmd);
4663 break;
4664 }
4665
4666 case SVGA_3D_CMD_COND_BIND_GB_SURFACE:
4667 {
4668 SVGA3dCmdCondBindGBSurface *pCmd = (SVGA3dCmdCondBindGBSurface *)pvCmd;
4669 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4670 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4671 break;
4672 }
4673
4674 case SVGA_3D_CMD_UPDATE_GB_IMAGE:
4675 {
4676 SVGA3dCmdUpdateGBImage *pCmd = (SVGA3dCmdUpdateGBImage *)pvCmd;
4677 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4678 vmsvga3dCmdUpdateGBImage(pThisCC, pCmd);
4679 break;
4680 }
4681
4682 case SVGA_3D_CMD_UPDATE_GB_SURFACE:
4683 {
4684 SVGA3dCmdUpdateGBSurface *pCmd = (SVGA3dCmdUpdateGBSurface *)pvCmd;
4685 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4686 vmsvga3dCmdUpdateGBSurface(pThisCC, pCmd);
4687 break;
4688 }
4689
4690 case SVGA_3D_CMD_READBACK_GB_IMAGE:
4691 {
4692 SVGA3dCmdReadbackGBImage *pCmd = (SVGA3dCmdReadbackGBImage *)pvCmd;
4693 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4694 vmsvga3dCmdReadbackGBImage(pThisCC, pCmd);
4695 break;
4696 }
4697
4698 case SVGA_3D_CMD_READBACK_GB_SURFACE:
4699 {
4700 SVGA3dCmdReadbackGBSurface *pCmd = (SVGA3dCmdReadbackGBSurface *)pvCmd;
4701 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4702 vmsvga3dCmdReadbackGBSurface(pThisCC, pCmd);
4703 break;
4704 }
4705
4706 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE:
4707 {
4708 SVGA3dCmdInvalidateGBImage *pCmd = (SVGA3dCmdInvalidateGBImage *)pvCmd;
4709 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4710 vmsvga3dCmdInvalidateGBImage(pThisCC, pCmd);
4711 break;
4712 }
4713
4714 case SVGA_3D_CMD_INVALIDATE_GB_SURFACE:
4715 {
4716 SVGA3dCmdInvalidateGBSurface *pCmd = (SVGA3dCmdInvalidateGBSurface *)pvCmd;
4717 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4718 vmsvga3dCmdInvalidateGBSurface(pThisCC, pCmd);
4719 break;
4720 }
4721
4722 case SVGA_3D_CMD_DEFINE_GB_CONTEXT:
4723 {
4724 SVGA3dCmdDefineGBContext *pCmd = (SVGA3dCmdDefineGBContext *)pvCmd;
4725 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4726 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4727 break;
4728 }
4729
4730 case SVGA_3D_CMD_DESTROY_GB_CONTEXT:
4731 {
4732 SVGA3dCmdDestroyGBContext *pCmd = (SVGA3dCmdDestroyGBContext *)pvCmd;
4733 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4734 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4735 break;
4736 }
4737
4738 case SVGA_3D_CMD_BIND_GB_CONTEXT:
4739 {
4740 SVGA3dCmdBindGBContext *pCmd = (SVGA3dCmdBindGBContext *)pvCmd;
4741 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4742 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4743 break;
4744 }
4745
4746 case SVGA_3D_CMD_READBACK_GB_CONTEXT:
4747 {
4748 SVGA3dCmdReadbackGBContext *pCmd = (SVGA3dCmdReadbackGBContext *)pvCmd;
4749 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4750 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4751 break;
4752 }
4753
4754 case SVGA_3D_CMD_INVALIDATE_GB_CONTEXT:
4755 {
4756 SVGA3dCmdInvalidateGBContext *pCmd = (SVGA3dCmdInvalidateGBContext *)pvCmd;
4757 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4758 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4759 break;
4760 }
4761
4762 case SVGA_3D_CMD_DEFINE_GB_SHADER:
4763 {
4764 SVGA3dCmdDefineGBShader *pCmd = (SVGA3dCmdDefineGBShader *)pvCmd;
4765 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4766 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4767 break;
4768 }
4769
4770 case SVGA_3D_CMD_DESTROY_GB_SHADER:
4771 {
4772 SVGA3dCmdDestroyGBShader *pCmd = (SVGA3dCmdDestroyGBShader *)pvCmd;
4773 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4774 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4775 break;
4776 }
4777
4778 case SVGA_3D_CMD_BIND_GB_SHADER:
4779 {
4780 SVGA3dCmdBindGBShader *pCmd = (SVGA3dCmdBindGBShader *)pvCmd;
4781 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4782 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4783 break;
4784 }
4785
4786 case SVGA_3D_CMD_SET_OTABLE_BASE64:
4787 {
4788 SVGA3dCmdSetOTableBase64 *pCmd = (SVGA3dCmdSetOTableBase64 *)pvCmd;
4789 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4790 vmsvga3dCmdSetOTableBase64(pThisCC, pCmd);
4791 break;
4792 }
4793
4794 case SVGA_3D_CMD_BEGIN_GB_QUERY:
4795 {
4796 SVGA3dCmdBeginGBQuery *pCmd = (SVGA3dCmdBeginGBQuery *)pvCmd;
4797 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4798 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4799 break;
4800 }
4801
4802 case SVGA_3D_CMD_END_GB_QUERY:
4803 {
4804 SVGA3dCmdEndGBQuery *pCmd = (SVGA3dCmdEndGBQuery *)pvCmd;
4805 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4806 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4807 break;
4808 }
4809
4810 case SVGA_3D_CMD_WAIT_FOR_GB_QUERY:
4811 {
4812 SVGA3dCmdWaitForGBQuery *pCmd = (SVGA3dCmdWaitForGBQuery *)pvCmd;
4813 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4814 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4815 break;
4816 }
4817
4818 case SVGA_3D_CMD_NOP:
4819 {
4820 /* Apparently there is nothing to do. */
4821 break;
4822 }
4823
4824 case SVGA_3D_CMD_ENABLE_GART:
4825 {
4826 SVGA3dCmdEnableGart *pCmd = (SVGA3dCmdEnableGart *)pvCmd;
4827 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4828 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4829 break;
4830 }
4831
4832 case SVGA_3D_CMD_DISABLE_GART:
4833 {
4834 /* No corresponding SVGA3dCmd structure. */
4835 VMSVGA_3D_CMD_NOTIMPL();
4836 break;
4837 }
4838
4839 case SVGA_3D_CMD_MAP_MOB_INTO_GART:
4840 {
4841 SVGA3dCmdMapMobIntoGart *pCmd = (SVGA3dCmdMapMobIntoGart *)pvCmd;
4842 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4843 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4844 break;
4845 }
4846
4847 case SVGA_3D_CMD_UNMAP_GART_RANGE:
4848 {
4849 SVGA3dCmdUnmapGartRange *pCmd = (SVGA3dCmdUnmapGartRange *)pvCmd;
4850 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4851 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4852 break;
4853 }
4854
4855 case SVGA_3D_CMD_DEFINE_GB_SCREENTARGET:
4856 {
4857 SVGA3dCmdDefineGBScreenTarget *pCmd = (SVGA3dCmdDefineGBScreenTarget *)pvCmd;
4858 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4859 vmsvga3dCmdDefineGBScreenTarget(pThis, pThisCC, pCmd);
4860 break;
4861 }
4862
4863 case SVGA_3D_CMD_DESTROY_GB_SCREENTARGET:
4864 {
4865 SVGA3dCmdDestroyGBScreenTarget *pCmd = (SVGA3dCmdDestroyGBScreenTarget *)pvCmd;
4866 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4867 vmsvga3dCmdDestroyGBScreenTarget(pThis, pThisCC, pCmd);
4868 break;
4869 }
4870
4871 case SVGA_3D_CMD_BIND_GB_SCREENTARGET:
4872 {
4873 SVGA3dCmdBindGBScreenTarget *pCmd = (SVGA3dCmdBindGBScreenTarget *)pvCmd;
4874 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4875 vmsvga3dCmdBindGBScreenTarget(pThisCC, pCmd);
4876 break;
4877 }
4878
4879 case SVGA_3D_CMD_UPDATE_GB_SCREENTARGET:
4880 {
4881 SVGA3dCmdUpdateGBScreenTarget *pCmd = (SVGA3dCmdUpdateGBScreenTarget *)pvCmd;
4882 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4883 vmsvga3dCmdUpdateGBScreenTarget(pThisCC, pCmd);
4884 break;
4885 }
4886
4887 case SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL:
4888 {
4889 SVGA3dCmdReadbackGBImagePartial *pCmd = (SVGA3dCmdReadbackGBImagePartial *)pvCmd;
4890 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4891 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4892 break;
4893 }
4894
4895 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL:
4896 {
4897 SVGA3dCmdInvalidateGBImagePartial *pCmd = (SVGA3dCmdInvalidateGBImagePartial *)pvCmd;
4898 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4899 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4900 break;
4901 }
4902
4903 case SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE:
4904 {
4905 SVGA3dCmdSetGBShaderConstInline *pCmd = (SVGA3dCmdSetGBShaderConstInline *)pvCmd;
4906 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4907 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4908 break;
4909 }
4910
4911 case SVGA_3D_CMD_GB_SCREEN_DMA:
4912 {
4913 SVGA3dCmdGBScreenDMA *pCmd = (SVGA3dCmdGBScreenDMA *)pvCmd;
4914 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4915 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4916 break;
4917 }
4918
4919 case SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH:
4920 {
4921 SVGA3dCmdBindGBSurfaceWithPitch *pCmd = (SVGA3dCmdBindGBSurfaceWithPitch *)pvCmd;
4922 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4923 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4924 break;
4925 }
4926
4927 case SVGA_3D_CMD_GB_MOB_FENCE:
4928 {
4929 SVGA3dCmdGBMobFence *pCmd = (SVGA3dCmdGBMobFence *)pvCmd;
4930 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4931 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4932 break;
4933 }
4934
4935 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V2:
4936 {
4937 SVGA3dCmdDefineGBSurface_v2 *pCmd = (SVGA3dCmdDefineGBSurface_v2 *)pvCmd;
4938 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4939 vmsvga3dCmdDefineGBSurface_v2(pThisCC, pCmd);
4940 break;
4941 }
4942
4943 case SVGA_3D_CMD_DEFINE_GB_MOB64:
4944 {
4945 SVGA3dCmdDefineGBMob64 *pCmd = (SVGA3dCmdDefineGBMob64 *)pvCmd;
4946 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4947 vmsvga3dCmdDefineGBMob64(pThisCC, pCmd);
4948 break;
4949 }
4950
4951 case SVGA_3D_CMD_REDEFINE_GB_MOB64:
4952 {
4953 SVGA3dCmdRedefineGBMob64 *pCmd = (SVGA3dCmdRedefineGBMob64 *)pvCmd;
4954 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4955 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4956 break;
4957 }
4958
4959 case SVGA_3D_CMD_NOP_ERROR:
4960 {
4961 /* Apparently there is nothing to do. */
4962 break;
4963 }
4964
4965 case SVGA_3D_CMD_SET_VERTEX_STREAMS:
4966 {
4967 SVGA3dCmdSetVertexStreams *pCmd = (SVGA3dCmdSetVertexStreams *)pvCmd;
4968 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4969 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4970 break;
4971 }
4972
4973 case SVGA_3D_CMD_SET_VERTEX_DECLS:
4974 {
4975 SVGA3dCmdSetVertexDecls *pCmd = (SVGA3dCmdSetVertexDecls *)pvCmd;
4976 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4977 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4978 break;
4979 }
4980
4981 case SVGA_3D_CMD_SET_VERTEX_DIVISORS:
4982 {
4983 SVGA3dCmdSetVertexDivisors *pCmd = (SVGA3dCmdSetVertexDivisors *)pvCmd;
4984 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4985 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4986 break;
4987 }
4988
4989 case SVGA_3D_CMD_DRAW:
4990 {
4991 /* No corresponding SVGA3dCmd structure. */
4992 VMSVGA_3D_CMD_NOTIMPL();
4993 break;
4994 }
4995
4996 case SVGA_3D_CMD_DRAW_INDEXED:
4997 {
4998 /* No corresponding SVGA3dCmd structure. */
4999 VMSVGA_3D_CMD_NOTIMPL();
5000 break;
5001 }
5002
5003 case SVGA_3D_CMD_DX_DEFINE_CONTEXT:
5004 {
5005 SVGA3dCmdDXDefineContext *pCmd = (SVGA3dCmdDXDefineContext *)pvCmd;
5006 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5007 rcParse = vmsvga3dCmdDXDefineContext(pThisCC, pCmd, cbCmd);
5008 break;
5009 }
5010
5011 case SVGA_3D_CMD_DX_DESTROY_CONTEXT:
5012 {
5013 SVGA3dCmdDXDestroyContext *pCmd = (SVGA3dCmdDXDestroyContext *)pvCmd;
5014 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5015 rcParse = vmsvga3dCmdDXDestroyContext(pThisCC, pCmd, cbCmd);
5016 break;
5017 }
5018
5019 case SVGA_3D_CMD_DX_BIND_CONTEXT:
5020 {
5021 SVGA3dCmdDXBindContext *pCmd = (SVGA3dCmdDXBindContext *)pvCmd;
5022 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5023 rcParse = vmsvga3dCmdDXBindContext(pThisCC, pCmd, cbCmd);
5024 break;
5025 }
5026
5027 case SVGA_3D_CMD_DX_READBACK_CONTEXT:
5028 {
5029 SVGA3dCmdDXReadbackContext *pCmd = (SVGA3dCmdDXReadbackContext *)pvCmd;
5030 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5031 rcParse = vmsvga3dCmdDXReadbackContext(pThisCC, pCmd, cbCmd);
5032 break;
5033 }
5034
5035 case SVGA_3D_CMD_DX_INVALIDATE_CONTEXT:
5036 {
5037 SVGA3dCmdDXInvalidateContext *pCmd = (SVGA3dCmdDXInvalidateContext *)pvCmd;
5038 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5039 rcParse = vmsvga3dCmdDXInvalidateContext(pThisCC, idDXContext, pCmd, cbCmd);
5040 break;
5041 }
5042
5043 case SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER:
5044 {
5045 SVGA3dCmdDXSetSingleConstantBuffer *pCmd = (SVGA3dCmdDXSetSingleConstantBuffer *)pvCmd;
5046 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5047 rcParse = vmsvga3dCmdDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5048 break;
5049 }
5050
5051 case SVGA_3D_CMD_DX_SET_SHADER_RESOURCES:
5052 {
5053 SVGA3dCmdDXSetShaderResources *pCmd = (SVGA3dCmdDXSetShaderResources *)pvCmd;
5054 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5055 rcParse = vmsvga3dCmdDXSetShaderResources(pThisCC, idDXContext, pCmd, cbCmd);
5056 break;
5057 }
5058
5059 case SVGA_3D_CMD_DX_SET_SHADER:
5060 {
5061 SVGA3dCmdDXSetShader *pCmd = (SVGA3dCmdDXSetShader *)pvCmd;
5062 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5063 rcParse = vmsvga3dCmdDXSetShader(pThisCC, idDXContext, pCmd, cbCmd);
5064 break;
5065 }
5066
5067 case SVGA_3D_CMD_DX_SET_SAMPLERS:
5068 {
5069 SVGA3dCmdDXSetSamplers *pCmd = (SVGA3dCmdDXSetSamplers *)pvCmd;
5070 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5071 rcParse = vmsvga3dCmdDXSetSamplers(pThisCC, idDXContext, pCmd, cbCmd);
5072 break;
5073 }
5074
5075 case SVGA_3D_CMD_DX_DRAW:
5076 {
5077 SVGA3dCmdDXDraw *pCmd = (SVGA3dCmdDXDraw *)pvCmd;
5078 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5079 rcParse = vmsvga3dCmdDXDraw(pThisCC, idDXContext, pCmd, cbCmd);
5080 break;
5081 }
5082
5083 case SVGA_3D_CMD_DX_DRAW_INDEXED:
5084 {
5085 SVGA3dCmdDXDrawIndexed *pCmd = (SVGA3dCmdDXDrawIndexed *)pvCmd;
5086 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5087 rcParse = vmsvga3dCmdDXDrawIndexed(pThisCC, idDXContext, pCmd, cbCmd);
5088 break;
5089 }
5090
5091 case SVGA_3D_CMD_DX_DRAW_INSTANCED:
5092 {
5093 SVGA3dCmdDXDrawInstanced *pCmd = (SVGA3dCmdDXDrawInstanced *)pvCmd;
5094 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5095 rcParse = vmsvga3dCmdDXDrawInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5096 break;
5097 }
5098
5099 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED:
5100 {
5101 SVGA3dCmdDXDrawIndexedInstanced *pCmd = (SVGA3dCmdDXDrawIndexedInstanced *)pvCmd;
5102 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5103 rcParse = vmsvga3dCmdDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5104 break;
5105 }
5106
5107 case SVGA_3D_CMD_DX_DRAW_AUTO:
5108 {
5109 SVGA3dCmdDXDrawAuto *pCmd = (SVGA3dCmdDXDrawAuto *)pvCmd;
5110 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5111 rcParse = vmsvga3dCmdDXDrawAuto(pThisCC, idDXContext, pCmd, cbCmd);
5112 break;
5113 }
5114
5115 case SVGA_3D_CMD_DX_SET_INPUT_LAYOUT:
5116 {
5117 SVGA3dCmdDXSetInputLayout *pCmd = (SVGA3dCmdDXSetInputLayout *)pvCmd;
5118 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5119 rcParse = vmsvga3dCmdDXSetInputLayout(pThisCC, idDXContext, pCmd, cbCmd);
5120 break;
5121 }
5122
5123 case SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS:
5124 {
5125 SVGA3dCmdDXSetVertexBuffers *pCmd = (SVGA3dCmdDXSetVertexBuffers *)pvCmd;
5126 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5127 rcParse = vmsvga3dCmdDXSetVertexBuffers(pThisCC, idDXContext, pCmd, cbCmd);
5128 break;
5129 }
5130
5131 case SVGA_3D_CMD_DX_SET_INDEX_BUFFER:
5132 {
5133 SVGA3dCmdDXSetIndexBuffer *pCmd = (SVGA3dCmdDXSetIndexBuffer *)pvCmd;
5134 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5135 rcParse = vmsvga3dCmdDXSetIndexBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5136 break;
5137 }
5138
5139 case SVGA_3D_CMD_DX_SET_TOPOLOGY:
5140 {
5141 SVGA3dCmdDXSetTopology *pCmd = (SVGA3dCmdDXSetTopology *)pvCmd;
5142 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5143 rcParse = vmsvga3dCmdDXSetTopology(pThisCC, idDXContext, pCmd, cbCmd);
5144 break;
5145 }
5146
5147 case SVGA_3D_CMD_DX_SET_RENDERTARGETS:
5148 {
5149 SVGA3dCmdDXSetRenderTargets *pCmd = (SVGA3dCmdDXSetRenderTargets *)pvCmd;
5150 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5151 rcParse = vmsvga3dCmdDXSetRenderTargets(pThisCC, idDXContext, pCmd, cbCmd);
5152 break;
5153 }
5154
5155 case SVGA_3D_CMD_DX_SET_BLEND_STATE:
5156 {
5157 SVGA3dCmdDXSetBlendState *pCmd = (SVGA3dCmdDXSetBlendState *)pvCmd;
5158 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5159 rcParse = vmsvga3dCmdDXSetBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5160 break;
5161 }
5162
5163 case SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE:
5164 {
5165 SVGA3dCmdDXSetDepthStencilState *pCmd = (SVGA3dCmdDXSetDepthStencilState *)pvCmd;
5166 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5167 rcParse = vmsvga3dCmdDXSetDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5168 break;
5169 }
5170
5171 case SVGA_3D_CMD_DX_SET_RASTERIZER_STATE:
5172 {
5173 SVGA3dCmdDXSetRasterizerState *pCmd = (SVGA3dCmdDXSetRasterizerState *)pvCmd;
5174 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5175 rcParse = vmsvga3dCmdDXSetRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5176 break;
5177 }
5178
5179 case SVGA_3D_CMD_DX_DEFINE_QUERY:
5180 {
5181 SVGA3dCmdDXDefineQuery *pCmd = (SVGA3dCmdDXDefineQuery *)pvCmd;
5182 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5183 rcParse = vmsvga3dCmdDXDefineQuery(pThisCC, idDXContext, pCmd, cbCmd);
5184 break;
5185 }
5186
5187 case SVGA_3D_CMD_DX_DESTROY_QUERY:
5188 {
5189 SVGA3dCmdDXDestroyQuery *pCmd = (SVGA3dCmdDXDestroyQuery *)pvCmd;
5190 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5191 rcParse = vmsvga3dCmdDXDestroyQuery(pThisCC, idDXContext, pCmd, cbCmd);
5192 break;
5193 }
5194
5195 case SVGA_3D_CMD_DX_BIND_QUERY:
5196 {
5197 SVGA3dCmdDXBindQuery *pCmd = (SVGA3dCmdDXBindQuery *)pvCmd;
5198 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5199 rcParse = vmsvga3dCmdDXBindQuery(pThisCC, idDXContext, pCmd, cbCmd);
5200 break;
5201 }
5202
5203 case SVGA_3D_CMD_DX_SET_QUERY_OFFSET:
5204 {
5205 SVGA3dCmdDXSetQueryOffset *pCmd = (SVGA3dCmdDXSetQueryOffset *)pvCmd;
5206 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5207 rcParse = vmsvga3dCmdDXSetQueryOffset(pThisCC, idDXContext, pCmd, cbCmd);
5208 break;
5209 }
5210
5211 case SVGA_3D_CMD_DX_BEGIN_QUERY:
5212 {
5213 SVGA3dCmdDXBeginQuery *pCmd = (SVGA3dCmdDXBeginQuery *)pvCmd;
5214 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5215 rcParse = vmsvga3dCmdDXBeginQuery(pThisCC, idDXContext, pCmd, cbCmd);
5216 break;
5217 }
5218
5219 case SVGA_3D_CMD_DX_END_QUERY:
5220 {
5221 SVGA3dCmdDXEndQuery *pCmd = (SVGA3dCmdDXEndQuery *)pvCmd;
5222 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5223 rcParse = vmsvga3dCmdDXEndQuery(pThisCC, idDXContext, pCmd, cbCmd);
5224 break;
5225 }
5226
5227 case SVGA_3D_CMD_DX_READBACK_QUERY:
5228 {
5229 SVGA3dCmdDXReadbackQuery *pCmd = (SVGA3dCmdDXReadbackQuery *)pvCmd;
5230 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5231 rcParse = vmsvga3dCmdDXReadbackQuery(pThisCC, idDXContext, pCmd, cbCmd);
5232 break;
5233 }
5234
5235 case SVGA_3D_CMD_DX_SET_PREDICATION:
5236 {
5237 SVGA3dCmdDXSetPredication *pCmd = (SVGA3dCmdDXSetPredication *)pvCmd;
5238 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5239 rcParse = vmsvga3dCmdDXSetPredication(pThisCC, idDXContext, pCmd, cbCmd);
5240 break;
5241 }
5242
5243 case SVGA_3D_CMD_DX_SET_SOTARGETS:
5244 {
5245 SVGA3dCmdDXSetSOTargets *pCmd = (SVGA3dCmdDXSetSOTargets *)pvCmd;
5246 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5247 rcParse = vmsvga3dCmdDXSetSOTargets(pThisCC, idDXContext, pCmd, cbCmd);
5248 break;
5249 }
5250
5251 case SVGA_3D_CMD_DX_SET_VIEWPORTS:
5252 {
5253 SVGA3dCmdDXSetViewports *pCmd = (SVGA3dCmdDXSetViewports *)pvCmd;
5254 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5255 rcParse = vmsvga3dCmdDXSetViewports(pThisCC, idDXContext, pCmd, cbCmd);
5256 break;
5257 }
5258
5259 case SVGA_3D_CMD_DX_SET_SCISSORRECTS:
5260 {
5261 SVGA3dCmdDXSetScissorRects *pCmd = (SVGA3dCmdDXSetScissorRects *)pvCmd;
5262 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5263 rcParse = vmsvga3dCmdDXSetScissorRects(pThisCC, idDXContext, pCmd, cbCmd);
5264 break;
5265 }
5266
5267 case SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW:
5268 {
5269 SVGA3dCmdDXClearRenderTargetView *pCmd = (SVGA3dCmdDXClearRenderTargetView *)pvCmd;
5270 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5271 rcParse = vmsvga3dCmdDXClearRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5272 break;
5273 }
5274
5275 case SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW:
5276 {
5277 SVGA3dCmdDXClearDepthStencilView *pCmd = (SVGA3dCmdDXClearDepthStencilView *)pvCmd;
5278 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5279 rcParse = vmsvga3dCmdDXClearDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5280 break;
5281 }
5282
5283 case SVGA_3D_CMD_DX_PRED_COPY_REGION:
5284 {
5285 SVGA3dCmdDXPredCopyRegion *pCmd = (SVGA3dCmdDXPredCopyRegion *)pvCmd;
5286 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5287 rcParse = vmsvga3dCmdDXPredCopyRegion(pThisCC, idDXContext, pCmd, cbCmd);
5288 break;
5289 }
5290
5291 case SVGA_3D_CMD_DX_PRED_COPY:
5292 {
5293 SVGA3dCmdDXPredCopy *pCmd = (SVGA3dCmdDXPredCopy *)pvCmd;
5294 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5295 rcParse = vmsvga3dCmdDXPredCopy(pThisCC, idDXContext, pCmd, cbCmd);
5296 break;
5297 }
5298
5299 case SVGA_3D_CMD_DX_PRESENTBLT:
5300 {
5301 SVGA3dCmdDXPresentBlt *pCmd = (SVGA3dCmdDXPresentBlt *)pvCmd;
5302 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5303 rcParse = vmsvga3dCmdDXPresentBlt(pThisCC, idDXContext, pCmd, cbCmd);
5304 break;
5305 }
5306
5307 case SVGA_3D_CMD_DX_GENMIPS:
5308 {
5309 SVGA3dCmdDXGenMips *pCmd = (SVGA3dCmdDXGenMips *)pvCmd;
5310 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5311 rcParse = vmsvga3dCmdDXGenMips(pThisCC, idDXContext, pCmd, cbCmd);
5312 break;
5313 }
5314
5315 case SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE:
5316 {
5317 SVGA3dCmdDXUpdateSubResource *pCmd = (SVGA3dCmdDXUpdateSubResource *)pvCmd;
5318 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5319 rcParse = vmsvga3dCmdDXUpdateSubResource(pThisCC, pCmd, cbCmd);
5320 break;
5321 }
5322
5323 case SVGA_3D_CMD_DX_READBACK_SUBRESOURCE:
5324 {
5325 SVGA3dCmdDXReadbackSubResource *pCmd = (SVGA3dCmdDXReadbackSubResource *)pvCmd;
5326 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5327 rcParse = vmsvga3dCmdDXReadbackSubResource(pThisCC, pCmd, cbCmd);
5328 break;
5329 }
5330
5331 case SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE:
5332 {
5333 SVGA3dCmdDXInvalidateSubResource *pCmd = (SVGA3dCmdDXInvalidateSubResource *)pvCmd;
5334 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5335 rcParse = vmsvga3dCmdDXInvalidateSubResource(pThisCC, pCmd, cbCmd);
5336 break;
5337 }
5338
5339 case SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW:
5340 {
5341 SVGA3dCmdDXDefineShaderResourceView *pCmd = (SVGA3dCmdDXDefineShaderResourceView *)pvCmd;
5342 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5343 rcParse = vmsvga3dCmdDXDefineShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5344 break;
5345 }
5346
5347 case SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW:
5348 {
5349 SVGA3dCmdDXDestroyShaderResourceView *pCmd = (SVGA3dCmdDXDestroyShaderResourceView *)pvCmd;
5350 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5351 rcParse = vmsvga3dCmdDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5352 break;
5353 }
5354
5355 case SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW:
5356 {
5357 SVGA3dCmdDXDefineRenderTargetView *pCmd = (SVGA3dCmdDXDefineRenderTargetView *)pvCmd;
5358 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5359 rcParse = vmsvga3dCmdDXDefineRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5360 break;
5361 }
5362
5363 case SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW:
5364 {
5365 SVGA3dCmdDXDestroyRenderTargetView *pCmd = (SVGA3dCmdDXDestroyRenderTargetView *)pvCmd;
5366 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5367 rcParse = vmsvga3dCmdDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5368 break;
5369 }
5370
5371 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW:
5372 {
5373 SVGA3dCmdDXDefineDepthStencilView *pCmd = (SVGA3dCmdDXDefineDepthStencilView *)pvCmd;
5374 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5375 rcParse = vmsvga3dCmdDXDefineDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5376 break;
5377 }
5378
5379 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW:
5380 {
5381 SVGA3dCmdDXDestroyDepthStencilView *pCmd = (SVGA3dCmdDXDestroyDepthStencilView *)pvCmd;
5382 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5383 rcParse = vmsvga3dCmdDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5384 break;
5385 }
5386
5387 case SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT:
5388 {
5389 SVGA3dCmdDXDefineElementLayout *pCmd = (SVGA3dCmdDXDefineElementLayout *)pvCmd;
5390 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5391 rcParse = vmsvga3dCmdDXDefineElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5392 break;
5393 }
5394
5395 case SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT:
5396 {
5397 SVGA3dCmdDXDestroyElementLayout *pCmd = (SVGA3dCmdDXDestroyElementLayout *)pvCmd;
5398 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5399 rcParse = vmsvga3dCmdDXDestroyElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5400 break;
5401 }
5402
5403 case SVGA_3D_CMD_DX_DEFINE_BLEND_STATE:
5404 {
5405 SVGA3dCmdDXDefineBlendState *pCmd = (SVGA3dCmdDXDefineBlendState *)pvCmd;
5406 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5407 rcParse = vmsvga3dCmdDXDefineBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5408 break;
5409 }
5410
5411 case SVGA_3D_CMD_DX_DESTROY_BLEND_STATE:
5412 {
5413 SVGA3dCmdDXDestroyBlendState *pCmd = (SVGA3dCmdDXDestroyBlendState *)pvCmd;
5414 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5415 rcParse = vmsvga3dCmdDXDestroyBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5416 break;
5417 }
5418
5419 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE:
5420 {
5421 SVGA3dCmdDXDefineDepthStencilState *pCmd = (SVGA3dCmdDXDefineDepthStencilState *)pvCmd;
5422 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5423 rcParse = vmsvga3dCmdDXDefineDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5424 break;
5425 }
5426
5427 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE:
5428 {
5429 SVGA3dCmdDXDestroyDepthStencilState *pCmd = (SVGA3dCmdDXDestroyDepthStencilState *)pvCmd;
5430 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5431 rcParse = vmsvga3dCmdDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5432 break;
5433 }
5434
5435 case SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE:
5436 {
5437 SVGA3dCmdDXDefineRasterizerState *pCmd = (SVGA3dCmdDXDefineRasterizerState *)pvCmd;
5438 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5439 rcParse = vmsvga3dCmdDXDefineRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5440 break;
5441 }
5442
5443 case SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE:
5444 {
5445 SVGA3dCmdDXDestroyRasterizerState *pCmd = (SVGA3dCmdDXDestroyRasterizerState *)pvCmd;
5446 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5447 rcParse = vmsvga3dCmdDXDestroyRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5448 break;
5449 }
5450
5451 case SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE:
5452 {
5453 SVGA3dCmdDXDefineSamplerState *pCmd = (SVGA3dCmdDXDefineSamplerState *)pvCmd;
5454 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5455 rcParse = vmsvga3dCmdDXDefineSamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5456 break;
5457 }
5458
5459 case SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE:
5460 {
5461 SVGA3dCmdDXDestroySamplerState *pCmd = (SVGA3dCmdDXDestroySamplerState *)pvCmd;
5462 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5463 rcParse = vmsvga3dCmdDXDestroySamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5464 break;
5465 }
5466
5467 case SVGA_3D_CMD_DX_DEFINE_SHADER:
5468 {
5469 SVGA3dCmdDXDefineShader *pCmd = (SVGA3dCmdDXDefineShader *)pvCmd;
5470 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5471 rcParse = vmsvga3dCmdDXDefineShader(pThisCC, idDXContext, pCmd, cbCmd);
5472 break;
5473 }
5474
5475 case SVGA_3D_CMD_DX_DESTROY_SHADER:
5476 {
5477 SVGA3dCmdDXDestroyShader *pCmd = (SVGA3dCmdDXDestroyShader *)pvCmd;
5478 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5479 rcParse = vmsvga3dCmdDXDestroyShader(pThisCC, idDXContext, pCmd, cbCmd);
5480 break;
5481 }
5482
5483 case SVGA_3D_CMD_DX_BIND_SHADER:
5484 {
5485 SVGA3dCmdDXBindShader *pCmd = (SVGA3dCmdDXBindShader *)pvCmd;
5486 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5487 rcParse = vmsvga3dCmdDXBindShader(pThisCC, idDXContext, pCmd, cbCmd);
5488 break;
5489 }
5490
5491 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT:
5492 {
5493 SVGA3dCmdDXDefineStreamOutput *pCmd = (SVGA3dCmdDXDefineStreamOutput *)pvCmd;
5494 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5495 rcParse = vmsvga3dCmdDXDefineStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5496 break;
5497 }
5498
5499 case SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT:
5500 {
5501 SVGA3dCmdDXDestroyStreamOutput *pCmd = (SVGA3dCmdDXDestroyStreamOutput *)pvCmd;
5502 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5503 rcParse = vmsvga3dCmdDXDestroyStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5504 break;
5505 }
5506
5507 case SVGA_3D_CMD_DX_SET_STREAMOUTPUT:
5508 {
5509 SVGA3dCmdDXSetStreamOutput *pCmd = (SVGA3dCmdDXSetStreamOutput *)pvCmd;
5510 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5511 rcParse = vmsvga3dCmdDXSetStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5512 break;
5513 }
5514
5515 case SVGA_3D_CMD_DX_SET_COTABLE:
5516 {
5517 SVGA3dCmdDXSetCOTable *pCmd = (SVGA3dCmdDXSetCOTable *)pvCmd;
5518 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5519 rcParse = vmsvga3dCmdDXSetCOTable(pThisCC, pCmd, cbCmd);
5520 break;
5521 }
5522
5523 case SVGA_3D_CMD_DX_READBACK_COTABLE:
5524 {
5525 SVGA3dCmdDXReadbackCOTable *pCmd = (SVGA3dCmdDXReadbackCOTable *)pvCmd;
5526 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5527 rcParse = vmsvga3dCmdDXReadbackCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5528 break;
5529 }
5530
5531 case SVGA_3D_CMD_DX_BUFFER_COPY:
5532 {
5533 SVGA3dCmdDXBufferCopy *pCmd = (SVGA3dCmdDXBufferCopy *)pvCmd;
5534 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5535 rcParse = vmsvga3dCmdDXBufferCopy(pThisCC, idDXContext, pCmd, cbCmd);
5536 break;
5537 }
5538
5539 case SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER:
5540 {
5541 SVGA3dCmdDXTransferFromBuffer *pCmd = (SVGA3dCmdDXTransferFromBuffer *)pvCmd;
5542 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5543 rcParse = vmsvga3dCmdDXTransferFromBuffer(pThisCC, pCmd, cbCmd);
5544 break;
5545 }
5546
5547 case SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK:
5548 {
5549 SVGA3dCmdDXSurfaceCopyAndReadback *pCmd = (SVGA3dCmdDXSurfaceCopyAndReadback *)pvCmd;
5550 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5551 rcParse = vmsvga3dCmdDXSurfaceCopyAndReadback(pThisCC, idDXContext, pCmd, cbCmd);
5552 break;
5553 }
5554
5555 case SVGA_3D_CMD_DX_MOVE_QUERY:
5556 {
5557 SVGA3dCmdDXMoveQuery *pCmd = (SVGA3dCmdDXMoveQuery *)pvCmd;
5558 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5559 rcParse = vmsvga3dCmdDXMoveQuery(pThisCC, idDXContext, pCmd, cbCmd);
5560 break;
5561 }
5562
5563 case SVGA_3D_CMD_DX_BIND_ALL_QUERY:
5564 {
5565 SVGA3dCmdDXBindAllQuery *pCmd = (SVGA3dCmdDXBindAllQuery *)pvCmd;
5566 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5567 rcParse = vmsvga3dCmdDXBindAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5568 break;
5569 }
5570
5571 case SVGA_3D_CMD_DX_READBACK_ALL_QUERY:
5572 {
5573 SVGA3dCmdDXReadbackAllQuery *pCmd = (SVGA3dCmdDXReadbackAllQuery *)pvCmd;
5574 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5575 rcParse = vmsvga3dCmdDXReadbackAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5576 break;
5577 }
5578
5579 case SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER:
5580 {
5581 SVGA3dCmdDXPredTransferFromBuffer *pCmd = (SVGA3dCmdDXPredTransferFromBuffer *)pvCmd;
5582 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5583 rcParse = vmsvga3dCmdDXPredTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5584 break;
5585 }
5586
5587 case SVGA_3D_CMD_DX_MOB_FENCE_64:
5588 {
5589 SVGA3dCmdDXMobFence64 *pCmd = (SVGA3dCmdDXMobFence64 *)pvCmd;
5590 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5591 rcParse = vmsvga3dCmdDXMobFence64(pThisCC, idDXContext, pCmd, cbCmd);
5592 break;
5593 }
5594
5595 case SVGA_3D_CMD_DX_BIND_ALL_SHADER:
5596 {
5597 SVGA3dCmdDXBindAllShader *pCmd = (SVGA3dCmdDXBindAllShader *)pvCmd;
5598 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5599 rcParse = vmsvga3dCmdDXBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5600 break;
5601 }
5602
5603 case SVGA_3D_CMD_DX_HINT:
5604 {
5605 SVGA3dCmdDXHint *pCmd = (SVGA3dCmdDXHint *)pvCmd;
5606 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5607 rcParse = vmsvga3dCmdDXHint(pThisCC, idDXContext, pCmd, cbCmd);
5608 break;
5609 }
5610
5611 case SVGA_3D_CMD_DX_BUFFER_UPDATE:
5612 {
5613 SVGA3dCmdDXBufferUpdate *pCmd = (SVGA3dCmdDXBufferUpdate *)pvCmd;
5614 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5615 rcParse = vmsvga3dCmdDXBufferUpdate(pThisCC, idDXContext, pCmd, cbCmd);
5616 break;
5617 }
5618
5619 case SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET:
5620 {
5621 SVGA3dCmdDXSetVSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetVSConstantBufferOffset *)pvCmd;
5622 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5623 rcParse = vmsvga3dCmdDXSetVSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5624 break;
5625 }
5626
5627 case SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET:
5628 {
5629 SVGA3dCmdDXSetPSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetPSConstantBufferOffset *)pvCmd;
5630 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5631 rcParse = vmsvga3dCmdDXSetPSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5632 break;
5633 }
5634
5635 case SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET:
5636 {
5637 SVGA3dCmdDXSetGSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetGSConstantBufferOffset *)pvCmd;
5638 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5639 rcParse = vmsvga3dCmdDXSetGSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5640 break;
5641 }
5642
5643 case SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET:
5644 {
5645 SVGA3dCmdDXSetHSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetHSConstantBufferOffset *)pvCmd;
5646 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5647 rcParse = vmsvga3dCmdDXSetHSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5648 break;
5649 }
5650
5651 case SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET:
5652 {
5653 SVGA3dCmdDXSetDSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetDSConstantBufferOffset *)pvCmd;
5654 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5655 rcParse = vmsvga3dCmdDXSetDSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5656 break;
5657 }
5658
5659 case SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET:
5660 {
5661 SVGA3dCmdDXSetCSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetCSConstantBufferOffset *)pvCmd;
5662 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5663 rcParse = vmsvga3dCmdDXSetCSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5664 break;
5665 }
5666
5667 case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER:
5668 {
5669 SVGA3dCmdDXCondBindAllShader *pCmd = (SVGA3dCmdDXCondBindAllShader *)pvCmd;
5670 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5671 rcParse = vmsvga3dCmdDXCondBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5672 break;
5673 }
5674
5675 case SVGA_3D_CMD_SCREEN_COPY:
5676 {
5677 SVGA3dCmdScreenCopy *pCmd = (SVGA3dCmdScreenCopy *)pvCmd;
5678 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5679 rcParse = vmsvga3dCmdScreenCopy(pThisCC, idDXContext, pCmd, cbCmd);
5680 break;
5681 }
5682
5683 case SVGA_3D_CMD_RESERVED1:
5684 {
5685 VMSVGA_3D_CMD_NOTIMPL();
5686 break;
5687 }
5688
5689 case SVGA_3D_CMD_RESERVED2:
5690 {
5691 VMSVGA_3D_CMD_NOTIMPL();
5692 break;
5693 }
5694
5695 case SVGA_3D_CMD_RESERVED3:
5696 {
5697 VMSVGA_3D_CMD_NOTIMPL();
5698 break;
5699 }
5700
5701 case SVGA_3D_CMD_RESERVED4:
5702 {
5703 VMSVGA_3D_CMD_NOTIMPL();
5704 break;
5705 }
5706
5707 case SVGA_3D_CMD_RESERVED5:
5708 {
5709 VMSVGA_3D_CMD_NOTIMPL();
5710 break;
5711 }
5712
5713 case SVGA_3D_CMD_RESERVED6:
5714 {
5715 VMSVGA_3D_CMD_NOTIMPL();
5716 break;
5717 }
5718
5719 case SVGA_3D_CMD_RESERVED7:
5720 {
5721 VMSVGA_3D_CMD_NOTIMPL();
5722 break;
5723 }
5724
5725 case SVGA_3D_CMD_RESERVED8:
5726 {
5727 VMSVGA_3D_CMD_NOTIMPL();
5728 break;
5729 }
5730
5731 case SVGA_3D_CMD_GROW_OTABLE:
5732 {
5733 SVGA3dCmdGrowOTable *pCmd = (SVGA3dCmdGrowOTable *)pvCmd;
5734 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5735 rcParse = vmsvga3dCmdGrowOTable(pThisCC, idDXContext, pCmd, cbCmd);
5736 break;
5737 }
5738
5739 case SVGA_3D_CMD_DX_GROW_COTABLE:
5740 {
5741 SVGA3dCmdDXGrowCOTable *pCmd = (SVGA3dCmdDXGrowCOTable *)pvCmd;
5742 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5743 rcParse = vmsvga3dCmdDXGrowCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5744 break;
5745 }
5746
5747 case SVGA_3D_CMD_INTRA_SURFACE_COPY:
5748 {
5749 SVGA3dCmdIntraSurfaceCopy *pCmd = (SVGA3dCmdIntraSurfaceCopy *)pvCmd;
5750 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5751 rcParse = vmsvga3dCmdIntraSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5752 break;
5753 }
5754
5755 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V3:
5756 {
5757 SVGA3dCmdDefineGBSurface_v3 *pCmd = (SVGA3dCmdDefineGBSurface_v3 *)pvCmd;
5758 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5759 rcParse = vmsvga3dCmdDefineGBSurface_v3(pThisCC, idDXContext, pCmd, cbCmd);
5760 break;
5761 }
5762
5763 case SVGA_3D_CMD_DX_RESOLVE_COPY:
5764 {
5765 SVGA3dCmdDXResolveCopy *pCmd = (SVGA3dCmdDXResolveCopy *)pvCmd;
5766 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5767 rcParse = vmsvga3dCmdDXResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5768 break;
5769 }
5770
5771 case SVGA_3D_CMD_DX_PRED_RESOLVE_COPY:
5772 {
5773 SVGA3dCmdDXPredResolveCopy *pCmd = (SVGA3dCmdDXPredResolveCopy *)pvCmd;
5774 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5775 rcParse = vmsvga3dCmdDXPredResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5776 break;
5777 }
5778
5779 case SVGA_3D_CMD_DX_PRED_CONVERT_REGION:
5780 {
5781 SVGA3dCmdDXPredConvertRegion *pCmd = (SVGA3dCmdDXPredConvertRegion *)pvCmd;
5782 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5783 rcParse = vmsvga3dCmdDXPredConvertRegion(pThisCC, idDXContext, pCmd, cbCmd);
5784 break;
5785 }
5786
5787 case SVGA_3D_CMD_DX_PRED_CONVERT:
5788 {
5789 SVGA3dCmdDXPredConvert *pCmd = (SVGA3dCmdDXPredConvert *)pvCmd;
5790 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5791 rcParse = vmsvga3dCmdDXPredConvert(pThisCC, idDXContext, pCmd, cbCmd);
5792 break;
5793 }
5794
5795 case SVGA_3D_CMD_WHOLE_SURFACE_COPY:
5796 {
5797 SVGA3dCmdWholeSurfaceCopy *pCmd = (SVGA3dCmdWholeSurfaceCopy *)pvCmd;
5798 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5799 rcParse = vmsvga3dCmdWholeSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5800 break;
5801 }
5802
5803 case SVGA_3D_CMD_DX_DEFINE_UA_VIEW:
5804 {
5805 SVGA3dCmdDXDefineUAView *pCmd = (SVGA3dCmdDXDefineUAView *)pvCmd;
5806 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5807 rcParse = vmsvga3dCmdDXDefineUAView(pThisCC, idDXContext, pCmd, cbCmd);
5808 break;
5809 }
5810
5811 case SVGA_3D_CMD_DX_DESTROY_UA_VIEW:
5812 {
5813 SVGA3dCmdDXDestroyUAView *pCmd = (SVGA3dCmdDXDestroyUAView *)pvCmd;
5814 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5815 rcParse = vmsvga3dCmdDXDestroyUAView(pThisCC, idDXContext, pCmd, cbCmd);
5816 break;
5817 }
5818
5819 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT:
5820 {
5821 SVGA3dCmdDXClearUAViewUint *pCmd = (SVGA3dCmdDXClearUAViewUint *)pvCmd;
5822 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5823 rcParse = vmsvga3dCmdDXClearUAViewUint(pThisCC, idDXContext, pCmd, cbCmd);
5824 break;
5825 }
5826
5827 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT:
5828 {
5829 SVGA3dCmdDXClearUAViewFloat *pCmd = (SVGA3dCmdDXClearUAViewFloat *)pvCmd;
5830 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5831 rcParse = vmsvga3dCmdDXClearUAViewFloat(pThisCC, idDXContext, pCmd, cbCmd);
5832 break;
5833 }
5834
5835 case SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT:
5836 {
5837 SVGA3dCmdDXCopyStructureCount *pCmd = (SVGA3dCmdDXCopyStructureCount *)pvCmd;
5838 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5839 rcParse = vmsvga3dCmdDXCopyStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5840 break;
5841 }
5842
5843 case SVGA_3D_CMD_DX_SET_UA_VIEWS:
5844 {
5845 SVGA3dCmdDXSetUAViews *pCmd = (SVGA3dCmdDXSetUAViews *)pvCmd;
5846 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5847 rcParse = vmsvga3dCmdDXSetUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5848 break;
5849 }
5850
5851 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT:
5852 {
5853 SVGA3dCmdDXDrawIndexedInstancedIndirect *pCmd = (SVGA3dCmdDXDrawIndexedInstancedIndirect *)pvCmd;
5854 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5855 rcParse = vmsvga3dCmdDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5856 break;
5857 }
5858
5859 case SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT:
5860 {
5861 SVGA3dCmdDXDrawInstancedIndirect *pCmd = (SVGA3dCmdDXDrawInstancedIndirect *)pvCmd;
5862 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5863 rcParse = vmsvga3dCmdDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5864 break;
5865 }
5866
5867 case SVGA_3D_CMD_DX_DISPATCH:
5868 {
5869 SVGA3dCmdDXDispatch *pCmd = (SVGA3dCmdDXDispatch *)pvCmd;
5870 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5871 rcParse = vmsvga3dCmdDXDispatch(pThisCC, idDXContext, pCmd, cbCmd);
5872 break;
5873 }
5874
5875 case SVGA_3D_CMD_DX_DISPATCH_INDIRECT:
5876 {
5877 SVGA3dCmdDXDispatchIndirect *pCmd = (SVGA3dCmdDXDispatchIndirect *)pvCmd;
5878 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5879 rcParse = vmsvga3dCmdDXDispatchIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5880 break;
5881 }
5882
5883 case SVGA_3D_CMD_WRITE_ZERO_SURFACE:
5884 {
5885 SVGA3dCmdWriteZeroSurface *pCmd = (SVGA3dCmdWriteZeroSurface *)pvCmd;
5886 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5887 rcParse = vmsvga3dCmdWriteZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5888 break;
5889 }
5890
5891 case SVGA_3D_CMD_HINT_ZERO_SURFACE:
5892 {
5893 SVGA3dCmdHintZeroSurface *pCmd = (SVGA3dCmdHintZeroSurface *)pvCmd;
5894 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5895 rcParse = vmsvga3dCmdHintZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5896 break;
5897 }
5898
5899 case SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER:
5900 {
5901 SVGA3dCmdDXTransferToBuffer *pCmd = (SVGA3dCmdDXTransferToBuffer *)pvCmd;
5902 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5903 rcParse = vmsvga3dCmdDXTransferToBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5904 break;
5905 }
5906
5907 case SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT:
5908 {
5909 SVGA3dCmdDXSetStructureCount *pCmd = (SVGA3dCmdDXSetStructureCount *)pvCmd;
5910 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5911 rcParse = vmsvga3dCmdDXSetStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5912 break;
5913 }
5914
5915 case SVGA_3D_CMD_LOGICOPS_BITBLT:
5916 {
5917 SVGA3dCmdLogicOpsBitBlt *pCmd = (SVGA3dCmdLogicOpsBitBlt *)pvCmd;
5918 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5919 rcParse = vmsvga3dCmdLogicOpsBitBlt(pThisCC, idDXContext, pCmd, cbCmd);
5920 break;
5921 }
5922
5923 case SVGA_3D_CMD_LOGICOPS_TRANSBLT:
5924 {
5925 SVGA3dCmdLogicOpsTransBlt *pCmd = (SVGA3dCmdLogicOpsTransBlt *)pvCmd;
5926 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5927 rcParse = vmsvga3dCmdLogicOpsTransBlt(pThisCC, idDXContext, pCmd, cbCmd);
5928 break;
5929 }
5930
5931 case SVGA_3D_CMD_LOGICOPS_STRETCHBLT:
5932 {
5933 SVGA3dCmdLogicOpsStretchBlt *pCmd = (SVGA3dCmdLogicOpsStretchBlt *)pvCmd;
5934 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5935 rcParse = vmsvga3dCmdLogicOpsStretchBlt(pThisCC, idDXContext, pCmd, cbCmd);
5936 break;
5937 }
5938
5939 case SVGA_3D_CMD_LOGICOPS_COLORFILL:
5940 {
5941 SVGA3dCmdLogicOpsColorFill *pCmd = (SVGA3dCmdLogicOpsColorFill *)pvCmd;
5942 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5943 rcParse = vmsvga3dCmdLogicOpsColorFill(pThisCC, idDXContext, pCmd, cbCmd);
5944 break;
5945 }
5946
5947 case SVGA_3D_CMD_LOGICOPS_ALPHABLEND:
5948 {
5949 SVGA3dCmdLogicOpsAlphaBlend *pCmd = (SVGA3dCmdLogicOpsAlphaBlend *)pvCmd;
5950 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5951 rcParse = vmsvga3dCmdLogicOpsAlphaBlend(pThisCC, idDXContext, pCmd, cbCmd);
5952 break;
5953 }
5954
5955 case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND:
5956 {
5957 SVGA3dCmdLogicOpsClearTypeBlend *pCmd = (SVGA3dCmdLogicOpsClearTypeBlend *)pvCmd;
5958 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5959 rcParse = vmsvga3dCmdLogicOpsClearTypeBlend(pThisCC, idDXContext, pCmd, cbCmd);
5960 break;
5961 }
5962
5963 case SVGA_3D_CMD_RESERVED2_1:
5964 {
5965 VMSVGA_3D_CMD_NOTIMPL();
5966 break;
5967 }
5968
5969 case SVGA_3D_CMD_RESERVED2_2:
5970 {
5971 VMSVGA_3D_CMD_NOTIMPL();
5972 break;
5973 }
5974
5975 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V4:
5976 {
5977 SVGA3dCmdDefineGBSurface_v4 *pCmd = (SVGA3dCmdDefineGBSurface_v4 *)pvCmd;
5978 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5979 rcParse = vmsvga3dCmdDefineGBSurface_v4(pThisCC, idDXContext, pCmd, cbCmd);
5980 break;
5981 }
5982
5983 case SVGA_3D_CMD_DX_SET_CS_UA_VIEWS:
5984 {
5985 SVGA3dCmdDXSetCSUAViews *pCmd = (SVGA3dCmdDXSetCSUAViews *)pvCmd;
5986 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5987 rcParse = vmsvga3dCmdDXSetCSUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5988 break;
5989 }
5990
5991 case SVGA_3D_CMD_DX_SET_MIN_LOD:
5992 {
5993 SVGA3dCmdDXSetMinLOD *pCmd = (SVGA3dCmdDXSetMinLOD *)pvCmd;
5994 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5995 rcParse = vmsvga3dCmdDXSetMinLOD(pThisCC, idDXContext, pCmd, cbCmd);
5996 break;
5997 }
5998
5999 case SVGA_3D_CMD_RESERVED2_3:
6000 {
6001 VMSVGA_3D_CMD_NOTIMPL();
6002 break;
6003 }
6004
6005 case SVGA_3D_CMD_RESERVED2_4:
6006 {
6007 VMSVGA_3D_CMD_NOTIMPL();
6008 break;
6009 }
6010
6011 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2:
6012 {
6013 SVGA3dCmdDXDefineDepthStencilView_v2 *pCmd = (SVGA3dCmdDXDefineDepthStencilView_v2 *)pvCmd;
6014 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6015 rcParse = vmsvga3dCmdDXDefineDepthStencilView_v2(pThisCC, idDXContext, pCmd, cbCmd);
6016 break;
6017 }
6018
6019 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB:
6020 {
6021 SVGA3dCmdDXDefineStreamOutputWithMob *pCmd = (SVGA3dCmdDXDefineStreamOutputWithMob *)pvCmd;
6022 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6023 rcParse = vmsvga3dCmdDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd, cbCmd);
6024 break;
6025 }
6026
6027 case SVGA_3D_CMD_DX_SET_SHADER_IFACE:
6028 {
6029 SVGA3dCmdDXSetShaderIface *pCmd = (SVGA3dCmdDXSetShaderIface *)pvCmd;
6030 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6031 rcParse = vmsvga3dCmdDXSetShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6032 break;
6033 }
6034
6035 case SVGA_3D_CMD_DX_BIND_STREAMOUTPUT:
6036 {
6037 SVGA3dCmdDXBindStreamOutput *pCmd = (SVGA3dCmdDXBindStreamOutput *)pvCmd;
6038 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6039 rcParse = vmsvga3dCmdDXBindStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
6040 break;
6041 }
6042
6043 case SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS:
6044 {
6045 SVGA3dCmdSurfaceStretchBltNonMSToMS *pCmd = (SVGA3dCmdSurfaceStretchBltNonMSToMS *)pvCmd;
6046 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6047 rcParse = vmsvga3dCmdSurfaceStretchBltNonMSToMS(pThisCC, idDXContext, pCmd, cbCmd);
6048 break;
6049 }
6050
6051 case SVGA_3D_CMD_DX_BIND_SHADER_IFACE:
6052 {
6053 SVGA3dCmdDXBindShaderIface *pCmd = (SVGA3dCmdDXBindShaderIface *)pvCmd;
6054 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6055 rcParse = vmsvga3dCmdDXBindShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6056 break;
6057 }
6058
6059 /* Unsupported commands. */
6060 case SVGA_3D_CMD_DEAD4: /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
6061 case SVGA_3D_CMD_DEAD5: /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
6062 case SVGA_3D_CMD_DEAD6: /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
6063 case SVGA_3D_CMD_DEAD7: /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
6064 case SVGA_3D_CMD_DEAD8: /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
6065 case SVGA_3D_CMD_DEAD9: /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
6066 case SVGA_3D_CMD_DEAD10: /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
6067 case SVGA_3D_CMD_DEAD11: /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
6068 /* Prevent the compiler warning. */
6069 case SVGA_3D_CMD_LEGACY_BASE:
6070 case SVGA_3D_CMD_MAX:
6071 case SVGA_3D_CMD_FUTURE_MAX:
6072 /* No 'default' case */
6073 STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
6074 ASSERT_GUEST_MSG_FAILED(("enmCmdId=%d\n", enmCmdId));
6075 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
6076 rcParse = VERR_NOT_IMPLEMENTED;
6077 break;
6078 }
6079
6080 return VINF_SUCCESS;
6081// return rcParse;
6082}
6083# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
6084#endif /* VBOX_WITH_VMSVGA3D */
6085
6086
6087/*
6088 *
6089 * Handlers for FIFO commands.
6090 *
6091 * Every handler takes the following parameters:
6092 *
6093 * pThis The shared VGA/VMSVGA state.
6094 * pThisCC The VGA/VMSVGA state for ring-3.
6095 * pCmd The command data.
6096 */
6097
6098
6099/* SVGA_CMD_UPDATE */
6100void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
6101{
6102 RT_NOREF(pThis);
6103 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6104
6105 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
6106 Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
6107
6108 /** @todo Multiple screens? */
6109 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6110 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6111 return;
6112
6113 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6114}
6115
6116
6117/* SVGA_CMD_UPDATE_VERBOSE */
6118void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
6119{
6120 RT_NOREF(pThis);
6121 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6122
6123 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
6124 Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
6125
6126 /** @todo Multiple screens? */
6127 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6128 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6129 return;
6130
6131 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6132}
6133
6134
6135/* SVGA_CMD_RECT_FILL */
6136void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
6137{
6138 RT_NOREF(pThis, pCmd);
6139 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6140
6141 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
6142 Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6143 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
6144}
6145
6146
6147/* SVGA_CMD_RECT_COPY */
6148void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
6149{
6150 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6151
6152 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
6153 Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6154
6155 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6156 AssertPtrReturnVoid(pScreen);
6157
6158 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6159 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6160 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6161 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6162 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6163 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6164 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6165
6166 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6167 pCmd->width, pCmd->height, pThis->vram_size);
6168 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6169}
6170
6171
6172/* SVGA_CMD_RECT_ROP_COPY */
6173void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
6174{
6175 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6176
6177 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
6178 Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6179
6180 if (pCmd->rop != SVGA_ROP_COPY)
6181 {
6182 /* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
6183 * as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
6184 * respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
6185 * SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
6186 */
6187 LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
6188 pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6189 return;
6190 }
6191
6192 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6193 AssertPtrReturnVoid(pScreen);
6194
6195 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6196 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6197 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6198 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6199 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6200 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6201 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6202
6203 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6204 pCmd->width, pCmd->height, pThis->vram_size);
6205 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6206}
6207
6208
6209/* SVGA_CMD_DISPLAY_CURSOR */
6210void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
6211{
6212 RT_NOREF(pThis, pCmd);
6213 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6214
6215 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
6216 Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
6217 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
6218}
6219
6220
6221/* SVGA_CMD_MOVE_CURSOR */
6222void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
6223{
6224 RT_NOREF(pThis, pCmd);
6225 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6226
6227 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
6228 Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
6229 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
6230}
6231
6232
6233/* SVGA_CMD_DEFINE_CURSOR */
6234void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
6235{
6236 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6237
6238 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
6239 Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
6240 pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
6241
6242 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6243 ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
6244 ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
6245 RT_UNTRUSTED_VALIDATED_FENCE();
6246
6247 uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
6248 uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
6249 uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
6250
6251 uint8_t const *pbSrcAndMask = (uint8_t const *)(pCmd + 1);
6252 uint8_t const *pbSrcXorMask = (uint8_t const *)(pCmd + 1) + cbSrcAndMask;
6253
6254 uint32_t const cx = pCmd->width;
6255 uint32_t const cy = pCmd->height;
6256
6257 /*
6258 * Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
6259 * The AND data uses 8-bit aligned scanlines.
6260 * The XOR data must be starting on a 32-bit boundrary.
6261 */
6262 uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
6263 uint32_t cbDstAndMask = cbDstAndLine * cy;
6264 uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
6265 uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
6266
6267 uint8_t *pbCopy = (uint8_t *)RTMemAlloc(cbCopy);
6268 AssertReturnVoid(pbCopy);
6269
6270 /* Convert the AND mask. */
6271 uint8_t *pbDst = pbCopy;
6272 uint8_t const *pbSrc = pbSrcAndMask;
6273 switch (pCmd->andMaskDepth)
6274 {
6275 case 1:
6276 if (cbSrcAndLine == cbDstAndLine)
6277 memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
6278 else
6279 {
6280 Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
6281 for (uint32_t y = 0; y < cy; y++)
6282 {
6283 memcpy(pbDst, pbSrc, cbDstAndLine);
6284 pbDst += cbDstAndLine;
6285 pbSrc += cbSrcAndLine;
6286 }
6287 }
6288 break;
6289 /* Should take the XOR mask into account for the multi-bit AND mask. */
6290 case 8:
6291 for (uint32_t y = 0; y < cy; y++)
6292 {
6293 for (uint32_t x = 0; x < cx; )
6294 {
6295 uint8_t bDst = 0;
6296 uint8_t fBit = 0x80;
6297 do
6298 {
6299 uintptr_t const idxPal = pbSrc[x] * 3;
6300 if ((( pThis->last_palette[idxPal]
6301 | (pThis->last_palette[idxPal] >> 8)
6302 | (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
6303 bDst |= fBit;
6304 fBit >>= 1;
6305 x++;
6306 } while (x < cx && (x & 7));
6307 pbDst[(x - 1) / 8] = bDst;
6308 }
6309 pbDst += cbDstAndLine;
6310 pbSrc += cbSrcAndLine;
6311 }
6312 break;
6313 case 15:
6314 for (uint32_t y = 0; y < cy; y++)
6315 {
6316 for (uint32_t x = 0; x < cx; )
6317 {
6318 uint8_t bDst = 0;
6319 uint8_t fBit = 0x80;
6320 do
6321 {
6322 if ((pbSrc[x * 2] | (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
6323 bDst |= fBit;
6324 fBit >>= 1;
6325 x++;
6326 } while (x < cx && (x & 7));
6327 pbDst[(x - 1) / 8] = bDst;
6328 }
6329 pbDst += cbDstAndLine;
6330 pbSrc += cbSrcAndLine;
6331 }
6332 break;
6333 case 16:
6334 for (uint32_t y = 0; y < cy; y++)
6335 {
6336 for (uint32_t x = 0; x < cx; )
6337 {
6338 uint8_t bDst = 0;
6339 uint8_t fBit = 0x80;
6340 do
6341 {
6342 if ((pbSrc[x * 2] | pbSrc[x * 2 + 1]) >= 0xfc)
6343 bDst |= fBit;
6344 fBit >>= 1;
6345 x++;
6346 } while (x < cx && (x & 7));
6347 pbDst[(x - 1) / 8] = bDst;
6348 }
6349 pbDst += cbDstAndLine;
6350 pbSrc += cbSrcAndLine;
6351 }
6352 break;
6353 case 24:
6354 for (uint32_t y = 0; y < cy; y++)
6355 {
6356 for (uint32_t x = 0; x < cx; )
6357 {
6358 uint8_t bDst = 0;
6359 uint8_t fBit = 0x80;
6360 do
6361 {
6362 if ((pbSrc[x * 3] | pbSrc[x * 3 + 1] | pbSrc[x * 3 + 2]) >= 0xfc)
6363 bDst |= fBit;
6364 fBit >>= 1;
6365 x++;
6366 } while (x < cx && (x & 7));
6367 pbDst[(x - 1) / 8] = bDst;
6368 }
6369 pbDst += cbDstAndLine;
6370 pbSrc += cbSrcAndLine;
6371 }
6372 break;
6373 case 32:
6374 for (uint32_t y = 0; y < cy; y++)
6375 {
6376 for (uint32_t x = 0; x < cx; )
6377 {
6378 uint8_t bDst = 0;
6379 uint8_t fBit = 0x80;
6380 do
6381 {
6382 if ((pbSrc[x * 4] | pbSrc[x * 4 + 1] | pbSrc[x * 4 + 2] | pbSrc[x * 4 + 3]) >= 0xfc)
6383 bDst |= fBit;
6384 fBit >>= 1;
6385 x++;
6386 } while (x < cx && (x & 7));
6387 pbDst[(x - 1) / 8] = bDst;
6388 }
6389 pbDst += cbDstAndLine;
6390 pbSrc += cbSrcAndLine;
6391 }
6392 break;
6393 default:
6394 RTMemFreeZ(pbCopy, cbCopy);
6395 AssertFailedReturnVoid();
6396 }
6397
6398 /* Convert the XOR mask. */
6399 uint32_t *pu32Dst = (uint32_t *)(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
6400 pbSrc = pbSrcXorMask;
6401 switch (pCmd->xorMaskDepth)
6402 {
6403 case 1:
6404 for (uint32_t y = 0; y < cy; y++)
6405 {
6406 for (uint32_t x = 0; x < cx; )
6407 {
6408 /* most significant bit is the left most one. */
6409 uint8_t bSrc = pbSrc[x / 8];
6410 do
6411 {
6412 *pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
6413 bSrc <<= 1;
6414 x++;
6415 } while ((x & 7) && x < cx);
6416 }
6417 pbSrc += cbSrcXorLine;
6418 }
6419 break;
6420 case 8:
6421 for (uint32_t y = 0; y < cy; y++)
6422 {
6423 for (uint32_t x = 0; x < cx; x++)
6424 {
6425 uint32_t u = pThis->last_palette[pbSrc[x]];
6426 *pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
6427 }
6428 pbSrc += cbSrcXorLine;
6429 }
6430 break;
6431 case 15: /* Src: RGB-5-5-5 */
6432 for (uint32_t y = 0; y < cy; y++)
6433 {
6434 for (uint32_t x = 0; x < cx; x++)
6435 {
6436 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6437 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6438 ((uValue >> 5) & 0x1f) << 3,
6439 ((uValue >> 10) & 0x1f) << 3, 0);
6440 }
6441 pbSrc += cbSrcXorLine;
6442 }
6443 break;
6444 case 16: /* Src: RGB-5-6-5 */
6445 for (uint32_t y = 0; y < cy; y++)
6446 {
6447 for (uint32_t x = 0; x < cx; x++)
6448 {
6449 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6450 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6451 ((uValue >> 5) & 0x3f) << 2,
6452 ((uValue >> 11) & 0x1f) << 3, 0);
6453 }
6454 pbSrc += cbSrcXorLine;
6455 }
6456 break;
6457 case 24:
6458 for (uint32_t y = 0; y < cy; y++)
6459 {
6460 for (uint32_t x = 0; x < cx; x++)
6461 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*3], pbSrc[x*3 + 1], pbSrc[x*3 + 2], 0);
6462 pbSrc += cbSrcXorLine;
6463 }
6464 break;
6465 case 32:
6466 for (uint32_t y = 0; y < cy; y++)
6467 {
6468 for (uint32_t x = 0; x < cx; x++)
6469 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*4], pbSrc[x*4 + 1], pbSrc[x*4 + 2], 0);
6470 pbSrc += cbSrcXorLine;
6471 }
6472 break;
6473 default:
6474 RTMemFreeZ(pbCopy, cbCopy);
6475 AssertFailedReturnVoid();
6476 }
6477
6478 /*
6479 * Pass it to the frontend/whatever.
6480 */
6481 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6482 cx, cy, pbCopy, cbCopy);
6483}
6484
6485
6486/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
6487void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
6488{
6489 RT_NOREF(pThis);
6490 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6491
6492 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
6493 Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
6494
6495 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
6496 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6497 RT_UNTRUSTED_VALIDATED_FENCE();
6498
6499 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
6500 uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
6501 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
6502 uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
6503 uint32_t cbCursorShape = cbAndMask + cbXorMask;
6504
6505 uint8_t *pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
6506 AssertPtrReturnVoid(pCursorCopy);
6507
6508 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
6509 memset(pCursorCopy, 0xff, cbAndMask);
6510 /* Colour data */
6511 memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
6512
6513 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6514 pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
6515}
6516
6517
6518/* SVGA_CMD_ESCAPE */
6519void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
6520{
6521 RT_NOREF(pThis);
6522 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6523
6524 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
6525
6526 if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
6527 {
6528 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
6529 RT_UNTRUSTED_VALIDATED_FENCE();
6530
6531 uint32_t const cmd = *(uint32_t *)(pCmd + 1);
6532 Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
6533
6534 switch (cmd)
6535 {
6536 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
6537 {
6538 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pCmd + 1);
6539 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
6540 RT_UNTRUSTED_VALIDATED_FENCE();
6541
6542 uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
6543
6544 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
6545 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
6546 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
6547 RT_NOREF_PV(pVideoCmd);
6548 break;
6549 }
6550
6551 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
6552 {
6553 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pCmd + 1);
6554 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
6555 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
6556 RT_NOREF_PV(pVideoCmd);
6557 break;
6558 }
6559
6560 default:
6561 Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
6562 break;
6563 }
6564 }
6565 else
6566 Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
6567}
6568
6569
6570/* SVGA_CMD_DEFINE_SCREEN */
6571void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
6572{
6573 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6574
6575 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
6576 Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
6577 pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
6578 pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
6579
6580 uint32_t const idScreen = pCmd->screen.id;
6581 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6582
6583 uint32_t const uWidth = pCmd->screen.size.width;
6584 ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
6585
6586 uint32_t const uHeight = pCmd->screen.size.height;
6587 ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
6588
6589 uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
6590 uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
6591 ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
6592
6593 uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
6594 ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
6595
6596 uint32_t const cbVram = pThis->vram_size - uScreenOffset;
6597 /* If we have a not zero pitch, then height can't exceed the available VRAM. */
6598 ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
6599 || (cbPitch > 0 && uHeight <= cbVram / cbPitch));
6600 RT_UNTRUSTED_VALIDATED_FENCE();
6601
6602 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6603 pScreen->fDefined = true;
6604 pScreen->fModified = true;
6605 pScreen->fuScreen = pCmd->screen.flags;
6606 pScreen->idScreen = idScreen;
6607 if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE | SVGA_SCREEN_BLANKING)))
6608 {
6609 /* Not blanked. */
6610 ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
6611 RT_UNTRUSTED_VALIDATED_FENCE();
6612
6613 pScreen->xOrigin = pCmd->screen.root.x;
6614 pScreen->yOrigin = pCmd->screen.root.y;
6615 pScreen->cWidth = uWidth;
6616 pScreen->cHeight = uHeight;
6617 pScreen->offVRAM = uScreenOffset;
6618 pScreen->cbPitch = cbPitch;
6619 pScreen->cBpp = 32;
6620 }
6621 else
6622 {
6623 /* Screen blanked. Keep old values. */
6624 }
6625
6626 pThis->svga.fGFBRegisters = false;
6627 vmsvgaR3ChangeMode(pThis, pThisCC);
6628
6629#ifdef VBOX_WITH_VMSVGA3D
6630 if (RT_LIKELY(pThis->svga.f3DEnabled))
6631 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
6632#endif
6633}
6634
6635
6636/* SVGA_CMD_DESTROY_SCREEN */
6637void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
6638{
6639 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6640
6641 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
6642 Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
6643
6644 uint32_t const idScreen = pCmd->screenId;
6645 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6646 RT_UNTRUSTED_VALIDATED_FENCE();
6647
6648 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6649 pScreen->fModified = true;
6650 pScreen->fDefined = false;
6651 pScreen->idScreen = idScreen;
6652
6653#ifdef VBOX_WITH_VMSVGA3D
6654 if (RT_LIKELY(pThis->svga.f3DEnabled))
6655 vmsvga3dDestroyScreen(pThisCC, pScreen);
6656#endif
6657 vmsvgaR3ChangeMode(pThis, pThisCC);
6658}
6659
6660
6661/* SVGA_CMD_DEFINE_GMRFB */
6662void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
6663{
6664 RT_NOREF(pThis);
6665 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6666
6667 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
6668 Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
6669 pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
6670
6671 pSvgaR3State->GMRFB.ptr = pCmd->ptr;
6672 pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
6673 pSvgaR3State->GMRFB.format = pCmd->format;
6674}
6675
6676
6677/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
6678void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
6679{
6680 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6681
6682 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
6683 Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
6684 pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
6685
6686 ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6687 RT_UNTRUSTED_VALIDATED_FENCE();
6688
6689 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
6690 AssertPtrReturnVoid(pScreen);
6691
6692 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
6693 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6694
6695 /* Clip destRect to the screen dimensions. */
6696 SVGASignedRect screenRect;
6697 screenRect.left = 0;
6698 screenRect.top = 0;
6699 screenRect.right = pScreen->cWidth;
6700 screenRect.bottom = pScreen->cHeight;
6701 SVGASignedRect clipRect = pCmd->destRect;
6702 vmsvgaR3ClipRect(&screenRect, &clipRect);
6703 RT_UNTRUSTED_VALIDATED_FENCE();
6704
6705 uint32_t const width = clipRect.right - clipRect.left;
6706 uint32_t const height = clipRect.bottom - clipRect.top;
6707
6708 if ( width == 0
6709 || height == 0)
6710 return; /* Nothing to do. */
6711
6712 int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
6713 int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
6714
6715 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6716 * Prepare parameters for vmsvgaR3GmrTransfer.
6717 */
6718 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6719
6720 /* Destination: host buffer which describes the screen 0 VRAM.
6721 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6722 */
6723 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6724 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6725 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6726 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6727 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6728 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6729 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6730 + cbScanline * clipRect.top;
6731 int32_t const cbHstPitch = cbScanline;
6732
6733 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6734 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6735 uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6736 + pSvgaR3State->GMRFB.bytesPerLine * srcy;
6737 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6738
6739 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
6740 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6741 gstPtr, offGst, cbGstPitch,
6742 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6743 AssertRC(rc);
6744 vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
6745}
6746
6747
6748/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
6749void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
6750{
6751 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6752
6753 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
6754 /* Note! This can fetch 3d render results as well!! */
6755 Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
6756 pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
6757
6758 ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6759 RT_UNTRUSTED_VALIDATED_FENCE();
6760
6761 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
6762 AssertPtrReturnVoid(pScreen);
6763
6764 /** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
6765 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6766
6767 /* Clip destRect to the screen dimensions. */
6768 SVGASignedRect screenRect;
6769 screenRect.left = 0;
6770 screenRect.top = 0;
6771 screenRect.right = pScreen->cWidth;
6772 screenRect.bottom = pScreen->cHeight;
6773 SVGASignedRect clipRect = pCmd->srcRect;
6774 vmsvgaR3ClipRect(&screenRect, &clipRect);
6775 RT_UNTRUSTED_VALIDATED_FENCE();
6776
6777 uint32_t const width = clipRect.right - clipRect.left;
6778 uint32_t const height = clipRect.bottom - clipRect.top;
6779
6780 if ( width == 0
6781 || height == 0)
6782 return; /* Nothing to do. */
6783
6784 int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
6785 int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
6786
6787 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6788 * Prepare parameters for vmsvgaR3GmrTransfer.
6789 */
6790 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6791
6792 /* Source: host buffer which describes the screen 0 VRAM.
6793 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6794 */
6795 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6796 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6797 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6798 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6799 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6800 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6801 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6802 + cbScanline * clipRect.top;
6803 int32_t const cbHstPitch = cbScanline;
6804
6805 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6806 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6807 uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6808 + pSvgaR3State->GMRFB.bytesPerLine * dsty;
6809 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6810
6811 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
6812 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6813 gstPtr, offGst, cbGstPitch,
6814 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6815 AssertRC(rc);
6816}
6817
6818
6819/* SVGA_CMD_ANNOTATION_FILL */
6820void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
6821{
6822 RT_NOREF(pThis);
6823 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6824
6825 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
6826 Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
6827
6828 pSvgaR3State->colorAnnotation = pCmd->color;
6829}
6830
6831
6832/* SVGA_CMD_ANNOTATION_COPY */
6833void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
6834{
6835 RT_NOREF(pThis, pCmd);
6836 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6837
6838 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
6839 Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
6840
6841 AssertFailed();
6842}
6843
6844
6845#ifdef VBOX_WITH_VMSVGA3D
6846/* SVGA_CMD_DEFINE_GMR2 */
6847void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
6848{
6849 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6850
6851 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
6852 Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
6853
6854 /* Validate current GMR id. */
6855 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6856 ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
6857 RT_UNTRUSTED_VALIDATED_FENCE();
6858
6859 if (!pCmd->numPages)
6860 {
6861 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
6862 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6863 }
6864 else
6865 {
6866 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6867 if (pGMR->cMaxPages)
6868 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
6869
6870 /* Not sure if we should always free the descriptor, but for simplicity
6871 we do so if the new size is smaller than the current. */
6872 /** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
6873 if (pGMR->cbTotal / X86_PAGE_SIZE > pCmd->numPages)
6874 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6875
6876 pGMR->cMaxPages = pCmd->numPages;
6877 /* The rest is done by the REMAP_GMR2 command. */
6878 }
6879}
6880
6881
6882/* SVGA_CMD_REMAP_GMR2 */
6883void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
6884{
6885 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6886
6887 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
6888 Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
6889
6890 /* Validate current GMR id and size. */
6891 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6892 RT_UNTRUSTED_VALIDATED_FENCE();
6893 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6894 ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
6895 <= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
6896 ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
6897
6898 if (pCmd->numPages == 0)
6899 return;
6900 RT_UNTRUSTED_VALIDATED_FENCE();
6901
6902 /* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
6903 uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
6904
6905 /*
6906 * We flatten the existing descriptors into a page array, overwrite the
6907 * pages specified in this command and then recompress the descriptor.
6908 */
6909 /** @todo Optimize the GMR remap algorithm! */
6910
6911 /* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
6912 uint64_t *paNewPage64 = NULL;
6913 if (pGMR->paDesc)
6914 {
6915 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
6916
6917 paNewPage64 = (uint64_t *)RTMemAllocZ(cNewTotalPages * sizeof(uint64_t));
6918 AssertPtrReturnVoid(paNewPage64);
6919
6920 uint32_t idxPage = 0;
6921 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
6922 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
6923 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
6924 AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
6925 RT_UNTRUSTED_VALIDATED_FENCE();
6926 }
6927
6928 /* Free the old GMR if present. */
6929 if (pGMR->paDesc)
6930 RTMemFree(pGMR->paDesc);
6931
6932 /* Allocate the maximum amount possible (everything non-continuous) */
6933 PVMSVGAGMRDESCRIPTOR paDescs;
6934 pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
6935 AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
6936
6937 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
6938 {
6939 /** @todo */
6940 AssertFailed();
6941 pGMR->numDescriptors = 0;
6942 }
6943 else
6944 {
6945 uint32_t *paPages32 = (uint32_t *)(pCmd + 1);
6946 uint64_t *paPages64 = (uint64_t *)(pCmd + 1);
6947 bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
6948
6949 uint32_t cPages;
6950 if (paNewPage64)
6951 {
6952 /* Overwrite the old page array with the new page values. */
6953 if (fGCPhys64)
6954 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6955 paNewPage64[i] = paPages64[i - pCmd->offsetPages];
6956 else
6957 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6958 paNewPage64[i] = paPages32[i - pCmd->offsetPages];
6959
6960 /* Use the updated page array instead of the command data. */
6961 fGCPhys64 = true;
6962 paPages64 = paNewPage64;
6963 cPages = cNewTotalPages;
6964 }
6965 else
6966 cPages = pCmd->numPages;
6967
6968 /* The first page. */
6969 /** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
6970 * applied to paNewPage64. */
6971 RTGCPHYS GCPhys;
6972 if (fGCPhys64)
6973 GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6974 else
6975 GCPhys = (RTGCPHYS)paPages32[0] << GUEST_PAGE_SHIFT;
6976 paDescs[0].GCPhys = GCPhys;
6977 paDescs[0].numPages = 1;
6978
6979 /* Subsequent pages. */
6980 uint32_t iDescriptor = 0;
6981 for (uint32_t i = 1; i < cPages; i++)
6982 {
6983 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
6984 GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6985 else
6986 GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
6987
6988 /* Continuous physical memory? */
6989 if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
6990 {
6991 Assert(paDescs[iDescriptor].numPages);
6992 paDescs[iDescriptor].numPages++;
6993 Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
6994 }
6995 else
6996 {
6997 iDescriptor++;
6998 paDescs[iDescriptor].GCPhys = GCPhys;
6999 paDescs[iDescriptor].numPages = 1;
7000 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
7001 }
7002 }
7003
7004 pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
7005 Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
7006 pGMR->numDescriptors = iDescriptor + 1;
7007 }
7008
7009 if (paNewPage64)
7010 RTMemFree(paNewPage64);
7011}
7012
7013
7014/**
7015 * Free the specified GMR
7016 *
7017 * @param pThisCC The VGA/VMSVGA state for ring-3.
7018 * @param idGMR GMR id
7019 */
7020void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
7021{
7022 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7023
7024 /* Free the old descriptor if present. */
7025 PGMR pGMR = &pSVGAState->paGMR[idGMR];
7026 if ( pGMR->numDescriptors
7027 || pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
7028 {
7029# ifdef DEBUG_GMR_ACCESS
7030 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
7031# endif
7032
7033 Assert(pGMR->paDesc);
7034 RTMemFree(pGMR->paDesc);
7035 pGMR->paDesc = NULL;
7036 pGMR->numDescriptors = 0;
7037 pGMR->cbTotal = 0;
7038 pGMR->cMaxPages = 0;
7039 }
7040 Assert(!pGMR->cMaxPages);
7041 Assert(!pGMR->cbTotal);
7042}
7043#endif /* VBOX_WITH_VMSVGA3D */
7044
7045
7046/**
7047 * Copy between a GMR and a host memory buffer.
7048 *
7049 * @returns VBox status code.
7050 * @param pThis The shared VGA/VMSVGA instance data.
7051 * @param pThisCC The VGA/VMSVGA state for ring-3.
7052 * @param enmTransferType Transfer type (read/write)
7053 * @param pbHstBuf Host buffer pointer (valid)
7054 * @param cbHstBuf Size of host buffer (valid)
7055 * @param offHst Host buffer offset of the first scanline
7056 * @param cbHstPitch Destination buffer pitch
7057 * @param gstPtr GMR description
7058 * @param offGst Guest buffer offset of the first scanline
7059 * @param cbGstPitch Guest buffer pitch
7060 * @param cbWidth Width in bytes to copy
7061 * @param cHeight Number of scanllines to copy
7062 */
7063int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
7064 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
7065 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
7066 uint32_t cbWidth, uint32_t cHeight)
7067{
7068 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7069 PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
7070 int rc;
7071
7072 LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
7073 enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
7074 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
7075 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
7076 AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
7077
7078 PGMR pGMR;
7079 uint32_t cbGmr; /* The GMR size in bytes. */
7080 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7081 {
7082 pGMR = NULL;
7083 cbGmr = pThis->vram_size;
7084 }
7085 else
7086 {
7087 AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
7088 RT_UNTRUSTED_VALIDATED_FENCE();
7089 pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
7090 cbGmr = pGMR->cbTotal;
7091 }
7092
7093 /*
7094 * GMR
7095 */
7096 /* Calculate GMR offset of the data to be copied. */
7097 AssertMsgReturn(gstPtr.offset < cbGmr,
7098 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7099 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7100 VERR_INVALID_PARAMETER);
7101 RT_UNTRUSTED_VALIDATED_FENCE();
7102 AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
7103 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7104 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7105 VERR_INVALID_PARAMETER);
7106 RT_UNTRUSTED_VALIDATED_FENCE();
7107 uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
7108
7109 /* Verify that cbWidth is less than scanline and fits into the GMR. */
7110 uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
7111 AssertMsgReturn(cbGmrScanline != 0,
7112 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7113 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7114 VERR_INVALID_PARAMETER);
7115 RT_UNTRUSTED_VALIDATED_FENCE();
7116 AssertMsgReturn(cbWidth <= cbGmrScanline,
7117 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7118 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7119 VERR_INVALID_PARAMETER);
7120 AssertMsgReturn(cbWidth <= cbGmr - offGmr,
7121 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7122 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7123 VERR_INVALID_PARAMETER);
7124 RT_UNTRUSTED_VALIDATED_FENCE();
7125
7126 /* How many bytes are available for the data in the GMR. */
7127 uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
7128
7129 /* How many scanlines would fit into the available data. */
7130 uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
7131 uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
7132 if (cbWidth <= cbGmrLastScanline)
7133 ++cGmrScanlines;
7134
7135 if (cHeight > cGmrScanlines)
7136 cHeight = cGmrScanlines;
7137
7138 AssertMsgReturn(cHeight > 0,
7139 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7140 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7141 VERR_INVALID_PARAMETER);
7142 RT_UNTRUSTED_VALIDATED_FENCE();
7143
7144 /*
7145 * Host buffer.
7146 */
7147 AssertMsgReturn(offHst < cbHstBuf,
7148 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7149 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7150 VERR_INVALID_PARAMETER);
7151
7152 /* Verify that cbWidth is less than scanline and fits into the buffer. */
7153 uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
7154 AssertMsgReturn(cbHstScanline != 0,
7155 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7156 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7157 VERR_INVALID_PARAMETER);
7158 AssertMsgReturn(cbWidth <= cbHstScanline,
7159 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7160 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7161 VERR_INVALID_PARAMETER);
7162 AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
7163 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7164 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7165 VERR_INVALID_PARAMETER);
7166
7167 /* How many bytes are available for the data in the buffer. */
7168 uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
7169
7170 /* How many scanlines would fit into the available data. */
7171 uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
7172 uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
7173 if (cbWidth <= cbHstLastScanline)
7174 ++cHstScanlines;
7175
7176 if (cHeight > cHstScanlines)
7177 cHeight = cHstScanlines;
7178
7179 AssertMsgReturn(cHeight > 0,
7180 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7181 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7182 VERR_INVALID_PARAMETER);
7183
7184 uint8_t *pbHst = pbHstBuf + offHst;
7185
7186 /* Shortcut for the framebuffer. */
7187 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7188 {
7189 uint8_t *pbGst = pThisCC->pbVRam + offGmr;
7190
7191 uint8_t const *pbSrc;
7192 int32_t cbSrcPitch;
7193 uint8_t *pbDst;
7194 int32_t cbDstPitch;
7195
7196 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
7197 {
7198 pbSrc = pbHst;
7199 cbSrcPitch = cbHstPitch;
7200 pbDst = pbGst;
7201 cbDstPitch = cbGstPitch;
7202 }
7203 else
7204 {
7205 pbSrc = pbGst;
7206 cbSrcPitch = cbGstPitch;
7207 pbDst = pbHst;
7208 cbDstPitch = cbHstPitch;
7209 }
7210
7211 if ( cbWidth == (uint32_t)cbGstPitch
7212 && cbGstPitch == cbHstPitch)
7213 {
7214 /* Entire scanlines, positive pitch. */
7215 memcpy(pbDst, pbSrc, cbWidth * cHeight);
7216 }
7217 else
7218 {
7219 for (uint32_t i = 0; i < cHeight; ++i)
7220 {
7221 memcpy(pbDst, pbSrc, cbWidth);
7222
7223 pbDst += cbDstPitch;
7224 pbSrc += cbSrcPitch;
7225 }
7226 }
7227 return VINF_SUCCESS;
7228 }
7229
7230 AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
7231 AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
7232
7233 PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
7234 uint32_t iDesc = 0; /* Index in the descriptor array. */
7235 uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
7236 uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
7237 uint8_t *pbHstScanline = pbHst; /* Host address of the scanline which is being copied. */
7238 for (uint32_t i = 0; i < cHeight; ++i)
7239 {
7240 uint32_t cbCurrentWidth = cbWidth;
7241 uint32_t offGmrCurrent = offGmrScanline;
7242 uint8_t *pbCurrentHost = pbHstScanline;
7243
7244 /* Find the right descriptor */
7245 while (offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE <= offGmrCurrent)
7246 {
7247 offDesc += paDesc[iDesc].numPages * GUEST_PAGE_SIZE;
7248 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
7249 ++iDesc;
7250 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7251 }
7252
7253 while (cbCurrentWidth)
7254 {
7255 uint32_t cbToCopy;
7256
7257 if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE)
7258 cbToCopy = cbCurrentWidth;
7259 else
7260 {
7261 cbToCopy = (offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE - offGmrCurrent);
7262 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
7263 }
7264
7265 RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
7266
7267 Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
7268
7269 /*
7270 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
7271 * guest-side VMSVGA driver seems to allocate non-DMA (physical memory) addresses,
7272 * see @bugref{9654#c75}.
7273 */
7274 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
7275 rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7276 else
7277 rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7278 AssertRCBreak(rc);
7279
7280 cbCurrentWidth -= cbToCopy;
7281 offGmrCurrent += cbToCopy;
7282 pbCurrentHost += cbToCopy;
7283
7284 /* Go to the next descriptor if there's anything left. */
7285 if (cbCurrentWidth)
7286 {
7287 offDesc += paDesc[iDesc].numPages * GUEST_PAGE_SIZE;
7288 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
7289 ++iDesc;
7290 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7291 }
7292 }
7293
7294 offGmrScanline += cbGstPitch;
7295 pbHstScanline += cbHstPitch;
7296 }
7297
7298 return VINF_SUCCESS;
7299}
7300
7301
7302/**
7303 * Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
7304 *
7305 * @param pSizeSrc Source surface dimensions.
7306 * @param pSizeDest Destination surface dimensions.
7307 * @param pBox Coordinates to be clipped.
7308 */
7309void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox)
7310{
7311 /* Src x, w */
7312 if (pBox->srcx > pSizeSrc->width)
7313 pBox->srcx = pSizeSrc->width;
7314 if (pBox->w > pSizeSrc->width - pBox->srcx)
7315 pBox->w = pSizeSrc->width - pBox->srcx;
7316
7317 /* Src y, h */
7318 if (pBox->srcy > pSizeSrc->height)
7319 pBox->srcy = pSizeSrc->height;
7320 if (pBox->h > pSizeSrc->height - pBox->srcy)
7321 pBox->h = pSizeSrc->height - pBox->srcy;
7322
7323 /* Src z, d */
7324 if (pBox->srcz > pSizeSrc->depth)
7325 pBox->srcz = pSizeSrc->depth;
7326 if (pBox->d > pSizeSrc->depth - pBox->srcz)
7327 pBox->d = pSizeSrc->depth - pBox->srcz;
7328
7329 /* Dest x, w */
7330 if (pBox->x > pSizeDest->width)
7331 pBox->x = pSizeDest->width;
7332 if (pBox->w > pSizeDest->width - pBox->x)
7333 pBox->w = pSizeDest->width - pBox->x;
7334
7335 /* Dest y, h */
7336 if (pBox->y > pSizeDest->height)
7337 pBox->y = pSizeDest->height;
7338 if (pBox->h > pSizeDest->height - pBox->y)
7339 pBox->h = pSizeDest->height - pBox->y;
7340
7341 /* Dest z, d */
7342 if (pBox->z > pSizeDest->depth)
7343 pBox->z = pSizeDest->depth;
7344 if (pBox->d > pSizeDest->depth - pBox->z)
7345 pBox->d = pSizeDest->depth - pBox->z;
7346}
7347
7348
7349/**
7350 * Unsigned coordinates in pBox. Clip to [0; pSize).
7351 *
7352 * @param pSize Source surface dimensions.
7353 * @param pBox Coordinates to be clipped.
7354 */
7355void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox)
7356{
7357 /* x, w */
7358 if (pBox->x > pSize->width)
7359 pBox->x = pSize->width;
7360 if (pBox->w > pSize->width - pBox->x)
7361 pBox->w = pSize->width - pBox->x;
7362
7363 /* y, h */
7364 if (pBox->y > pSize->height)
7365 pBox->y = pSize->height;
7366 if (pBox->h > pSize->height - pBox->y)
7367 pBox->h = pSize->height - pBox->y;
7368
7369 /* z, d */
7370 if (pBox->z > pSize->depth)
7371 pBox->z = pSize->depth;
7372 if (pBox->d > pSize->depth - pBox->z)
7373 pBox->d = pSize->depth - pBox->z;
7374}
7375
7376
7377/**
7378 * Clip.
7379 *
7380 * @param pBound Bounding rectangle.
7381 * @param pRect Rectangle to be clipped.
7382 */
7383void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect)
7384{
7385 int32_t left;
7386 int32_t top;
7387 int32_t right;
7388 int32_t bottom;
7389
7390 /* Right order. */
7391 Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
7392 if (pRect->left < pRect->right)
7393 {
7394 left = pRect->left;
7395 right = pRect->right;
7396 }
7397 else
7398 {
7399 left = pRect->right;
7400 right = pRect->left;
7401 }
7402 if (pRect->top < pRect->bottom)
7403 {
7404 top = pRect->top;
7405 bottom = pRect->bottom;
7406 }
7407 else
7408 {
7409 top = pRect->bottom;
7410 bottom = pRect->top;
7411 }
7412
7413 if (left < pBound->left)
7414 left = pBound->left;
7415 if (right < pBound->left)
7416 right = pBound->left;
7417
7418 if (left > pBound->right)
7419 left = pBound->right;
7420 if (right > pBound->right)
7421 right = pBound->right;
7422
7423 if (top < pBound->top)
7424 top = pBound->top;
7425 if (bottom < pBound->top)
7426 bottom = pBound->top;
7427
7428 if (top > pBound->bottom)
7429 top = pBound->bottom;
7430 if (bottom > pBound->bottom)
7431 bottom = pBound->bottom;
7432
7433 pRect->left = left;
7434 pRect->right = right;
7435 pRect->top = top;
7436 pRect->bottom = bottom;
7437}
7438
7439
7440/**
7441 * Clip.
7442 *
7443 * @param pBound Bounding rectangle.
7444 * @param pRect Rectangle to be clipped.
7445 */
7446void vmsvgaR3Clip3dRect(SVGA3dRect const *pBound, SVGA3dRect RT_UNTRUSTED_GUEST *pRect)
7447{
7448 uint32_t const leftBound = pBound->x;
7449 uint32_t const rightBound = pBound->x + pBound->w;
7450 uint32_t const topBound = pBound->y;
7451 uint32_t const bottomBound = pBound->y + pBound->h;
7452
7453 uint32_t x = pRect->x;
7454 uint32_t y = pRect->y;
7455 uint32_t w = pRect->w;
7456 uint32_t h = pRect->h;
7457
7458 /* Make sure that right and bottom coordinates can be safely computed. */
7459 if (x > rightBound)
7460 x = rightBound;
7461 if (w > rightBound - x)
7462 w = rightBound - x;
7463 if (y > bottomBound)
7464 y = bottomBound;
7465 if (h > bottomBound - y)
7466 h = bottomBound - y;
7467
7468 /* Switch from x, y, w, h to left, top, right, bottom. */
7469 uint32_t left = x;
7470 uint32_t right = x + w;
7471 uint32_t top = y;
7472 uint32_t bottom = y + h;
7473
7474 /* A standard left, right, bottom, top clipping. */
7475 if (left < leftBound)
7476 left = leftBound;
7477 if (right < leftBound)
7478 right = leftBound;
7479
7480 if (left > rightBound)
7481 left = rightBound;
7482 if (right > rightBound)
7483 right = rightBound;
7484
7485 if (top < topBound)
7486 top = topBound;
7487 if (bottom < topBound)
7488 bottom = topBound;
7489
7490 if (top > bottomBound)
7491 top = bottomBound;
7492 if (bottom > bottomBound)
7493 bottom = bottomBound;
7494
7495 /* Back to x, y, w, h representation. */
7496 pRect->x = left;
7497 pRect->y = top;
7498 pRect->w = right - left;
7499 pRect->h = bottom - top;
7500}
7501
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