DevVGA-SVGA-cmd.cpp@ 92162

Last change on this file since 92162 was 91928, checked in by vboxsync, 3 years ago
VMM,Devices: Eliminate direct calls to PGMHandlerPhysical* APIs and introduce callbacks in the device helper callback table, bugref:10074
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 271.4 KB

Line
1	/* $Id: DevVGA-SVGA-cmd.cpp 91928 2021-10-21 09:09:51Z vboxsync $ */
2	/** @file
3	* VMware SVGA device - implementation of VMSVGA commands.
4	*/
5
6	/*
7	* Copyright (C) 2013-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef IN_RING3
19	# error "DevVGA-SVGA-cmd.cpp is only for ring-3 code"
20	#endif
21
22
23	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
24	#include <iprt/mem.h>
25	#include <VBox/AssertGuest.h>
26	#include <VBox/log.h>
27	#include <VBox/vmm/pdmdev.h>
28	#include <VBoxVideo.h>
29
30	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
31	#include "DevVGA.h"
32
33	/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
34	#ifdef VBOX_WITH_VMSVGA3D
35	# include "DevVGA-SVGA3d.h"
36	#endif
37	#include "DevVGA-SVGA-internal.h"
38
39	#include <iprt/formats/bmp.h>
40	#include <stdio.h>
41
42	#if defined(LOG_ENABLED) \|\| defined(VBOX_STRICT)
43	# define SVGA_CASE_ID2STR(idx) case idx: return #idx
44
45	static const char *vmsvgaFifo3dCmdToString(SVGAFifo3dCmdId enmCmdId)
46	{
47	switch (enmCmdId)
48	{
49	SVGA_CASE_ID2STR(SVGA_3D_CMD_LEGACY_BASE);
50	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
51	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
52	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
53	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
54	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
55	SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
56	SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
57	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
58	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
59	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
60	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
61	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
62	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
63	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
64	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
65	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
66	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
67	SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
68	SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
69	SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
70	SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
71	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
72	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
73	SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
74	SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
75	SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
76	SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
77	SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
78	SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
79	SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
80	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
81	SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
82	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD4); /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
83	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD5); /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
84	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD6); /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
85	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD7); /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
86	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD8); /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
87	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD9); /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
88	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD10); /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
89	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD11); /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
90	SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
91	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
92	SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
93	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD1);
94	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
95	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD12); /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
96	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD13); /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
97	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD14); /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
98	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD15); /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
99	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD16); /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
100	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD17); /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
101	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
102	SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
103	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
104	SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
105	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
106	SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
107	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
108	SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
109	SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
110	SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
111	SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
112	SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
113	SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
114	SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
115	SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
116	SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
117	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
118	SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
119	SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
120	SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
121	SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
122	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
123	SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
124	SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
125	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
126	SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
127	SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
128	SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
129	SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
130	SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
131	SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
132	SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
133	SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
134	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
135	SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
136	SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
137	SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
138	SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
139	SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
140	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
141	SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
142	SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
143	SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
144	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
145	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
146	SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
147	SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
148	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
149	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
150	SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
151	SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
152	SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
153	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
154	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
155	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
156	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
157	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
158	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
159	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
160	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
161	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
162	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
163	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
164	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
165	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
166	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
167	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
168	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
169	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
170	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
171	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
172	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
173	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
174	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
175	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
176	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
177	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
178	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
179	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
180	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
181	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
182	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
183	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
184	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
185	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
186	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
187	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
188	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
189	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
190	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRESENTBLT);
191	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
192	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
193	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
194	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
195	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
196	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
197	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
198	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
199	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
200	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
201	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
202	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
203	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
204	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
205	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
206	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
207	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
208	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
209	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
210	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
211	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
212	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
213	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
214	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
215	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
216	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
217	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
218	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
219	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
220	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
221	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
222	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
223	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
224	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
225	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
226	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
227	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
228	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
229	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
230	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
231	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
232	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
233	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET);
234	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET);
235	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET);
236	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
237	SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_COPY);
238	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED1);
239	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2);
240	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED3);
241	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED4);
242	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED5);
243	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED6);
244	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED7);
245	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED8);
246	SVGA_CASE_ID2STR(SVGA_3D_CMD_GROW_OTABLE);
247	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GROW_COTABLE);
248	SVGA_CASE_ID2STR(SVGA_3D_CMD_INTRA_SURFACE_COPY);
249	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V3);
250	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESOLVE_COPY);
251	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_RESOLVE_COPY);
252	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT_REGION);
253	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT);
254	SVGA_CASE_ID2STR(SVGA_3D_CMD_WHOLE_SURFACE_COPY);
255	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_UA_VIEW);
256	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_UA_VIEW);
257	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT);
258	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT);
259	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT);
260	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_UA_VIEWS);
261	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT);
262	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT);
263	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH);
264	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH_INDIRECT);
265	SVGA_CASE_ID2STR(SVGA_3D_CMD_WRITE_ZERO_SURFACE);
266	SVGA_CASE_ID2STR(SVGA_3D_CMD_HINT_ZERO_SURFACE);
267	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER);
268	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT);
269	SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
270	SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
271	SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
272	SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
273	SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
274	SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
275	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_1);
276	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_2);
277	SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4);
278	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS);
279	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_MIN_LOD);
280	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_3);
281	SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_4);
282	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2);
283	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB);
284	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_IFACE);
285	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT);
286	SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS);
287	SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER_IFACE);
288	SVGA_CASE_ID2STR(SVGA_3D_CMD_MAX);
289	SVGA_CASE_ID2STR(SVGA_3D_CMD_FUTURE_MAX);
290	}
291	return "UNKNOWN_3D";
292	}
293
294	/**
295	* FIFO command name lookup
296	*
297	* @returns FIFO command string or "UNKNOWN"
298	* @param u32Cmd FIFO command
299	*/
300	const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
301	{
302	switch (u32Cmd)
303	{
304	SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
305	SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
306	SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
307	SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
308	SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
309	SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
310	SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
311	SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
312	SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
313	SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
314	SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
315	SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
316	SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
317	SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
318	SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
319	SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
320	SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
321	SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
322	SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
323	SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
324	SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
325	SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
326	SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
327	SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
328	SVGA_CASE_ID2STR(SVGA_CMD_NOP);
329	SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
330	SVGA_CASE_ID2STR(SVGA_CMD_MAX);
331	default:
332	if ( u32Cmd >= SVGA_3D_CMD_BASE
333	&& u32Cmd < SVGA_3D_CMD_MAX)
334	return vmsvgaFifo3dCmdToString((SVGAFifo3dCmdId)u32Cmd);
335	}
336	return "UNKNOWN";
337	}
338	# undef SVGA_CASE_ID2STR
339	#endif /* LOG_ENABLED \|\| VBOX_STRICT */
340
341
342	/*
343	*
344	* Guest-Backed Objects (GBO).
345	*
346	*/
347
348	/**
349	* HC access handler for GBOs which require write protection, i.e. OTables, etc.
350	*
351	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
352	* @param pVM VM Handle.
353	* @param pVCpu The cross context CPU structure for the calling EMT.
354	* @param GCPhys The physical address the guest is writing to.
355	* @param pvPhys The HC mapping of that address.
356	* @param pvBuf What the guest is reading/writing.
357	* @param cbBuf How much it's reading/writing.
358	* @param enmAccessType The access type.
359	* @param enmOrigin Who is making the access.
360	* @param pvUser User argument.
361	*/
362	DECLCALLBACK(VBOXSTRICTRC)
363	vmsvgaR3GboAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
364	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
365	{
366	RT_NOREF(pVM, pVCpu, pvPhys, enmAccessType);
367
368	if (RT_LIKELY(enmOrigin == PGMACCESSORIGIN_DEVICE \|\| enmOrigin == PGMACCESSORIGIN_DEBUGGER))
369	return VINF_PGM_HANDLER_DO_DEFAULT;
370
371	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
372	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
373	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
374	PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
375
376	/*
377	* The guest is not allowed to access the memory.
378	* Set the error condition.
379	*/
380	ASMAtomicWriteBool(&pThis->svga.fBadGuest, true);
381
382	/* Try to find the GBO which the guest is accessing. */
383	char const *pszTarget = NULL;
384	for (uint32_t i = 0; i < RT_ELEMENTS(pSvgaR3State->aGboOTables) && !pszTarget; ++i)
385	{
386	PVMSVGAGBO pGbo = &pSvgaR3State->aGboOTables[i];
387	if (pGbo->cDescriptors)
388	{
389	for (uint32_t j = 0; j < pGbo->cDescriptors; ++j)
390	{
391	if ( GCPhys >= pGbo->paDescriptors[j].GCPhys
392	&& GCPhys < pGbo->paDescriptors[j].GCPhys + pGbo->paDescriptors[j].cPages * PAGE_SIZE)
393	{
394	switch (i)
395	{
396	case SVGA_OTABLE_MOB: pszTarget = "SVGA_OTABLE_MOB"; break;
397	case SVGA_OTABLE_SURFACE: pszTarget = "SVGA_OTABLE_SURFACE"; break;
398	case SVGA_OTABLE_CONTEXT: pszTarget = "SVGA_OTABLE_CONTEXT"; break;
399	case SVGA_OTABLE_SHADER: pszTarget = "SVGA_OTABLE_SHADER"; break;
400	case SVGA_OTABLE_SCREENTARGET: pszTarget = "SVGA_OTABLE_SCREENTARGET"; break;
401	case SVGA_OTABLE_DXCONTEXT: pszTarget = "SVGA_OTABLE_DXCONTEXT"; break;
402	default: pszTarget = "Unknown OTABLE"; break;
403	}
404	break;
405	}
406	}
407	}
408	}
409
410	LogRelMax(8, ("VMSVGA: invalid guest access to page %RGp, target %s:\n"
411	"%.*Rhxd\n",
412	GCPhys, pszTarget ? pszTarget : "unknown", RT_MIN(cbBuf, 256), pvBuf));
413
414	return VINF_PGM_HANDLER_DO_DEFAULT;
415	}
416
417
418	#ifdef VBOX_WITH_VMSVGA3D
419	static int vmsvgaR3GboCreate(PVMSVGAR3STATE pSvgaR3State, SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, bool fGCPhys64, bool fWriteProtected, PVMSVGAGBO pGbo)
420	{
421	ASSERT_GUEST_RETURN(sizeInBytes <= _128M, VERR_INVALID_PARAMETER); /** @todo Less than SVGA_REG_MOB_MAX_SIZE */
422
423	/*
424	* The 'baseAddress' is a page number and points to the 'root page' of the GBO.
425	* Content of the root page depends on the ptDepth value:
426	* SVGA3D_MOBFMT_PTDEPTH[64]_0 - the only data page;
427	* SVGA3D_MOBFMT_PTDEPTH[64]_1 - array of page numbers for data pages;
428	* SVGA3D_MOBFMT_PTDEPTH[64]_2 - array of page numbers for SVGA3D_MOBFMT_PTDEPTH[64]_1 pages.
429	* The code below extracts the page addresses of the GBO.
430	*/
431
432	/* Verify and normalize the ptDepth value. */
433	if (RT_LIKELY( ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0
434	\|\| ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1
435	\|\| ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2))
436	ASSERT_GUEST_RETURN(fGCPhys64, VERR_INVALID_PARAMETER);
437	else if ( ptDepth == SVGA3D_MOBFMT_PTDEPTH_0
438	\|\| ptDepth == SVGA3D_MOBFMT_PTDEPTH_1
439	\|\| ptDepth == SVGA3D_MOBFMT_PTDEPTH_2)
440	{
441	ASSERT_GUEST_RETURN(!fGCPhys64, VERR_INVALID_PARAMETER);
442	/* Shift ptDepth to the SVGA3D_MOBFMT_PTDEPTH64_x range. */
443	ptDepth = (SVGAMobFormat)(ptDepth + SVGA3D_MOBFMT_PTDEPTH64_0 - SVGA3D_MOBFMT_PTDEPTH_0);
444	}
445	else if (ptDepth == SVGA3D_MOBFMT_RANGE)
446	{ }
447	else
448	ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
449
450	uint32_t const cPPNsPerPage = X86_PAGE_SIZE / (fGCPhys64 ? sizeof(PPN64) : sizeof(PPN));
451
452	pGbo->cbTotal = sizeInBytes;
453	pGbo->cTotalPages = (sizeInBytes + X86_PAGE_SIZE - 1) >> X86_PAGE_SHIFT;
454
455	/* Allocate the maximum amount possible (everything non-continuous) */
456	PVMSVGAGBODESCRIPTOR paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAlloc(pGbo->cTotalPages * sizeof(VMSVGAGBODESCRIPTOR));
457	AssertReturn(paDescriptors, VERR_NO_MEMORY);
458
459	int rc = VINF_SUCCESS;
460	if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0)
461	{
462	ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages == 1,
463	RTMemFree(paDescriptors),
464	VERR_INVALID_PARAMETER);
465
466	RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
467	GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
468	paDescriptors[0].GCPhys = GCPhys;
469	paDescriptors[0].cPages = 1;
470	}
471	else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1)
472	{
473	ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage,
474	RTMemFree(paDescriptors),
475	VERR_INVALID_PARAMETER);
476
477	/* Read the root page. */
478	uint8_t au8RootPage[X86_PAGE_SIZE];
479	RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
480	rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPage, sizeof(au8RootPage));
481	if (RT_SUCCESS(rc))
482	{
483	PPN64 paPPN64 = (PPN64 )&au8RootPage[0];
484	PPN paPPN32 = (PPN )&au8RootPage[0];
485	for (uint32_t iPPN = 0; iPPN < pGbo->cTotalPages; ++iPPN)
486	{
487	GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
488	GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
489	paDescriptors[iPPN].GCPhys = GCPhys;
490	paDescriptors[iPPN].cPages = 1;
491	}
492	}
493	}
494	else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2)
495	{
496	ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage * cPPNsPerPage,
497	RTMemFree(paDescriptors),
498	VERR_INVALID_PARAMETER);
499
500	/* Read the Level2 root page. */
501	uint8_t au8RootPageLevel2[X86_PAGE_SIZE];
502	RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
503	rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPageLevel2, sizeof(au8RootPageLevel2));
504	if (RT_SUCCESS(rc))
505	{
506	uint32_t cPagesLeft = pGbo->cTotalPages;
507
508	PPN64 paPPN64Level2 = (PPN64 )&au8RootPageLevel2[0];
509	PPN paPPN32Level2 = (PPN )&au8RootPageLevel2[0];
510
511	uint32_t const cPPNsLevel2 = (pGbo->cTotalPages + cPPNsPerPage - 1) / cPPNsPerPage;
512	for (uint32_t iPPNLevel2 = 0; iPPNLevel2 < cPPNsLevel2; ++iPPNLevel2)
513	{
514	/* Read the Level1 root page. */
515	uint8_t au8RootPage[X86_PAGE_SIZE];
516	RTGCPHYS GCPhysLevel1 = (RTGCPHYS)(fGCPhys64 ? paPPN64Level2[iPPNLevel2] : paPPN32Level2[iPPNLevel2]) << X86_PAGE_SHIFT;
517	GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
518	rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhysLevel1, &au8RootPage, sizeof(au8RootPage));
519	if (RT_SUCCESS(rc))
520	{
521	PPN64 paPPN64 = (PPN64 )&au8RootPage[0];
522	PPN paPPN32 = (PPN )&au8RootPage[0];
523
524	uint32_t const cPPNs = RT_MIN(cPagesLeft, cPPNsPerPage);
525	for (uint32_t iPPN = 0; iPPN < cPPNs; ++iPPN)
526	{
527	GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
528	GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
529	paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].GCPhys = GCPhys;
530	paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].cPages = 1;
531	}
532	cPagesLeft -= cPPNs;
533	}
534	}
535	}
536	}
537	else if (ptDepth == SVGA3D_MOBFMT_RANGE)
538	{
539	RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
540	GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
541	paDescriptors[0].GCPhys = GCPhys;
542	paDescriptors[0].cPages = pGbo->cTotalPages;
543	}
544	else
545	{
546	AssertFailed();
547	return VERR_INTERNAL_ERROR; /* ptDepth should be already verified. */
548	}
549
550	/* Compress the descriptors. */
551	if (ptDepth != SVGA3D_MOBFMT_RANGE)
552	{
553	uint32_t iDescriptor = 0;
554	for (uint32_t i = 1; i < pGbo->cTotalPages; ++i)
555	{
556	/* Continuous physical memory? */
557	if (paDescriptors[i].GCPhys == paDescriptors[iDescriptor].GCPhys + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
558	{
559	Assert(paDescriptors[iDescriptor].cPages);
560	paDescriptors[iDescriptor].cPages++;
561	Log5Func(("Page %x GCPhys=%RGp successor\n", i, paDescriptors[i].GCPhys));
562	}
563	else
564	{
565	iDescriptor++;
566	paDescriptors[iDescriptor].GCPhys = paDescriptors[i].GCPhys;
567	paDescriptors[iDescriptor].cPages = 1;
568	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescriptors[iDescriptor].GCPhys));
569	}
570	}
571
572	pGbo->cDescriptors = iDescriptor + 1;
573	Log5Func(("Nr of descriptors %d\n", pGbo->cDescriptors));
574	}
575	else
576	pGbo->cDescriptors = 1;
577
578	if (RT_LIKELY(pGbo->cDescriptors < pGbo->cTotalPages))
579	{
580	pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemRealloc(paDescriptors, pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
581	AssertReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
582	}
583	else
584	pGbo->paDescriptors = paDescriptors;
585
586	#if 1 /// @todo PGMHandlerPhysicalRegister asserts deep in PGM code with enmKind of a page being out of range.
587	fWriteProtected = false;
588	#endif
589	if (fWriteProtected)
590	{
591	pGbo->fGboFlags \|= VMSVGAGBO_F_WRITE_PROTECTED;
592	for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
593	{
594	rc = PDMDevHlpPGMHandlerPhysicalRegister(pSvgaR3State->pDevIns,
595	pGbo->paDescriptors[i].GCPhys, pGbo->paDescriptors[i].GCPhys + pGbo->paDescriptors[i].cPages * PAGE_SIZE - 1,
596	pSvgaR3State->hGboAccessHandlerType, pSvgaR3State->pDevIns, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GBO");
597	AssertRC(rc);
598	}
599	}
600
601	return VINF_SUCCESS;
602	}
603
604
605	static void vmsvgaR3GboDestroy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
606	{
607	if (RT_LIKELY(VMSVGA_IS_GBO_CREATED(pGbo)))
608	{
609	if (pGbo->fGboFlags & VMSVGAGBO_F_WRITE_PROTECTED)
610	{
611	for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
612	{
613	int rc = PDMDevHlpPGMHandlerPhysicalDeregister(pSvgaR3State->pDevIns, pGbo->paDescriptors[i].GCPhys);
614	AssertRC(rc);
615	}
616	}
617	RTMemFree(pGbo->paDescriptors);
618	RT_ZERO(pGbo);
619	}
620	}
621
622	/** @todo static void vmsvgaR3GboWriteProtect(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, bool fWriteProtect) */
623
624	typedef enum VMSVGAGboTransferDirection
625	{
626	VMSVGAGboTransferDirection_Read,
627	VMSVGAGboTransferDirection_Write,
628	} VMSVGAGboTransferDirection;
629
630	static int vmsvgaR3GboTransfer(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
631	uint32_t off, void *pvData, uint32_t cbData,
632	VMSVGAGboTransferDirection enmDirection)
633	{
634	//DEBUG_BREAKPOINT_TEST();
635	int rc = VINF_SUCCESS;
636	uint8_t pu8CurrentHost = (uint8_t )pvData;
637
638	/* Find the right descriptor */
639	PCVMSVGAGBODESCRIPTOR const paDescriptors = pGbo->paDescriptors;
640	uint32_t iDescriptor = 0; /* Index in the descriptor array. */
641	uint32_t offDescriptor = 0; /* GMR offset of the current descriptor. */
642	while (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE <= off)
643	{
644	offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
645	AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
646	++iDescriptor;
647	AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
648	}
649
650	while (cbData)
651	{
652	uint32_t cbToCopy;
653	if (off + cbData <= offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
654	cbToCopy = cbData;
655	else
656	{
657	cbToCopy = (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE - off);
658	AssertReturn(cbToCopy <= cbData, VERR_INVALID_PARAMETER);
659	}
660
661	RTGCPHYS const GCPhys = paDescriptors[iDescriptor].GCPhys + off - offDescriptor;
662	Log5Func(("%s phys=%RGp\n", (enmDirection == VMSVGAGboTransferDirection_Read) ? "READ" : "WRITE", GCPhys));
663
664	/*
665	* We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read\|Write] as the
666	* guest-side VMSVGA driver seems to allocate non-DMA (regular physical) addresses,
667	* see @bugref{9654#c75}.
668	*/
669	if (enmDirection == VMSVGAGboTransferDirection_Read)
670	rc = PDMDevHlpPhysRead(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
671	else
672	rc = PDMDevHlpPhysWrite(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
673	AssertRCBreak(rc);
674
675	cbData -= cbToCopy;
676	off += cbToCopy;
677	pu8CurrentHost += cbToCopy;
678
679	/* Go to the next descriptor if there's anything left. */
680	if (cbData)
681	{
682	offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
683	AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR);
684	++iDescriptor;
685	AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
686	}
687	}
688	return rc;
689	}
690
691
692	static int vmsvgaR3GboWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
693	uint32_t off, void const *pvData, uint32_t cbData)
694	{
695	return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
696	off, (void *)pvData, cbData,
697	VMSVGAGboTransferDirection_Write);
698	}
699
700
701	static int vmsvgaR3GboRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
702	uint32_t off, void *pvData, uint32_t cbData)
703	{
704	return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
705	off, pvData, cbData,
706	VMSVGAGboTransferDirection_Read);
707	}
708
709
710	static int vmsvgaR3GboBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, uint32_t cbValid)
711	{
712	int rc;
713
714	/* Just reread the data if pvHost has been allocated already. */
715	if (!(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED))
716	pGbo->pvHost = RTMemAllocZ(pGbo->cbTotal);
717
718	if (pGbo->pvHost)
719	{
720	cbValid = RT_MIN(cbValid, pGbo->cbTotal);
721	rc = vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, cbValid);
722	}
723	else
724	rc = VERR_NO_MEMORY;
725
726	if (RT_SUCCESS(rc))
727	pGbo->fGboFlags \|= VMSVGAGBO_F_HOST_BACKED;
728	else
729	{
730	RTMemFree(pGbo->pvHost);
731	pGbo->pvHost = NULL;
732	}
733	return rc;
734	}
735
736
737	static void vmsvgaR3GboBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
738	{
739	RT_NOREF(pSvgaR3State);
740	AssertReturnVoid(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED);
741	RTMemFree(pGbo->pvHost);
742	pGbo->pvHost = NULL;
743	pGbo->fGboFlags &= ~VMSVGAGBO_F_HOST_BACKED;
744	}
745
746
747	static int vmsvgaR3GboBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
748	{
749	AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
750	return vmsvgaR3GboWrite(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
751	}
752
753
754	static int vmsvgaR3GboBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
755	{
756	AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
757	return vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
758	}
759
760
761
762	/*
763	*
764	* Object Tables.
765	*
766	*/
767
768	static int vmsvgaR3OTableVerifyIndex(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
769	uint32_t idx, uint32_t cbEntry)
770	{
771	RT_NOREF(pSvgaR3State);
772
773	/* The table must exist and the index must be within the table. */
774	ASSERT_GUEST_RETURN(VMSVGA_IS_GBO_CREATED(pGboOTable), VERR_INVALID_PARAMETER);
775	ASSERT_GUEST_RETURN(idx < pGboOTable->cbTotal / cbEntry, VERR_INVALID_PARAMETER);
776	RT_UNTRUSTED_VALIDATED_FENCE();
777	return VINF_SUCCESS;
778	}
779
780
781	static int vmsvgaR3OTableRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
782	uint32_t idx, uint32_t cbEntry,
783	void *pvData, uint32_t cbData)
784	{
785	AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
786
787	int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
788	if (RT_SUCCESS(rc))
789	{
790	uint32_t const off = idx * cbEntry;
791	rc = vmsvgaR3GboRead(pSvgaR3State, pGboOTable, off, pvData, cbData);
792	}
793	return rc;
794	}
795
796	static int vmsvgaR3OTableWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
797	uint32_t idx, uint32_t cbEntry,
798	void const *pvData, uint32_t cbData)
799	{
800	AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
801
802	int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
803	if (RT_SUCCESS(rc))
804	{
805	uint32_t const off = idx * cbEntry;
806	rc = vmsvgaR3GboWrite(pSvgaR3State, pGboOTable, off, pvData, cbData);
807	}
808	return rc;
809	}
810
811
812	/*
813	*
814	* The guest's Memory OBjects (MOB).
815	*
816	*/
817
818	static int vmsvgaR3MobCreate(PVMSVGAR3STATE pSvgaR3State,
819	SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, SVGAMobId mobid,
820	bool fGCPhys64, PVMSVGAMOB pMob)
821	{
822	RT_ZERO(*pMob);
823
824	/* Update the entry in the pSvgaR3State->pGboOTableMob. */
825	SVGAOTableMobEntry entry;
826	entry.ptDepth = ptDepth;
827	entry.sizeInBytes = sizeInBytes;
828	entry.base = baseAddress;
829	int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
830	mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
831	if (RT_SUCCESS(rc))
832	{
833	/* Create the corresponding GBO. */
834	rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, fGCPhys64, /* fWriteProtected = */ false, &pMob->Gbo);
835	if (RT_SUCCESS(rc))
836	{
837	/* Add to the tree of known GBOs and the LRU list. */
838	pMob->Core.Key = mobid;
839	if (RTAvlU32Insert(&pSvgaR3State->MOBTree, &pMob->Core))
840	{
841	RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
842	return VINF_SUCCESS;
843	}
844
845	vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
846	}
847	}
848
849	return rc;
850	}
851
852
853	static int vmsvgaR3MobDestroy(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
854	{
855	/* Update the entry in the pSvgaR3State->pGboOTableMob. */
856	SVGAOTableMobEntry entry;
857	RT_ZERO(entry);
858	vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
859	mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
860
861	PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
862	if (pMob)
863	{
864	RTListNodeRemove(&pMob->nodeLRU);
865	vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
866	RTMemFree(pMob);
867	return VINF_SUCCESS;
868	}
869
870	return VERR_INVALID_PARAMETER;
871	}
872
873
874	static PVMSVGAMOB vmsvgaR3MobGet(PVMSVGAR3STATE pSvgaR3State, SVGAMobId RT_UNTRUSTED_GUEST mobid)
875	{
876	if (mobid == SVGA_ID_INVALID)
877	return NULL;
878
879	PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Get(&pSvgaR3State->MOBTree, mobid);
880	if (pMob)
881	{
882	/* Move to the head of the LRU list. */
883	RTListNodeRemove(&pMob->nodeLRU);
884	RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
885	}
886	else
887	ASSERT_GUEST_FAILED();
888
889	return pMob;
890	}
891
892
893	/** Create a host ring-3 pointer to the MOB data.
894	* Current approach is to allocate a host memory buffer and copy the guest MOB data if necessary.
895	* @param pSvgaR3State R3 device state.
896	* @param pMob The MOB.
897	* @param cbValid How many bytes of the guest backing memory contain valid data.
898	* @return VBox status.
899	*/
900	/** @todo uint32_t cbValid -> uint32_t offStart, uint32_t cbData */
901	int vmsvgaR3MobBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob, uint32_t cbValid)
902	{
903	AssertReturn(pMob, VERR_INVALID_PARAMETER);
904	return vmsvgaR3GboBackingStoreCreate(pSvgaR3State, &pMob->Gbo, cbValid);
905	}
906
907
908	void vmsvgaR3MobBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
909	{
910	if (pMob)
911	vmsvgaR3GboBackingStoreDelete(pSvgaR3State, &pMob->Gbo);
912	}
913
914
915	int vmsvgaR3MobBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
916	{
917	if (pMob)
918	return vmsvgaR3GboBackingStoreWriteToGuest(pSvgaR3State, &pMob->Gbo);
919	return VERR_INVALID_PARAMETER;
920	}
921
922
923	int vmsvgaR3MobBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
924	{
925	if (pMob)
926	return vmsvgaR3GboBackingStoreReadFromGuest(pSvgaR3State, &pMob->Gbo);
927	return VERR_INVALID_PARAMETER;
928	}
929
930
931	void *vmsvgaR3MobBackingStorePtr(PVMSVGAMOB pMob, uint32_t off)
932	{
933	if (pMob && (pMob->Gbo.fGboFlags & VMSVGAGBO_F_HOST_BACKED))
934	{
935	if (off <= pMob->Gbo.cbTotal)
936	return (uint8_t *)pMob->Gbo.pvHost + off;
937	}
938	return NULL;
939	}
940
941
942	int vmsvgaR3UpdateGBSurface(PVGASTATECC pThisCC, SVGA3dSurfaceImageId const pImageId, SVGA3dBox const pBox)
943	{
944	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
945
946	SVGAOTableSurfaceEntry entrySurface;
947	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
948	pImageId->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
949	if (RT_SUCCESS(rc))
950	{
951	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
952	if (pMob)
953	{
954	VMSVGA3D_MAPPED_SURFACE map;
955	rc = vmsvga3dSurfaceMap(pThisCC, pImageId, pBox, VMSVGA3D_SURFACE_MAP_WRITE, &map);
956	if (RT_SUCCESS(rc))
957	{
958	/* Copy MOB -> mapped surface. */
959	uint32_t offSrc = pBox->x * map.cbPixel
960	+ pBox->y * entrySurface.size.width * map.cbPixel
961	+ pBox->z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
962	uint8_t pu8Dst = (uint8_t )map.pvData;
963	for (uint32_t z = 0; z < pBox->d; ++z)
964	{
965	for (uint32_t y = 0; y < pBox->h; ++y)
966	{
967	rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pBox->w * map.cbPixel);
968	if (RT_FAILURE(rc))
969	break;
970
971	pu8Dst += map.cbRowPitch;
972	offSrc += entrySurface.size.width * map.cbPixel;
973	}
974
975	pu8Dst += map.cbDepthPitch;
976	offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
977	}
978
979	vmsvga3dSurfaceUnmap(pThisCC, pImageId, &map, /* fWritten= */ true);
980	}
981	}
982	else
983	rc = VERR_INVALID_STATE;
984	}
985
986	return rc;
987	}
988
989
990	int vmsvgaR3UpdateGBSurfaceEx(PVGASTATECC pThisCC, SVGA3dSurfaceImageId const pImageId, SVGA3dBox const pBoxDst, SVGA3dPoint const *pPtSrc)
991	{
992	/* pPtSrc must be verified by the caller. */
993	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
994
995	SVGAOTableSurfaceEntry entrySurface;
996	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
997	pImageId->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
998	if (RT_SUCCESS(rc))
999	{
1000	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1001	if (pMob)
1002	{
1003	VMSVGA3D_MAPPED_SURFACE map;
1004	rc = vmsvga3dSurfaceMap(pThisCC, pImageId, pBoxDst, VMSVGA3D_SURFACE_MAP_WRITE, &map);
1005	if (RT_SUCCESS(rc))
1006	{
1007	/* Copy MOB -> mapped surface. */
1008	uint32_t offSrc = pPtSrc->x * map.cbPixel
1009	+ pPtSrc->y * entrySurface.size.width * map.cbPixel
1010	+ pPtSrc->z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1011	uint8_t pu8Dst = (uint8_t )map.pvData;
1012	for (uint32_t z = 0; z < pBoxDst->d; ++z)
1013	{
1014	for (uint32_t y = 0; y < pBoxDst->h; ++y)
1015	{
1016	rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pBoxDst->w * map.cbPixel);
1017	if (RT_FAILURE(rc))
1018	break;
1019
1020	pu8Dst += map.cbRowPitch;
1021	offSrc += entrySurface.size.width * map.cbPixel;
1022	}
1023
1024	pu8Dst += map.cbDepthPitch;
1025	offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1026	}
1027
1028	vmsvga3dSurfaceUnmap(pThisCC, pImageId, &map, /* fWritten= */ true);
1029	}
1030	}
1031	else
1032	rc = VERR_INVALID_STATE;
1033	}
1034
1035	return rc;
1036	}
1037	#endif /* VBOX_WITH_VMSVGA3D */
1038
1039
1040	/*
1041	* Screen objects.
1042	*/
1043	VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
1044	{
1045	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1046	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
1047	&& pSVGAState
1048	&& pSVGAState->aScreens[idScreen].fDefined)
1049	{
1050	return &pSVGAState->aScreens[idScreen];
1051	}
1052	return NULL;
1053	}
1054
1055	void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
1056	{
1057	#ifdef VBOX_WITH_VMSVGA3D
1058	if (pThis->svga.f3DEnabled)
1059	{
1060	for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
1061	{
1062	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
1063	if (pScreen)
1064	vmsvga3dDestroyScreen(pThisCC, pScreen);
1065	}
1066	}
1067	#else
1068	RT_NOREF(pThis, pThisCC);
1069	#endif
1070	}
1071
1072
1073	/**
1074	* Copy a rectangle of pixels within guest VRAM.
1075	*/
1076	static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1077	uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1078	{
1079	if (!width \|\| !height)
1080	return; /* Nothing to do, don't even bother. */
1081
1082	/*
1083	* The guest VRAM (aka GFB) is considered to be a bitmap in the format
1084	* corresponding to the current display mode.
1085	*/
1086	uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1087	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1088	uint8_t const *pSrc;
1089	uint8_t *pDst;
1090	unsigned const cbRectWidth = width * cbPixel;
1091	unsigned uMaxOffset;
1092
1093	uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1094	if (uMaxOffset >= cbFrameBuffer)
1095	{
1096	Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1097	return; /* Just don't listen to a bad guest. */
1098	}
1099
1100	pSrc = pDst = pThisCC->pbVRam;
1101	pSrc += srcY * cbScanline + srcX * cbPixel;
1102	pDst += dstY * cbScanline + dstX * cbPixel;
1103
1104	if (srcY >= dstY)
1105	{
1106	/* Source below destination, copy top to bottom. */
1107	for (; height > 0; height--)
1108	{
1109	memmove(pDst, pSrc, cbRectWidth);
1110	pSrc += cbScanline;
1111	pDst += cbScanline;
1112	}
1113	}
1114	else
1115	{
1116	/* Source above destination, copy bottom to top. */
1117	pSrc += cbScanline * (height - 1);
1118	pDst += cbScanline * (height - 1);
1119	for (; height > 0; height--)
1120	{
1121	memmove(pDst, pSrc, cbRectWidth);
1122	pSrc -= cbScanline;
1123	pDst -= cbScanline;
1124	}
1125	}
1126	}
1127
1128
1129	/**
1130	* Common worker for changing the pointer shape.
1131	*
1132	* @param pThisCC The VGA/VMSVGA state for ring-3.
1133	* @param pSVGAState The VMSVGA ring-3 instance data.
1134	* @param fAlpha Whether there is alpha or not.
1135	* @param xHot Hotspot x coordinate.
1136	* @param yHot Hotspot y coordinate.
1137	* @param cx Width.
1138	* @param cy Height.
1139	* @param pbData Heap copy of the cursor data. Consumed.
1140	* @param cbData The size of the data.
1141	*/
1142	static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
1143	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
1144	{
1145	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
1146	#ifdef LOG_ENABLED
1147	if (LogIs2Enabled())
1148	{
1149	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
1150	if (!fAlpha)
1151	{
1152	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
1153	for (uint32_t y = 0; y < cy; y++)
1154	{
1155	Log2(("%3u:", y));
1156	uint8_t const pbLine = &pbData[y cbAndLine];
1157	for (uint32_t x = 0; x < cx; x += 8)
1158	{
1159	uint8_t b = pbLine[x / 8];
1160	char szByte[12];
1161	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
1162	szByte[1] = b & 0x40 ? '*' : ' ';
1163	szByte[2] = b & 0x20 ? '*' : ' ';
1164	szByte[3] = b & 0x10 ? '*' : ' ';
1165	szByte[4] = b & 0x08 ? '*' : ' ';
1166	szByte[5] = b & 0x04 ? '*' : ' ';
1167	szByte[6] = b & 0x02 ? '*' : ' ';
1168	szByte[7] = b & 0x01 ? '*' : ' ';
1169	szByte[8] = '\0';
1170	Log2(("%s", szByte));
1171	}
1172	Log2(("\n"));
1173	}
1174	}
1175
1176	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
1177	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
1178	for (uint32_t y = 0; y < cy; y++)
1179	{
1180	Log2(("%3u:", y));
1181	uint32_t const pu32Line = &pu32Xor[y cx];
1182	for (uint32_t x = 0; x < cx; x++)
1183	Log2((" %08x", pu32Line[x]));
1184	Log2(("\n"));
1185	}
1186	}
1187	#endif
1188
1189	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
1190	AssertRC(rc);
1191
1192	if (pSVGAState->Cursor.fActive)
1193	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
1194
1195	pSVGAState->Cursor.fActive = true;
1196	pSVGAState->Cursor.xHotspot = xHot;
1197	pSVGAState->Cursor.yHotspot = yHot;
1198	pSVGAState->Cursor.width = cx;
1199	pSVGAState->Cursor.height = cy;
1200	pSVGAState->Cursor.cbData = cbData;
1201	pSVGAState->Cursor.pData = pbData;
1202	}
1203
1204
1205	#ifdef VBOX_WITH_VMSVGA3D
1206
1207	/*
1208	* SVGA_3D_CMD_* handlers.
1209	*/
1210
1211
1212	/** SVGA_3D_CMD_SURFACE_DEFINE 1040, SVGA_3D_CMD_SURFACE_DEFINE_V2 1070
1213	*
1214	* @param pThisCC The VGA/VMSVGA state for the current context.
1215	* @param pCmd The VMSVGA command.
1216	* @param cMipLevelSizes Number of elements in the paMipLevelSizes array.
1217	* @param paMipLevelSizes Arrays of surface sizes for each face and miplevel.
1218	*/
1219	static void vmsvga3dCmdDefineSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineSurface_v2 const *pCmd,
1220	uint32_t cMipLevelSizes, SVGA3dSize *paMipLevelSizes)
1221	{
1222	ASSERT_GUEST_RETURN_VOID(pCmd->sid < SVGA3D_MAX_SURFACE_IDS);
1223	ASSERT_GUEST_RETURN_VOID(cMipLevelSizes >= 1);
1224	RT_UNTRUSTED_VALIDATED_FENCE();
1225
1226	/* Number of faces (cFaces) is specified as the number of the first non-zero elements in the 'face' array.
1227	* Since only plain surfaces (cFaces == 1) and cubemaps (cFaces == 6) are supported
1228	* (see also SVGA3dCmdDefineSurface definition in svga3d_reg.h), we ignore anything else.
1229	*/
1230	uint32_t cRemainingMipLevels = cMipLevelSizes;
1231	uint32_t cFaces = 0;
1232	for (uint32_t i = 0; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1233	{
1234	if (pCmd->face[i].numMipLevels == 0)
1235	break;
1236
1237	/* All SVGA3dSurfaceFace structures must have the same value of numMipLevels field */
1238	ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == pCmd->face[0].numMipLevels);
1239
1240	/* numMipLevels value can't be greater than the number of remaining elements in the paMipLevelSizes array. */
1241	ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels <= cRemainingMipLevels);
1242	cRemainingMipLevels -= pCmd->face[i].numMipLevels;
1243
1244	++cFaces;
1245	}
1246	for (uint32_t i = cFaces; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1247	ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == 0);
1248
1249	/* cFaces must be 6 for a cubemap and 1 otherwise. */
1250	ASSERT_GUEST_RETURN_VOID(cFaces == (uint32_t)((pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP) ? 6 : 1));
1251
1252	/* Sum of face[i].numMipLevels must be equal to cMipLevels. */
1253	ASSERT_GUEST_RETURN_VOID(cRemainingMipLevels == 0);
1254	RT_UNTRUSTED_VALIDATED_FENCE();
1255
1256	/* Verify paMipLevelSizes */
1257	uint32_t cWidth = paMipLevelSizes[0].width;
1258	uint32_t cHeight = paMipLevelSizes[0].height;
1259	uint32_t cDepth = paMipLevelSizes[0].depth;
1260	for (uint32_t i = 1; i < pCmd->face[0].numMipLevels; ++i)
1261	{
1262	cWidth >>= 1;
1263	if (cWidth == 0) cWidth = 1;
1264	cHeight >>= 1;
1265	if (cHeight == 0) cHeight = 1;
1266	cDepth >>= 1;
1267	if (cDepth == 0) cDepth = 1;
1268	for (uint32_t iFace = 0; iFace < cFaces; ++iFace)
1269	{
1270	uint32_t const iMipLevelSize = iFace * pCmd->face[0].numMipLevels + i;
1271	ASSERT_GUEST_RETURN_VOID( cWidth == paMipLevelSizes[iMipLevelSize].width
1272	&& cHeight == paMipLevelSizes[iMipLevelSize].height
1273	&& cDepth == paMipLevelSizes[iMipLevelSize].depth);
1274	}
1275	}
1276	RT_UNTRUSTED_VALIDATED_FENCE();
1277
1278	/* Create the surface. */
1279	vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1280	pCmd->multisampleCount, pCmd->autogenFilter,
1281	pCmd->face[0].numMipLevels, &paMipLevelSizes[0], /* fAllocMipLevels = */ true);
1282	}
1283
1284
1285	/* SVGA_3D_CMD_DEFINE_GB_MOB 1093 */
1286	static void vmsvga3dCmdDefineGBMob(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob const *pCmd)
1287	{
1288	DEBUG_BREAKPOINT_TEST();
1289	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1290
1291	ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1292
1293	/* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1294	/* Allocate a structure for the MOB. */
1295	PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1296	AssertPtrReturnVoid(pMob);
1297
1298	int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /fGCPhys64=/ false, pMob);
1299	if (RT_SUCCESS(rc))
1300	{
1301	return;
1302	}
1303
1304	AssertFailed();
1305
1306	RTMemFree(pMob);
1307	}
1308
1309
1310	/* SVGA_3D_CMD_DESTROY_GB_MOB 1094 */
1311	static void vmsvga3dCmdDestroyGBMob(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBMob const *pCmd)
1312	{
1313	//DEBUG_BREAKPOINT_TEST();
1314	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1315
1316	ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1317
1318	int rc = vmsvgaR3MobDestroy(pSvgaR3State, pCmd->mobid);
1319	if (RT_SUCCESS(rc))
1320	{
1321	return;
1322	}
1323
1324	AssertFailed();
1325	}
1326
1327
1328	/* SVGA_3D_CMD_DEFINE_GB_SURFACE 1097 */
1329	static void vmsvga3dCmdDefineGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface const *pCmd)
1330	{
1331	//DEBUG_BREAKPOINT_TEST();
1332	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1333
1334	/* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1335	SVGAOTableSurfaceEntry entry;
1336	RT_ZERO(entry);
1337	entry.format = pCmd->format;
1338	entry.surface1Flags = pCmd->surfaceFlags;
1339	entry.numMipLevels = pCmd->numMipLevels;
1340	entry.multisampleCount = pCmd->multisampleCount;
1341	entry.autogenFilter = pCmd->autogenFilter;
1342	entry.size = pCmd->size;
1343	entry.mobid = SVGA_ID_INVALID;
1344	// entry.arraySize = 0;
1345	// entry.mobPitch = 0;
1346	int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1347	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1348	if (RT_SUCCESS(rc))
1349	{
1350	/* Create the host surface. */
1351	vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1352	pCmd->multisampleCount, pCmd->autogenFilter,
1353	pCmd->numMipLevels, &pCmd->size, /* fAllocMipLevels = */ false);
1354	}
1355	}
1356
1357
1358	/* SVGA_3D_CMD_DESTROY_GB_SURFACE 1098 */
1359	static void vmsvga3dCmdDestroyGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBSurface const *pCmd)
1360	{
1361	//DEBUG_BREAKPOINT_TEST();
1362	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1363
1364	/* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1365	SVGAOTableSurfaceEntry entry;
1366	RT_ZERO(entry);
1367	entry.mobid = SVGA_ID_INVALID;
1368	vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1369	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1370
1371	vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
1372	}
1373
1374
1375	/* SVGA_3D_CMD_BIND_GB_SURFACE 1099 */
1376	static void vmsvga3dCmdBindGBSurface(PVGASTATECC pThisCC, SVGA3dCmdBindGBSurface const *pCmd)
1377	{
1378	//DEBUG_BREAKPOINT_TEST();
1379	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1380
1381	/* Assign the mobid to the surface. */
1382	int rc = VINF_SUCCESS;
1383	if (pCmd->mobid != SVGA_ID_INVALID)
1384	rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1385	pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1386	if (RT_SUCCESS(rc))
1387	{
1388	SVGAOTableSurfaceEntry entry;
1389	rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1390	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1391	if (RT_SUCCESS(rc))
1392	{
1393	entry.mobid = pCmd->mobid;
1394	rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1395	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1396	if (RT_SUCCESS(rc))
1397	{
1398	/* */
1399	}
1400	}
1401	}
1402	}
1403
1404
1405	static int vmsvga3dBmpWrite(const char pszFilename, VMSVGA3D_MAPPED_SURFACE const pMap)
1406	{
1407	if (pMap->cbPixel != 4)
1408	return VERR_NOT_SUPPORTED;
1409
1410	int const w = pMap->box.w;
1411	int const h = pMap->box.h;
1412
1413	const int cbBitmap = w * h * 4;
1414
1415	FILE *f = fopen(pszFilename, "wb");
1416	if (!f)
1417	return VERR_FILE_NOT_FOUND;
1418
1419	{
1420	BMPFILEHDR fileHdr;
1421	RT_ZERO(fileHdr);
1422	fileHdr.uType = BMP_HDR_MAGIC;
1423	fileHdr.cbFileSize = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR) + cbBitmap;
1424	fileHdr.offBits = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR);
1425
1426	BMPWIN3XINFOHDR coreHdr;
1427	RT_ZERO(coreHdr);
1428	coreHdr.cbSize = sizeof(coreHdr);
1429	coreHdr.uWidth = w;
1430	coreHdr.uHeight = -h;
1431	coreHdr.cPlanes = 1;
1432	coreHdr.cBits = 32;
1433	coreHdr.cbSizeImage = cbBitmap;
1434
1435	fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1436	fwrite(&coreHdr, 1, sizeof(coreHdr), f);
1437	}
1438
1439	if (pMap->cbPixel == 4)
1440	{
1441	const uint8_t s = (uint8_t )pMap->pvData;
1442	for (int32_t y = 0; y < h; ++y)
1443	{
1444	fwrite(s, 1, w * pMap->cbPixel, f);
1445
1446	s += pMap->cbRowPitch;
1447	}
1448	}
1449
1450	fclose(f);
1451
1452	return VINF_SUCCESS;
1453	}
1454
1455
1456	void vmsvga3dMapWriteBmpFile(VMSVGA3D_MAPPED_SURFACE const pMap, char const pszPrefix)
1457	{
1458	static int idxBitmap = 0;
1459	char *pszFilename = RTStrAPrintf2("bmp\\%s%d.bmp", pszPrefix, idxBitmap++);
1460	int rc = vmsvga3dBmpWrite(pszFilename, pMap);
1461	Log(("WriteBmpFile %s %Rrc\n", pszFilename, rc)); RT_NOREF(rc);
1462	RTStrFree(pszFilename);
1463	}
1464
1465
1466	static int vmsvgaR3TransferSurfaceLevel(PVGASTATECC pThisCC,
1467	PVMSVGAMOB pMob,
1468	SVGA3dSurfaceImageId const *pImage,
1469	SVGA3dBox const *pBox,
1470	SVGA3dTransferType enmTransfer)
1471	{
1472	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1473
1474	VMSVGA3D_SURFACE_MAP enmMapType;
1475	if (enmTransfer == SVGA3D_WRITE_HOST_VRAM)
1476	enmMapType = pBox
1477	? VMSVGA3D_SURFACE_MAP_WRITE
1478	: VMSVGA3D_SURFACE_MAP_WRITE_DISCARD;
1479	else if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1480	enmMapType = VMSVGA3D_SURFACE_MAP_READ;
1481	else
1482	AssertFailedReturn(VERR_INVALID_PARAMETER);
1483
1484	VMSGA3D_BOX_DIMENSIONS dims;
1485	int rc = vmsvga3dGetBoxDimensions(pThisCC, pImage, pBox, &dims);
1486	AssertRCReturn(rc, rc);
1487
1488	VMSVGA3D_MAPPED_SURFACE map;
1489	rc = vmsvga3dSurfaceMap(pThisCC, pImage, pBox, enmMapType, &map);
1490	if (RT_SUCCESS(rc))
1491	{
1492	/* Copy mapped surface <-> MOB. */
1493	uint8_t pu8Map = (uint8_t )map.pvData;
1494	uint32_t offMob = dims.offSubresource + dims.offBox;
1495	for (uint32_t z = 0; z < dims.cDepth; ++z)
1496	{
1497	for (uint32_t y = 0; y < dims.cyBlocks; ++y)
1498	{
1499	if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1500	rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1501	else
1502	rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1503	if (RT_FAILURE(rc))
1504	break;
1505
1506	pu8Map += map.cbRowPitch;
1507	offMob += dims.cbPitch;
1508	}
1509	}
1510
1511	// vmsvga3dMapWriteBmpFile(&map, "Dynamic");
1512
1513	bool const fWritten = (enmTransfer == SVGA3D_WRITE_HOST_VRAM);
1514	vmsvga3dSurfaceUnmap(pThisCC, pImage, &map, fWritten);
1515	}
1516
1517	return rc;
1518	}
1519
1520
1521	/* SVGA_3D_CMD_UPDATE_GB_IMAGE 1101 */
1522	static void vmsvga3dCmdUpdateGBImage(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBImage const *pCmd)
1523	{
1524	//DEBUG_BREAKPOINT_TEST();
1525	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1526
1527	LogFlowFunc(("sid=%u @%u,%u,%u %ux%ux%u\n",
1528	pCmd->image.sid, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
1529
1530	/*
1531	SVGA3dSurfaceFormat format;
1532	SVGA3dSurface1Flags surface1Flags;
1533	uint32 numMipLevels;
1534	uint32 multisampleCount;
1535	SVGA3dTextureFilter autogenFilter;
1536	SVGA3dSize size;
1537	SVGAMobId mobid;
1538	uint32 arraySize;
1539	uint32 mobPitch;
1540	SVGA3dSurface2Flags surface2Flags;
1541	uint8 multisamplePattern;
1542	uint8 qualityLevel;
1543	uint16 bufferByteStride;
1544	float minLOD;
1545	*/
1546
1547	/* "update a surface from its backing MOB." */
1548	SVGAOTableSurfaceEntry entrySurface;
1549	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1550	pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1551	if (RT_SUCCESS(rc))
1552	{
1553	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1554	if (pMob)
1555	{
1556	rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
1557	AssertRC(rc);
1558	}
1559	}
1560	}
1561
1562
1563	/* SVGA_3D_CMD_UPDATE_GB_SURFACE 1102 */
1564	static void vmsvga3dCmdUpdateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBSurface const *pCmd)
1565	{
1566	//DEBUG_BREAKPOINT_TEST();
1567	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1568
1569	LogFlowFunc(("sid=%u\n",
1570	pCmd->sid));
1571
1572	/* "update a surface from its backing MOB." */
1573	SVGAOTableSurfaceEntry entrySurface;
1574	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1575	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1576	if (RT_SUCCESS(rc))
1577	{
1578	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1579	if (pMob)
1580	{
1581	uint32 const arraySize = (entrySurface.surface1Flags & SVGA3D_SURFACE_CUBEMAP)
1582	? SVGA3D_MAX_SURFACE_FACES
1583	: RT_MAX(entrySurface.arraySize, 1);
1584	for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1585	{
1586	for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1587	{
1588	SVGA3dSurfaceImageId image;
1589	image.sid = pCmd->sid;
1590	image.face = iArray;
1591	image.mipmap = iMipmap;
1592
1593	rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_WRITE_HOST_VRAM);
1594	AssertRCBreak(rc);
1595	}
1596	}
1597	}
1598	}
1599	}
1600
1601
1602	/* SVGA_3D_CMD_READBACK_GB_IMAGE 1103 */
1603	static void vmsvga3dCmdReadbackGBImage(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBImage const *pCmd)
1604	{
1605	//DEBUG_BREAKPOINT_TEST();
1606	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1607
1608	LogFlowFunc(("sid=%u, face=%u, mipmap=%u\n",
1609	pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap));
1610
1611	/* Read a surface to its backing MOB. */
1612	SVGAOTableSurfaceEntry entrySurface;
1613	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1614	pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1615	if (RT_SUCCESS(rc))
1616	{
1617	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1618	if (pMob)
1619	{
1620	rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1621	AssertRC(rc);
1622	}
1623	}
1624	}
1625
1626
1627	/* SVGA_3D_CMD_READBACK_GB_SURFACE 1104 */
1628	static void vmsvga3dCmdReadbackGBSurface(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBSurface const *pCmd)
1629	{
1630	//DEBUG_BREAKPOINT_TEST();
1631	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1632
1633	LogFlowFunc(("sid=%u\n",
1634	pCmd->sid));
1635
1636	/* Read a surface to its backing MOB. */
1637	SVGAOTableSurfaceEntry entrySurface;
1638	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1639	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1640	if (RT_SUCCESS(rc))
1641	{
1642	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1643	if (pMob)
1644	{
1645	uint32 const arraySize = (entrySurface.surface1Flags & SVGA3D_SURFACE_CUBEMAP)
1646	? SVGA3D_MAX_SURFACE_FACES
1647	: RT_MAX(entrySurface.arraySize, 1);
1648	for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1649	{
1650	for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1651	{
1652	SVGA3dSurfaceImageId image;
1653	image.sid = pCmd->sid;
1654	image.face = iArray;
1655	image.mipmap = iMipmap;
1656
1657	rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1658	AssertRCBreak(rc);
1659	}
1660	}
1661	}
1662	}
1663	}
1664
1665
1666	/* SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105 */
1667	static void vmsvga3dCmdInvalidateGBImage(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBImage const *pCmd)
1668	{
1669	//DEBUG_BREAKPOINT_TEST();
1670	vmsvga3dSurfaceInvalidate(pThisCC, pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap);
1671	}
1672
1673
1674	/* SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106 */
1675	static void vmsvga3dCmdInvalidateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBSurface const *pCmd)
1676	{
1677	//DEBUG_BREAKPOINT_TEST();
1678	vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, SVGA_ID_INVALID, SVGA_ID_INVALID);
1679	}
1680
1681
1682	/* SVGA_3D_CMD_SET_OTABLE_BASE64 1115 */
1683	static void vmsvga3dCmdSetOTableBase64(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase64 const *pCmd)
1684	{
1685	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1686
1687	/*
1688	* Create a GBO for the table.
1689	*/
1690	PVMSVGAGBO pGbo;
1691	if (pCmd->type <= RT_ELEMENTS(pSvgaR3State->aGboOTables))
1692	{
1693	RT_UNTRUSTED_VALIDATED_FENCE();
1694	pGbo = &pSvgaR3State->aGboOTables[pCmd->type];
1695	}
1696	else
1697	{
1698	ASSERT_GUEST_FAILED();
1699	pGbo = NULL;
1700	}
1701
1702	if (pGbo)
1703	{
1704	/* Recreate. */
1705	vmsvgaR3GboDestroy(pSvgaR3State, pGbo);
1706	int rc = vmsvgaR3GboCreate(pSvgaR3State, pCmd->ptDepth, pCmd->baseAddress, pCmd->sizeInBytes, /fGCPhys64=/ true, /* fWriteProtected = */ true, pGbo);
1707	AssertRC(rc);
1708	}
1709	}
1710
1711
1712	/* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124 */
1713	static void vmsvga3dCmdDefineGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDefineGBScreenTarget const *pCmd)
1714	{
1715	//DEBUG_BREAKPOINT_TEST();
1716	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1717
1718	ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1719	ASSERT_GUEST_RETURN_VOID(pCmd->width > 0 && pCmd->width <= pThis->svga.u32MaxWidth); /* SVGA_REG_SCREENTARGET_MAX_WIDTH */
1720	ASSERT_GUEST_RETURN_VOID(pCmd->height > 0 && pCmd->height <= pThis->svga.u32MaxHeight); /* SVGA_REG_SCREENTARGET_MAX_HEIGHT */
1721	RT_UNTRUSTED_VALIDATED_FENCE();
1722
1723	/* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1724	SVGAOTableScreenTargetEntry entry;
1725	RT_ZERO(entry);
1726	entry.image.sid = SVGA_ID_INVALID;
1727	// entry.image.face = 0;
1728	// entry.image.mipmap = 0;
1729	entry.width = pCmd->width;
1730	entry.height = pCmd->height;
1731	entry.xRoot = pCmd->xRoot;
1732	entry.yRoot = pCmd->yRoot;
1733	entry.flags = pCmd->flags;
1734	entry.dpi = pCmd->dpi;
1735
1736	int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1737	pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1738	if (RT_SUCCESS(rc))
1739	{
1740	/* Screen objects and screen targets are similar, therefore we will use the same for both. */
1741	/** @todo Generic screen object/target interface. */
1742	VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1743	pScreen->fDefined = true;
1744	pScreen->fModified = true;
1745	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET
1746	\| (RT_BOOL(pCmd->flags & SVGA_STFLAG_PRIMARY) ? SVGA_SCREEN_IS_PRIMARY : 0);
1747	pScreen->idScreen = pCmd->stid;
1748
1749	pScreen->xOrigin = pCmd->xRoot;
1750	pScreen->yOrigin = pCmd->yRoot;
1751	pScreen->cWidth = pCmd->width;
1752	pScreen->cHeight = pCmd->height;
1753	pScreen->offVRAM = 0; /* Not applicable for screen targets, they use either a separate memory buffer or a host window. */
1754	pScreen->cbPitch = pCmd->width * 4;
1755	pScreen->cBpp = 32;
1756
1757	if (RT_LIKELY(pThis->svga.f3DEnabled))
1758	vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
1759
1760	if (!pScreen->pHwScreen)
1761	{
1762	/* System memory buffer. */
1763	pScreen->pvScreenBitmap = RTMemAllocZ(pScreen->cHeight * pScreen->cbPitch);
1764	}
1765
1766	pThis->svga.fGFBRegisters = false;
1767	vmsvgaR3ChangeMode(pThis, pThisCC);
1768	}
1769	}
1770
1771
1772	/* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125 */
1773	static void vmsvga3dCmdDestroyGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDestroyGBScreenTarget const *pCmd)
1774	{
1775	//DEBUG_BREAKPOINT_TEST();
1776	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1777
1778	ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1779	RT_UNTRUSTED_VALIDATED_FENCE();
1780
1781	/* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1782	SVGAOTableScreenTargetEntry entry;
1783	RT_ZERO(entry);
1784	int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1785	pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1786	if (RT_SUCCESS(rc))
1787	{
1788	/* Screen objects and screen targets are similar, therefore we will use the same for both. */
1789	/** @todo Generic screen object/target interface. */
1790	VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1791	pScreen->fModified = true;
1792	pScreen->fDefined = false;
1793	pScreen->idScreen = pCmd->stid;
1794
1795	if (RT_LIKELY(pThis->svga.f3DEnabled))
1796	vmsvga3dDestroyScreen(pThisCC, pScreen);
1797
1798	vmsvgaR3ChangeMode(pThis, pThisCC);
1799
1800	RTMemFree(pScreen->pvScreenBitmap);
1801	pScreen->pvScreenBitmap = NULL;
1802	}
1803	}
1804
1805
1806	/* SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126 */
1807	static void vmsvga3dCmdBindGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdBindGBScreenTarget const *pCmd)
1808	{
1809	//DEBUG_BREAKPOINT_TEST();
1810	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1811
1812	/* "Binding a surface to a Screen Target the same as flipping" */
1813
1814	ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1815	ASSERT_GUEST_RETURN_VOID(pCmd->image.face == 0 && pCmd->image.mipmap == 0);
1816	RT_UNTRUSTED_VALIDATED_FENCE();
1817
1818	/* Assign the surface to the screen target. */
1819	int rc = VINF_SUCCESS;
1820	if (pCmd->image.sid != SVGA_ID_INVALID)
1821	rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1822	pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE);
1823	if (RT_SUCCESS(rc))
1824	{
1825	SVGAOTableScreenTargetEntry entry;
1826	rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1827	pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1828	if (RT_SUCCESS(rc))
1829	{
1830	entry.image = pCmd->image;
1831	rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1832	pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1833	if (RT_SUCCESS(rc))
1834	{
1835	VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1836	rc = pSvgaR3State->pFuncsGBO->pfnScreenTargetBind(pThisCC, pScreen, pCmd->image.sid);
1837	AssertRC(rc);
1838	}
1839	}
1840	}
1841	}
1842
1843
1844	/* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127 */
1845	static void vmsvga3dCmdUpdateGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBScreenTarget const *pCmd)
1846	{
1847	//DEBUG_BREAKPOINT_TEST();
1848	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1849
1850	/* Update the screen target from its backing surface. */
1851	ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1852	RT_UNTRUSTED_VALIDATED_FENCE();
1853
1854	/* Get the screen target info. */
1855	SVGAOTableScreenTargetEntry entryScreenTarget;
1856	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1857	pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entryScreenTarget, sizeof(entryScreenTarget));
1858	if (RT_SUCCESS(rc))
1859	{
1860	ASSERT_GUEST_RETURN_VOID(entryScreenTarget.image.face == 0 && entryScreenTarget.image.mipmap == 0);
1861	RT_UNTRUSTED_VALIDATED_FENCE();
1862
1863	if (entryScreenTarget.image.sid != SVGA_ID_INVALID)
1864	{
1865	SVGAOTableSurfaceEntry entrySurface;
1866	rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1867	entryScreenTarget.image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1868	if (RT_SUCCESS(rc))
1869	{
1870	/* Copy entrySurface.mobid content to the screen target. */
1871	if (entrySurface.mobid != SVGA_ID_INVALID)
1872	{
1873	RT_UNTRUSTED_VALIDATED_FENCE();
1874	SVGA3dRect targetRect = pCmd->rect;
1875
1876	VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1877	if (pScreen->pHwScreen)
1878	{
1879	/* Copy the screen target surface to the backend's screen. */
1880	pSvgaR3State->pFuncsGBO->pfnScreenTargetUpdate(pThisCC, pScreen, &targetRect);
1881	}
1882	else if (pScreen->pvScreenBitmap)
1883	{
1884	/* Copy the screen target surface to the memory buffer. */
1885	VMSVGA3D_MAPPED_SURFACE map;
1886	rc = vmsvga3dSurfaceMap(pThisCC, &entryScreenTarget.image, NULL, VMSVGA3D_SURFACE_MAP_READ, &map);
1887	if (RT_SUCCESS(rc))
1888	{
1889	uint8_t const pu8Src = (uint8_t )map.pvData
1890	+ targetRect.x * map.cbPixel
1891	+ targetRect.y * map.cbRowPitch;
1892	uint8_t pu8Dst = (uint8_t )pScreen->pvScreenBitmap
1893	+ targetRect.x * map.cbPixel
1894	+ targetRect.y * map.box.w * map.cbPixel;
1895	for (uint32_t y = 0; y < targetRect.h; ++y)
1896	{
1897	memcpy(pu8Dst, pu8Src, targetRect.w * map.cbPixel);
1898
1899	pu8Src += map.cbRowPitch;
1900	pu8Dst += map.box.w * map.cbPixel;
1901	}
1902
1903	vmsvga3dSurfaceUnmap(pThisCC, &entryScreenTarget.image, &map, /* fWritten = */ false);
1904
1905	vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->rect.x, pCmd->rect.y, pCmd->rect.w, pCmd->rect.h);
1906	}
1907	else
1908	AssertFailed();
1909	}
1910	}
1911	}
1912	}
1913	}
1914	}
1915
1916
1917	/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134 */
1918	static void vmsvga3dCmdDefineGBSurface_v2(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v2 const *pCmd)
1919	{
1920	//DEBUG_BREAKPOINT_TEST();
1921	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1922
1923	/* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1924	SVGAOTableSurfaceEntry entry;
1925	RT_ZERO(entry);
1926	entry.format = pCmd->format;
1927	entry.surface1Flags = pCmd->surfaceFlags;
1928	entry.numMipLevels = pCmd->numMipLevels;
1929	entry.multisampleCount = pCmd->multisampleCount;
1930	entry.autogenFilter = pCmd->autogenFilter;
1931	entry.size = pCmd->size;
1932	entry.mobid = SVGA_ID_INVALID;
1933	entry.arraySize = pCmd->arraySize;
1934	// entry.mobPitch = 0;
1935	// ...
1936	Assert( pCmd->arraySize == 0
1937	\|\| pCmd->arraySize == 1
1938	\|\| (pCmd->arraySize == 6 && (pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP)));
1939	int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1940	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1941	if (RT_SUCCESS(rc))
1942	{
1943	/* Create the host surface. */
1944	/** @todo SVGAOTableSurfaceEntry as input parameter? */
1945	vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1946	pCmd->multisampleCount, pCmd->autogenFilter,
1947	pCmd->numMipLevels, &pCmd->size, /* fAllocMipLevels = */ false);
1948	}
1949	}
1950
1951
1952	/* SVGA_3D_CMD_DEFINE_GB_MOB64 1135 */
1953	static void vmsvga3dCmdDefineGBMob64(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob64 const *pCmd)
1954	{
1955	//DEBUG_BREAKPOINT_TEST();
1956	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1957
1958	ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1959
1960	/* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1961	/* Allocate a structure for the MOB. */
1962	PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1963	AssertPtrReturnVoid(pMob);
1964
1965	int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /fGCPhys64=/ true, pMob);
1966	if (RT_SUCCESS(rc))
1967	{
1968	return;
1969	}
1970
1971	RTMemFree(pMob);
1972	}
1973
1974
1975	/* SVGA_3D_CMD_DX_DEFINE_CONTEXT 1143 */
1976	static int vmsvga3dCmdDXDefineContext(PVGASTATECC pThisCC, SVGA3dCmdDXDefineContext const *pCmd, uint32_t cbCmd)
1977	{
1978	#ifdef VMSVGA3D_DX
1979	//DEBUG_BREAKPOINT_TEST();
1980	RT_NOREF(cbCmd);
1981
1982	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1983
1984	/* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
1985	SVGAOTableDXContextEntry entry;
1986	RT_ZERO(entry);
1987	entry.cid = pCmd->cid;
1988	entry.mobid = SVGA_ID_INVALID;
1989	int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1990	pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1991	if (RT_SUCCESS(rc))
1992	{
1993	/* Create the host context. */
1994	rc = vmsvga3dDXDefineContext(pThisCC, pCmd->cid);
1995	}
1996
1997	return rc;
1998	#else
1999	RT_NOREF(pThisCC, pCmd, cbCmd);
2000	return VERR_NOT_SUPPORTED;
2001	#endif
2002	}
2003
2004
2005	/* SVGA_3D_CMD_DX_DESTROY_CONTEXT 1144 */
2006	static int vmsvga3dCmdDXDestroyContext(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyContext const *pCmd, uint32_t cbCmd)
2007	{
2008	#ifdef VMSVGA3D_DX
2009	//DEBUG_BREAKPOINT_TEST();
2010	RT_NOREF(cbCmd);
2011
2012	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2013
2014	/* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
2015	SVGAOTableDXContextEntry entry;
2016	RT_ZERO(entry);
2017	vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2018	pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2019
2020	return vmsvga3dDXDestroyContext(pThisCC, pCmd->cid);
2021	#else
2022	RT_NOREF(pThisCC, pCmd, cbCmd);
2023	return VERR_NOT_SUPPORTED;
2024	#endif
2025	}
2026
2027
2028	/* SVGA_3D_CMD_DX_BIND_CONTEXT 1145 */
2029	static int vmsvga3dCmdDXBindContext(PVGASTATECC pThisCC, SVGA3dCmdDXBindContext const *pCmd, uint32_t cbCmd)
2030	{
2031	#ifdef VMSVGA3D_DX
2032	//DEBUG_BREAKPOINT_TEST();
2033	RT_NOREF(cbCmd);
2034
2035	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2036
2037	/* Assign a mobid to a cid. */
2038	int rc = VINF_SUCCESS;
2039	if (pCmd->mobid != SVGA_ID_INVALID)
2040	rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
2041	pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
2042	if (RT_SUCCESS(rc))
2043	{
2044	SVGAOTableDXContextEntry entry;
2045	rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2046	pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2047	if (RT_SUCCESS(rc))
2048	{
2049	SVGADXContextMobFormat *pSvgaDXContext = NULL;
2050	if (pCmd->mobid != entry.mobid && entry.mobid != SVGA_ID_INVALID)
2051	{
2052	/* Unbind notification to the DX backend. Copy the context data to the guest backing memory. */
2053	pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2054	if (pSvgaDXContext)
2055	{
2056	rc = vmsvga3dDXUnbindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2057	if (RT_SUCCESS(rc))
2058	{
2059	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2060	if (pMob)
2061	{
2062	rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2063	}
2064	}
2065
2066	RTMemFree(pSvgaDXContext);
2067	pSvgaDXContext = NULL;
2068	}
2069	}
2070
2071	if (pCmd->mobid != SVGA_ID_INVALID)
2072	{
2073	/* Bind a new context. Copy existing data from the guest backing memory. */
2074	if (pCmd->validContents)
2075	{
2076	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2077	if (pMob)
2078	{
2079	pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2080	if (pSvgaDXContext)
2081	{
2082	rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2083	if (RT_FAILURE(rc))
2084	{
2085	RTMemFree(pSvgaDXContext);
2086	pSvgaDXContext = NULL;
2087	}
2088	}
2089	}
2090	}
2091
2092	rc = vmsvga3dDXBindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2093
2094	RTMemFree(pSvgaDXContext);
2095	}
2096
2097	/* Update the object table. */
2098	entry.mobid = pCmd->mobid;
2099	rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2100	pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2101	}
2102	}
2103
2104	return rc;
2105	#else
2106	RT_NOREF(pThisCC, pCmd, cbCmd);
2107	return VERR_NOT_SUPPORTED;
2108	#endif
2109	}
2110
2111
2112	/* SVGA_3D_CMD_DX_READBACK_CONTEXT 1146 */
2113	static int vmsvga3dCmdDXReadbackContext(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackContext const *pCmd, uint32_t cbCmd)
2114	{
2115	#ifdef VMSVGA3D_DX
2116	//DEBUG_BREAKPOINT_TEST();
2117	RT_NOREF(cbCmd);
2118
2119	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2120
2121	/* "Request that the device flush the contents back into guest memory." */
2122	SVGAOTableDXContextEntry entry;
2123	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2124	pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2125	if (RT_SUCCESS(rc))
2126	{
2127	if (entry.mobid != SVGA_ID_INVALID)
2128	{
2129	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2130	if (pMob)
2131	{
2132	/* Get the content. */
2133	SVGADXContextMobFormat pSvgaDXContext = (SVGADXContextMobFormat )RTMemAlloc(sizeof(SVGADXContextMobFormat));
2134	if (pSvgaDXContext)
2135	{
2136	rc = vmsvga3dDXReadbackContext(pThisCC, pCmd->cid, pSvgaDXContext);
2137	if (RT_SUCCESS(rc))
2138	rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2139
2140	RTMemFree(pSvgaDXContext);
2141	}
2142	else
2143	rc = VERR_NO_MEMORY;
2144	}
2145	}
2146	}
2147
2148	return rc;
2149	#else
2150	RT_NOREF(pThisCC, pCmd, cbCmd);
2151	return VERR_NOT_SUPPORTED;
2152	#endif
2153	}
2154
2155
2156	/* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT 1147 */
2157	static int vmsvga3dCmdDXInvalidateContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateContext const *pCmd, uint32_t cbCmd)
2158	{
2159	#ifdef VMSVGA3D_DX
2160	DEBUG_BREAKPOINT_TEST();
2161	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2162	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2163	return vmsvga3dDXInvalidateContext(pThisCC, idDXContext);
2164	#else
2165	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2166	return VERR_NOT_SUPPORTED;
2167	#endif
2168	}
2169
2170
2171	/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER 1148 */
2172	static int vmsvga3dCmdDXSetSingleConstantBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSingleConstantBuffer const *pCmd, uint32_t cbCmd)
2173	{
2174	#ifdef VMSVGA3D_DX
2175	//DEBUG_BREAKPOINT_TEST();
2176	RT_NOREF(cbCmd);
2177	return vmsvga3dDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd);
2178	#else
2179	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2180	return VERR_NOT_SUPPORTED;
2181	#endif
2182	}
2183
2184
2185	/* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES 1149 */
2186	static int vmsvga3dCmdDXSetShaderResources(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderResources const *pCmd, uint32_t cbCmd)
2187	{
2188	#ifdef VMSVGA3D_DX
2189	//DEBUG_BREAKPOINT_TEST();
2190	SVGA3dShaderResourceViewId const paShaderResourceViewId = (SVGA3dShaderResourceViewId )&pCmd[1];
2191	uint32_t const cShaderResourceViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dShaderResourceViewId);
2192	return vmsvga3dDXSetShaderResources(pThisCC, idDXContext, pCmd, cShaderResourceViewId, paShaderResourceViewId);
2193	#else
2194	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2195	return VERR_NOT_SUPPORTED;
2196	#endif
2197	}
2198
2199
2200	/* SVGA_3D_CMD_DX_SET_SHADER 1150 */
2201	static int vmsvga3dCmdDXSetShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShader const *pCmd, uint32_t cbCmd)
2202	{
2203	#ifdef VMSVGA3D_DX
2204	//DEBUG_BREAKPOINT_TEST();
2205	RT_NOREF(cbCmd);
2206	return vmsvga3dDXSetShader(pThisCC, idDXContext, pCmd);
2207	#else
2208	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2209	return VERR_NOT_SUPPORTED;
2210	#endif
2211	}
2212
2213
2214	/* SVGA_3D_CMD_DX_SET_SAMPLERS 1151 */
2215	static int vmsvga3dCmdDXSetSamplers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSamplers const *pCmd, uint32_t cbCmd)
2216	{
2217	#ifdef VMSVGA3D_DX
2218	//DEBUG_BREAKPOINT_TEST();
2219	SVGA3dSamplerId const paSamplerId = (SVGA3dSamplerId )&pCmd[1];
2220	uint32_t const cSamplerId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSamplerId);
2221	return vmsvga3dDXSetSamplers(pThisCC, idDXContext, pCmd, cSamplerId, paSamplerId);
2222	#else
2223	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2224	return VERR_NOT_SUPPORTED;
2225	#endif
2226	}
2227
2228
2229	/* SVGA_3D_CMD_DX_DRAW 1152 */
2230	static int vmsvga3dCmdDXDraw(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDraw const *pCmd, uint32_t cbCmd)
2231	{
2232	#ifdef VMSVGA3D_DX
2233	//DEBUG_BREAKPOINT_TEST();
2234	RT_NOREF(cbCmd);
2235	return vmsvga3dDXDraw(pThisCC, idDXContext, pCmd);
2236	#else
2237	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2238	return VERR_NOT_SUPPORTED;
2239	#endif
2240	}
2241
2242
2243	/* SVGA_3D_CMD_DX_DRAW_INDEXED 1153 */
2244	static int vmsvga3dCmdDXDrawIndexed(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexed const *pCmd, uint32_t cbCmd)
2245	{
2246	#ifdef VMSVGA3D_DX
2247	//DEBUG_BREAKPOINT_TEST();
2248	RT_NOREF(cbCmd);
2249	return vmsvga3dDXDrawIndexed(pThisCC, idDXContext, pCmd);
2250	#else
2251	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2252	return VERR_NOT_SUPPORTED;
2253	#endif
2254	}
2255
2256
2257	/* SVGA_3D_CMD_DX_DRAW_INSTANCED 1154 */
2258	static int vmsvga3dCmdDXDrawInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstanced const *pCmd, uint32_t cbCmd)
2259	{
2260	#ifdef VMSVGA3D_DX
2261	//DEBUG_BREAKPOINT_TEST();
2262	RT_NOREF(cbCmd);
2263	return vmsvga3dDXDrawInstanced(pThisCC, idDXContext, pCmd);
2264	#else
2265	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2266	return VERR_NOT_SUPPORTED;
2267	#endif
2268	}
2269
2270
2271	/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED 1155 */
2272	static int vmsvga3dCmdDXDrawIndexedInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstanced const *pCmd, uint32_t cbCmd)
2273	{
2274	#ifdef VMSVGA3D_DX
2275	//DEBUG_BREAKPOINT_TEST();
2276	RT_NOREF(cbCmd);
2277	return vmsvga3dDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd);
2278	#else
2279	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2280	return VERR_NOT_SUPPORTED;
2281	#endif
2282	}
2283
2284
2285	/* SVGA_3D_CMD_DX_DRAW_AUTO 1156 */
2286	static int vmsvga3dCmdDXDrawAuto(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawAuto const *pCmd, uint32_t cbCmd)
2287	{
2288	#ifdef VMSVGA3D_DX
2289	DEBUG_BREAKPOINT_TEST();
2290	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2291	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2292	return vmsvga3dDXDrawAuto(pThisCC, idDXContext);
2293	#else
2294	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2295	return VERR_NOT_SUPPORTED;
2296	#endif
2297	}
2298
2299
2300	/* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT 1157 */
2301	static int vmsvga3dCmdDXSetInputLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetInputLayout const *pCmd, uint32_t cbCmd)
2302	{
2303	#ifdef VMSVGA3D_DX
2304	//DEBUG_BREAKPOINT_TEST();
2305	RT_NOREF(cbCmd);
2306	return vmsvga3dDXSetInputLayout(pThisCC, idDXContext, pCmd->elementLayoutId);
2307	#else
2308	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2309	return VERR_NOT_SUPPORTED;
2310	#endif
2311	}
2312
2313
2314	/* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS 1158 */
2315	static int vmsvga3dCmdDXSetVertexBuffers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVertexBuffers const *pCmd, uint32_t cbCmd)
2316	{
2317	#ifdef VMSVGA3D_DX
2318	//DEBUG_BREAKPOINT_TEST();
2319	SVGA3dVertexBuffer const paVertexBuffer = (SVGA3dVertexBuffer )&pCmd[1];
2320	uint32_t const cVertexBuffer = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dVertexBuffer);
2321	return vmsvga3dDXSetVertexBuffers(pThisCC, idDXContext, pCmd->startBuffer, cVertexBuffer, paVertexBuffer);
2322	#else
2323	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2324	return VERR_NOT_SUPPORTED;
2325	#endif
2326	}
2327
2328
2329	/* SVGA_3D_CMD_DX_SET_INDEX_BUFFER 1159 */
2330	static int vmsvga3dCmdDXSetIndexBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetIndexBuffer const *pCmd, uint32_t cbCmd)
2331	{
2332	#ifdef VMSVGA3D_DX
2333	//DEBUG_BREAKPOINT_TEST();
2334	RT_NOREF(cbCmd);
2335	return vmsvga3dDXSetIndexBuffer(pThisCC, idDXContext, pCmd);
2336	#else
2337	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2338	return VERR_NOT_SUPPORTED;
2339	#endif
2340	}
2341
2342
2343	/* SVGA_3D_CMD_DX_SET_TOPOLOGY 1160 */
2344	static int vmsvga3dCmdDXSetTopology(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetTopology const *pCmd, uint32_t cbCmd)
2345	{
2346	#ifdef VMSVGA3D_DX
2347	//DEBUG_BREAKPOINT_TEST();
2348	RT_NOREF(cbCmd);
2349	return vmsvga3dDXSetTopology(pThisCC, idDXContext, pCmd->topology);
2350	#else
2351	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2352	return VERR_NOT_SUPPORTED;
2353	#endif
2354	}
2355
2356
2357	/* SVGA_3D_CMD_DX_SET_RENDERTARGETS 1161 */
2358	static int vmsvga3dCmdDXSetRenderTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRenderTargets const *pCmd, uint32_t cbCmd)
2359	{
2360	#ifdef VMSVGA3D_DX
2361	//DEBUG_BREAKPOINT_TEST();
2362	SVGA3dRenderTargetViewId const paRenderTargetViewId = (SVGA3dRenderTargetViewId )&pCmd[1];
2363	uint32_t const cRenderTargetViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderTargetViewId);
2364	return vmsvga3dDXSetRenderTargets(pThisCC, idDXContext, pCmd->depthStencilViewId, cRenderTargetViewId, paRenderTargetViewId);
2365	#else
2366	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2367	return VERR_NOT_SUPPORTED;
2368	#endif
2369	}
2370
2371
2372	/* SVGA_3D_CMD_DX_SET_BLEND_STATE 1162 */
2373	static int vmsvga3dCmdDXSetBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetBlendState const *pCmd, uint32_t cbCmd)
2374	{
2375	#ifdef VMSVGA3D_DX
2376	//DEBUG_BREAKPOINT_TEST();
2377	RT_NOREF(cbCmd);
2378	return vmsvga3dDXSetBlendState(pThisCC, idDXContext, pCmd);
2379	#else
2380	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2381	return VERR_NOT_SUPPORTED;
2382	#endif
2383	}
2384
2385
2386	/* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE 1163 */
2387	static int vmsvga3dCmdDXSetDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDepthStencilState const *pCmd, uint32_t cbCmd)
2388	{
2389	#ifdef VMSVGA3D_DX
2390	//DEBUG_BREAKPOINT_TEST();
2391	RT_NOREF(cbCmd);
2392	return vmsvga3dDXSetDepthStencilState(pThisCC, idDXContext, pCmd);
2393	#else
2394	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2395	return VERR_NOT_SUPPORTED;
2396	#endif
2397	}
2398
2399
2400	/* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE 1164 */
2401	static int vmsvga3dCmdDXSetRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRasterizerState const *pCmd, uint32_t cbCmd)
2402	{
2403	#ifdef VMSVGA3D_DX
2404	//DEBUG_BREAKPOINT_TEST();
2405	RT_NOREF(cbCmd);
2406	return vmsvga3dDXSetRasterizerState(pThisCC, idDXContext, pCmd->rasterizerId);
2407	#else
2408	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2409	return VERR_NOT_SUPPORTED;
2410	#endif
2411	}
2412
2413
2414	/* SVGA_3D_CMD_DX_DEFINE_QUERY 1165 */
2415	static int vmsvga3dCmdDXDefineQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineQuery const *pCmd, uint32_t cbCmd)
2416	{
2417	#ifdef VMSVGA3D_DX
2418	DEBUG_BREAKPOINT_TEST();
2419	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2420	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2421	return vmsvga3dDXDefineQuery(pThisCC, idDXContext);
2422	#else
2423	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2424	return VERR_NOT_SUPPORTED;
2425	#endif
2426	}
2427
2428
2429	/* SVGA_3D_CMD_DX_DESTROY_QUERY 1166 */
2430	static int vmsvga3dCmdDXDestroyQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyQuery const *pCmd, uint32_t cbCmd)
2431	{
2432	#ifdef VMSVGA3D_DX
2433	DEBUG_BREAKPOINT_TEST();
2434	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2435	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2436	return vmsvga3dDXDestroyQuery(pThisCC, idDXContext);
2437	#else
2438	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2439	return VERR_NOT_SUPPORTED;
2440	#endif
2441	}
2442
2443
2444	/* SVGA_3D_CMD_DX_BIND_QUERY 1167 */
2445	static int vmsvga3dCmdDXBindQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindQuery const *pCmd, uint32_t cbCmd)
2446	{
2447	#ifdef VMSVGA3D_DX
2448	DEBUG_BREAKPOINT_TEST();
2449	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2450	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2451	return vmsvga3dDXBindQuery(pThisCC, idDXContext);
2452	#else
2453	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2454	return VERR_NOT_SUPPORTED;
2455	#endif
2456	}
2457
2458
2459	/* SVGA_3D_CMD_DX_SET_QUERY_OFFSET 1168 */
2460	static int vmsvga3dCmdDXSetQueryOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetQueryOffset const *pCmd, uint32_t cbCmd)
2461	{
2462	#ifdef VMSVGA3D_DX
2463	DEBUG_BREAKPOINT_TEST();
2464	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2465	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2466	return vmsvga3dDXSetQueryOffset(pThisCC, idDXContext);
2467	#else
2468	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2469	return VERR_NOT_SUPPORTED;
2470	#endif
2471	}
2472
2473
2474	/* SVGA_3D_CMD_DX_BEGIN_QUERY 1169 */
2475	static int vmsvga3dCmdDXBeginQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBeginQuery const *pCmd, uint32_t cbCmd)
2476	{
2477	#ifdef VMSVGA3D_DX
2478	DEBUG_BREAKPOINT_TEST();
2479	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2480	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2481	return vmsvga3dDXBeginQuery(pThisCC, idDXContext);
2482	#else
2483	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2484	return VERR_NOT_SUPPORTED;
2485	#endif
2486	}
2487
2488
2489	/* SVGA_3D_CMD_DX_END_QUERY 1170 */
2490	static int vmsvga3dCmdDXEndQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXEndQuery const *pCmd, uint32_t cbCmd)
2491	{
2492	#ifdef VMSVGA3D_DX
2493	DEBUG_BREAKPOINT_TEST();
2494	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2495	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2496	return vmsvga3dDXEndQuery(pThisCC, idDXContext);
2497	#else
2498	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2499	return VERR_NOT_SUPPORTED;
2500	#endif
2501	}
2502
2503
2504	/* SVGA_3D_CMD_DX_READBACK_QUERY 1171 */
2505	static int vmsvga3dCmdDXReadbackQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackQuery const *pCmd, uint32_t cbCmd)
2506	{
2507	#ifdef VMSVGA3D_DX
2508	DEBUG_BREAKPOINT_TEST();
2509	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2510	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2511	return vmsvga3dDXReadbackQuery(pThisCC, idDXContext);
2512	#else
2513	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2514	return VERR_NOT_SUPPORTED;
2515	#endif
2516	}
2517
2518
2519	/* SVGA_3D_CMD_DX_SET_PREDICATION 1172 */
2520	static int vmsvga3dCmdDXSetPredication(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPredication const *pCmd, uint32_t cbCmd)
2521	{
2522	#ifdef VMSVGA3D_DX
2523	DEBUG_BREAKPOINT_TEST();
2524	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2525	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2526	return vmsvga3dDXSetPredication(pThisCC, idDXContext);
2527	#else
2528	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2529	return VERR_NOT_SUPPORTED;
2530	#endif
2531	}
2532
2533
2534	/* SVGA_3D_CMD_DX_SET_SOTARGETS 1173 */
2535	static int vmsvga3dCmdDXSetSOTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSOTargets const *pCmd, uint32_t cbCmd)
2536	{
2537	#ifdef VMSVGA3D_DX
2538	//DEBUG_BREAKPOINT_TEST();
2539	SVGA3dSoTarget const paSoTarget = (SVGA3dSoTarget )&pCmd[1];
2540	uint32_t const cSoTarget = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSoTarget);
2541	return vmsvga3dDXSetSOTargets(pThisCC, idDXContext, cSoTarget, paSoTarget);
2542	#else
2543	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2544	return VERR_NOT_SUPPORTED;
2545	#endif
2546	}
2547
2548
2549	/* SVGA_3D_CMD_DX_SET_VIEWPORTS 1174 */
2550	static int vmsvga3dCmdDXSetViewports(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetViewports const *pCmd, uint32_t cbCmd)
2551	{
2552	#ifdef VMSVGA3D_DX
2553	//DEBUG_BREAKPOINT_TEST();
2554	SVGA3dViewport const paViewport = (SVGA3dViewport )&pCmd[1];
2555	uint32_t const cViewport = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dViewport);
2556	return vmsvga3dDXSetViewports(pThisCC, idDXContext, cViewport, paViewport);
2557	#else
2558	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2559	return VERR_NOT_SUPPORTED;
2560	#endif
2561	}
2562
2563
2564	/* SVGA_3D_CMD_DX_SET_SCISSORRECTS 1175 */
2565	static int vmsvga3dCmdDXSetScissorRects(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetScissorRects const *pCmd, uint32_t cbCmd)
2566	{
2567	#ifdef VMSVGA3D_DX
2568	//DEBUG_BREAKPOINT_TEST();
2569	SVGASignedRect const paRect = (SVGASignedRect )&pCmd[1];
2570	uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
2571	return vmsvga3dDXSetScissorRects(pThisCC, idDXContext, cRect, paRect);
2572	#else
2573	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2574	return VERR_NOT_SUPPORTED;
2575	#endif
2576	}
2577
2578
2579	/* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW 1176 */
2580	static int vmsvga3dCmdDXClearRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearRenderTargetView const *pCmd, uint32_t cbCmd)
2581	{
2582	#ifdef VMSVGA3D_DX
2583	//DEBUG_BREAKPOINT_TEST();
2584	RT_NOREF(cbCmd);
2585	return vmsvga3dDXClearRenderTargetView(pThisCC, idDXContext, pCmd);
2586	#else
2587	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2588	return VERR_NOT_SUPPORTED;
2589	#endif
2590	}
2591
2592
2593	/* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW 1177 */
2594	static int vmsvga3dCmdDXClearDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearDepthStencilView const *pCmd, uint32_t cbCmd)
2595	{
2596	#ifdef VMSVGA3D_DX
2597	//DEBUG_BREAKPOINT_TEST();
2598	RT_NOREF(cbCmd);
2599	return vmsvga3dDXClearDepthStencilView(pThisCC, idDXContext, pCmd);
2600	#else
2601	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2602	return VERR_NOT_SUPPORTED;
2603	#endif
2604	}
2605
2606
2607	/* SVGA_3D_CMD_DX_PRED_COPY_REGION 1178 */
2608	static int vmsvga3dCmdDXPredCopyRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopyRegion const *pCmd, uint32_t cbCmd)
2609	{
2610	#ifdef VMSVGA3D_DX
2611	//DEBUG_BREAKPOINT_TEST();
2612	RT_NOREF(cbCmd);
2613	return vmsvga3dDXPredCopyRegion(pThisCC, idDXContext, pCmd);
2614	#else
2615	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2616	return VERR_NOT_SUPPORTED;
2617	#endif
2618	}
2619
2620
2621	/* SVGA_3D_CMD_DX_PRED_COPY 1179 */
2622	static int vmsvga3dCmdDXPredCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopy const *pCmd, uint32_t cbCmd)
2623	{
2624	#ifdef VMSVGA3D_DX
2625	DEBUG_BREAKPOINT_TEST();
2626	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2627	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2628	return vmsvga3dDXPredCopy(pThisCC, idDXContext);
2629	#else
2630	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2631	return VERR_NOT_SUPPORTED;
2632	#endif
2633	}
2634
2635
2636	/* SVGA_3D_CMD_DX_PRESENTBLT 1180 */
2637	static int vmsvga3dCmdDXPresentBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPresentBlt const *pCmd, uint32_t cbCmd)
2638	{
2639	#ifdef VMSVGA3D_DX
2640	DEBUG_BREAKPOINT_TEST();
2641	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2642	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2643	return vmsvga3dDXPresentBlt(pThisCC, idDXContext);
2644	#else
2645	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2646	return VERR_NOT_SUPPORTED;
2647	#endif
2648	}
2649
2650
2651	/* SVGA_3D_CMD_DX_GENMIPS 1181 */
2652	static int vmsvga3dCmdDXGenMips(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGenMips const *pCmd, uint32_t cbCmd)
2653	{
2654	#ifdef VMSVGA3D_DX
2655	//DEBUG_BREAKPOINT_TEST();
2656	RT_NOREF(cbCmd);
2657	return vmsvga3dDXGenMips(pThisCC, idDXContext, pCmd);
2658	#else
2659	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2660	return VERR_NOT_SUPPORTED;
2661	#endif
2662	}
2663
2664
2665	/* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE 1182 */
2666	static int vmsvga3dCmdDXUpdateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXUpdateSubResource const *pCmd, uint32_t cbCmd)
2667	{
2668	#ifdef VMSVGA3D_DX
2669	//DEBUG_BREAKPOINT_TEST();
2670	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2671	RT_NOREF(cbCmd);
2672
2673	LogFlowFunc(("sid=%u, subResource=%u, box=%d,%d,%d %ux%ux%u\n",
2674	pCmd->sid, pCmd->subResource, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.z));
2675
2676	/* "Inform the device that the guest-contents have been updated." */
2677	SVGAOTableSurfaceEntry entrySurface;
2678	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2679	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2680	if (RT_SUCCESS(rc))
2681	{
2682	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2683	if (pMob)
2684	{
2685	uint32 const arraySize = (entrySurface.surface1Flags & SVGA3D_SURFACE_CUBEMAP)
2686	? SVGA3D_MAX_SURFACE_FACES
2687	: RT_MAX(entrySurface.arraySize, 1);
2688	ASSERT_GUEST_RETURN(pCmd->subResource < arraySize * entrySurface.numMipLevels, VERR_INVALID_PARAMETER);
2689	/* pCmd->box will be verified by the mapping function. */
2690	RT_UNTRUSTED_VALIDATED_FENCE();
2691
2692	/** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2693	SVGA3dSurfaceImageId image;
2694	image.sid = pCmd->sid;
2695	vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2696
2697	rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
2698	AssertRC(rc);
2699	}
2700	}
2701
2702	return rc;
2703	#else
2704	RT_NOREF(pThisCC, pCmd, cbCmd);
2705	return VERR_NOT_SUPPORTED;
2706	#endif
2707	}
2708
2709
2710	/* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE 1183 */
2711	static int vmsvga3dCmdDXReadbackSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackSubResource const *pCmd, uint32_t cbCmd)
2712	{
2713	#ifdef VMSVGA3D_DX
2714	//DEBUG_BREAKPOINT_TEST();
2715	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2716	RT_NOREF(cbCmd);
2717
2718	LogFlowFunc(("sid=%u, subResource=%u\n",
2719	pCmd->sid, pCmd->subResource));
2720
2721	/* "Request the device to flush the dirty contents into the guest." */
2722	SVGAOTableSurfaceEntry entrySurface;
2723	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2724	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2725	if (RT_SUCCESS(rc))
2726	{
2727	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2728	if (pMob)
2729	{
2730	uint32 const arraySize = (entrySurface.surface1Flags & SVGA3D_SURFACE_CUBEMAP)
2731	? SVGA3D_MAX_SURFACE_FACES
2732	: RT_MAX(entrySurface.arraySize, 1);
2733	ASSERT_GUEST_RETURN(pCmd->subResource < arraySize * entrySurface.numMipLevels, VERR_INVALID_PARAMETER);
2734	RT_UNTRUSTED_VALIDATED_FENCE();
2735
2736	/** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2737	SVGA3dSurfaceImageId image;
2738	image.sid = pCmd->sid;
2739	vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2740
2741	rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
2742	AssertRC(rc);
2743	}
2744	}
2745
2746	return rc;
2747	#else
2748	RT_NOREF(pThisCC, pCmd, cbCmd);
2749	return VERR_NOT_SUPPORTED;
2750	#endif
2751	}
2752
2753
2754	/* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE 1184 */
2755	static int vmsvga3dCmdDXInvalidateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXInvalidateSubResource const *pCmd, uint32_t cbCmd)
2756	{
2757	#ifdef VMSVGA3D_DX
2758	DEBUG_BREAKPOINT_TEST();
2759	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2760	RT_NOREF(cbCmd);
2761
2762	LogFlowFunc(("sid=%u, subResource=%u\n",
2763	pCmd->sid, pCmd->subResource));
2764
2765	/* "Notify the device that the contents can be lost." */
2766	SVGAOTableSurfaceEntry entrySurface;
2767	int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2768	pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2769	if (RT_SUCCESS(rc))
2770	{
2771	uint32_t iFace;
2772	uint32_t iMipmap;
2773	vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &iMipmap, &iFace);
2774	vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, iFace, iMipmap);
2775	}
2776
2777	return rc;
2778	#else
2779	RT_NOREF(pThisCC, pCmd, cbCmd);
2780	return VERR_NOT_SUPPORTED;
2781	#endif
2782	}
2783
2784
2785	/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW 1185 */
2786	static int vmsvga3dCmdDXDefineShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShaderResourceView const *pCmd, uint32_t cbCmd)
2787	{
2788	#ifdef VMSVGA3D_DX
2789	//DEBUG_BREAKPOINT_TEST();
2790	RT_NOREF(cbCmd);
2791	return vmsvga3dDXDefineShaderResourceView(pThisCC, idDXContext, pCmd);
2792	#else
2793	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2794	return VERR_NOT_SUPPORTED;
2795	#endif
2796	}
2797
2798
2799	/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW 1186 */
2800	static int vmsvga3dCmdDXDestroyShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShaderResourceView const *pCmd, uint32_t cbCmd)
2801	{
2802	#ifdef VMSVGA3D_DX
2803	//DEBUG_BREAKPOINT_TEST();
2804	RT_NOREF(cbCmd);
2805	return vmsvga3dDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd);
2806	#else
2807	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2808	return VERR_NOT_SUPPORTED;
2809	#endif
2810	}
2811
2812
2813	/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW 1187 */
2814	static int vmsvga3dCmdDXDefineRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRenderTargetView const *pCmd, uint32_t cbCmd)
2815	{
2816	#ifdef VMSVGA3D_DX
2817	//DEBUG_BREAKPOINT_TEST();
2818	RT_NOREF(cbCmd);
2819	return vmsvga3dDXDefineRenderTargetView(pThisCC, idDXContext, pCmd);
2820	#else
2821	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2822	return VERR_NOT_SUPPORTED;
2823	#endif
2824	}
2825
2826
2827	/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW 1188 */
2828	static int vmsvga3dCmdDXDestroyRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRenderTargetView const *pCmd, uint32_t cbCmd)
2829	{
2830	#ifdef VMSVGA3D_DX
2831	//DEBUG_BREAKPOINT_TEST();
2832	RT_NOREF(cbCmd);
2833	return vmsvga3dDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd);
2834	#else
2835	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2836	return VERR_NOT_SUPPORTED;
2837	#endif
2838	}
2839
2840
2841	/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW 1189 */
2842	static int vmsvga3dCmdDXDefineDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView const *pCmd, uint32_t cbCmd)
2843	{
2844	#ifdef VMSVGA3D_DX
2845	//DEBUG_BREAKPOINT_TEST();
2846	RT_NOREF(cbCmd);
2847	SVGA3dCmdDXDefineDepthStencilView_v2 cmd;
2848	cmd.depthStencilViewId = pCmd->depthStencilViewId;
2849	cmd.sid = pCmd->sid;
2850	cmd.format = pCmd->format;
2851	cmd.resourceDimension = pCmd->resourceDimension;
2852	cmd.mipSlice = pCmd->mipSlice;
2853	cmd.firstArraySlice = pCmd->firstArraySlice;
2854	cmd.arraySize = pCmd->arraySize;
2855	cmd.flags = 0;
2856	return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, &cmd);
2857	#else
2858	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2859	return VERR_NOT_SUPPORTED;
2860	#endif
2861	}
2862
2863
2864	/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW 1190 */
2865	static int vmsvga3dCmdDXDestroyDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilView const *pCmd, uint32_t cbCmd)
2866	{
2867	#ifdef VMSVGA3D_DX
2868	//DEBUG_BREAKPOINT_TEST();
2869	RT_NOREF(cbCmd);
2870	return vmsvga3dDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd);
2871	#else
2872	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2873	return VERR_NOT_SUPPORTED;
2874	#endif
2875	}
2876
2877
2878	/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT 1191 */
2879	static int vmsvga3dCmdDXDefineElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineElementLayout const *pCmd, uint32_t cbCmd)
2880	{
2881	#ifdef VMSVGA3D_DX
2882	//DEBUG_BREAKPOINT_TEST();
2883	SVGA3dInputElementDesc const paDesc = (SVGA3dInputElementDesc )&pCmd[1];
2884	uint32_t const cDesc = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dInputElementDesc);
2885	return vmsvga3dDXDefineElementLayout(pThisCC, idDXContext, pCmd->elementLayoutId, cDesc, paDesc);
2886	#else
2887	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2888	return VERR_NOT_SUPPORTED;
2889	#endif
2890	}
2891
2892
2893	/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT 1192 */
2894	static int vmsvga3dCmdDXDestroyElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyElementLayout const *pCmd, uint32_t cbCmd)
2895	{
2896	#ifdef VMSVGA3D_DX
2897	DEBUG_BREAKPOINT_TEST();
2898	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2899	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2900	return vmsvga3dDXDestroyElementLayout(pThisCC, idDXContext);
2901	#else
2902	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2903	return VERR_NOT_SUPPORTED;
2904	#endif
2905	}
2906
2907
2908	/* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE 1193 */
2909	static int vmsvga3dCmdDXDefineBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineBlendState const *pCmd, uint32_t cbCmd)
2910	{
2911	#ifdef VMSVGA3D_DX
2912	//DEBUG_BREAKPOINT_TEST();
2913	RT_NOREF(cbCmd);
2914	return vmsvga3dDXDefineBlendState(pThisCC, idDXContext, pCmd);
2915	#else
2916	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2917	return VERR_NOT_SUPPORTED;
2918	#endif
2919	}
2920
2921
2922	/* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE 1194 */
2923	static int vmsvga3dCmdDXDestroyBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyBlendState const *pCmd, uint32_t cbCmd)
2924	{
2925	#ifdef VMSVGA3D_DX
2926	DEBUG_BREAKPOINT_TEST();
2927	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2928	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2929	return vmsvga3dDXDestroyBlendState(pThisCC, idDXContext);
2930	#else
2931	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2932	return VERR_NOT_SUPPORTED;
2933	#endif
2934	}
2935
2936
2937	/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE 1195 */
2938	static int vmsvga3dCmdDXDefineDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilState const *pCmd, uint32_t cbCmd)
2939	{
2940	#ifdef VMSVGA3D_DX
2941	//DEBUG_BREAKPOINT_TEST();
2942	RT_NOREF(cbCmd);
2943	return vmsvga3dDXDefineDepthStencilState(pThisCC, idDXContext, pCmd);
2944	#else
2945	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2946	return VERR_NOT_SUPPORTED;
2947	#endif
2948	}
2949
2950
2951	/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE 1196 */
2952	static int vmsvga3dCmdDXDestroyDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilState const *pCmd, uint32_t cbCmd)
2953	{
2954	#ifdef VMSVGA3D_DX
2955	DEBUG_BREAKPOINT_TEST();
2956	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2957	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2958	return vmsvga3dDXDestroyDepthStencilState(pThisCC, idDXContext);
2959	#else
2960	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2961	return VERR_NOT_SUPPORTED;
2962	#endif
2963	}
2964
2965
2966	/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE 1197 */
2967	static int vmsvga3dCmdDXDefineRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRasterizerState const *pCmd, uint32_t cbCmd)
2968	{
2969	#ifdef VMSVGA3D_DX
2970	//DEBUG_BREAKPOINT_TEST();
2971	RT_NOREF(cbCmd);
2972	return vmsvga3dDXDefineRasterizerState(pThisCC, idDXContext, pCmd);
2973	#else
2974	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2975	return VERR_NOT_SUPPORTED;
2976	#endif
2977	}
2978
2979
2980	/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE 1198 */
2981	static int vmsvga3dCmdDXDestroyRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRasterizerState const *pCmd, uint32_t cbCmd)
2982	{
2983	#ifdef VMSVGA3D_DX
2984	DEBUG_BREAKPOINT_TEST();
2985	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2986	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2987	return vmsvga3dDXDestroyRasterizerState(pThisCC, idDXContext);
2988	#else
2989	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2990	return VERR_NOT_SUPPORTED;
2991	#endif
2992	}
2993
2994
2995	/* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE 1199 */
2996	static int vmsvga3dCmdDXDefineSamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineSamplerState const *pCmd, uint32_t cbCmd)
2997	{
2998	#ifdef VMSVGA3D_DX
2999	//DEBUG_BREAKPOINT_TEST();
3000	RT_NOREF(cbCmd);
3001	return vmsvga3dDXDefineSamplerState(pThisCC, idDXContext, pCmd);
3002	#else
3003	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3004	return VERR_NOT_SUPPORTED;
3005	#endif
3006	}
3007
3008
3009	/* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE 1200 */
3010	static int vmsvga3dCmdDXDestroySamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroySamplerState const *pCmd, uint32_t cbCmd)
3011	{
3012	#ifdef VMSVGA3D_DX
3013	DEBUG_BREAKPOINT_TEST();
3014	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3015	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3016	return vmsvga3dDXDestroySamplerState(pThisCC, idDXContext);
3017	#else
3018	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3019	return VERR_NOT_SUPPORTED;
3020	#endif
3021	}
3022
3023
3024	/* SVGA_3D_CMD_DX_DEFINE_SHADER 1201 */
3025	static int vmsvga3dCmdDXDefineShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShader const *pCmd, uint32_t cbCmd)
3026	{
3027	#ifdef VMSVGA3D_DX
3028	//DEBUG_BREAKPOINT_TEST();
3029	RT_NOREF(cbCmd);
3030	return vmsvga3dDXDefineShader(pThisCC, idDXContext, pCmd);
3031	#else
3032	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3033	return VERR_NOT_SUPPORTED;
3034	#endif
3035	}
3036
3037
3038	/* SVGA_3D_CMD_DX_DESTROY_SHADER 1202 */
3039	static int vmsvga3dCmdDXDestroyShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShader const *pCmd, uint32_t cbCmd)
3040	{
3041	#ifdef VMSVGA3D_DX
3042	//DEBUG_BREAKPOINT_TEST();
3043	RT_NOREF(cbCmd);
3044	return vmsvga3dDXDestroyShader(pThisCC, idDXContext, pCmd);
3045	#else
3046	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3047	return VERR_NOT_SUPPORTED;
3048	#endif
3049	}
3050
3051
3052	/* SVGA_3D_CMD_DX_BIND_SHADER 1203 */
3053	static int vmsvga3dCmdDXBindShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShader const *pCmd, uint32_t cbCmd)
3054	{
3055	#ifdef VMSVGA3D_DX
3056	//DEBUG_BREAKPOINT_TEST();
3057	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3058	RT_NOREF(idDXContext, cbCmd);
3059	/* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3060	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3061	return vmsvga3dDXBindShader(pThisCC, pCmd, pMob);
3062	#else
3063	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3064	return VERR_NOT_SUPPORTED;
3065	#endif
3066	}
3067
3068
3069	/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT 1204 */
3070	static int vmsvga3dCmdDXDefineStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutput const *pCmd, uint32_t cbCmd)
3071	{
3072	#ifdef VMSVGA3D_DX
3073	//DEBUG_BREAKPOINT_TEST();
3074	RT_NOREF(cbCmd);
3075	return vmsvga3dDXDefineStreamOutput(pThisCC, idDXContext, pCmd);
3076	#else
3077	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3078	return VERR_NOT_SUPPORTED;
3079	#endif
3080	}
3081
3082
3083	/* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT 1205 */
3084	static int vmsvga3dCmdDXDestroyStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyStreamOutput const *pCmd, uint32_t cbCmd)
3085	{
3086	#ifdef VMSVGA3D_DX
3087	DEBUG_BREAKPOINT_TEST();
3088	RT_NOREF(cbCmd);
3089	return vmsvga3dDXDestroyStreamOutput(pThisCC, idDXContext, pCmd);
3090	#else
3091	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3092	return VERR_NOT_SUPPORTED;
3093	#endif
3094	}
3095
3096
3097	/* SVGA_3D_CMD_DX_SET_STREAMOUTPUT 1206 */
3098	static int vmsvga3dCmdDXSetStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStreamOutput const *pCmd, uint32_t cbCmd)
3099	{
3100	#ifdef VMSVGA3D_DX
3101	//DEBUG_BREAKPOINT_TEST();
3102	RT_NOREF(cbCmd);
3103	return vmsvga3dDXSetStreamOutput(pThisCC, idDXContext, pCmd);
3104	#else
3105	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3106	return VERR_NOT_SUPPORTED;
3107	#endif
3108	}
3109
3110
3111	/* SVGA_3D_CMD_DX_SET_COTABLE 1207 */
3112	static int vmsvga3dCmdDXSetCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXSetCOTable const *pCmd, uint32_t cbCmd)
3113	{
3114	#ifdef VMSVGA3D_DX
3115	//DEBUG_BREAKPOINT_TEST();
3116	RT_NOREF(cbCmd);
3117	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3118	/* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3119	PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3120	return vmsvga3dDXSetCOTable(pThisCC, pCmd, pMob);
3121	#else
3122	RT_NOREF(pThisCC, pCmd, cbCmd);
3123	return VERR_NOT_SUPPORTED;
3124	#endif
3125	}
3126
3127
3128	/* SVGA_3D_CMD_DX_READBACK_COTABLE 1208 */
3129	static int vmsvga3dCmdDXReadbackCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackCOTable const *pCmd, uint32_t cbCmd)
3130	{
3131	#ifdef VMSVGA3D_DX
3132	//DEBUG_BREAKPOINT_TEST();
3133	RT_NOREF(idDXContext, cbCmd);
3134	return vmsvga3dDXReadbackCOTable(pThisCC, pCmd);
3135	#else
3136	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3137	return VERR_NOT_SUPPORTED;
3138	#endif
3139	}
3140
3141
3142	/* SVGA_3D_CMD_DX_BUFFER_COPY 1209 */
3143	static int vmsvga3dCmdDXBufferCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferCopy const *pCmd, uint32_t cbCmd)
3144	{
3145	#ifdef VMSVGA3D_DX
3146	DEBUG_BREAKPOINT_TEST();
3147	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3148	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3149	return vmsvga3dDXBufferCopy(pThisCC, idDXContext);
3150	#else
3151	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3152	return VERR_NOT_SUPPORTED;
3153	#endif
3154	}
3155
3156
3157	/* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER 1210 */
3158	static int vmsvga3dCmdDXTransferFromBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXTransferFromBuffer const *pCmd, uint32_t cbCmd)
3159	{
3160	#ifdef VMSVGA3D_DX
3161	//DEBUG_BREAKPOINT_TEST();
3162	RT_NOREF(cbCmd);
3163
3164	/* Plan:
3165	* - map the buffer;
3166	* - map the surface;
3167	* - copy from buffer map to the surface map.
3168	*/
3169
3170	int rc;
3171
3172	SVGA3dSurfaceImageId imageBuffer;
3173	imageBuffer.sid = pCmd->srcSid;
3174	imageBuffer.face = 0;
3175	imageBuffer.mipmap = 0;
3176
3177	SVGA3dSurfaceImageId imageSurface;
3178	imageSurface.sid = pCmd->destSid;
3179	rc = vmsvga3dCalcSurfaceMipmapAndFace(pThisCC, pCmd->destSid, pCmd->destSubResource, &imageSurface.mipmap, &imageSurface.face);
3180	AssertRCReturn(rc, rc);
3181
3182	/*
3183	* Map the buffer.
3184	*/
3185	VMSVGA3D_MAPPED_SURFACE mapBuffer;
3186	rc = vmsvga3dSurfaceMap(pThisCC, &imageBuffer, NULL, VMSVGA3D_SURFACE_MAP_READ, &mapBuffer);
3187	if (RT_SUCCESS(rc))
3188	{
3189	/*
3190	* Map the surface.
3191	*/
3192	VMSVGA3D_MAPPED_SURFACE mapSurface;
3193	rc = vmsvga3dSurfaceMap(pThisCC, &imageSurface, &pCmd->destBox, VMSVGA3D_SURFACE_MAP_WRITE, &mapSurface);
3194	if (RT_SUCCESS(rc))
3195	{
3196	/*
3197	* Copy the mapped buffer to the surface.
3198	*/
3199	uint8_t const pu8Buffer = (uint8_t )mapBuffer.pvData;
3200	uint32_t const cbBuffer = mapBuffer.box.w * mapBuffer.cbPixel;
3201
3202	if (pCmd->srcOffset <= cbBuffer)
3203	{
3204	RT_UNTRUSTED_VALIDATED_FENCE();
3205	uint8_t const *pu8BufferBegin = pu8Buffer;
3206	uint8_t const *pu8BufferEnd = pu8Buffer + cbBuffer;
3207
3208	pu8Buffer += pCmd->srcOffset;
3209
3210	uint8_t pu8Surface = (uint8_t )mapSurface.pvData;
3211
3212	uint32_t const cbWidth = mapSurface.box.w * mapSurface.cbPixel;
3213	for (uint32_t z = 0; z < mapSurface.box.d && RT_SUCCESS(rc); ++z)
3214	{
3215	uint8_t const *pu8BufferRow = pu8Buffer;
3216	uint8_t *pu8SurfaceRow = pu8Surface;
3217	for (uint32_t y = 0; y < mapSurface.box.h; ++y)
3218	{
3219	ASSERT_GUEST_STMT_BREAK( (uintptr_t)pu8BufferRow >= (uintptr_t)pu8BufferBegin
3220	&& (uintptr_t)pu8BufferRow < (uintptr_t)pu8BufferEnd
3221	&& (uintptr_t)(pu8BufferRow + cbWidth) > (uintptr_t)pu8BufferBegin
3222	&& (uintptr_t)(pu8BufferRow + cbWidth) <= (uintptr_t)pu8BufferEnd,
3223	rc = VERR_INVALID_PARAMETER);
3224
3225	memcpy(pu8SurfaceRow, pu8BufferRow, cbWidth);
3226
3227	pu8SurfaceRow += mapSurface.cbRowPitch;
3228	pu8BufferRow += pCmd->srcPitch;
3229	}
3230
3231	pu8Buffer += pCmd->srcSlicePitch;
3232	pu8Surface += mapSurface.cbDepthPitch;
3233	}
3234	}
3235	else
3236	ASSERT_GUEST_FAILED_STMT(rc = VERR_INVALID_PARAMETER);
3237
3238	vmsvga3dSurfaceUnmap(pThisCC, &imageSurface, &mapSurface, true);
3239	}
3240
3241	vmsvga3dSurfaceUnmap(pThisCC, &imageBuffer, &mapBuffer, false);
3242	}
3243
3244	return rc;
3245	#else
3246	RT_NOREF(pThisCC, pCmd, cbCmd);
3247	return VERR_NOT_SUPPORTED;
3248	#endif
3249	}
3250
3251
3252	/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK 1211 */
3253	static int vmsvga3dCmdDXSurfaceCopyAndReadback(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSurfaceCopyAndReadback const *pCmd, uint32_t cbCmd)
3254	{
3255	#ifdef VMSVGA3D_DX
3256	DEBUG_BREAKPOINT_TEST();
3257	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3258	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3259	return vmsvga3dDXSurfaceCopyAndReadback(pThisCC, idDXContext);
3260	#else
3261	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3262	return VERR_NOT_SUPPORTED;
3263	#endif
3264	}
3265
3266
3267	/* SVGA_3D_CMD_DX_MOVE_QUERY 1212 */
3268	static int vmsvga3dCmdDXMoveQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMoveQuery const *pCmd, uint32_t cbCmd)
3269	{
3270	#ifdef VMSVGA3D_DX
3271	DEBUG_BREAKPOINT_TEST();
3272	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3273	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3274	return vmsvga3dDXMoveQuery(pThisCC, idDXContext);
3275	#else
3276	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3277	return VERR_NOT_SUPPORTED;
3278	#endif
3279	}
3280
3281
3282	/* SVGA_3D_CMD_DX_BIND_ALL_QUERY 1213 */
3283	static int vmsvga3dCmdDXBindAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllQuery const *pCmd, uint32_t cbCmd)
3284	{
3285	#ifdef VMSVGA3D_DX
3286	DEBUG_BREAKPOINT_TEST();
3287	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3288	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3289	return vmsvga3dDXBindAllQuery(pThisCC, idDXContext);
3290	#else
3291	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3292	return VERR_NOT_SUPPORTED;
3293	#endif
3294	}
3295
3296
3297	/* SVGA_3D_CMD_DX_READBACK_ALL_QUERY 1214 */
3298	static int vmsvga3dCmdDXReadbackAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackAllQuery const *pCmd, uint32_t cbCmd)
3299	{
3300	#ifdef VMSVGA3D_DX
3301	DEBUG_BREAKPOINT_TEST();
3302	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3303	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3304	return vmsvga3dDXReadbackAllQuery(pThisCC, idDXContext);
3305	#else
3306	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3307	return VERR_NOT_SUPPORTED;
3308	#endif
3309	}
3310
3311
3312	/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER 1215 */
3313	static int vmsvga3dCmdDXPredTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredTransferFromBuffer const *pCmd, uint32_t cbCmd)
3314	{
3315	#ifdef VMSVGA3D_DX
3316	//DEBUG_BREAKPOINT_TEST();
3317	RT_NOREF(idDXContext, cbCmd);
3318
3319	/* This command is executed in a context: "The context is implied from the command buffer header."
3320	* However the device design allows to do the transfer without a context, so re-use context-less command handler.
3321	*/
3322	SVGA3dCmdDXTransferFromBuffer cmd;
3323	cmd.srcSid = pCmd->srcSid;
3324	cmd.srcOffset = pCmd->srcOffset;
3325	cmd.srcPitch = pCmd->srcPitch;
3326	cmd.srcSlicePitch = pCmd->srcSlicePitch;
3327	cmd.destSid = pCmd->destSid;
3328	cmd.destSubResource = pCmd->destSubResource;
3329	cmd.destBox = pCmd->destBox;
3330	return vmsvga3dCmdDXTransferFromBuffer(pThisCC, &cmd, sizeof(cmd));
3331	#else
3332	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3333	return VERR_NOT_SUPPORTED;
3334	#endif
3335	}
3336
3337
3338	/* SVGA_3D_CMD_DX_MOB_FENCE_64 1216 */
3339	static int vmsvga3dCmdDXMobFence64(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMobFence64 const *pCmd, uint32_t cbCmd)
3340	{
3341	#ifdef VMSVGA3D_DX
3342	DEBUG_BREAKPOINT_TEST();
3343	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3344	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3345	return vmsvga3dDXMobFence64(pThisCC, idDXContext);
3346	#else
3347	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3348	return VERR_NOT_SUPPORTED;
3349	#endif
3350	}
3351
3352
3353	/* SVGA_3D_CMD_DX_BIND_ALL_SHADER 1217 */
3354	static int vmsvga3dCmdDXBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllShader const *pCmd, uint32_t cbCmd)
3355	{
3356	#ifdef VMSVGA3D_DX
3357	DEBUG_BREAKPOINT_TEST();
3358	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3359	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3360	return vmsvga3dDXBindAllShader(pThisCC, idDXContext);
3361	#else
3362	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3363	return VERR_NOT_SUPPORTED;
3364	#endif
3365	}
3366
3367
3368	/* SVGA_3D_CMD_DX_HINT 1218 */
3369	static int vmsvga3dCmdDXHint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXHint const *pCmd, uint32_t cbCmd)
3370	{
3371	#ifdef VMSVGA3D_DX
3372	DEBUG_BREAKPOINT_TEST();
3373	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3374	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3375	return vmsvga3dDXHint(pThisCC, idDXContext);
3376	#else
3377	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3378	return VERR_NOT_SUPPORTED;
3379	#endif
3380	}
3381
3382
3383	/* SVGA_3D_CMD_DX_BUFFER_UPDATE 1219 */
3384	static int vmsvga3dCmdDXBufferUpdate(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferUpdate const *pCmd, uint32_t cbCmd)
3385	{
3386	#ifdef VMSVGA3D_DX
3387	DEBUG_BREAKPOINT_TEST();
3388	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3389	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3390	return vmsvga3dDXBufferUpdate(pThisCC, idDXContext);
3391	#else
3392	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3393	return VERR_NOT_SUPPORTED;
3394	#endif
3395	}
3396
3397
3398	/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET 1220 */
3399	static int vmsvga3dCmdDXSetVSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3400	{
3401	#ifdef VMSVGA3D_DX
3402	DEBUG_BREAKPOINT_TEST();
3403	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3404	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3405	return vmsvga3dDXSetVSConstantBufferOffset(pThisCC, idDXContext);
3406	#else
3407	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3408	return VERR_NOT_SUPPORTED;
3409	#endif
3410	}
3411
3412
3413	/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET 1221 */
3414	static int vmsvga3dCmdDXSetPSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3415	{
3416	#ifdef VMSVGA3D_DX
3417	DEBUG_BREAKPOINT_TEST();
3418	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3419	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3420	return vmsvga3dDXSetPSConstantBufferOffset(pThisCC, idDXContext);
3421	#else
3422	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3423	return VERR_NOT_SUPPORTED;
3424	#endif
3425	}
3426
3427
3428	/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET 1222 */
3429	static int vmsvga3dCmdDXSetGSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetGSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3430	{
3431	#ifdef VMSVGA3D_DX
3432	DEBUG_BREAKPOINT_TEST();
3433	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3434	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3435	return vmsvga3dDXSetGSConstantBufferOffset(pThisCC, idDXContext);
3436	#else
3437	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3438	return VERR_NOT_SUPPORTED;
3439	#endif
3440	}
3441
3442
3443	/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET 1223 */
3444	static int vmsvga3dCmdDXSetHSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetHSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3445	{
3446	#ifdef VMSVGA3D_DX
3447	DEBUG_BREAKPOINT_TEST();
3448	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3449	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3450	return vmsvga3dDXSetHSConstantBufferOffset(pThisCC, idDXContext);
3451	#else
3452	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3453	return VERR_NOT_SUPPORTED;
3454	#endif
3455	}
3456
3457
3458	/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET 1224 */
3459	static int vmsvga3dCmdDXSetDSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3460	{
3461	#ifdef VMSVGA3D_DX
3462	DEBUG_BREAKPOINT_TEST();
3463	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3464	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3465	return vmsvga3dDXSetDSConstantBufferOffset(pThisCC, idDXContext);
3466	#else
3467	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3468	return VERR_NOT_SUPPORTED;
3469	#endif
3470	}
3471
3472
3473	/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET 1225 */
3474	static int vmsvga3dCmdDXSetCSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3475	{
3476	#ifdef VMSVGA3D_DX
3477	DEBUG_BREAKPOINT_TEST();
3478	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3479	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3480	return vmsvga3dDXSetCSConstantBufferOffset(pThisCC, idDXContext);
3481	#else
3482	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3483	return VERR_NOT_SUPPORTED;
3484	#endif
3485	}
3486
3487
3488	/* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER 1226 */
3489	static int vmsvga3dCmdDXCondBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCondBindAllShader const *pCmd, uint32_t cbCmd)
3490	{
3491	#ifdef VMSVGA3D_DX
3492	DEBUG_BREAKPOINT_TEST();
3493	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3494	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3495	return vmsvga3dDXCondBindAllShader(pThisCC, idDXContext);
3496	#else
3497	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3498	return VERR_NOT_SUPPORTED;
3499	#endif
3500	}
3501
3502
3503	/* SVGA_3D_CMD_SCREEN_COPY 1227 */
3504	static int vmsvga3dCmdScreenCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdScreenCopy const *pCmd, uint32_t cbCmd)
3505	{
3506	#ifdef VMSVGA3D_DX
3507	DEBUG_BREAKPOINT_TEST();
3508	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3509	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3510	return vmsvga3dScreenCopy(pThisCC, idDXContext);
3511	#else
3512	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3513	return VERR_NOT_SUPPORTED;
3514	#endif
3515	}
3516
3517
3518	/* SVGA_3D_CMD_GROW_OTABLE 1236 */
3519	static int vmsvga3dCmdGrowOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdGrowOTable const *pCmd, uint32_t cbCmd)
3520	{
3521	#ifdef VMSVGA3D_DX
3522	DEBUG_BREAKPOINT_TEST();
3523	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3524	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3525	return vmsvga3dGrowOTable(pThisCC, idDXContext);
3526	#else
3527	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3528	return VERR_NOT_SUPPORTED;
3529	#endif
3530	}
3531
3532
3533	/* SVGA_3D_CMD_DX_GROW_COTABLE 1237 */
3534	static int vmsvga3dCmdDXGrowCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGrowCOTable const *pCmd, uint32_t cbCmd)
3535	{
3536	#ifdef VMSVGA3D_DX
3537	DEBUG_BREAKPOINT_TEST();
3538	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3539	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3540	return vmsvga3dDXGrowCOTable(pThisCC, idDXContext);
3541	#else
3542	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3543	return VERR_NOT_SUPPORTED;
3544	#endif
3545	}
3546
3547
3548	/* SVGA_3D_CMD_INTRA_SURFACE_COPY 1238 */
3549	static int vmsvga3dCmdIntraSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdIntraSurfaceCopy const *pCmd, uint32_t cbCmd)
3550	{
3551	#ifdef VMSVGA3D_DX
3552	DEBUG_BREAKPOINT_TEST();
3553	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3554	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3555	return vmsvga3dIntraSurfaceCopy(pThisCC, idDXContext);
3556	#else
3557	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3558	return VERR_NOT_SUPPORTED;
3559	#endif
3560	}
3561
3562
3563	/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 1239 */
3564	static int vmsvga3dCmdDefineGBSurface_v3(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v3 const *pCmd, uint32_t cbCmd)
3565	{
3566	#ifdef VMSVGA3D_DX
3567	DEBUG_BREAKPOINT_TEST();
3568	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3569	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3570	return vmsvga3dDefineGBSurface_v3(pThisCC, idDXContext);
3571	#else
3572	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3573	return VERR_NOT_SUPPORTED;
3574	#endif
3575	}
3576
3577
3578	/* SVGA_3D_CMD_DX_RESOLVE_COPY 1240 */
3579	static int vmsvga3dCmdDXResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXResolveCopy const *pCmd, uint32_t cbCmd)
3580	{
3581	#ifdef VMSVGA3D_DX
3582	DEBUG_BREAKPOINT_TEST();
3583	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3584	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3585	return vmsvga3dDXResolveCopy(pThisCC, idDXContext);
3586	#else
3587	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3588	return VERR_NOT_SUPPORTED;
3589	#endif
3590	}
3591
3592
3593	/* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY 1241 */
3594	static int vmsvga3dCmdDXPredResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredResolveCopy const *pCmd, uint32_t cbCmd)
3595	{
3596	#ifdef VMSVGA3D_DX
3597	DEBUG_BREAKPOINT_TEST();
3598	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3599	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3600	return vmsvga3dDXPredResolveCopy(pThisCC, idDXContext);
3601	#else
3602	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3603	return VERR_NOT_SUPPORTED;
3604	#endif
3605	}
3606
3607
3608	/* SVGA_3D_CMD_DX_PRED_CONVERT_REGION 1242 */
3609	static int vmsvga3dCmdDXPredConvertRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvertRegion const *pCmd, uint32_t cbCmd)
3610	{
3611	#ifdef VMSVGA3D_DX
3612	DEBUG_BREAKPOINT_TEST();
3613	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3614	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3615	return vmsvga3dDXPredConvertRegion(pThisCC, idDXContext);
3616	#else
3617	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3618	return VERR_NOT_SUPPORTED;
3619	#endif
3620	}
3621
3622
3623	/* SVGA_3D_CMD_DX_PRED_CONVERT 1243 */
3624	static int vmsvga3dCmdDXPredConvert(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvert const *pCmd, uint32_t cbCmd)
3625	{
3626	#ifdef VMSVGA3D_DX
3627	DEBUG_BREAKPOINT_TEST();
3628	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3629	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3630	return vmsvga3dDXPredConvert(pThisCC, idDXContext);
3631	#else
3632	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3633	return VERR_NOT_SUPPORTED;
3634	#endif
3635	}
3636
3637
3638	/* SVGA_3D_CMD_WHOLE_SURFACE_COPY 1244 */
3639	static int vmsvga3dCmdWholeSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWholeSurfaceCopy const *pCmd, uint32_t cbCmd)
3640	{
3641	#ifdef VMSVGA3D_DX
3642	DEBUG_BREAKPOINT_TEST();
3643	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3644	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3645	return vmsvga3dWholeSurfaceCopy(pThisCC, idDXContext);
3646	#else
3647	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3648	return VERR_NOT_SUPPORTED;
3649	#endif
3650	}
3651
3652
3653	/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW 1245 */
3654	static int vmsvga3dCmdDXDefineUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineUAView const *pCmd, uint32_t cbCmd)
3655	{
3656	#ifdef VMSVGA3D_DX
3657	DEBUG_BREAKPOINT_TEST();
3658	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3659	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3660	return vmsvga3dDXDefineUAView(pThisCC, idDXContext);
3661	#else
3662	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3663	return VERR_NOT_SUPPORTED;
3664	#endif
3665	}
3666
3667
3668	/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW 1246 */
3669	static int vmsvga3dCmdDXDestroyUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyUAView const *pCmd, uint32_t cbCmd)
3670	{
3671	#ifdef VMSVGA3D_DX
3672	DEBUG_BREAKPOINT_TEST();
3673	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3674	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3675	return vmsvga3dDXDestroyUAView(pThisCC, idDXContext);
3676	#else
3677	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3678	return VERR_NOT_SUPPORTED;
3679	#endif
3680	}
3681
3682
3683	/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT 1247 */
3684	static int vmsvga3dCmdDXClearUAViewUint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewUint const *pCmd, uint32_t cbCmd)
3685	{
3686	#ifdef VMSVGA3D_DX
3687	DEBUG_BREAKPOINT_TEST();
3688	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3689	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3690	return vmsvga3dDXClearUAViewUint(pThisCC, idDXContext);
3691	#else
3692	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3693	return VERR_NOT_SUPPORTED;
3694	#endif
3695	}
3696
3697
3698	/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT 1248 */
3699	static int vmsvga3dCmdDXClearUAViewFloat(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewFloat const *pCmd, uint32_t cbCmd)
3700	{
3701	#ifdef VMSVGA3D_DX
3702	DEBUG_BREAKPOINT_TEST();
3703	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3704	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3705	return vmsvga3dDXClearUAViewFloat(pThisCC, idDXContext);
3706	#else
3707	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3708	return VERR_NOT_SUPPORTED;
3709	#endif
3710	}
3711
3712
3713	/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT 1249 */
3714	static int vmsvga3dCmdDXCopyStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCopyStructureCount const *pCmd, uint32_t cbCmd)
3715	{
3716	#ifdef VMSVGA3D_DX
3717	DEBUG_BREAKPOINT_TEST();
3718	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3719	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3720	return vmsvga3dDXCopyStructureCount(pThisCC, idDXContext);
3721	#else
3722	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3723	return VERR_NOT_SUPPORTED;
3724	#endif
3725	}
3726
3727
3728	/* SVGA_3D_CMD_DX_SET_UA_VIEWS 1250 */
3729	static int vmsvga3dCmdDXSetUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetUAViews const *pCmd, uint32_t cbCmd)
3730	{
3731	#ifdef VMSVGA3D_DX
3732	DEBUG_BREAKPOINT_TEST();
3733	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3734	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3735	return vmsvga3dDXSetUAViews(pThisCC, idDXContext);
3736	#else
3737	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3738	return VERR_NOT_SUPPORTED;
3739	#endif
3740	}
3741
3742
3743	/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT 1251 */
3744	static int vmsvga3dCmdDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd, uint32_t cbCmd)
3745	{
3746	#ifdef VMSVGA3D_DX
3747	DEBUG_BREAKPOINT_TEST();
3748	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3749	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3750	return vmsvga3dDXDrawIndexedInstancedIndirect(pThisCC, idDXContext);
3751	#else
3752	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3753	return VERR_NOT_SUPPORTED;
3754	#endif
3755	}
3756
3757
3758	/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT 1252 */
3759	static int vmsvga3dCmdDXDrawInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstancedIndirect const *pCmd, uint32_t cbCmd)
3760	{
3761	#ifdef VMSVGA3D_DX
3762	DEBUG_BREAKPOINT_TEST();
3763	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3764	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3765	return vmsvga3dDXDrawInstancedIndirect(pThisCC, idDXContext);
3766	#else
3767	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3768	return VERR_NOT_SUPPORTED;
3769	#endif
3770	}
3771
3772
3773	/* SVGA_3D_CMD_DX_DISPATCH 1253 */
3774	static int vmsvga3dCmdDXDispatch(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatch const *pCmd, uint32_t cbCmd)
3775	{
3776	#ifdef VMSVGA3D_DX
3777	DEBUG_BREAKPOINT_TEST();
3778	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3779	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3780	return vmsvga3dDXDispatch(pThisCC, idDXContext);
3781	#else
3782	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3783	return VERR_NOT_SUPPORTED;
3784	#endif
3785	}
3786
3787
3788	/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT 1254 */
3789	static int vmsvga3dCmdDXDispatchIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatchIndirect const *pCmd, uint32_t cbCmd)
3790	{
3791	#ifdef VMSVGA3D_DX
3792	DEBUG_BREAKPOINT_TEST();
3793	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3794	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3795	return vmsvga3dDXDispatchIndirect(pThisCC, idDXContext);
3796	#else
3797	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3798	return VERR_NOT_SUPPORTED;
3799	#endif
3800	}
3801
3802
3803	/* SVGA_3D_CMD_WRITE_ZERO_SURFACE 1255 */
3804	static int vmsvga3dCmdWriteZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWriteZeroSurface const *pCmd, uint32_t cbCmd)
3805	{
3806	#ifdef VMSVGA3D_DX
3807	DEBUG_BREAKPOINT_TEST();
3808	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3809	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3810	return vmsvga3dWriteZeroSurface(pThisCC, idDXContext);
3811	#else
3812	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3813	return VERR_NOT_SUPPORTED;
3814	#endif
3815	}
3816
3817
3818	/* SVGA_3D_CMD_HINT_ZERO_SURFACE 1256 */
3819	static int vmsvga3dCmdHintZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdHintZeroSurface const *pCmd, uint32_t cbCmd)
3820	{
3821	#ifdef VMSVGA3D_DX
3822	DEBUG_BREAKPOINT_TEST();
3823	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3824	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3825	return vmsvga3dHintZeroSurface(pThisCC, idDXContext);
3826	#else
3827	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3828	return VERR_NOT_SUPPORTED;
3829	#endif
3830	}
3831
3832
3833	/* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER 1257 */
3834	static int vmsvga3dCmdDXTransferToBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferToBuffer const *pCmd, uint32_t cbCmd)
3835	{
3836	#ifdef VMSVGA3D_DX
3837	DEBUG_BREAKPOINT_TEST();
3838	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3839	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3840	return vmsvga3dDXTransferToBuffer(pThisCC, idDXContext);
3841	#else
3842	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3843	return VERR_NOT_SUPPORTED;
3844	#endif
3845	}
3846
3847
3848	/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT 1258 */
3849	static int vmsvga3dCmdDXSetStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStructureCount const *pCmd, uint32_t cbCmd)
3850	{
3851	#ifdef VMSVGA3D_DX
3852	DEBUG_BREAKPOINT_TEST();
3853	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3854	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3855	return vmsvga3dDXSetStructureCount(pThisCC, idDXContext);
3856	#else
3857	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3858	return VERR_NOT_SUPPORTED;
3859	#endif
3860	}
3861
3862
3863	/* SVGA_3D_CMD_LOGICOPS_BITBLT 1259 */
3864	static int vmsvga3dCmdLogicOpsBitBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsBitBlt const *pCmd, uint32_t cbCmd)
3865	{
3866	#ifdef VMSVGA3D_DX
3867	DEBUG_BREAKPOINT_TEST();
3868	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3869	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3870	return vmsvga3dLogicOpsBitBlt(pThisCC, idDXContext);
3871	#else
3872	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3873	return VERR_NOT_SUPPORTED;
3874	#endif
3875	}
3876
3877
3878	/* SVGA_3D_CMD_LOGICOPS_TRANSBLT 1260 */
3879	static int vmsvga3dCmdLogicOpsTransBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsTransBlt const *pCmd, uint32_t cbCmd)
3880	{
3881	#ifdef VMSVGA3D_DX
3882	DEBUG_BREAKPOINT_TEST();
3883	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3884	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3885	return vmsvga3dLogicOpsTransBlt(pThisCC, idDXContext);
3886	#else
3887	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3888	return VERR_NOT_SUPPORTED;
3889	#endif
3890	}
3891
3892
3893	/* SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1261 */
3894	static int vmsvga3dCmdLogicOpsStretchBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsStretchBlt const *pCmd, uint32_t cbCmd)
3895	{
3896	#ifdef VMSVGA3D_DX
3897	DEBUG_BREAKPOINT_TEST();
3898	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3899	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3900	return vmsvga3dLogicOpsStretchBlt(pThisCC, idDXContext);
3901	#else
3902	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3903	return VERR_NOT_SUPPORTED;
3904	#endif
3905	}
3906
3907
3908	/* SVGA_3D_CMD_LOGICOPS_COLORFILL 1262 */
3909	static int vmsvga3dCmdLogicOpsColorFill(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsColorFill const *pCmd, uint32_t cbCmd)
3910	{
3911	#ifdef VMSVGA3D_DX
3912	DEBUG_BREAKPOINT_TEST();
3913	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3914	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3915	return vmsvga3dLogicOpsColorFill(pThisCC, idDXContext);
3916	#else
3917	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3918	return VERR_NOT_SUPPORTED;
3919	#endif
3920	}
3921
3922
3923	/* SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1263 */
3924	static int vmsvga3dCmdLogicOpsAlphaBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsAlphaBlend const *pCmd, uint32_t cbCmd)
3925	{
3926	#ifdef VMSVGA3D_DX
3927	DEBUG_BREAKPOINT_TEST();
3928	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3929	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3930	return vmsvga3dLogicOpsAlphaBlend(pThisCC, idDXContext);
3931	#else
3932	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3933	return VERR_NOT_SUPPORTED;
3934	#endif
3935	}
3936
3937
3938	/* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1264 */
3939	static int vmsvga3dCmdLogicOpsClearTypeBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsClearTypeBlend const *pCmd, uint32_t cbCmd)
3940	{
3941	#ifdef VMSVGA3D_DX
3942	DEBUG_BREAKPOINT_TEST();
3943	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3944	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3945	return vmsvga3dLogicOpsClearTypeBlend(pThisCC, idDXContext);
3946	#else
3947	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3948	return VERR_NOT_SUPPORTED;
3949	#endif
3950	}
3951
3952
3953	/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 1267 */
3954	static int vmsvga3dCmdDefineGBSurface_v4(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v4 const *pCmd, uint32_t cbCmd)
3955	{
3956	#ifdef VMSVGA3D_DX
3957	DEBUG_BREAKPOINT_TEST();
3958	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3959	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3960	return vmsvga3dDefineGBSurface_v4(pThisCC, idDXContext);
3961	#else
3962	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3963	return VERR_NOT_SUPPORTED;
3964	#endif
3965	}
3966
3967
3968	/* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS 1268 */
3969	static int vmsvga3dCmdDXSetCSUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSUAViews const *pCmd, uint32_t cbCmd)
3970	{
3971	#ifdef VMSVGA3D_DX
3972	DEBUG_BREAKPOINT_TEST();
3973	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3974	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3975	return vmsvga3dDXSetCSUAViews(pThisCC, idDXContext);
3976	#else
3977	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3978	return VERR_NOT_SUPPORTED;
3979	#endif
3980	}
3981
3982
3983	/* SVGA_3D_CMD_DX_SET_MIN_LOD 1269 */
3984	static int vmsvga3dCmdDXSetMinLOD(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetMinLOD const *pCmd, uint32_t cbCmd)
3985	{
3986	#ifdef VMSVGA3D_DX
3987	DEBUG_BREAKPOINT_TEST();
3988	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3989	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3990	return vmsvga3dDXSetMinLOD(pThisCC, idDXContext);
3991	#else
3992	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3993	return VERR_NOT_SUPPORTED;
3994	#endif
3995	}
3996
3997
3998	/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 1272 */
3999	static int vmsvga3dCmdDXDefineDepthStencilView_v2(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd, uint32_t cbCmd)
4000	{
4001	#ifdef VMSVGA3D_DX
4002	//DEBUG_BREAKPOINT_TEST();
4003	RT_NOREF(cbCmd);
4004	return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, pCmd);
4005	#else
4006	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4007	return VERR_NOT_SUPPORTED;
4008	#endif
4009	}
4010
4011
4012	/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB 1273 */
4013	static int vmsvga3dCmdDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd, uint32_t cbCmd)
4014	{
4015	#ifdef VMSVGA3D_DX
4016	DEBUG_BREAKPOINT_TEST();
4017	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4018	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4019	return vmsvga3dDXDefineStreamOutputWithMob(pThisCC, idDXContext);
4020	#else
4021	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4022	return VERR_NOT_SUPPORTED;
4023	#endif
4024	}
4025
4026
4027	/* SVGA_3D_CMD_DX_SET_SHADER_IFACE 1274 */
4028	static int vmsvga3dCmdDXSetShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderIface const *pCmd, uint32_t cbCmd)
4029	{
4030	#ifdef VMSVGA3D_DX
4031	DEBUG_BREAKPOINT_TEST();
4032	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4033	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4034	return vmsvga3dDXSetShaderIface(pThisCC, idDXContext);
4035	#else
4036	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4037	return VERR_NOT_SUPPORTED;
4038	#endif
4039	}
4040
4041
4042	/* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT 1275 */
4043	static int vmsvga3dCmdDXBindStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindStreamOutput const *pCmd, uint32_t cbCmd)
4044	{
4045	#ifdef VMSVGA3D_DX
4046	DEBUG_BREAKPOINT_TEST();
4047	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4048	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4049	return vmsvga3dDXBindStreamOutput(pThisCC, idDXContext);
4050	#else
4051	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4052	return VERR_NOT_SUPPORTED;
4053	#endif
4054	}
4055
4056
4057	/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS 1276 */
4058	static int vmsvga3dCmdSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdSurfaceStretchBltNonMSToMS const *pCmd, uint32_t cbCmd)
4059	{
4060	#ifdef VMSVGA3D_DX
4061	DEBUG_BREAKPOINT_TEST();
4062	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4063	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4064	return vmsvga3dSurfaceStretchBltNonMSToMS(pThisCC, idDXContext);
4065	#else
4066	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4067	return VERR_NOT_SUPPORTED;
4068	#endif
4069	}
4070
4071
4072	/* SVGA_3D_CMD_DX_BIND_SHADER_IFACE 1277 */
4073	static int vmsvga3dCmdDXBindShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShaderIface const *pCmd, uint32_t cbCmd)
4074	{
4075	#ifdef VMSVGA3D_DX
4076	DEBUG_BREAKPOINT_TEST();
4077	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4078	RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4079	return vmsvga3dDXBindShaderIface(pThisCC, idDXContext);
4080	#else
4081	RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4082	return VERR_NOT_SUPPORTED;
4083	#endif
4084	}
4085
4086
4087	/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4088	* Check that the 3D command has at least a_cbMin of payload bytes after the
4089	* header. Will break out of the switch if it doesn't.
4090	*/
4091	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4092	if (1) { \
4093	AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
4094	RT_UNTRUSTED_VALIDATED_FENCE(); \
4095	} else do {} while (0)
4096
4097	# define VMSVGA_3D_CMD_NOTIMPL() \
4098	if (1) { \
4099	AssertMsgFailed(("Not implemented %d %s\n", enmCmdId, vmsvgaR3FifoCmdToString(enmCmdId))); \
4100	} else do {} while (0)
4101
4102	/** SVGA_3D_CMD_* handler.
4103	* This function parses the command and calls the corresponding command handler.
4104	*
4105	* @param pThis The shared VGA/VMSVGA state.
4106	* @param pThisCC The VGA/VMSVGA state for the current context.
4107	* @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
4108	* @param enmCmdId SVGA_3D_CMD_* command identifier.
4109	* @param cbCmd Size of the command in bytes.
4110	* @param pvCmd Pointer to the command.
4111	* @returns VBox status code if an error was detected parsing a command.
4112	*/
4113	int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, SVGAFifo3dCmdId enmCmdId, uint32_t cbCmd, void const *pvCmd)
4114	{
4115	if (enmCmdId > SVGA_3D_CMD_MAX)
4116	{
4117	LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
4118	ASSERT_GUEST_FAILED_RETURN(VERR_NOT_IMPLEMENTED);
4119	}
4120
4121	int rcParse = VINF_SUCCESS;
4122	PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
4123
4124	switch (enmCmdId)
4125	{
4126	case SVGA_3D_CMD_SURFACE_DEFINE:
4127	{
4128	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )pvCmd;
4129	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4130	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefine);
4131
4132	SVGA3dCmdDefineSurface_v2 cmd;
4133	cmd.sid = pCmd->sid;
4134	cmd.surfaceFlags = pCmd->surfaceFlags;
4135	cmd.format = pCmd->format;
4136	memcpy(cmd.face, pCmd->face, sizeof(cmd.face));
4137	cmd.multisampleCount = 0;
4138	cmd.autogenFilter = SVGA3D_TEX_FILTER_NONE;
4139
4140	uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4141	vmsvga3dCmdDefineSurface(pThisCC, &cmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4142	# ifdef DEBUG_GMR_ACCESS
4143	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4144	# endif
4145	break;
4146	}
4147
4148	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4149	{
4150	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )pvCmd;
4151	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4152	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefineV2);
4153
4154	uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4155	vmsvga3dCmdDefineSurface(pThisCC, pCmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4156	# ifdef DEBUG_GMR_ACCESS
4157	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4158	# endif
4159	break;
4160	}
4161
4162	case SVGA_3D_CMD_SURFACE_DESTROY:
4163	{
4164	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )pvCmd;
4165	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4166	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDestroy);
4167
4168	vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4169	break;
4170	}
4171
4172	case SVGA_3D_CMD_SURFACE_COPY:
4173	{
4174	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )pvCmd;
4175	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4176	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceCopy);
4177
4178	uint32_t const cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4179	vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4180	break;
4181	}
4182
4183	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4184	{
4185	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )pvCmd;
4186	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4187	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceStretchBlt);
4188
4189	vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4190	&pCmd->src, &pCmd->boxSrc, pCmd->mode);
4191	break;
4192	}
4193
4194	case SVGA_3D_CMD_SURFACE_DMA:
4195	{
4196	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )pvCmd;
4197	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4198	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDma);
4199
4200	uint64_t u64NanoTS = 0;
4201	if (LogRelIs3Enabled())
4202	u64NanoTS = RTTimeNanoTS();
4203	uint32_t const cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4204	STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4205	vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4206	cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4207	STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4208	if (LogRelIs3Enabled())
4209	{
4210	if (cCopyBoxes)
4211	{
4212	SVGA3dCopyBox pFirstBox = (SVGA3dCopyBox )(pCmd + 1);
4213	LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4214	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4215	pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4216	pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4217	}
4218	}
4219	break;
4220	}
4221
4222	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4223	{
4224	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )pvCmd;
4225	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4226	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceScreen);
4227
4228	static uint64_t u64FrameStartNanoTS = 0;
4229	static uint64_t u64ElapsedPerSecNano = 0;
4230	static int cFrames = 0;
4231	uint64_t u64NanoTS = 0;
4232	if (LogRelIs3Enabled())
4233	u64NanoTS = RTTimeNanoTS();
4234	uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4235	STAM_REL_PROFILE_START(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4236	vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4237	pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4238	STAM_REL_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4239	if (LogRelIs3Enabled())
4240	{
4241	uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
4242	u64ElapsedPerSecNano += u64ElapsedNano;
4243
4244	SVGASignedRect pFirstRect = cRects ? (SVGASignedRect )(pCmd + 1) : &pCmd->destRect;
4245	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4246	(u64ElapsedNano) / 1000ULL, cRects,
4247	pFirstRect->left, pFirstRect->top,
4248	pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4249
4250	++cFrames;
4251	if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
4252	{
4253	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
4254	cFrames, u64ElapsedPerSecNano / 1000ULL));
4255	u64FrameStartNanoTS = u64NanoTS;
4256	cFrames = 0;
4257	u64ElapsedPerSecNano = 0;
4258	}
4259	}
4260	break;
4261	}
4262
4263	case SVGA_3D_CMD_CONTEXT_DEFINE:
4264	{
4265	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )pvCmd;
4266	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4267	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDefine);
4268
4269	vmsvga3dContextDefine(pThisCC, pCmd->cid);
4270	break;
4271	}
4272
4273	case SVGA_3D_CMD_CONTEXT_DESTROY:
4274	{
4275	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )pvCmd;
4276	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4277	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDestroy);
4278
4279	vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4280	break;
4281	}
4282
4283	case SVGA_3D_CMD_SETTRANSFORM:
4284	{
4285	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )pvCmd;
4286	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4287	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTransform);
4288
4289	vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4290	break;
4291	}
4292
4293	case SVGA_3D_CMD_SETZRANGE:
4294	{
4295	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )pvCmd;
4296	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4297	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetZRange);
4298
4299	vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4300	break;
4301	}
4302
4303	case SVGA_3D_CMD_SETRENDERSTATE:
4304	{
4305	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )pvCmd;
4306	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4307	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderState);
4308
4309	uint32_t const cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4310	vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4311	break;
4312	}
4313
4314	case SVGA_3D_CMD_SETRENDERTARGET:
4315	{
4316	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )pvCmd;
4317	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4318	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderTarget);
4319
4320	vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4321	break;
4322	}
4323
4324	case SVGA_3D_CMD_SETTEXTURESTATE:
4325	{
4326	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )pvCmd;
4327	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4328	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTextureState);
4329
4330	uint32_t const cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4331	vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4332	break;
4333	}
4334
4335	case SVGA_3D_CMD_SETMATERIAL:
4336	{
4337	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )pvCmd;
4338	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4339	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetMaterial);
4340
4341	vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4342	break;
4343	}
4344
4345	case SVGA_3D_CMD_SETLIGHTDATA:
4346	{
4347	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )pvCmd;
4348	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4349	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightData);
4350
4351	vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4352	break;
4353	}
4354
4355	case SVGA_3D_CMD_SETLIGHTENABLED:
4356	{
4357	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )pvCmd;
4358	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4359	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightEnable);
4360
4361	vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4362	break;
4363	}
4364
4365	case SVGA_3D_CMD_SETVIEWPORT:
4366	{
4367	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )pvCmd;
4368	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4369	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetViewPort);
4370
4371	vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4372	break;
4373	}
4374
4375	case SVGA_3D_CMD_SETCLIPPLANE:
4376	{
4377	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )pvCmd;
4378	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4379	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetClipPlane);
4380
4381	vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4382	break;
4383	}
4384
4385	case SVGA_3D_CMD_CLEAR:
4386	{
4387	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )pvCmd;
4388	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4389	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dClear);
4390
4391	uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4392	vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4393	break;
4394	}
4395
4396	case SVGA_3D_CMD_PRESENT:
4397	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4398	{
4399	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )pvCmd;
4400	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4401	if (enmCmdId == SVGA_3D_CMD_PRESENT)
4402	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent);
4403	else
4404	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresentReadBack);
4405
4406	uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4407	STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4408	vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4409	STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4410	break;
4411	}
4412
4413	case SVGA_3D_CMD_SHADER_DEFINE:
4414	{
4415	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )pvCmd;
4416	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4417	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDefine);
4418
4419	uint32_t const cbData = (cbCmd - sizeof(*pCmd));
4420	vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4421	break;
4422	}
4423
4424	case SVGA_3D_CMD_SHADER_DESTROY:
4425	{
4426	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )pvCmd;
4427	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4428	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDestroy);
4429
4430	vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4431	break;
4432	}
4433
4434	case SVGA_3D_CMD_SET_SHADER:
4435	{
4436	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )pvCmd;
4437	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4438	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShader);
4439
4440	vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4441	break;
4442	}
4443
4444	case SVGA_3D_CMD_SET_SHADER_CONST:
4445	{
4446	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )pvCmd;
4447	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4448	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShaderConst);
4449
4450	uint32_t const cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4451	vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4452	break;
4453	}
4454
4455	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4456	{
4457	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )pvCmd;
4458	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4459	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDrawPrimitives);
4460
4461	ASSERT_GUEST_STMT_BREAK(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES, rcParse = VERR_INVALID_PARAMETER);
4462	ASSERT_GUEST_STMT_BREAK(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS, rcParse = VERR_INVALID_PARAMETER);
4463	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4464	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4465	ASSERT_GUEST_STMT_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd), rcParse = VERR_INVALID_PARAMETER);
4466
4467	uint32_t const cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4468	ASSERT_GUEST_STMT_BREAK(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls, rcParse = VERR_INVALID_PARAMETER);
4469	RT_UNTRUSTED_VALIDATED_FENCE();
4470
4471	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4472	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4473	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4474
4475	STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4476	vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4477	pNumRange, cVertexDivisor, pVertexDivisor);
4478	STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4479	break;
4480	}
4481
4482	case SVGA_3D_CMD_SETSCISSORRECT:
4483	{
4484	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )pvCmd;
4485	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4486	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetScissorRect);
4487
4488	vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4489	break;
4490	}
4491
4492	case SVGA_3D_CMD_BEGIN_QUERY:
4493	{
4494	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )pvCmd;
4495	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4496	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dBeginQuery);
4497
4498	vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4499	break;
4500	}
4501
4502	case SVGA_3D_CMD_END_QUERY:
4503	{
4504	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )pvCmd;
4505	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4506	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dEndQuery);
4507
4508	vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type);
4509	break;
4510	}
4511
4512	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4513	{
4514	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )pvCmd;
4515	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4516	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dWaitForQuery);
4517
4518	vmsvga3dQueryWait(pThisCC, pCmd->cid, pCmd->type, pThis, &pCmd->guestResult);
4519	break;
4520	}
4521
4522	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4523	{
4524	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )pvCmd;
4525	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4526	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dGenerateMipmaps);
4527
4528	vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4529	break;
4530	}
4531
4532	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4533	/* context id + surface id? */
4534	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dActivateSurface);
4535	break;
4536
4537	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4538	/* context id + surface id? */
4539	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDeactivateSurface);
4540	break;
4541
4542	/*
4543	*
4544	* VPGU10: SVGA_CAP_GBOBJECTS+ commands.
4545	*
4546	*/
4547	case SVGA_3D_CMD_SCREEN_DMA:
4548	{
4549	SVGA3dCmdScreenDMA pCmd = (SVGA3dCmdScreenDMA )pvCmd;
4550	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4551	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4552	break;
4553	}
4554
4555	case SVGA_3D_CMD_DEAD1:
4556	case SVGA_3D_CMD_DEAD2:
4557	case SVGA_3D_CMD_DEAD12: /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
4558	case SVGA_3D_CMD_DEAD13: /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
4559	case SVGA_3D_CMD_DEAD14: /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
4560	case SVGA_3D_CMD_DEAD15: /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
4561	case SVGA_3D_CMD_DEAD16: /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
4562	case SVGA_3D_CMD_DEAD17: /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
4563	{
4564	VMSVGA_3D_CMD_NOTIMPL();
4565	break;
4566	}
4567
4568	case SVGA_3D_CMD_SET_OTABLE_BASE:
4569	{
4570	SVGA3dCmdSetOTableBase pCmd = (SVGA3dCmdSetOTableBase )pvCmd;
4571	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4572	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4573	break;
4574	}
4575
4576	case SVGA_3D_CMD_READBACK_OTABLE:
4577	{
4578	SVGA3dCmdReadbackOTable pCmd = (SVGA3dCmdReadbackOTable )pvCmd;
4579	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4580	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4581	break;
4582	}
4583
4584	case SVGA_3D_CMD_DEFINE_GB_MOB:
4585	{
4586	SVGA3dCmdDefineGBMob pCmd = (SVGA3dCmdDefineGBMob )pvCmd;
4587	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4588	vmsvga3dCmdDefineGBMob(pThisCC, pCmd);
4589	break;
4590	}
4591
4592	case SVGA_3D_CMD_DESTROY_GB_MOB:
4593	{
4594	SVGA3dCmdDestroyGBMob pCmd = (SVGA3dCmdDestroyGBMob )pvCmd;
4595	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4596	vmsvga3dCmdDestroyGBMob(pThisCC, pCmd);
4597	break;
4598	}
4599
4600	case SVGA_3D_CMD_DEAD3:
4601	{
4602	VMSVGA_3D_CMD_NOTIMPL();
4603	break;
4604	}
4605
4606	case SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING:
4607	{
4608	SVGA3dCmdUpdateGBMobMapping pCmd = (SVGA3dCmdUpdateGBMobMapping )pvCmd;
4609	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4610	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4611	break;
4612	}
4613
4614	case SVGA_3D_CMD_DEFINE_GB_SURFACE:
4615	{
4616	SVGA3dCmdDefineGBSurface pCmd = (SVGA3dCmdDefineGBSurface )pvCmd;
4617	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4618	vmsvga3dCmdDefineGBSurface(pThisCC, pCmd);
4619	break;
4620	}
4621
4622	case SVGA_3D_CMD_DESTROY_GB_SURFACE:
4623	{
4624	SVGA3dCmdDestroyGBSurface pCmd = (SVGA3dCmdDestroyGBSurface )pvCmd;
4625	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4626	vmsvga3dCmdDestroyGBSurface(pThisCC, pCmd);
4627	break;
4628	}
4629
4630	case SVGA_3D_CMD_BIND_GB_SURFACE:
4631	{
4632	SVGA3dCmdBindGBSurface pCmd = (SVGA3dCmdBindGBSurface )pvCmd;
4633	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4634	vmsvga3dCmdBindGBSurface(pThisCC, pCmd);
4635	break;
4636	}
4637
4638	case SVGA_3D_CMD_COND_BIND_GB_SURFACE:
4639	{
4640	SVGA3dCmdCondBindGBSurface pCmd = (SVGA3dCmdCondBindGBSurface )pvCmd;
4641	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4642	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4643	break;
4644	}
4645
4646	case SVGA_3D_CMD_UPDATE_GB_IMAGE:
4647	{
4648	SVGA3dCmdUpdateGBImage pCmd = (SVGA3dCmdUpdateGBImage )pvCmd;
4649	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4650	vmsvga3dCmdUpdateGBImage(pThisCC, pCmd);
4651	break;
4652	}
4653
4654	case SVGA_3D_CMD_UPDATE_GB_SURFACE:
4655	{
4656	SVGA3dCmdUpdateGBSurface pCmd = (SVGA3dCmdUpdateGBSurface )pvCmd;
4657	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4658	vmsvga3dCmdUpdateGBSurface(pThisCC, pCmd);
4659	break;
4660	}
4661
4662	case SVGA_3D_CMD_READBACK_GB_IMAGE:
4663	{
4664	SVGA3dCmdReadbackGBImage pCmd = (SVGA3dCmdReadbackGBImage )pvCmd;
4665	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4666	vmsvga3dCmdReadbackGBImage(pThisCC, pCmd);
4667	break;
4668	}
4669
4670	case SVGA_3D_CMD_READBACK_GB_SURFACE:
4671	{
4672	SVGA3dCmdReadbackGBSurface pCmd = (SVGA3dCmdReadbackGBSurface )pvCmd;
4673	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4674	vmsvga3dCmdReadbackGBSurface(pThisCC, pCmd);
4675	break;
4676	}
4677
4678	case SVGA_3D_CMD_INVALIDATE_GB_IMAGE:
4679	{
4680	SVGA3dCmdInvalidateGBImage pCmd = (SVGA3dCmdInvalidateGBImage )pvCmd;
4681	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4682	vmsvga3dCmdInvalidateGBImage(pThisCC, pCmd);
4683	break;
4684	}
4685
4686	case SVGA_3D_CMD_INVALIDATE_GB_SURFACE:
4687	{
4688	SVGA3dCmdInvalidateGBSurface pCmd = (SVGA3dCmdInvalidateGBSurface )pvCmd;
4689	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4690	vmsvga3dCmdInvalidateGBSurface(pThisCC, pCmd);
4691	break;
4692	}
4693
4694	case SVGA_3D_CMD_DEFINE_GB_CONTEXT:
4695	{
4696	SVGA3dCmdDefineGBContext pCmd = (SVGA3dCmdDefineGBContext )pvCmd;
4697	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4698	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4699	break;
4700	}
4701
4702	case SVGA_3D_CMD_DESTROY_GB_CONTEXT:
4703	{
4704	SVGA3dCmdDestroyGBContext pCmd = (SVGA3dCmdDestroyGBContext )pvCmd;
4705	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4706	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4707	break;
4708	}
4709
4710	case SVGA_3D_CMD_BIND_GB_CONTEXT:
4711	{
4712	SVGA3dCmdBindGBContext pCmd = (SVGA3dCmdBindGBContext )pvCmd;
4713	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4714	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4715	break;
4716	}
4717
4718	case SVGA_3D_CMD_READBACK_GB_CONTEXT:
4719	{
4720	SVGA3dCmdReadbackGBContext pCmd = (SVGA3dCmdReadbackGBContext )pvCmd;
4721	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4722	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4723	break;
4724	}
4725
4726	case SVGA_3D_CMD_INVALIDATE_GB_CONTEXT:
4727	{
4728	SVGA3dCmdInvalidateGBContext pCmd = (SVGA3dCmdInvalidateGBContext )pvCmd;
4729	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4730	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4731	break;
4732	}
4733
4734	case SVGA_3D_CMD_DEFINE_GB_SHADER:
4735	{
4736	SVGA3dCmdDefineGBShader pCmd = (SVGA3dCmdDefineGBShader )pvCmd;
4737	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4738	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4739	break;
4740	}
4741
4742	case SVGA_3D_CMD_DESTROY_GB_SHADER:
4743	{
4744	SVGA3dCmdDestroyGBShader pCmd = (SVGA3dCmdDestroyGBShader )pvCmd;
4745	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4746	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4747	break;
4748	}
4749
4750	case SVGA_3D_CMD_BIND_GB_SHADER:
4751	{
4752	SVGA3dCmdBindGBShader pCmd = (SVGA3dCmdBindGBShader )pvCmd;
4753	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4754	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4755	break;
4756	}
4757
4758	case SVGA_3D_CMD_SET_OTABLE_BASE64:
4759	{
4760	SVGA3dCmdSetOTableBase64 pCmd = (SVGA3dCmdSetOTableBase64 )pvCmd;
4761	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4762	vmsvga3dCmdSetOTableBase64(pThisCC, pCmd);
4763	break;
4764	}
4765
4766	case SVGA_3D_CMD_BEGIN_GB_QUERY:
4767	{
4768	SVGA3dCmdBeginGBQuery pCmd = (SVGA3dCmdBeginGBQuery )pvCmd;
4769	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4770	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4771	break;
4772	}
4773
4774	case SVGA_3D_CMD_END_GB_QUERY:
4775	{
4776	SVGA3dCmdEndGBQuery pCmd = (SVGA3dCmdEndGBQuery )pvCmd;
4777	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4778	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4779	break;
4780	}
4781
4782	case SVGA_3D_CMD_WAIT_FOR_GB_QUERY:
4783	{
4784	SVGA3dCmdWaitForGBQuery pCmd = (SVGA3dCmdWaitForGBQuery )pvCmd;
4785	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4786	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4787	break;
4788	}
4789
4790	case SVGA_3D_CMD_NOP:
4791	{
4792	/* Apparently there is nothing to do. */
4793	break;
4794	}
4795
4796	case SVGA_3D_CMD_ENABLE_GART:
4797	{
4798	SVGA3dCmdEnableGart pCmd = (SVGA3dCmdEnableGart )pvCmd;
4799	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4800	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4801	break;
4802	}
4803
4804	case SVGA_3D_CMD_DISABLE_GART:
4805	{
4806	/* No corresponding SVGA3dCmd structure. */
4807	VMSVGA_3D_CMD_NOTIMPL();
4808	break;
4809	}
4810
4811	case SVGA_3D_CMD_MAP_MOB_INTO_GART:
4812	{
4813	SVGA3dCmdMapMobIntoGart pCmd = (SVGA3dCmdMapMobIntoGart )pvCmd;
4814	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4815	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4816	break;
4817	}
4818
4819	case SVGA_3D_CMD_UNMAP_GART_RANGE:
4820	{
4821	SVGA3dCmdUnmapGartRange pCmd = (SVGA3dCmdUnmapGartRange )pvCmd;
4822	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4823	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4824	break;
4825	}
4826
4827	case SVGA_3D_CMD_DEFINE_GB_SCREENTARGET:
4828	{
4829	SVGA3dCmdDefineGBScreenTarget pCmd = (SVGA3dCmdDefineGBScreenTarget )pvCmd;
4830	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4831	vmsvga3dCmdDefineGBScreenTarget(pThis, pThisCC, pCmd);
4832	break;
4833	}
4834
4835	case SVGA_3D_CMD_DESTROY_GB_SCREENTARGET:
4836	{
4837	SVGA3dCmdDestroyGBScreenTarget pCmd = (SVGA3dCmdDestroyGBScreenTarget )pvCmd;
4838	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4839	vmsvga3dCmdDestroyGBScreenTarget(pThis, pThisCC, pCmd);
4840	break;
4841	}
4842
4843	case SVGA_3D_CMD_BIND_GB_SCREENTARGET:
4844	{
4845	SVGA3dCmdBindGBScreenTarget pCmd = (SVGA3dCmdBindGBScreenTarget )pvCmd;
4846	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4847	vmsvga3dCmdBindGBScreenTarget(pThisCC, pCmd);
4848	break;
4849	}
4850
4851	case SVGA_3D_CMD_UPDATE_GB_SCREENTARGET:
4852	{
4853	SVGA3dCmdUpdateGBScreenTarget pCmd = (SVGA3dCmdUpdateGBScreenTarget )pvCmd;
4854	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4855	vmsvga3dCmdUpdateGBScreenTarget(pThisCC, pCmd);
4856	break;
4857	}
4858
4859	case SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL:
4860	{
4861	SVGA3dCmdReadbackGBImagePartial pCmd = (SVGA3dCmdReadbackGBImagePartial )pvCmd;
4862	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4863	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4864	break;
4865	}
4866
4867	case SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL:
4868	{
4869	SVGA3dCmdInvalidateGBImagePartial pCmd = (SVGA3dCmdInvalidateGBImagePartial )pvCmd;
4870	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4871	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4872	break;
4873	}
4874
4875	case SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE:
4876	{
4877	SVGA3dCmdSetGBShaderConstInline pCmd = (SVGA3dCmdSetGBShaderConstInline )pvCmd;
4878	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4879	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4880	break;
4881	}
4882
4883	case SVGA_3D_CMD_GB_SCREEN_DMA:
4884	{
4885	SVGA3dCmdGBScreenDMA pCmd = (SVGA3dCmdGBScreenDMA )pvCmd;
4886	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4887	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4888	break;
4889	}
4890
4891	case SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH:
4892	{
4893	SVGA3dCmdBindGBSurfaceWithPitch pCmd = (SVGA3dCmdBindGBSurfaceWithPitch )pvCmd;
4894	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4895	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4896	break;
4897	}
4898
4899	case SVGA_3D_CMD_GB_MOB_FENCE:
4900	{
4901	SVGA3dCmdGBMobFence pCmd = (SVGA3dCmdGBMobFence )pvCmd;
4902	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4903	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4904	break;
4905	}
4906
4907	case SVGA_3D_CMD_DEFINE_GB_SURFACE_V2:
4908	{
4909	SVGA3dCmdDefineGBSurface_v2 pCmd = (SVGA3dCmdDefineGBSurface_v2 )pvCmd;
4910	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4911	vmsvga3dCmdDefineGBSurface_v2(pThisCC, pCmd);
4912	break;
4913	}
4914
4915	case SVGA_3D_CMD_DEFINE_GB_MOB64:
4916	{
4917	SVGA3dCmdDefineGBMob64 pCmd = (SVGA3dCmdDefineGBMob64 )pvCmd;
4918	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4919	vmsvga3dCmdDefineGBMob64(pThisCC, pCmd);
4920	break;
4921	}
4922
4923	case SVGA_3D_CMD_REDEFINE_GB_MOB64:
4924	{
4925	SVGA3dCmdRedefineGBMob64 pCmd = (SVGA3dCmdRedefineGBMob64 )pvCmd;
4926	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4927	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4928	break;
4929	}
4930
4931	case SVGA_3D_CMD_NOP_ERROR:
4932	{
4933	/* Apparently there is nothing to do. */
4934	break;
4935	}
4936
4937	case SVGA_3D_CMD_SET_VERTEX_STREAMS:
4938	{
4939	SVGA3dCmdSetVertexStreams pCmd = (SVGA3dCmdSetVertexStreams )pvCmd;
4940	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4941	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4942	break;
4943	}
4944
4945	case SVGA_3D_CMD_SET_VERTEX_DECLS:
4946	{
4947	SVGA3dCmdSetVertexDecls pCmd = (SVGA3dCmdSetVertexDecls )pvCmd;
4948	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4949	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4950	break;
4951	}
4952
4953	case SVGA_3D_CMD_SET_VERTEX_DIVISORS:
4954	{
4955	SVGA3dCmdSetVertexDivisors pCmd = (SVGA3dCmdSetVertexDivisors )pvCmd;
4956	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4957	VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4958	break;
4959	}
4960
4961	case SVGA_3D_CMD_DRAW:
4962	{
4963	/* No corresponding SVGA3dCmd structure. */
4964	VMSVGA_3D_CMD_NOTIMPL();
4965	break;
4966	}
4967
4968	case SVGA_3D_CMD_DRAW_INDEXED:
4969	{
4970	/* No corresponding SVGA3dCmd structure. */
4971	VMSVGA_3D_CMD_NOTIMPL();
4972	break;
4973	}
4974
4975	case SVGA_3D_CMD_DX_DEFINE_CONTEXT:
4976	{
4977	SVGA3dCmdDXDefineContext pCmd = (SVGA3dCmdDXDefineContext )pvCmd;
4978	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4979	rcParse = vmsvga3dCmdDXDefineContext(pThisCC, pCmd, cbCmd);
4980	break;
4981	}
4982
4983	case SVGA_3D_CMD_DX_DESTROY_CONTEXT:
4984	{
4985	SVGA3dCmdDXDestroyContext pCmd = (SVGA3dCmdDXDestroyContext )pvCmd;
4986	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4987	rcParse = vmsvga3dCmdDXDestroyContext(pThisCC, pCmd, cbCmd);
4988	break;
4989	}
4990
4991	case SVGA_3D_CMD_DX_BIND_CONTEXT:
4992	{
4993	SVGA3dCmdDXBindContext pCmd = (SVGA3dCmdDXBindContext )pvCmd;
4994	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4995	rcParse = vmsvga3dCmdDXBindContext(pThisCC, pCmd, cbCmd);
4996	break;
4997	}
4998
4999	case SVGA_3D_CMD_DX_READBACK_CONTEXT:
5000	{
5001	SVGA3dCmdDXReadbackContext pCmd = (SVGA3dCmdDXReadbackContext )pvCmd;
5002	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5003	rcParse = vmsvga3dCmdDXReadbackContext(pThisCC, pCmd, cbCmd);
5004	break;
5005	}
5006
5007	case SVGA_3D_CMD_DX_INVALIDATE_CONTEXT:
5008	{
5009	SVGA3dCmdDXInvalidateContext pCmd = (SVGA3dCmdDXInvalidateContext )pvCmd;
5010	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5011	rcParse = vmsvga3dCmdDXInvalidateContext(pThisCC, idDXContext, pCmd, cbCmd);
5012	break;
5013	}
5014
5015	case SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER:
5016	{
5017	SVGA3dCmdDXSetSingleConstantBuffer pCmd = (SVGA3dCmdDXSetSingleConstantBuffer )pvCmd;
5018	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5019	rcParse = vmsvga3dCmdDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5020	break;
5021	}
5022
5023	case SVGA_3D_CMD_DX_SET_SHADER_RESOURCES:
5024	{
5025	SVGA3dCmdDXSetShaderResources pCmd = (SVGA3dCmdDXSetShaderResources )pvCmd;
5026	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5027	rcParse = vmsvga3dCmdDXSetShaderResources(pThisCC, idDXContext, pCmd, cbCmd);
5028	break;
5029	}
5030
5031	case SVGA_3D_CMD_DX_SET_SHADER:
5032	{
5033	SVGA3dCmdDXSetShader pCmd = (SVGA3dCmdDXSetShader )pvCmd;
5034	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5035	rcParse = vmsvga3dCmdDXSetShader(pThisCC, idDXContext, pCmd, cbCmd);
5036	break;
5037	}
5038
5039	case SVGA_3D_CMD_DX_SET_SAMPLERS:
5040	{
5041	SVGA3dCmdDXSetSamplers pCmd = (SVGA3dCmdDXSetSamplers )pvCmd;
5042	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5043	rcParse = vmsvga3dCmdDXSetSamplers(pThisCC, idDXContext, pCmd, cbCmd);
5044	break;
5045	}
5046
5047	case SVGA_3D_CMD_DX_DRAW:
5048	{
5049	SVGA3dCmdDXDraw pCmd = (SVGA3dCmdDXDraw )pvCmd;
5050	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5051	rcParse = vmsvga3dCmdDXDraw(pThisCC, idDXContext, pCmd, cbCmd);
5052	break;
5053	}
5054
5055	case SVGA_3D_CMD_DX_DRAW_INDEXED:
5056	{
5057	SVGA3dCmdDXDrawIndexed pCmd = (SVGA3dCmdDXDrawIndexed )pvCmd;
5058	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5059	rcParse = vmsvga3dCmdDXDrawIndexed(pThisCC, idDXContext, pCmd, cbCmd);
5060	break;
5061	}
5062
5063	case SVGA_3D_CMD_DX_DRAW_INSTANCED:
5064	{
5065	SVGA3dCmdDXDrawInstanced pCmd = (SVGA3dCmdDXDrawInstanced )pvCmd;
5066	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5067	rcParse = vmsvga3dCmdDXDrawInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5068	break;
5069	}
5070
5071	case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED:
5072	{
5073	SVGA3dCmdDXDrawIndexedInstanced pCmd = (SVGA3dCmdDXDrawIndexedInstanced )pvCmd;
5074	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5075	rcParse = vmsvga3dCmdDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5076	break;
5077	}
5078
5079	case SVGA_3D_CMD_DX_DRAW_AUTO:
5080	{
5081	SVGA3dCmdDXDrawAuto pCmd = (SVGA3dCmdDXDrawAuto )pvCmd;
5082	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5083	rcParse = vmsvga3dCmdDXDrawAuto(pThisCC, idDXContext, pCmd, cbCmd);
5084	break;
5085	}
5086
5087	case SVGA_3D_CMD_DX_SET_INPUT_LAYOUT:
5088	{
5089	SVGA3dCmdDXSetInputLayout pCmd = (SVGA3dCmdDXSetInputLayout )pvCmd;
5090	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5091	rcParse = vmsvga3dCmdDXSetInputLayout(pThisCC, idDXContext, pCmd, cbCmd);
5092	break;
5093	}
5094
5095	case SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS:
5096	{
5097	SVGA3dCmdDXSetVertexBuffers pCmd = (SVGA3dCmdDXSetVertexBuffers )pvCmd;
5098	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5099	rcParse = vmsvga3dCmdDXSetVertexBuffers(pThisCC, idDXContext, pCmd, cbCmd);
5100	break;
5101	}
5102
5103	case SVGA_3D_CMD_DX_SET_INDEX_BUFFER:
5104	{
5105	SVGA3dCmdDXSetIndexBuffer pCmd = (SVGA3dCmdDXSetIndexBuffer )pvCmd;
5106	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5107	rcParse = vmsvga3dCmdDXSetIndexBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5108	break;
5109	}
5110
5111	case SVGA_3D_CMD_DX_SET_TOPOLOGY:
5112	{
5113	SVGA3dCmdDXSetTopology pCmd = (SVGA3dCmdDXSetTopology )pvCmd;
5114	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5115	rcParse = vmsvga3dCmdDXSetTopology(pThisCC, idDXContext, pCmd, cbCmd);
5116	break;
5117	}
5118
5119	case SVGA_3D_CMD_DX_SET_RENDERTARGETS:
5120	{
5121	SVGA3dCmdDXSetRenderTargets pCmd = (SVGA3dCmdDXSetRenderTargets )pvCmd;
5122	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5123	rcParse = vmsvga3dCmdDXSetRenderTargets(pThisCC, idDXContext, pCmd, cbCmd);
5124	break;
5125	}
5126
5127	case SVGA_3D_CMD_DX_SET_BLEND_STATE:
5128	{
5129	SVGA3dCmdDXSetBlendState pCmd = (SVGA3dCmdDXSetBlendState )pvCmd;
5130	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5131	rcParse = vmsvga3dCmdDXSetBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5132	break;
5133	}
5134
5135	case SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE:
5136	{
5137	SVGA3dCmdDXSetDepthStencilState pCmd = (SVGA3dCmdDXSetDepthStencilState )pvCmd;
5138	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5139	rcParse = vmsvga3dCmdDXSetDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5140	break;
5141	}
5142
5143	case SVGA_3D_CMD_DX_SET_RASTERIZER_STATE:
5144	{
5145	SVGA3dCmdDXSetRasterizerState pCmd = (SVGA3dCmdDXSetRasterizerState )pvCmd;
5146	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5147	rcParse = vmsvga3dCmdDXSetRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5148	break;
5149	}
5150
5151	case SVGA_3D_CMD_DX_DEFINE_QUERY:
5152	{
5153	SVGA3dCmdDXDefineQuery pCmd = (SVGA3dCmdDXDefineQuery )pvCmd;
5154	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5155	rcParse = vmsvga3dCmdDXDefineQuery(pThisCC, idDXContext, pCmd, cbCmd);
5156	break;
5157	}
5158
5159	case SVGA_3D_CMD_DX_DESTROY_QUERY:
5160	{
5161	SVGA3dCmdDXDestroyQuery pCmd = (SVGA3dCmdDXDestroyQuery )pvCmd;
5162	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5163	rcParse = vmsvga3dCmdDXDestroyQuery(pThisCC, idDXContext, pCmd, cbCmd);
5164	break;
5165	}
5166
5167	case SVGA_3D_CMD_DX_BIND_QUERY:
5168	{
5169	SVGA3dCmdDXBindQuery pCmd = (SVGA3dCmdDXBindQuery )pvCmd;
5170	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5171	rcParse = vmsvga3dCmdDXBindQuery(pThisCC, idDXContext, pCmd, cbCmd);
5172	break;
5173	}
5174
5175	case SVGA_3D_CMD_DX_SET_QUERY_OFFSET:
5176	{
5177	SVGA3dCmdDXSetQueryOffset pCmd = (SVGA3dCmdDXSetQueryOffset )pvCmd;
5178	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5179	rcParse = vmsvga3dCmdDXSetQueryOffset(pThisCC, idDXContext, pCmd, cbCmd);
5180	break;
5181	}
5182
5183	case SVGA_3D_CMD_DX_BEGIN_QUERY:
5184	{
5185	SVGA3dCmdDXBeginQuery pCmd = (SVGA3dCmdDXBeginQuery )pvCmd;
5186	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5187	rcParse = vmsvga3dCmdDXBeginQuery(pThisCC, idDXContext, pCmd, cbCmd);
5188	break;
5189	}
5190
5191	case SVGA_3D_CMD_DX_END_QUERY:
5192	{
5193	SVGA3dCmdDXEndQuery pCmd = (SVGA3dCmdDXEndQuery )pvCmd;
5194	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5195	rcParse = vmsvga3dCmdDXEndQuery(pThisCC, idDXContext, pCmd, cbCmd);
5196	break;
5197	}
5198
5199	case SVGA_3D_CMD_DX_READBACK_QUERY:
5200	{
5201	SVGA3dCmdDXReadbackQuery pCmd = (SVGA3dCmdDXReadbackQuery )pvCmd;
5202	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5203	rcParse = vmsvga3dCmdDXReadbackQuery(pThisCC, idDXContext, pCmd, cbCmd);
5204	break;
5205	}
5206
5207	case SVGA_3D_CMD_DX_SET_PREDICATION:
5208	{
5209	SVGA3dCmdDXSetPredication pCmd = (SVGA3dCmdDXSetPredication )pvCmd;
5210	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5211	rcParse = vmsvga3dCmdDXSetPredication(pThisCC, idDXContext, pCmd, cbCmd);
5212	break;
5213	}
5214
5215	case SVGA_3D_CMD_DX_SET_SOTARGETS:
5216	{
5217	SVGA3dCmdDXSetSOTargets pCmd = (SVGA3dCmdDXSetSOTargets )pvCmd;
5218	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5219	rcParse = vmsvga3dCmdDXSetSOTargets(pThisCC, idDXContext, pCmd, cbCmd);
5220	break;
5221	}
5222
5223	case SVGA_3D_CMD_DX_SET_VIEWPORTS:
5224	{
5225	SVGA3dCmdDXSetViewports pCmd = (SVGA3dCmdDXSetViewports )pvCmd;
5226	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5227	rcParse = vmsvga3dCmdDXSetViewports(pThisCC, idDXContext, pCmd, cbCmd);
5228	break;
5229	}
5230
5231	case SVGA_3D_CMD_DX_SET_SCISSORRECTS:
5232	{
5233	SVGA3dCmdDXSetScissorRects pCmd = (SVGA3dCmdDXSetScissorRects )pvCmd;
5234	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5235	rcParse = vmsvga3dCmdDXSetScissorRects(pThisCC, idDXContext, pCmd, cbCmd);
5236	break;
5237	}
5238
5239	case SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW:
5240	{
5241	SVGA3dCmdDXClearRenderTargetView pCmd = (SVGA3dCmdDXClearRenderTargetView )pvCmd;
5242	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5243	rcParse = vmsvga3dCmdDXClearRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5244	break;
5245	}
5246
5247	case SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW:
5248	{
5249	SVGA3dCmdDXClearDepthStencilView pCmd = (SVGA3dCmdDXClearDepthStencilView )pvCmd;
5250	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5251	rcParse = vmsvga3dCmdDXClearDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5252	break;
5253	}
5254
5255	case SVGA_3D_CMD_DX_PRED_COPY_REGION:
5256	{
5257	SVGA3dCmdDXPredCopyRegion pCmd = (SVGA3dCmdDXPredCopyRegion )pvCmd;
5258	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5259	rcParse = vmsvga3dCmdDXPredCopyRegion(pThisCC, idDXContext, pCmd, cbCmd);
5260	break;
5261	}
5262
5263	case SVGA_3D_CMD_DX_PRED_COPY:
5264	{
5265	SVGA3dCmdDXPredCopy pCmd = (SVGA3dCmdDXPredCopy )pvCmd;
5266	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5267	rcParse = vmsvga3dCmdDXPredCopy(pThisCC, idDXContext, pCmd, cbCmd);
5268	break;
5269	}
5270
5271	case SVGA_3D_CMD_DX_PRESENTBLT:
5272	{
5273	SVGA3dCmdDXPresentBlt pCmd = (SVGA3dCmdDXPresentBlt )pvCmd;
5274	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5275	rcParse = vmsvga3dCmdDXPresentBlt(pThisCC, idDXContext, pCmd, cbCmd);
5276	break;
5277	}
5278
5279	case SVGA_3D_CMD_DX_GENMIPS:
5280	{
5281	SVGA3dCmdDXGenMips pCmd = (SVGA3dCmdDXGenMips )pvCmd;
5282	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5283	rcParse = vmsvga3dCmdDXGenMips(pThisCC, idDXContext, pCmd, cbCmd);
5284	break;
5285	}
5286
5287	case SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE:
5288	{
5289	SVGA3dCmdDXUpdateSubResource pCmd = (SVGA3dCmdDXUpdateSubResource )pvCmd;
5290	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5291	rcParse = vmsvga3dCmdDXUpdateSubResource(pThisCC, pCmd, cbCmd);
5292	break;
5293	}
5294
5295	case SVGA_3D_CMD_DX_READBACK_SUBRESOURCE:
5296	{
5297	SVGA3dCmdDXReadbackSubResource pCmd = (SVGA3dCmdDXReadbackSubResource )pvCmd;
5298	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5299	rcParse = vmsvga3dCmdDXReadbackSubResource(pThisCC, pCmd, cbCmd);
5300	break;
5301	}
5302
5303	case SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE:
5304	{
5305	SVGA3dCmdDXInvalidateSubResource pCmd = (SVGA3dCmdDXInvalidateSubResource )pvCmd;
5306	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5307	rcParse = vmsvga3dCmdDXInvalidateSubResource(pThisCC, pCmd, cbCmd);
5308	break;
5309	}
5310
5311	case SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW:
5312	{
5313	SVGA3dCmdDXDefineShaderResourceView pCmd = (SVGA3dCmdDXDefineShaderResourceView )pvCmd;
5314	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5315	rcParse = vmsvga3dCmdDXDefineShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5316	break;
5317	}
5318
5319	case SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW:
5320	{
5321	SVGA3dCmdDXDestroyShaderResourceView pCmd = (SVGA3dCmdDXDestroyShaderResourceView )pvCmd;
5322	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5323	rcParse = vmsvga3dCmdDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5324	break;
5325	}
5326
5327	case SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW:
5328	{
5329	SVGA3dCmdDXDefineRenderTargetView pCmd = (SVGA3dCmdDXDefineRenderTargetView )pvCmd;
5330	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5331	rcParse = vmsvga3dCmdDXDefineRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5332	break;
5333	}
5334
5335	case SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW:
5336	{
5337	SVGA3dCmdDXDestroyRenderTargetView pCmd = (SVGA3dCmdDXDestroyRenderTargetView )pvCmd;
5338	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5339	rcParse = vmsvga3dCmdDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5340	break;
5341	}
5342
5343	case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW:
5344	{
5345	SVGA3dCmdDXDefineDepthStencilView pCmd = (SVGA3dCmdDXDefineDepthStencilView )pvCmd;
5346	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5347	rcParse = vmsvga3dCmdDXDefineDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5348	break;
5349	}
5350
5351	case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW:
5352	{
5353	SVGA3dCmdDXDestroyDepthStencilView pCmd = (SVGA3dCmdDXDestroyDepthStencilView )pvCmd;
5354	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5355	rcParse = vmsvga3dCmdDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5356	break;
5357	}
5358
5359	case SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT:
5360	{
5361	SVGA3dCmdDXDefineElementLayout pCmd = (SVGA3dCmdDXDefineElementLayout )pvCmd;
5362	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5363	rcParse = vmsvga3dCmdDXDefineElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5364	break;
5365	}
5366
5367	case SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT:
5368	{
5369	SVGA3dCmdDXDestroyElementLayout pCmd = (SVGA3dCmdDXDestroyElementLayout )pvCmd;
5370	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5371	rcParse = vmsvga3dCmdDXDestroyElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5372	break;
5373	}
5374
5375	case SVGA_3D_CMD_DX_DEFINE_BLEND_STATE:
5376	{
5377	SVGA3dCmdDXDefineBlendState pCmd = (SVGA3dCmdDXDefineBlendState )pvCmd;
5378	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5379	rcParse = vmsvga3dCmdDXDefineBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5380	break;
5381	}
5382
5383	case SVGA_3D_CMD_DX_DESTROY_BLEND_STATE:
5384	{
5385	SVGA3dCmdDXDestroyBlendState pCmd = (SVGA3dCmdDXDestroyBlendState )pvCmd;
5386	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5387	rcParse = vmsvga3dCmdDXDestroyBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5388	break;
5389	}
5390
5391	case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE:
5392	{
5393	SVGA3dCmdDXDefineDepthStencilState pCmd = (SVGA3dCmdDXDefineDepthStencilState )pvCmd;
5394	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5395	rcParse = vmsvga3dCmdDXDefineDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5396	break;
5397	}
5398
5399	case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE:
5400	{
5401	SVGA3dCmdDXDestroyDepthStencilState pCmd = (SVGA3dCmdDXDestroyDepthStencilState )pvCmd;
5402	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5403	rcParse = vmsvga3dCmdDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5404	break;
5405	}
5406
5407	case SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE:
5408	{
5409	SVGA3dCmdDXDefineRasterizerState pCmd = (SVGA3dCmdDXDefineRasterizerState )pvCmd;
5410	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5411	rcParse = vmsvga3dCmdDXDefineRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5412	break;
5413	}
5414
5415	case SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE:
5416	{
5417	SVGA3dCmdDXDestroyRasterizerState pCmd = (SVGA3dCmdDXDestroyRasterizerState )pvCmd;
5418	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5419	rcParse = vmsvga3dCmdDXDestroyRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5420	break;
5421	}
5422
5423	case SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE:
5424	{
5425	SVGA3dCmdDXDefineSamplerState pCmd = (SVGA3dCmdDXDefineSamplerState )pvCmd;
5426	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5427	rcParse = vmsvga3dCmdDXDefineSamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5428	break;
5429	}
5430
5431	case SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE:
5432	{
5433	SVGA3dCmdDXDestroySamplerState pCmd = (SVGA3dCmdDXDestroySamplerState )pvCmd;
5434	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5435	rcParse = vmsvga3dCmdDXDestroySamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5436	break;
5437	}
5438
5439	case SVGA_3D_CMD_DX_DEFINE_SHADER:
5440	{
5441	SVGA3dCmdDXDefineShader pCmd = (SVGA3dCmdDXDefineShader )pvCmd;
5442	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5443	rcParse = vmsvga3dCmdDXDefineShader(pThisCC, idDXContext, pCmd, cbCmd);
5444	break;
5445	}
5446
5447	case SVGA_3D_CMD_DX_DESTROY_SHADER:
5448	{
5449	SVGA3dCmdDXDestroyShader pCmd = (SVGA3dCmdDXDestroyShader )pvCmd;
5450	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5451	rcParse = vmsvga3dCmdDXDestroyShader(pThisCC, idDXContext, pCmd, cbCmd);
5452	break;
5453	}
5454
5455	case SVGA_3D_CMD_DX_BIND_SHADER:
5456	{
5457	SVGA3dCmdDXBindShader pCmd = (SVGA3dCmdDXBindShader )pvCmd;
5458	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5459	rcParse = vmsvga3dCmdDXBindShader(pThisCC, idDXContext, pCmd, cbCmd);
5460	break;
5461	}
5462
5463	case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT:
5464	{
5465	SVGA3dCmdDXDefineStreamOutput pCmd = (SVGA3dCmdDXDefineStreamOutput )pvCmd;
5466	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5467	rcParse = vmsvga3dCmdDXDefineStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5468	break;
5469	}
5470
5471	case SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT:
5472	{
5473	SVGA3dCmdDXDestroyStreamOutput pCmd = (SVGA3dCmdDXDestroyStreamOutput )pvCmd;
5474	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5475	rcParse = vmsvga3dCmdDXDestroyStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5476	break;
5477	}
5478
5479	case SVGA_3D_CMD_DX_SET_STREAMOUTPUT:
5480	{
5481	SVGA3dCmdDXSetStreamOutput pCmd = (SVGA3dCmdDXSetStreamOutput )pvCmd;
5482	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5483	rcParse = vmsvga3dCmdDXSetStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5484	break;
5485	}
5486
5487	case SVGA_3D_CMD_DX_SET_COTABLE:
5488	{
5489	SVGA3dCmdDXSetCOTable pCmd = (SVGA3dCmdDXSetCOTable )pvCmd;
5490	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5491	rcParse = vmsvga3dCmdDXSetCOTable(pThisCC, pCmd, cbCmd);
5492	break;
5493	}
5494
5495	case SVGA_3D_CMD_DX_READBACK_COTABLE:
5496	{
5497	SVGA3dCmdDXReadbackCOTable pCmd = (SVGA3dCmdDXReadbackCOTable )pvCmd;
5498	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5499	rcParse = vmsvga3dCmdDXReadbackCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5500	break;
5501	}
5502
5503	case SVGA_3D_CMD_DX_BUFFER_COPY:
5504	{
5505	SVGA3dCmdDXBufferCopy pCmd = (SVGA3dCmdDXBufferCopy )pvCmd;
5506	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5507	rcParse = vmsvga3dCmdDXBufferCopy(pThisCC, idDXContext, pCmd, cbCmd);
5508	break;
5509	}
5510
5511	case SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER:
5512	{
5513	SVGA3dCmdDXTransferFromBuffer pCmd = (SVGA3dCmdDXTransferFromBuffer )pvCmd;
5514	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5515	rcParse = vmsvga3dCmdDXTransferFromBuffer(pThisCC, pCmd, cbCmd);
5516	break;
5517	}
5518
5519	case SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK:
5520	{
5521	SVGA3dCmdDXSurfaceCopyAndReadback pCmd = (SVGA3dCmdDXSurfaceCopyAndReadback )pvCmd;
5522	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5523	rcParse = vmsvga3dCmdDXSurfaceCopyAndReadback(pThisCC, idDXContext, pCmd, cbCmd);
5524	break;
5525	}
5526
5527	case SVGA_3D_CMD_DX_MOVE_QUERY:
5528	{
5529	SVGA3dCmdDXMoveQuery pCmd = (SVGA3dCmdDXMoveQuery )pvCmd;
5530	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5531	rcParse = vmsvga3dCmdDXMoveQuery(pThisCC, idDXContext, pCmd, cbCmd);
5532	break;
5533	}
5534
5535	case SVGA_3D_CMD_DX_BIND_ALL_QUERY:
5536	{
5537	SVGA3dCmdDXBindAllQuery pCmd = (SVGA3dCmdDXBindAllQuery )pvCmd;
5538	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5539	rcParse = vmsvga3dCmdDXBindAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5540	break;
5541	}
5542
5543	case SVGA_3D_CMD_DX_READBACK_ALL_QUERY:
5544	{
5545	SVGA3dCmdDXReadbackAllQuery pCmd = (SVGA3dCmdDXReadbackAllQuery )pvCmd;
5546	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5547	rcParse = vmsvga3dCmdDXReadbackAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5548	break;
5549	}
5550
5551	case SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER:
5552	{
5553	SVGA3dCmdDXPredTransferFromBuffer pCmd = (SVGA3dCmdDXPredTransferFromBuffer )pvCmd;
5554	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5555	rcParse = vmsvga3dCmdDXPredTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5556	break;
5557	}
5558
5559	case SVGA_3D_CMD_DX_MOB_FENCE_64:
5560	{
5561	SVGA3dCmdDXMobFence64 pCmd = (SVGA3dCmdDXMobFence64 )pvCmd;
5562	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5563	rcParse = vmsvga3dCmdDXMobFence64(pThisCC, idDXContext, pCmd, cbCmd);
5564	break;
5565	}
5566
5567	case SVGA_3D_CMD_DX_BIND_ALL_SHADER:
5568	{
5569	SVGA3dCmdDXBindAllShader pCmd = (SVGA3dCmdDXBindAllShader )pvCmd;
5570	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5571	rcParse = vmsvga3dCmdDXBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5572	break;
5573	}
5574
5575	case SVGA_3D_CMD_DX_HINT:
5576	{
5577	SVGA3dCmdDXHint pCmd = (SVGA3dCmdDXHint )pvCmd;
5578	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5579	rcParse = vmsvga3dCmdDXHint(pThisCC, idDXContext, pCmd, cbCmd);
5580	break;
5581	}
5582
5583	case SVGA_3D_CMD_DX_BUFFER_UPDATE:
5584	{
5585	SVGA3dCmdDXBufferUpdate pCmd = (SVGA3dCmdDXBufferUpdate )pvCmd;
5586	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5587	rcParse = vmsvga3dCmdDXBufferUpdate(pThisCC, idDXContext, pCmd, cbCmd);
5588	break;
5589	}
5590
5591	case SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET:
5592	{
5593	SVGA3dCmdDXSetVSConstantBufferOffset pCmd = (SVGA3dCmdDXSetVSConstantBufferOffset )pvCmd;
5594	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5595	rcParse = vmsvga3dCmdDXSetVSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5596	break;
5597	}
5598
5599	case SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET:
5600	{
5601	SVGA3dCmdDXSetPSConstantBufferOffset pCmd = (SVGA3dCmdDXSetPSConstantBufferOffset )pvCmd;
5602	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5603	rcParse = vmsvga3dCmdDXSetPSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5604	break;
5605	}
5606
5607	case SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET:
5608	{
5609	SVGA3dCmdDXSetGSConstantBufferOffset pCmd = (SVGA3dCmdDXSetGSConstantBufferOffset )pvCmd;
5610	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5611	rcParse = vmsvga3dCmdDXSetGSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5612	break;
5613	}
5614
5615	case SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET:
5616	{
5617	SVGA3dCmdDXSetHSConstantBufferOffset pCmd = (SVGA3dCmdDXSetHSConstantBufferOffset )pvCmd;
5618	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5619	rcParse = vmsvga3dCmdDXSetHSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5620	break;
5621	}
5622
5623	case SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET:
5624	{
5625	SVGA3dCmdDXSetDSConstantBufferOffset pCmd = (SVGA3dCmdDXSetDSConstantBufferOffset )pvCmd;
5626	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5627	rcParse = vmsvga3dCmdDXSetDSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5628	break;
5629	}
5630
5631	case SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET:
5632	{
5633	SVGA3dCmdDXSetCSConstantBufferOffset pCmd = (SVGA3dCmdDXSetCSConstantBufferOffset )pvCmd;
5634	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5635	rcParse = vmsvga3dCmdDXSetCSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5636	break;
5637	}
5638
5639	case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER:
5640	{
5641	SVGA3dCmdDXCondBindAllShader pCmd = (SVGA3dCmdDXCondBindAllShader )pvCmd;
5642	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5643	rcParse = vmsvga3dCmdDXCondBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5644	break;
5645	}
5646
5647	case SVGA_3D_CMD_SCREEN_COPY:
5648	{
5649	SVGA3dCmdScreenCopy pCmd = (SVGA3dCmdScreenCopy )pvCmd;
5650	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5651	rcParse = vmsvga3dCmdScreenCopy(pThisCC, idDXContext, pCmd, cbCmd);
5652	break;
5653	}
5654
5655	case SVGA_3D_CMD_RESERVED1:
5656	{
5657	VMSVGA_3D_CMD_NOTIMPL();
5658	break;
5659	}
5660
5661	case SVGA_3D_CMD_RESERVED2:
5662	{
5663	VMSVGA_3D_CMD_NOTIMPL();
5664	break;
5665	}
5666
5667	case SVGA_3D_CMD_RESERVED3:
5668	{
5669	VMSVGA_3D_CMD_NOTIMPL();
5670	break;
5671	}
5672
5673	case SVGA_3D_CMD_RESERVED4:
5674	{
5675	VMSVGA_3D_CMD_NOTIMPL();
5676	break;
5677	}
5678
5679	case SVGA_3D_CMD_RESERVED5:
5680	{
5681	VMSVGA_3D_CMD_NOTIMPL();
5682	break;
5683	}
5684
5685	case SVGA_3D_CMD_RESERVED6:
5686	{
5687	VMSVGA_3D_CMD_NOTIMPL();
5688	break;
5689	}
5690
5691	case SVGA_3D_CMD_RESERVED7:
5692	{
5693	VMSVGA_3D_CMD_NOTIMPL();
5694	break;
5695	}
5696
5697	case SVGA_3D_CMD_RESERVED8:
5698	{
5699	VMSVGA_3D_CMD_NOTIMPL();
5700	break;
5701	}
5702
5703	case SVGA_3D_CMD_GROW_OTABLE:
5704	{
5705	SVGA3dCmdGrowOTable pCmd = (SVGA3dCmdGrowOTable )pvCmd;
5706	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5707	rcParse = vmsvga3dCmdGrowOTable(pThisCC, idDXContext, pCmd, cbCmd);
5708	break;
5709	}
5710
5711	case SVGA_3D_CMD_DX_GROW_COTABLE:
5712	{
5713	SVGA3dCmdDXGrowCOTable pCmd = (SVGA3dCmdDXGrowCOTable )pvCmd;
5714	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5715	rcParse = vmsvga3dCmdDXGrowCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5716	break;
5717	}
5718
5719	case SVGA_3D_CMD_INTRA_SURFACE_COPY:
5720	{
5721	SVGA3dCmdIntraSurfaceCopy pCmd = (SVGA3dCmdIntraSurfaceCopy )pvCmd;
5722	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5723	rcParse = vmsvga3dCmdIntraSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5724	break;
5725	}
5726
5727	case SVGA_3D_CMD_DEFINE_GB_SURFACE_V3:
5728	{
5729	SVGA3dCmdDefineGBSurface_v3 pCmd = (SVGA3dCmdDefineGBSurface_v3 )pvCmd;
5730	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5731	rcParse = vmsvga3dCmdDefineGBSurface_v3(pThisCC, idDXContext, pCmd, cbCmd);
5732	break;
5733	}
5734
5735	case SVGA_3D_CMD_DX_RESOLVE_COPY:
5736	{
5737	SVGA3dCmdDXResolveCopy pCmd = (SVGA3dCmdDXResolveCopy )pvCmd;
5738	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5739	rcParse = vmsvga3dCmdDXResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5740	break;
5741	}
5742
5743	case SVGA_3D_CMD_DX_PRED_RESOLVE_COPY:
5744	{
5745	SVGA3dCmdDXPredResolveCopy pCmd = (SVGA3dCmdDXPredResolveCopy )pvCmd;
5746	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5747	rcParse = vmsvga3dCmdDXPredResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5748	break;
5749	}
5750
5751	case SVGA_3D_CMD_DX_PRED_CONVERT_REGION:
5752	{
5753	SVGA3dCmdDXPredConvertRegion pCmd = (SVGA3dCmdDXPredConvertRegion )pvCmd;
5754	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5755	rcParse = vmsvga3dCmdDXPredConvertRegion(pThisCC, idDXContext, pCmd, cbCmd);
5756	break;
5757	}
5758
5759	case SVGA_3D_CMD_DX_PRED_CONVERT:
5760	{
5761	SVGA3dCmdDXPredConvert pCmd = (SVGA3dCmdDXPredConvert )pvCmd;
5762	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5763	rcParse = vmsvga3dCmdDXPredConvert(pThisCC, idDXContext, pCmd, cbCmd);
5764	break;
5765	}
5766
5767	case SVGA_3D_CMD_WHOLE_SURFACE_COPY:
5768	{
5769	SVGA3dCmdWholeSurfaceCopy pCmd = (SVGA3dCmdWholeSurfaceCopy )pvCmd;
5770	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5771	rcParse = vmsvga3dCmdWholeSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5772	break;
5773	}
5774
5775	case SVGA_3D_CMD_DX_DEFINE_UA_VIEW:
5776	{
5777	SVGA3dCmdDXDefineUAView pCmd = (SVGA3dCmdDXDefineUAView )pvCmd;
5778	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5779	rcParse = vmsvga3dCmdDXDefineUAView(pThisCC, idDXContext, pCmd, cbCmd);
5780	break;
5781	}
5782
5783	case SVGA_3D_CMD_DX_DESTROY_UA_VIEW:
5784	{
5785	SVGA3dCmdDXDestroyUAView pCmd = (SVGA3dCmdDXDestroyUAView )pvCmd;
5786	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5787	rcParse = vmsvga3dCmdDXDestroyUAView(pThisCC, idDXContext, pCmd, cbCmd);
5788	break;
5789	}
5790
5791	case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT:
5792	{
5793	SVGA3dCmdDXClearUAViewUint pCmd = (SVGA3dCmdDXClearUAViewUint )pvCmd;
5794	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5795	rcParse = vmsvga3dCmdDXClearUAViewUint(pThisCC, idDXContext, pCmd, cbCmd);
5796	break;
5797	}
5798
5799	case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT:
5800	{
5801	SVGA3dCmdDXClearUAViewFloat pCmd = (SVGA3dCmdDXClearUAViewFloat )pvCmd;
5802	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5803	rcParse = vmsvga3dCmdDXClearUAViewFloat(pThisCC, idDXContext, pCmd, cbCmd);
5804	break;
5805	}
5806
5807	case SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT:
5808	{
5809	SVGA3dCmdDXCopyStructureCount pCmd = (SVGA3dCmdDXCopyStructureCount )pvCmd;
5810	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5811	rcParse = vmsvga3dCmdDXCopyStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5812	break;
5813	}
5814
5815	case SVGA_3D_CMD_DX_SET_UA_VIEWS:
5816	{
5817	SVGA3dCmdDXSetUAViews pCmd = (SVGA3dCmdDXSetUAViews )pvCmd;
5818	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5819	rcParse = vmsvga3dCmdDXSetUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5820	break;
5821	}
5822
5823	case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT:
5824	{
5825	SVGA3dCmdDXDrawIndexedInstancedIndirect pCmd = (SVGA3dCmdDXDrawIndexedInstancedIndirect )pvCmd;
5826	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5827	rcParse = vmsvga3dCmdDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5828	break;
5829	}
5830
5831	case SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT:
5832	{
5833	SVGA3dCmdDXDrawInstancedIndirect pCmd = (SVGA3dCmdDXDrawInstancedIndirect )pvCmd;
5834	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5835	rcParse = vmsvga3dCmdDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5836	break;
5837	}
5838
5839	case SVGA_3D_CMD_DX_DISPATCH:
5840	{
5841	SVGA3dCmdDXDispatch pCmd = (SVGA3dCmdDXDispatch )pvCmd;
5842	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5843	rcParse = vmsvga3dCmdDXDispatch(pThisCC, idDXContext, pCmd, cbCmd);
5844	break;
5845	}
5846
5847	case SVGA_3D_CMD_DX_DISPATCH_INDIRECT:
5848	{
5849	SVGA3dCmdDXDispatchIndirect pCmd = (SVGA3dCmdDXDispatchIndirect )pvCmd;
5850	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5851	rcParse = vmsvga3dCmdDXDispatchIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5852	break;
5853	}
5854
5855	case SVGA_3D_CMD_WRITE_ZERO_SURFACE:
5856	{
5857	SVGA3dCmdWriteZeroSurface pCmd = (SVGA3dCmdWriteZeroSurface )pvCmd;
5858	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5859	rcParse = vmsvga3dCmdWriteZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5860	break;
5861	}
5862
5863	case SVGA_3D_CMD_HINT_ZERO_SURFACE:
5864	{
5865	SVGA3dCmdHintZeroSurface pCmd = (SVGA3dCmdHintZeroSurface )pvCmd;
5866	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5867	rcParse = vmsvga3dCmdHintZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5868	break;
5869	}
5870
5871	case SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER:
5872	{
5873	SVGA3dCmdDXTransferToBuffer pCmd = (SVGA3dCmdDXTransferToBuffer )pvCmd;
5874	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5875	rcParse = vmsvga3dCmdDXTransferToBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5876	break;
5877	}
5878
5879	case SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT:
5880	{
5881	SVGA3dCmdDXSetStructureCount pCmd = (SVGA3dCmdDXSetStructureCount )pvCmd;
5882	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5883	rcParse = vmsvga3dCmdDXSetStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5884	break;
5885	}
5886
5887	case SVGA_3D_CMD_LOGICOPS_BITBLT:
5888	{
5889	SVGA3dCmdLogicOpsBitBlt pCmd = (SVGA3dCmdLogicOpsBitBlt )pvCmd;
5890	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5891	rcParse = vmsvga3dCmdLogicOpsBitBlt(pThisCC, idDXContext, pCmd, cbCmd);
5892	break;
5893	}
5894
5895	case SVGA_3D_CMD_LOGICOPS_TRANSBLT:
5896	{
5897	SVGA3dCmdLogicOpsTransBlt pCmd = (SVGA3dCmdLogicOpsTransBlt )pvCmd;
5898	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5899	rcParse = vmsvga3dCmdLogicOpsTransBlt(pThisCC, idDXContext, pCmd, cbCmd);
5900	break;
5901	}
5902
5903	case SVGA_3D_CMD_LOGICOPS_STRETCHBLT:
5904	{
5905	SVGA3dCmdLogicOpsStretchBlt pCmd = (SVGA3dCmdLogicOpsStretchBlt )pvCmd;
5906	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5907	rcParse = vmsvga3dCmdLogicOpsStretchBlt(pThisCC, idDXContext, pCmd, cbCmd);
5908	break;
5909	}
5910
5911	case SVGA_3D_CMD_LOGICOPS_COLORFILL:
5912	{
5913	SVGA3dCmdLogicOpsColorFill pCmd = (SVGA3dCmdLogicOpsColorFill )pvCmd;
5914	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5915	rcParse = vmsvga3dCmdLogicOpsColorFill(pThisCC, idDXContext, pCmd, cbCmd);
5916	break;
5917	}
5918
5919	case SVGA_3D_CMD_LOGICOPS_ALPHABLEND:
5920	{
5921	SVGA3dCmdLogicOpsAlphaBlend pCmd = (SVGA3dCmdLogicOpsAlphaBlend )pvCmd;
5922	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5923	rcParse = vmsvga3dCmdLogicOpsAlphaBlend(pThisCC, idDXContext, pCmd, cbCmd);
5924	break;
5925	}
5926
5927	case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND:
5928	{
5929	SVGA3dCmdLogicOpsClearTypeBlend pCmd = (SVGA3dCmdLogicOpsClearTypeBlend )pvCmd;
5930	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5931	rcParse = vmsvga3dCmdLogicOpsClearTypeBlend(pThisCC, idDXContext, pCmd, cbCmd);
5932	break;
5933	}
5934
5935	case SVGA_3D_CMD_RESERVED2_1:
5936	{
5937	VMSVGA_3D_CMD_NOTIMPL();
5938	break;
5939	}
5940
5941	case SVGA_3D_CMD_RESERVED2_2:
5942	{
5943	VMSVGA_3D_CMD_NOTIMPL();
5944	break;
5945	}
5946
5947	case SVGA_3D_CMD_DEFINE_GB_SURFACE_V4:
5948	{
5949	SVGA3dCmdDefineGBSurface_v4 pCmd = (SVGA3dCmdDefineGBSurface_v4 )pvCmd;
5950	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5951	rcParse = vmsvga3dCmdDefineGBSurface_v4(pThisCC, idDXContext, pCmd, cbCmd);
5952	break;
5953	}
5954
5955	case SVGA_3D_CMD_DX_SET_CS_UA_VIEWS:
5956	{
5957	SVGA3dCmdDXSetCSUAViews pCmd = (SVGA3dCmdDXSetCSUAViews )pvCmd;
5958	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5959	rcParse = vmsvga3dCmdDXSetCSUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5960	break;
5961	}
5962
5963	case SVGA_3D_CMD_DX_SET_MIN_LOD:
5964	{
5965	SVGA3dCmdDXSetMinLOD pCmd = (SVGA3dCmdDXSetMinLOD )pvCmd;
5966	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5967	rcParse = vmsvga3dCmdDXSetMinLOD(pThisCC, idDXContext, pCmd, cbCmd);
5968	break;
5969	}
5970
5971	case SVGA_3D_CMD_RESERVED2_3:
5972	{
5973	VMSVGA_3D_CMD_NOTIMPL();
5974	break;
5975	}
5976
5977	case SVGA_3D_CMD_RESERVED2_4:
5978	{
5979	VMSVGA_3D_CMD_NOTIMPL();
5980	break;
5981	}
5982
5983	case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2:
5984	{
5985	SVGA3dCmdDXDefineDepthStencilView_v2 pCmd = (SVGA3dCmdDXDefineDepthStencilView_v2 )pvCmd;
5986	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5987	rcParse = vmsvga3dCmdDXDefineDepthStencilView_v2(pThisCC, idDXContext, pCmd, cbCmd);
5988	break;
5989	}
5990
5991	case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB:
5992	{
5993	SVGA3dCmdDXDefineStreamOutputWithMob pCmd = (SVGA3dCmdDXDefineStreamOutputWithMob )pvCmd;
5994	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5995	rcParse = vmsvga3dCmdDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd, cbCmd);
5996	break;
5997	}
5998
5999	case SVGA_3D_CMD_DX_SET_SHADER_IFACE:
6000	{
6001	SVGA3dCmdDXSetShaderIface pCmd = (SVGA3dCmdDXSetShaderIface )pvCmd;
6002	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6003	rcParse = vmsvga3dCmdDXSetShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6004	break;
6005	}
6006
6007	case SVGA_3D_CMD_DX_BIND_STREAMOUTPUT:
6008	{
6009	SVGA3dCmdDXBindStreamOutput pCmd = (SVGA3dCmdDXBindStreamOutput )pvCmd;
6010	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6011	rcParse = vmsvga3dCmdDXBindStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
6012	break;
6013	}
6014
6015	case SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS:
6016	{
6017	SVGA3dCmdSurfaceStretchBltNonMSToMS pCmd = (SVGA3dCmdSurfaceStretchBltNonMSToMS )pvCmd;
6018	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6019	rcParse = vmsvga3dCmdSurfaceStretchBltNonMSToMS(pThisCC, idDXContext, pCmd, cbCmd);
6020	break;
6021	}
6022
6023	case SVGA_3D_CMD_DX_BIND_SHADER_IFACE:
6024	{
6025	SVGA3dCmdDXBindShaderIface pCmd = (SVGA3dCmdDXBindShaderIface )pvCmd;
6026	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6027	rcParse = vmsvga3dCmdDXBindShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6028	break;
6029	}
6030
6031	/* Unsupported commands. */
6032	case SVGA_3D_CMD_DEAD4: /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
6033	case SVGA_3D_CMD_DEAD5: /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
6034	case SVGA_3D_CMD_DEAD6: /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
6035	case SVGA_3D_CMD_DEAD7: /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
6036	case SVGA_3D_CMD_DEAD8: /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
6037	case SVGA_3D_CMD_DEAD9: /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
6038	case SVGA_3D_CMD_DEAD10: /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
6039	case SVGA_3D_CMD_DEAD11: /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
6040	/* Prevent the compiler warning. */
6041	case SVGA_3D_CMD_LEGACY_BASE:
6042	case SVGA_3D_CMD_MAX:
6043	case SVGA_3D_CMD_FUTURE_MAX:
6044	/* No 'default' case */
6045	STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
6046	ASSERT_GUEST_MSG_FAILED(("enmCmdId=%d\n", enmCmdId));
6047	LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
6048	rcParse = VERR_NOT_IMPLEMENTED;
6049	break;
6050	}
6051
6052	return VINF_SUCCESS;
6053	// return rcParse;
6054	}
6055	# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
6056	#endif /* VBOX_WITH_VMSVGA3D */
6057
6058
6059	/*
6060	*
6061	* Handlers for FIFO commands.
6062	*
6063	* Every handler takes the following parameters:
6064	*
6065	* pThis The shared VGA/VMSVGA state.
6066	* pThisCC The VGA/VMSVGA state for ring-3.
6067	* pCmd The command data.
6068	*/
6069
6070
6071	/* SVGA_CMD_UPDATE */
6072	void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
6073	{
6074	RT_NOREF(pThis);
6075	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6076
6077	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
6078	Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
6079
6080	/** @todo Multiple screens? */
6081	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6082	if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6083	return;
6084
6085	vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6086	}
6087
6088
6089	/* SVGA_CMD_UPDATE_VERBOSE */
6090	void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
6091	{
6092	RT_NOREF(pThis);
6093	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6094
6095	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
6096	Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
6097
6098	/** @todo Multiple screens? */
6099	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6100	if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6101	return;
6102
6103	vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6104	}
6105
6106
6107	/* SVGA_CMD_RECT_FILL */
6108	void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
6109	{
6110	RT_NOREF(pThis, pCmd);
6111	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6112
6113	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
6114	Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6115	LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
6116	}
6117
6118
6119	/* SVGA_CMD_RECT_COPY */
6120	void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
6121	{
6122	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6123
6124	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
6125	Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6126
6127	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6128	AssertPtrReturnVoid(pScreen);
6129
6130	/* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6131	ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6132	ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6133	ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6134	ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6135	ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6136	ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6137
6138	vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6139	pCmd->width, pCmd->height, pThis->vram_size);
6140	vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6141	}
6142
6143
6144	/* SVGA_CMD_RECT_ROP_COPY */
6145	void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
6146	{
6147	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6148
6149	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
6150	Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6151
6152	if (pCmd->rop != SVGA_ROP_COPY)
6153	{
6154	/* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
6155	* as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
6156	* respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
6157	* SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
6158	*/
6159	LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
6160	pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6161	return;
6162	}
6163
6164	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6165	AssertPtrReturnVoid(pScreen);
6166
6167	/* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6168	ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6169	ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6170	ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6171	ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6172	ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6173	ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6174
6175	vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6176	pCmd->width, pCmd->height, pThis->vram_size);
6177	vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6178	}
6179
6180
6181	/* SVGA_CMD_DISPLAY_CURSOR */
6182	void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
6183	{
6184	RT_NOREF(pThis, pCmd);
6185	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6186
6187	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
6188	Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
6189	LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
6190	}
6191
6192
6193	/* SVGA_CMD_MOVE_CURSOR */
6194	void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
6195	{
6196	RT_NOREF(pThis, pCmd);
6197	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6198
6199	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
6200	Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
6201	LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
6202	}
6203
6204
6205	/* SVGA_CMD_DEFINE_CURSOR */
6206	void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
6207	{
6208	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6209
6210	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
6211	Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
6212	pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
6213
6214	ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6215	ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
6216	ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
6217	RT_UNTRUSTED_VALIDATED_FENCE();
6218
6219	uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
6220	uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
6221	uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
6222
6223	uint8_t const pbSrcAndMask = (uint8_t const )(pCmd + 1);
6224	uint8_t const pbSrcXorMask = (uint8_t const )(pCmd + 1) + cbSrcAndMask;
6225
6226	uint32_t const cx = pCmd->width;
6227	uint32_t const cy = pCmd->height;
6228
6229	/*
6230	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
6231	* The AND data uses 8-bit aligned scanlines.
6232	* The XOR data must be starting on a 32-bit boundrary.
6233	*/
6234	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
6235	uint32_t cbDstAndMask = cbDstAndLine * cy;
6236	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
6237	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
6238
6239	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
6240	AssertReturnVoid(pbCopy);
6241
6242	/* Convert the AND mask. */
6243	uint8_t *pbDst = pbCopy;
6244	uint8_t const *pbSrc = pbSrcAndMask;
6245	switch (pCmd->andMaskDepth)
6246	{
6247	case 1:
6248	if (cbSrcAndLine == cbDstAndLine)
6249	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
6250	else
6251	{
6252	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
6253	for (uint32_t y = 0; y < cy; y++)
6254	{
6255	memcpy(pbDst, pbSrc, cbDstAndLine);
6256	pbDst += cbDstAndLine;
6257	pbSrc += cbSrcAndLine;
6258	}
6259	}
6260	break;
6261	/* Should take the XOR mask into account for the multi-bit AND mask. */
6262	case 8:
6263	for (uint32_t y = 0; y < cy; y++)
6264	{
6265	for (uint32_t x = 0; x < cx; )
6266	{
6267	uint8_t bDst = 0;
6268	uint8_t fBit = 0x80;
6269	do
6270	{
6271	uintptr_t const idxPal = pbSrc[x] * 3;
6272	if ((( pThis->last_palette[idxPal]
6273	\| (pThis->last_palette[idxPal] >> 8)
6274	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
6275	bDst \|= fBit;
6276	fBit >>= 1;
6277	x++;
6278	} while (x < cx && (x & 7));
6279	pbDst[(x - 1) / 8] = bDst;
6280	}
6281	pbDst += cbDstAndLine;
6282	pbSrc += cbSrcAndLine;
6283	}
6284	break;
6285	case 15:
6286	for (uint32_t y = 0; y < cy; y++)
6287	{
6288	for (uint32_t x = 0; x < cx; )
6289	{
6290	uint8_t bDst = 0;
6291	uint8_t fBit = 0x80;
6292	do
6293	{
6294	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
6295	bDst \|= fBit;
6296	fBit >>= 1;
6297	x++;
6298	} while (x < cx && (x & 7));
6299	pbDst[(x - 1) / 8] = bDst;
6300	}
6301	pbDst += cbDstAndLine;
6302	pbSrc += cbSrcAndLine;
6303	}
6304	break;
6305	case 16:
6306	for (uint32_t y = 0; y < cy; y++)
6307	{
6308	for (uint32_t x = 0; x < cx; )
6309	{
6310	uint8_t bDst = 0;
6311	uint8_t fBit = 0x80;
6312	do
6313	{
6314	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
6315	bDst \|= fBit;
6316	fBit >>= 1;
6317	x++;
6318	} while (x < cx && (x & 7));
6319	pbDst[(x - 1) / 8] = bDst;
6320	}
6321	pbDst += cbDstAndLine;
6322	pbSrc += cbSrcAndLine;
6323	}
6324	break;
6325	case 24:
6326	for (uint32_t y = 0; y < cy; y++)
6327	{
6328	for (uint32_t x = 0; x < cx; )
6329	{
6330	uint8_t bDst = 0;
6331	uint8_t fBit = 0x80;
6332	do
6333	{
6334	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
6335	bDst \|= fBit;
6336	fBit >>= 1;
6337	x++;
6338	} while (x < cx && (x & 7));
6339	pbDst[(x - 1) / 8] = bDst;
6340	}
6341	pbDst += cbDstAndLine;
6342	pbSrc += cbSrcAndLine;
6343	}
6344	break;
6345	case 32:
6346	for (uint32_t y = 0; y < cy; y++)
6347	{
6348	for (uint32_t x = 0; x < cx; )
6349	{
6350	uint8_t bDst = 0;
6351	uint8_t fBit = 0x80;
6352	do
6353	{
6354	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
6355	bDst \|= fBit;
6356	fBit >>= 1;
6357	x++;
6358	} while (x < cx && (x & 7));
6359	pbDst[(x - 1) / 8] = bDst;
6360	}
6361	pbDst += cbDstAndLine;
6362	pbSrc += cbSrcAndLine;
6363	}
6364	break;
6365	default:
6366	RTMemFreeZ(pbCopy, cbCopy);
6367	AssertFailedReturnVoid();
6368	}
6369
6370	/* Convert the XOR mask. */
6371	uint32_t pu32Dst = (uint32_t )(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
6372	pbSrc = pbSrcXorMask;
6373	switch (pCmd->xorMaskDepth)
6374	{
6375	case 1:
6376	for (uint32_t y = 0; y < cy; y++)
6377	{
6378	for (uint32_t x = 0; x < cx; )
6379	{
6380	/* most significant bit is the left most one. */
6381	uint8_t bSrc = pbSrc[x / 8];
6382	do
6383	{
6384	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
6385	bSrc <<= 1;
6386	x++;
6387	} while ((x & 7) && x < cx);
6388	}
6389	pbSrc += cbSrcXorLine;
6390	}
6391	break;
6392	case 8:
6393	for (uint32_t y = 0; y < cy; y++)
6394	{
6395	for (uint32_t x = 0; x < cx; x++)
6396	{
6397	uint32_t u = pThis->last_palette[pbSrc[x]];
6398	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
6399	}
6400	pbSrc += cbSrcXorLine;
6401	}
6402	break;
6403	case 15: /* Src: RGB-5-5-5 */
6404	for (uint32_t y = 0; y < cy; y++)
6405	{
6406	for (uint32_t x = 0; x < cx; x++)
6407	{
6408	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6409	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6410	((uValue >> 5) & 0x1f) << 3,
6411	((uValue >> 10) & 0x1f) << 3, 0);
6412	}
6413	pbSrc += cbSrcXorLine;
6414	}
6415	break;
6416	case 16: /* Src: RGB-5-6-5 */
6417	for (uint32_t y = 0; y < cy; y++)
6418	{
6419	for (uint32_t x = 0; x < cx; x++)
6420	{
6421	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6422	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6423	((uValue >> 5) & 0x3f) << 2,
6424	((uValue >> 11) & 0x1f) << 3, 0);
6425	}
6426	pbSrc += cbSrcXorLine;
6427	}
6428	break;
6429	case 24:
6430	for (uint32_t y = 0; y < cy; y++)
6431	{
6432	for (uint32_t x = 0; x < cx; x++)
6433	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
6434	pbSrc += cbSrcXorLine;
6435	}
6436	break;
6437	case 32:
6438	for (uint32_t y = 0; y < cy; y++)
6439	{
6440	for (uint32_t x = 0; x < cx; x++)
6441	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
6442	pbSrc += cbSrcXorLine;
6443	}
6444	break;
6445	default:
6446	RTMemFreeZ(pbCopy, cbCopy);
6447	AssertFailedReturnVoid();
6448	}
6449
6450	/*
6451	* Pass it to the frontend/whatever.
6452	*/
6453	vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /fAlpha/, pCmd->hotspotX, pCmd->hotspotY,
6454	cx, cy, pbCopy, cbCopy);
6455	}
6456
6457
6458	/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
6459	void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
6460	{
6461	RT_NOREF(pThis);
6462	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6463
6464	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
6465	Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
6466
6467	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
6468	ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6469	RT_UNTRUSTED_VALIDATED_FENCE();
6470
6471	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
6472	uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
6473	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
6474	uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
6475	uint32_t cbCursorShape = cbAndMask + cbXorMask;
6476
6477	uint8_t pCursorCopy = (uint8_t )RTMemAlloc(cbCursorShape);
6478	AssertPtrReturnVoid(pCursorCopy);
6479
6480	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
6481	memset(pCursorCopy, 0xff, cbAndMask);
6482	/* Colour data */
6483	memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
6484
6485	vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /fAlpha/, pCmd->hotspotX, pCmd->hotspotY,
6486	pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
6487	}
6488
6489
6490	/* SVGA_CMD_ESCAPE */
6491	void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
6492	{
6493	RT_NOREF(pThis);
6494	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6495
6496	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
6497
6498	if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
6499	{
6500	ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
6501	RT_UNTRUSTED_VALIDATED_FENCE();
6502
6503	uint32_t const cmd = (uint32_t )(pCmd + 1);
6504	Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
6505
6506	switch (cmd)
6507	{
6508	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
6509	{
6510	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pCmd + 1);
6511	ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
6512	RT_UNTRUSTED_VALIDATED_FENCE();
6513
6514	uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
6515
6516	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
6517	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
6518	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
6519	RT_NOREF_PV(pVideoCmd);
6520	break;
6521	}
6522
6523	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
6524	{
6525	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pCmd + 1);
6526	ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
6527	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
6528	RT_NOREF_PV(pVideoCmd);
6529	break;
6530	}
6531
6532	default:
6533	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
6534	break;
6535	}
6536	}
6537	else
6538	Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
6539	}
6540
6541
6542	/* SVGA_CMD_DEFINE_SCREEN */
6543	void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
6544	{
6545	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6546
6547	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
6548	Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
6549	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
6550	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
6551
6552	uint32_t const idScreen = pCmd->screen.id;
6553	ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6554
6555	uint32_t const uWidth = pCmd->screen.size.width;
6556	ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
6557
6558	uint32_t const uHeight = pCmd->screen.size.height;
6559	ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
6560
6561	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
6562	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
6563	ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
6564
6565	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
6566	ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
6567
6568	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
6569	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
6570	ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
6571	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
6572	RT_UNTRUSTED_VALIDATED_FENCE();
6573
6574	VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6575	pScreen->fDefined = true;
6576	pScreen->fModified = true;
6577	pScreen->fuScreen = pCmd->screen.flags;
6578	pScreen->idScreen = idScreen;
6579	if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING)))
6580	{
6581	/* Not blanked. */
6582	ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
6583	RT_UNTRUSTED_VALIDATED_FENCE();
6584
6585	pScreen->xOrigin = pCmd->screen.root.x;
6586	pScreen->yOrigin = pCmd->screen.root.y;
6587	pScreen->cWidth = uWidth;
6588	pScreen->cHeight = uHeight;
6589	pScreen->offVRAM = uScreenOffset;
6590	pScreen->cbPitch = cbPitch;
6591	pScreen->cBpp = 32;
6592	}
6593	else
6594	{
6595	/* Screen blanked. Keep old values. */
6596	}
6597
6598	pThis->svga.fGFBRegisters = false;
6599	vmsvgaR3ChangeMode(pThis, pThisCC);
6600
6601	#ifdef VBOX_WITH_VMSVGA3D
6602	if (RT_LIKELY(pThis->svga.f3DEnabled))
6603	vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
6604	#endif
6605	}
6606
6607
6608	/* SVGA_CMD_DESTROY_SCREEN */
6609	void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
6610	{
6611	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6612
6613	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
6614	Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
6615
6616	uint32_t const idScreen = pCmd->screenId;
6617	ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6618	RT_UNTRUSTED_VALIDATED_FENCE();
6619
6620	VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6621	pScreen->fModified = true;
6622	pScreen->fDefined = false;
6623	pScreen->idScreen = idScreen;
6624
6625	#ifdef VBOX_WITH_VMSVGA3D
6626	if (RT_LIKELY(pThis->svga.f3DEnabled))
6627	vmsvga3dDestroyScreen(pThisCC, pScreen);
6628	#endif
6629	vmsvgaR3ChangeMode(pThis, pThisCC);
6630	}
6631
6632
6633	/* SVGA_CMD_DEFINE_GMRFB */
6634	void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
6635	{
6636	RT_NOREF(pThis);
6637	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6638
6639	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
6640	Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
6641	pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
6642
6643	pSvgaR3State->GMRFB.ptr = pCmd->ptr;
6644	pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
6645	pSvgaR3State->GMRFB.format = pCmd->format;
6646	}
6647
6648
6649	/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
6650	void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
6651	{
6652	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6653
6654	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
6655	Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
6656	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
6657
6658	ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6659	RT_UNTRUSTED_VALIDATED_FENCE();
6660
6661	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
6662	AssertPtrReturnVoid(pScreen);
6663
6664	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
6665	AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6666
6667	/* Clip destRect to the screen dimensions. */
6668	SVGASignedRect screenRect;
6669	screenRect.left = 0;
6670	screenRect.top = 0;
6671	screenRect.right = pScreen->cWidth;
6672	screenRect.bottom = pScreen->cHeight;
6673	SVGASignedRect clipRect = pCmd->destRect;
6674	vmsvgaR3ClipRect(&screenRect, &clipRect);
6675	RT_UNTRUSTED_VALIDATED_FENCE();
6676
6677	uint32_t const width = clipRect.right - clipRect.left;
6678	uint32_t const height = clipRect.bottom - clipRect.top;
6679
6680	if ( width == 0
6681	\|\| height == 0)
6682	return; /* Nothing to do. */
6683
6684	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
6685	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
6686
6687	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
6688	* Prepare parameters for vmsvgaR3GmrTransfer.
6689	*/
6690	AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6691
6692	/* Destination: host buffer which describes the screen 0 VRAM.
6693	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6694	*/
6695	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6696	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6697	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6698	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6699	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6700	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6701	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6702	+ cbScanline * clipRect.top;
6703	int32_t const cbHstPitch = cbScanline;
6704
6705	/* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6706	SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6707	uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6708	+ pSvgaR3State->GMRFB.bytesPerLine * srcy;
6709	int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6710
6711	int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
6712	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6713	gstPtr, offGst, cbGstPitch,
6714	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6715	AssertRC(rc);
6716	vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
6717	}
6718
6719
6720	/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
6721	void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
6722	{
6723	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6724
6725	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
6726	/* Note! This can fetch 3d render results as well!! */
6727	Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
6728	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
6729
6730	ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6731	RT_UNTRUSTED_VALIDATED_FENCE();
6732
6733	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
6734	AssertPtrReturnVoid(pScreen);
6735
6736	/** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
6737	AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6738
6739	/* Clip destRect to the screen dimensions. */
6740	SVGASignedRect screenRect;
6741	screenRect.left = 0;
6742	screenRect.top = 0;
6743	screenRect.right = pScreen->cWidth;
6744	screenRect.bottom = pScreen->cHeight;
6745	SVGASignedRect clipRect = pCmd->srcRect;
6746	vmsvgaR3ClipRect(&screenRect, &clipRect);
6747	RT_UNTRUSTED_VALIDATED_FENCE();
6748
6749	uint32_t const width = clipRect.right - clipRect.left;
6750	uint32_t const height = clipRect.bottom - clipRect.top;
6751
6752	if ( width == 0
6753	\|\| height == 0)
6754	return; /* Nothing to do. */
6755
6756	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
6757	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
6758
6759	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
6760	* Prepare parameters for vmsvgaR3GmrTransfer.
6761	*/
6762	AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6763
6764	/* Source: host buffer which describes the screen 0 VRAM.
6765	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6766	*/
6767	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6768	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6769	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6770	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6771	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6772	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6773	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6774	+ cbScanline * clipRect.top;
6775	int32_t const cbHstPitch = cbScanline;
6776
6777	/* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6778	SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6779	uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6780	+ pSvgaR3State->GMRFB.bytesPerLine * dsty;
6781	int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6782
6783	int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
6784	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6785	gstPtr, offGst, cbGstPitch,
6786	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6787	AssertRC(rc);
6788	}
6789
6790
6791	/* SVGA_CMD_ANNOTATION_FILL */
6792	void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
6793	{
6794	RT_NOREF(pThis);
6795	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6796
6797	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
6798	Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
6799
6800	pSvgaR3State->colorAnnotation = pCmd->color;
6801	}
6802
6803
6804	/* SVGA_CMD_ANNOTATION_COPY */
6805	void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
6806	{
6807	RT_NOREF(pThis, pCmd);
6808	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6809
6810	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
6811	Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
6812
6813	AssertFailed();
6814	}
6815
6816
6817	#ifdef VBOX_WITH_VMSVGA3D
6818	/* SVGA_CMD_DEFINE_GMR2 */
6819	void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
6820	{
6821	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6822
6823	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
6824	Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
6825
6826	/* Validate current GMR id. */
6827	ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6828	ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
6829	RT_UNTRUSTED_VALIDATED_FENCE();
6830
6831	if (!pCmd->numPages)
6832	{
6833	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
6834	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6835	}
6836	else
6837	{
6838	PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6839	if (pGMR->cMaxPages)
6840	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
6841
6842	/* Not sure if we should always free the descriptor, but for simplicity
6843	we do so if the new size is smaller than the current. */
6844	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
6845	if (pGMR->cbTotal / X86_PAGE_SIZE > pCmd->numPages)
6846	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6847
6848	pGMR->cMaxPages = pCmd->numPages;
6849	/* The rest is done by the REMAP_GMR2 command. */
6850	}
6851	}
6852
6853
6854	/* SVGA_CMD_REMAP_GMR2 */
6855	void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
6856	{
6857	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6858
6859	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
6860	Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
6861
6862	/* Validate current GMR id and size. */
6863	ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6864	RT_UNTRUSTED_VALIDATED_FENCE();
6865	PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6866	ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
6867	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
6868	ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
6869
6870	if (pCmd->numPages == 0)
6871	return;
6872	RT_UNTRUSTED_VALIDATED_FENCE();
6873
6874	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
6875	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
6876
6877	/*
6878	* We flatten the existing descriptors into a page array, overwrite the
6879	* pages specified in this command and then recompress the descriptor.
6880	*/
6881	/** @todo Optimize the GMR remap algorithm! */
6882
6883	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
6884	uint64_t *paNewPage64 = NULL;
6885	if (pGMR->paDesc)
6886	{
6887	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
6888
6889	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
6890	AssertPtrReturnVoid(paNewPage64);
6891
6892	uint32_t idxPage = 0;
6893	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
6894	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
6895	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
6896	AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
6897	RT_UNTRUSTED_VALIDATED_FENCE();
6898	}
6899
6900	/* Free the old GMR if present. */
6901	if (pGMR->paDesc)
6902	RTMemFree(pGMR->paDesc);
6903
6904	/* Allocate the maximum amount possible (everything non-continuous) */
6905	PVMSVGAGMRDESCRIPTOR paDescs;
6906	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
6907	AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
6908
6909	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
6910	{
6911	/** @todo */
6912	AssertFailed();
6913	pGMR->numDescriptors = 0;
6914	}
6915	else
6916	{
6917	uint32_t paPages32 = (uint32_t )(pCmd + 1);
6918	uint64_t paPages64 = (uint64_t )(pCmd + 1);
6919	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
6920
6921	uint32_t cPages;
6922	if (paNewPage64)
6923	{
6924	/* Overwrite the old page array with the new page values. */
6925	if (fGCPhys64)
6926	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6927	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
6928	else
6929	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6930	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
6931
6932	/* Use the updated page array instead of the command data. */
6933	fGCPhys64 = true;
6934	paPages64 = paNewPage64;
6935	cPages = cNewTotalPages;
6936	}
6937	else
6938	cPages = pCmd->numPages;
6939
6940	/* The first page. */
6941	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
6942	* applied to paNewPage64. */
6943	RTGCPHYS GCPhys;
6944	if (fGCPhys64)
6945	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6946	else
6947	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
6948	paDescs[0].GCPhys = GCPhys;
6949	paDescs[0].numPages = 1;
6950
6951	/* Subsequent pages. */
6952	uint32_t iDescriptor = 0;
6953	for (uint32_t i = 1; i < cPages; i++)
6954	{
6955	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
6956	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6957	else
6958	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
6959
6960	/* Continuous physical memory? */
6961	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
6962	{
6963	Assert(paDescs[iDescriptor].numPages);
6964	paDescs[iDescriptor].numPages++;
6965	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
6966	}
6967	else
6968	{
6969	iDescriptor++;
6970	paDescs[iDescriptor].GCPhys = GCPhys;
6971	paDescs[iDescriptor].numPages = 1;
6972	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
6973	}
6974	}
6975
6976	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
6977	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
6978	pGMR->numDescriptors = iDescriptor + 1;
6979	}
6980
6981	if (paNewPage64)
6982	RTMemFree(paNewPage64);
6983	}
6984
6985
6986	/**
6987	* Free the specified GMR
6988	*
6989	* @param pThisCC The VGA/VMSVGA state for ring-3.
6990	* @param idGMR GMR id
6991	*/
6992	void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
6993	{
6994	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6995
6996	/* Free the old descriptor if present. */
6997	PGMR pGMR = &pSVGAState->paGMR[idGMR];
6998	if ( pGMR->numDescriptors
6999	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
7000	{
7001	# ifdef DEBUG_GMR_ACCESS
7002	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
7003	# endif
7004
7005	Assert(pGMR->paDesc);
7006	RTMemFree(pGMR->paDesc);
7007	pGMR->paDesc = NULL;
7008	pGMR->numDescriptors = 0;
7009	pGMR->cbTotal = 0;
7010	pGMR->cMaxPages = 0;
7011	}
7012	Assert(!pGMR->cMaxPages);
7013	Assert(!pGMR->cbTotal);
7014	}
7015	#endif /* VBOX_WITH_VMSVGA3D */
7016
7017
7018	/**
7019	* Copy between a GMR and a host memory buffer.
7020	*
7021	* @returns VBox status code.
7022	* @param pThis The shared VGA/VMSVGA instance data.
7023	* @param pThisCC The VGA/VMSVGA state for ring-3.
7024	* @param enmTransferType Transfer type (read/write)
7025	* @param pbHstBuf Host buffer pointer (valid)
7026	* @param cbHstBuf Size of host buffer (valid)
7027	* @param offHst Host buffer offset of the first scanline
7028	* @param cbHstPitch Destination buffer pitch
7029	* @param gstPtr GMR description
7030	* @param offGst Guest buffer offset of the first scanline
7031	* @param cbGstPitch Guest buffer pitch
7032	* @param cbWidth Width in bytes to copy
7033	* @param cHeight Number of scanllines to copy
7034	*/
7035	int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
7036	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
7037	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
7038	uint32_t cbWidth, uint32_t cHeight)
7039	{
7040	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7041	PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
7042	int rc;
7043
7044	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
7045	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
7046	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
7047	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
7048	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
7049
7050	PGMR pGMR;
7051	uint32_t cbGmr; /* The GMR size in bytes. */
7052	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7053	{
7054	pGMR = NULL;
7055	cbGmr = pThis->vram_size;
7056	}
7057	else
7058	{
7059	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
7060	RT_UNTRUSTED_VALIDATED_FENCE();
7061	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
7062	cbGmr = pGMR->cbTotal;
7063	}
7064
7065	/*
7066	* GMR
7067	*/
7068	/* Calculate GMR offset of the data to be copied. */
7069	AssertMsgReturn(gstPtr.offset < cbGmr,
7070	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7071	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7072	VERR_INVALID_PARAMETER);
7073	RT_UNTRUSTED_VALIDATED_FENCE();
7074	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
7075	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7076	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7077	VERR_INVALID_PARAMETER);
7078	RT_UNTRUSTED_VALIDATED_FENCE();
7079	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
7080
7081	/* Verify that cbWidth is less than scanline and fits into the GMR. */
7082	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
7083	AssertMsgReturn(cbGmrScanline != 0,
7084	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7085	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7086	VERR_INVALID_PARAMETER);
7087	RT_UNTRUSTED_VALIDATED_FENCE();
7088	AssertMsgReturn(cbWidth <= cbGmrScanline,
7089	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7090	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7091	VERR_INVALID_PARAMETER);
7092	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
7093	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7094	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7095	VERR_INVALID_PARAMETER);
7096	RT_UNTRUSTED_VALIDATED_FENCE();
7097
7098	/* How many bytes are available for the data in the GMR. */
7099	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
7100
7101	/* How many scanlines would fit into the available data. */
7102	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
7103	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
7104	if (cbWidth <= cbGmrLastScanline)
7105	++cGmrScanlines;
7106
7107	if (cHeight > cGmrScanlines)
7108	cHeight = cGmrScanlines;
7109
7110	AssertMsgReturn(cHeight > 0,
7111	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7112	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7113	VERR_INVALID_PARAMETER);
7114	RT_UNTRUSTED_VALIDATED_FENCE();
7115
7116	/*
7117	* Host buffer.
7118	*/
7119	AssertMsgReturn(offHst < cbHstBuf,
7120	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7121	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7122	VERR_INVALID_PARAMETER);
7123
7124	/* Verify that cbWidth is less than scanline and fits into the buffer. */
7125	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
7126	AssertMsgReturn(cbHstScanline != 0,
7127	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7128	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7129	VERR_INVALID_PARAMETER);
7130	AssertMsgReturn(cbWidth <= cbHstScanline,
7131	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7132	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7133	VERR_INVALID_PARAMETER);
7134	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
7135	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7136	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7137	VERR_INVALID_PARAMETER);
7138
7139	/* How many bytes are available for the data in the buffer. */
7140	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
7141
7142	/* How many scanlines would fit into the available data. */
7143	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
7144	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
7145	if (cbWidth <= cbHstLastScanline)
7146	++cHstScanlines;
7147
7148	if (cHeight > cHstScanlines)
7149	cHeight = cHstScanlines;
7150
7151	AssertMsgReturn(cHeight > 0,
7152	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7153	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7154	VERR_INVALID_PARAMETER);
7155
7156	uint8_t *pbHst = pbHstBuf + offHst;
7157
7158	/* Shortcut for the framebuffer. */
7159	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7160	{
7161	uint8_t *pbGst = pThisCC->pbVRam + offGmr;
7162
7163	uint8_t const *pbSrc;
7164	int32_t cbSrcPitch;
7165	uint8_t *pbDst;
7166	int32_t cbDstPitch;
7167
7168	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
7169	{
7170	pbSrc = pbHst;
7171	cbSrcPitch = cbHstPitch;
7172	pbDst = pbGst;
7173	cbDstPitch = cbGstPitch;
7174	}
7175	else
7176	{
7177	pbSrc = pbGst;
7178	cbSrcPitch = cbGstPitch;
7179	pbDst = pbHst;
7180	cbDstPitch = cbHstPitch;
7181	}
7182
7183	if ( cbWidth == (uint32_t)cbGstPitch
7184	&& cbGstPitch == cbHstPitch)
7185	{
7186	/* Entire scanlines, positive pitch. */
7187	memcpy(pbDst, pbSrc, cbWidth * cHeight);
7188	}
7189	else
7190	{
7191	for (uint32_t i = 0; i < cHeight; ++i)
7192	{
7193	memcpy(pbDst, pbSrc, cbWidth);
7194
7195	pbDst += cbDstPitch;
7196	pbSrc += cbSrcPitch;
7197	}
7198	}
7199	return VINF_SUCCESS;
7200	}
7201
7202	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
7203	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
7204
7205	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
7206	uint32_t iDesc = 0; /* Index in the descriptor array. */
7207	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
7208	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
7209	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
7210	for (uint32_t i = 0; i < cHeight; ++i)
7211	{
7212	uint32_t cbCurrentWidth = cbWidth;
7213	uint32_t offGmrCurrent = offGmrScanline;
7214	uint8_t *pbCurrentHost = pbHstScanline;
7215
7216	/* Find the right descriptor */
7217	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
7218	{
7219	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
7220	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
7221	++iDesc;
7222	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7223	}
7224
7225	while (cbCurrentWidth)
7226	{
7227	uint32_t cbToCopy;
7228
7229	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
7230	{
7231	cbToCopy = cbCurrentWidth;
7232	}
7233	else
7234	{
7235	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
7236	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
7237	}
7238
7239	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
7240
7241	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
7242
7243	/*
7244	* We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read\|Write] as the
7245	* guest-side VMSVGA driver seems to allocate non-DMA (physical memory) addresses,
7246	* see @bugref{9654#c75}.
7247	*/
7248	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
7249	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7250	else
7251	rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7252	AssertRCBreak(rc);
7253
7254	cbCurrentWidth -= cbToCopy;
7255	offGmrCurrent += cbToCopy;
7256	pbCurrentHost += cbToCopy;
7257
7258	/* Go to the next descriptor if there's anything left. */
7259	if (cbCurrentWidth)
7260	{
7261	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
7262	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
7263	++iDesc;
7264	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7265	}
7266	}
7267
7268	offGmrScanline += cbGstPitch;
7269	pbHstScanline += cbHstPitch;
7270	}
7271
7272	return VINF_SUCCESS;
7273	}
7274
7275
7276	/**
7277	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
7278	*
7279	* @param pSizeSrc Source surface dimensions.
7280	* @param pSizeDest Destination surface dimensions.
7281	* @param pBox Coordinates to be clipped.
7282	*/
7283	void vmsvgaR3ClipCopyBox(const SVGA3dSize pSizeSrc, const SVGA3dSize pSizeDest, SVGA3dCopyBox *pBox)
7284	{
7285	/* Src x, w */
7286	if (pBox->srcx > pSizeSrc->width)
7287	pBox->srcx = pSizeSrc->width;
7288	if (pBox->w > pSizeSrc->width - pBox->srcx)
7289	pBox->w = pSizeSrc->width - pBox->srcx;
7290
7291	/* Src y, h */
7292	if (pBox->srcy > pSizeSrc->height)
7293	pBox->srcy = pSizeSrc->height;
7294	if (pBox->h > pSizeSrc->height - pBox->srcy)
7295	pBox->h = pSizeSrc->height - pBox->srcy;
7296
7297	/* Src z, d */
7298	if (pBox->srcz > pSizeSrc->depth)
7299	pBox->srcz = pSizeSrc->depth;
7300	if (pBox->d > pSizeSrc->depth - pBox->srcz)
7301	pBox->d = pSizeSrc->depth - pBox->srcz;
7302
7303	/* Dest x, w */
7304	if (pBox->x > pSizeDest->width)
7305	pBox->x = pSizeDest->width;
7306	if (pBox->w > pSizeDest->width - pBox->x)
7307	pBox->w = pSizeDest->width - pBox->x;
7308
7309	/* Dest y, h */
7310	if (pBox->y > pSizeDest->height)
7311	pBox->y = pSizeDest->height;
7312	if (pBox->h > pSizeDest->height - pBox->y)
7313	pBox->h = pSizeDest->height - pBox->y;
7314
7315	/* Dest z, d */
7316	if (pBox->z > pSizeDest->depth)
7317	pBox->z = pSizeDest->depth;
7318	if (pBox->d > pSizeDest->depth - pBox->z)
7319	pBox->d = pSizeDest->depth - pBox->z;
7320	}
7321
7322
7323	/**
7324	* Unsigned coordinates in pBox. Clip to [0; pSize).
7325	*
7326	* @param pSize Source surface dimensions.
7327	* @param pBox Coordinates to be clipped.
7328	*/
7329	void vmsvgaR3ClipBox(const SVGA3dSize pSize, SVGA3dBox pBox)
7330	{
7331	/* x, w */
7332	if (pBox->x > pSize->width)
7333	pBox->x = pSize->width;
7334	if (pBox->w > pSize->width - pBox->x)
7335	pBox->w = pSize->width - pBox->x;
7336
7337	/* y, h */
7338	if (pBox->y > pSize->height)
7339	pBox->y = pSize->height;
7340	if (pBox->h > pSize->height - pBox->y)
7341	pBox->h = pSize->height - pBox->y;
7342
7343	/* z, d */
7344	if (pBox->z > pSize->depth)
7345	pBox->z = pSize->depth;
7346	if (pBox->d > pSize->depth - pBox->z)
7347	pBox->d = pSize->depth - pBox->z;
7348	}
7349
7350
7351	/**
7352	* Clip.
7353	*
7354	* @param pBound Bounding rectangle.
7355	* @param pRect Rectangle to be clipped.
7356	*/
7357	void vmsvgaR3ClipRect(SVGASignedRect const pBound, SVGASignedRect pRect)
7358	{
7359	int32_t left;
7360	int32_t top;
7361	int32_t right;
7362	int32_t bottom;
7363
7364	/* Right order. */
7365	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
7366	if (pRect->left < pRect->right)
7367	{
7368	left = pRect->left;
7369	right = pRect->right;
7370	}
7371	else
7372	{
7373	left = pRect->right;
7374	right = pRect->left;
7375	}
7376	if (pRect->top < pRect->bottom)
7377	{
7378	top = pRect->top;
7379	bottom = pRect->bottom;
7380	}
7381	else
7382	{
7383	top = pRect->bottom;
7384	bottom = pRect->top;
7385	}
7386
7387	if (left < pBound->left)
7388	left = pBound->left;
7389	if (right < pBound->left)
7390	right = pBound->left;
7391
7392	if (left > pBound->right)
7393	left = pBound->right;
7394	if (right > pBound->right)
7395	right = pBound->right;
7396
7397	if (top < pBound->top)
7398	top = pBound->top;
7399	if (bottom < pBound->top)
7400	bottom = pBound->top;
7401
7402	if (top > pBound->bottom)
7403	top = pBound->bottom;
7404	if (bottom > pBound->bottom)
7405	bottom = pBound->bottom;
7406
7407	pRect->left = left;
7408	pRect->right = right;
7409	pRect->top = top;
7410	pRect->bottom = bottom;
7411	}
7412
7413
7414	/**
7415	* Clip.
7416	*
7417	* @param pBound Bounding rectangle.
7418	* @param pRect Rectangle to be clipped.
7419	*/
7420	void vmsvgaR3Clip3dRect(SVGA3dRect const pBound, SVGA3dRect RT_UNTRUSTED_GUEST pRect)
7421	{
7422	uint32_t const leftBound = pBound->x;
7423	uint32_t const rightBound = pBound->x + pBound->w;
7424	uint32_t const topBound = pBound->y;
7425	uint32_t const bottomBound = pBound->y + pBound->h;
7426
7427	uint32_t x = pRect->x;
7428	uint32_t y = pRect->y;
7429	uint32_t w = pRect->w;
7430	uint32_t h = pRect->h;
7431
7432	/* Make sure that right and bottom coordinates can be safely computed. */
7433	if (x > rightBound)
7434	x = rightBound;
7435	if (w > rightBound - x)
7436	w = rightBound - x;
7437	if (y > bottomBound)
7438	y = bottomBound;
7439	if (h > bottomBound - y)
7440	h = bottomBound - y;
7441
7442	/* Switch from x, y, w, h to left, top, right, bottom. */
7443	uint32_t left = x;
7444	uint32_t right = x + w;
7445	uint32_t top = y;
7446	uint32_t bottom = y + h;
7447
7448	/* A standard left, right, bottom, top clipping. */
7449	if (left < leftBound)
7450	left = leftBound;
7451	if (right < leftBound)
7452	right = leftBound;
7453
7454	if (left > rightBound)
7455	left = rightBound;
7456	if (right > rightBound)
7457	right = rightBound;
7458
7459	if (top < topBound)
7460	top = topBound;
7461	if (bottom < topBound)
7462	bottom = topBound;
7463
7464	if (top > bottomBound)
7465	top = bottomBound;
7466	if (bottom > bottomBound)
7467	bottom = bottomBound;
7468
7469	/* Back to x, y, w, h representation. */
7470	pRect->x = left;
7471	pRect->y = top;
7472	pRect->w = right - left;
7473	pRect->h = bottom - top;
7474	}
7475

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp@ 92162

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