VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp@ 88904

Last change on this file since 88904 was 88904, checked in by vboxsync, 4 years ago

Devices/Graphics: Helpers to read and write guest MOB memory; fixed some commands; started to deal with shared surfaces; make code more straightforward. bugref:9830
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 257.9 KB
Line 
1/* $Id: DevVGA-SVGA-cmd.cpp 88904 2021-05-06 14:02:43Z vboxsync $ */
2/** @file
3 * VMware SVGA device - implementation of VMSVGA commands.
4 */
5
6/*
7 * Copyright (C) 2013-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef IN_RING3
19# error "DevVGA-SVGA-cmd.cpp is only for ring-3 code"
20#endif
21
22
23#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
24#include <iprt/mem.h>
25#include <VBox/AssertGuest.h>
26#include <VBox/log.h>
27#include <VBox/vmm/pdmdev.h>
28#include <VBoxVideo.h>
29
30/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
31#include "DevVGA.h"
32
33/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
34#ifdef VBOX_WITH_VMSVGA3D
35# include "DevVGA-SVGA3d.h"
36#endif
37#include "DevVGA-SVGA-internal.h"
38
39#ifdef DUMP_BITMAPS
40# include <iprt/formats/bmp.h>
41# include <stdio.h>
42#endif
43
44#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
45# define SVGA_CASE_ID2STR(idx) case idx: return #idx
46
47static const char *vmsvgaFifo3dCmdToString(SVGAFifo3dCmdId enmCmdId)
48{
49 switch (enmCmdId)
50 {
51 SVGA_CASE_ID2STR(SVGA_3D_CMD_LEGACY_BASE);
52 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
53 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
54 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
55 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
56 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
57 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
58 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
59 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
60 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
61 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
62 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
63 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
64 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
65 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
66 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
67 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
68 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
69 SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
70 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
71 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
72 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
73 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
74 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
75 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
76 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
77 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
78 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
79 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
80 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
81 SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
82 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
83 SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
84 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD4); /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
85 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD5); /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
86 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD6); /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
87 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD7); /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
88 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD8); /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
89 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD9); /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
90 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD10); /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
91 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD11); /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
92 SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
93 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
94 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
95 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD1);
96 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
97 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD12); /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
98 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD13); /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
99 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD14); /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
100 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD15); /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
101 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD16); /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
102 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD17); /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
103 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
104 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
105 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
106 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
107 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
108 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
109 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
110 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
111 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
112 SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
113 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
114 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
115 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
116 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
117 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
118 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
119 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
120 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
121 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
122 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
123 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
124 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
125 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
126 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
127 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
128 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
129 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
130 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
131 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
132 SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
133 SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
134 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
135 SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
136 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
137 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
138 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
139 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
140 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
141 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
142 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
143 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
144 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
145 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
146 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
147 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
148 SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
149 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
150 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
151 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
152 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
153 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
154 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
155 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
156 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
157 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
158 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
159 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
160 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
161 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
162 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
163 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
164 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
165 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
166 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
167 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
168 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
169 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
170 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
171 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
172 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
173 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
174 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
175 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
176 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
177 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
178 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
179 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
180 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
181 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
182 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
183 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
184 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
185 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
186 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
187 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
188 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
189 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
190 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
191 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
192 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRESENTBLT);
193 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
194 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
195 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
196 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
197 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
198 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
199 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
200 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
201 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
202 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
203 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
204 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
205 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
206 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
207 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
208 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
209 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
210 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
211 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
212 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
213 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
214 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
215 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
216 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
217 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
218 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
219 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
220 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
221 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
222 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
223 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
224 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
225 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
226 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
227 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
228 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
229 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
230 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
231 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
232 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
233 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
234 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
235 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET);
236 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET);
237 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET);
238 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
239 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_COPY);
240 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED1);
241 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2);
242 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED3);
243 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED4);
244 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED5);
245 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED6);
246 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED7);
247 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED8);
248 SVGA_CASE_ID2STR(SVGA_3D_CMD_GROW_OTABLE);
249 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GROW_COTABLE);
250 SVGA_CASE_ID2STR(SVGA_3D_CMD_INTRA_SURFACE_COPY);
251 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V3);
252 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESOLVE_COPY);
253 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_RESOLVE_COPY);
254 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT_REGION);
255 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT);
256 SVGA_CASE_ID2STR(SVGA_3D_CMD_WHOLE_SURFACE_COPY);
257 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_UA_VIEW);
258 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_UA_VIEW);
259 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT);
260 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT);
261 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT);
262 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_UA_VIEWS);
263 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT);
264 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT);
265 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH);
266 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH_INDIRECT);
267 SVGA_CASE_ID2STR(SVGA_3D_CMD_WRITE_ZERO_SURFACE);
268 SVGA_CASE_ID2STR(SVGA_3D_CMD_HINT_ZERO_SURFACE);
269 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER);
270 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT);
271 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
272 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
273 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
274 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
275 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
276 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
277 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_1);
278 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_2);
279 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4);
280 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS);
281 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_MIN_LOD);
282 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_3);
283 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_4);
284 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2);
285 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB);
286 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_IFACE);
287 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT);
288 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS);
289 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER_IFACE);
290 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAX);
291 SVGA_CASE_ID2STR(SVGA_3D_CMD_FUTURE_MAX);
292 }
293 return "UNKNOWN_3D";
294}
295
296/**
297 * FIFO command name lookup
298 *
299 * @returns FIFO command string or "UNKNOWN"
300 * @param u32Cmd FIFO command
301 */
302const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
303{
304 switch (u32Cmd)
305 {
306 SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
307 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
308 SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
309 SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
310 SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
311 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
312 SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
313 SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
314 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
315 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
316 SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
317 SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
318 SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
319 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
320 SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
321 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
322 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
323 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
324 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
325 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
326 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
327 SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
328 SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
329 SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
330 SVGA_CASE_ID2STR(SVGA_CMD_NOP);
331 SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
332 SVGA_CASE_ID2STR(SVGA_CMD_MAX);
333 default:
334 if ( u32Cmd >= SVGA_3D_CMD_BASE
335 && u32Cmd < SVGA_3D_CMD_MAX)
336 return vmsvgaFifo3dCmdToString((SVGAFifo3dCmdId)u32Cmd);
337 }
338 return "UNKNOWN";
339}
340# undef SVGA_CASE_ID2STR
341#endif /* LOG_ENABLED || VBOX_STRICT */
342
343
344/*
345 *
346 * Guest-Backed Objects (GBO).
347 *
348 */
349
350/**
351 * HC access handler for GBOs which require write protection, i.e. OTables, etc.
352 *
353 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
354 * @param pVM VM Handle.
355 * @param pVCpu The cross context CPU structure for the calling EMT.
356 * @param GCPhys The physical address the guest is writing to.
357 * @param pvPhys The HC mapping of that address.
358 * @param pvBuf What the guest is reading/writing.
359 * @param cbBuf How much it's reading/writing.
360 * @param enmAccessType The access type.
361 * @param enmOrigin Who is making the access.
362 * @param pvUser User argument.
363 */
364DECLCALLBACK(VBOXSTRICTRC)
365vmsvgaR3GboAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
366 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
367{
368 RT_NOREF(pVM, pVCpu, pvPhys, enmAccessType);
369
370 if (RT_LIKELY(enmOrigin == PGMACCESSORIGIN_DEVICE || enmOrigin == PGMACCESSORIGIN_DEBUGGER))
371 return VINF_PGM_HANDLER_DO_DEFAULT;
372
373 PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
374 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
375 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
376 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
377
378 /*
379 * The guest is not allowed to access the memory.
380 * Set the error condition.
381 */
382 ASMAtomicWriteBool(&pThis->svga.fBadGuest, true);
383
384 /* Try to find the GBO which the guest is accessing. */
385 char const *pszTarget = NULL;
386 for (uint32_t i = 0; i < RT_ELEMENTS(pSvgaR3State->aGboOTables) && !pszTarget; ++i)
387 {
388 PVMSVGAGBO pGbo = &pSvgaR3State->aGboOTables[i];
389 if (pGbo->cDescriptors)
390 {
391 for (uint32_t j = 0; j < pGbo->cDescriptors; ++j)
392 {
393 if ( GCPhys >= pGbo->paDescriptors[j].GCPhys
394 && GCPhys < pGbo->paDescriptors[j].GCPhys + pGbo->paDescriptors[j].cPages * PAGE_SIZE)
395 {
396 switch (i)
397 {
398 case SVGA_OTABLE_MOB: pszTarget = "SVGA_OTABLE_MOB"; break;
399 case SVGA_OTABLE_SURFACE: pszTarget = "SVGA_OTABLE_SURFACE"; break;
400 case SVGA_OTABLE_CONTEXT: pszTarget = "SVGA_OTABLE_CONTEXT"; break;
401 case SVGA_OTABLE_SHADER: pszTarget = "SVGA_OTABLE_SHADER"; break;
402 case SVGA_OTABLE_SCREENTARGET: pszTarget = "SVGA_OTABLE_SCREENTARGET"; break;
403 case SVGA_OTABLE_DXCONTEXT: pszTarget = "SVGA_OTABLE_DXCONTEXT"; break;
404 default: pszTarget = "Unknown OTABLE"; break;
405 }
406 break;
407 }
408 }
409 }
410 }
411
412 LogRelMax(8, ("VMSVGA: invalid guest access to page %RGp, target %s:\n"
413 "%.*Rhxd\n",
414 GCPhys, pszTarget ? pszTarget : "unknown", RT_MIN(cbBuf, 256), pvBuf));
415
416 return VINF_PGM_HANDLER_DO_DEFAULT;
417}
418
419
420static int vmsvgaR3GboCreate(PVMSVGAR3STATE pSvgaR3State, SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, bool fGCPhys64, bool fWriteProtected, PVMSVGAGBO pGbo)
421{
422 ASSERT_GUEST_RETURN(sizeInBytes <= _128M, VERR_INVALID_PARAMETER); /** @todo Less than SVGA_REG_MOB_MAX_SIZE */
423
424 /*
425 * The 'baseAddress' is a page number and points to the 'root page' of the GBO.
426 * Content of the root page depends on the ptDepth value:
427 * SVGA3D_MOBFMT_PTDEPTH[64]_0 - the only data page;
428 * SVGA3D_MOBFMT_PTDEPTH[64]_1 - array of page numbers for data pages;
429 * SVGA3D_MOBFMT_PTDEPTH[64]_2 - array of page numbers for SVGA3D_MOBFMT_PTDEPTH[64]_1 pages.
430 * The code below extracts the page addresses of the GBO.
431 */
432
433 /* Verify and normalize the ptDepth value. */
434 if (RT_LIKELY( ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0
435 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1
436 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2))
437 ASSERT_GUEST_RETURN(fGCPhys64, VERR_INVALID_PARAMETER);
438 else if ( ptDepth == SVGA3D_MOBFMT_PTDEPTH_0
439 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_1
440 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_2)
441 {
442 ASSERT_GUEST_RETURN(!fGCPhys64, VERR_INVALID_PARAMETER);
443 /* Shift ptDepth to the SVGA3D_MOBFMT_PTDEPTH64_x range. */
444 ptDepth = (SVGAMobFormat)(ptDepth + SVGA3D_MOBFMT_PTDEPTH64_0 - SVGA3D_MOBFMT_PTDEPTH_0);
445 }
446 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
447 { }
448 else
449 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
450
451 uint32_t const cPPNsPerPage = X86_PAGE_SIZE / (fGCPhys64 ? sizeof(PPN64) : sizeof(PPN));
452
453 pGbo->cbTotal = sizeInBytes;
454 pGbo->cTotalPages = (sizeInBytes + X86_PAGE_SIZE - 1) >> X86_PAGE_SHIFT;
455
456 /* Allocate the maximum amount possible (everything non-continuous) */
457 PVMSVGAGBODESCRIPTOR paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAlloc(pGbo->cTotalPages * sizeof(VMSVGAGBODESCRIPTOR));
458 AssertReturn(paDescriptors, VERR_NO_MEMORY);
459
460 int rc = VINF_SUCCESS;
461 if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0)
462 {
463 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages == 1,
464 RTMemFree(paDescriptors),
465 VERR_INVALID_PARAMETER);
466
467 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
468 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
469 paDescriptors[0].GCPhys = GCPhys;
470 paDescriptors[0].cPages = 1;
471 }
472 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1)
473 {
474 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage,
475 RTMemFree(paDescriptors),
476 VERR_INVALID_PARAMETER);
477
478 /* Read the root page. */
479 uint8_t au8RootPage[X86_PAGE_SIZE];
480 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
481 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPage, sizeof(au8RootPage));
482 if (RT_SUCCESS(rc))
483 {
484 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
485 PPN *paPPN32 = (PPN *)&au8RootPage[0];
486 for (uint32_t iPPN = 0; iPPN < pGbo->cTotalPages; ++iPPN)
487 {
488 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
489 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
490 paDescriptors[iPPN].GCPhys = GCPhys;
491 paDescriptors[iPPN].cPages = 1;
492 }
493 }
494 }
495 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2)
496 {
497 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage * cPPNsPerPage,
498 RTMemFree(paDescriptors),
499 VERR_INVALID_PARAMETER);
500
501 /* Read the Level2 root page. */
502 uint8_t au8RootPageLevel2[X86_PAGE_SIZE];
503 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
504 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPageLevel2, sizeof(au8RootPageLevel2));
505 if (RT_SUCCESS(rc))
506 {
507 uint32_t cPagesLeft = pGbo->cTotalPages;
508
509 PPN64 *paPPN64Level2 = (PPN64 *)&au8RootPageLevel2[0];
510 PPN *paPPN32Level2 = (PPN *)&au8RootPageLevel2[0];
511
512 uint32_t const cPPNsLevel2 = (pGbo->cTotalPages + cPPNsPerPage - 1) / cPPNsPerPage;
513 for (uint32_t iPPNLevel2 = 0; iPPNLevel2 < cPPNsLevel2; ++iPPNLevel2)
514 {
515 /* Read the Level1 root page. */
516 uint8_t au8RootPage[X86_PAGE_SIZE];
517 RTGCPHYS GCPhysLevel1 = (RTGCPHYS)(fGCPhys64 ? paPPN64Level2[iPPNLevel2] : paPPN32Level2[iPPNLevel2]) << X86_PAGE_SHIFT;
518 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
519 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhysLevel1, &au8RootPage, sizeof(au8RootPage));
520 if (RT_SUCCESS(rc))
521 {
522 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
523 PPN *paPPN32 = (PPN *)&au8RootPage[0];
524
525 uint32_t const cPPNs = RT_MIN(cPagesLeft, cPPNsPerPage);
526 for (uint32_t iPPN = 0; iPPN < cPPNs; ++iPPN)
527 {
528 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
529 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
530 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].GCPhys = GCPhys;
531 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].cPages = 1;
532 }
533 cPagesLeft -= cPPNs;
534 }
535 }
536 }
537 }
538 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
539 {
540 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
541 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
542 paDescriptors[0].GCPhys = GCPhys;
543 paDescriptors[0].cPages = pGbo->cTotalPages;
544 }
545 else
546 {
547 AssertFailed();
548 return VERR_INTERNAL_ERROR; /* ptDepth should be already verified. */
549 }
550
551 /* Compress the descriptors. */
552 if (ptDepth != SVGA3D_MOBFMT_RANGE)
553 {
554 uint32_t iDescriptor = 0;
555 for (uint32_t i = 1; i < pGbo->cTotalPages; ++i)
556 {
557 /* Continuous physical memory? */
558 if (paDescriptors[i].GCPhys == paDescriptors[iDescriptor].GCPhys + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
559 {
560 Assert(paDescriptors[iDescriptor].cPages);
561 paDescriptors[iDescriptor].cPages++;
562 Log5Func(("Page %x GCPhys=%RGp successor\n", i, paDescriptors[i].GCPhys));
563 }
564 else
565 {
566 iDescriptor++;
567 paDescriptors[iDescriptor].GCPhys = paDescriptors[i].GCPhys;
568 paDescriptors[iDescriptor].cPages = 1;
569 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescriptors[iDescriptor].GCPhys));
570 }
571 }
572
573 pGbo->cDescriptors = iDescriptor + 1;
574 Log5Func(("Nr of descriptors %d\n", pGbo->cDescriptors));
575 }
576 else
577 pGbo->cDescriptors = 1;
578
579 if (RT_LIKELY(pGbo->cDescriptors < pGbo->cTotalPages))
580 {
581 pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemRealloc(paDescriptors, pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
582 AssertReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
583 }
584 else
585 pGbo->paDescriptors = paDescriptors;
586
587#if 1 /// @todo PGMHandlerPhysicalRegister asserts deep in PGM code with enmKind of a page being out of range.
588fWriteProtected = false;
589#endif
590 if (fWriteProtected)
591 {
592 pGbo->fGboFlags |= VMSVGAGBO_F_WRITE_PROTECTED;
593 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
594 {
595 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pSvgaR3State->pDevIns),
596 pGbo->paDescriptors[i].GCPhys, pGbo->paDescriptors[i].GCPhys + pGbo->paDescriptors[i].cPages * PAGE_SIZE - 1,
597 pSvgaR3State->hGboAccessHandlerType, pSvgaR3State->pDevIns, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GBO");
598 AssertRC(rc);
599 }
600 }
601
602 return VINF_SUCCESS;
603}
604
605
606static void vmsvgaR3GboDestroy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
607{
608 if (RT_LIKELY(VMSVGA_IS_GBO_CREATED(pGbo)))
609 {
610 if (pGbo->fGboFlags & VMSVGAGBO_F_WRITE_PROTECTED)
611 {
612 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
613 {
614 int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pSvgaR3State->pDevIns), pGbo->paDescriptors[i].GCPhys);
615 AssertRC(rc);
616 }
617 }
618 RTMemFree(pGbo->paDescriptors);
619 RT_ZERO(pGbo);
620 }
621}
622
623/** @todo static void vmsvgaR3GboWriteProtect(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, bool fWriteProtect) */
624
625typedef enum VMSVGAGboTransferDirection
626{
627 VMSVGAGboTransferDirection_Read,
628 VMSVGAGboTransferDirection_Write,
629} VMSVGAGboTransferDirection;
630
631static int vmsvgaR3GboTransfer(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
632 uint32_t off, void *pvData, uint32_t cbData,
633 VMSVGAGboTransferDirection enmDirection)
634{
635// ASMBreakpoint();
636 int rc = VINF_SUCCESS;
637 uint8_t *pu8CurrentHost = (uint8_t *)pvData;
638
639 /* Find the right descriptor */
640 PCVMSVGAGBODESCRIPTOR const paDescriptors = pGbo->paDescriptors;
641 uint32_t iDescriptor = 0; /* Index in the descriptor array. */
642 uint32_t offDescriptor = 0; /* GMR offset of the current descriptor. */
643 while (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE <= off)
644 {
645 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
646 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
647 ++iDescriptor;
648 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
649 }
650
651 while (cbData)
652 {
653 uint32_t cbToCopy;
654 if (off + cbData <= offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
655 cbToCopy = cbData;
656 else
657 {
658 cbToCopy = (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE - off);
659 AssertReturn(cbToCopy <= cbData, VERR_INVALID_PARAMETER);
660 }
661
662 RTGCPHYS const GCPhys = paDescriptors[iDescriptor].GCPhys + off - offDescriptor;
663 Log5Func(("%s phys=%RGp\n", (enmDirection == VMSVGAGboTransferDirection_Read) ? "READ" : "WRITE", GCPhys));
664
665 /*
666 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
667 * guest-side VMSVGA driver seems to allocate non-DMA (regular physical) addresses,
668 * see @bugref{9654#c75}.
669 */
670 if (enmDirection == VMSVGAGboTransferDirection_Read)
671 rc = PDMDevHlpPhysRead(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
672 else
673 rc = PDMDevHlpPhysWrite(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
674 AssertRCBreak(rc);
675
676 cbData -= cbToCopy;
677 off += cbToCopy;
678 pu8CurrentHost += cbToCopy;
679
680 /* Go to the next descriptor if there's anything left. */
681 if (cbData)
682 {
683 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
684 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR);
685 ++iDescriptor;
686 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
687 }
688 }
689 return rc;
690}
691
692
693static int vmsvgaR3GboWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
694 uint32_t off, void const *pvData, uint32_t cbData)
695{
696 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
697 off, (void *)pvData, cbData,
698 VMSVGAGboTransferDirection_Write);
699}
700
701
702static int vmsvgaR3GboRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
703 uint32_t off, void *pvData, uint32_t cbData)
704{
705 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
706 off, pvData, cbData,
707 VMSVGAGboTransferDirection_Read);
708}
709
710
711static int vmsvgaR3GboBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, uint32_t cbValid)
712{
713 int rc;
714
715 /* Just reread the data if pvHost has been allocated already. */
716 if (!(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED))
717 pGbo->pvHost = RTMemAllocZ(pGbo->cbTotal);
718
719 if (pGbo->pvHost)
720 {
721 cbValid = RT_MIN(cbValid, pGbo->cbTotal);
722 rc = vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, cbValid);
723 }
724 else
725 rc = VERR_NO_MEMORY;
726
727 if (RT_SUCCESS(rc))
728 pGbo->fGboFlags |= VMSVGAGBO_F_HOST_BACKED;
729 else
730 {
731 RTMemFree(pGbo->pvHost);
732 pGbo->pvHost = NULL;
733 }
734 return rc;
735}
736
737
738static void vmsvgaR3GboBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
739{
740 RT_NOREF(pSvgaR3State);
741 AssertReturnVoid(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED);
742 RTMemFree(pGbo->pvHost);
743 pGbo->pvHost = NULL;
744 pGbo->fGboFlags &= ~VMSVGAGBO_F_HOST_BACKED;
745}
746
747
748static int vmsvgaR3GboBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
749{
750 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
751 return vmsvgaR3GboWrite(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
752}
753
754
755static int vmsvgaR3GboBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
756{
757 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
758 return vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
759}
760
761
762
763/*
764 *
765 * Object Tables.
766 *
767 */
768
769static int vmsvgaR3OTableVerifyIndex(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
770 uint32_t idx, uint32_t cbEntry)
771{
772 RT_NOREF(pSvgaR3State);
773
774 /* The table must exist and the index must be within the table. */
775 ASSERT_GUEST_RETURN(VMSVGA_IS_GBO_CREATED(pGboOTable), VERR_INVALID_PARAMETER);
776 ASSERT_GUEST_RETURN(idx < pGboOTable->cbTotal / cbEntry, VERR_INVALID_PARAMETER);
777 RT_UNTRUSTED_VALIDATED_FENCE();
778 return VINF_SUCCESS;
779}
780
781
782static int vmsvgaR3OTableRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
783 uint32_t idx, uint32_t cbEntry,
784 void *pvData, uint32_t cbData)
785{
786 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
787
788 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
789 if (RT_SUCCESS(rc))
790 {
791 uint32_t const off = idx * cbEntry;
792 rc = vmsvgaR3GboRead(pSvgaR3State, pGboOTable, off, pvData, cbData);
793 }
794 return rc;
795}
796
797static int vmsvgaR3OTableWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
798 uint32_t idx, uint32_t cbEntry,
799 void const *pvData, uint32_t cbData)
800{
801 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
802
803 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
804 if (RT_SUCCESS(rc))
805 {
806 uint32_t const off = idx * cbEntry;
807 rc = vmsvgaR3GboWrite(pSvgaR3State, pGboOTable, off, pvData, cbData);
808 }
809 return rc;
810}
811
812
813/*
814 *
815 * The guest's Memory OBjects (MOB).
816 *
817 */
818
819static int vmsvgaR3MobCreate(PVMSVGAR3STATE pSvgaR3State,
820 SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, SVGAMobId mobid,
821 bool fGCPhys64, PVMSVGAMOB pMob)
822{
823 RT_ZERO(*pMob);
824
825 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
826 SVGAOTableMobEntry entry;
827 entry.ptDepth = ptDepth;
828 entry.sizeInBytes = sizeInBytes;
829 entry.base = baseAddress;
830 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
831 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
832 if (RT_SUCCESS(rc))
833 {
834 /* Create the corresponding GBO. */
835 rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, fGCPhys64, /* fWriteProtected = */ false, &pMob->Gbo);
836 if (RT_SUCCESS(rc))
837 {
838 /* Add to the tree of known GBOs and the LRU list. */
839 pMob->Core.Key = mobid;
840 if (RTAvlU32Insert(&pSvgaR3State->MOBTree, &pMob->Core))
841 {
842 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
843 return VINF_SUCCESS;
844 }
845
846 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
847 }
848 }
849
850 return rc;
851}
852
853
854static int vmsvgaR3MobDestroy(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
855{
856 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
857 SVGAOTableMobEntry entry;
858 RT_ZERO(entry);
859 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
860 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
861
862 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
863 if (pMob)
864 {
865 RTListNodeRemove(&pMob->nodeLRU);
866 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
867 RTMemFree(pMob);
868 return VINF_SUCCESS;
869 }
870
871 return VERR_INVALID_PARAMETER;
872}
873
874
875static PVMSVGAMOB vmsvgaR3MobGet(PVMSVGAR3STATE pSvgaR3State, SVGAMobId RT_UNTRUSTED_GUEST mobid)
876{
877 if (mobid == SVGA_ID_INVALID)
878 return NULL;
879
880 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Get(&pSvgaR3State->MOBTree, mobid);
881 if (pMob)
882 {
883 /* Move to the head of the LRU list. */
884 RTListNodeRemove(&pMob->nodeLRU);
885 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
886 }
887 else
888 ASSERT_GUEST_FAILED();
889
890 return pMob;
891}
892
893
894/** Create a host ring-3 pointer to the MOB data.
895 * Current approach is to allocate a host memory buffer and copy the guest MOB data if necessary.
896 * @param pSvgaR3State R3 device state.
897 * @param pMob The MOB.
898 * @param cbValid How many bytes of the guest backing memory contain valid data.
899 * @return VBox status.
900 */
901/** @todo uint32_t cbValid -> uint32_t offStart, uint32_t cbData */
902int vmsvgaR3MobBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob, uint32_t cbValid)
903{
904 AssertReturn(pMob, VERR_INVALID_PARAMETER);
905 return vmsvgaR3GboBackingStoreCreate(pSvgaR3State, &pMob->Gbo, cbValid);
906}
907
908
909void vmsvgaR3MobBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
910{
911 if (pMob)
912 vmsvgaR3GboBackingStoreDelete(pSvgaR3State, &pMob->Gbo);
913}
914
915
916int vmsvgaR3MobBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
917{
918 if (pMob)
919 return vmsvgaR3GboBackingStoreWriteToGuest(pSvgaR3State, &pMob->Gbo);
920 return VERR_INVALID_PARAMETER;
921}
922
923
924int vmsvgaR3MobBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
925{
926 if (pMob)
927 return vmsvgaR3GboBackingStoreReadFromGuest(pSvgaR3State, &pMob->Gbo);
928 return VERR_INVALID_PARAMETER;
929}
930
931
932void *vmsvgaR3MobBackingStorePtr(PVMSVGAMOB pMob, uint32_t off)
933{
934 if (pMob && (pMob->Gbo.fGboFlags & VMSVGAGBO_F_HOST_BACKED))
935 {
936 if (off <= pMob->Gbo.cbTotal)
937 return (uint8_t *)pMob->Gbo.pvHost + off;
938 }
939 return NULL;
940}
941
942
943#ifdef VBOX_WITH_VMSVGA3D
944int vmsvgaR3UpdateGBSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dSurfaceImageId const *pImageId, SVGA3dBox const *pBox)
945{
946 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
947
948 SVGAOTableSurfaceEntry entrySurface;
949 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
950 pImageId->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
951 if (RT_SUCCESS(rc))
952 {
953 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
954 if (pMob)
955 {
956 VMSVGA3D_MAPPED_SURFACE map;
957 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, idDXContext, pImageId, pBox, VMSVGA3D_SURFACE_MAP_WRITE_DISCARD, &map);
958 if (RT_SUCCESS(rc))
959 {
960 /* Copy MOB -> mapped surface. */
961 uint32_t offSrc = pBox->x * map.cbPixel
962 + pBox->y * entrySurface.size.width * map.cbPixel
963 + pBox->z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
964 uint8_t *pu8Dst = (uint8_t *)map.pvData;
965 for (uint32_t z = 0; z < pBox->d; ++z)
966 {
967 for (uint32_t y = 0; y < pBox->h; ++y)
968 {
969 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pBox->w * map.cbPixel);
970 if (RT_FAILURE(rc))
971 break;
972
973 pu8Dst += map.cbRowPitch;
974 offSrc += entrySurface.size.width * map.cbPixel;
975 }
976
977 pu8Dst += map.cbDepthPitch;
978 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
979 }
980
981 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, pImageId, &map, /* fWritten= */ true);
982 }
983 }
984 else
985 rc = VERR_INVALID_STATE;
986 }
987
988 return rc;
989}
990
991
992int vmsvgaR3UpdateGBSurfaceEx(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dSurfaceImageId const *pImageId, SVGA3dBox const *pBoxDst, SVGA3dPoint const *pPtSrc)
993{
994 /* pPtSrc must be verified by the caller. */
995 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
996
997 SVGAOTableSurfaceEntry entrySurface;
998 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
999 pImageId->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1000 if (RT_SUCCESS(rc))
1001 {
1002 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1003 if (pMob)
1004 {
1005 VMSVGA3D_MAPPED_SURFACE map;
1006 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, idDXContext, pImageId, pBoxDst, VMSVGA3D_SURFACE_MAP_WRITE_DISCARD, &map);
1007 if (RT_SUCCESS(rc))
1008 {
1009 /* Copy MOB -> mapped surface. */
1010 uint32_t offSrc = pPtSrc->x * map.cbPixel
1011 + pPtSrc->y * entrySurface.size.width * map.cbPixel
1012 + pPtSrc->z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1013 uint8_t *pu8Dst = (uint8_t *)map.pvData;
1014 for (uint32_t z = 0; z < pBoxDst->d; ++z)
1015 {
1016 for (uint32_t y = 0; y < pBoxDst->h; ++y)
1017 {
1018 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pBoxDst->w * map.cbPixel);
1019 if (RT_FAILURE(rc))
1020 break;
1021
1022 pu8Dst += map.cbRowPitch;
1023 offSrc += entrySurface.size.width * map.cbPixel;
1024 }
1025
1026 pu8Dst += map.cbDepthPitch;
1027 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1028 }
1029
1030 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, pImageId, &map, /* fWritten= */ true);
1031 }
1032 }
1033 else
1034 rc = VERR_INVALID_STATE;
1035 }
1036
1037 return rc;
1038}
1039#endif /* VBOX_WITH_VMSVGA3D */
1040
1041
1042/*
1043 * Screen objects.
1044 */
1045VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
1046{
1047 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1048 if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
1049 && pSVGAState
1050 && pSVGAState->aScreens[idScreen].fDefined)
1051 {
1052 return &pSVGAState->aScreens[idScreen];
1053 }
1054 return NULL;
1055}
1056
1057void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
1058{
1059#ifdef VBOX_WITH_VMSVGA3D
1060 if (pThis->svga.f3DEnabled)
1061 {
1062 for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
1063 {
1064 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
1065 if (pScreen)
1066 vmsvga3dDestroyScreen(pThisCC, pScreen);
1067 }
1068 }
1069#else
1070 RT_NOREF(pThis, pThisCC);
1071#endif
1072}
1073
1074
1075/**
1076 * Copy a rectangle of pixels within guest VRAM.
1077 */
1078static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1079 uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1080{
1081 if (!width || !height)
1082 return; /* Nothing to do, don't even bother. */
1083
1084 /*
1085 * The guest VRAM (aka GFB) is considered to be a bitmap in the format
1086 * corresponding to the current display mode.
1087 */
1088 uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1089 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1090 uint8_t const *pSrc;
1091 uint8_t *pDst;
1092 unsigned const cbRectWidth = width * cbPixel;
1093 unsigned uMaxOffset;
1094
1095 uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1096 if (uMaxOffset >= cbFrameBuffer)
1097 {
1098 Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1099 return; /* Just don't listen to a bad guest. */
1100 }
1101
1102 pSrc = pDst = pThisCC->pbVRam;
1103 pSrc += srcY * cbScanline + srcX * cbPixel;
1104 pDst += dstY * cbScanline + dstX * cbPixel;
1105
1106 if (srcY >= dstY)
1107 {
1108 /* Source below destination, copy top to bottom. */
1109 for (; height > 0; height--)
1110 {
1111 memmove(pDst, pSrc, cbRectWidth);
1112 pSrc += cbScanline;
1113 pDst += cbScanline;
1114 }
1115 }
1116 else
1117 {
1118 /* Source above destination, copy bottom to top. */
1119 pSrc += cbScanline * (height - 1);
1120 pDst += cbScanline * (height - 1);
1121 for (; height > 0; height--)
1122 {
1123 memmove(pDst, pSrc, cbRectWidth);
1124 pSrc -= cbScanline;
1125 pDst -= cbScanline;
1126 }
1127 }
1128}
1129
1130
1131/**
1132 * Common worker for changing the pointer shape.
1133 *
1134 * @param pThisCC The VGA/VMSVGA state for ring-3.
1135 * @param pSVGAState The VMSVGA ring-3 instance data.
1136 * @param fAlpha Whether there is alpha or not.
1137 * @param xHot Hotspot x coordinate.
1138 * @param yHot Hotspot y coordinate.
1139 * @param cx Width.
1140 * @param cy Height.
1141 * @param pbData Heap copy of the cursor data. Consumed.
1142 * @param cbData The size of the data.
1143 */
1144static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
1145 uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
1146{
1147 LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
1148#ifdef LOG_ENABLED
1149 if (LogIs2Enabled())
1150 {
1151 uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
1152 if (!fAlpha)
1153 {
1154 Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
1155 for (uint32_t y = 0; y < cy; y++)
1156 {
1157 Log2(("%3u:", y));
1158 uint8_t const *pbLine = &pbData[y * cbAndLine];
1159 for (uint32_t x = 0; x < cx; x += 8)
1160 {
1161 uint8_t b = pbLine[x / 8];
1162 char szByte[12];
1163 szByte[0] = b & 0x80 ? '*' : ' '; /* most significant bit first */
1164 szByte[1] = b & 0x40 ? '*' : ' ';
1165 szByte[2] = b & 0x20 ? '*' : ' ';
1166 szByte[3] = b & 0x10 ? '*' : ' ';
1167 szByte[4] = b & 0x08 ? '*' : ' ';
1168 szByte[5] = b & 0x04 ? '*' : ' ';
1169 szByte[6] = b & 0x02 ? '*' : ' ';
1170 szByte[7] = b & 0x01 ? '*' : ' ';
1171 szByte[8] = '\0';
1172 Log2(("%s", szByte));
1173 }
1174 Log2(("\n"));
1175 }
1176 }
1177
1178 Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
1179 uint32_t const *pu32Xor = (uint32_t const *)&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
1180 for (uint32_t y = 0; y < cy; y++)
1181 {
1182 Log2(("%3u:", y));
1183 uint32_t const *pu32Line = &pu32Xor[y * cx];
1184 for (uint32_t x = 0; x < cx; x++)
1185 Log2((" %08x", pu32Line[x]));
1186 Log2(("\n"));
1187 }
1188 }
1189#endif
1190
1191 int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, fAlpha, xHot, yHot, cx, cy, pbData);
1192 AssertRC(rc);
1193
1194 if (pSVGAState->Cursor.fActive)
1195 RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
1196
1197 pSVGAState->Cursor.fActive = true;
1198 pSVGAState->Cursor.xHotspot = xHot;
1199 pSVGAState->Cursor.yHotspot = yHot;
1200 pSVGAState->Cursor.width = cx;
1201 pSVGAState->Cursor.height = cy;
1202 pSVGAState->Cursor.cbData = cbData;
1203 pSVGAState->Cursor.pData = pbData;
1204}
1205
1206
1207#ifdef VBOX_WITH_VMSVGA3D
1208
1209/*
1210 * SVGA_3D_CMD_* handlers.
1211 */
1212
1213
1214/** SVGA_3D_CMD_SURFACE_DEFINE 1040, SVGA_3D_CMD_SURFACE_DEFINE_V2 1070
1215 *
1216 * @param pThisCC The VGA/VMSVGA state for the current context.
1217 * @param pCmd The VMSVGA command.
1218 * @param cMipLevelSizes Number of elements in the paMipLevelSizes array.
1219 * @param paMipLevelSizes Arrays of surface sizes for each face and miplevel.
1220 */
1221static void vmsvga3dCmdDefineSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineSurface_v2 const *pCmd,
1222 uint32_t cMipLevelSizes, SVGA3dSize *paMipLevelSizes)
1223{
1224 ASSERT_GUEST_RETURN_VOID(pCmd->sid < SVGA3D_MAX_SURFACE_IDS);
1225 ASSERT_GUEST_RETURN_VOID(cMipLevelSizes >= 1);
1226 RT_UNTRUSTED_VALIDATED_FENCE();
1227
1228 /* Number of faces (cFaces) is specified as the number of the first non-zero elements in the 'face' array.
1229 * Since only plain surfaces (cFaces == 1) and cubemaps (cFaces == 6) are supported
1230 * (see also SVGA3dCmdDefineSurface definition in svga3d_reg.h), we ignore anything else.
1231 */
1232 uint32_t cRemainingMipLevels = cMipLevelSizes;
1233 uint32_t cFaces = 0;
1234 for (uint32_t i = 0; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1235 {
1236 if (pCmd->face[i].numMipLevels == 0)
1237 break;
1238
1239 /* All SVGA3dSurfaceFace structures must have the same value of numMipLevels field */
1240 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == pCmd->face[0].numMipLevels);
1241
1242 /* numMipLevels value can't be greater than the number of remaining elements in the paMipLevelSizes array. */
1243 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels <= cRemainingMipLevels);
1244 cRemainingMipLevels -= pCmd->face[i].numMipLevels;
1245
1246 ++cFaces;
1247 }
1248 for (uint32_t i = cFaces; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1249 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == 0);
1250
1251 /* cFaces must be 6 for a cubemap and 1 otherwise. */
1252 ASSERT_GUEST_RETURN_VOID(cFaces == (uint32_t)((pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP) ? 6 : 1));
1253
1254 /* Sum of face[i].numMipLevels must be equal to cMipLevels. */
1255 ASSERT_GUEST_RETURN_VOID(cRemainingMipLevels == 0);
1256 RT_UNTRUSTED_VALIDATED_FENCE();
1257
1258 /* Verify paMipLevelSizes */
1259 uint32_t cWidth = paMipLevelSizes[0].width;
1260 uint32_t cHeight = paMipLevelSizes[0].height;
1261 uint32_t cDepth = paMipLevelSizes[0].depth;
1262 for (uint32_t i = 1; i < pCmd->face[0].numMipLevels; ++i)
1263 {
1264 cWidth >>= 1;
1265 if (cWidth == 0) cWidth = 1;
1266 cHeight >>= 1;
1267 if (cHeight == 0) cHeight = 1;
1268 cDepth >>= 1;
1269 if (cDepth == 0) cDepth = 1;
1270 for (uint32_t iFace = 0; iFace < cFaces; ++iFace)
1271 {
1272 uint32_t const iMipLevelSize = iFace * pCmd->face[0].numMipLevels + i;
1273 ASSERT_GUEST_RETURN_VOID( cWidth == paMipLevelSizes[iMipLevelSize].width
1274 && cHeight == paMipLevelSizes[iMipLevelSize].height
1275 && cDepth == paMipLevelSizes[iMipLevelSize].depth);
1276 }
1277 }
1278 RT_UNTRUSTED_VALIDATED_FENCE();
1279
1280 /* Create the surface. */
1281 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1282 pCmd->multisampleCount, pCmd->autogenFilter,
1283 pCmd->face[0].numMipLevels, &paMipLevelSizes[0]);
1284}
1285
1286
1287/* SVGA_3D_CMD_DEFINE_GB_MOB 1093 */
1288static void vmsvga3dCmdDefineGBMob(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob const *pCmd)
1289{
1290 ASMBreakpoint();
1291 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1292
1293 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1294
1295 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1296 /* Allocate a structure for the MOB. */
1297 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1298 AssertPtrReturnVoid(pMob);
1299
1300 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ false, pMob);
1301 if (RT_SUCCESS(rc))
1302 {
1303 return;
1304 }
1305
1306 AssertFailed();
1307
1308 RTMemFree(pMob);
1309}
1310
1311
1312/* SVGA_3D_CMD_DESTROY_GB_MOB 1094 */
1313static void vmsvga3dCmdDestroyGBMob(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBMob const *pCmd)
1314{
1315// ASMBreakpoint();
1316 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1317
1318 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1319
1320 int rc = vmsvgaR3MobDestroy(pSvgaR3State, pCmd->mobid);
1321 if (RT_SUCCESS(rc))
1322 {
1323 return;
1324 }
1325
1326 AssertFailed();
1327}
1328
1329
1330/* SVGA_3D_CMD_DEFINE_GB_SURFACE 1097 */
1331static void vmsvga3dCmdDefineGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface const *pCmd)
1332{
1333// ASMBreakpoint();
1334 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1335
1336 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1337 SVGAOTableSurfaceEntry entry;
1338 RT_ZERO(entry);
1339 entry.format = pCmd->format;
1340 entry.surface1Flags = pCmd->surfaceFlags;
1341 entry.numMipLevels = pCmd->numMipLevels;
1342 entry.multisampleCount = pCmd->multisampleCount;
1343 entry.autogenFilter = pCmd->autogenFilter;
1344 entry.size = pCmd->size;
1345 entry.mobid = SVGA_ID_INVALID;
1346 // entry.arraySize = 0;
1347 // entry.mobPitch = 0;
1348 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1349 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1350 if (RT_SUCCESS(rc))
1351 {
1352 /* Create the host surface. */
1353 /** @todo fGBO = true flag. */
1354 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1355 pCmd->multisampleCount, pCmd->autogenFilter,
1356 pCmd->numMipLevels, &pCmd->size);
1357 }
1358}
1359
1360
1361/* SVGA_3D_CMD_DESTROY_GB_SURFACE 1098 */
1362static void vmsvga3dCmdDestroyGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBSurface const *pCmd)
1363{
1364// ASMBreakpoint();
1365 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1366
1367 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1368 SVGAOTableSurfaceEntry entry;
1369 RT_ZERO(entry);
1370 entry.mobid = SVGA_ID_INVALID;
1371 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1372 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1373
1374 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
1375}
1376
1377
1378/* SVGA_3D_CMD_BIND_GB_SURFACE 1099 */
1379static void vmsvga3dCmdBindGBSurface(PVGASTATECC pThisCC, SVGA3dCmdBindGBSurface const *pCmd)
1380{
1381// ASMBreakpoint();
1382 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1383
1384 /* Assign the mobid to the surface. */
1385 int rc = VINF_SUCCESS;
1386 if (pCmd->mobid != SVGA_ID_INVALID)
1387 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1388 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1389 if (RT_SUCCESS(rc))
1390 {
1391 SVGAOTableSurfaceEntry entry;
1392 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1393 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1394 if (RT_SUCCESS(rc))
1395 {
1396 entry.mobid = pCmd->mobid;
1397 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1398 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1399 if (RT_SUCCESS(rc))
1400 {
1401 /* */
1402 }
1403 }
1404 }
1405}
1406
1407
1408#ifdef DUMP_BITMAPS
1409static int vmsvga3dBmpWrite(const char *pszFilename, VMSVGA3D_MAPPED_SURFACE const *pMap)
1410{
1411 if (pMap->cbPixel != 4)
1412 return VERR_NOT_SUPPORTED;
1413
1414 int const w = pMap->box.w;
1415 int const h = pMap->box.h;
1416
1417 const int cbBitmap = w * h * 4;
1418
1419 FILE *f = fopen(pszFilename, "wb");
1420 if (!f)
1421 return VERR_FILE_NOT_FOUND;
1422
1423 {
1424 BMPFILEHDR fileHdr;
1425 RT_ZERO(fileHdr);
1426 fileHdr.uType = BMP_HDR_MAGIC;
1427 fileHdr.cbFileSize = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR) + cbBitmap;
1428 fileHdr.offBits = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR);
1429
1430 BMPWIN3XINFOHDR coreHdr;
1431 RT_ZERO(coreHdr);
1432 coreHdr.cbSize = sizeof(coreHdr);
1433 coreHdr.uWidth = w;
1434 coreHdr.uHeight = -h;
1435 coreHdr.cPlanes = 1;
1436 coreHdr.cBits = 32;
1437 coreHdr.cbSizeImage = cbBitmap;
1438
1439 fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1440 fwrite(&coreHdr, 1, sizeof(coreHdr), f);
1441 }
1442
1443 if (pMap->cbPixel == 4)
1444 {
1445 const uint8_t *s = (uint8_t *)pMap->pvData;
1446 for (int32_t y = 0; y < h; ++y)
1447 {
1448 fwrite(s, 1, w * pMap->cbPixel, f);
1449
1450 s += pMap->cbRowPitch;
1451 }
1452 }
1453
1454 fclose(f);
1455
1456 return VINF_SUCCESS;
1457}
1458
1459
1460void vmsvga3dMapWriteBmpFile(VMSVGA3D_MAPPED_SURFACE const *pMap, char const *pszPrefix)
1461{
1462 static int idxBitmap = 0;
1463 char *pszFilename = RTStrAPrintf2("bmp\\%s%d.bmp", pszPrefix, idxBitmap++);
1464 int rc = vmsvga3dBmpWrite(pszFilename, pMap);
1465 Log(("WriteBmpFile %s %Rrc\n", pszFilename, rc)); RT_NOREF(rc);
1466 RTStrFree(pszFilename);
1467}
1468#endif /* DUMP_BITMAPS */
1469
1470
1471/* SVGA_3D_CMD_UPDATE_GB_IMAGE 1101 */
1472static void vmsvga3dCmdUpdateGBImage(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdUpdateGBImage const *pCmd)
1473{
1474// ASMBreakpoint();
1475 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1476
1477 LogFlowFunc(("sid=%u @%u,%u,%u %ux%ux%u\n",
1478 pCmd->image.sid, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
1479
1480 /* "update a surface from its backing MOB." */
1481 SVGAOTableSurfaceEntry entrySurface;
1482 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1483 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1484 if (RT_SUCCESS(rc))
1485 {
1486 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1487 if (pMob)
1488 {
1489 VMSVGA3D_MAPPED_SURFACE map;
1490 /** @todo vmsvga3dSurfaceMap */
1491 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, idDXContext, &pCmd->image, &pCmd->box, VMSVGA3D_SURFACE_MAP_WRITE_DISCARD, &map);
1492 if (RT_SUCCESS(rc))
1493 {
1494 /* Copy MOB -> mapped surface. */
1495 uint32_t offSrc = pCmd->box.x * map.cbPixel
1496 + pCmd->box.y * entrySurface.size.width * map.cbPixel
1497 + pCmd->box.z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1498 uint8_t *pu8Dst = (uint8_t *)map.pvData;
1499 for (uint32_t z = 0; z < pCmd->box.d; ++z)
1500 {
1501 for (uint32_t y = 0; y < pCmd->box.h; ++y)
1502 {
1503 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pCmd->box.w * map.cbPixel);
1504 if (RT_FAILURE(rc))
1505 break;
1506
1507 pu8Dst += map.cbRowPitch;
1508 offSrc += entrySurface.size.width * map.cbPixel;
1509 }
1510
1511 pu8Dst += map.cbDepthPitch;
1512 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1513 }
1514
1515 // vmsvga3dMapWriteBmpFile(&map, "Dynamic");
1516
1517 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, &pCmd->image, &map, /* fWritten = */true);
1518 }
1519 }
1520 }
1521}
1522
1523
1524/* SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105 */
1525static void vmsvga3dCmdInvalidateGBImage(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBImage const *pCmd)
1526{
1527// ASMBreakpoint();
1528 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap);
1529}
1530
1531
1532/* SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106 */
1533static void vmsvga3dCmdInvalidateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBSurface const *pCmd)
1534{
1535// ASMBreakpoint();
1536 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, SVGA_ID_INVALID, SVGA_ID_INVALID);
1537}
1538
1539
1540/* SVGA_3D_CMD_SET_OTABLE_BASE64 1115 */
1541static void vmsvga3dCmdSetOTableBase64(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase64 const *pCmd)
1542{
1543 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1544
1545 /*
1546 * Create a GBO for the table.
1547 */
1548 PVMSVGAGBO pGbo;
1549 if (pCmd->type <= RT_ELEMENTS(pSvgaR3State->aGboOTables))
1550 {
1551 RT_UNTRUSTED_VALIDATED_FENCE();
1552 pGbo = &pSvgaR3State->aGboOTables[pCmd->type];
1553 }
1554 else
1555 {
1556 ASSERT_GUEST_FAILED();
1557 pGbo = NULL;
1558 }
1559
1560 if (pGbo)
1561 {
1562 /* Recreate. */
1563 vmsvgaR3GboDestroy(pSvgaR3State, pGbo);
1564 int rc = vmsvgaR3GboCreate(pSvgaR3State, pCmd->ptDepth, pCmd->baseAddress, pCmd->sizeInBytes, /*fGCPhys64=*/ true, /* fWriteProtected = */ true, pGbo);
1565 AssertRC(rc);
1566 }
1567}
1568
1569
1570/* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124 */
1571static void vmsvga3dCmdDefineGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDefineGBScreenTarget const *pCmd)
1572{
1573// ASMBreakpoint();
1574 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1575
1576 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1577 ASSERT_GUEST_RETURN_VOID(pCmd->width > 0 && pCmd->width <= pThis->svga.u32MaxWidth); /* SVGA_REG_SCREENTARGET_MAX_WIDTH */
1578 ASSERT_GUEST_RETURN_VOID(pCmd->height > 0 && pCmd->height <= pThis->svga.u32MaxHeight); /* SVGA_REG_SCREENTARGET_MAX_HEIGHT */
1579 RT_UNTRUSTED_VALIDATED_FENCE();
1580
1581 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1582 SVGAOTableScreenTargetEntry entry;
1583 RT_ZERO(entry);
1584 entry.image.sid = SVGA_ID_INVALID;
1585 // entry.image.face = 0;
1586 // entry.image.mipmap = 0;
1587 entry.width = pCmd->width;
1588 entry.height = pCmd->height;
1589 entry.xRoot = pCmd->xRoot;
1590 entry.yRoot = pCmd->yRoot;
1591 entry.flags = pCmd->flags;
1592 entry.dpi = pCmd->dpi;
1593
1594 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1595 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1596 if (RT_SUCCESS(rc))
1597 {
1598 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1599 /** @todo Generic screen object/target interface. */
1600 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1601 pScreen->fDefined = true;
1602 pScreen->fModified = true;
1603 pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET
1604 | (RT_BOOL(pCmd->flags & SVGA_STFLAG_PRIMARY) ? SVGA_SCREEN_IS_PRIMARY : 0);
1605 pScreen->idScreen = pCmd->stid;
1606
1607 pScreen->xOrigin = pCmd->xRoot;
1608 pScreen->yOrigin = pCmd->yRoot;
1609 pScreen->cWidth = pCmd->width;
1610 pScreen->cHeight = pCmd->height;
1611 pScreen->offVRAM = 0; /* Not applicable for screen targets, they use either a separate memory buffer or a host window. */
1612 pScreen->cbPitch = pCmd->width * 4;
1613 pScreen->cBpp = 32;
1614
1615 if (RT_LIKELY(pThis->svga.f3DEnabled))
1616 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
1617
1618 if (!pScreen->pHwScreen)
1619 {
1620 /* System memory buffer. */
1621 pScreen->pvScreenBitmap = RTMemAllocZ(pScreen->cHeight * pScreen->cbPitch);
1622 }
1623
1624 pThis->svga.fGFBRegisters = false;
1625 vmsvgaR3ChangeMode(pThis, pThisCC);
1626 }
1627}
1628
1629
1630/* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125 */
1631static void vmsvga3dCmdDestroyGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDestroyGBScreenTarget const *pCmd)
1632{
1633// ASMBreakpoint();
1634 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1635
1636 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1637 RT_UNTRUSTED_VALIDATED_FENCE();
1638
1639 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1640 SVGAOTableScreenTargetEntry entry;
1641 RT_ZERO(entry);
1642 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1643 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1644 if (RT_SUCCESS(rc))
1645 {
1646 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1647 /** @todo Generic screen object/target interface. */
1648 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1649 pScreen->fModified = true;
1650 pScreen->fDefined = false;
1651 pScreen->idScreen = pCmd->stid;
1652
1653 if (RT_LIKELY(pThis->svga.f3DEnabled))
1654 vmsvga3dDestroyScreen(pThisCC, pScreen);
1655
1656 vmsvgaR3ChangeMode(pThis, pThisCC);
1657
1658 RTMemFree(pScreen->pvScreenBitmap);
1659 pScreen->pvScreenBitmap = NULL;
1660 }
1661}
1662
1663
1664/* SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126 */
1665static void vmsvga3dCmdBindGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdBindGBScreenTarget const *pCmd)
1666{
1667// ASMBreakpoint();
1668 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1669
1670 /* "Binding a surface to a Screen Target the same as flipping" */
1671
1672 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1673 ASSERT_GUEST_RETURN_VOID(pCmd->image.face == 0 && pCmd->image.mipmap == 0);
1674 RT_UNTRUSTED_VALIDATED_FENCE();
1675
1676 /* Assign the surface to the screen target. */
1677 int rc = VINF_SUCCESS;
1678 if (pCmd->image.sid != SVGA_ID_INVALID)
1679 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1680 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE);
1681 if (RT_SUCCESS(rc))
1682 {
1683 SVGAOTableScreenTargetEntry entry;
1684 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1685 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1686 if (RT_SUCCESS(rc))
1687 {
1688 entry.image = pCmd->image;
1689 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1690 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1691 if (RT_SUCCESS(rc))
1692 {
1693 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1694 rc = pSvgaR3State->pFuncsGBO->pfnScreenTargetBind(pThisCC, pScreen, pCmd->image.sid);
1695 AssertRC(rc);
1696 }
1697 }
1698 }
1699}
1700
1701
1702/* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127 */
1703static void vmsvga3dCmdUpdateGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBScreenTarget const *pCmd)
1704{
1705// ASMBreakpoint();
1706 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1707
1708 /* Update the screen target from its backing surface. */
1709 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1710 RT_UNTRUSTED_VALIDATED_FENCE();
1711
1712 /* Get the screen target info. */
1713 SVGAOTableScreenTargetEntry entryScreenTarget;
1714 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1715 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entryScreenTarget, sizeof(entryScreenTarget));
1716 if (RT_SUCCESS(rc))
1717 {
1718 ASSERT_GUEST_RETURN_VOID(entryScreenTarget.image.face == 0 && entryScreenTarget.image.mipmap == 0);
1719 RT_UNTRUSTED_VALIDATED_FENCE();
1720
1721 if (entryScreenTarget.image.sid != SVGA_ID_INVALID)
1722 {
1723 SVGAOTableSurfaceEntry entrySurface;
1724 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1725 entryScreenTarget.image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1726 if (RT_SUCCESS(rc))
1727 {
1728 /* Copy entrySurface.mobid content to the screen target. */
1729 if (entrySurface.mobid != SVGA_ID_INVALID)
1730 {
1731 RT_UNTRUSTED_VALIDATED_FENCE();
1732 SVGA3dRect targetRect = pCmd->rect;
1733
1734 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1735 if (pScreen->pHwScreen)
1736 {
1737 /* Copy the screen target surface to the backend's screen. */
1738 pSvgaR3State->pFuncsGBO->pfnScreenTargetUpdate(pThisCC, pScreen, &targetRect);
1739 }
1740 else if (pScreen->pvScreenBitmap)
1741 {
1742 /* Copy the screen target surface to the memory buffer. */
1743 VMSVGA3D_MAPPED_SURFACE map;
1744 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, SVGA_ID_INVALID, &entryScreenTarget.image, NULL, VMSVGA3D_SURFACE_MAP_READ, &map);
1745 if (RT_SUCCESS(rc))
1746 {
1747 uint8_t const *pu8Src = (uint8_t *)map.pvData
1748 + targetRect.x * map.cbPixel
1749 + targetRect.y * map.cbRowPitch;
1750 uint8_t *pu8Dst = (uint8_t *)pScreen->pvScreenBitmap
1751 + targetRect.x * map.cbPixel
1752 + targetRect.y * map.box.w * map.cbPixel;
1753 for (uint32_t y = 0; y < targetRect.h; ++y)
1754 {
1755 memcpy(pu8Dst, pu8Src, targetRect.w * map.cbPixel);
1756
1757 pu8Src += map.cbRowPitch;
1758 pu8Dst += map.box.w * map.cbPixel;
1759 }
1760
1761 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, &entryScreenTarget.image, &map, /* fWritten = */ false);
1762
1763 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->rect.x, pCmd->rect.y, pCmd->rect.w, pCmd->rect.h);
1764 }
1765 else
1766 AssertFailed();
1767 }
1768 }
1769 }
1770 }
1771 }
1772}
1773
1774
1775/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134 */
1776static void vmsvga3dCmdDefineGBSurface_v2(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v2 const *pCmd)
1777{
1778//ASMBreakpoint();
1779 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1780
1781 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1782 SVGAOTableSurfaceEntry entry;
1783 RT_ZERO(entry);
1784 entry.format = pCmd->format;
1785 entry.surface1Flags = pCmd->surfaceFlags;
1786 entry.numMipLevels = pCmd->numMipLevels;
1787 entry.multisampleCount = pCmd->multisampleCount;
1788 entry.autogenFilter = pCmd->autogenFilter;
1789 entry.size = pCmd->size;
1790 entry.mobid = SVGA_ID_INVALID;
1791 entry.arraySize = pCmd->arraySize;
1792 // entry.mobPitch = 0;
1793 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1794 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1795 if (RT_SUCCESS(rc))
1796 {
1797 /* Create the host surface. */
1798 /** @todo fGBO = true flag. */
1799 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1800 pCmd->multisampleCount, pCmd->autogenFilter,
1801 pCmd->numMipLevels, &pCmd->size);
1802 }
1803}
1804
1805
1806/* SVGA_3D_CMD_DEFINE_GB_MOB64 1135 */
1807static void vmsvga3dCmdDefineGBMob64(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob64 const *pCmd)
1808{
1809// ASMBreakpoint();
1810 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1811
1812 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1813
1814 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1815 /* Allocate a structure for the MOB. */
1816 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1817 AssertPtrReturnVoid(pMob);
1818
1819 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ true, pMob);
1820 if (RT_SUCCESS(rc))
1821 {
1822 return;
1823 }
1824
1825 RTMemFree(pMob);
1826}
1827
1828
1829/* SVGA_3D_CMD_DX_DEFINE_CONTEXT 1143 */
1830static int vmsvga3dCmdDXDefineContext(PVGASTATECC pThisCC, SVGA3dCmdDXDefineContext const *pCmd, uint32_t cbCmd)
1831{
1832#ifdef VMSVGA3D_DX
1833//ASMBreakpoint();
1834 RT_NOREF(cbCmd);
1835
1836 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1837
1838 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
1839 SVGAOTableDXContextEntry entry;
1840 RT_ZERO(entry);
1841 entry.cid = pCmd->cid;
1842 entry.mobid = SVGA_ID_INVALID;
1843 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1844 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1845 if (RT_SUCCESS(rc))
1846 {
1847 /* Create the host context. */
1848 rc = vmsvga3dDXDefineContext(pThisCC, pCmd->cid);
1849 }
1850
1851 return rc;
1852#else
1853 RT_NOREF(pThisCC, pCmd, cbCmd);
1854 return VERR_NOT_SUPPORTED;
1855#endif
1856}
1857
1858
1859/* SVGA_3D_CMD_DX_DESTROY_CONTEXT 1144 */
1860static int vmsvga3dCmdDXDestroyContext(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyContext const *pCmd, uint32_t cbCmd)
1861{
1862#ifdef VMSVGA3D_DX
1863//ASMBreakpoint();
1864 RT_NOREF(cbCmd);
1865
1866 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1867
1868 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
1869 SVGAOTableDXContextEntry entry;
1870 RT_ZERO(entry);
1871 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1872 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1873
1874 return vmsvga3dDXDestroyContext(pThisCC, pCmd->cid);
1875#else
1876 RT_NOREF(pThisCC, pCmd, cbCmd);
1877 return VERR_NOT_SUPPORTED;
1878#endif
1879}
1880
1881
1882/* SVGA_3D_CMD_DX_BIND_CONTEXT 1145 */
1883static int vmsvga3dCmdDXBindContext(PVGASTATECC pThisCC, SVGA3dCmdDXBindContext const *pCmd, uint32_t cbCmd)
1884{
1885#ifdef VMSVGA3D_DX
1886//ASMBreakpoint();
1887 RT_NOREF(cbCmd);
1888
1889 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1890
1891 /* Assign a mobid to a cid. */
1892 int rc = VINF_SUCCESS;
1893 if (pCmd->mobid != SVGA_ID_INVALID)
1894 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1895 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1896 if (RT_SUCCESS(rc))
1897 {
1898 SVGAOTableDXContextEntry entry;
1899 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1900 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1901 if (RT_SUCCESS(rc))
1902 {
1903 SVGADXContextMobFormat *pSvgaDXContext = NULL;
1904 if (pCmd->mobid != entry.mobid && entry.mobid != SVGA_ID_INVALID)
1905 {
1906 /* Unbind notification to the DX backend. Copy the context data to the guest backing memory. */
1907 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
1908 if (pSvgaDXContext)
1909 {
1910 rc = vmsvga3dDXUnbindContext(pThisCC, pCmd->cid, pSvgaDXContext);
1911 if (RT_SUCCESS(rc))
1912 {
1913 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
1914 if (pMob)
1915 {
1916 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
1917 }
1918 }
1919
1920 RTMemFree(pSvgaDXContext);
1921 pSvgaDXContext = NULL;
1922 }
1923 }
1924
1925 if (pCmd->mobid != SVGA_ID_INVALID)
1926 {
1927 /* Bind a new context. Copy existing data from the guest backing memory. */
1928 if (pCmd->validContents)
1929 {
1930 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
1931 if (pMob)
1932 {
1933 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
1934 if (pSvgaDXContext)
1935 {
1936 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
1937 if (RT_FAILURE(rc))
1938 {
1939 RTMemFree(pSvgaDXContext);
1940 pSvgaDXContext = NULL;
1941 }
1942 }
1943 }
1944 }
1945
1946 rc = vmsvga3dDXBindContext(pThisCC, pCmd->cid, pSvgaDXContext);
1947
1948 RTMemFree(pSvgaDXContext);
1949 }
1950
1951 /* Update the object table. */
1952 entry.mobid = pCmd->mobid;
1953 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1954 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1955 }
1956 }
1957
1958 return rc;
1959#else
1960 RT_NOREF(pThisCC, pCmd, cbCmd);
1961 return VERR_NOT_SUPPORTED;
1962#endif
1963}
1964
1965
1966/* SVGA_3D_CMD_DX_READBACK_CONTEXT 1146 */
1967static int vmsvga3dCmdDXReadbackContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackContext const *pCmd, uint32_t cbCmd)
1968{
1969#ifdef VMSVGA3D_DX
1970ASMBreakpoint();
1971 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1972 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
1973 return vmsvga3dDXReadbackContext(pThisCC, idDXContext);
1974#else
1975 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
1976 return VERR_NOT_SUPPORTED;
1977#endif
1978}
1979
1980
1981/* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT 1147 */
1982static int vmsvga3dCmdDXInvalidateContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateContext const *pCmd, uint32_t cbCmd)
1983{
1984#ifdef VMSVGA3D_DX
1985ASMBreakpoint();
1986 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1987 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
1988 return vmsvga3dDXInvalidateContext(pThisCC, idDXContext);
1989#else
1990 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
1991 return VERR_NOT_SUPPORTED;
1992#endif
1993}
1994
1995
1996/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER 1148 */
1997static int vmsvga3dCmdDXSetSingleConstantBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSingleConstantBuffer const *pCmd, uint32_t cbCmd)
1998{
1999#ifdef VMSVGA3D_DX
2000//ASMBreakpoint();
2001 RT_NOREF(cbCmd);
2002 return vmsvga3dDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd);
2003#else
2004 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2005 return VERR_NOT_SUPPORTED;
2006#endif
2007}
2008
2009
2010/* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES 1149 */
2011static int vmsvga3dCmdDXSetShaderResources(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderResources const *pCmd, uint32_t cbCmd)
2012{
2013#ifdef VMSVGA3D_DX
2014//ASMBreakpoint();
2015 SVGA3dShaderResourceViewId const *paShaderResourceViewId = (SVGA3dShaderResourceViewId *)&pCmd[1];
2016 uint32_t const cShaderResourceViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dShaderResourceViewId);
2017 return vmsvga3dDXSetShaderResources(pThisCC, idDXContext, pCmd, cShaderResourceViewId, paShaderResourceViewId);
2018#else
2019 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2020 return VERR_NOT_SUPPORTED;
2021#endif
2022}
2023
2024
2025/* SVGA_3D_CMD_DX_SET_SHADER 1150 */
2026static int vmsvga3dCmdDXSetShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShader const *pCmd, uint32_t cbCmd)
2027{
2028#ifdef VMSVGA3D_DX
2029//ASMBreakpoint();
2030 RT_NOREF(cbCmd);
2031 return vmsvga3dDXSetShader(pThisCC, idDXContext, pCmd);
2032#else
2033 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2034 return VERR_NOT_SUPPORTED;
2035#endif
2036}
2037
2038
2039/* SVGA_3D_CMD_DX_SET_SAMPLERS 1151 */
2040static int vmsvga3dCmdDXSetSamplers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSamplers const *pCmd, uint32_t cbCmd)
2041{
2042#ifdef VMSVGA3D_DX
2043//ASMBreakpoint();
2044 SVGA3dSamplerId const *paSamplerId = (SVGA3dSamplerId *)&pCmd[1];
2045 uint32_t const cSamplerId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSamplerId);
2046 return vmsvga3dDXSetSamplers(pThisCC, idDXContext, pCmd, cSamplerId, paSamplerId);
2047#else
2048 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2049 return VERR_NOT_SUPPORTED;
2050#endif
2051}
2052
2053
2054/* SVGA_3D_CMD_DX_DRAW 1152 */
2055static int vmsvga3dCmdDXDraw(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDraw const *pCmd, uint32_t cbCmd)
2056{
2057#ifdef VMSVGA3D_DX
2058//ASMBreakpoint();
2059 RT_NOREF(cbCmd);
2060 return vmsvga3dDXDraw(pThisCC, idDXContext, pCmd);
2061#else
2062 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2063 return VERR_NOT_SUPPORTED;
2064#endif
2065}
2066
2067
2068/* SVGA_3D_CMD_DX_DRAW_INDEXED 1153 */
2069static int vmsvga3dCmdDXDrawIndexed(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexed const *pCmd, uint32_t cbCmd)
2070{
2071#ifdef VMSVGA3D_DX
2072//ASMBreakpoint();
2073 RT_NOREF(cbCmd);
2074 return vmsvga3dDXDrawIndexed(pThisCC, idDXContext, pCmd);
2075#else
2076 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2077 return VERR_NOT_SUPPORTED;
2078#endif
2079}
2080
2081
2082/* SVGA_3D_CMD_DX_DRAW_INSTANCED 1154 */
2083static int vmsvga3dCmdDXDrawInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstanced const *pCmd, uint32_t cbCmd)
2084{
2085#ifdef VMSVGA3D_DX
2086ASMBreakpoint();
2087 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2088 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2089 return vmsvga3dDXDrawInstanced(pThisCC, idDXContext);
2090#else
2091 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2092 return VERR_NOT_SUPPORTED;
2093#endif
2094}
2095
2096
2097/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED 1155 */
2098static int vmsvga3dCmdDXDrawIndexedInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstanced const *pCmd, uint32_t cbCmd)
2099{
2100#ifdef VMSVGA3D_DX
2101ASMBreakpoint();
2102 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2103 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2104 return vmsvga3dDXDrawIndexedInstanced(pThisCC, idDXContext);
2105#else
2106 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2107 return VERR_NOT_SUPPORTED;
2108#endif
2109}
2110
2111
2112/* SVGA_3D_CMD_DX_DRAW_AUTO 1156 */
2113static int vmsvga3dCmdDXDrawAuto(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawAuto const *pCmd, uint32_t cbCmd)
2114{
2115#ifdef VMSVGA3D_DX
2116ASMBreakpoint();
2117 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2118 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2119 return vmsvga3dDXDrawAuto(pThisCC, idDXContext);
2120#else
2121 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2122 return VERR_NOT_SUPPORTED;
2123#endif
2124}
2125
2126
2127/* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT 1157 */
2128static int vmsvga3dCmdDXSetInputLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetInputLayout const *pCmd, uint32_t cbCmd)
2129{
2130#ifdef VMSVGA3D_DX
2131//ASMBreakpoint();
2132 RT_NOREF(cbCmd);
2133 return vmsvga3dDXSetInputLayout(pThisCC, idDXContext, pCmd->elementLayoutId);
2134#else
2135 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2136 return VERR_NOT_SUPPORTED;
2137#endif
2138}
2139
2140
2141/* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS 1158 */
2142static int vmsvga3dCmdDXSetVertexBuffers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVertexBuffers const *pCmd, uint32_t cbCmd)
2143{
2144#ifdef VMSVGA3D_DX
2145//ASMBreakpoint();
2146 SVGA3dVertexBuffer const *paVertexBuffer = (SVGA3dVertexBuffer *)&pCmd[1];
2147 uint32_t const cVertexBuffer = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dVertexBuffer);
2148 return vmsvga3dDXSetVertexBuffers(pThisCC, idDXContext, pCmd->startBuffer, cVertexBuffer, paVertexBuffer);
2149#else
2150 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2151 return VERR_NOT_SUPPORTED;
2152#endif
2153}
2154
2155
2156/* SVGA_3D_CMD_DX_SET_INDEX_BUFFER 1159 */
2157static int vmsvga3dCmdDXSetIndexBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetIndexBuffer const *pCmd, uint32_t cbCmd)
2158{
2159#ifdef VMSVGA3D_DX
2160//ASMBreakpoint();
2161 RT_NOREF(cbCmd);
2162 return vmsvga3dDXSetIndexBuffer(pThisCC, idDXContext, pCmd);
2163#else
2164 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2165 return VERR_NOT_SUPPORTED;
2166#endif
2167}
2168
2169
2170/* SVGA_3D_CMD_DX_SET_TOPOLOGY 1160 */
2171static int vmsvga3dCmdDXSetTopology(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetTopology const *pCmd, uint32_t cbCmd)
2172{
2173#ifdef VMSVGA3D_DX
2174//ASMBreakpoint();
2175 RT_NOREF(cbCmd);
2176 return vmsvga3dDXSetTopology(pThisCC, idDXContext, pCmd->topology);
2177#else
2178 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2179 return VERR_NOT_SUPPORTED;
2180#endif
2181}
2182
2183
2184/* SVGA_3D_CMD_DX_SET_RENDERTARGETS 1161 */
2185static int vmsvga3dCmdDXSetRenderTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRenderTargets const *pCmd, uint32_t cbCmd)
2186{
2187#ifdef VMSVGA3D_DX
2188//ASMBreakpoint();
2189 SVGA3dRenderTargetViewId const *paRenderTargetViewId = (SVGA3dRenderTargetViewId *)&pCmd[1];
2190 uint32_t const cRenderTargetViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderTargetViewId);
2191 return vmsvga3dDXSetRenderTargets(pThisCC, idDXContext, pCmd->depthStencilViewId, cRenderTargetViewId, paRenderTargetViewId);
2192#else
2193 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2194 return VERR_NOT_SUPPORTED;
2195#endif
2196}
2197
2198
2199/* SVGA_3D_CMD_DX_SET_BLEND_STATE 1162 */
2200static int vmsvga3dCmdDXSetBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetBlendState const *pCmd, uint32_t cbCmd)
2201{
2202#ifdef VMSVGA3D_DX
2203//ASMBreakpoint();
2204 RT_NOREF(cbCmd);
2205 return vmsvga3dDXSetBlendState(pThisCC, idDXContext, pCmd);
2206#else
2207 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2208 return VERR_NOT_SUPPORTED;
2209#endif
2210}
2211
2212
2213/* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE 1163 */
2214static int vmsvga3dCmdDXSetDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDepthStencilState const *pCmd, uint32_t cbCmd)
2215{
2216#ifdef VMSVGA3D_DX
2217//ASMBreakpoint();
2218 RT_NOREF(cbCmd);
2219 return vmsvga3dDXSetDepthStencilState(pThisCC, idDXContext, pCmd);
2220#else
2221 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2222 return VERR_NOT_SUPPORTED;
2223#endif
2224}
2225
2226
2227/* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE 1164 */
2228static int vmsvga3dCmdDXSetRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRasterizerState const *pCmd, uint32_t cbCmd)
2229{
2230#ifdef VMSVGA3D_DX
2231//ASMBreakpoint();
2232 RT_NOREF(cbCmd);
2233 return vmsvga3dDXSetRasterizerState(pThisCC, idDXContext, pCmd->rasterizerId);
2234#else
2235 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2236 return VERR_NOT_SUPPORTED;
2237#endif
2238}
2239
2240
2241/* SVGA_3D_CMD_DX_DEFINE_QUERY 1165 */
2242static int vmsvga3dCmdDXDefineQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineQuery const *pCmd, uint32_t cbCmd)
2243{
2244#ifdef VMSVGA3D_DX
2245ASMBreakpoint();
2246 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2247 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2248 return vmsvga3dDXDefineQuery(pThisCC, idDXContext);
2249#else
2250 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2251 return VERR_NOT_SUPPORTED;
2252#endif
2253}
2254
2255
2256/* SVGA_3D_CMD_DX_DESTROY_QUERY 1166 */
2257static int vmsvga3dCmdDXDestroyQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyQuery const *pCmd, uint32_t cbCmd)
2258{
2259#ifdef VMSVGA3D_DX
2260ASMBreakpoint();
2261 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2262 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2263 return vmsvga3dDXDestroyQuery(pThisCC, idDXContext);
2264#else
2265 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2266 return VERR_NOT_SUPPORTED;
2267#endif
2268}
2269
2270
2271/* SVGA_3D_CMD_DX_BIND_QUERY 1167 */
2272static int vmsvga3dCmdDXBindQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindQuery const *pCmd, uint32_t cbCmd)
2273{
2274#ifdef VMSVGA3D_DX
2275ASMBreakpoint();
2276 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2277 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2278 return vmsvga3dDXBindQuery(pThisCC, idDXContext);
2279#else
2280 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2281 return VERR_NOT_SUPPORTED;
2282#endif
2283}
2284
2285
2286/* SVGA_3D_CMD_DX_SET_QUERY_OFFSET 1168 */
2287static int vmsvga3dCmdDXSetQueryOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetQueryOffset const *pCmd, uint32_t cbCmd)
2288{
2289#ifdef VMSVGA3D_DX
2290ASMBreakpoint();
2291 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2292 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2293 return vmsvga3dDXSetQueryOffset(pThisCC, idDXContext);
2294#else
2295 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2296 return VERR_NOT_SUPPORTED;
2297#endif
2298}
2299
2300
2301/* SVGA_3D_CMD_DX_BEGIN_QUERY 1169 */
2302static int vmsvga3dCmdDXBeginQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBeginQuery const *pCmd, uint32_t cbCmd)
2303{
2304#ifdef VMSVGA3D_DX
2305ASMBreakpoint();
2306 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2307 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2308 return vmsvga3dDXBeginQuery(pThisCC, idDXContext);
2309#else
2310 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2311 return VERR_NOT_SUPPORTED;
2312#endif
2313}
2314
2315
2316/* SVGA_3D_CMD_DX_END_QUERY 1170 */
2317static int vmsvga3dCmdDXEndQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXEndQuery const *pCmd, uint32_t cbCmd)
2318{
2319#ifdef VMSVGA3D_DX
2320ASMBreakpoint();
2321 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2322 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2323 return vmsvga3dDXEndQuery(pThisCC, idDXContext);
2324#else
2325 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2326 return VERR_NOT_SUPPORTED;
2327#endif
2328}
2329
2330
2331/* SVGA_3D_CMD_DX_READBACK_QUERY 1171 */
2332static int vmsvga3dCmdDXReadbackQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackQuery const *pCmd, uint32_t cbCmd)
2333{
2334#ifdef VMSVGA3D_DX
2335ASMBreakpoint();
2336 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2337 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2338 return vmsvga3dDXReadbackQuery(pThisCC, idDXContext);
2339#else
2340 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2341 return VERR_NOT_SUPPORTED;
2342#endif
2343}
2344
2345
2346/* SVGA_3D_CMD_DX_SET_PREDICATION 1172 */
2347static int vmsvga3dCmdDXSetPredication(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPredication const *pCmd, uint32_t cbCmd)
2348{
2349#ifdef VMSVGA3D_DX
2350ASMBreakpoint();
2351 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2352 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2353 return vmsvga3dDXSetPredication(pThisCC, idDXContext);
2354#else
2355 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2356 return VERR_NOT_SUPPORTED;
2357#endif
2358}
2359
2360
2361/* SVGA_3D_CMD_DX_SET_SOTARGETS 1173 */
2362static int vmsvga3dCmdDXSetSOTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSOTargets const *pCmd, uint32_t cbCmd)
2363{
2364#ifdef VMSVGA3D_DX
2365ASMBreakpoint();
2366 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2367 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2368 return vmsvga3dDXSetSOTargets(pThisCC, idDXContext);
2369#else
2370 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2371 return VERR_NOT_SUPPORTED;
2372#endif
2373}
2374
2375
2376/* SVGA_3D_CMD_DX_SET_VIEWPORTS 1174 */
2377static int vmsvga3dCmdDXSetViewports(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetViewports const *pCmd, uint32_t cbCmd)
2378{
2379#ifdef VMSVGA3D_DX
2380//ASMBreakpoint();
2381 SVGA3dViewport const *paViewport = (SVGA3dViewport *)&pCmd[1];
2382 uint32_t const cViewport = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dViewport);
2383 return vmsvga3dDXSetViewports(pThisCC, idDXContext, cViewport, paViewport);
2384#else
2385 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2386 return VERR_NOT_SUPPORTED;
2387#endif
2388}
2389
2390
2391/* SVGA_3D_CMD_DX_SET_SCISSORRECTS 1175 */
2392static int vmsvga3dCmdDXSetScissorRects(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetScissorRects const *pCmd, uint32_t cbCmd)
2393{
2394#ifdef VMSVGA3D_DX
2395//ASMBreakpoint();
2396 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
2397 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
2398 return vmsvga3dDXSetScissorRects(pThisCC, idDXContext, cRect, paRect);
2399#else
2400 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2401 return VERR_NOT_SUPPORTED;
2402#endif
2403}
2404
2405
2406/* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW 1176 */
2407static int vmsvga3dCmdDXClearRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearRenderTargetView const *pCmd, uint32_t cbCmd)
2408{
2409#ifdef VMSVGA3D_DX
2410//ASMBreakpoint();
2411 RT_NOREF(cbCmd);
2412 return vmsvga3dDXClearRenderTargetView(pThisCC, idDXContext, pCmd);
2413#else
2414 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2415 return VERR_NOT_SUPPORTED;
2416#endif
2417}
2418
2419
2420/* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW 1177 */
2421static int vmsvga3dCmdDXClearDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearDepthStencilView const *pCmd, uint32_t cbCmd)
2422{
2423#ifdef VMSVGA3D_DX
2424//ASMBreakpoint();
2425 RT_NOREF(cbCmd);
2426 return vmsvga3dDXClearDepthStencilView(pThisCC, idDXContext, pCmd);
2427#else
2428 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2429 return VERR_NOT_SUPPORTED;
2430#endif
2431}
2432
2433
2434/* SVGA_3D_CMD_DX_PRED_COPY_REGION 1178 */
2435static int vmsvga3dCmdDXPredCopyRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopyRegion const *pCmd, uint32_t cbCmd)
2436{
2437#ifdef VMSVGA3D_DX
2438//ASMBreakpoint();
2439 RT_NOREF(cbCmd);
2440 return vmsvga3dDXPredCopyRegion(pThisCC, idDXContext, pCmd);
2441#else
2442 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2443 return VERR_NOT_SUPPORTED;
2444#endif
2445}
2446
2447
2448/* SVGA_3D_CMD_DX_PRED_COPY 1179 */
2449static int vmsvga3dCmdDXPredCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopy const *pCmd, uint32_t cbCmd)
2450{
2451#ifdef VMSVGA3D_DX
2452ASMBreakpoint();
2453 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2454 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2455 return vmsvga3dDXPredCopy(pThisCC, idDXContext);
2456#else
2457 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2458 return VERR_NOT_SUPPORTED;
2459#endif
2460}
2461
2462
2463/* SVGA_3D_CMD_DX_PRESENTBLT 1180 */
2464static int vmsvga3dCmdDXPresentBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPresentBlt const *pCmd, uint32_t cbCmd)
2465{
2466#ifdef VMSVGA3D_DX
2467ASMBreakpoint();
2468 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2469 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2470 return vmsvga3dDXPresentBlt(pThisCC, idDXContext);
2471#else
2472 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2473 return VERR_NOT_SUPPORTED;
2474#endif
2475}
2476
2477
2478/* SVGA_3D_CMD_DX_GENMIPS 1181 */
2479static int vmsvga3dCmdDXGenMips(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGenMips const *pCmd, uint32_t cbCmd)
2480{
2481#ifdef VMSVGA3D_DX
2482//ASMBreakpoint();
2483 RT_NOREF(cbCmd);
2484 return vmsvga3dDXGenMips(pThisCC, idDXContext, pCmd);
2485#else
2486 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2487 return VERR_NOT_SUPPORTED;
2488#endif
2489}
2490
2491
2492/* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE 1182 */
2493static int vmsvga3dCmdDXUpdateSubResource(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXUpdateSubResource const *pCmd, uint32_t cbCmd)
2494{
2495#ifdef VMSVGA3D_DX
2496ASMBreakpoint();
2497 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2498 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2499 return vmsvga3dDXUpdateSubResource(pThisCC, idDXContext);
2500#else
2501 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2502 return VERR_NOT_SUPPORTED;
2503#endif
2504}
2505
2506
2507/* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE 1183 */
2508static int vmsvga3dCmdDXReadbackSubResource(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackSubResource const *pCmd, uint32_t cbCmd)
2509{
2510#ifdef VMSVGA3D_DX
2511ASMBreakpoint();
2512 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2513 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2514 return vmsvga3dDXReadbackSubResource(pThisCC, idDXContext);
2515#else
2516 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2517 return VERR_NOT_SUPPORTED;
2518#endif
2519}
2520
2521
2522/* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE 1184 */
2523static int vmsvga3dCmdDXInvalidateSubResource(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateSubResource const *pCmd, uint32_t cbCmd)
2524{
2525#ifdef VMSVGA3D_DX
2526ASMBreakpoint();
2527 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2528 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2529 return vmsvga3dDXInvalidateSubResource(pThisCC, idDXContext);
2530#else
2531 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2532 return VERR_NOT_SUPPORTED;
2533#endif
2534}
2535
2536
2537/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW 1185 */
2538static int vmsvga3dCmdDXDefineShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShaderResourceView const *pCmd, uint32_t cbCmd)
2539{
2540#ifdef VMSVGA3D_DX
2541//ASMBreakpoint();
2542 RT_NOREF(cbCmd);
2543 return vmsvga3dDXDefineShaderResourceView(pThisCC, idDXContext, pCmd);
2544#else
2545 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2546 return VERR_NOT_SUPPORTED;
2547#endif
2548}
2549
2550
2551/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW 1186 */
2552static int vmsvga3dCmdDXDestroyShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShaderResourceView const *pCmd, uint32_t cbCmd)
2553{
2554#ifdef VMSVGA3D_DX
2555//ASMBreakpoint();
2556 RT_NOREF(cbCmd);
2557 return vmsvga3dDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd);
2558#else
2559 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2560 return VERR_NOT_SUPPORTED;
2561#endif
2562}
2563
2564
2565/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW 1187 */
2566static int vmsvga3dCmdDXDefineRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRenderTargetView const *pCmd, uint32_t cbCmd)
2567{
2568#ifdef VMSVGA3D_DX
2569//ASMBreakpoint();
2570 RT_NOREF(cbCmd);
2571 return vmsvga3dDXDefineRenderTargetView(pThisCC, idDXContext, pCmd);
2572#else
2573 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2574 return VERR_NOT_SUPPORTED;
2575#endif
2576}
2577
2578
2579/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW 1188 */
2580static int vmsvga3dCmdDXDestroyRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRenderTargetView const *pCmd, uint32_t cbCmd)
2581{
2582#ifdef VMSVGA3D_DX
2583//ASMBreakpoint();
2584 RT_NOREF(cbCmd);
2585 return vmsvga3dDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd);
2586#else
2587 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2588 return VERR_NOT_SUPPORTED;
2589#endif
2590}
2591
2592
2593/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW 1189 */
2594static int vmsvga3dCmdDXDefineDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView const *pCmd, uint32_t cbCmd)
2595{
2596#ifdef VMSVGA3D_DX
2597//ASMBreakpoint();
2598 RT_NOREF(cbCmd);
2599 SVGA3dCmdDXDefineDepthStencilView_v2 cmd;
2600 cmd.depthStencilViewId = pCmd->depthStencilViewId;
2601 cmd.sid = pCmd->sid;
2602 cmd.format = pCmd->format;
2603 cmd.resourceDimension = pCmd->resourceDimension;
2604 cmd.mipSlice = pCmd->mipSlice;
2605 cmd.firstArraySlice = pCmd->firstArraySlice;
2606 cmd.arraySize = pCmd->arraySize;
2607 cmd.flags = 0;
2608 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, &cmd);
2609#else
2610 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2611 return VERR_NOT_SUPPORTED;
2612#endif
2613}
2614
2615
2616/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW 1190 */
2617static int vmsvga3dCmdDXDestroyDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilView const *pCmd, uint32_t cbCmd)
2618{
2619#ifdef VMSVGA3D_DX
2620//ASMBreakpoint();
2621 RT_NOREF(cbCmd);
2622 return vmsvga3dDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd);
2623#else
2624 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2625 return VERR_NOT_SUPPORTED;
2626#endif
2627}
2628
2629
2630/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT 1191 */
2631static int vmsvga3dCmdDXDefineElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineElementLayout const *pCmd, uint32_t cbCmd)
2632{
2633#ifdef VMSVGA3D_DX
2634//ASMBreakpoint();
2635 SVGA3dInputElementDesc const *paDesc = (SVGA3dInputElementDesc *)&pCmd[1];
2636 uint32_t const cDesc = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dInputElementDesc);
2637 return vmsvga3dDXDefineElementLayout(pThisCC, idDXContext, pCmd->elementLayoutId, cDesc, paDesc);
2638#else
2639 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2640 return VERR_NOT_SUPPORTED;
2641#endif
2642}
2643
2644
2645/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT 1192 */
2646static int vmsvga3dCmdDXDestroyElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyElementLayout const *pCmd, uint32_t cbCmd)
2647{
2648#ifdef VMSVGA3D_DX
2649ASMBreakpoint();
2650 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2651 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2652 return vmsvga3dDXDestroyElementLayout(pThisCC, idDXContext);
2653#else
2654 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2655 return VERR_NOT_SUPPORTED;
2656#endif
2657}
2658
2659
2660/* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE 1193 */
2661static int vmsvga3dCmdDXDefineBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineBlendState const *pCmd, uint32_t cbCmd)
2662{
2663#ifdef VMSVGA3D_DX
2664//ASMBreakpoint();
2665 RT_NOREF(cbCmd);
2666 return vmsvga3dDXDefineBlendState(pThisCC, idDXContext, pCmd);
2667#else
2668 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2669 return VERR_NOT_SUPPORTED;
2670#endif
2671}
2672
2673
2674/* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE 1194 */
2675static int vmsvga3dCmdDXDestroyBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyBlendState const *pCmd, uint32_t cbCmd)
2676{
2677#ifdef VMSVGA3D_DX
2678ASMBreakpoint();
2679 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2680 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2681 return vmsvga3dDXDestroyBlendState(pThisCC, idDXContext);
2682#else
2683 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2684 return VERR_NOT_SUPPORTED;
2685#endif
2686}
2687
2688
2689/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE 1195 */
2690static int vmsvga3dCmdDXDefineDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilState const *pCmd, uint32_t cbCmd)
2691{
2692#ifdef VMSVGA3D_DX
2693//ASMBreakpoint();
2694 RT_NOREF(cbCmd);
2695 return vmsvga3dDXDefineDepthStencilState(pThisCC, idDXContext, pCmd);
2696#else
2697 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2698 return VERR_NOT_SUPPORTED;
2699#endif
2700}
2701
2702
2703/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE 1196 */
2704static int vmsvga3dCmdDXDestroyDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilState const *pCmd, uint32_t cbCmd)
2705{
2706#ifdef VMSVGA3D_DX
2707ASMBreakpoint();
2708 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2709 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2710 return vmsvga3dDXDestroyDepthStencilState(pThisCC, idDXContext);
2711#else
2712 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2713 return VERR_NOT_SUPPORTED;
2714#endif
2715}
2716
2717
2718/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE 1197 */
2719static int vmsvga3dCmdDXDefineRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRasterizerState const *pCmd, uint32_t cbCmd)
2720{
2721#ifdef VMSVGA3D_DX
2722//ASMBreakpoint();
2723 RT_NOREF(cbCmd);
2724 return vmsvga3dDXDefineRasterizerState(pThisCC, idDXContext, pCmd);
2725#else
2726 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2727 return VERR_NOT_SUPPORTED;
2728#endif
2729}
2730
2731
2732/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE 1198 */
2733static int vmsvga3dCmdDXDestroyRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRasterizerState const *pCmd, uint32_t cbCmd)
2734{
2735#ifdef VMSVGA3D_DX
2736ASMBreakpoint();
2737 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2738 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2739 return vmsvga3dDXDestroyRasterizerState(pThisCC, idDXContext);
2740#else
2741 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2742 return VERR_NOT_SUPPORTED;
2743#endif
2744}
2745
2746
2747/* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE 1199 */
2748static int vmsvga3dCmdDXDefineSamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineSamplerState const *pCmd, uint32_t cbCmd)
2749{
2750#ifdef VMSVGA3D_DX
2751//ASMBreakpoint();
2752 RT_NOREF(cbCmd);
2753 return vmsvga3dDXDefineSamplerState(pThisCC, idDXContext, pCmd);
2754#else
2755 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2756 return VERR_NOT_SUPPORTED;
2757#endif
2758}
2759
2760
2761/* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE 1200 */
2762static int vmsvga3dCmdDXDestroySamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroySamplerState const *pCmd, uint32_t cbCmd)
2763{
2764#ifdef VMSVGA3D_DX
2765ASMBreakpoint();
2766 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2767 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2768 return vmsvga3dDXDestroySamplerState(pThisCC, idDXContext);
2769#else
2770 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2771 return VERR_NOT_SUPPORTED;
2772#endif
2773}
2774
2775
2776/* SVGA_3D_CMD_DX_DEFINE_SHADER 1201 */
2777static int vmsvga3dCmdDXDefineShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShader const *pCmd, uint32_t cbCmd)
2778{
2779#ifdef VMSVGA3D_DX
2780//ASMBreakpoint();
2781 RT_NOREF(cbCmd);
2782 return vmsvga3dDXDefineShader(pThisCC, idDXContext, pCmd);
2783#else
2784 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2785 return VERR_NOT_SUPPORTED;
2786#endif
2787}
2788
2789
2790/* SVGA_3D_CMD_DX_DESTROY_SHADER 1202 */
2791static int vmsvga3dCmdDXDestroyShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShader const *pCmd, uint32_t cbCmd)
2792{
2793#ifdef VMSVGA3D_DX
2794ASMBreakpoint();
2795 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2796 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2797 return vmsvga3dDXDestroyShader(pThisCC, idDXContext);
2798#else
2799 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2800 return VERR_NOT_SUPPORTED;
2801#endif
2802}
2803
2804
2805/* SVGA_3D_CMD_DX_BIND_SHADER 1203 */
2806static int vmsvga3dCmdDXBindShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShader const *pCmd, uint32_t cbCmd)
2807{
2808#ifdef VMSVGA3D_DX
2809//ASMBreakpoint();
2810 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2811 RT_NOREF(idDXContext, cbCmd);
2812 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
2813 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2814 return vmsvga3dDXBindShader(pThisCC, pCmd, pMob);
2815#else
2816 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2817 return VERR_NOT_SUPPORTED;
2818#endif
2819}
2820
2821
2822/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT 1204 */
2823static int vmsvga3dCmdDXDefineStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutput const *pCmd, uint32_t cbCmd)
2824{
2825#ifdef VMSVGA3D_DX
2826ASMBreakpoint();
2827 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2828 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2829 return vmsvga3dDXDefineStreamOutput(pThisCC, idDXContext);
2830#else
2831 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2832 return VERR_NOT_SUPPORTED;
2833#endif
2834}
2835
2836
2837/* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT 1205 */
2838static int vmsvga3dCmdDXDestroyStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyStreamOutput const *pCmd, uint32_t cbCmd)
2839{
2840#ifdef VMSVGA3D_DX
2841ASMBreakpoint();
2842 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2843 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2844 return vmsvga3dDXDestroyStreamOutput(pThisCC, idDXContext);
2845#else
2846 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2847 return VERR_NOT_SUPPORTED;
2848#endif
2849}
2850
2851
2852/* SVGA_3D_CMD_DX_SET_STREAMOUTPUT 1206 */
2853static int vmsvga3dCmdDXSetStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStreamOutput const *pCmd, uint32_t cbCmd)
2854{
2855#ifdef VMSVGA3D_DX
2856ASMBreakpoint();
2857 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2858 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2859 return vmsvga3dDXSetStreamOutput(pThisCC, idDXContext);
2860#else
2861 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2862 return VERR_NOT_SUPPORTED;
2863#endif
2864}
2865
2866
2867/* SVGA_3D_CMD_DX_SET_COTABLE 1207 */
2868static int vmsvga3dCmdDXSetCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXSetCOTable const *pCmd, uint32_t cbCmd)
2869{
2870#ifdef VMSVGA3D_DX
2871//ASMBreakpoint();
2872 RT_NOREF(cbCmd);
2873 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2874 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
2875 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2876 return vmsvga3dDXSetCOTable(pThisCC, pCmd, pMob);
2877#else
2878 RT_NOREF(pThisCC, pCmd, cbCmd);
2879 return VERR_NOT_SUPPORTED;
2880#endif
2881}
2882
2883
2884/* SVGA_3D_CMD_DX_READBACK_COTABLE 1208 */
2885static int vmsvga3dCmdDXReadbackCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackCOTable const *pCmd, uint32_t cbCmd)
2886{
2887#ifdef VMSVGA3D_DX
2888//ASMBreakpoint();
2889 RT_NOREF(idDXContext, cbCmd);
2890 return vmsvga3dDXReadbackCOTable(pThisCC, pCmd);
2891#else
2892 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2893 return VERR_NOT_SUPPORTED;
2894#endif
2895}
2896
2897
2898/* SVGA_3D_CMD_DX_BUFFER_COPY 1209 */
2899static int vmsvga3dCmdDXBufferCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferCopy const *pCmd, uint32_t cbCmd)
2900{
2901#ifdef VMSVGA3D_DX
2902ASMBreakpoint();
2903 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2904 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2905 return vmsvga3dDXBufferCopy(pThisCC, idDXContext);
2906#else
2907 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2908 return VERR_NOT_SUPPORTED;
2909#endif
2910}
2911
2912
2913/* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER 1210 */
2914static int vmsvga3dCmdDXTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferFromBuffer const *pCmd, uint32_t cbCmd)
2915{
2916#ifdef VMSVGA3D_DX
2917ASMBreakpoint();
2918 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2919 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2920 return vmsvga3dDXTransferFromBuffer(pThisCC, idDXContext);
2921#else
2922 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2923 return VERR_NOT_SUPPORTED;
2924#endif
2925}
2926
2927
2928/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK 1211 */
2929static int vmsvga3dCmdDXSurfaceCopyAndReadback(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSurfaceCopyAndReadback const *pCmd, uint32_t cbCmd)
2930{
2931#ifdef VMSVGA3D_DX
2932ASMBreakpoint();
2933 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2934 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2935 return vmsvga3dDXSurfaceCopyAndReadback(pThisCC, idDXContext);
2936#else
2937 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2938 return VERR_NOT_SUPPORTED;
2939#endif
2940}
2941
2942
2943/* SVGA_3D_CMD_DX_MOVE_QUERY 1212 */
2944static int vmsvga3dCmdDXMoveQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMoveQuery const *pCmd, uint32_t cbCmd)
2945{
2946#ifdef VMSVGA3D_DX
2947ASMBreakpoint();
2948 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2949 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2950 return vmsvga3dDXMoveQuery(pThisCC, idDXContext);
2951#else
2952 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2953 return VERR_NOT_SUPPORTED;
2954#endif
2955}
2956
2957
2958/* SVGA_3D_CMD_DX_BIND_ALL_QUERY 1213 */
2959static int vmsvga3dCmdDXBindAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllQuery const *pCmd, uint32_t cbCmd)
2960{
2961#ifdef VMSVGA3D_DX
2962ASMBreakpoint();
2963 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2964 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2965 return vmsvga3dDXBindAllQuery(pThisCC, idDXContext);
2966#else
2967 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2968 return VERR_NOT_SUPPORTED;
2969#endif
2970}
2971
2972
2973/* SVGA_3D_CMD_DX_READBACK_ALL_QUERY 1214 */
2974static int vmsvga3dCmdDXReadbackAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackAllQuery const *pCmd, uint32_t cbCmd)
2975{
2976#ifdef VMSVGA3D_DX
2977ASMBreakpoint();
2978 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2979 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2980 return vmsvga3dDXReadbackAllQuery(pThisCC, idDXContext);
2981#else
2982 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2983 return VERR_NOT_SUPPORTED;
2984#endif
2985}
2986
2987
2988/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER 1215 */
2989static int vmsvga3dCmdDXPredTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredTransferFromBuffer const *pCmd, uint32_t cbCmd)
2990{
2991#ifdef VMSVGA3D_DX
2992ASMBreakpoint();
2993 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2994 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2995 return vmsvga3dDXPredTransferFromBuffer(pThisCC, idDXContext);
2996#else
2997 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2998 return VERR_NOT_SUPPORTED;
2999#endif
3000}
3001
3002
3003/* SVGA_3D_CMD_DX_MOB_FENCE_64 1216 */
3004static int vmsvga3dCmdDXMobFence64(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMobFence64 const *pCmd, uint32_t cbCmd)
3005{
3006#ifdef VMSVGA3D_DX
3007ASMBreakpoint();
3008 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3009 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3010 return vmsvga3dDXMobFence64(pThisCC, idDXContext);
3011#else
3012 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3013 return VERR_NOT_SUPPORTED;
3014#endif
3015}
3016
3017
3018/* SVGA_3D_CMD_DX_BIND_ALL_SHADER 1217 */
3019static int vmsvga3dCmdDXBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllShader const *pCmd, uint32_t cbCmd)
3020{
3021#ifdef VMSVGA3D_DX
3022ASMBreakpoint();
3023 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3024 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3025 return vmsvga3dDXBindAllShader(pThisCC, idDXContext);
3026#else
3027 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3028 return VERR_NOT_SUPPORTED;
3029#endif
3030}
3031
3032
3033/* SVGA_3D_CMD_DX_HINT 1218 */
3034static int vmsvga3dCmdDXHint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXHint const *pCmd, uint32_t cbCmd)
3035{
3036#ifdef VMSVGA3D_DX
3037ASMBreakpoint();
3038 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3039 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3040 return vmsvga3dDXHint(pThisCC, idDXContext);
3041#else
3042 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3043 return VERR_NOT_SUPPORTED;
3044#endif
3045}
3046
3047
3048/* SVGA_3D_CMD_DX_BUFFER_UPDATE 1219 */
3049static int vmsvga3dCmdDXBufferUpdate(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferUpdate const *pCmd, uint32_t cbCmd)
3050{
3051#ifdef VMSVGA3D_DX
3052ASMBreakpoint();
3053 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3054 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3055 return vmsvga3dDXBufferUpdate(pThisCC, idDXContext);
3056#else
3057 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3058 return VERR_NOT_SUPPORTED;
3059#endif
3060}
3061
3062
3063/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET 1220 */
3064static int vmsvga3dCmdDXSetVSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3065{
3066#ifdef VMSVGA3D_DX
3067ASMBreakpoint();
3068 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3069 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3070 return vmsvga3dDXSetVSConstantBufferOffset(pThisCC, idDXContext);
3071#else
3072 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3073 return VERR_NOT_SUPPORTED;
3074#endif
3075}
3076
3077
3078/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET 1221 */
3079static int vmsvga3dCmdDXSetPSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3080{
3081#ifdef VMSVGA3D_DX
3082ASMBreakpoint();
3083 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3084 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3085 return vmsvga3dDXSetPSConstantBufferOffset(pThisCC, idDXContext);
3086#else
3087 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3088 return VERR_NOT_SUPPORTED;
3089#endif
3090}
3091
3092
3093/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET 1222 */
3094static int vmsvga3dCmdDXSetGSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetGSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3095{
3096#ifdef VMSVGA3D_DX
3097ASMBreakpoint();
3098 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3099 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3100 return vmsvga3dDXSetGSConstantBufferOffset(pThisCC, idDXContext);
3101#else
3102 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3103 return VERR_NOT_SUPPORTED;
3104#endif
3105}
3106
3107
3108/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET 1223 */
3109static int vmsvga3dCmdDXSetHSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetHSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3110{
3111#ifdef VMSVGA3D_DX
3112ASMBreakpoint();
3113 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3114 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3115 return vmsvga3dDXSetHSConstantBufferOffset(pThisCC, idDXContext);
3116#else
3117 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3118 return VERR_NOT_SUPPORTED;
3119#endif
3120}
3121
3122
3123/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET 1224 */
3124static int vmsvga3dCmdDXSetDSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3125{
3126#ifdef VMSVGA3D_DX
3127ASMBreakpoint();
3128 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3129 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3130 return vmsvga3dDXSetDSConstantBufferOffset(pThisCC, idDXContext);
3131#else
3132 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3133 return VERR_NOT_SUPPORTED;
3134#endif
3135}
3136
3137
3138/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET 1225 */
3139static int vmsvga3dCmdDXSetCSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3140{
3141#ifdef VMSVGA3D_DX
3142ASMBreakpoint();
3143 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3144 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3145 return vmsvga3dDXSetCSConstantBufferOffset(pThisCC, idDXContext);
3146#else
3147 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3148 return VERR_NOT_SUPPORTED;
3149#endif
3150}
3151
3152
3153/* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER 1226 */
3154static int vmsvga3dCmdDXCondBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCondBindAllShader const *pCmd, uint32_t cbCmd)
3155{
3156#ifdef VMSVGA3D_DX
3157ASMBreakpoint();
3158 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3159 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3160 return vmsvga3dDXCondBindAllShader(pThisCC, idDXContext);
3161#else
3162 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3163 return VERR_NOT_SUPPORTED;
3164#endif
3165}
3166
3167
3168/* SVGA_3D_CMD_SCREEN_COPY 1227 */
3169static int vmsvga3dCmdScreenCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdScreenCopy const *pCmd, uint32_t cbCmd)
3170{
3171#ifdef VMSVGA3D_DX
3172ASMBreakpoint();
3173 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3174 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3175 return vmsvga3dScreenCopy(pThisCC, idDXContext);
3176#else
3177 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3178 return VERR_NOT_SUPPORTED;
3179#endif
3180}
3181
3182
3183/* SVGA_3D_CMD_GROW_OTABLE 1236 */
3184static int vmsvga3dCmdGrowOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdGrowOTable const *pCmd, uint32_t cbCmd)
3185{
3186#ifdef VMSVGA3D_DX
3187ASMBreakpoint();
3188 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3189 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3190 return vmsvga3dGrowOTable(pThisCC, idDXContext);
3191#else
3192 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3193 return VERR_NOT_SUPPORTED;
3194#endif
3195}
3196
3197
3198/* SVGA_3D_CMD_DX_GROW_COTABLE 1237 */
3199static int vmsvga3dCmdDXGrowCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGrowCOTable const *pCmd, uint32_t cbCmd)
3200{
3201#ifdef VMSVGA3D_DX
3202ASMBreakpoint();
3203 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3204 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3205 return vmsvga3dDXGrowCOTable(pThisCC, idDXContext);
3206#else
3207 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3208 return VERR_NOT_SUPPORTED;
3209#endif
3210}
3211
3212
3213/* SVGA_3D_CMD_INTRA_SURFACE_COPY 1238 */
3214static int vmsvga3dCmdIntraSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdIntraSurfaceCopy const *pCmd, uint32_t cbCmd)
3215{
3216#ifdef VMSVGA3D_DX
3217ASMBreakpoint();
3218 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3219 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3220 return vmsvga3dIntraSurfaceCopy(pThisCC, idDXContext);
3221#else
3222 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3223 return VERR_NOT_SUPPORTED;
3224#endif
3225}
3226
3227
3228/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 1239 */
3229static int vmsvga3dCmdDefineGBSurface_v3(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v3 const *pCmd, uint32_t cbCmd)
3230{
3231#ifdef VMSVGA3D_DX
3232ASMBreakpoint();
3233 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3234 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3235 return vmsvga3dDefineGBSurface_v3(pThisCC, idDXContext);
3236#else
3237 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3238 return VERR_NOT_SUPPORTED;
3239#endif
3240}
3241
3242
3243/* SVGA_3D_CMD_DX_RESOLVE_COPY 1240 */
3244static int vmsvga3dCmdDXResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXResolveCopy const *pCmd, uint32_t cbCmd)
3245{
3246#ifdef VMSVGA3D_DX
3247ASMBreakpoint();
3248 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3249 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3250 return vmsvga3dDXResolveCopy(pThisCC, idDXContext);
3251#else
3252 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3253 return VERR_NOT_SUPPORTED;
3254#endif
3255}
3256
3257
3258/* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY 1241 */
3259static int vmsvga3dCmdDXPredResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredResolveCopy const *pCmd, uint32_t cbCmd)
3260{
3261#ifdef VMSVGA3D_DX
3262ASMBreakpoint();
3263 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3264 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3265 return vmsvga3dDXPredResolveCopy(pThisCC, idDXContext);
3266#else
3267 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3268 return VERR_NOT_SUPPORTED;
3269#endif
3270}
3271
3272
3273/* SVGA_3D_CMD_DX_PRED_CONVERT_REGION 1242 */
3274static int vmsvga3dCmdDXPredConvertRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvertRegion const *pCmd, uint32_t cbCmd)
3275{
3276#ifdef VMSVGA3D_DX
3277ASMBreakpoint();
3278 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3279 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3280 return vmsvga3dDXPredConvertRegion(pThisCC, idDXContext);
3281#else
3282 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3283 return VERR_NOT_SUPPORTED;
3284#endif
3285}
3286
3287
3288/* SVGA_3D_CMD_DX_PRED_CONVERT 1243 */
3289static int vmsvga3dCmdDXPredConvert(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvert const *pCmd, uint32_t cbCmd)
3290{
3291#ifdef VMSVGA3D_DX
3292ASMBreakpoint();
3293 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3294 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3295 return vmsvga3dDXPredConvert(pThisCC, idDXContext);
3296#else
3297 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3298 return VERR_NOT_SUPPORTED;
3299#endif
3300}
3301
3302
3303/* SVGA_3D_CMD_WHOLE_SURFACE_COPY 1244 */
3304static int vmsvga3dCmdWholeSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWholeSurfaceCopy const *pCmd, uint32_t cbCmd)
3305{
3306#ifdef VMSVGA3D_DX
3307ASMBreakpoint();
3308 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3309 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3310 return vmsvga3dWholeSurfaceCopy(pThisCC, idDXContext);
3311#else
3312 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3313 return VERR_NOT_SUPPORTED;
3314#endif
3315}
3316
3317
3318/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW 1245 */
3319static int vmsvga3dCmdDXDefineUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineUAView const *pCmd, uint32_t cbCmd)
3320{
3321#ifdef VMSVGA3D_DX
3322ASMBreakpoint();
3323 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3324 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3325 return vmsvga3dDXDefineUAView(pThisCC, idDXContext);
3326#else
3327 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3328 return VERR_NOT_SUPPORTED;
3329#endif
3330}
3331
3332
3333/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW 1246 */
3334static int vmsvga3dCmdDXDestroyUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyUAView const *pCmd, uint32_t cbCmd)
3335{
3336#ifdef VMSVGA3D_DX
3337ASMBreakpoint();
3338 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3339 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3340 return vmsvga3dDXDestroyUAView(pThisCC, idDXContext);
3341#else
3342 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3343 return VERR_NOT_SUPPORTED;
3344#endif
3345}
3346
3347
3348/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT 1247 */
3349static int vmsvga3dCmdDXClearUAViewUint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewUint const *pCmd, uint32_t cbCmd)
3350{
3351#ifdef VMSVGA3D_DX
3352ASMBreakpoint();
3353 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3354 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3355 return vmsvga3dDXClearUAViewUint(pThisCC, idDXContext);
3356#else
3357 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3358 return VERR_NOT_SUPPORTED;
3359#endif
3360}
3361
3362
3363/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT 1248 */
3364static int vmsvga3dCmdDXClearUAViewFloat(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewFloat const *pCmd, uint32_t cbCmd)
3365{
3366#ifdef VMSVGA3D_DX
3367ASMBreakpoint();
3368 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3369 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3370 return vmsvga3dDXClearUAViewFloat(pThisCC, idDXContext);
3371#else
3372 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3373 return VERR_NOT_SUPPORTED;
3374#endif
3375}
3376
3377
3378/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT 1249 */
3379static int vmsvga3dCmdDXCopyStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCopyStructureCount const *pCmd, uint32_t cbCmd)
3380{
3381#ifdef VMSVGA3D_DX
3382ASMBreakpoint();
3383 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3384 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3385 return vmsvga3dDXCopyStructureCount(pThisCC, idDXContext);
3386#else
3387 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3388 return VERR_NOT_SUPPORTED;
3389#endif
3390}
3391
3392
3393/* SVGA_3D_CMD_DX_SET_UA_VIEWS 1250 */
3394static int vmsvga3dCmdDXSetUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetUAViews const *pCmd, uint32_t cbCmd)
3395{
3396#ifdef VMSVGA3D_DX
3397ASMBreakpoint();
3398 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3399 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3400 return vmsvga3dDXSetUAViews(pThisCC, idDXContext);
3401#else
3402 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3403 return VERR_NOT_SUPPORTED;
3404#endif
3405}
3406
3407
3408/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT 1251 */
3409static int vmsvga3dCmdDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd, uint32_t cbCmd)
3410{
3411#ifdef VMSVGA3D_DX
3412ASMBreakpoint();
3413 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3414 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3415 return vmsvga3dDXDrawIndexedInstancedIndirect(pThisCC, idDXContext);
3416#else
3417 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3418 return VERR_NOT_SUPPORTED;
3419#endif
3420}
3421
3422
3423/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT 1252 */
3424static int vmsvga3dCmdDXDrawInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstancedIndirect const *pCmd, uint32_t cbCmd)
3425{
3426#ifdef VMSVGA3D_DX
3427ASMBreakpoint();
3428 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3429 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3430 return vmsvga3dDXDrawInstancedIndirect(pThisCC, idDXContext);
3431#else
3432 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3433 return VERR_NOT_SUPPORTED;
3434#endif
3435}
3436
3437
3438/* SVGA_3D_CMD_DX_DISPATCH 1253 */
3439static int vmsvga3dCmdDXDispatch(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatch const *pCmd, uint32_t cbCmd)
3440{
3441#ifdef VMSVGA3D_DX
3442ASMBreakpoint();
3443 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3444 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3445 return vmsvga3dDXDispatch(pThisCC, idDXContext);
3446#else
3447 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3448 return VERR_NOT_SUPPORTED;
3449#endif
3450}
3451
3452
3453/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT 1254 */
3454static int vmsvga3dCmdDXDispatchIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatchIndirect const *pCmd, uint32_t cbCmd)
3455{
3456#ifdef VMSVGA3D_DX
3457ASMBreakpoint();
3458 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3459 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3460 return vmsvga3dDXDispatchIndirect(pThisCC, idDXContext);
3461#else
3462 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3463 return VERR_NOT_SUPPORTED;
3464#endif
3465}
3466
3467
3468/* SVGA_3D_CMD_WRITE_ZERO_SURFACE 1255 */
3469static int vmsvga3dCmdWriteZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWriteZeroSurface const *pCmd, uint32_t cbCmd)
3470{
3471#ifdef VMSVGA3D_DX
3472ASMBreakpoint();
3473 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3474 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3475 return vmsvga3dWriteZeroSurface(pThisCC, idDXContext);
3476#else
3477 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3478 return VERR_NOT_SUPPORTED;
3479#endif
3480}
3481
3482
3483/* SVGA_3D_CMD_HINT_ZERO_SURFACE 1256 */
3484static int vmsvga3dCmdHintZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdHintZeroSurface const *pCmd, uint32_t cbCmd)
3485{
3486#ifdef VMSVGA3D_DX
3487ASMBreakpoint();
3488 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3489 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3490 return vmsvga3dHintZeroSurface(pThisCC, idDXContext);
3491#else
3492 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3493 return VERR_NOT_SUPPORTED;
3494#endif
3495}
3496
3497
3498/* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER 1257 */
3499static int vmsvga3dCmdDXTransferToBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferToBuffer const *pCmd, uint32_t cbCmd)
3500{
3501#ifdef VMSVGA3D_DX
3502ASMBreakpoint();
3503 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3504 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3505 return vmsvga3dDXTransferToBuffer(pThisCC, idDXContext);
3506#else
3507 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3508 return VERR_NOT_SUPPORTED;
3509#endif
3510}
3511
3512
3513/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT 1258 */
3514static int vmsvga3dCmdDXSetStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStructureCount const *pCmd, uint32_t cbCmd)
3515{
3516#ifdef VMSVGA3D_DX
3517ASMBreakpoint();
3518 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3519 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3520 return vmsvga3dDXSetStructureCount(pThisCC, idDXContext);
3521#else
3522 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3523 return VERR_NOT_SUPPORTED;
3524#endif
3525}
3526
3527
3528/* SVGA_3D_CMD_LOGICOPS_BITBLT 1259 */
3529static int vmsvga3dCmdLogicOpsBitBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsBitBlt const *pCmd, uint32_t cbCmd)
3530{
3531#ifdef VMSVGA3D_DX
3532ASMBreakpoint();
3533 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3534 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3535 return vmsvga3dLogicOpsBitBlt(pThisCC, idDXContext);
3536#else
3537 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3538 return VERR_NOT_SUPPORTED;
3539#endif
3540}
3541
3542
3543/* SVGA_3D_CMD_LOGICOPS_TRANSBLT 1260 */
3544static int vmsvga3dCmdLogicOpsTransBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsTransBlt const *pCmd, uint32_t cbCmd)
3545{
3546#ifdef VMSVGA3D_DX
3547ASMBreakpoint();
3548 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3549 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3550 return vmsvga3dLogicOpsTransBlt(pThisCC, idDXContext);
3551#else
3552 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3553 return VERR_NOT_SUPPORTED;
3554#endif
3555}
3556
3557
3558/* SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1261 */
3559static int vmsvga3dCmdLogicOpsStretchBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsStretchBlt const *pCmd, uint32_t cbCmd)
3560{
3561#ifdef VMSVGA3D_DX
3562ASMBreakpoint();
3563 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3564 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3565 return vmsvga3dLogicOpsStretchBlt(pThisCC, idDXContext);
3566#else
3567 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3568 return VERR_NOT_SUPPORTED;
3569#endif
3570}
3571
3572
3573/* SVGA_3D_CMD_LOGICOPS_COLORFILL 1262 */
3574static int vmsvga3dCmdLogicOpsColorFill(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsColorFill const *pCmd, uint32_t cbCmd)
3575{
3576#ifdef VMSVGA3D_DX
3577ASMBreakpoint();
3578 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3579 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3580 return vmsvga3dLogicOpsColorFill(pThisCC, idDXContext);
3581#else
3582 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3583 return VERR_NOT_SUPPORTED;
3584#endif
3585}
3586
3587
3588/* SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1263 */
3589static int vmsvga3dCmdLogicOpsAlphaBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsAlphaBlend const *pCmd, uint32_t cbCmd)
3590{
3591#ifdef VMSVGA3D_DX
3592ASMBreakpoint();
3593 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3594 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3595 return vmsvga3dLogicOpsAlphaBlend(pThisCC, idDXContext);
3596#else
3597 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3598 return VERR_NOT_SUPPORTED;
3599#endif
3600}
3601
3602
3603/* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1264 */
3604static int vmsvga3dCmdLogicOpsClearTypeBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsClearTypeBlend const *pCmd, uint32_t cbCmd)
3605{
3606#ifdef VMSVGA3D_DX
3607ASMBreakpoint();
3608 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3609 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3610 return vmsvga3dLogicOpsClearTypeBlend(pThisCC, idDXContext);
3611#else
3612 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3613 return VERR_NOT_SUPPORTED;
3614#endif
3615}
3616
3617
3618/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 1267 */
3619static int vmsvga3dCmdDefineGBSurface_v4(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v4 const *pCmd, uint32_t cbCmd)
3620{
3621#ifdef VMSVGA3D_DX
3622ASMBreakpoint();
3623 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3624 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3625 return vmsvga3dDefineGBSurface_v4(pThisCC, idDXContext);
3626#else
3627 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3628 return VERR_NOT_SUPPORTED;
3629#endif
3630}
3631
3632
3633/* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS 1268 */
3634static int vmsvga3dCmdDXSetCSUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSUAViews const *pCmd, uint32_t cbCmd)
3635{
3636#ifdef VMSVGA3D_DX
3637ASMBreakpoint();
3638 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3639 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3640 return vmsvga3dDXSetCSUAViews(pThisCC, idDXContext);
3641#else
3642 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3643 return VERR_NOT_SUPPORTED;
3644#endif
3645}
3646
3647
3648/* SVGA_3D_CMD_DX_SET_MIN_LOD 1269 */
3649static int vmsvga3dCmdDXSetMinLOD(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetMinLOD const *pCmd, uint32_t cbCmd)
3650{
3651#ifdef VMSVGA3D_DX
3652ASMBreakpoint();
3653 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3654 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3655 return vmsvga3dDXSetMinLOD(pThisCC, idDXContext);
3656#else
3657 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3658 return VERR_NOT_SUPPORTED;
3659#endif
3660}
3661
3662
3663/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 1272 */
3664static int vmsvga3dCmdDXDefineDepthStencilView_v2(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd, uint32_t cbCmd)
3665{
3666#ifdef VMSVGA3D_DX
3667//ASMBreakpoint();
3668 RT_NOREF(cbCmd);
3669 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, pCmd);
3670#else
3671 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3672 return VERR_NOT_SUPPORTED;
3673#endif
3674}
3675
3676
3677/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB 1273 */
3678static int vmsvga3dCmdDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd, uint32_t cbCmd)
3679{
3680#ifdef VMSVGA3D_DX
3681ASMBreakpoint();
3682 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3683 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3684 return vmsvga3dDXDefineStreamOutputWithMob(pThisCC, idDXContext);
3685#else
3686 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3687 return VERR_NOT_SUPPORTED;
3688#endif
3689}
3690
3691
3692/* SVGA_3D_CMD_DX_SET_SHADER_IFACE 1274 */
3693static int vmsvga3dCmdDXSetShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderIface const *pCmd, uint32_t cbCmd)
3694{
3695#ifdef VMSVGA3D_DX
3696ASMBreakpoint();
3697 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3698 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3699 return vmsvga3dDXSetShaderIface(pThisCC, idDXContext);
3700#else
3701 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3702 return VERR_NOT_SUPPORTED;
3703#endif
3704}
3705
3706
3707/* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT 1275 */
3708static int vmsvga3dCmdDXBindStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindStreamOutput const *pCmd, uint32_t cbCmd)
3709{
3710#ifdef VMSVGA3D_DX
3711ASMBreakpoint();
3712 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3713 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3714 return vmsvga3dDXBindStreamOutput(pThisCC, idDXContext);
3715#else
3716 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3717 return VERR_NOT_SUPPORTED;
3718#endif
3719}
3720
3721
3722/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS 1276 */
3723static int vmsvga3dCmdSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdSurfaceStretchBltNonMSToMS const *pCmd, uint32_t cbCmd)
3724{
3725#ifdef VMSVGA3D_DX
3726ASMBreakpoint();
3727 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3728 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3729 return vmsvga3dSurfaceStretchBltNonMSToMS(pThisCC, idDXContext);
3730#else
3731 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3732 return VERR_NOT_SUPPORTED;
3733#endif
3734}
3735
3736
3737/* SVGA_3D_CMD_DX_BIND_SHADER_IFACE 1277 */
3738static int vmsvga3dCmdDXBindShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShaderIface const *pCmd, uint32_t cbCmd)
3739{
3740#ifdef VMSVGA3D_DX
3741ASMBreakpoint();
3742 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3743 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3744 return vmsvga3dDXBindShaderIface(pThisCC, idDXContext);
3745#else
3746 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3747 return VERR_NOT_SUPPORTED;
3748#endif
3749}
3750
3751
3752/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
3753 * Check that the 3D command has at least a_cbMin of payload bytes after the
3754 * header. Will break out of the switch if it doesn't.
3755 */
3756# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3757 if (1) { \
3758 AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
3759 RT_UNTRUSTED_VALIDATED_FENCE(); \
3760 } else do {} while (0)
3761
3762# define VMSVGA_3D_CMD_NOTIMPL() \
3763 if (1) { \
3764 AssertMsgFailed(("Not implemented %d %s\n", enmCmdId, vmsvgaR3FifoCmdToString(enmCmdId))); \
3765 } else do {} while (0)
3766
3767/** SVGA_3D_CMD_* handler.
3768 * This function parses the command and calls the corresponding command handler.
3769 *
3770 * @param pThis The shared VGA/VMSVGA state.
3771 * @param pThisCC The VGA/VMSVGA state for the current context.
3772 * @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
3773 * @param enmCmdId SVGA_3D_CMD_* command identifier.
3774 * @param cbCmd Size of the command in bytes.
3775 * @param pvCmd Pointer to the command.
3776 * @returns VBox status code if an error was detected parsing a command.
3777 */
3778int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, SVGAFifo3dCmdId enmCmdId, uint32_t cbCmd, void const *pvCmd)
3779{
3780 if (enmCmdId > SVGA_3D_CMD_MAX)
3781 {
3782 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
3783 ASSERT_GUEST_FAILED_RETURN(VERR_NOT_IMPLEMENTED);
3784 }
3785
3786 int rcParse = VINF_SUCCESS;
3787 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
3788
3789 switch (enmCmdId)
3790 {
3791 case SVGA_3D_CMD_SURFACE_DEFINE:
3792 {
3793 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)pvCmd;
3794 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3795 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefine);
3796
3797 SVGA3dCmdDefineSurface_v2 cmd;
3798 cmd.sid = pCmd->sid;
3799 cmd.surfaceFlags = pCmd->surfaceFlags;
3800 cmd.format = pCmd->format;
3801 memcpy(cmd.face, pCmd->face, sizeof(cmd.face));
3802 cmd.multisampleCount = 0;
3803 cmd.autogenFilter = SVGA3D_TEX_FILTER_NONE;
3804
3805 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3806 vmsvga3dCmdDefineSurface(pThisCC, &cmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
3807# ifdef DEBUG_GMR_ACCESS
3808 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
3809# endif
3810 break;
3811 }
3812
3813 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3814 {
3815 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)pvCmd;
3816 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3817 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefineV2);
3818
3819 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3820 vmsvga3dCmdDefineSurface(pThisCC, pCmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
3821# ifdef DEBUG_GMR_ACCESS
3822 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
3823# endif
3824 break;
3825 }
3826
3827 case SVGA_3D_CMD_SURFACE_DESTROY:
3828 {
3829 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)pvCmd;
3830 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3831 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDestroy);
3832
3833 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
3834 break;
3835 }
3836
3837 case SVGA_3D_CMD_SURFACE_COPY:
3838 {
3839 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)pvCmd;
3840 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3841 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceCopy);
3842
3843 uint32_t const cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3844 vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3845 break;
3846 }
3847
3848 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3849 {
3850 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)pvCmd;
3851 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3852 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceStretchBlt);
3853
3854 vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
3855 &pCmd->src, &pCmd->boxSrc, pCmd->mode);
3856 break;
3857 }
3858
3859 case SVGA_3D_CMD_SURFACE_DMA:
3860 {
3861 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)pvCmd;
3862 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3863 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDma);
3864
3865 uint64_t u64NanoTS = 0;
3866 if (LogRelIs3Enabled())
3867 u64NanoTS = RTTimeNanoTS();
3868 uint32_t const cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3869 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
3870 vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
3871 cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3872 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
3873 if (LogRelIs3Enabled())
3874 {
3875 if (cCopyBoxes)
3876 {
3877 SVGA3dCopyBox *pFirstBox = (SVGA3dCopyBox *)(pCmd + 1);
3878 LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
3879 (RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
3880 pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
3881 pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
3882 }
3883 }
3884 break;
3885 }
3886
3887 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3888 {
3889 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)pvCmd;
3890 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3891 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceScreen);
3892
3893 static uint64_t u64FrameStartNanoTS = 0;
3894 static uint64_t u64ElapsedPerSecNano = 0;
3895 static int cFrames = 0;
3896 uint64_t u64NanoTS = 0;
3897 if (LogRelIs3Enabled())
3898 u64NanoTS = RTTimeNanoTS();
3899 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3900 STAM_REL_PROFILE_START(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
3901 vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
3902 pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3903 STAM_REL_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
3904 if (LogRelIs3Enabled())
3905 {
3906 uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
3907 u64ElapsedPerSecNano += u64ElapsedNano;
3908
3909 SVGASignedRect *pFirstRect = cRects ? (SVGASignedRect *)(pCmd + 1) : &pCmd->destRect;
3910 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
3911 (u64ElapsedNano) / 1000ULL, cRects,
3912 pFirstRect->left, pFirstRect->top,
3913 pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
3914
3915 ++cFrames;
3916 if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
3917 {
3918 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
3919 cFrames, u64ElapsedPerSecNano / 1000ULL));
3920 u64FrameStartNanoTS = u64NanoTS;
3921 cFrames = 0;
3922 u64ElapsedPerSecNano = 0;
3923 }
3924 }
3925 break;
3926 }
3927
3928 case SVGA_3D_CMD_CONTEXT_DEFINE:
3929 {
3930 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)pvCmd;
3931 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3932 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDefine);
3933
3934 vmsvga3dContextDefine(pThisCC, pCmd->cid);
3935 break;
3936 }
3937
3938 case SVGA_3D_CMD_CONTEXT_DESTROY:
3939 {
3940 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)pvCmd;
3941 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3942 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDestroy);
3943
3944 vmsvga3dContextDestroy(pThisCC, pCmd->cid);
3945 break;
3946 }
3947
3948 case SVGA_3D_CMD_SETTRANSFORM:
3949 {
3950 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)pvCmd;
3951 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3952 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTransform);
3953
3954 vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
3955 break;
3956 }
3957
3958 case SVGA_3D_CMD_SETZRANGE:
3959 {
3960 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)pvCmd;
3961 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3962 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetZRange);
3963
3964 vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
3965 break;
3966 }
3967
3968 case SVGA_3D_CMD_SETRENDERSTATE:
3969 {
3970 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)pvCmd;
3971 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3972 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderState);
3973
3974 uint32_t const cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3975 vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3976 break;
3977 }
3978
3979 case SVGA_3D_CMD_SETRENDERTARGET:
3980 {
3981 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)pvCmd;
3982 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3983 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderTarget);
3984
3985 vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
3986 break;
3987 }
3988
3989 case SVGA_3D_CMD_SETTEXTURESTATE:
3990 {
3991 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)pvCmd;
3992 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3993 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTextureState);
3994
3995 uint32_t const cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3996 vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3997 break;
3998 }
3999
4000 case SVGA_3D_CMD_SETMATERIAL:
4001 {
4002 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)pvCmd;
4003 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4004 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetMaterial);
4005
4006 vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4007 break;
4008 }
4009
4010 case SVGA_3D_CMD_SETLIGHTDATA:
4011 {
4012 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)pvCmd;
4013 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4014 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightData);
4015
4016 vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4017 break;
4018 }
4019
4020 case SVGA_3D_CMD_SETLIGHTENABLED:
4021 {
4022 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)pvCmd;
4023 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4024 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightEnable);
4025
4026 vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4027 break;
4028 }
4029
4030 case SVGA_3D_CMD_SETVIEWPORT:
4031 {
4032 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)pvCmd;
4033 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4034 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetViewPort);
4035
4036 vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4037 break;
4038 }
4039
4040 case SVGA_3D_CMD_SETCLIPPLANE:
4041 {
4042 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)pvCmd;
4043 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4044 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetClipPlane);
4045
4046 vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4047 break;
4048 }
4049
4050 case SVGA_3D_CMD_CLEAR:
4051 {
4052 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)pvCmd;
4053 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4054 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dClear);
4055
4056 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4057 vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4058 break;
4059 }
4060
4061 case SVGA_3D_CMD_PRESENT:
4062 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4063 {
4064 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)pvCmd;
4065 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4066 if (enmCmdId == SVGA_3D_CMD_PRESENT)
4067 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent);
4068 else
4069 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresentReadBack);
4070
4071 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4072 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4073 vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4074 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4075 break;
4076 }
4077
4078 case SVGA_3D_CMD_SHADER_DEFINE:
4079 {
4080 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)pvCmd;
4081 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4082 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDefine);
4083
4084 uint32_t const cbData = (cbCmd - sizeof(*pCmd));
4085 vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4086 break;
4087 }
4088
4089 case SVGA_3D_CMD_SHADER_DESTROY:
4090 {
4091 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)pvCmd;
4092 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4093 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDestroy);
4094
4095 vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4096 break;
4097 }
4098
4099 case SVGA_3D_CMD_SET_SHADER:
4100 {
4101 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)pvCmd;
4102 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4103 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShader);
4104
4105 vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4106 break;
4107 }
4108
4109 case SVGA_3D_CMD_SET_SHADER_CONST:
4110 {
4111 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)pvCmd;
4112 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4113 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShaderConst);
4114
4115 uint32_t const cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4116 vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4117 break;
4118 }
4119
4120 case SVGA_3D_CMD_DRAW_PRIMITIVES:
4121 {
4122 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)pvCmd;
4123 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4124 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDrawPrimitives);
4125
4126 ASSERT_GUEST_STMT_BREAK(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES, rcParse = VERR_INVALID_PARAMETER);
4127 ASSERT_GUEST_STMT_BREAK(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS, rcParse = VERR_INVALID_PARAMETER);
4128 uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4129 + pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4130 ASSERT_GUEST_STMT_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd), rcParse = VERR_INVALID_PARAMETER);
4131
4132 uint32_t const cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4133 ASSERT_GUEST_STMT_BREAK(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls, rcParse = VERR_INVALID_PARAMETER);
4134 RT_UNTRUSTED_VALIDATED_FENCE();
4135
4136 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
4137 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *)&pVertexDecl[pCmd->numVertexDecls];
4138 SVGA3dVertexDivisor *pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor *)&pNumRange[pCmd->numRanges] : NULL;
4139
4140 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4141 vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4142 pNumRange, cVertexDivisor, pVertexDivisor);
4143 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4144 break;
4145 }
4146
4147 case SVGA_3D_CMD_SETSCISSORRECT:
4148 {
4149 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)pvCmd;
4150 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4151 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetScissorRect);
4152
4153 vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4154 break;
4155 }
4156
4157 case SVGA_3D_CMD_BEGIN_QUERY:
4158 {
4159 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)pvCmd;
4160 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4161 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dBeginQuery);
4162
4163 vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4164 break;
4165 }
4166
4167 case SVGA_3D_CMD_END_QUERY:
4168 {
4169 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)pvCmd;
4170 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4171 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dEndQuery);
4172
4173 vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4174 break;
4175 }
4176
4177 case SVGA_3D_CMD_WAIT_FOR_QUERY:
4178 {
4179 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)pvCmd;
4180 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4181 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dWaitForQuery);
4182
4183 vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4184 break;
4185 }
4186
4187 case SVGA_3D_CMD_GENERATE_MIPMAPS:
4188 {
4189 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)pvCmd;
4190 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4191 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dGenerateMipmaps);
4192
4193 vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4194 break;
4195 }
4196
4197 case SVGA_3D_CMD_ACTIVATE_SURFACE:
4198 /* context id + surface id? */
4199 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dActivateSurface);
4200 break;
4201
4202 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4203 /* context id + surface id? */
4204 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDeactivateSurface);
4205 break;
4206
4207 /*
4208 *
4209 * VPGU10: SVGA_CAP_GBOBJECTS+ commands.
4210 *
4211 */
4212 case SVGA_3D_CMD_SCREEN_DMA:
4213 {
4214 SVGA3dCmdScreenDMA *pCmd = (SVGA3dCmdScreenDMA *)pvCmd;
4215 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4216 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4217 break;
4218 }
4219
4220 case SVGA_3D_CMD_DEAD1:
4221 case SVGA_3D_CMD_DEAD2:
4222 case SVGA_3D_CMD_DEAD12: /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
4223 case SVGA_3D_CMD_DEAD13: /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
4224 case SVGA_3D_CMD_DEAD14: /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
4225 case SVGA_3D_CMD_DEAD15: /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
4226 case SVGA_3D_CMD_DEAD16: /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
4227 case SVGA_3D_CMD_DEAD17: /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
4228 {
4229 VMSVGA_3D_CMD_NOTIMPL();
4230 break;
4231 }
4232
4233 case SVGA_3D_CMD_SET_OTABLE_BASE:
4234 {
4235 SVGA3dCmdSetOTableBase *pCmd = (SVGA3dCmdSetOTableBase *)pvCmd;
4236 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4237 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4238 break;
4239 }
4240
4241 case SVGA_3D_CMD_READBACK_OTABLE:
4242 {
4243 SVGA3dCmdReadbackOTable *pCmd = (SVGA3dCmdReadbackOTable *)pvCmd;
4244 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4245 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4246 break;
4247 }
4248
4249 case SVGA_3D_CMD_DEFINE_GB_MOB:
4250 {
4251 SVGA3dCmdDefineGBMob *pCmd = (SVGA3dCmdDefineGBMob *)pvCmd;
4252 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4253 vmsvga3dCmdDefineGBMob(pThisCC, pCmd);
4254 break;
4255 }
4256
4257 case SVGA_3D_CMD_DESTROY_GB_MOB:
4258 {
4259 SVGA3dCmdDestroyGBMob *pCmd = (SVGA3dCmdDestroyGBMob *)pvCmd;
4260 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4261 vmsvga3dCmdDestroyGBMob(pThisCC, pCmd);
4262 break;
4263 }
4264
4265 case SVGA_3D_CMD_DEAD3:
4266 {
4267 VMSVGA_3D_CMD_NOTIMPL();
4268 break;
4269 }
4270
4271 case SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING:
4272 {
4273 SVGA3dCmdUpdateGBMobMapping *pCmd = (SVGA3dCmdUpdateGBMobMapping *)pvCmd;
4274 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4275 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4276 break;
4277 }
4278
4279 case SVGA_3D_CMD_DEFINE_GB_SURFACE:
4280 {
4281 SVGA3dCmdDefineGBSurface *pCmd = (SVGA3dCmdDefineGBSurface *)pvCmd;
4282 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4283 vmsvga3dCmdDefineGBSurface(pThisCC, pCmd);
4284 break;
4285 }
4286
4287 case SVGA_3D_CMD_DESTROY_GB_SURFACE:
4288 {
4289 SVGA3dCmdDestroyGBSurface *pCmd = (SVGA3dCmdDestroyGBSurface *)pvCmd;
4290 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4291 vmsvga3dCmdDestroyGBSurface(pThisCC, pCmd);
4292 break;
4293 }
4294
4295 case SVGA_3D_CMD_BIND_GB_SURFACE:
4296 {
4297 SVGA3dCmdBindGBSurface *pCmd = (SVGA3dCmdBindGBSurface *)pvCmd;
4298 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4299 vmsvga3dCmdBindGBSurface(pThisCC, pCmd);
4300 break;
4301 }
4302
4303 case SVGA_3D_CMD_COND_BIND_GB_SURFACE:
4304 {
4305 SVGA3dCmdCondBindGBSurface *pCmd = (SVGA3dCmdCondBindGBSurface *)pvCmd;
4306 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4307 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4308 break;
4309 }
4310
4311 case SVGA_3D_CMD_UPDATE_GB_IMAGE:
4312 {
4313 SVGA3dCmdUpdateGBImage *pCmd = (SVGA3dCmdUpdateGBImage *)pvCmd;
4314 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4315 vmsvga3dCmdUpdateGBImage(pThisCC, idDXContext, pCmd);
4316 break;
4317 }
4318
4319 case SVGA_3D_CMD_UPDATE_GB_SURFACE:
4320 {
4321 SVGA3dCmdUpdateGBSurface *pCmd = (SVGA3dCmdUpdateGBSurface *)pvCmd;
4322 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4323 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4324 break;
4325 }
4326
4327 case SVGA_3D_CMD_READBACK_GB_IMAGE:
4328 {
4329 SVGA3dCmdReadbackGBImage *pCmd = (SVGA3dCmdReadbackGBImage *)pvCmd;
4330 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4331 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4332 break;
4333 }
4334
4335 case SVGA_3D_CMD_READBACK_GB_SURFACE:
4336 {
4337 SVGA3dCmdReadbackGBSurface *pCmd = (SVGA3dCmdReadbackGBSurface *)pvCmd;
4338 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4339 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4340 break;
4341 }
4342
4343 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE:
4344 {
4345 SVGA3dCmdInvalidateGBImage *pCmd = (SVGA3dCmdInvalidateGBImage *)pvCmd;
4346 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4347 vmsvga3dCmdInvalidateGBImage(pThisCC, pCmd);
4348 break;
4349 }
4350
4351 case SVGA_3D_CMD_INVALIDATE_GB_SURFACE:
4352 {
4353 SVGA3dCmdInvalidateGBSurface *pCmd = (SVGA3dCmdInvalidateGBSurface *)pvCmd;
4354 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4355 vmsvga3dCmdInvalidateGBSurface(pThisCC, pCmd);
4356 break;
4357 }
4358
4359 case SVGA_3D_CMD_DEFINE_GB_CONTEXT:
4360 {
4361 SVGA3dCmdDefineGBContext *pCmd = (SVGA3dCmdDefineGBContext *)pvCmd;
4362 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4363 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4364 break;
4365 }
4366
4367 case SVGA_3D_CMD_DESTROY_GB_CONTEXT:
4368 {
4369 SVGA3dCmdDestroyGBContext *pCmd = (SVGA3dCmdDestroyGBContext *)pvCmd;
4370 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4371 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4372 break;
4373 }
4374
4375 case SVGA_3D_CMD_BIND_GB_CONTEXT:
4376 {
4377 SVGA3dCmdBindGBContext *pCmd = (SVGA3dCmdBindGBContext *)pvCmd;
4378 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4379 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4380 break;
4381 }
4382
4383 case SVGA_3D_CMD_READBACK_GB_CONTEXT:
4384 {
4385 SVGA3dCmdReadbackGBContext *pCmd = (SVGA3dCmdReadbackGBContext *)pvCmd;
4386 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4387 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4388 break;
4389 }
4390
4391 case SVGA_3D_CMD_INVALIDATE_GB_CONTEXT:
4392 {
4393 SVGA3dCmdInvalidateGBContext *pCmd = (SVGA3dCmdInvalidateGBContext *)pvCmd;
4394 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4395 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4396 break;
4397 }
4398
4399 case SVGA_3D_CMD_DEFINE_GB_SHADER:
4400 {
4401 SVGA3dCmdDefineGBShader *pCmd = (SVGA3dCmdDefineGBShader *)pvCmd;
4402 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4403 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4404 break;
4405 }
4406
4407 case SVGA_3D_CMD_DESTROY_GB_SHADER:
4408 {
4409 SVGA3dCmdDestroyGBShader *pCmd = (SVGA3dCmdDestroyGBShader *)pvCmd;
4410 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4411 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4412 break;
4413 }
4414
4415 case SVGA_3D_CMD_BIND_GB_SHADER:
4416 {
4417 SVGA3dCmdBindGBShader *pCmd = (SVGA3dCmdBindGBShader *)pvCmd;
4418 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4419 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4420 break;
4421 }
4422
4423 case SVGA_3D_CMD_SET_OTABLE_BASE64:
4424 {
4425 SVGA3dCmdSetOTableBase64 *pCmd = (SVGA3dCmdSetOTableBase64 *)pvCmd;
4426 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4427 vmsvga3dCmdSetOTableBase64(pThisCC, pCmd);
4428 break;
4429 }
4430
4431 case SVGA_3D_CMD_BEGIN_GB_QUERY:
4432 {
4433 SVGA3dCmdBeginGBQuery *pCmd = (SVGA3dCmdBeginGBQuery *)pvCmd;
4434 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4435 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4436 break;
4437 }
4438
4439 case SVGA_3D_CMD_END_GB_QUERY:
4440 {
4441 SVGA3dCmdEndGBQuery *pCmd = (SVGA3dCmdEndGBQuery *)pvCmd;
4442 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4443 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4444 break;
4445 }
4446
4447 case SVGA_3D_CMD_WAIT_FOR_GB_QUERY:
4448 {
4449 SVGA3dCmdWaitForGBQuery *pCmd = (SVGA3dCmdWaitForGBQuery *)pvCmd;
4450 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4451 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4452 break;
4453 }
4454
4455 case SVGA_3D_CMD_NOP:
4456 {
4457 /* Apparently there is nothing to do. */
4458 break;
4459 }
4460
4461 case SVGA_3D_CMD_ENABLE_GART:
4462 {
4463 SVGA3dCmdEnableGart *pCmd = (SVGA3dCmdEnableGart *)pvCmd;
4464 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4465 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4466 break;
4467 }
4468
4469 case SVGA_3D_CMD_DISABLE_GART:
4470 {
4471 /* No corresponding SVGA3dCmd structure. */
4472 VMSVGA_3D_CMD_NOTIMPL();
4473 break;
4474 }
4475
4476 case SVGA_3D_CMD_MAP_MOB_INTO_GART:
4477 {
4478 SVGA3dCmdMapMobIntoGart *pCmd = (SVGA3dCmdMapMobIntoGart *)pvCmd;
4479 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4480 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4481 break;
4482 }
4483
4484 case SVGA_3D_CMD_UNMAP_GART_RANGE:
4485 {
4486 SVGA3dCmdUnmapGartRange *pCmd = (SVGA3dCmdUnmapGartRange *)pvCmd;
4487 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4488 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4489 break;
4490 }
4491
4492 case SVGA_3D_CMD_DEFINE_GB_SCREENTARGET:
4493 {
4494 SVGA3dCmdDefineGBScreenTarget *pCmd = (SVGA3dCmdDefineGBScreenTarget *)pvCmd;
4495 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4496 vmsvga3dCmdDefineGBScreenTarget(pThis, pThisCC, pCmd);
4497 break;
4498 }
4499
4500 case SVGA_3D_CMD_DESTROY_GB_SCREENTARGET:
4501 {
4502 SVGA3dCmdDestroyGBScreenTarget *pCmd = (SVGA3dCmdDestroyGBScreenTarget *)pvCmd;
4503 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4504 vmsvga3dCmdDestroyGBScreenTarget(pThis, pThisCC, pCmd);
4505 break;
4506 }
4507
4508 case SVGA_3D_CMD_BIND_GB_SCREENTARGET:
4509 {
4510 SVGA3dCmdBindGBScreenTarget *pCmd = (SVGA3dCmdBindGBScreenTarget *)pvCmd;
4511 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4512 vmsvga3dCmdBindGBScreenTarget(pThisCC, pCmd);
4513 break;
4514 }
4515
4516 case SVGA_3D_CMD_UPDATE_GB_SCREENTARGET:
4517 {
4518 SVGA3dCmdUpdateGBScreenTarget *pCmd = (SVGA3dCmdUpdateGBScreenTarget *)pvCmd;
4519 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4520 vmsvga3dCmdUpdateGBScreenTarget(pThisCC, pCmd);
4521 break;
4522 }
4523
4524 case SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL:
4525 {
4526 SVGA3dCmdReadbackGBImagePartial *pCmd = (SVGA3dCmdReadbackGBImagePartial *)pvCmd;
4527 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4528 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4529 break;
4530 }
4531
4532 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL:
4533 {
4534 SVGA3dCmdInvalidateGBImagePartial *pCmd = (SVGA3dCmdInvalidateGBImagePartial *)pvCmd;
4535 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4536 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4537 break;
4538 }
4539
4540 case SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE:
4541 {
4542 SVGA3dCmdSetGBShaderConstInline *pCmd = (SVGA3dCmdSetGBShaderConstInline *)pvCmd;
4543 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4544 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4545 break;
4546 }
4547
4548 case SVGA_3D_CMD_GB_SCREEN_DMA:
4549 {
4550 SVGA3dCmdGBScreenDMA *pCmd = (SVGA3dCmdGBScreenDMA *)pvCmd;
4551 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4552 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4553 break;
4554 }
4555
4556 case SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH:
4557 {
4558 SVGA3dCmdBindGBSurfaceWithPitch *pCmd = (SVGA3dCmdBindGBSurfaceWithPitch *)pvCmd;
4559 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4560 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4561 break;
4562 }
4563
4564 case SVGA_3D_CMD_GB_MOB_FENCE:
4565 {
4566 SVGA3dCmdGBMobFence *pCmd = (SVGA3dCmdGBMobFence *)pvCmd;
4567 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4568 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4569 break;
4570 }
4571
4572 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V2:
4573 {
4574 SVGA3dCmdDefineGBSurface_v2 *pCmd = (SVGA3dCmdDefineGBSurface_v2 *)pvCmd;
4575 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4576 vmsvga3dCmdDefineGBSurface_v2(pThisCC, pCmd);
4577 break;
4578 }
4579
4580 case SVGA_3D_CMD_DEFINE_GB_MOB64:
4581 {
4582 SVGA3dCmdDefineGBMob64 *pCmd = (SVGA3dCmdDefineGBMob64 *)pvCmd;
4583 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4584 vmsvga3dCmdDefineGBMob64(pThisCC, pCmd);
4585 break;
4586 }
4587
4588 case SVGA_3D_CMD_REDEFINE_GB_MOB64:
4589 {
4590 SVGA3dCmdRedefineGBMob64 *pCmd = (SVGA3dCmdRedefineGBMob64 *)pvCmd;
4591 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4592 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4593 break;
4594 }
4595
4596 case SVGA_3D_CMD_NOP_ERROR:
4597 {
4598 /* Apparently there is nothing to do. */
4599 break;
4600 }
4601
4602 case SVGA_3D_CMD_SET_VERTEX_STREAMS:
4603 {
4604 SVGA3dCmdSetVertexStreams *pCmd = (SVGA3dCmdSetVertexStreams *)pvCmd;
4605 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4606 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4607 break;
4608 }
4609
4610 case SVGA_3D_CMD_SET_VERTEX_DECLS:
4611 {
4612 SVGA3dCmdSetVertexDecls *pCmd = (SVGA3dCmdSetVertexDecls *)pvCmd;
4613 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4614 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4615 break;
4616 }
4617
4618 case SVGA_3D_CMD_SET_VERTEX_DIVISORS:
4619 {
4620 SVGA3dCmdSetVertexDivisors *pCmd = (SVGA3dCmdSetVertexDivisors *)pvCmd;
4621 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4622 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4623 break;
4624 }
4625
4626 case SVGA_3D_CMD_DRAW:
4627 {
4628 /* No corresponding SVGA3dCmd structure. */
4629 VMSVGA_3D_CMD_NOTIMPL();
4630 break;
4631 }
4632
4633 case SVGA_3D_CMD_DRAW_INDEXED:
4634 {
4635 /* No corresponding SVGA3dCmd structure. */
4636 VMSVGA_3D_CMD_NOTIMPL();
4637 break;
4638 }
4639
4640 case SVGA_3D_CMD_DX_DEFINE_CONTEXT:
4641 {
4642 SVGA3dCmdDXDefineContext *pCmd = (SVGA3dCmdDXDefineContext *)pvCmd;
4643 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4644 rcParse = vmsvga3dCmdDXDefineContext(pThisCC, pCmd, cbCmd);
4645 break;
4646 }
4647
4648 case SVGA_3D_CMD_DX_DESTROY_CONTEXT:
4649 {
4650 SVGA3dCmdDXDestroyContext *pCmd = (SVGA3dCmdDXDestroyContext *)pvCmd;
4651 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4652 rcParse = vmsvga3dCmdDXDestroyContext(pThisCC, pCmd, cbCmd);
4653 break;
4654 }
4655
4656 case SVGA_3D_CMD_DX_BIND_CONTEXT:
4657 {
4658 SVGA3dCmdDXBindContext *pCmd = (SVGA3dCmdDXBindContext *)pvCmd;
4659 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4660 rcParse = vmsvga3dCmdDXBindContext(pThisCC, pCmd, cbCmd);
4661 break;
4662 }
4663
4664 case SVGA_3D_CMD_DX_READBACK_CONTEXT:
4665 {
4666 SVGA3dCmdDXReadbackContext *pCmd = (SVGA3dCmdDXReadbackContext *)pvCmd;
4667 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4668 rcParse = vmsvga3dCmdDXReadbackContext(pThisCC, idDXContext, pCmd, cbCmd);
4669 break;
4670 }
4671
4672 case SVGA_3D_CMD_DX_INVALIDATE_CONTEXT:
4673 {
4674 SVGA3dCmdDXInvalidateContext *pCmd = (SVGA3dCmdDXInvalidateContext *)pvCmd;
4675 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4676 rcParse = vmsvga3dCmdDXInvalidateContext(pThisCC, idDXContext, pCmd, cbCmd);
4677 break;
4678 }
4679
4680 case SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER:
4681 {
4682 SVGA3dCmdDXSetSingleConstantBuffer *pCmd = (SVGA3dCmdDXSetSingleConstantBuffer *)pvCmd;
4683 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4684 rcParse = vmsvga3dCmdDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd, cbCmd);
4685 break;
4686 }
4687
4688 case SVGA_3D_CMD_DX_SET_SHADER_RESOURCES:
4689 {
4690 SVGA3dCmdDXSetShaderResources *pCmd = (SVGA3dCmdDXSetShaderResources *)pvCmd;
4691 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4692 rcParse = vmsvga3dCmdDXSetShaderResources(pThisCC, idDXContext, pCmd, cbCmd);
4693 break;
4694 }
4695
4696 case SVGA_3D_CMD_DX_SET_SHADER:
4697 {
4698 SVGA3dCmdDXSetShader *pCmd = (SVGA3dCmdDXSetShader *)pvCmd;
4699 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4700 rcParse = vmsvga3dCmdDXSetShader(pThisCC, idDXContext, pCmd, cbCmd);
4701 break;
4702 }
4703
4704 case SVGA_3D_CMD_DX_SET_SAMPLERS:
4705 {
4706 SVGA3dCmdDXSetSamplers *pCmd = (SVGA3dCmdDXSetSamplers *)pvCmd;
4707 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4708 rcParse = vmsvga3dCmdDXSetSamplers(pThisCC, idDXContext, pCmd, cbCmd);
4709 break;
4710 }
4711
4712 case SVGA_3D_CMD_DX_DRAW:
4713 {
4714 SVGA3dCmdDXDraw *pCmd = (SVGA3dCmdDXDraw *)pvCmd;
4715 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4716 rcParse = vmsvga3dCmdDXDraw(pThisCC, idDXContext, pCmd, cbCmd);
4717 break;
4718 }
4719
4720 case SVGA_3D_CMD_DX_DRAW_INDEXED:
4721 {
4722 SVGA3dCmdDXDrawIndexed *pCmd = (SVGA3dCmdDXDrawIndexed *)pvCmd;
4723 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4724 rcParse = vmsvga3dCmdDXDrawIndexed(pThisCC, idDXContext, pCmd, cbCmd);
4725 break;
4726 }
4727
4728 case SVGA_3D_CMD_DX_DRAW_INSTANCED:
4729 {
4730 SVGA3dCmdDXDrawInstanced *pCmd = (SVGA3dCmdDXDrawInstanced *)pvCmd;
4731 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4732 rcParse = vmsvga3dCmdDXDrawInstanced(pThisCC, idDXContext, pCmd, cbCmd);
4733 break;
4734 }
4735
4736 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED:
4737 {
4738 SVGA3dCmdDXDrawIndexedInstanced *pCmd = (SVGA3dCmdDXDrawIndexedInstanced *)pvCmd;
4739 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4740 rcParse = vmsvga3dCmdDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd, cbCmd);
4741 break;
4742 }
4743
4744 case SVGA_3D_CMD_DX_DRAW_AUTO:
4745 {
4746 SVGA3dCmdDXDrawAuto *pCmd = (SVGA3dCmdDXDrawAuto *)pvCmd;
4747 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4748 rcParse = vmsvga3dCmdDXDrawAuto(pThisCC, idDXContext, pCmd, cbCmd);
4749 break;
4750 }
4751
4752 case SVGA_3D_CMD_DX_SET_INPUT_LAYOUT:
4753 {
4754 SVGA3dCmdDXSetInputLayout *pCmd = (SVGA3dCmdDXSetInputLayout *)pvCmd;
4755 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4756 rcParse = vmsvga3dCmdDXSetInputLayout(pThisCC, idDXContext, pCmd, cbCmd);
4757 break;
4758 }
4759
4760 case SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS:
4761 {
4762 SVGA3dCmdDXSetVertexBuffers *pCmd = (SVGA3dCmdDXSetVertexBuffers *)pvCmd;
4763 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4764 rcParse = vmsvga3dCmdDXSetVertexBuffers(pThisCC, idDXContext, pCmd, cbCmd);
4765 break;
4766 }
4767
4768 case SVGA_3D_CMD_DX_SET_INDEX_BUFFER:
4769 {
4770 SVGA3dCmdDXSetIndexBuffer *pCmd = (SVGA3dCmdDXSetIndexBuffer *)pvCmd;
4771 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4772 rcParse = vmsvga3dCmdDXSetIndexBuffer(pThisCC, idDXContext, pCmd, cbCmd);
4773 break;
4774 }
4775
4776 case SVGA_3D_CMD_DX_SET_TOPOLOGY:
4777 {
4778 SVGA3dCmdDXSetTopology *pCmd = (SVGA3dCmdDXSetTopology *)pvCmd;
4779 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4780 rcParse = vmsvga3dCmdDXSetTopology(pThisCC, idDXContext, pCmd, cbCmd);
4781 break;
4782 }
4783
4784 case SVGA_3D_CMD_DX_SET_RENDERTARGETS:
4785 {
4786 SVGA3dCmdDXSetRenderTargets *pCmd = (SVGA3dCmdDXSetRenderTargets *)pvCmd;
4787 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4788 rcParse = vmsvga3dCmdDXSetRenderTargets(pThisCC, idDXContext, pCmd, cbCmd);
4789 break;
4790 }
4791
4792 case SVGA_3D_CMD_DX_SET_BLEND_STATE:
4793 {
4794 SVGA3dCmdDXSetBlendState *pCmd = (SVGA3dCmdDXSetBlendState *)pvCmd;
4795 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4796 rcParse = vmsvga3dCmdDXSetBlendState(pThisCC, idDXContext, pCmd, cbCmd);
4797 break;
4798 }
4799
4800 case SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE:
4801 {
4802 SVGA3dCmdDXSetDepthStencilState *pCmd = (SVGA3dCmdDXSetDepthStencilState *)pvCmd;
4803 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4804 rcParse = vmsvga3dCmdDXSetDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
4805 break;
4806 }
4807
4808 case SVGA_3D_CMD_DX_SET_RASTERIZER_STATE:
4809 {
4810 SVGA3dCmdDXSetRasterizerState *pCmd = (SVGA3dCmdDXSetRasterizerState *)pvCmd;
4811 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4812 rcParse = vmsvga3dCmdDXSetRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
4813 break;
4814 }
4815
4816 case SVGA_3D_CMD_DX_DEFINE_QUERY:
4817 {
4818 SVGA3dCmdDXDefineQuery *pCmd = (SVGA3dCmdDXDefineQuery *)pvCmd;
4819 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4820 rcParse = vmsvga3dCmdDXDefineQuery(pThisCC, idDXContext, pCmd, cbCmd);
4821 break;
4822 }
4823
4824 case SVGA_3D_CMD_DX_DESTROY_QUERY:
4825 {
4826 SVGA3dCmdDXDestroyQuery *pCmd = (SVGA3dCmdDXDestroyQuery *)pvCmd;
4827 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4828 rcParse = vmsvga3dCmdDXDestroyQuery(pThisCC, idDXContext, pCmd, cbCmd);
4829 break;
4830 }
4831
4832 case SVGA_3D_CMD_DX_BIND_QUERY:
4833 {
4834 SVGA3dCmdDXBindQuery *pCmd = (SVGA3dCmdDXBindQuery *)pvCmd;
4835 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4836 rcParse = vmsvga3dCmdDXBindQuery(pThisCC, idDXContext, pCmd, cbCmd);
4837 break;
4838 }
4839
4840 case SVGA_3D_CMD_DX_SET_QUERY_OFFSET:
4841 {
4842 SVGA3dCmdDXSetQueryOffset *pCmd = (SVGA3dCmdDXSetQueryOffset *)pvCmd;
4843 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4844 rcParse = vmsvga3dCmdDXSetQueryOffset(pThisCC, idDXContext, pCmd, cbCmd);
4845 break;
4846 }
4847
4848 case SVGA_3D_CMD_DX_BEGIN_QUERY:
4849 {
4850 SVGA3dCmdDXBeginQuery *pCmd = (SVGA3dCmdDXBeginQuery *)pvCmd;
4851 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4852 rcParse = vmsvga3dCmdDXBeginQuery(pThisCC, idDXContext, pCmd, cbCmd);
4853 break;
4854 }
4855
4856 case SVGA_3D_CMD_DX_END_QUERY:
4857 {
4858 SVGA3dCmdDXEndQuery *pCmd = (SVGA3dCmdDXEndQuery *)pvCmd;
4859 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4860 rcParse = vmsvga3dCmdDXEndQuery(pThisCC, idDXContext, pCmd, cbCmd);
4861 break;
4862 }
4863
4864 case SVGA_3D_CMD_DX_READBACK_QUERY:
4865 {
4866 SVGA3dCmdDXReadbackQuery *pCmd = (SVGA3dCmdDXReadbackQuery *)pvCmd;
4867 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4868 rcParse = vmsvga3dCmdDXReadbackQuery(pThisCC, idDXContext, pCmd, cbCmd);
4869 break;
4870 }
4871
4872 case SVGA_3D_CMD_DX_SET_PREDICATION:
4873 {
4874 SVGA3dCmdDXSetPredication *pCmd = (SVGA3dCmdDXSetPredication *)pvCmd;
4875 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4876 rcParse = vmsvga3dCmdDXSetPredication(pThisCC, idDXContext, pCmd, cbCmd);
4877 break;
4878 }
4879
4880 case SVGA_3D_CMD_DX_SET_SOTARGETS:
4881 {
4882 SVGA3dCmdDXSetSOTargets *pCmd = (SVGA3dCmdDXSetSOTargets *)pvCmd;
4883 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4884 rcParse = vmsvga3dCmdDXSetSOTargets(pThisCC, idDXContext, pCmd, cbCmd);
4885 break;
4886 }
4887
4888 case SVGA_3D_CMD_DX_SET_VIEWPORTS:
4889 {
4890 SVGA3dCmdDXSetViewports *pCmd = (SVGA3dCmdDXSetViewports *)pvCmd;
4891 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4892 rcParse = vmsvga3dCmdDXSetViewports(pThisCC, idDXContext, pCmd, cbCmd);
4893 break;
4894 }
4895
4896 case SVGA_3D_CMD_DX_SET_SCISSORRECTS:
4897 {
4898 SVGA3dCmdDXSetScissorRects *pCmd = (SVGA3dCmdDXSetScissorRects *)pvCmd;
4899 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4900 rcParse = vmsvga3dCmdDXSetScissorRects(pThisCC, idDXContext, pCmd, cbCmd);
4901 break;
4902 }
4903
4904 case SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW:
4905 {
4906 SVGA3dCmdDXClearRenderTargetView *pCmd = (SVGA3dCmdDXClearRenderTargetView *)pvCmd;
4907 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4908 rcParse = vmsvga3dCmdDXClearRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
4909 break;
4910 }
4911
4912 case SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW:
4913 {
4914 SVGA3dCmdDXClearDepthStencilView *pCmd = (SVGA3dCmdDXClearDepthStencilView *)pvCmd;
4915 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4916 rcParse = vmsvga3dCmdDXClearDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
4917 break;
4918 }
4919
4920 case SVGA_3D_CMD_DX_PRED_COPY_REGION:
4921 {
4922 SVGA3dCmdDXPredCopyRegion *pCmd = (SVGA3dCmdDXPredCopyRegion *)pvCmd;
4923 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4924 rcParse = vmsvga3dCmdDXPredCopyRegion(pThisCC, idDXContext, pCmd, cbCmd);
4925 break;
4926 }
4927
4928 case SVGA_3D_CMD_DX_PRED_COPY:
4929 {
4930 SVGA3dCmdDXPredCopy *pCmd = (SVGA3dCmdDXPredCopy *)pvCmd;
4931 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4932 rcParse = vmsvga3dCmdDXPredCopy(pThisCC, idDXContext, pCmd, cbCmd);
4933 break;
4934 }
4935
4936 case SVGA_3D_CMD_DX_PRESENTBLT:
4937 {
4938 SVGA3dCmdDXPresentBlt *pCmd = (SVGA3dCmdDXPresentBlt *)pvCmd;
4939 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4940 rcParse = vmsvga3dCmdDXPresentBlt(pThisCC, idDXContext, pCmd, cbCmd);
4941 break;
4942 }
4943
4944 case SVGA_3D_CMD_DX_GENMIPS:
4945 {
4946 SVGA3dCmdDXGenMips *pCmd = (SVGA3dCmdDXGenMips *)pvCmd;
4947 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4948 rcParse = vmsvga3dCmdDXGenMips(pThisCC, idDXContext, pCmd, cbCmd);
4949 break;
4950 }
4951
4952 case SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE:
4953 {
4954 SVGA3dCmdDXUpdateSubResource *pCmd = (SVGA3dCmdDXUpdateSubResource *)pvCmd;
4955 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4956 rcParse = vmsvga3dCmdDXUpdateSubResource(pThisCC, idDXContext, pCmd, cbCmd);
4957 break;
4958 }
4959
4960 case SVGA_3D_CMD_DX_READBACK_SUBRESOURCE:
4961 {
4962 SVGA3dCmdDXReadbackSubResource *pCmd = (SVGA3dCmdDXReadbackSubResource *)pvCmd;
4963 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4964 rcParse = vmsvga3dCmdDXReadbackSubResource(pThisCC, idDXContext, pCmd, cbCmd);
4965 break;
4966 }
4967
4968 case SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE:
4969 {
4970 SVGA3dCmdDXInvalidateSubResource *pCmd = (SVGA3dCmdDXInvalidateSubResource *)pvCmd;
4971 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4972 rcParse = vmsvga3dCmdDXInvalidateSubResource(pThisCC, idDXContext, pCmd, cbCmd);
4973 break;
4974 }
4975
4976 case SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW:
4977 {
4978 SVGA3dCmdDXDefineShaderResourceView *pCmd = (SVGA3dCmdDXDefineShaderResourceView *)pvCmd;
4979 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4980 rcParse = vmsvga3dCmdDXDefineShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
4981 break;
4982 }
4983
4984 case SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW:
4985 {
4986 SVGA3dCmdDXDestroyShaderResourceView *pCmd = (SVGA3dCmdDXDestroyShaderResourceView *)pvCmd;
4987 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4988 rcParse = vmsvga3dCmdDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
4989 break;
4990 }
4991
4992 case SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW:
4993 {
4994 SVGA3dCmdDXDefineRenderTargetView *pCmd = (SVGA3dCmdDXDefineRenderTargetView *)pvCmd;
4995 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4996 rcParse = vmsvga3dCmdDXDefineRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
4997 break;
4998 }
4999
5000 case SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW:
5001 {
5002 SVGA3dCmdDXDestroyRenderTargetView *pCmd = (SVGA3dCmdDXDestroyRenderTargetView *)pvCmd;
5003 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5004 rcParse = vmsvga3dCmdDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5005 break;
5006 }
5007
5008 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW:
5009 {
5010 SVGA3dCmdDXDefineDepthStencilView *pCmd = (SVGA3dCmdDXDefineDepthStencilView *)pvCmd;
5011 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5012 rcParse = vmsvga3dCmdDXDefineDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5013 break;
5014 }
5015
5016 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW:
5017 {
5018 SVGA3dCmdDXDestroyDepthStencilView *pCmd = (SVGA3dCmdDXDestroyDepthStencilView *)pvCmd;
5019 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5020 rcParse = vmsvga3dCmdDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5021 break;
5022 }
5023
5024 case SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT:
5025 {
5026 SVGA3dCmdDXDefineElementLayout *pCmd = (SVGA3dCmdDXDefineElementLayout *)pvCmd;
5027 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5028 rcParse = vmsvga3dCmdDXDefineElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5029 break;
5030 }
5031
5032 case SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT:
5033 {
5034 SVGA3dCmdDXDestroyElementLayout *pCmd = (SVGA3dCmdDXDestroyElementLayout *)pvCmd;
5035 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5036 rcParse = vmsvga3dCmdDXDestroyElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5037 break;
5038 }
5039
5040 case SVGA_3D_CMD_DX_DEFINE_BLEND_STATE:
5041 {
5042 SVGA3dCmdDXDefineBlendState *pCmd = (SVGA3dCmdDXDefineBlendState *)pvCmd;
5043 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5044 rcParse = vmsvga3dCmdDXDefineBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5045 break;
5046 }
5047
5048 case SVGA_3D_CMD_DX_DESTROY_BLEND_STATE:
5049 {
5050 SVGA3dCmdDXDestroyBlendState *pCmd = (SVGA3dCmdDXDestroyBlendState *)pvCmd;
5051 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5052 rcParse = vmsvga3dCmdDXDestroyBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5053 break;
5054 }
5055
5056 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE:
5057 {
5058 SVGA3dCmdDXDefineDepthStencilState *pCmd = (SVGA3dCmdDXDefineDepthStencilState *)pvCmd;
5059 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5060 rcParse = vmsvga3dCmdDXDefineDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5061 break;
5062 }
5063
5064 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE:
5065 {
5066 SVGA3dCmdDXDestroyDepthStencilState *pCmd = (SVGA3dCmdDXDestroyDepthStencilState *)pvCmd;
5067 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5068 rcParse = vmsvga3dCmdDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5069 break;
5070 }
5071
5072 case SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE:
5073 {
5074 SVGA3dCmdDXDefineRasterizerState *pCmd = (SVGA3dCmdDXDefineRasterizerState *)pvCmd;
5075 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5076 rcParse = vmsvga3dCmdDXDefineRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5077 break;
5078 }
5079
5080 case SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE:
5081 {
5082 SVGA3dCmdDXDestroyRasterizerState *pCmd = (SVGA3dCmdDXDestroyRasterizerState *)pvCmd;
5083 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5084 rcParse = vmsvga3dCmdDXDestroyRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5085 break;
5086 }
5087
5088 case SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE:
5089 {
5090 SVGA3dCmdDXDefineSamplerState *pCmd = (SVGA3dCmdDXDefineSamplerState *)pvCmd;
5091 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5092 rcParse = vmsvga3dCmdDXDefineSamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5093 break;
5094 }
5095
5096 case SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE:
5097 {
5098 SVGA3dCmdDXDestroySamplerState *pCmd = (SVGA3dCmdDXDestroySamplerState *)pvCmd;
5099 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5100 rcParse = vmsvga3dCmdDXDestroySamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5101 break;
5102 }
5103
5104 case SVGA_3D_CMD_DX_DEFINE_SHADER:
5105 {
5106 SVGA3dCmdDXDefineShader *pCmd = (SVGA3dCmdDXDefineShader *)pvCmd;
5107 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5108 rcParse = vmsvga3dCmdDXDefineShader(pThisCC, idDXContext, pCmd, cbCmd);
5109 break;
5110 }
5111
5112 case SVGA_3D_CMD_DX_DESTROY_SHADER:
5113 {
5114 SVGA3dCmdDXDestroyShader *pCmd = (SVGA3dCmdDXDestroyShader *)pvCmd;
5115 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5116 rcParse = vmsvga3dCmdDXDestroyShader(pThisCC, idDXContext, pCmd, cbCmd);
5117 break;
5118 }
5119
5120 case SVGA_3D_CMD_DX_BIND_SHADER:
5121 {
5122 SVGA3dCmdDXBindShader *pCmd = (SVGA3dCmdDXBindShader *)pvCmd;
5123 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5124 rcParse = vmsvga3dCmdDXBindShader(pThisCC, idDXContext, pCmd, cbCmd);
5125 break;
5126 }
5127
5128 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT:
5129 {
5130 SVGA3dCmdDXDefineStreamOutput *pCmd = (SVGA3dCmdDXDefineStreamOutput *)pvCmd;
5131 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5132 rcParse = vmsvga3dCmdDXDefineStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5133 break;
5134 }
5135
5136 case SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT:
5137 {
5138 SVGA3dCmdDXDestroyStreamOutput *pCmd = (SVGA3dCmdDXDestroyStreamOutput *)pvCmd;
5139 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5140 rcParse = vmsvga3dCmdDXDestroyStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5141 break;
5142 }
5143
5144 case SVGA_3D_CMD_DX_SET_STREAMOUTPUT:
5145 {
5146 SVGA3dCmdDXSetStreamOutput *pCmd = (SVGA3dCmdDXSetStreamOutput *)pvCmd;
5147 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5148 rcParse = vmsvga3dCmdDXSetStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5149 break;
5150 }
5151
5152 case SVGA_3D_CMD_DX_SET_COTABLE:
5153 {
5154 SVGA3dCmdDXSetCOTable *pCmd = (SVGA3dCmdDXSetCOTable *)pvCmd;
5155 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5156 rcParse = vmsvga3dCmdDXSetCOTable(pThisCC, pCmd, cbCmd);
5157 break;
5158 }
5159
5160 case SVGA_3D_CMD_DX_READBACK_COTABLE:
5161 {
5162 SVGA3dCmdDXReadbackCOTable *pCmd = (SVGA3dCmdDXReadbackCOTable *)pvCmd;
5163 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5164 rcParse = vmsvga3dCmdDXReadbackCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5165 break;
5166 }
5167
5168 case SVGA_3D_CMD_DX_BUFFER_COPY:
5169 {
5170 SVGA3dCmdDXBufferCopy *pCmd = (SVGA3dCmdDXBufferCopy *)pvCmd;
5171 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5172 rcParse = vmsvga3dCmdDXBufferCopy(pThisCC, idDXContext, pCmd, cbCmd);
5173 break;
5174 }
5175
5176 case SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER:
5177 {
5178 SVGA3dCmdDXTransferFromBuffer *pCmd = (SVGA3dCmdDXTransferFromBuffer *)pvCmd;
5179 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5180 rcParse = vmsvga3dCmdDXTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5181 break;
5182 }
5183
5184 case SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK:
5185 {
5186 SVGA3dCmdDXSurfaceCopyAndReadback *pCmd = (SVGA3dCmdDXSurfaceCopyAndReadback *)pvCmd;
5187 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5188 rcParse = vmsvga3dCmdDXSurfaceCopyAndReadback(pThisCC, idDXContext, pCmd, cbCmd);
5189 break;
5190 }
5191
5192 case SVGA_3D_CMD_DX_MOVE_QUERY:
5193 {
5194 SVGA3dCmdDXMoveQuery *pCmd = (SVGA3dCmdDXMoveQuery *)pvCmd;
5195 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5196 rcParse = vmsvga3dCmdDXMoveQuery(pThisCC, idDXContext, pCmd, cbCmd);
5197 break;
5198 }
5199
5200 case SVGA_3D_CMD_DX_BIND_ALL_QUERY:
5201 {
5202 SVGA3dCmdDXBindAllQuery *pCmd = (SVGA3dCmdDXBindAllQuery *)pvCmd;
5203 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5204 rcParse = vmsvga3dCmdDXBindAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5205 break;
5206 }
5207
5208 case SVGA_3D_CMD_DX_READBACK_ALL_QUERY:
5209 {
5210 SVGA3dCmdDXReadbackAllQuery *pCmd = (SVGA3dCmdDXReadbackAllQuery *)pvCmd;
5211 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5212 rcParse = vmsvga3dCmdDXReadbackAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5213 break;
5214 }
5215
5216 case SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER:
5217 {
5218 SVGA3dCmdDXPredTransferFromBuffer *pCmd = (SVGA3dCmdDXPredTransferFromBuffer *)pvCmd;
5219 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5220 rcParse = vmsvga3dCmdDXPredTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5221 break;
5222 }
5223
5224 case SVGA_3D_CMD_DX_MOB_FENCE_64:
5225 {
5226 SVGA3dCmdDXMobFence64 *pCmd = (SVGA3dCmdDXMobFence64 *)pvCmd;
5227 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5228 rcParse = vmsvga3dCmdDXMobFence64(pThisCC, idDXContext, pCmd, cbCmd);
5229 break;
5230 }
5231
5232 case SVGA_3D_CMD_DX_BIND_ALL_SHADER:
5233 {
5234 SVGA3dCmdDXBindAllShader *pCmd = (SVGA3dCmdDXBindAllShader *)pvCmd;
5235 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5236 rcParse = vmsvga3dCmdDXBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5237 break;
5238 }
5239
5240 case SVGA_3D_CMD_DX_HINT:
5241 {
5242 SVGA3dCmdDXHint *pCmd = (SVGA3dCmdDXHint *)pvCmd;
5243 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5244 rcParse = vmsvga3dCmdDXHint(pThisCC, idDXContext, pCmd, cbCmd);
5245 break;
5246 }
5247
5248 case SVGA_3D_CMD_DX_BUFFER_UPDATE:
5249 {
5250 SVGA3dCmdDXBufferUpdate *pCmd = (SVGA3dCmdDXBufferUpdate *)pvCmd;
5251 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5252 rcParse = vmsvga3dCmdDXBufferUpdate(pThisCC, idDXContext, pCmd, cbCmd);
5253 break;
5254 }
5255
5256 case SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET:
5257 {
5258 SVGA3dCmdDXSetVSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetVSConstantBufferOffset *)pvCmd;
5259 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5260 rcParse = vmsvga3dCmdDXSetVSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5261 break;
5262 }
5263
5264 case SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET:
5265 {
5266 SVGA3dCmdDXSetPSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetPSConstantBufferOffset *)pvCmd;
5267 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5268 rcParse = vmsvga3dCmdDXSetPSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5269 break;
5270 }
5271
5272 case SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET:
5273 {
5274 SVGA3dCmdDXSetGSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetGSConstantBufferOffset *)pvCmd;
5275 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5276 rcParse = vmsvga3dCmdDXSetGSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5277 break;
5278 }
5279
5280 case SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET:
5281 {
5282 SVGA3dCmdDXSetHSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetHSConstantBufferOffset *)pvCmd;
5283 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5284 rcParse = vmsvga3dCmdDXSetHSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5285 break;
5286 }
5287
5288 case SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET:
5289 {
5290 SVGA3dCmdDXSetDSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetDSConstantBufferOffset *)pvCmd;
5291 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5292 rcParse = vmsvga3dCmdDXSetDSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5293 break;
5294 }
5295
5296 case SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET:
5297 {
5298 SVGA3dCmdDXSetCSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetCSConstantBufferOffset *)pvCmd;
5299 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5300 rcParse = vmsvga3dCmdDXSetCSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5301 break;
5302 }
5303
5304 case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER:
5305 {
5306 SVGA3dCmdDXCondBindAllShader *pCmd = (SVGA3dCmdDXCondBindAllShader *)pvCmd;
5307 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5308 rcParse = vmsvga3dCmdDXCondBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5309 break;
5310 }
5311
5312 case SVGA_3D_CMD_SCREEN_COPY:
5313 {
5314 SVGA3dCmdScreenCopy *pCmd = (SVGA3dCmdScreenCopy *)pvCmd;
5315 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5316 rcParse = vmsvga3dCmdScreenCopy(pThisCC, idDXContext, pCmd, cbCmd);
5317 break;
5318 }
5319
5320 case SVGA_3D_CMD_RESERVED1:
5321 {
5322 VMSVGA_3D_CMD_NOTIMPL();
5323 break;
5324 }
5325
5326 case SVGA_3D_CMD_RESERVED2:
5327 {
5328 VMSVGA_3D_CMD_NOTIMPL();
5329 break;
5330 }
5331
5332 case SVGA_3D_CMD_RESERVED3:
5333 {
5334 VMSVGA_3D_CMD_NOTIMPL();
5335 break;
5336 }
5337
5338 case SVGA_3D_CMD_RESERVED4:
5339 {
5340 VMSVGA_3D_CMD_NOTIMPL();
5341 break;
5342 }
5343
5344 case SVGA_3D_CMD_RESERVED5:
5345 {
5346 VMSVGA_3D_CMD_NOTIMPL();
5347 break;
5348 }
5349
5350 case SVGA_3D_CMD_RESERVED6:
5351 {
5352 VMSVGA_3D_CMD_NOTIMPL();
5353 break;
5354 }
5355
5356 case SVGA_3D_CMD_RESERVED7:
5357 {
5358 VMSVGA_3D_CMD_NOTIMPL();
5359 break;
5360 }
5361
5362 case SVGA_3D_CMD_RESERVED8:
5363 {
5364 VMSVGA_3D_CMD_NOTIMPL();
5365 break;
5366 }
5367
5368 case SVGA_3D_CMD_GROW_OTABLE:
5369 {
5370 SVGA3dCmdGrowOTable *pCmd = (SVGA3dCmdGrowOTable *)pvCmd;
5371 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5372 rcParse = vmsvga3dCmdGrowOTable(pThisCC, idDXContext, pCmd, cbCmd);
5373 break;
5374 }
5375
5376 case SVGA_3D_CMD_DX_GROW_COTABLE:
5377 {
5378 SVGA3dCmdDXGrowCOTable *pCmd = (SVGA3dCmdDXGrowCOTable *)pvCmd;
5379 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5380 rcParse = vmsvga3dCmdDXGrowCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5381 break;
5382 }
5383
5384 case SVGA_3D_CMD_INTRA_SURFACE_COPY:
5385 {
5386 SVGA3dCmdIntraSurfaceCopy *pCmd = (SVGA3dCmdIntraSurfaceCopy *)pvCmd;
5387 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5388 rcParse = vmsvga3dCmdIntraSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5389 break;
5390 }
5391
5392 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V3:
5393 {
5394 SVGA3dCmdDefineGBSurface_v3 *pCmd = (SVGA3dCmdDefineGBSurface_v3 *)pvCmd;
5395 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5396 rcParse = vmsvga3dCmdDefineGBSurface_v3(pThisCC, idDXContext, pCmd, cbCmd);
5397 break;
5398 }
5399
5400 case SVGA_3D_CMD_DX_RESOLVE_COPY:
5401 {
5402 SVGA3dCmdDXResolveCopy *pCmd = (SVGA3dCmdDXResolveCopy *)pvCmd;
5403 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5404 rcParse = vmsvga3dCmdDXResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5405 break;
5406 }
5407
5408 case SVGA_3D_CMD_DX_PRED_RESOLVE_COPY:
5409 {
5410 SVGA3dCmdDXPredResolveCopy *pCmd = (SVGA3dCmdDXPredResolveCopy *)pvCmd;
5411 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5412 rcParse = vmsvga3dCmdDXPredResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5413 break;
5414 }
5415
5416 case SVGA_3D_CMD_DX_PRED_CONVERT_REGION:
5417 {
5418 SVGA3dCmdDXPredConvertRegion *pCmd = (SVGA3dCmdDXPredConvertRegion *)pvCmd;
5419 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5420 rcParse = vmsvga3dCmdDXPredConvertRegion(pThisCC, idDXContext, pCmd, cbCmd);
5421 break;
5422 }
5423
5424 case SVGA_3D_CMD_DX_PRED_CONVERT:
5425 {
5426 SVGA3dCmdDXPredConvert *pCmd = (SVGA3dCmdDXPredConvert *)pvCmd;
5427 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5428 rcParse = vmsvga3dCmdDXPredConvert(pThisCC, idDXContext, pCmd, cbCmd);
5429 break;
5430 }
5431
5432 case SVGA_3D_CMD_WHOLE_SURFACE_COPY:
5433 {
5434 SVGA3dCmdWholeSurfaceCopy *pCmd = (SVGA3dCmdWholeSurfaceCopy *)pvCmd;
5435 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5436 rcParse = vmsvga3dCmdWholeSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5437 break;
5438 }
5439
5440 case SVGA_3D_CMD_DX_DEFINE_UA_VIEW:
5441 {
5442 SVGA3dCmdDXDefineUAView *pCmd = (SVGA3dCmdDXDefineUAView *)pvCmd;
5443 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5444 rcParse = vmsvga3dCmdDXDefineUAView(pThisCC, idDXContext, pCmd, cbCmd);
5445 break;
5446 }
5447
5448 case SVGA_3D_CMD_DX_DESTROY_UA_VIEW:
5449 {
5450 SVGA3dCmdDXDestroyUAView *pCmd = (SVGA3dCmdDXDestroyUAView *)pvCmd;
5451 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5452 rcParse = vmsvga3dCmdDXDestroyUAView(pThisCC, idDXContext, pCmd, cbCmd);
5453 break;
5454 }
5455
5456 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT:
5457 {
5458 SVGA3dCmdDXClearUAViewUint *pCmd = (SVGA3dCmdDXClearUAViewUint *)pvCmd;
5459 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5460 rcParse = vmsvga3dCmdDXClearUAViewUint(pThisCC, idDXContext, pCmd, cbCmd);
5461 break;
5462 }
5463
5464 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT:
5465 {
5466 SVGA3dCmdDXClearUAViewFloat *pCmd = (SVGA3dCmdDXClearUAViewFloat *)pvCmd;
5467 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5468 rcParse = vmsvga3dCmdDXClearUAViewFloat(pThisCC, idDXContext, pCmd, cbCmd);
5469 break;
5470 }
5471
5472 case SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT:
5473 {
5474 SVGA3dCmdDXCopyStructureCount *pCmd = (SVGA3dCmdDXCopyStructureCount *)pvCmd;
5475 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5476 rcParse = vmsvga3dCmdDXCopyStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5477 break;
5478 }
5479
5480 case SVGA_3D_CMD_DX_SET_UA_VIEWS:
5481 {
5482 SVGA3dCmdDXSetUAViews *pCmd = (SVGA3dCmdDXSetUAViews *)pvCmd;
5483 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5484 rcParse = vmsvga3dCmdDXSetUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5485 break;
5486 }
5487
5488 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT:
5489 {
5490 SVGA3dCmdDXDrawIndexedInstancedIndirect *pCmd = (SVGA3dCmdDXDrawIndexedInstancedIndirect *)pvCmd;
5491 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5492 rcParse = vmsvga3dCmdDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5493 break;
5494 }
5495
5496 case SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT:
5497 {
5498 SVGA3dCmdDXDrawInstancedIndirect *pCmd = (SVGA3dCmdDXDrawInstancedIndirect *)pvCmd;
5499 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5500 rcParse = vmsvga3dCmdDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5501 break;
5502 }
5503
5504 case SVGA_3D_CMD_DX_DISPATCH:
5505 {
5506 SVGA3dCmdDXDispatch *pCmd = (SVGA3dCmdDXDispatch *)pvCmd;
5507 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5508 rcParse = vmsvga3dCmdDXDispatch(pThisCC, idDXContext, pCmd, cbCmd);
5509 break;
5510 }
5511
5512 case SVGA_3D_CMD_DX_DISPATCH_INDIRECT:
5513 {
5514 SVGA3dCmdDXDispatchIndirect *pCmd = (SVGA3dCmdDXDispatchIndirect *)pvCmd;
5515 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5516 rcParse = vmsvga3dCmdDXDispatchIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5517 break;
5518 }
5519
5520 case SVGA_3D_CMD_WRITE_ZERO_SURFACE:
5521 {
5522 SVGA3dCmdWriteZeroSurface *pCmd = (SVGA3dCmdWriteZeroSurface *)pvCmd;
5523 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5524 rcParse = vmsvga3dCmdWriteZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5525 break;
5526 }
5527
5528 case SVGA_3D_CMD_HINT_ZERO_SURFACE:
5529 {
5530 SVGA3dCmdHintZeroSurface *pCmd = (SVGA3dCmdHintZeroSurface *)pvCmd;
5531 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5532 rcParse = vmsvga3dCmdHintZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5533 break;
5534 }
5535
5536 case SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER:
5537 {
5538 SVGA3dCmdDXTransferToBuffer *pCmd = (SVGA3dCmdDXTransferToBuffer *)pvCmd;
5539 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5540 rcParse = vmsvga3dCmdDXTransferToBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5541 break;
5542 }
5543
5544 case SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT:
5545 {
5546 SVGA3dCmdDXSetStructureCount *pCmd = (SVGA3dCmdDXSetStructureCount *)pvCmd;
5547 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5548 rcParse = vmsvga3dCmdDXSetStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5549 break;
5550 }
5551
5552 case SVGA_3D_CMD_LOGICOPS_BITBLT:
5553 {
5554 SVGA3dCmdLogicOpsBitBlt *pCmd = (SVGA3dCmdLogicOpsBitBlt *)pvCmd;
5555 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5556 rcParse = vmsvga3dCmdLogicOpsBitBlt(pThisCC, idDXContext, pCmd, cbCmd);
5557 break;
5558 }
5559
5560 case SVGA_3D_CMD_LOGICOPS_TRANSBLT:
5561 {
5562 SVGA3dCmdLogicOpsTransBlt *pCmd = (SVGA3dCmdLogicOpsTransBlt *)pvCmd;
5563 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5564 rcParse = vmsvga3dCmdLogicOpsTransBlt(pThisCC, idDXContext, pCmd, cbCmd);
5565 break;
5566 }
5567
5568 case SVGA_3D_CMD_LOGICOPS_STRETCHBLT:
5569 {
5570 SVGA3dCmdLogicOpsStretchBlt *pCmd = (SVGA3dCmdLogicOpsStretchBlt *)pvCmd;
5571 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5572 rcParse = vmsvga3dCmdLogicOpsStretchBlt(pThisCC, idDXContext, pCmd, cbCmd);
5573 break;
5574 }
5575
5576 case SVGA_3D_CMD_LOGICOPS_COLORFILL:
5577 {
5578 SVGA3dCmdLogicOpsColorFill *pCmd = (SVGA3dCmdLogicOpsColorFill *)pvCmd;
5579 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5580 rcParse = vmsvga3dCmdLogicOpsColorFill(pThisCC, idDXContext, pCmd, cbCmd);
5581 break;
5582 }
5583
5584 case SVGA_3D_CMD_LOGICOPS_ALPHABLEND:
5585 {
5586 SVGA3dCmdLogicOpsAlphaBlend *pCmd = (SVGA3dCmdLogicOpsAlphaBlend *)pvCmd;
5587 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5588 rcParse = vmsvga3dCmdLogicOpsAlphaBlend(pThisCC, idDXContext, pCmd, cbCmd);
5589 break;
5590 }
5591
5592 case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND:
5593 {
5594 SVGA3dCmdLogicOpsClearTypeBlend *pCmd = (SVGA3dCmdLogicOpsClearTypeBlend *)pvCmd;
5595 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5596 rcParse = vmsvga3dCmdLogicOpsClearTypeBlend(pThisCC, idDXContext, pCmd, cbCmd);
5597 break;
5598 }
5599
5600 case SVGA_3D_CMD_RESERVED2_1:
5601 {
5602 VMSVGA_3D_CMD_NOTIMPL();
5603 break;
5604 }
5605
5606 case SVGA_3D_CMD_RESERVED2_2:
5607 {
5608 VMSVGA_3D_CMD_NOTIMPL();
5609 break;
5610 }
5611
5612 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V4:
5613 {
5614 SVGA3dCmdDefineGBSurface_v4 *pCmd = (SVGA3dCmdDefineGBSurface_v4 *)pvCmd;
5615 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5616 rcParse = vmsvga3dCmdDefineGBSurface_v4(pThisCC, idDXContext, pCmd, cbCmd);
5617 break;
5618 }
5619
5620 case SVGA_3D_CMD_DX_SET_CS_UA_VIEWS:
5621 {
5622 SVGA3dCmdDXSetCSUAViews *pCmd = (SVGA3dCmdDXSetCSUAViews *)pvCmd;
5623 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5624 rcParse = vmsvga3dCmdDXSetCSUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5625 break;
5626 }
5627
5628 case SVGA_3D_CMD_DX_SET_MIN_LOD:
5629 {
5630 SVGA3dCmdDXSetMinLOD *pCmd = (SVGA3dCmdDXSetMinLOD *)pvCmd;
5631 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5632 rcParse = vmsvga3dCmdDXSetMinLOD(pThisCC, idDXContext, pCmd, cbCmd);
5633 break;
5634 }
5635
5636 case SVGA_3D_CMD_RESERVED2_3:
5637 {
5638 VMSVGA_3D_CMD_NOTIMPL();
5639 break;
5640 }
5641
5642 case SVGA_3D_CMD_RESERVED2_4:
5643 {
5644 VMSVGA_3D_CMD_NOTIMPL();
5645 break;
5646 }
5647
5648 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2:
5649 {
5650 SVGA3dCmdDXDefineDepthStencilView_v2 *pCmd = (SVGA3dCmdDXDefineDepthStencilView_v2 *)pvCmd;
5651 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5652 rcParse = vmsvga3dCmdDXDefineDepthStencilView_v2(pThisCC, idDXContext, pCmd, cbCmd);
5653 break;
5654 }
5655
5656 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB:
5657 {
5658 SVGA3dCmdDXDefineStreamOutputWithMob *pCmd = (SVGA3dCmdDXDefineStreamOutputWithMob *)pvCmd;
5659 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5660 rcParse = vmsvga3dCmdDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd, cbCmd);
5661 break;
5662 }
5663
5664 case SVGA_3D_CMD_DX_SET_SHADER_IFACE:
5665 {
5666 SVGA3dCmdDXSetShaderIface *pCmd = (SVGA3dCmdDXSetShaderIface *)pvCmd;
5667 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5668 rcParse = vmsvga3dCmdDXSetShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
5669 break;
5670 }
5671
5672 case SVGA_3D_CMD_DX_BIND_STREAMOUTPUT:
5673 {
5674 SVGA3dCmdDXBindStreamOutput *pCmd = (SVGA3dCmdDXBindStreamOutput *)pvCmd;
5675 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5676 rcParse = vmsvga3dCmdDXBindStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5677 break;
5678 }
5679
5680 case SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS:
5681 {
5682 SVGA3dCmdSurfaceStretchBltNonMSToMS *pCmd = (SVGA3dCmdSurfaceStretchBltNonMSToMS *)pvCmd;
5683 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5684 rcParse = vmsvga3dCmdSurfaceStretchBltNonMSToMS(pThisCC, idDXContext, pCmd, cbCmd);
5685 break;
5686 }
5687
5688 case SVGA_3D_CMD_DX_BIND_SHADER_IFACE:
5689 {
5690 SVGA3dCmdDXBindShaderIface *pCmd = (SVGA3dCmdDXBindShaderIface *)pvCmd;
5691 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5692 rcParse = vmsvga3dCmdDXBindShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
5693 break;
5694 }
5695
5696 /* Unsupported commands. */
5697 case SVGA_3D_CMD_DEAD4: /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
5698 case SVGA_3D_CMD_DEAD5: /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
5699 case SVGA_3D_CMD_DEAD6: /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
5700 case SVGA_3D_CMD_DEAD7: /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
5701 case SVGA_3D_CMD_DEAD8: /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
5702 case SVGA_3D_CMD_DEAD9: /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
5703 case SVGA_3D_CMD_DEAD10: /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
5704 case SVGA_3D_CMD_DEAD11: /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
5705 /* Prevent the compiler warning. */
5706 case SVGA_3D_CMD_LEGACY_BASE:
5707 case SVGA_3D_CMD_MAX:
5708 case SVGA_3D_CMD_FUTURE_MAX:
5709 /* No 'default' case */
5710 STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
5711 ASSERT_GUEST_MSG_FAILED(("enmCmdId=%d\n", enmCmdId));
5712 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
5713 rcParse = VERR_NOT_IMPLEMENTED;
5714 break;
5715 }
5716
5717 return VINF_SUCCESS;
5718// return rcParse;
5719}
5720# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
5721#endif /* VBOX_WITH_VMSVGA3D */
5722
5723
5724/*
5725 *
5726 * Handlers for FIFO commands.
5727 *
5728 * Every handler takes the following parameters:
5729 *
5730 * pThis The shared VGA/VMSVGA state.
5731 * pThisCC The VGA/VMSVGA state for ring-3.
5732 * pCmd The command data.
5733 */
5734
5735
5736/* SVGA_CMD_UPDATE */
5737void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
5738{
5739 RT_NOREF(pThis);
5740 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5741
5742 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
5743 Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
5744
5745 /** @todo Multiple screens? */
5746 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5747 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
5748 return;
5749
5750 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
5751}
5752
5753
5754/* SVGA_CMD_UPDATE_VERBOSE */
5755void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
5756{
5757 RT_NOREF(pThis);
5758 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5759
5760 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
5761 Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
5762
5763 /** @todo Multiple screens? */
5764 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5765 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
5766 return;
5767
5768 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
5769}
5770
5771
5772/* SVGA_CMD_RECT_FILL */
5773void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
5774{
5775 RT_NOREF(pThis, pCmd);
5776 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5777
5778 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
5779 Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
5780 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
5781}
5782
5783
5784/* SVGA_CMD_RECT_COPY */
5785void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
5786{
5787 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5788
5789 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
5790 Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
5791
5792 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5793 AssertPtrReturnVoid(pScreen);
5794
5795 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
5796 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
5797 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
5798 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
5799 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
5800 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
5801 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
5802
5803 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
5804 pCmd->width, pCmd->height, pThis->vram_size);
5805 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
5806}
5807
5808
5809/* SVGA_CMD_RECT_ROP_COPY */
5810void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
5811{
5812 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5813
5814 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
5815 Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
5816
5817 if (pCmd->rop != SVGA_ROP_COPY)
5818 {
5819 /* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
5820 * as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
5821 * respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
5822 * SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
5823 */
5824 LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
5825 pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
5826 return;
5827 }
5828
5829 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5830 AssertPtrReturnVoid(pScreen);
5831
5832 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
5833 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
5834 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
5835 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
5836 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
5837 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
5838 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
5839
5840 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
5841 pCmd->width, pCmd->height, pThis->vram_size);
5842 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
5843}
5844
5845
5846/* SVGA_CMD_DISPLAY_CURSOR */
5847void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
5848{
5849 RT_NOREF(pThis, pCmd);
5850 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5851
5852 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
5853 Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
5854 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
5855}
5856
5857
5858/* SVGA_CMD_MOVE_CURSOR */
5859void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
5860{
5861 RT_NOREF(pThis, pCmd);
5862 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5863
5864 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
5865 Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
5866 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
5867}
5868
5869
5870/* SVGA_CMD_DEFINE_CURSOR */
5871void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
5872{
5873 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5874
5875 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
5876 Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
5877 pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
5878
5879 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
5880 ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
5881 ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
5882 RT_UNTRUSTED_VALIDATED_FENCE();
5883
5884 uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
5885 uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
5886 uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
5887
5888 uint8_t const *pbSrcAndMask = (uint8_t const *)(pCmd + 1);
5889 uint8_t const *pbSrcXorMask = (uint8_t const *)(pCmd + 1) + cbSrcAndMask;
5890
5891 uint32_t const cx = pCmd->width;
5892 uint32_t const cy = pCmd->height;
5893
5894 /*
5895 * Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
5896 * The AND data uses 8-bit aligned scanlines.
5897 * The XOR data must be starting on a 32-bit boundrary.
5898 */
5899 uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
5900 uint32_t cbDstAndMask = cbDstAndLine * cy;
5901 uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
5902 uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
5903
5904 uint8_t *pbCopy = (uint8_t *)RTMemAlloc(cbCopy);
5905 AssertReturnVoid(pbCopy);
5906
5907 /* Convert the AND mask. */
5908 uint8_t *pbDst = pbCopy;
5909 uint8_t const *pbSrc = pbSrcAndMask;
5910 switch (pCmd->andMaskDepth)
5911 {
5912 case 1:
5913 if (cbSrcAndLine == cbDstAndLine)
5914 memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
5915 else
5916 {
5917 Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
5918 for (uint32_t y = 0; y < cy; y++)
5919 {
5920 memcpy(pbDst, pbSrc, cbDstAndLine);
5921 pbDst += cbDstAndLine;
5922 pbSrc += cbSrcAndLine;
5923 }
5924 }
5925 break;
5926 /* Should take the XOR mask into account for the multi-bit AND mask. */
5927 case 8:
5928 for (uint32_t y = 0; y < cy; y++)
5929 {
5930 for (uint32_t x = 0; x < cx; )
5931 {
5932 uint8_t bDst = 0;
5933 uint8_t fBit = 0x80;
5934 do
5935 {
5936 uintptr_t const idxPal = pbSrc[x] * 3;
5937 if ((( pThis->last_palette[idxPal]
5938 | (pThis->last_palette[idxPal] >> 8)
5939 | (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
5940 bDst |= fBit;
5941 fBit >>= 1;
5942 x++;
5943 } while (x < cx && (x & 7));
5944 pbDst[(x - 1) / 8] = bDst;
5945 }
5946 pbDst += cbDstAndLine;
5947 pbSrc += cbSrcAndLine;
5948 }
5949 break;
5950 case 15:
5951 for (uint32_t y = 0; y < cy; y++)
5952 {
5953 for (uint32_t x = 0; x < cx; )
5954 {
5955 uint8_t bDst = 0;
5956 uint8_t fBit = 0x80;
5957 do
5958 {
5959 if ((pbSrc[x * 2] | (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
5960 bDst |= fBit;
5961 fBit >>= 1;
5962 x++;
5963 } while (x < cx && (x & 7));
5964 pbDst[(x - 1) / 8] = bDst;
5965 }
5966 pbDst += cbDstAndLine;
5967 pbSrc += cbSrcAndLine;
5968 }
5969 break;
5970 case 16:
5971 for (uint32_t y = 0; y < cy; y++)
5972 {
5973 for (uint32_t x = 0; x < cx; )
5974 {
5975 uint8_t bDst = 0;
5976 uint8_t fBit = 0x80;
5977 do
5978 {
5979 if ((pbSrc[x * 2] | pbSrc[x * 2 + 1]) >= 0xfc)
5980 bDst |= fBit;
5981 fBit >>= 1;
5982 x++;
5983 } while (x < cx && (x & 7));
5984 pbDst[(x - 1) / 8] = bDst;
5985 }
5986 pbDst += cbDstAndLine;
5987 pbSrc += cbSrcAndLine;
5988 }
5989 break;
5990 case 24:
5991 for (uint32_t y = 0; y < cy; y++)
5992 {
5993 for (uint32_t x = 0; x < cx; )
5994 {
5995 uint8_t bDst = 0;
5996 uint8_t fBit = 0x80;
5997 do
5998 {
5999 if ((pbSrc[x * 3] | pbSrc[x * 3 + 1] | pbSrc[x * 3 + 2]) >= 0xfc)
6000 bDst |= fBit;
6001 fBit >>= 1;
6002 x++;
6003 } while (x < cx && (x & 7));
6004 pbDst[(x - 1) / 8] = bDst;
6005 }
6006 pbDst += cbDstAndLine;
6007 pbSrc += cbSrcAndLine;
6008 }
6009 break;
6010 case 32:
6011 for (uint32_t y = 0; y < cy; y++)
6012 {
6013 for (uint32_t x = 0; x < cx; )
6014 {
6015 uint8_t bDst = 0;
6016 uint8_t fBit = 0x80;
6017 do
6018 {
6019 if ((pbSrc[x * 4] | pbSrc[x * 4 + 1] | pbSrc[x * 4 + 2] | pbSrc[x * 4 + 3]) >= 0xfc)
6020 bDst |= fBit;
6021 fBit >>= 1;
6022 x++;
6023 } while (x < cx && (x & 7));
6024 pbDst[(x - 1) / 8] = bDst;
6025 }
6026 pbDst += cbDstAndLine;
6027 pbSrc += cbSrcAndLine;
6028 }
6029 break;
6030 default:
6031 RTMemFreeZ(pbCopy, cbCopy);
6032 AssertFailedReturnVoid();
6033 }
6034
6035 /* Convert the XOR mask. */
6036 uint32_t *pu32Dst = (uint32_t *)(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
6037 pbSrc = pbSrcXorMask;
6038 switch (pCmd->xorMaskDepth)
6039 {
6040 case 1:
6041 for (uint32_t y = 0; y < cy; y++)
6042 {
6043 for (uint32_t x = 0; x < cx; )
6044 {
6045 /* most significant bit is the left most one. */
6046 uint8_t bSrc = pbSrc[x / 8];
6047 do
6048 {
6049 *pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
6050 bSrc <<= 1;
6051 x++;
6052 } while ((x & 7) && x < cx);
6053 }
6054 pbSrc += cbSrcXorLine;
6055 }
6056 break;
6057 case 8:
6058 for (uint32_t y = 0; y < cy; y++)
6059 {
6060 for (uint32_t x = 0; x < cx; x++)
6061 {
6062 uint32_t u = pThis->last_palette[pbSrc[x]];
6063 *pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
6064 }
6065 pbSrc += cbSrcXorLine;
6066 }
6067 break;
6068 case 15: /* Src: RGB-5-5-5 */
6069 for (uint32_t y = 0; y < cy; y++)
6070 {
6071 for (uint32_t x = 0; x < cx; x++)
6072 {
6073 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6074 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6075 ((uValue >> 5) & 0x1f) << 3,
6076 ((uValue >> 10) & 0x1f) << 3, 0);
6077 }
6078 pbSrc += cbSrcXorLine;
6079 }
6080 break;
6081 case 16: /* Src: RGB-5-6-5 */
6082 for (uint32_t y = 0; y < cy; y++)
6083 {
6084 for (uint32_t x = 0; x < cx; x++)
6085 {
6086 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6087 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6088 ((uValue >> 5) & 0x3f) << 2,
6089 ((uValue >> 11) & 0x1f) << 3, 0);
6090 }
6091 pbSrc += cbSrcXorLine;
6092 }
6093 break;
6094 case 24:
6095 for (uint32_t y = 0; y < cy; y++)
6096 {
6097 for (uint32_t x = 0; x < cx; x++)
6098 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*3], pbSrc[x*3 + 1], pbSrc[x*3 + 2], 0);
6099 pbSrc += cbSrcXorLine;
6100 }
6101 break;
6102 case 32:
6103 for (uint32_t y = 0; y < cy; y++)
6104 {
6105 for (uint32_t x = 0; x < cx; x++)
6106 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*4], pbSrc[x*4 + 1], pbSrc[x*4 + 2], 0);
6107 pbSrc += cbSrcXorLine;
6108 }
6109 break;
6110 default:
6111 RTMemFreeZ(pbCopy, cbCopy);
6112 AssertFailedReturnVoid();
6113 }
6114
6115 /*
6116 * Pass it to the frontend/whatever.
6117 */
6118 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6119 cx, cy, pbCopy, cbCopy);
6120}
6121
6122
6123/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
6124void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
6125{
6126 RT_NOREF(pThis);
6127 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6128
6129 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
6130 Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
6131
6132 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
6133 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6134 RT_UNTRUSTED_VALIDATED_FENCE();
6135
6136 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
6137 uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
6138 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
6139 uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
6140 uint32_t cbCursorShape = cbAndMask + cbXorMask;
6141
6142 uint8_t *pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
6143 AssertPtrReturnVoid(pCursorCopy);
6144
6145 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
6146 memset(pCursorCopy, 0xff, cbAndMask);
6147 /* Colour data */
6148 memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
6149
6150 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6151 pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
6152}
6153
6154
6155/* SVGA_CMD_ESCAPE */
6156void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
6157{
6158 RT_NOREF(pThis);
6159 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6160
6161 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
6162
6163 if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
6164 {
6165 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
6166 RT_UNTRUSTED_VALIDATED_FENCE();
6167
6168 uint32_t const cmd = *(uint32_t *)(pCmd + 1);
6169 Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
6170
6171 switch (cmd)
6172 {
6173 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
6174 {
6175 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pCmd + 1);
6176 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
6177 RT_UNTRUSTED_VALIDATED_FENCE();
6178
6179 uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
6180
6181 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
6182 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
6183 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
6184 RT_NOREF_PV(pVideoCmd);
6185 break;
6186 }
6187
6188 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
6189 {
6190 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pCmd + 1);
6191 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
6192 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
6193 RT_NOREF_PV(pVideoCmd);
6194 break;
6195 }
6196
6197 default:
6198 Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
6199 break;
6200 }
6201 }
6202 else
6203 Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
6204}
6205
6206
6207/* SVGA_CMD_DEFINE_SCREEN */
6208void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
6209{
6210 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6211
6212 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
6213 Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
6214 pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
6215 pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
6216
6217 uint32_t const idScreen = pCmd->screen.id;
6218 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6219
6220 uint32_t const uWidth = pCmd->screen.size.width;
6221 ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
6222
6223 uint32_t const uHeight = pCmd->screen.size.height;
6224 ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
6225
6226 uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
6227 uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
6228 ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
6229
6230 uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
6231 ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
6232
6233 uint32_t const cbVram = pThis->vram_size - uScreenOffset;
6234 /* If we have a not zero pitch, then height can't exceed the available VRAM. */
6235 ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
6236 || (cbPitch > 0 && uHeight <= cbVram / cbPitch));
6237 RT_UNTRUSTED_VALIDATED_FENCE();
6238
6239 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6240 pScreen->fDefined = true;
6241 pScreen->fModified = true;
6242 pScreen->fuScreen = pCmd->screen.flags;
6243 pScreen->idScreen = idScreen;
6244 if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE | SVGA_SCREEN_BLANKING)))
6245 {
6246 /* Not blanked. */
6247 ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
6248 RT_UNTRUSTED_VALIDATED_FENCE();
6249
6250 pScreen->xOrigin = pCmd->screen.root.x;
6251 pScreen->yOrigin = pCmd->screen.root.y;
6252 pScreen->cWidth = uWidth;
6253 pScreen->cHeight = uHeight;
6254 pScreen->offVRAM = uScreenOffset;
6255 pScreen->cbPitch = cbPitch;
6256 pScreen->cBpp = 32;
6257 }
6258 else
6259 {
6260 /* Screen blanked. Keep old values. */
6261 }
6262
6263 pThis->svga.fGFBRegisters = false;
6264 vmsvgaR3ChangeMode(pThis, pThisCC);
6265
6266#ifdef VBOX_WITH_VMSVGA3D
6267 if (RT_LIKELY(pThis->svga.f3DEnabled))
6268 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
6269#endif
6270}
6271
6272
6273/* SVGA_CMD_DESTROY_SCREEN */
6274void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
6275{
6276 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6277
6278 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
6279 Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
6280
6281 uint32_t const idScreen = pCmd->screenId;
6282 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6283 RT_UNTRUSTED_VALIDATED_FENCE();
6284
6285 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6286 pScreen->fModified = true;
6287 pScreen->fDefined = false;
6288 pScreen->idScreen = idScreen;
6289
6290#ifdef VBOX_WITH_VMSVGA3D
6291 if (RT_LIKELY(pThis->svga.f3DEnabled))
6292 vmsvga3dDestroyScreen(pThisCC, pScreen);
6293#endif
6294 vmsvgaR3ChangeMode(pThis, pThisCC);
6295}
6296
6297
6298/* SVGA_CMD_DEFINE_GMRFB */
6299void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
6300{
6301 RT_NOREF(pThis);
6302 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6303
6304 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
6305 Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
6306 pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
6307
6308 pSvgaR3State->GMRFB.ptr = pCmd->ptr;
6309 pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
6310 pSvgaR3State->GMRFB.format = pCmd->format;
6311}
6312
6313
6314/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
6315void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
6316{
6317 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6318
6319 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
6320 Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
6321 pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
6322
6323 ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6324 RT_UNTRUSTED_VALIDATED_FENCE();
6325
6326 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
6327 AssertPtrReturnVoid(pScreen);
6328
6329 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
6330 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6331
6332 /* Clip destRect to the screen dimensions. */
6333 SVGASignedRect screenRect;
6334 screenRect.left = 0;
6335 screenRect.top = 0;
6336 screenRect.right = pScreen->cWidth;
6337 screenRect.bottom = pScreen->cHeight;
6338 SVGASignedRect clipRect = pCmd->destRect;
6339 vmsvgaR3ClipRect(&screenRect, &clipRect);
6340 RT_UNTRUSTED_VALIDATED_FENCE();
6341
6342 uint32_t const width = clipRect.right - clipRect.left;
6343 uint32_t const height = clipRect.bottom - clipRect.top;
6344
6345 if ( width == 0
6346 || height == 0)
6347 return; /* Nothing to do. */
6348
6349 int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
6350 int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
6351
6352 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6353 * Prepare parameters for vmsvgaR3GmrTransfer.
6354 */
6355 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6356
6357 /* Destination: host buffer which describes the screen 0 VRAM.
6358 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6359 */
6360 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6361 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6362 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6363 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6364 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6365 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6366 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6367 + cbScanline * clipRect.top;
6368 int32_t const cbHstPitch = cbScanline;
6369
6370 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6371 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6372 uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6373 + pSvgaR3State->GMRFB.bytesPerLine * srcy;
6374 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6375
6376 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
6377 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6378 gstPtr, offGst, cbGstPitch,
6379 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6380 AssertRC(rc);
6381 vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
6382}
6383
6384
6385/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
6386void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
6387{
6388 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6389
6390 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
6391 /* Note! This can fetch 3d render results as well!! */
6392 Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
6393 pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
6394
6395 ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6396 RT_UNTRUSTED_VALIDATED_FENCE();
6397
6398 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
6399 AssertPtrReturnVoid(pScreen);
6400
6401 /** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
6402 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6403
6404 /* Clip destRect to the screen dimensions. */
6405 SVGASignedRect screenRect;
6406 screenRect.left = 0;
6407 screenRect.top = 0;
6408 screenRect.right = pScreen->cWidth;
6409 screenRect.bottom = pScreen->cHeight;
6410 SVGASignedRect clipRect = pCmd->srcRect;
6411 vmsvgaR3ClipRect(&screenRect, &clipRect);
6412 RT_UNTRUSTED_VALIDATED_FENCE();
6413
6414 uint32_t const width = clipRect.right - clipRect.left;
6415 uint32_t const height = clipRect.bottom - clipRect.top;
6416
6417 if ( width == 0
6418 || height == 0)
6419 return; /* Nothing to do. */
6420
6421 int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
6422 int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
6423
6424 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6425 * Prepare parameters for vmsvgaR3GmrTransfer.
6426 */
6427 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6428
6429 /* Source: host buffer which describes the screen 0 VRAM.
6430 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6431 */
6432 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6433 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6434 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6435 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6436 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6437 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6438 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6439 + cbScanline * clipRect.top;
6440 int32_t const cbHstPitch = cbScanline;
6441
6442 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6443 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6444 uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6445 + pSvgaR3State->GMRFB.bytesPerLine * dsty;
6446 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6447
6448 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
6449 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6450 gstPtr, offGst, cbGstPitch,
6451 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6452 AssertRC(rc);
6453}
6454
6455
6456/* SVGA_CMD_ANNOTATION_FILL */
6457void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
6458{
6459 RT_NOREF(pThis);
6460 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6461
6462 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
6463 Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
6464
6465 pSvgaR3State->colorAnnotation = pCmd->color;
6466}
6467
6468
6469/* SVGA_CMD_ANNOTATION_COPY */
6470void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
6471{
6472 RT_NOREF(pThis, pCmd);
6473 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6474
6475 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
6476 Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
6477
6478 AssertFailed();
6479}
6480
6481
6482#ifdef VBOX_WITH_VMSVGA3D
6483/* SVGA_CMD_DEFINE_GMR2 */
6484void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
6485{
6486 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6487
6488 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
6489 Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
6490
6491 /* Validate current GMR id. */
6492 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6493 ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
6494 RT_UNTRUSTED_VALIDATED_FENCE();
6495
6496 if (!pCmd->numPages)
6497 {
6498 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
6499 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6500 }
6501 else
6502 {
6503 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6504 if (pGMR->cMaxPages)
6505 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
6506
6507 /* Not sure if we should always free the descriptor, but for simplicity
6508 we do so if the new size is smaller than the current. */
6509 /** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
6510 if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
6511 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6512
6513 pGMR->cMaxPages = pCmd->numPages;
6514 /* The rest is done by the REMAP_GMR2 command. */
6515 }
6516}
6517
6518
6519/* SVGA_CMD_REMAP_GMR2 */
6520void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
6521{
6522 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6523
6524 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
6525 Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
6526
6527 /* Validate current GMR id and size. */
6528 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6529 RT_UNTRUSTED_VALIDATED_FENCE();
6530 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6531 ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
6532 <= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
6533 ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
6534
6535 if (pCmd->numPages == 0)
6536 return;
6537 RT_UNTRUSTED_VALIDATED_FENCE();
6538
6539 /* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
6540 uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
6541
6542 /*
6543 * We flatten the existing descriptors into a page array, overwrite the
6544 * pages specified in this command and then recompress the descriptor.
6545 */
6546 /** @todo Optimize the GMR remap algorithm! */
6547
6548 /* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
6549 uint64_t *paNewPage64 = NULL;
6550 if (pGMR->paDesc)
6551 {
6552 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
6553
6554 paNewPage64 = (uint64_t *)RTMemAllocZ(cNewTotalPages * sizeof(uint64_t));
6555 AssertPtrReturnVoid(paNewPage64);
6556
6557 uint32_t idxPage = 0;
6558 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
6559 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
6560 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
6561 AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
6562 RT_UNTRUSTED_VALIDATED_FENCE();
6563 }
6564
6565 /* Free the old GMR if present. */
6566 if (pGMR->paDesc)
6567 RTMemFree(pGMR->paDesc);
6568
6569 /* Allocate the maximum amount possible (everything non-continuous) */
6570 PVMSVGAGMRDESCRIPTOR paDescs;
6571 pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
6572 AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
6573
6574 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
6575 {
6576 /** @todo */
6577 AssertFailed();
6578 pGMR->numDescriptors = 0;
6579 }
6580 else
6581 {
6582 uint32_t *paPages32 = (uint32_t *)(pCmd + 1);
6583 uint64_t *paPages64 = (uint64_t *)(pCmd + 1);
6584 bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
6585
6586 uint32_t cPages;
6587 if (paNewPage64)
6588 {
6589 /* Overwrite the old page array with the new page values. */
6590 if (fGCPhys64)
6591 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6592 paNewPage64[i] = paPages64[i - pCmd->offsetPages];
6593 else
6594 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6595 paNewPage64[i] = paPages32[i - pCmd->offsetPages];
6596
6597 /* Use the updated page array instead of the command data. */
6598 fGCPhys64 = true;
6599 paPages64 = paNewPage64;
6600 cPages = cNewTotalPages;
6601 }
6602 else
6603 cPages = pCmd->numPages;
6604
6605 /* The first page. */
6606 /** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
6607 * applied to paNewPage64. */
6608 RTGCPHYS GCPhys;
6609 if (fGCPhys64)
6610 GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6611 else
6612 GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
6613 paDescs[0].GCPhys = GCPhys;
6614 paDescs[0].numPages = 1;
6615
6616 /* Subsequent pages. */
6617 uint32_t iDescriptor = 0;
6618 for (uint32_t i = 1; i < cPages; i++)
6619 {
6620 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
6621 GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6622 else
6623 GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
6624
6625 /* Continuous physical memory? */
6626 if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
6627 {
6628 Assert(paDescs[iDescriptor].numPages);
6629 paDescs[iDescriptor].numPages++;
6630 Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
6631 }
6632 else
6633 {
6634 iDescriptor++;
6635 paDescs[iDescriptor].GCPhys = GCPhys;
6636 paDescs[iDescriptor].numPages = 1;
6637 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
6638 }
6639 }
6640
6641 pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
6642 Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
6643 pGMR->numDescriptors = iDescriptor + 1;
6644 }
6645
6646 if (paNewPage64)
6647 RTMemFree(paNewPage64);
6648}
6649
6650
6651/**
6652 * Free the specified GMR
6653 *
6654 * @param pThisCC The VGA/VMSVGA state for ring-3.
6655 * @param idGMR GMR id
6656 */
6657void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
6658{
6659 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6660
6661 /* Free the old descriptor if present. */
6662 PGMR pGMR = &pSVGAState->paGMR[idGMR];
6663 if ( pGMR->numDescriptors
6664 || pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
6665 {
6666# ifdef DEBUG_GMR_ACCESS
6667 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
6668# endif
6669
6670 Assert(pGMR->paDesc);
6671 RTMemFree(pGMR->paDesc);
6672 pGMR->paDesc = NULL;
6673 pGMR->numDescriptors = 0;
6674 pGMR->cbTotal = 0;
6675 pGMR->cMaxPages = 0;
6676 }
6677 Assert(!pGMR->cMaxPages);
6678 Assert(!pGMR->cbTotal);
6679}
6680#endif /* VBOX_WITH_VMSVGA3D */
6681
6682
6683/**
6684 * Copy between a GMR and a host memory buffer.
6685 *
6686 * @returns VBox status code.
6687 * @param pThis The shared VGA/VMSVGA instance data.
6688 * @param pThisCC The VGA/VMSVGA state for ring-3.
6689 * @param enmTransferType Transfer type (read/write)
6690 * @param pbHstBuf Host buffer pointer (valid)
6691 * @param cbHstBuf Size of host buffer (valid)
6692 * @param offHst Host buffer offset of the first scanline
6693 * @param cbHstPitch Destination buffer pitch
6694 * @param gstPtr GMR description
6695 * @param offGst Guest buffer offset of the first scanline
6696 * @param cbGstPitch Guest buffer pitch
6697 * @param cbWidth Width in bytes to copy
6698 * @param cHeight Number of scanllines to copy
6699 */
6700int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
6701 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
6702 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
6703 uint32_t cbWidth, uint32_t cHeight)
6704{
6705 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6706 PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
6707 int rc;
6708
6709 LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
6710 enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
6711 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6712 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
6713 AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
6714
6715 PGMR pGMR;
6716 uint32_t cbGmr; /* The GMR size in bytes. */
6717 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
6718 {
6719 pGMR = NULL;
6720 cbGmr = pThis->vram_size;
6721 }
6722 else
6723 {
6724 AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
6725 RT_UNTRUSTED_VALIDATED_FENCE();
6726 pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
6727 cbGmr = pGMR->cbTotal;
6728 }
6729
6730 /*
6731 * GMR
6732 */
6733 /* Calculate GMR offset of the data to be copied. */
6734 AssertMsgReturn(gstPtr.offset < cbGmr,
6735 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6736 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6737 VERR_INVALID_PARAMETER);
6738 RT_UNTRUSTED_VALIDATED_FENCE();
6739 AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
6740 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6741 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6742 VERR_INVALID_PARAMETER);
6743 RT_UNTRUSTED_VALIDATED_FENCE();
6744 uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
6745
6746 /* Verify that cbWidth is less than scanline and fits into the GMR. */
6747 uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
6748 AssertMsgReturn(cbGmrScanline != 0,
6749 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6750 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6751 VERR_INVALID_PARAMETER);
6752 RT_UNTRUSTED_VALIDATED_FENCE();
6753 AssertMsgReturn(cbWidth <= cbGmrScanline,
6754 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6755 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6756 VERR_INVALID_PARAMETER);
6757 AssertMsgReturn(cbWidth <= cbGmr - offGmr,
6758 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6759 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6760 VERR_INVALID_PARAMETER);
6761 RT_UNTRUSTED_VALIDATED_FENCE();
6762
6763 /* How many bytes are available for the data in the GMR. */
6764 uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
6765
6766 /* How many scanlines would fit into the available data. */
6767 uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
6768 uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
6769 if (cbWidth <= cbGmrLastScanline)
6770 ++cGmrScanlines;
6771
6772 if (cHeight > cGmrScanlines)
6773 cHeight = cGmrScanlines;
6774
6775 AssertMsgReturn(cHeight > 0,
6776 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6777 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6778 VERR_INVALID_PARAMETER);
6779 RT_UNTRUSTED_VALIDATED_FENCE();
6780
6781 /*
6782 * Host buffer.
6783 */
6784 AssertMsgReturn(offHst < cbHstBuf,
6785 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6786 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6787 VERR_INVALID_PARAMETER);
6788
6789 /* Verify that cbWidth is less than scanline and fits into the buffer. */
6790 uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
6791 AssertMsgReturn(cbHstScanline != 0,
6792 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6793 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6794 VERR_INVALID_PARAMETER);
6795 AssertMsgReturn(cbWidth <= cbHstScanline,
6796 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6797 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6798 VERR_INVALID_PARAMETER);
6799 AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
6800 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6801 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6802 VERR_INVALID_PARAMETER);
6803
6804 /* How many bytes are available for the data in the buffer. */
6805 uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
6806
6807 /* How many scanlines would fit into the available data. */
6808 uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
6809 uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
6810 if (cbWidth <= cbHstLastScanline)
6811 ++cHstScanlines;
6812
6813 if (cHeight > cHstScanlines)
6814 cHeight = cHstScanlines;
6815
6816 AssertMsgReturn(cHeight > 0,
6817 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6818 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6819 VERR_INVALID_PARAMETER);
6820
6821 uint8_t *pbHst = pbHstBuf + offHst;
6822
6823 /* Shortcut for the framebuffer. */
6824 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
6825 {
6826 uint8_t *pbGst = pThisCC->pbVRam + offGmr;
6827
6828 uint8_t const *pbSrc;
6829 int32_t cbSrcPitch;
6830 uint8_t *pbDst;
6831 int32_t cbDstPitch;
6832
6833 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
6834 {
6835 pbSrc = pbHst;
6836 cbSrcPitch = cbHstPitch;
6837 pbDst = pbGst;
6838 cbDstPitch = cbGstPitch;
6839 }
6840 else
6841 {
6842 pbSrc = pbGst;
6843 cbSrcPitch = cbGstPitch;
6844 pbDst = pbHst;
6845 cbDstPitch = cbHstPitch;
6846 }
6847
6848 if ( cbWidth == (uint32_t)cbGstPitch
6849 && cbGstPitch == cbHstPitch)
6850 {
6851 /* Entire scanlines, positive pitch. */
6852 memcpy(pbDst, pbSrc, cbWidth * cHeight);
6853 }
6854 else
6855 {
6856 for (uint32_t i = 0; i < cHeight; ++i)
6857 {
6858 memcpy(pbDst, pbSrc, cbWidth);
6859
6860 pbDst += cbDstPitch;
6861 pbSrc += cbSrcPitch;
6862 }
6863 }
6864 return VINF_SUCCESS;
6865 }
6866
6867 AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
6868 AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
6869
6870 PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
6871 uint32_t iDesc = 0; /* Index in the descriptor array. */
6872 uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
6873 uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
6874 uint8_t *pbHstScanline = pbHst; /* Host address of the scanline which is being copied. */
6875 for (uint32_t i = 0; i < cHeight; ++i)
6876 {
6877 uint32_t cbCurrentWidth = cbWidth;
6878 uint32_t offGmrCurrent = offGmrScanline;
6879 uint8_t *pbCurrentHost = pbHstScanline;
6880
6881 /* Find the right descriptor */
6882 while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
6883 {
6884 offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
6885 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
6886 ++iDesc;
6887 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
6888 }
6889
6890 while (cbCurrentWidth)
6891 {
6892 uint32_t cbToCopy;
6893
6894 if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
6895 {
6896 cbToCopy = cbCurrentWidth;
6897 }
6898 else
6899 {
6900 cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
6901 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
6902 }
6903
6904 RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
6905
6906 Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
6907
6908 /*
6909 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
6910 * guest-side VMSVGA driver seems to allocate non-DMA (physical memory) addresses,
6911 * see @bugref{9654#c75}.
6912 */
6913 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
6914 rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
6915 else
6916 rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
6917 AssertRCBreak(rc);
6918
6919 cbCurrentWidth -= cbToCopy;
6920 offGmrCurrent += cbToCopy;
6921 pbCurrentHost += cbToCopy;
6922
6923 /* Go to the next descriptor if there's anything left. */
6924 if (cbCurrentWidth)
6925 {
6926 offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
6927 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
6928 ++iDesc;
6929 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
6930 }
6931 }
6932
6933 offGmrScanline += cbGstPitch;
6934 pbHstScanline += cbHstPitch;
6935 }
6936
6937 return VINF_SUCCESS;
6938}
6939
6940
6941/**
6942 * Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
6943 *
6944 * @param pSizeSrc Source surface dimensions.
6945 * @param pSizeDest Destination surface dimensions.
6946 * @param pBox Coordinates to be clipped.
6947 */
6948void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox)
6949{
6950 /* Src x, w */
6951 if (pBox->srcx > pSizeSrc->width)
6952 pBox->srcx = pSizeSrc->width;
6953 if (pBox->w > pSizeSrc->width - pBox->srcx)
6954 pBox->w = pSizeSrc->width - pBox->srcx;
6955
6956 /* Src y, h */
6957 if (pBox->srcy > pSizeSrc->height)
6958 pBox->srcy = pSizeSrc->height;
6959 if (pBox->h > pSizeSrc->height - pBox->srcy)
6960 pBox->h = pSizeSrc->height - pBox->srcy;
6961
6962 /* Src z, d */
6963 if (pBox->srcz > pSizeSrc->depth)
6964 pBox->srcz = pSizeSrc->depth;
6965 if (pBox->d > pSizeSrc->depth - pBox->srcz)
6966 pBox->d = pSizeSrc->depth - pBox->srcz;
6967
6968 /* Dest x, w */
6969 if (pBox->x > pSizeDest->width)
6970 pBox->x = pSizeDest->width;
6971 if (pBox->w > pSizeDest->width - pBox->x)
6972 pBox->w = pSizeDest->width - pBox->x;
6973
6974 /* Dest y, h */
6975 if (pBox->y > pSizeDest->height)
6976 pBox->y = pSizeDest->height;
6977 if (pBox->h > pSizeDest->height - pBox->y)
6978 pBox->h = pSizeDest->height - pBox->y;
6979
6980 /* Dest z, d */
6981 if (pBox->z > pSizeDest->depth)
6982 pBox->z = pSizeDest->depth;
6983 if (pBox->d > pSizeDest->depth - pBox->z)
6984 pBox->d = pSizeDest->depth - pBox->z;
6985}
6986
6987
6988/**
6989 * Unsigned coordinates in pBox. Clip to [0; pSize).
6990 *
6991 * @param pSize Source surface dimensions.
6992 * @param pBox Coordinates to be clipped.
6993 */
6994void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox)
6995{
6996 /* x, w */
6997 if (pBox->x > pSize->width)
6998 pBox->x = pSize->width;
6999 if (pBox->w > pSize->width - pBox->x)
7000 pBox->w = pSize->width - pBox->x;
7001
7002 /* y, h */
7003 if (pBox->y > pSize->height)
7004 pBox->y = pSize->height;
7005 if (pBox->h > pSize->height - pBox->y)
7006 pBox->h = pSize->height - pBox->y;
7007
7008 /* z, d */
7009 if (pBox->z > pSize->depth)
7010 pBox->z = pSize->depth;
7011 if (pBox->d > pSize->depth - pBox->z)
7012 pBox->d = pSize->depth - pBox->z;
7013}
7014
7015
7016/**
7017 * Clip.
7018 *
7019 * @param pBound Bounding rectangle.
7020 * @param pRect Rectangle to be clipped.
7021 */
7022void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect)
7023{
7024 int32_t left;
7025 int32_t top;
7026 int32_t right;
7027 int32_t bottom;
7028
7029 /* Right order. */
7030 Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
7031 if (pRect->left < pRect->right)
7032 {
7033 left = pRect->left;
7034 right = pRect->right;
7035 }
7036 else
7037 {
7038 left = pRect->right;
7039 right = pRect->left;
7040 }
7041 if (pRect->top < pRect->bottom)
7042 {
7043 top = pRect->top;
7044 bottom = pRect->bottom;
7045 }
7046 else
7047 {
7048 top = pRect->bottom;
7049 bottom = pRect->top;
7050 }
7051
7052 if (left < pBound->left)
7053 left = pBound->left;
7054 if (right < pBound->left)
7055 right = pBound->left;
7056
7057 if (left > pBound->right)
7058 left = pBound->right;
7059 if (right > pBound->right)
7060 right = pBound->right;
7061
7062 if (top < pBound->top)
7063 top = pBound->top;
7064 if (bottom < pBound->top)
7065 bottom = pBound->top;
7066
7067 if (top > pBound->bottom)
7068 top = pBound->bottom;
7069 if (bottom > pBound->bottom)
7070 bottom = pBound->bottom;
7071
7072 pRect->left = left;
7073 pRect->right = right;
7074 pRect->top = top;
7075 pRect->bottom = bottom;
7076}
7077
7078
7079/**
7080 * Clip.
7081 *
7082 * @param pBound Bounding rectangle.
7083 * @param pRect Rectangle to be clipped.
7084 */
7085void vmsvgaR3Clip3dRect(SVGA3dRect const *pBound, SVGA3dRect RT_UNTRUSTED_GUEST *pRect)
7086{
7087 uint32_t const leftBound = pBound->x;
7088 uint32_t const rightBound = pBound->x + pBound->w;
7089 uint32_t const topBound = pBound->y;
7090 uint32_t const bottomBound = pBound->y + pBound->h;
7091
7092 uint32_t x = pRect->x;
7093 uint32_t y = pRect->y;
7094 uint32_t w = pRect->w;
7095 uint32_t h = pRect->h;
7096
7097 /* Make sure that right and bottom coordinates can be safely computed. */
7098 if (x > rightBound)
7099 x = rightBound;
7100 if (w > rightBound - x)
7101 w = rightBound - x;
7102 if (y > bottomBound)
7103 y = bottomBound;
7104 if (h > bottomBound - y)
7105 h = bottomBound - y;
7106
7107 /* Switch from x, y, w, h to left, top, right, bottom. */
7108 uint32_t left = x;
7109 uint32_t right = x + w;
7110 uint32_t top = y;
7111 uint32_t bottom = y + h;
7112
7113 /* A standard left, right, bottom, top clipping. */
7114 if (left < leftBound)
7115 left = leftBound;
7116 if (right < leftBound)
7117 right = leftBound;
7118
7119 if (left > rightBound)
7120 left = rightBound;
7121 if (right > rightBound)
7122 right = rightBound;
7123
7124 if (top < topBound)
7125 top = topBound;
7126 if (bottom < topBound)
7127 bottom = topBound;
7128
7129 if (top > bottomBound)
7130 top = bottomBound;
7131 if (bottom > bottomBound)
7132 bottom = bottomBound;
7133
7134 /* Back to x, y, w, h representation. */
7135 pRect->x = left;
7136 pRect->y = top;
7137 pRect->w = right - left;
7138 pRect->h = bottom - top;
7139}
7140
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