VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp@ 88831

Last change on this file since 88831 was 88831, checked in by vboxsync, 4 years ago

Devices/Graphics: resource creation; logging; emulate TRIANGLEFAN topology. bugref:9830
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 257.2 KB
Line 
1/* $Id: DevVGA-SVGA-cmd.cpp 88831 2021-05-03 12:37:23Z vboxsync $ */
2/** @file
3 * VMware SVGA device - implementation of VMSVGA commands.
4 */
5
6/*
7 * Copyright (C) 2013-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef IN_RING3
19# error "DevVGA-SVGA-cmd.cpp is only for ring-3 code"
20#endif
21
22
23#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
24#include <iprt/mem.h>
25#include <VBox/AssertGuest.h>
26#include <VBox/log.h>
27#include <VBox/vmm/pdmdev.h>
28#include <VBoxVideo.h>
29
30/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
31#include "DevVGA.h"
32
33/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
34#ifdef VBOX_WITH_VMSVGA3D
35# include "DevVGA-SVGA3d.h"
36#endif
37#include "DevVGA-SVGA-internal.h"
38
39#ifdef DUMP_BITMAPS
40# include <iprt/formats/bmp.h>
41# include <stdio.h>
42#endif
43
44#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
45# define SVGA_CASE_ID2STR(idx) case idx: return #idx
46
47static const char *vmsvgaFifo3dCmdToString(SVGAFifo3dCmdId enmCmdId)
48{
49 switch (enmCmdId)
50 {
51 SVGA_CASE_ID2STR(SVGA_3D_CMD_LEGACY_BASE);
52 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
53 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
54 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
55 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
56 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
57 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
58 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
59 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
60 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
61 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
62 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
63 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
64 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
65 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
66 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
67 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
68 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
69 SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
70 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
71 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
72 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
73 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
74 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
75 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
76 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
77 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
78 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
79 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
80 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
81 SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
82 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
83 SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
84 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD4); /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
85 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD5); /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
86 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD6); /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
87 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD7); /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
88 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD8); /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
89 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD9); /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
90 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD10); /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
91 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD11); /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
92 SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
93 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
94 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
95 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD1);
96 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
97 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD12); /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
98 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD13); /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
99 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD14); /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
100 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD15); /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
101 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD16); /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
102 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD17); /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
103 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
104 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
105 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
106 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
107 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
108 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
109 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
110 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
111 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
112 SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
113 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
114 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
115 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
116 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
117 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
118 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
119 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
120 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
121 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
122 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
123 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
124 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
125 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
126 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
127 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
128 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
129 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
130 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
131 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
132 SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
133 SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
134 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
135 SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
136 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
137 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
138 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
139 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
140 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
141 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
142 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
143 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
144 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
145 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
146 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
147 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
148 SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
149 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
150 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
151 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
152 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
153 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
154 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
155 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
156 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
157 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
158 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
159 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
160 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
161 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
162 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
163 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
164 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
165 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
166 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
167 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
168 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
169 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
170 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
171 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
172 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
173 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
174 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
175 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
176 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
177 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
178 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
179 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
180 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
181 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
182 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
183 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
184 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
185 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
186 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
187 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
188 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
189 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
190 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
191 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
192 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRESENTBLT);
193 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
194 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
195 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
196 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
197 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
198 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
199 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
200 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
201 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
202 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
203 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
204 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
205 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
206 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
207 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
208 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
209 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
210 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
211 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
212 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
213 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
214 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
215 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
216 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
217 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
218 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
219 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
220 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
221 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
222 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
223 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
224 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
225 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
226 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
227 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
228 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
229 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
230 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
231 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
232 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
233 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
234 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
235 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET);
236 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET);
237 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET);
238 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
239 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_COPY);
240 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED1);
241 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2);
242 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED3);
243 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED4);
244 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED5);
245 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED6);
246 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED7);
247 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED8);
248 SVGA_CASE_ID2STR(SVGA_3D_CMD_GROW_OTABLE);
249 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GROW_COTABLE);
250 SVGA_CASE_ID2STR(SVGA_3D_CMD_INTRA_SURFACE_COPY);
251 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V3);
252 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESOLVE_COPY);
253 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_RESOLVE_COPY);
254 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT_REGION);
255 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT);
256 SVGA_CASE_ID2STR(SVGA_3D_CMD_WHOLE_SURFACE_COPY);
257 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_UA_VIEW);
258 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_UA_VIEW);
259 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT);
260 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT);
261 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT);
262 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_UA_VIEWS);
263 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT);
264 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT);
265 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH);
266 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH_INDIRECT);
267 SVGA_CASE_ID2STR(SVGA_3D_CMD_WRITE_ZERO_SURFACE);
268 SVGA_CASE_ID2STR(SVGA_3D_CMD_HINT_ZERO_SURFACE);
269 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER);
270 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT);
271 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
272 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
273 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
274 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
275 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
276 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
277 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_1);
278 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_2);
279 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4);
280 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS);
281 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_MIN_LOD);
282 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_3);
283 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_4);
284 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2);
285 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB);
286 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_IFACE);
287 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT);
288 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS);
289 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER_IFACE);
290 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAX);
291 SVGA_CASE_ID2STR(SVGA_3D_CMD_FUTURE_MAX);
292 }
293 return "UNKNOWN_3D";
294}
295
296/**
297 * FIFO command name lookup
298 *
299 * @returns FIFO command string or "UNKNOWN"
300 * @param u32Cmd FIFO command
301 */
302const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
303{
304 switch (u32Cmd)
305 {
306 SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
307 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
308 SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
309 SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
310 SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
311 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
312 SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
313 SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
314 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
315 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
316 SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
317 SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
318 SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
319 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
320 SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
321 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
322 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
323 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
324 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
325 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
326 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
327 SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
328 SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
329 SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
330 SVGA_CASE_ID2STR(SVGA_CMD_NOP);
331 SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
332 SVGA_CASE_ID2STR(SVGA_CMD_MAX);
333 default:
334 if ( u32Cmd >= SVGA_3D_CMD_BASE
335 && u32Cmd < SVGA_3D_CMD_MAX)
336 return vmsvgaFifo3dCmdToString((SVGAFifo3dCmdId)u32Cmd);
337 }
338 return "UNKNOWN";
339}
340# undef SVGA_CASE_ID2STR
341#endif /* LOG_ENABLED || VBOX_STRICT */
342
343
344/*
345 *
346 * Guest-Backed Objects (GBO).
347 *
348 */
349
350/**
351 * HC access handler for GBOs which require write protection, i.e. OTables, etc.
352 *
353 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
354 * @param pVM VM Handle.
355 * @param pVCpu The cross context CPU structure for the calling EMT.
356 * @param GCPhys The physical address the guest is writing to.
357 * @param pvPhys The HC mapping of that address.
358 * @param pvBuf What the guest is reading/writing.
359 * @param cbBuf How much it's reading/writing.
360 * @param enmAccessType The access type.
361 * @param enmOrigin Who is making the access.
362 * @param pvUser User argument.
363 */
364DECLCALLBACK(VBOXSTRICTRC)
365vmsvgaR3GboAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
366 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
367{
368 RT_NOREF(pVM, pVCpu, pvPhys, enmAccessType);
369
370 if (RT_LIKELY(enmOrigin == PGMACCESSORIGIN_DEVICE || enmOrigin == PGMACCESSORIGIN_DEBUGGER))
371 return VINF_PGM_HANDLER_DO_DEFAULT;
372
373 PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
374 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
375 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
376 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
377
378 /*
379 * The guest is not allowed to access the memory.
380 * Set the error condition.
381 */
382 ASMAtomicWriteBool(&pThis->svga.fBadGuest, true);
383
384 /* Try to find the GBO which the guest is accessing. */
385 char const *pszTarget = NULL;
386 for (uint32_t i = 0; i < RT_ELEMENTS(pSvgaR3State->aGboOTables) && !pszTarget; ++i)
387 {
388 PVMSVGAGBO pGbo = &pSvgaR3State->aGboOTables[i];
389 if (pGbo->cDescriptors)
390 {
391 for (uint32_t j = 0; j < pGbo->cDescriptors; ++j)
392 {
393 if ( GCPhys >= pGbo->paDescriptors[j].GCPhys
394 && GCPhys < pGbo->paDescriptors[j].GCPhys + pGbo->paDescriptors[j].cPages * PAGE_SIZE)
395 {
396 switch (i)
397 {
398 case SVGA_OTABLE_MOB: pszTarget = "SVGA_OTABLE_MOB"; break;
399 case SVGA_OTABLE_SURFACE: pszTarget = "SVGA_OTABLE_SURFACE"; break;
400 case SVGA_OTABLE_CONTEXT: pszTarget = "SVGA_OTABLE_CONTEXT"; break;
401 case SVGA_OTABLE_SHADER: pszTarget = "SVGA_OTABLE_SHADER"; break;
402 case SVGA_OTABLE_SCREENTARGET: pszTarget = "SVGA_OTABLE_SCREENTARGET"; break;
403 case SVGA_OTABLE_DXCONTEXT: pszTarget = "SVGA_OTABLE_DXCONTEXT"; break;
404 default: pszTarget = "Unknown OTABLE"; break;
405 }
406 break;
407 }
408 }
409 }
410 }
411
412 LogRelMax(8, ("VMSVGA: invalid guest access to page %RGp, target %s:\n"
413 "%.*Rhxd\n",
414 GCPhys, pszTarget ? pszTarget : "unknown", RT_MIN(cbBuf, 256), pvBuf));
415
416 return VINF_PGM_HANDLER_DO_DEFAULT;
417}
418
419
420static int vmsvgaR3GboCreate(PVMSVGAR3STATE pSvgaR3State, SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, bool fGCPhys64, bool fWriteProtected, PVMSVGAGBO pGbo)
421{
422 ASSERT_GUEST_RETURN(sizeInBytes <= _128M, VERR_INVALID_PARAMETER); /** @todo Less than SVGA_REG_MOB_MAX_SIZE */
423
424 /*
425 * The 'baseAddress' is a page number and points to the 'root page' of the GBO.
426 * Content of the root page depends on the ptDepth value:
427 * SVGA3D_MOBFMT_PTDEPTH[64]_0 - the only data page;
428 * SVGA3D_MOBFMT_PTDEPTH[64]_1 - array of page numbers for data pages;
429 * SVGA3D_MOBFMT_PTDEPTH[64]_2 - array of page numbers for SVGA3D_MOBFMT_PTDEPTH[64]_1 pages.
430 * The code below extracts the page addresses of the GBO.
431 */
432
433 /* Verify and normalize the ptDepth value. */
434 if (RT_LIKELY( ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0
435 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1
436 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2))
437 ASSERT_GUEST_RETURN(fGCPhys64, VERR_INVALID_PARAMETER);
438 else if ( ptDepth == SVGA3D_MOBFMT_PTDEPTH_0
439 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_1
440 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_2)
441 {
442 ASSERT_GUEST_RETURN(!fGCPhys64, VERR_INVALID_PARAMETER);
443 /* Shift ptDepth to the SVGA3D_MOBFMT_PTDEPTH64_x range. */
444 ptDepth = (SVGAMobFormat)(ptDepth + SVGA3D_MOBFMT_PTDEPTH64_0 - SVGA3D_MOBFMT_PTDEPTH_0);
445 }
446 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
447 { }
448 else
449 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
450
451 uint32_t const cPPNsPerPage = X86_PAGE_SIZE / (fGCPhys64 ? sizeof(PPN64) : sizeof(PPN));
452
453 pGbo->cbTotal = sizeInBytes;
454 pGbo->cTotalPages = (sizeInBytes + X86_PAGE_SIZE - 1) >> X86_PAGE_SHIFT;
455
456 /* Allocate the maximum amount possible (everything non-continuous) */
457 PVMSVGAGBODESCRIPTOR paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAlloc(pGbo->cTotalPages * sizeof(VMSVGAGBODESCRIPTOR));
458 AssertReturn(paDescriptors, VERR_NO_MEMORY);
459
460 int rc = VINF_SUCCESS;
461 if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0)
462 {
463 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages == 1,
464 RTMemFree(paDescriptors),
465 VERR_INVALID_PARAMETER);
466
467 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
468 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
469 paDescriptors[0].GCPhys = GCPhys;
470 paDescriptors[0].cPages = 1;
471 }
472 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1)
473 {
474 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage,
475 RTMemFree(paDescriptors),
476 VERR_INVALID_PARAMETER);
477
478 /* Read the root page. */
479 uint8_t au8RootPage[X86_PAGE_SIZE];
480 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
481 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPage, sizeof(au8RootPage));
482 if (RT_SUCCESS(rc))
483 {
484 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
485 PPN *paPPN32 = (PPN *)&au8RootPage[0];
486 for (uint32_t iPPN = 0; iPPN < pGbo->cTotalPages; ++iPPN)
487 {
488 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
489 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
490 paDescriptors[iPPN].GCPhys = GCPhys;
491 paDescriptors[iPPN].cPages = 1;
492 }
493 }
494 }
495 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2)
496 {
497 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage * cPPNsPerPage,
498 RTMemFree(paDescriptors),
499 VERR_INVALID_PARAMETER);
500
501 /* Read the Level2 root page. */
502 uint8_t au8RootPageLevel2[X86_PAGE_SIZE];
503 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
504 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPageLevel2, sizeof(au8RootPageLevel2));
505 if (RT_SUCCESS(rc))
506 {
507 uint32_t cPagesLeft = pGbo->cTotalPages;
508
509 PPN64 *paPPN64Level2 = (PPN64 *)&au8RootPageLevel2[0];
510 PPN *paPPN32Level2 = (PPN *)&au8RootPageLevel2[0];
511
512 uint32_t const cPPNsLevel2 = (pGbo->cTotalPages + cPPNsPerPage - 1) / cPPNsPerPage;
513 for (uint32_t iPPNLevel2 = 0; iPPNLevel2 < cPPNsLevel2; ++iPPNLevel2)
514 {
515 /* Read the Level1 root page. */
516 uint8_t au8RootPage[X86_PAGE_SIZE];
517 RTGCPHYS GCPhysLevel1 = (RTGCPHYS)(fGCPhys64 ? paPPN64Level2[iPPNLevel2] : paPPN32Level2[iPPNLevel2]) << X86_PAGE_SHIFT;
518 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
519 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhysLevel1, &au8RootPage, sizeof(au8RootPage));
520 if (RT_SUCCESS(rc))
521 {
522 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
523 PPN *paPPN32 = (PPN *)&au8RootPage[0];
524
525 uint32_t const cPPNs = RT_MIN(cPagesLeft, cPPNsPerPage);
526 for (uint32_t iPPN = 0; iPPN < cPPNs; ++iPPN)
527 {
528 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
529 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
530 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].GCPhys = GCPhys;
531 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].cPages = 1;
532 }
533 cPagesLeft -= cPPNs;
534 }
535 }
536 }
537 }
538 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
539 {
540 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
541 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
542 paDescriptors[0].GCPhys = GCPhys;
543 paDescriptors[0].cPages = pGbo->cTotalPages;
544 }
545 else
546 {
547 AssertFailed();
548 return VERR_INTERNAL_ERROR; /* ptDepth should be already verified. */
549 }
550
551 /* Compress the descriptors. */
552 if (ptDepth != SVGA3D_MOBFMT_RANGE)
553 {
554 uint32_t iDescriptor = 0;
555 for (uint32_t i = 1; i < pGbo->cTotalPages; ++i)
556 {
557 /* Continuous physical memory? */
558 if (paDescriptors[i].GCPhys == paDescriptors[iDescriptor].GCPhys + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
559 {
560 Assert(paDescriptors[iDescriptor].cPages);
561 paDescriptors[iDescriptor].cPages++;
562 Log5Func(("Page %x GCPhys=%RGp successor\n", i, paDescriptors[i].GCPhys));
563 }
564 else
565 {
566 iDescriptor++;
567 paDescriptors[iDescriptor].GCPhys = paDescriptors[i].GCPhys;
568 paDescriptors[iDescriptor].cPages = 1;
569 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescriptors[iDescriptor].GCPhys));
570 }
571 }
572
573 pGbo->cDescriptors = iDescriptor + 1;
574 Log5Func(("Nr of descriptors %d\n", pGbo->cDescriptors));
575 }
576 else
577 pGbo->cDescriptors = 1;
578
579 if (RT_LIKELY(pGbo->cDescriptors < pGbo->cTotalPages))
580 {
581 pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemRealloc(paDescriptors, pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
582 AssertReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
583 }
584 else
585 pGbo->paDescriptors = paDescriptors;
586
587#if 1 /// @todo PGMHandlerPhysicalRegister asserts deep in PGM code with enmKind of a page being out of range.
588fWriteProtected = false;
589#endif
590 if (fWriteProtected)
591 {
592 pGbo->fGboFlags |= VMSVGAGBO_F_WRITE_PROTECTED;
593 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
594 {
595 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pSvgaR3State->pDevIns),
596 pGbo->paDescriptors[i].GCPhys, pGbo->paDescriptors[i].GCPhys + pGbo->paDescriptors[i].cPages * PAGE_SIZE - 1,
597 pSvgaR3State->hGboAccessHandlerType, pSvgaR3State->pDevIns, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GBO");
598 AssertRC(rc);
599 }
600 }
601
602 return VINF_SUCCESS;
603}
604
605
606static void vmsvgaR3GboDestroy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
607{
608 if (RT_LIKELY(VMSVGA_IS_GBO_CREATED(pGbo)))
609 {
610 if (pGbo->fGboFlags & VMSVGAGBO_F_WRITE_PROTECTED)
611 {
612 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
613 {
614 int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pSvgaR3State->pDevIns), pGbo->paDescriptors[i].GCPhys);
615 AssertRC(rc);
616 }
617 }
618 RTMemFree(pGbo->paDescriptors);
619 RT_ZERO(pGbo);
620 }
621}
622
623/** @todo static void vmsvgaR3GboWriteProtect(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, bool fWriteProtect) */
624
625typedef enum VMSVGAGboTransferDirection
626{
627 VMSVGAGboTransferDirection_Read,
628 VMSVGAGboTransferDirection_Write,
629} VMSVGAGboTransferDirection;
630
631static int vmsvgaR3GboTransfer(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
632 uint32_t off, void *pvData, uint32_t cbData,
633 VMSVGAGboTransferDirection enmDirection)
634{
635// ASMBreakpoint();
636 int rc = VINF_SUCCESS;
637 uint8_t *pu8CurrentHost = (uint8_t *)pvData;
638
639 /* Find the right descriptor */
640 PCVMSVGAGBODESCRIPTOR const paDescriptors = pGbo->paDescriptors;
641 uint32_t iDescriptor = 0; /* Index in the descriptor array. */
642 uint32_t offDescriptor = 0; /* GMR offset of the current descriptor. */
643 while (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE <= off)
644 {
645 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
646 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
647 ++iDescriptor;
648 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
649 }
650
651 while (cbData)
652 {
653 uint32_t cbToCopy;
654 if (off + cbData <= offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
655 cbToCopy = cbData;
656 else
657 {
658 cbToCopy = (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE - off);
659 AssertReturn(cbToCopy <= cbData, VERR_INVALID_PARAMETER);
660 }
661
662 RTGCPHYS const GCPhys = paDescriptors[iDescriptor].GCPhys + off - offDescriptor;
663 Log5Func(("%s phys=%RGp\n", (enmDirection == VMSVGAGboTransferDirection_Read) ? "READ" : "WRITE", GCPhys));
664
665 /*
666 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
667 * guest-side VMSVGA driver seems to allocate non-DMA (regular physical) addresses,
668 * see @bugref{9654#c75}.
669 */
670 if (enmDirection == VMSVGAGboTransferDirection_Read)
671 rc = PDMDevHlpPhysRead(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
672 else
673 rc = PDMDevHlpPhysWrite(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
674 AssertRCBreak(rc);
675
676 cbData -= cbToCopy;
677 off += cbToCopy;
678 pu8CurrentHost += cbToCopy;
679
680 /* Go to the next descriptor if there's anything left. */
681 if (cbData)
682 {
683 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
684 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR);
685 ++iDescriptor;
686 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
687 }
688 }
689 return rc;
690}
691
692
693static int vmsvgaR3GboWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
694 uint32_t off, void const *pvData, uint32_t cbData)
695{
696 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
697 off, (void *)pvData, cbData,
698 VMSVGAGboTransferDirection_Write);
699}
700
701
702static int vmsvgaR3GboRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
703 uint32_t off, void *pvData, uint32_t cbData)
704{
705 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
706 off, pvData, cbData,
707 VMSVGAGboTransferDirection_Read);
708}
709
710
711static void vmsvgaR3GboBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
712{
713 AssertReturnVoid(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED);
714 vmsvgaR3GboWrite(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
715 RTMemFree(pGbo->pvHost);
716 pGbo->pvHost = NULL;
717 pGbo->fGboFlags &= ~VMSVGAGBO_F_HOST_BACKED;
718}
719
720
721static int vmsvgaR3GboBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, uint32_t cbValid)
722{
723 int rc;
724
725 /* Just reread the data if pvHost has been allocated already. */
726 if (!(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED))
727 pGbo->pvHost = RTMemAllocZ(pGbo->cbTotal);
728
729 if (pGbo->pvHost)
730 {
731 rc = vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, cbValid);
732 }
733 else
734 rc = VERR_NO_MEMORY;
735
736 if (RT_SUCCESS(rc))
737 pGbo->fGboFlags |= VMSVGAGBO_F_HOST_BACKED;
738 else
739 {
740 RTMemFree(pGbo->pvHost);
741 pGbo->pvHost = NULL;
742 }
743 return rc;
744}
745
746
747
748/*
749 *
750 * Object Tables.
751 *
752 */
753
754static int vmsvgaR3OTableVerifyIndex(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
755 uint32_t idx, uint32_t cbEntry)
756{
757 RT_NOREF(pSvgaR3State);
758
759 /* The table must exist and the index must be within the table. */
760 ASSERT_GUEST_RETURN(VMSVGA_IS_GBO_CREATED(pGboOTable), VERR_INVALID_PARAMETER);
761 ASSERT_GUEST_RETURN(idx < pGboOTable->cbTotal / cbEntry, VERR_INVALID_PARAMETER);
762 RT_UNTRUSTED_VALIDATED_FENCE();
763 return VINF_SUCCESS;
764}
765
766
767static int vmsvgaR3OTableRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
768 uint32_t idx, uint32_t cbEntry,
769 void *pvData, uint32_t cbData)
770{
771 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
772
773 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
774 if (RT_SUCCESS(rc))
775 {
776 uint32_t const off = idx * cbEntry;
777 rc = vmsvgaR3GboRead(pSvgaR3State, pGboOTable, off, pvData, cbData);
778 }
779 return rc;
780}
781
782static int vmsvgaR3OTableWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
783 uint32_t idx, uint32_t cbEntry,
784 void const *pvData, uint32_t cbData)
785{
786 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
787
788 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
789 if (RT_SUCCESS(rc))
790 {
791 uint32_t const off = idx * cbEntry;
792 rc = vmsvgaR3GboWrite(pSvgaR3State, pGboOTable, off, pvData, cbData);
793 }
794 return rc;
795}
796
797
798/*
799 *
800 * The guest's Memory OBjects (MOB).
801 *
802 */
803
804static int vmsvgaR3MobCreate(PVMSVGAR3STATE pSvgaR3State,
805 SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, SVGAMobId mobid,
806 bool fGCPhys64, PVMSVGAMOB pMob)
807{
808 RT_ZERO(*pMob);
809
810 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
811 SVGAOTableMobEntry entry;
812 entry.ptDepth = ptDepth;
813 entry.sizeInBytes = sizeInBytes;
814 entry.base = baseAddress;
815 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
816 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
817 if (RT_SUCCESS(rc))
818 {
819 /* Create the corresponding GBO. */
820 rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, fGCPhys64, /* fWriteProtected = */ false, &pMob->Gbo);
821 if (RT_SUCCESS(rc))
822 {
823 /* Add to the tree of known GBOs and the LRU list. */
824 pMob->Core.Key = mobid;
825 if (RTAvlU32Insert(&pSvgaR3State->MOBTree, &pMob->Core))
826 {
827 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
828 return VINF_SUCCESS;
829 }
830
831 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
832 }
833 }
834
835 return rc;
836}
837
838
839static int vmsvgaR3MobDestroy(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
840{
841 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
842 SVGAOTableMobEntry entry;
843 RT_ZERO(entry);
844 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
845 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
846
847 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
848 if (pMob)
849 {
850 RTListNodeRemove(&pMob->nodeLRU);
851 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
852 RTMemFree(pMob);
853 return VINF_SUCCESS;
854 }
855
856 return VERR_INVALID_PARAMETER;
857}
858
859
860static PVMSVGAMOB vmsvgaR3MobGet(PVMSVGAR3STATE pSvgaR3State, SVGAMobId RT_UNTRUSTED_GUEST mobid)
861{
862 if (mobid == SVGA_ID_INVALID)
863 return NULL;
864
865 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Get(&pSvgaR3State->MOBTree, mobid);
866 if (pMob)
867 {
868 /* Move to the head of the LRU list. */
869 RTListNodeRemove(&pMob->nodeLRU);
870 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
871 }
872 else
873 ASSERT_GUEST_FAILED();
874
875 return pMob;
876}
877
878
879/** Create a host ring-3 pointer to the MOB data.
880 * Current approach is to allocate a host memory buffer and copy the guest MOB data if necessary.
881 * @param pSvgaR3State R3 device state.
882 * @param pMob The MOB.
883 * @param cbValid How many bytes of the guest backing memory contain valid data.
884 * @return VBox status.
885 */
886/** @todo uint32_t cbValid -> uint32_t offStart, uint32_t cbData */
887int vmsvgaR3MobBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob, uint32_t cbValid)
888{
889 AssertReturn(pMob, VERR_INVALID_PARAMETER);
890 return vmsvgaR3GboBackingStoreCreate(pSvgaR3State, &pMob->Gbo, cbValid);
891}
892
893
894void vmsvgaR3MobBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
895{
896 if (pMob)
897 vmsvgaR3GboBackingStoreDelete(pSvgaR3State, &pMob->Gbo);
898}
899
900
901void *vmsvgaR3MobBackingStoreGet(PVMSVGAMOB pMob, uint32_t off)
902{
903 if (pMob && (pMob->Gbo.fGboFlags & VMSVGAGBO_F_HOST_BACKED))
904 {
905 if (off <= pMob->Gbo.cbTotal)
906 return (uint8_t *)pMob->Gbo.pvHost + off;
907 }
908 return NULL;
909}
910
911
912#ifdef VBOX_WITH_VMSVGA3D
913int vmsvgaR3UpdateGBSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dSurfaceImageId const *pImageId, SVGA3dBox const *pBox)
914{
915 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
916
917 SVGAOTableSurfaceEntry entrySurface;
918 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
919 pImageId->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
920 if (RT_SUCCESS(rc))
921 {
922 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
923 if (pMob)
924 {
925 VMSVGA3D_MAPPED_SURFACE map;
926 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, idDXContext, pImageId, pBox, VMSVGA3D_SURFACE_MAP_WRITE_DISCARD, &map);
927 if (RT_SUCCESS(rc))
928 {
929 /* Copy MOB -> mapped surface. */
930 uint32_t offSrc = pBox->x * map.cbPixel
931 + pBox->y * entrySurface.size.width * map.cbPixel
932 + pBox->z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
933 uint8_t *pu8Dst = (uint8_t *)map.pvData;
934 for (uint32_t z = 0; z < pBox->d; ++z)
935 {
936 for (uint32_t y = 0; y < pBox->h; ++y)
937 {
938 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pBox->w * map.cbPixel);
939 if (RT_FAILURE(rc))
940 break;
941
942 pu8Dst += map.cbRowPitch;
943 offSrc += entrySurface.size.width * map.cbPixel;
944 }
945
946 pu8Dst += map.cbDepthPitch;
947 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
948 }
949
950 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, pImageId, &map, /* fWritten= */ true);
951 }
952 }
953 else
954 rc = VERR_INVALID_STATE;
955 }
956
957 return rc;
958}
959
960
961int vmsvgaR3UpdateGBSurfaceEx(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dSurfaceImageId const *pImageId, SVGA3dBox const *pBoxDst, SVGA3dPoint const *pPtSrc)
962{
963 /* pPtSrc must be verified by the caller. */
964 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
965
966 SVGAOTableSurfaceEntry entrySurface;
967 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
968 pImageId->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
969 if (RT_SUCCESS(rc))
970 {
971 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
972 if (pMob)
973 {
974 VMSVGA3D_MAPPED_SURFACE map;
975 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, idDXContext, pImageId, pBoxDst, VMSVGA3D_SURFACE_MAP_WRITE_DISCARD, &map);
976 if (RT_SUCCESS(rc))
977 {
978 /* Copy MOB -> mapped surface. */
979 uint32_t offSrc = pPtSrc->x * map.cbPixel
980 + pPtSrc->y * entrySurface.size.width * map.cbPixel
981 + pPtSrc->z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
982 uint8_t *pu8Dst = (uint8_t *)map.pvData;
983 for (uint32_t z = 0; z < pBoxDst->d; ++z)
984 {
985 for (uint32_t y = 0; y < pBoxDst->h; ++y)
986 {
987 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pBoxDst->w * map.cbPixel);
988 if (RT_FAILURE(rc))
989 break;
990
991 pu8Dst += map.cbRowPitch;
992 offSrc += entrySurface.size.width * map.cbPixel;
993 }
994
995 pu8Dst += map.cbDepthPitch;
996 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
997 }
998
999 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, pImageId, &map, /* fWritten= */ true);
1000 }
1001 }
1002 else
1003 rc = VERR_INVALID_STATE;
1004 }
1005
1006 return rc;
1007}
1008#endif /* VBOX_WITH_VMSVGA3D */
1009
1010
1011/*
1012 * Screen objects.
1013 */
1014VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
1015{
1016 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1017 if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
1018 && pSVGAState
1019 && pSVGAState->aScreens[idScreen].fDefined)
1020 {
1021 return &pSVGAState->aScreens[idScreen];
1022 }
1023 return NULL;
1024}
1025
1026void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
1027{
1028#ifdef VBOX_WITH_VMSVGA3D
1029 if (pThis->svga.f3DEnabled)
1030 {
1031 for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
1032 {
1033 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
1034 if (pScreen)
1035 vmsvga3dDestroyScreen(pThisCC, pScreen);
1036 }
1037 }
1038#else
1039 RT_NOREF(pThis, pThisCC);
1040#endif
1041}
1042
1043
1044/**
1045 * Copy a rectangle of pixels within guest VRAM.
1046 */
1047static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1048 uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1049{
1050 if (!width || !height)
1051 return; /* Nothing to do, don't even bother. */
1052
1053 /*
1054 * The guest VRAM (aka GFB) is considered to be a bitmap in the format
1055 * corresponding to the current display mode.
1056 */
1057 uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1058 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1059 uint8_t const *pSrc;
1060 uint8_t *pDst;
1061 unsigned const cbRectWidth = width * cbPixel;
1062 unsigned uMaxOffset;
1063
1064 uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1065 if (uMaxOffset >= cbFrameBuffer)
1066 {
1067 Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1068 return; /* Just don't listen to a bad guest. */
1069 }
1070
1071 pSrc = pDst = pThisCC->pbVRam;
1072 pSrc += srcY * cbScanline + srcX * cbPixel;
1073 pDst += dstY * cbScanline + dstX * cbPixel;
1074
1075 if (srcY >= dstY)
1076 {
1077 /* Source below destination, copy top to bottom. */
1078 for (; height > 0; height--)
1079 {
1080 memmove(pDst, pSrc, cbRectWidth);
1081 pSrc += cbScanline;
1082 pDst += cbScanline;
1083 }
1084 }
1085 else
1086 {
1087 /* Source above destination, copy bottom to top. */
1088 pSrc += cbScanline * (height - 1);
1089 pDst += cbScanline * (height - 1);
1090 for (; height > 0; height--)
1091 {
1092 memmove(pDst, pSrc, cbRectWidth);
1093 pSrc -= cbScanline;
1094 pDst -= cbScanline;
1095 }
1096 }
1097}
1098
1099
1100/**
1101 * Common worker for changing the pointer shape.
1102 *
1103 * @param pThisCC The VGA/VMSVGA state for ring-3.
1104 * @param pSVGAState The VMSVGA ring-3 instance data.
1105 * @param fAlpha Whether there is alpha or not.
1106 * @param xHot Hotspot x coordinate.
1107 * @param yHot Hotspot y coordinate.
1108 * @param cx Width.
1109 * @param cy Height.
1110 * @param pbData Heap copy of the cursor data. Consumed.
1111 * @param cbData The size of the data.
1112 */
1113static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
1114 uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
1115{
1116 LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
1117#ifdef LOG_ENABLED
1118 if (LogIs2Enabled())
1119 {
1120 uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
1121 if (!fAlpha)
1122 {
1123 Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
1124 for (uint32_t y = 0; y < cy; y++)
1125 {
1126 Log2(("%3u:", y));
1127 uint8_t const *pbLine = &pbData[y * cbAndLine];
1128 for (uint32_t x = 0; x < cx; x += 8)
1129 {
1130 uint8_t b = pbLine[x / 8];
1131 char szByte[12];
1132 szByte[0] = b & 0x80 ? '*' : ' '; /* most significant bit first */
1133 szByte[1] = b & 0x40 ? '*' : ' ';
1134 szByte[2] = b & 0x20 ? '*' : ' ';
1135 szByte[3] = b & 0x10 ? '*' : ' ';
1136 szByte[4] = b & 0x08 ? '*' : ' ';
1137 szByte[5] = b & 0x04 ? '*' : ' ';
1138 szByte[6] = b & 0x02 ? '*' : ' ';
1139 szByte[7] = b & 0x01 ? '*' : ' ';
1140 szByte[8] = '\0';
1141 Log2(("%s", szByte));
1142 }
1143 Log2(("\n"));
1144 }
1145 }
1146
1147 Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
1148 uint32_t const *pu32Xor = (uint32_t const *)&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
1149 for (uint32_t y = 0; y < cy; y++)
1150 {
1151 Log2(("%3u:", y));
1152 uint32_t const *pu32Line = &pu32Xor[y * cx];
1153 for (uint32_t x = 0; x < cx; x++)
1154 Log2((" %08x", pu32Line[x]));
1155 Log2(("\n"));
1156 }
1157 }
1158#endif
1159
1160 int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, fAlpha, xHot, yHot, cx, cy, pbData);
1161 AssertRC(rc);
1162
1163 if (pSVGAState->Cursor.fActive)
1164 RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
1165
1166 pSVGAState->Cursor.fActive = true;
1167 pSVGAState->Cursor.xHotspot = xHot;
1168 pSVGAState->Cursor.yHotspot = yHot;
1169 pSVGAState->Cursor.width = cx;
1170 pSVGAState->Cursor.height = cy;
1171 pSVGAState->Cursor.cbData = cbData;
1172 pSVGAState->Cursor.pData = pbData;
1173}
1174
1175
1176#ifdef VBOX_WITH_VMSVGA3D
1177
1178/*
1179 * SVGA_3D_CMD_* handlers.
1180 */
1181
1182
1183/** SVGA_3D_CMD_SURFACE_DEFINE 1040, SVGA_3D_CMD_SURFACE_DEFINE_V2 1070
1184 *
1185 * @param pThisCC The VGA/VMSVGA state for the current context.
1186 * @param pCmd The VMSVGA command.
1187 * @param cMipLevelSizes Number of elements in the paMipLevelSizes array.
1188 * @param paMipLevelSizes Arrays of surface sizes for each face and miplevel.
1189 */
1190static void vmsvga3dCmdDefineSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineSurface_v2 const *pCmd,
1191 uint32_t cMipLevelSizes, SVGA3dSize *paMipLevelSizes)
1192{
1193 ASSERT_GUEST_RETURN_VOID(pCmd->sid < SVGA3D_MAX_SURFACE_IDS);
1194 ASSERT_GUEST_RETURN_VOID(cMipLevelSizes >= 1);
1195 RT_UNTRUSTED_VALIDATED_FENCE();
1196
1197 /* Number of faces (cFaces) is specified as the number of the first non-zero elements in the 'face' array.
1198 * Since only plain surfaces (cFaces == 1) and cubemaps (cFaces == 6) are supported
1199 * (see also SVGA3dCmdDefineSurface definition in svga3d_reg.h), we ignore anything else.
1200 */
1201 uint32_t cRemainingMipLevels = cMipLevelSizes;
1202 uint32_t cFaces = 0;
1203 for (uint32_t i = 0; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1204 {
1205 if (pCmd->face[i].numMipLevels == 0)
1206 break;
1207
1208 /* All SVGA3dSurfaceFace structures must have the same value of numMipLevels field */
1209 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == pCmd->face[0].numMipLevels);
1210
1211 /* numMipLevels value can't be greater than the number of remaining elements in the paMipLevelSizes array. */
1212 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels <= cRemainingMipLevels);
1213 cRemainingMipLevels -= pCmd->face[i].numMipLevels;
1214
1215 ++cFaces;
1216 }
1217 for (uint32_t i = cFaces; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1218 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == 0);
1219
1220 /* cFaces must be 6 for a cubemap and 1 otherwise. */
1221 ASSERT_GUEST_RETURN_VOID(cFaces == (uint32_t)((pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP) ? 6 : 1));
1222
1223 /* Sum of face[i].numMipLevels must be equal to cMipLevels. */
1224 ASSERT_GUEST_RETURN_VOID(cRemainingMipLevels == 0);
1225 RT_UNTRUSTED_VALIDATED_FENCE();
1226
1227 /* Verify paMipLevelSizes */
1228 uint32_t cWidth = paMipLevelSizes[0].width;
1229 uint32_t cHeight = paMipLevelSizes[0].height;
1230 uint32_t cDepth = paMipLevelSizes[0].depth;
1231 for (uint32_t i = 1; i < pCmd->face[0].numMipLevels; ++i)
1232 {
1233 cWidth >>= 1;
1234 if (cWidth == 0) cWidth = 1;
1235 cHeight >>= 1;
1236 if (cHeight == 0) cHeight = 1;
1237 cDepth >>= 1;
1238 if (cDepth == 0) cDepth = 1;
1239 for (uint32_t iFace = 0; iFace < cFaces; ++iFace)
1240 {
1241 uint32_t const iMipLevelSize = iFace * pCmd->face[0].numMipLevels + i;
1242 ASSERT_GUEST_RETURN_VOID( cWidth == paMipLevelSizes[iMipLevelSize].width
1243 && cHeight == paMipLevelSizes[iMipLevelSize].height
1244 && cDepth == paMipLevelSizes[iMipLevelSize].depth);
1245 }
1246 }
1247 RT_UNTRUSTED_VALIDATED_FENCE();
1248
1249 /* Create the surface. */
1250 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1251 pCmd->multisampleCount, pCmd->autogenFilter,
1252 pCmd->face[0].numMipLevels, &paMipLevelSizes[0]);
1253}
1254
1255
1256/* SVGA_3D_CMD_DEFINE_GB_MOB 1093 */
1257static void vmsvga3dCmdDefineGBMob(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob const *pCmd)
1258{
1259 ASMBreakpoint();
1260 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1261
1262 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1263
1264 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1265 /* Allocate a structure for the MOB. */
1266 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1267 AssertPtrReturnVoid(pMob);
1268
1269 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ false, pMob);
1270 if (RT_SUCCESS(rc))
1271 {
1272 return;
1273 }
1274
1275 AssertFailed();
1276
1277 RTMemFree(pMob);
1278}
1279
1280
1281/* SVGA_3D_CMD_DESTROY_GB_MOB 1094 */
1282static void vmsvga3dCmdDestroyGBMob(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBMob const *pCmd)
1283{
1284// ASMBreakpoint();
1285 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1286
1287 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1288
1289 int rc = vmsvgaR3MobDestroy(pSvgaR3State, pCmd->mobid);
1290 if (RT_SUCCESS(rc))
1291 {
1292 return;
1293 }
1294
1295 AssertFailed();
1296}
1297
1298
1299/* SVGA_3D_CMD_DEFINE_GB_SURFACE 1097 */
1300static void vmsvga3dCmdDefineGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface const *pCmd)
1301{
1302// ASMBreakpoint();
1303 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1304
1305 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1306 SVGAOTableSurfaceEntry entry;
1307 RT_ZERO(entry);
1308 entry.format = pCmd->format;
1309 entry.surface1Flags = pCmd->surfaceFlags;
1310 entry.numMipLevels = pCmd->numMipLevels;
1311 entry.multisampleCount = pCmd->multisampleCount;
1312 entry.autogenFilter = pCmd->autogenFilter;
1313 entry.size = pCmd->size;
1314 entry.mobid = SVGA_ID_INVALID;
1315 // entry.arraySize = 0;
1316 // entry.mobPitch = 0;
1317 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1318 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1319 if (RT_SUCCESS(rc))
1320 {
1321 /* Create the host surface. */
1322 /** @todo fGBO = true flag. */
1323 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1324 pCmd->multisampleCount, pCmd->autogenFilter,
1325 pCmd->numMipLevels, &pCmd->size);
1326 }
1327}
1328
1329
1330/* SVGA_3D_CMD_DESTROY_GB_SURFACE 1098 */
1331static void vmsvga3dCmdDestroyGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBSurface const *pCmd)
1332{
1333// ASMBreakpoint();
1334 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1335
1336 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1337 SVGAOTableSurfaceEntry entry;
1338 RT_ZERO(entry);
1339 entry.mobid = SVGA_ID_INVALID;
1340 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1341 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1342
1343 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
1344}
1345
1346
1347/* SVGA_3D_CMD_BIND_GB_SURFACE 1099 */
1348static void vmsvga3dCmdBindGBSurface(PVGASTATECC pThisCC, SVGA3dCmdBindGBSurface const *pCmd)
1349{
1350// ASMBreakpoint();
1351 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1352
1353 /* Assign the mobid to the surface. */
1354 int rc = VINF_SUCCESS;
1355 if (pCmd->mobid != SVGA_ID_INVALID)
1356 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1357 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1358 if (RT_SUCCESS(rc))
1359 {
1360 SVGAOTableSurfaceEntry entry;
1361 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1362 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1363 if (RT_SUCCESS(rc))
1364 {
1365 entry.mobid = pCmd->mobid;
1366 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1367 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1368 if (RT_SUCCESS(rc))
1369 {
1370 /* */
1371 }
1372 }
1373 }
1374}
1375
1376
1377#ifdef DUMP_BITMAPS
1378static int vmsvga3dBmpWrite(const char *pszFilename, VMSVGA3D_MAPPED_SURFACE const *pMap)
1379{
1380 if (pMap->cbPixel != 4)
1381 return VERR_NOT_SUPPORTED;
1382
1383 int const w = pMap->box.w;
1384 int const h = pMap->box.h;
1385
1386 const int cbBitmap = w * h * 4;
1387
1388 FILE *f = fopen(pszFilename, "wb");
1389 if (!f)
1390 return VERR_FILE_NOT_FOUND;
1391
1392 {
1393 BMPFILEHDR fileHdr;
1394 RT_ZERO(fileHdr);
1395 fileHdr.uType = BMP_HDR_MAGIC;
1396 fileHdr.cbFileSize = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR) + cbBitmap;
1397 fileHdr.offBits = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR);
1398
1399 BMPWIN3XINFOHDR coreHdr;
1400 RT_ZERO(coreHdr);
1401 coreHdr.cbSize = sizeof(coreHdr);
1402 coreHdr.uWidth = w;
1403 coreHdr.uHeight = -h;
1404 coreHdr.cPlanes = 1;
1405 coreHdr.cBits = 32;
1406 coreHdr.cbSizeImage = cbBitmap;
1407
1408 fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1409 fwrite(&coreHdr, 1, sizeof(coreHdr), f);
1410 }
1411
1412 if (pMap->cbPixel == 4)
1413 {
1414 const uint8_t *s = (uint8_t *)pMap->pvData;
1415 for (int32_t y = 0; y < h; ++y)
1416 {
1417 fwrite(s, 1, w * pMap->cbPixel, f);
1418
1419 s += pMap->cbRowPitch;
1420 }
1421 }
1422
1423 fclose(f);
1424
1425 return VINF_SUCCESS;
1426}
1427
1428
1429void vmsvga3dMapWriteBmpFile(VMSVGA3D_MAPPED_SURFACE const *pMap, char const *pszPrefix)
1430{
1431 static int idxBitmap = 0;
1432 char *pszFilename = RTStrAPrintf2("bmp\\%s%d.bmp", pszPrefix, idxBitmap++);
1433 int rc = vmsvga3dBmpWrite(pszFilename, pMap);
1434 Log(("WriteBmpFile %s %Rrc\n", pszFilename, rc)); RT_NOREF(rc);
1435 RTStrFree(pszFilename);
1436}
1437#endif /* DUMP_BITMAPS */
1438
1439
1440/* SVGA_3D_CMD_UPDATE_GB_IMAGE 1101 */
1441static void vmsvga3dCmdUpdateGBImage(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdUpdateGBImage const *pCmd)
1442{
1443// ASMBreakpoint();
1444 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1445
1446 LogFlowFunc(("sid=%u @%u,%u,%u %ux%ux%u\n",
1447 pCmd->image.sid, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
1448
1449 /* "update a surface from its backing MOB." */
1450 SVGAOTableSurfaceEntry entrySurface;
1451 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1452 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1453 if (RT_SUCCESS(rc))
1454 {
1455 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1456 if (pMob)
1457 {
1458 VMSVGA3D_MAPPED_SURFACE map;
1459 /** @todo vmsvga3dSurfaceMap */
1460 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, idDXContext, &pCmd->image, &pCmd->box, VMSVGA3D_SURFACE_MAP_WRITE_DISCARD, &map);
1461 if (RT_SUCCESS(rc))
1462 {
1463 /* Copy MOB -> mapped surface. */
1464 uint32_t offSrc = pCmd->box.x * map.cbPixel
1465 + pCmd->box.y * entrySurface.size.width * map.cbPixel
1466 + pCmd->box.z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1467 uint8_t *pu8Dst = (uint8_t *)map.pvData;
1468 for (uint32_t z = 0; z < pCmd->box.d; ++z)
1469 {
1470 for (uint32_t y = 0; y < pCmd->box.h; ++y)
1471 {
1472 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pCmd->box.w * map.cbPixel);
1473 if (RT_FAILURE(rc))
1474 break;
1475
1476 pu8Dst += map.cbRowPitch;
1477 offSrc += entrySurface.size.width * map.cbPixel;
1478 }
1479
1480 pu8Dst += map.cbDepthPitch;
1481 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1482 }
1483
1484 // vmsvga3dMapWriteBmpFile(&map, "Dynamic");
1485
1486 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, &pCmd->image, &map, /* fWritten = */true);
1487 }
1488 }
1489 }
1490}
1491
1492
1493/* SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105 */
1494static void vmsvga3dCmdInvalidateGBImage(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBImage const *pCmd)
1495{
1496// ASMBreakpoint();
1497 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap);
1498}
1499
1500
1501/* SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106 */
1502static void vmsvga3dCmdInvalidateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBSurface const *pCmd)
1503{
1504// ASMBreakpoint();
1505 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, SVGA_ID_INVALID, SVGA_ID_INVALID);
1506}
1507
1508
1509/* SVGA_3D_CMD_SET_OTABLE_BASE64 1115 */
1510static void vmsvga3dCmdSetOTableBase64(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase64 const *pCmd)
1511{
1512 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1513
1514 /*
1515 * Create a GBO for the table.
1516 */
1517 PVMSVGAGBO pGbo;
1518 if (pCmd->type <= RT_ELEMENTS(pSvgaR3State->aGboOTables))
1519 {
1520 RT_UNTRUSTED_VALIDATED_FENCE();
1521 pGbo = &pSvgaR3State->aGboOTables[pCmd->type];
1522 }
1523 else
1524 {
1525 ASSERT_GUEST_FAILED();
1526 pGbo = NULL;
1527 }
1528
1529 if (pGbo)
1530 {
1531 /* Recreate. */
1532 vmsvgaR3GboDestroy(pSvgaR3State, pGbo);
1533 int rc = vmsvgaR3GboCreate(pSvgaR3State, pCmd->ptDepth, pCmd->baseAddress, pCmd->sizeInBytes, /*fGCPhys64=*/ true, /* fWriteProtected = */ true, pGbo);
1534 AssertRC(rc);
1535 }
1536}
1537
1538
1539/* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124 */
1540static void vmsvga3dCmdDefineGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDefineGBScreenTarget const *pCmd)
1541{
1542// ASMBreakpoint();
1543 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1544
1545 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1546 ASSERT_GUEST_RETURN_VOID(pCmd->width > 0 && pCmd->width <= pThis->svga.u32MaxWidth); /* SVGA_REG_SCREENTARGET_MAX_WIDTH */
1547 ASSERT_GUEST_RETURN_VOID(pCmd->height > 0 && pCmd->height <= pThis->svga.u32MaxHeight); /* SVGA_REG_SCREENTARGET_MAX_HEIGHT */
1548 RT_UNTRUSTED_VALIDATED_FENCE();
1549
1550 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1551 SVGAOTableScreenTargetEntry entry;
1552 RT_ZERO(entry);
1553 entry.image.sid = SVGA_ID_INVALID;
1554 // entry.image.face = 0;
1555 // entry.image.mipmap = 0;
1556 entry.width = pCmd->width;
1557 entry.height = pCmd->height;
1558 entry.xRoot = pCmd->xRoot;
1559 entry.yRoot = pCmd->yRoot;
1560 entry.flags = pCmd->flags;
1561 entry.dpi = pCmd->dpi;
1562
1563 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1564 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1565 if (RT_SUCCESS(rc))
1566 {
1567 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1568 /** @todo Generic screen object/target interface. */
1569 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1570 pScreen->fDefined = true;
1571 pScreen->fModified = true;
1572 pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET
1573 | (RT_BOOL(pCmd->flags & SVGA_STFLAG_PRIMARY) ? SVGA_SCREEN_IS_PRIMARY : 0);
1574 pScreen->idScreen = pCmd->stid;
1575
1576 pScreen->xOrigin = pCmd->xRoot;
1577 pScreen->yOrigin = pCmd->yRoot;
1578 pScreen->cWidth = pCmd->width;
1579 pScreen->cHeight = pCmd->height;
1580 pScreen->offVRAM = 0; /* Not applicable for screen targets, they use either a separate memory buffer or a host window. */
1581 pScreen->cbPitch = pCmd->width * 4;
1582 pScreen->cBpp = 32;
1583
1584 if (RT_LIKELY(pThis->svga.f3DEnabled))
1585 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
1586
1587 if (!pScreen->pHwScreen)
1588 {
1589 /* System memory buffer. */
1590 pScreen->pvScreenBitmap = RTMemAllocZ(pScreen->cHeight * pScreen->cbPitch);
1591 }
1592
1593 pThis->svga.fGFBRegisters = false;
1594 vmsvgaR3ChangeMode(pThis, pThisCC);
1595 }
1596}
1597
1598
1599/* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125 */
1600static void vmsvga3dCmdDestroyGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDestroyGBScreenTarget const *pCmd)
1601{
1602// ASMBreakpoint();
1603 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1604
1605 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1606 RT_UNTRUSTED_VALIDATED_FENCE();
1607
1608 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1609 SVGAOTableScreenTargetEntry entry;
1610 RT_ZERO(entry);
1611 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1612 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1613 if (RT_SUCCESS(rc))
1614 {
1615 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1616 /** @todo Generic screen object/target interface. */
1617 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1618 pScreen->fModified = true;
1619 pScreen->fDefined = false;
1620 pScreen->idScreen = pCmd->stid;
1621
1622 if (RT_LIKELY(pThis->svga.f3DEnabled))
1623 vmsvga3dDestroyScreen(pThisCC, pScreen);
1624
1625 vmsvgaR3ChangeMode(pThis, pThisCC);
1626
1627 RTMemFree(pScreen->pvScreenBitmap);
1628 pScreen->pvScreenBitmap = NULL;
1629 }
1630}
1631
1632
1633/* SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126 */
1634static void vmsvga3dCmdBindGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdBindGBScreenTarget const *pCmd)
1635{
1636// ASMBreakpoint();
1637 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1638
1639 /* "Binding a surface to a Screen Target the same as flipping" */
1640
1641 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1642 ASSERT_GUEST_RETURN_VOID(pCmd->image.face == 0 && pCmd->image.mipmap == 0);
1643 RT_UNTRUSTED_VALIDATED_FENCE();
1644
1645 /* Assign the surface to the screen target. */
1646 int rc = VINF_SUCCESS;
1647 if (pCmd->image.sid != SVGA_ID_INVALID)
1648 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1649 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE);
1650 if (RT_SUCCESS(rc))
1651 {
1652 SVGAOTableScreenTargetEntry entry;
1653 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1654 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1655 if (RT_SUCCESS(rc))
1656 {
1657 entry.image = pCmd->image;
1658 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1659 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1660 if (RT_SUCCESS(rc))
1661 {
1662 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1663 rc = pSvgaR3State->pFuncsGBO->pfnScreenTargetBind(pThisCC, pScreen, pCmd->image.sid);
1664 AssertRC(rc);
1665 }
1666 }
1667 }
1668}
1669
1670
1671/* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127 */
1672static void vmsvga3dCmdUpdateGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBScreenTarget const *pCmd)
1673{
1674// ASMBreakpoint();
1675 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1676
1677 /* Update the screen target from its backing surface. */
1678 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1679 RT_UNTRUSTED_VALIDATED_FENCE();
1680
1681 /* Get the screen target info. */
1682 SVGAOTableScreenTargetEntry entryScreenTarget;
1683 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1684 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entryScreenTarget, sizeof(entryScreenTarget));
1685 if (RT_SUCCESS(rc))
1686 {
1687 ASSERT_GUEST_RETURN_VOID(entryScreenTarget.image.face == 0 && entryScreenTarget.image.mipmap == 0);
1688 RT_UNTRUSTED_VALIDATED_FENCE();
1689
1690 if (entryScreenTarget.image.sid != SVGA_ID_INVALID)
1691 {
1692 SVGAOTableSurfaceEntry entrySurface;
1693 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1694 entryScreenTarget.image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1695 if (RT_SUCCESS(rc))
1696 {
1697 /* Copy entrySurface.mobid content to the screen target. */
1698 if (entrySurface.mobid != SVGA_ID_INVALID)
1699 {
1700 RT_UNTRUSTED_VALIDATED_FENCE();
1701 SVGA3dRect targetRect = pCmd->rect;
1702
1703 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1704 if (pScreen->pHwScreen)
1705 {
1706 /* Copy the screen target surface to the backend's screen. */
1707 pSvgaR3State->pFuncsGBO->pfnScreenTargetUpdate(pThisCC, pScreen, &targetRect);
1708 }
1709 else if (pScreen->pvScreenBitmap)
1710 {
1711 /* Copy the screen target surface to the memory buffer. */
1712 VMSVGA3D_MAPPED_SURFACE map;
1713 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, SVGA_ID_INVALID, &entryScreenTarget.image, NULL, VMSVGA3D_SURFACE_MAP_READ, &map);
1714 if (RT_SUCCESS(rc))
1715 {
1716 uint8_t const *pu8Src = (uint8_t *)map.pvData
1717 + targetRect.x * map.cbPixel
1718 + targetRect.y * map.cbRowPitch;
1719 uint8_t *pu8Dst = (uint8_t *)pScreen->pvScreenBitmap
1720 + targetRect.x * map.cbPixel
1721 + targetRect.y * map.box.w * map.cbPixel;
1722 for (uint32_t y = 0; y < targetRect.h; ++y)
1723 {
1724 memcpy(pu8Dst, pu8Src, targetRect.w * map.cbPixel);
1725
1726 pu8Src += map.cbRowPitch;
1727 pu8Dst += map.box.w * map.cbPixel;
1728 }
1729
1730 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, &entryScreenTarget.image, &map, /* fWritten = */ false);
1731
1732 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->rect.x, pCmd->rect.y, pCmd->rect.w, pCmd->rect.h);
1733 }
1734 else
1735 AssertFailed();
1736 }
1737 }
1738 }
1739 }
1740 }
1741}
1742
1743
1744/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134 */
1745static void vmsvga3dCmdDefineGBSurface_v2(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v2 const *pCmd)
1746{
1747//ASMBreakpoint();
1748 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1749
1750 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1751 SVGAOTableSurfaceEntry entry;
1752 RT_ZERO(entry);
1753 entry.format = pCmd->format;
1754 entry.surface1Flags = pCmd->surfaceFlags;
1755 entry.numMipLevels = pCmd->numMipLevels;
1756 entry.multisampleCount = pCmd->multisampleCount;
1757 entry.autogenFilter = pCmd->autogenFilter;
1758 entry.size = pCmd->size;
1759 entry.mobid = SVGA_ID_INVALID;
1760 entry.arraySize = pCmd->arraySize;
1761 // entry.mobPitch = 0;
1762 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1763 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1764 if (RT_SUCCESS(rc))
1765 {
1766 /* Create the host surface. */
1767 /** @todo fGBO = true flag. */
1768 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1769 pCmd->multisampleCount, pCmd->autogenFilter,
1770 pCmd->numMipLevels, &pCmd->size);
1771 }
1772}
1773
1774
1775/* SVGA_3D_CMD_DEFINE_GB_MOB64 1135 */
1776static void vmsvga3dCmdDefineGBMob64(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob64 const *pCmd)
1777{
1778// ASMBreakpoint();
1779 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1780
1781 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1782
1783 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1784 /* Allocate a structure for the MOB. */
1785 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1786 AssertPtrReturnVoid(pMob);
1787
1788 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ true, pMob);
1789 if (RT_SUCCESS(rc))
1790 {
1791 return;
1792 }
1793
1794 RTMemFree(pMob);
1795}
1796
1797
1798/* SVGA_3D_CMD_DX_DEFINE_CONTEXT 1143 */
1799static int vmsvga3dCmdDXDefineContext(PVGASTATECC pThisCC, SVGA3dCmdDXDefineContext const *pCmd, uint32_t cbCmd)
1800{
1801#ifdef VMSVGA3D_DX
1802//ASMBreakpoint();
1803 RT_NOREF(cbCmd);
1804
1805 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1806
1807 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
1808 SVGAOTableDXContextEntry entry;
1809 RT_ZERO(entry);
1810 entry.cid = pCmd->cid;
1811 entry.mobid = SVGA_ID_INVALID;
1812 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1813 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1814 if (RT_SUCCESS(rc))
1815 {
1816 /* Create the host context. */
1817 rc = vmsvga3dDXDefineContext(pThisCC, pCmd->cid);
1818 }
1819
1820 return rc;
1821#else
1822 RT_NOREF(pThisCC, pCmd, cbCmd);
1823 return VERR_NOT_SUPPORTED;
1824#endif
1825}
1826
1827
1828/* SVGA_3D_CMD_DX_DESTROY_CONTEXT 1144 */
1829static int vmsvga3dCmdDXDestroyContext(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyContext const *pCmd, uint32_t cbCmd)
1830{
1831#ifdef VMSVGA3D_DX
1832//ASMBreakpoint();
1833 RT_NOREF(cbCmd);
1834
1835 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1836
1837 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
1838 SVGAOTableDXContextEntry entry;
1839 RT_ZERO(entry);
1840 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1841 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1842
1843 return vmsvga3dDXDestroyContext(pThisCC, pCmd->cid);
1844#else
1845 RT_NOREF(pThisCC, pCmd, cbCmd);
1846 return VERR_NOT_SUPPORTED;
1847#endif
1848}
1849
1850
1851/* SVGA_3D_CMD_DX_BIND_CONTEXT 1145 */
1852static int vmsvga3dCmdDXBindContext(PVGASTATECC pThisCC, SVGA3dCmdDXBindContext const *pCmd, uint32_t cbCmd)
1853{
1854#ifdef VMSVGA3D_DX
1855//ASMBreakpoint();
1856 RT_NOREF(cbCmd);
1857
1858 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1859
1860 /* Assign a mobid to a cid. */
1861 int rc = VINF_SUCCESS;
1862 if (pCmd->mobid != SVGA_ID_INVALID)
1863 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1864 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1865 if (RT_SUCCESS(rc))
1866 {
1867 SVGAOTableDXContextEntry entry;
1868 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1869 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1870 if (RT_SUCCESS(rc))
1871 {
1872 SVGADXContextMobFormat *pSvgaDXContext = NULL;
1873 if (pCmd->mobid != entry.mobid && entry.mobid != SVGA_ID_INVALID)
1874 {
1875 /* Unbind notification to the DX backend. Copy the context data to the guest backing memory. */
1876 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
1877 if (pSvgaDXContext)
1878 {
1879 rc = vmsvga3dDXUnbindContext(pThisCC, pCmd->cid, pSvgaDXContext);
1880 if (RT_SUCCESS(rc))
1881 {
1882 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
1883 if (pMob)
1884 {
1885 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
1886 }
1887 }
1888
1889 RTMemFree(pSvgaDXContext);
1890 pSvgaDXContext = NULL;
1891 }
1892 }
1893
1894 if (pCmd->mobid != SVGA_ID_INVALID)
1895 {
1896 /* Bind a new context. Copy existing data from the guest backing memory. */
1897 if (pCmd->validContents)
1898 {
1899 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
1900 if (pMob)
1901 {
1902 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
1903 if (pSvgaDXContext)
1904 {
1905 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
1906 if (RT_FAILURE(rc))
1907 {
1908 RTMemFree(pSvgaDXContext);
1909 pSvgaDXContext = NULL;
1910 }
1911 }
1912 }
1913 }
1914
1915 rc = vmsvga3dDXBindContext(pThisCC, pCmd->cid, pSvgaDXContext);
1916
1917 RTMemFree(pSvgaDXContext);
1918 }
1919
1920 /* Update the object table. */
1921 entry.mobid = pCmd->mobid;
1922 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1923 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1924 }
1925 }
1926
1927 return rc;
1928#else
1929 RT_NOREF(pThisCC, pCmd, cbCmd);
1930 return VERR_NOT_SUPPORTED;
1931#endif
1932}
1933
1934
1935/* SVGA_3D_CMD_DX_READBACK_CONTEXT 1146 */
1936static int vmsvga3dCmdDXReadbackContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackContext const *pCmd, uint32_t cbCmd)
1937{
1938#ifdef VMSVGA3D_DX
1939ASMBreakpoint();
1940 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1941 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
1942 return vmsvga3dDXReadbackContext(pThisCC, idDXContext);
1943#else
1944 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
1945 return VERR_NOT_SUPPORTED;
1946#endif
1947}
1948
1949
1950/* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT 1147 */
1951static int vmsvga3dCmdDXInvalidateContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateContext const *pCmd, uint32_t cbCmd)
1952{
1953#ifdef VMSVGA3D_DX
1954ASMBreakpoint();
1955 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1956 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
1957 return vmsvga3dDXInvalidateContext(pThisCC, idDXContext);
1958#else
1959 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
1960 return VERR_NOT_SUPPORTED;
1961#endif
1962}
1963
1964
1965/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER 1148 */
1966static int vmsvga3dCmdDXSetSingleConstantBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSingleConstantBuffer const *pCmd, uint32_t cbCmd)
1967{
1968#ifdef VMSVGA3D_DX
1969//ASMBreakpoint();
1970 RT_NOREF(cbCmd);
1971 return vmsvga3dDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd);
1972#else
1973 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
1974 return VERR_NOT_SUPPORTED;
1975#endif
1976}
1977
1978
1979/* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES 1149 */
1980static int vmsvga3dCmdDXSetShaderResources(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderResources const *pCmd, uint32_t cbCmd)
1981{
1982#ifdef VMSVGA3D_DX
1983//ASMBreakpoint();
1984 SVGA3dShaderResourceViewId const *paShaderResourceViewId = (SVGA3dShaderResourceViewId *)&pCmd[1];
1985 uint32_t const cShaderResourceViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dShaderResourceViewId);
1986 return vmsvga3dDXSetShaderResources(pThisCC, idDXContext, pCmd, cShaderResourceViewId, paShaderResourceViewId);
1987#else
1988 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
1989 return VERR_NOT_SUPPORTED;
1990#endif
1991}
1992
1993
1994/* SVGA_3D_CMD_DX_SET_SHADER 1150 */
1995static int vmsvga3dCmdDXSetShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShader const *pCmd, uint32_t cbCmd)
1996{
1997#ifdef VMSVGA3D_DX
1998//ASMBreakpoint();
1999 RT_NOREF(cbCmd);
2000 return vmsvga3dDXSetShader(pThisCC, idDXContext, pCmd);
2001#else
2002 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2003 return VERR_NOT_SUPPORTED;
2004#endif
2005}
2006
2007
2008/* SVGA_3D_CMD_DX_SET_SAMPLERS 1151 */
2009static int vmsvga3dCmdDXSetSamplers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSamplers const *pCmd, uint32_t cbCmd)
2010{
2011#ifdef VMSVGA3D_DX
2012//ASMBreakpoint();
2013 SVGA3dSamplerId const *paSamplerId = (SVGA3dSamplerId *)&pCmd[1];
2014 uint32_t const cSamplerId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSamplerId);
2015 return vmsvga3dDXSetSamplers(pThisCC, idDXContext, pCmd, cSamplerId, paSamplerId);
2016#else
2017 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2018 return VERR_NOT_SUPPORTED;
2019#endif
2020}
2021
2022
2023/* SVGA_3D_CMD_DX_DRAW 1152 */
2024static int vmsvga3dCmdDXDraw(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDraw const *pCmd, uint32_t cbCmd)
2025{
2026#ifdef VMSVGA3D_DX
2027//ASMBreakpoint();
2028 RT_NOREF(cbCmd);
2029 return vmsvga3dDXDraw(pThisCC, idDXContext, pCmd);
2030#else
2031 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2032 return VERR_NOT_SUPPORTED;
2033#endif
2034}
2035
2036
2037/* SVGA_3D_CMD_DX_DRAW_INDEXED 1153 */
2038static int vmsvga3dCmdDXDrawIndexed(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexed const *pCmd, uint32_t cbCmd)
2039{
2040#ifdef VMSVGA3D_DX
2041//ASMBreakpoint();
2042 RT_NOREF(cbCmd);
2043 return vmsvga3dDXDrawIndexed(pThisCC, idDXContext, pCmd);
2044#else
2045 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2046 return VERR_NOT_SUPPORTED;
2047#endif
2048}
2049
2050
2051/* SVGA_3D_CMD_DX_DRAW_INSTANCED 1154 */
2052static int vmsvga3dCmdDXDrawInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstanced const *pCmd, uint32_t cbCmd)
2053{
2054#ifdef VMSVGA3D_DX
2055ASMBreakpoint();
2056 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2057 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2058 return vmsvga3dDXDrawInstanced(pThisCC, idDXContext);
2059#else
2060 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2061 return VERR_NOT_SUPPORTED;
2062#endif
2063}
2064
2065
2066/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED 1155 */
2067static int vmsvga3dCmdDXDrawIndexedInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstanced const *pCmd, uint32_t cbCmd)
2068{
2069#ifdef VMSVGA3D_DX
2070ASMBreakpoint();
2071 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2072 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2073 return vmsvga3dDXDrawIndexedInstanced(pThisCC, idDXContext);
2074#else
2075 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2076 return VERR_NOT_SUPPORTED;
2077#endif
2078}
2079
2080
2081/* SVGA_3D_CMD_DX_DRAW_AUTO 1156 */
2082static int vmsvga3dCmdDXDrawAuto(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawAuto const *pCmd, uint32_t cbCmd)
2083{
2084#ifdef VMSVGA3D_DX
2085ASMBreakpoint();
2086 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2087 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2088 return vmsvga3dDXDrawAuto(pThisCC, idDXContext);
2089#else
2090 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2091 return VERR_NOT_SUPPORTED;
2092#endif
2093}
2094
2095
2096/* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT 1157 */
2097static int vmsvga3dCmdDXSetInputLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetInputLayout const *pCmd, uint32_t cbCmd)
2098{
2099#ifdef VMSVGA3D_DX
2100//ASMBreakpoint();
2101 RT_NOREF(cbCmd);
2102 return vmsvga3dDXSetInputLayout(pThisCC, idDXContext, pCmd->elementLayoutId);
2103#else
2104 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2105 return VERR_NOT_SUPPORTED;
2106#endif
2107}
2108
2109
2110/* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS 1158 */
2111static int vmsvga3dCmdDXSetVertexBuffers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVertexBuffers const *pCmd, uint32_t cbCmd)
2112{
2113#ifdef VMSVGA3D_DX
2114//ASMBreakpoint();
2115 SVGA3dVertexBuffer const *paVertexBuffer = (SVGA3dVertexBuffer *)&pCmd[1];
2116 uint32_t const cVertexBuffer = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dVertexBuffer);
2117 return vmsvga3dDXSetVertexBuffers(pThisCC, idDXContext, pCmd->startBuffer, cVertexBuffer, paVertexBuffer);
2118#else
2119 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2120 return VERR_NOT_SUPPORTED;
2121#endif
2122}
2123
2124
2125/* SVGA_3D_CMD_DX_SET_INDEX_BUFFER 1159 */
2126static int vmsvga3dCmdDXSetIndexBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetIndexBuffer const *pCmd, uint32_t cbCmd)
2127{
2128#ifdef VMSVGA3D_DX
2129//ASMBreakpoint();
2130 RT_NOREF(cbCmd);
2131 return vmsvga3dDXSetIndexBuffer(pThisCC, idDXContext, pCmd);
2132#else
2133 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2134 return VERR_NOT_SUPPORTED;
2135#endif
2136}
2137
2138
2139/* SVGA_3D_CMD_DX_SET_TOPOLOGY 1160 */
2140static int vmsvga3dCmdDXSetTopology(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetTopology const *pCmd, uint32_t cbCmd)
2141{
2142#ifdef VMSVGA3D_DX
2143//ASMBreakpoint();
2144 RT_NOREF(cbCmd);
2145 return vmsvga3dDXSetTopology(pThisCC, idDXContext, pCmd->topology);
2146#else
2147 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2148 return VERR_NOT_SUPPORTED;
2149#endif
2150}
2151
2152
2153/* SVGA_3D_CMD_DX_SET_RENDERTARGETS 1161 */
2154static int vmsvga3dCmdDXSetRenderTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRenderTargets const *pCmd, uint32_t cbCmd)
2155{
2156#ifdef VMSVGA3D_DX
2157//ASMBreakpoint();
2158 SVGA3dRenderTargetViewId const *paRenderTargetViewId = (SVGA3dRenderTargetViewId *)&pCmd[1];
2159 uint32_t const cRenderTargetViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderTargetViewId);
2160 return vmsvga3dDXSetRenderTargets(pThisCC, idDXContext, pCmd->depthStencilViewId, cRenderTargetViewId, paRenderTargetViewId);
2161#else
2162 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2163 return VERR_NOT_SUPPORTED;
2164#endif
2165}
2166
2167
2168/* SVGA_3D_CMD_DX_SET_BLEND_STATE 1162 */
2169static int vmsvga3dCmdDXSetBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetBlendState const *pCmd, uint32_t cbCmd)
2170{
2171#ifdef VMSVGA3D_DX
2172//ASMBreakpoint();
2173 RT_NOREF(cbCmd);
2174 return vmsvga3dDXSetBlendState(pThisCC, idDXContext, pCmd);
2175#else
2176 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2177 return VERR_NOT_SUPPORTED;
2178#endif
2179}
2180
2181
2182/* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE 1163 */
2183static int vmsvga3dCmdDXSetDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDepthStencilState const *pCmd, uint32_t cbCmd)
2184{
2185#ifdef VMSVGA3D_DX
2186//ASMBreakpoint();
2187 RT_NOREF(cbCmd);
2188 return vmsvga3dDXSetDepthStencilState(pThisCC, idDXContext, pCmd);
2189#else
2190 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2191 return VERR_NOT_SUPPORTED;
2192#endif
2193}
2194
2195
2196/* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE 1164 */
2197static int vmsvga3dCmdDXSetRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRasterizerState const *pCmd, uint32_t cbCmd)
2198{
2199#ifdef VMSVGA3D_DX
2200//ASMBreakpoint();
2201 RT_NOREF(cbCmd);
2202 return vmsvga3dDXSetRasterizerState(pThisCC, idDXContext, pCmd->rasterizerId);
2203#else
2204 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2205 return VERR_NOT_SUPPORTED;
2206#endif
2207}
2208
2209
2210/* SVGA_3D_CMD_DX_DEFINE_QUERY 1165 */
2211static int vmsvga3dCmdDXDefineQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineQuery const *pCmd, uint32_t cbCmd)
2212{
2213#ifdef VMSVGA3D_DX
2214ASMBreakpoint();
2215 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2216 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2217 return vmsvga3dDXDefineQuery(pThisCC, idDXContext);
2218#else
2219 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2220 return VERR_NOT_SUPPORTED;
2221#endif
2222}
2223
2224
2225/* SVGA_3D_CMD_DX_DESTROY_QUERY 1166 */
2226static int vmsvga3dCmdDXDestroyQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyQuery const *pCmd, uint32_t cbCmd)
2227{
2228#ifdef VMSVGA3D_DX
2229ASMBreakpoint();
2230 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2231 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2232 return vmsvga3dDXDestroyQuery(pThisCC, idDXContext);
2233#else
2234 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2235 return VERR_NOT_SUPPORTED;
2236#endif
2237}
2238
2239
2240/* SVGA_3D_CMD_DX_BIND_QUERY 1167 */
2241static int vmsvga3dCmdDXBindQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindQuery const *pCmd, uint32_t cbCmd)
2242{
2243#ifdef VMSVGA3D_DX
2244ASMBreakpoint();
2245 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2246 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2247 return vmsvga3dDXBindQuery(pThisCC, idDXContext);
2248#else
2249 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2250 return VERR_NOT_SUPPORTED;
2251#endif
2252}
2253
2254
2255/* SVGA_3D_CMD_DX_SET_QUERY_OFFSET 1168 */
2256static int vmsvga3dCmdDXSetQueryOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetQueryOffset const *pCmd, uint32_t cbCmd)
2257{
2258#ifdef VMSVGA3D_DX
2259ASMBreakpoint();
2260 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2261 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2262 return vmsvga3dDXSetQueryOffset(pThisCC, idDXContext);
2263#else
2264 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2265 return VERR_NOT_SUPPORTED;
2266#endif
2267}
2268
2269
2270/* SVGA_3D_CMD_DX_BEGIN_QUERY 1169 */
2271static int vmsvga3dCmdDXBeginQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBeginQuery const *pCmd, uint32_t cbCmd)
2272{
2273#ifdef VMSVGA3D_DX
2274ASMBreakpoint();
2275 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2276 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2277 return vmsvga3dDXBeginQuery(pThisCC, idDXContext);
2278#else
2279 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2280 return VERR_NOT_SUPPORTED;
2281#endif
2282}
2283
2284
2285/* SVGA_3D_CMD_DX_END_QUERY 1170 */
2286static int vmsvga3dCmdDXEndQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXEndQuery const *pCmd, uint32_t cbCmd)
2287{
2288#ifdef VMSVGA3D_DX
2289ASMBreakpoint();
2290 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2291 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2292 return vmsvga3dDXEndQuery(pThisCC, idDXContext);
2293#else
2294 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2295 return VERR_NOT_SUPPORTED;
2296#endif
2297}
2298
2299
2300/* SVGA_3D_CMD_DX_READBACK_QUERY 1171 */
2301static int vmsvga3dCmdDXReadbackQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackQuery const *pCmd, uint32_t cbCmd)
2302{
2303#ifdef VMSVGA3D_DX
2304ASMBreakpoint();
2305 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2306 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2307 return vmsvga3dDXReadbackQuery(pThisCC, idDXContext);
2308#else
2309 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2310 return VERR_NOT_SUPPORTED;
2311#endif
2312}
2313
2314
2315/* SVGA_3D_CMD_DX_SET_PREDICATION 1172 */
2316static int vmsvga3dCmdDXSetPredication(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPredication const *pCmd, uint32_t cbCmd)
2317{
2318#ifdef VMSVGA3D_DX
2319ASMBreakpoint();
2320 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2321 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2322 return vmsvga3dDXSetPredication(pThisCC, idDXContext);
2323#else
2324 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2325 return VERR_NOT_SUPPORTED;
2326#endif
2327}
2328
2329
2330/* SVGA_3D_CMD_DX_SET_SOTARGETS 1173 */
2331static int vmsvga3dCmdDXSetSOTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSOTargets const *pCmd, uint32_t cbCmd)
2332{
2333#ifdef VMSVGA3D_DX
2334ASMBreakpoint();
2335 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2336 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2337 return vmsvga3dDXSetSOTargets(pThisCC, idDXContext);
2338#else
2339 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2340 return VERR_NOT_SUPPORTED;
2341#endif
2342}
2343
2344
2345/* SVGA_3D_CMD_DX_SET_VIEWPORTS 1174 */
2346static int vmsvga3dCmdDXSetViewports(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetViewports const *pCmd, uint32_t cbCmd)
2347{
2348#ifdef VMSVGA3D_DX
2349//ASMBreakpoint();
2350 SVGA3dViewport const *paViewport = (SVGA3dViewport *)&pCmd[1];
2351 uint32_t const cViewport = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dViewport);
2352 return vmsvga3dDXSetViewports(pThisCC, idDXContext, cViewport, paViewport);
2353#else
2354 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2355 return VERR_NOT_SUPPORTED;
2356#endif
2357}
2358
2359
2360/* SVGA_3D_CMD_DX_SET_SCISSORRECTS 1175 */
2361static int vmsvga3dCmdDXSetScissorRects(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetScissorRects const *pCmd, uint32_t cbCmd)
2362{
2363#ifdef VMSVGA3D_DX
2364//ASMBreakpoint();
2365 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
2366 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
2367 return vmsvga3dDXSetScissorRects(pThisCC, idDXContext, cRect, paRect);
2368#else
2369 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2370 return VERR_NOT_SUPPORTED;
2371#endif
2372}
2373
2374
2375/* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW 1176 */
2376static int vmsvga3dCmdDXClearRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearRenderTargetView const *pCmd, uint32_t cbCmd)
2377{
2378#ifdef VMSVGA3D_DX
2379//ASMBreakpoint();
2380 RT_NOREF(cbCmd);
2381 return vmsvga3dDXClearRenderTargetView(pThisCC, idDXContext, pCmd);
2382#else
2383 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2384 return VERR_NOT_SUPPORTED;
2385#endif
2386}
2387
2388
2389/* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW 1177 */
2390static int vmsvga3dCmdDXClearDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearDepthStencilView const *pCmd, uint32_t cbCmd)
2391{
2392#ifdef VMSVGA3D_DX
2393//ASMBreakpoint();
2394 RT_NOREF(cbCmd);
2395 return vmsvga3dDXClearDepthStencilView(pThisCC, idDXContext, pCmd);
2396#else
2397 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2398 return VERR_NOT_SUPPORTED;
2399#endif
2400}
2401
2402
2403/* SVGA_3D_CMD_DX_PRED_COPY_REGION 1178 */
2404static int vmsvga3dCmdDXPredCopyRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopyRegion const *pCmd, uint32_t cbCmd)
2405{
2406#ifdef VMSVGA3D_DX
2407//ASMBreakpoint();
2408 RT_NOREF(cbCmd);
2409 return vmsvga3dDXPredCopyRegion(pThisCC, idDXContext, pCmd);
2410#else
2411 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2412 return VERR_NOT_SUPPORTED;
2413#endif
2414}
2415
2416
2417/* SVGA_3D_CMD_DX_PRED_COPY 1179 */
2418static int vmsvga3dCmdDXPredCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopy const *pCmd, uint32_t cbCmd)
2419{
2420#ifdef VMSVGA3D_DX
2421ASMBreakpoint();
2422 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2423 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2424 return vmsvga3dDXPredCopy(pThisCC, idDXContext);
2425#else
2426 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2427 return VERR_NOT_SUPPORTED;
2428#endif
2429}
2430
2431
2432/* SVGA_3D_CMD_DX_PRESENTBLT 1180 */
2433static int vmsvga3dCmdDXPresentBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPresentBlt const *pCmd, uint32_t cbCmd)
2434{
2435#ifdef VMSVGA3D_DX
2436ASMBreakpoint();
2437 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2438 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2439 return vmsvga3dDXPresentBlt(pThisCC, idDXContext);
2440#else
2441 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2442 return VERR_NOT_SUPPORTED;
2443#endif
2444}
2445
2446
2447/* SVGA_3D_CMD_DX_GENMIPS 1181 */
2448static int vmsvga3dCmdDXGenMips(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGenMips const *pCmd, uint32_t cbCmd)
2449{
2450#ifdef VMSVGA3D_DX
2451//ASMBreakpoint();
2452 RT_NOREF(cbCmd);
2453 return vmsvga3dDXGenMips(pThisCC, idDXContext, pCmd);
2454#else
2455 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2456 return VERR_NOT_SUPPORTED;
2457#endif
2458}
2459
2460
2461/* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE 1182 */
2462static int vmsvga3dCmdDXUpdateSubResource(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXUpdateSubResource const *pCmd, uint32_t cbCmd)
2463{
2464#ifdef VMSVGA3D_DX
2465ASMBreakpoint();
2466 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2467 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2468 return vmsvga3dDXUpdateSubResource(pThisCC, idDXContext);
2469#else
2470 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2471 return VERR_NOT_SUPPORTED;
2472#endif
2473}
2474
2475
2476/* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE 1183 */
2477static int vmsvga3dCmdDXReadbackSubResource(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackSubResource const *pCmd, uint32_t cbCmd)
2478{
2479#ifdef VMSVGA3D_DX
2480ASMBreakpoint();
2481 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2482 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2483 return vmsvga3dDXReadbackSubResource(pThisCC, idDXContext);
2484#else
2485 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2486 return VERR_NOT_SUPPORTED;
2487#endif
2488}
2489
2490
2491/* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE 1184 */
2492static int vmsvga3dCmdDXInvalidateSubResource(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateSubResource const *pCmd, uint32_t cbCmd)
2493{
2494#ifdef VMSVGA3D_DX
2495ASMBreakpoint();
2496 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2497 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2498 return vmsvga3dDXInvalidateSubResource(pThisCC, idDXContext);
2499#else
2500 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2501 return VERR_NOT_SUPPORTED;
2502#endif
2503}
2504
2505
2506/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW 1185 */
2507static int vmsvga3dCmdDXDefineShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShaderResourceView const *pCmd, uint32_t cbCmd)
2508{
2509#ifdef VMSVGA3D_DX
2510//ASMBreakpoint();
2511 RT_NOREF(cbCmd);
2512 return vmsvga3dDXDefineShaderResourceView(pThisCC, idDXContext, pCmd);
2513#else
2514 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2515 return VERR_NOT_SUPPORTED;
2516#endif
2517}
2518
2519
2520/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW 1186 */
2521static int vmsvga3dCmdDXDestroyShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShaderResourceView const *pCmd, uint32_t cbCmd)
2522{
2523#ifdef VMSVGA3D_DX
2524//ASMBreakpoint();
2525 RT_NOREF(cbCmd);
2526 return vmsvga3dDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd);
2527#else
2528 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2529 return VERR_NOT_SUPPORTED;
2530#endif
2531}
2532
2533
2534/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW 1187 */
2535static int vmsvga3dCmdDXDefineRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRenderTargetView const *pCmd, uint32_t cbCmd)
2536{
2537#ifdef VMSVGA3D_DX
2538//ASMBreakpoint();
2539 RT_NOREF(cbCmd);
2540 return vmsvga3dDXDefineRenderTargetView(pThisCC, idDXContext, pCmd);
2541#else
2542 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2543 return VERR_NOT_SUPPORTED;
2544#endif
2545}
2546
2547
2548/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW 1188 */
2549static int vmsvga3dCmdDXDestroyRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRenderTargetView const *pCmd, uint32_t cbCmd)
2550{
2551#ifdef VMSVGA3D_DX
2552//ASMBreakpoint();
2553 RT_NOREF(cbCmd);
2554 return vmsvga3dDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd);
2555#else
2556 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2557 return VERR_NOT_SUPPORTED;
2558#endif
2559}
2560
2561
2562/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW 1189 */
2563static int vmsvga3dCmdDXDefineDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView const *pCmd, uint32_t cbCmd)
2564{
2565#ifdef VMSVGA3D_DX
2566//ASMBreakpoint();
2567 RT_NOREF(cbCmd);
2568 SVGA3dCmdDXDefineDepthStencilView_v2 cmd;
2569 cmd.depthStencilViewId = pCmd->depthStencilViewId;
2570 cmd.sid = pCmd->sid;
2571 cmd.format = pCmd->format;
2572 cmd.resourceDimension = pCmd->resourceDimension;
2573 cmd.mipSlice = pCmd->mipSlice;
2574 cmd.firstArraySlice = pCmd->firstArraySlice;
2575 cmd.arraySize = pCmd->arraySize;
2576 cmd.flags = 0;
2577 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, &cmd);
2578#else
2579 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2580 return VERR_NOT_SUPPORTED;
2581#endif
2582}
2583
2584
2585/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW 1190 */
2586static int vmsvga3dCmdDXDestroyDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilView const *pCmd, uint32_t cbCmd)
2587{
2588#ifdef VMSVGA3D_DX
2589//ASMBreakpoint();
2590 RT_NOREF(cbCmd);
2591 return vmsvga3dDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd);
2592#else
2593 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2594 return VERR_NOT_SUPPORTED;
2595#endif
2596}
2597
2598
2599/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT 1191 */
2600static int vmsvga3dCmdDXDefineElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineElementLayout const *pCmd, uint32_t cbCmd)
2601{
2602#ifdef VMSVGA3D_DX
2603//ASMBreakpoint();
2604 SVGA3dInputElementDesc const *paDesc = (SVGA3dInputElementDesc *)&pCmd[1];
2605 uint32_t const cDesc = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dInputElementDesc);
2606 return vmsvga3dDXDefineElementLayout(pThisCC, idDXContext, pCmd->elementLayoutId, cDesc, paDesc);
2607#else
2608 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2609 return VERR_NOT_SUPPORTED;
2610#endif
2611}
2612
2613
2614/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT 1192 */
2615static int vmsvga3dCmdDXDestroyElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyElementLayout const *pCmd, uint32_t cbCmd)
2616{
2617#ifdef VMSVGA3D_DX
2618ASMBreakpoint();
2619 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2620 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2621 return vmsvga3dDXDestroyElementLayout(pThisCC, idDXContext);
2622#else
2623 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2624 return VERR_NOT_SUPPORTED;
2625#endif
2626}
2627
2628
2629/* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE 1193 */
2630static int vmsvga3dCmdDXDefineBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineBlendState const *pCmd, uint32_t cbCmd)
2631{
2632#ifdef VMSVGA3D_DX
2633//ASMBreakpoint();
2634 RT_NOREF(cbCmd);
2635 return vmsvga3dDXDefineBlendState(pThisCC, idDXContext, pCmd);
2636#else
2637 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2638 return VERR_NOT_SUPPORTED;
2639#endif
2640}
2641
2642
2643/* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE 1194 */
2644static int vmsvga3dCmdDXDestroyBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyBlendState const *pCmd, uint32_t cbCmd)
2645{
2646#ifdef VMSVGA3D_DX
2647ASMBreakpoint();
2648 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2649 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2650 return vmsvga3dDXDestroyBlendState(pThisCC, idDXContext);
2651#else
2652 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2653 return VERR_NOT_SUPPORTED;
2654#endif
2655}
2656
2657
2658/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE 1195 */
2659static int vmsvga3dCmdDXDefineDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilState const *pCmd, uint32_t cbCmd)
2660{
2661#ifdef VMSVGA3D_DX
2662//ASMBreakpoint();
2663 RT_NOREF(cbCmd);
2664 return vmsvga3dDXDefineDepthStencilState(pThisCC, idDXContext, pCmd);
2665#else
2666 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2667 return VERR_NOT_SUPPORTED;
2668#endif
2669}
2670
2671
2672/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE 1196 */
2673static int vmsvga3dCmdDXDestroyDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilState const *pCmd, uint32_t cbCmd)
2674{
2675#ifdef VMSVGA3D_DX
2676ASMBreakpoint();
2677 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2678 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2679 return vmsvga3dDXDestroyDepthStencilState(pThisCC, idDXContext);
2680#else
2681 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2682 return VERR_NOT_SUPPORTED;
2683#endif
2684}
2685
2686
2687/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE 1197 */
2688static int vmsvga3dCmdDXDefineRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRasterizerState const *pCmd, uint32_t cbCmd)
2689{
2690#ifdef VMSVGA3D_DX
2691//ASMBreakpoint();
2692 RT_NOREF(cbCmd);
2693 return vmsvga3dDXDefineRasterizerState(pThisCC, idDXContext, pCmd);
2694#else
2695 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2696 return VERR_NOT_SUPPORTED;
2697#endif
2698}
2699
2700
2701/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE 1198 */
2702static int vmsvga3dCmdDXDestroyRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRasterizerState const *pCmd, uint32_t cbCmd)
2703{
2704#ifdef VMSVGA3D_DX
2705ASMBreakpoint();
2706 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2707 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2708 return vmsvga3dDXDestroyRasterizerState(pThisCC, idDXContext);
2709#else
2710 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2711 return VERR_NOT_SUPPORTED;
2712#endif
2713}
2714
2715
2716/* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE 1199 */
2717static int vmsvga3dCmdDXDefineSamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineSamplerState const *pCmd, uint32_t cbCmd)
2718{
2719#ifdef VMSVGA3D_DX
2720//ASMBreakpoint();
2721 RT_NOREF(cbCmd);
2722 return vmsvga3dDXDefineSamplerState(pThisCC, idDXContext, pCmd);
2723#else
2724 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2725 return VERR_NOT_SUPPORTED;
2726#endif
2727}
2728
2729
2730/* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE 1200 */
2731static int vmsvga3dCmdDXDestroySamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroySamplerState const *pCmd, uint32_t cbCmd)
2732{
2733#ifdef VMSVGA3D_DX
2734ASMBreakpoint();
2735 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2736 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2737 return vmsvga3dDXDestroySamplerState(pThisCC, idDXContext);
2738#else
2739 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2740 return VERR_NOT_SUPPORTED;
2741#endif
2742}
2743
2744
2745/* SVGA_3D_CMD_DX_DEFINE_SHADER 1201 */
2746static int vmsvga3dCmdDXDefineShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShader const *pCmd, uint32_t cbCmd)
2747{
2748#ifdef VMSVGA3D_DX
2749//ASMBreakpoint();
2750 RT_NOREF(cbCmd);
2751 return vmsvga3dDXDefineShader(pThisCC, idDXContext, pCmd);
2752#else
2753 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2754 return VERR_NOT_SUPPORTED;
2755#endif
2756}
2757
2758
2759/* SVGA_3D_CMD_DX_DESTROY_SHADER 1202 */
2760static int vmsvga3dCmdDXDestroyShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShader const *pCmd, uint32_t cbCmd)
2761{
2762#ifdef VMSVGA3D_DX
2763ASMBreakpoint();
2764 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2765 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2766 return vmsvga3dDXDestroyShader(pThisCC, idDXContext);
2767#else
2768 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2769 return VERR_NOT_SUPPORTED;
2770#endif
2771}
2772
2773
2774/* SVGA_3D_CMD_DX_BIND_SHADER 1203 */
2775static int vmsvga3dCmdDXBindShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShader const *pCmd, uint32_t cbCmd)
2776{
2777#ifdef VMSVGA3D_DX
2778//ASMBreakpoint();
2779 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2780 RT_NOREF(cbCmd);
2781 ASSERT_GUEST_LOGREL_MSG(idDXContext == pCmd->cid, ("idDXContext = %u, pCmd->cid = %u\n", idDXContext, pCmd->cid));
2782 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
2783 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2784 return vmsvga3dDXBindShader(pThisCC, pCmd->cid, pMob, pCmd->shid, pCmd->offsetInBytes);
2785#else
2786 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2787 return VERR_NOT_SUPPORTED;
2788#endif
2789}
2790
2791
2792/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT 1204 */
2793static int vmsvga3dCmdDXDefineStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutput const *pCmd, uint32_t cbCmd)
2794{
2795#ifdef VMSVGA3D_DX
2796ASMBreakpoint();
2797 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2798 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2799 return vmsvga3dDXDefineStreamOutput(pThisCC, idDXContext);
2800#else
2801 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2802 return VERR_NOT_SUPPORTED;
2803#endif
2804}
2805
2806
2807/* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT 1205 */
2808static int vmsvga3dCmdDXDestroyStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyStreamOutput const *pCmd, uint32_t cbCmd)
2809{
2810#ifdef VMSVGA3D_DX
2811ASMBreakpoint();
2812 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2813 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2814 return vmsvga3dDXDestroyStreamOutput(pThisCC, idDXContext);
2815#else
2816 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2817 return VERR_NOT_SUPPORTED;
2818#endif
2819}
2820
2821
2822/* SVGA_3D_CMD_DX_SET_STREAMOUTPUT 1206 */
2823static int vmsvga3dCmdDXSetStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStreamOutput const *pCmd, uint32_t cbCmd)
2824{
2825#ifdef VMSVGA3D_DX
2826ASMBreakpoint();
2827 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2828 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2829 return vmsvga3dDXSetStreamOutput(pThisCC, idDXContext);
2830#else
2831 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2832 return VERR_NOT_SUPPORTED;
2833#endif
2834}
2835
2836
2837/* SVGA_3D_CMD_DX_SET_COTABLE 1207 */
2838static int vmsvga3dCmdDXSetCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXSetCOTable const *pCmd, uint32_t cbCmd)
2839{
2840#ifdef VMSVGA3D_DX
2841//ASMBreakpoint();
2842 RT_NOREF(cbCmd);
2843 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2844 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
2845 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2846 return vmsvga3dDXSetCOTable(pThisCC, pCmd->cid, pMob, pCmd->type, pCmd->validSizeInBytes);
2847#else
2848 RT_NOREF(pThisCC, pCmd, cbCmd);
2849 return VERR_NOT_SUPPORTED;
2850#endif
2851}
2852
2853
2854/* SVGA_3D_CMD_DX_READBACK_COTABLE 1208 */
2855static int vmsvga3dCmdDXReadbackCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackCOTable const *pCmd, uint32_t cbCmd)
2856{
2857#ifdef VMSVGA3D_DX
2858ASMBreakpoint();
2859 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2860 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2861 return vmsvga3dDXReadbackCOTable(pThisCC, idDXContext);
2862#else
2863 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2864 return VERR_NOT_SUPPORTED;
2865#endif
2866}
2867
2868
2869/* SVGA_3D_CMD_DX_BUFFER_COPY 1209 */
2870static int vmsvga3dCmdDXBufferCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferCopy const *pCmd, uint32_t cbCmd)
2871{
2872#ifdef VMSVGA3D_DX
2873ASMBreakpoint();
2874 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2875 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2876 return vmsvga3dDXBufferCopy(pThisCC, idDXContext);
2877#else
2878 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2879 return VERR_NOT_SUPPORTED;
2880#endif
2881}
2882
2883
2884/* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER 1210 */
2885static int vmsvga3dCmdDXTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferFromBuffer const *pCmd, uint32_t cbCmd)
2886{
2887#ifdef VMSVGA3D_DX
2888ASMBreakpoint();
2889 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2890 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2891 return vmsvga3dDXTransferFromBuffer(pThisCC, idDXContext);
2892#else
2893 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2894 return VERR_NOT_SUPPORTED;
2895#endif
2896}
2897
2898
2899/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK 1211 */
2900static int vmsvga3dCmdDXSurfaceCopyAndReadback(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSurfaceCopyAndReadback const *pCmd, uint32_t cbCmd)
2901{
2902#ifdef VMSVGA3D_DX
2903ASMBreakpoint();
2904 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2905 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2906 return vmsvga3dDXSurfaceCopyAndReadback(pThisCC, idDXContext);
2907#else
2908 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2909 return VERR_NOT_SUPPORTED;
2910#endif
2911}
2912
2913
2914/* SVGA_3D_CMD_DX_MOVE_QUERY 1212 */
2915static int vmsvga3dCmdDXMoveQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMoveQuery const *pCmd, uint32_t cbCmd)
2916{
2917#ifdef VMSVGA3D_DX
2918ASMBreakpoint();
2919 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2920 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2921 return vmsvga3dDXMoveQuery(pThisCC, idDXContext);
2922#else
2923 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2924 return VERR_NOT_SUPPORTED;
2925#endif
2926}
2927
2928
2929/* SVGA_3D_CMD_DX_BIND_ALL_QUERY 1213 */
2930static int vmsvga3dCmdDXBindAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllQuery const *pCmd, uint32_t cbCmd)
2931{
2932#ifdef VMSVGA3D_DX
2933ASMBreakpoint();
2934 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2935 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2936 return vmsvga3dDXBindAllQuery(pThisCC, idDXContext);
2937#else
2938 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2939 return VERR_NOT_SUPPORTED;
2940#endif
2941}
2942
2943
2944/* SVGA_3D_CMD_DX_READBACK_ALL_QUERY 1214 */
2945static int vmsvga3dCmdDXReadbackAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackAllQuery const *pCmd, uint32_t cbCmd)
2946{
2947#ifdef VMSVGA3D_DX
2948ASMBreakpoint();
2949 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2950 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2951 return vmsvga3dDXReadbackAllQuery(pThisCC, idDXContext);
2952#else
2953 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2954 return VERR_NOT_SUPPORTED;
2955#endif
2956}
2957
2958
2959/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER 1215 */
2960static int vmsvga3dCmdDXPredTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredTransferFromBuffer const *pCmd, uint32_t cbCmd)
2961{
2962#ifdef VMSVGA3D_DX
2963ASMBreakpoint();
2964 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2965 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2966 return vmsvga3dDXPredTransferFromBuffer(pThisCC, idDXContext);
2967#else
2968 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2969 return VERR_NOT_SUPPORTED;
2970#endif
2971}
2972
2973
2974/* SVGA_3D_CMD_DX_MOB_FENCE_64 1216 */
2975static int vmsvga3dCmdDXMobFence64(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMobFence64 const *pCmd, uint32_t cbCmd)
2976{
2977#ifdef VMSVGA3D_DX
2978ASMBreakpoint();
2979 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2980 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2981 return vmsvga3dDXMobFence64(pThisCC, idDXContext);
2982#else
2983 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2984 return VERR_NOT_SUPPORTED;
2985#endif
2986}
2987
2988
2989/* SVGA_3D_CMD_DX_BIND_ALL_SHADER 1217 */
2990static int vmsvga3dCmdDXBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllShader const *pCmd, uint32_t cbCmd)
2991{
2992#ifdef VMSVGA3D_DX
2993ASMBreakpoint();
2994 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2995 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2996 return vmsvga3dDXBindAllShader(pThisCC, idDXContext);
2997#else
2998 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2999 return VERR_NOT_SUPPORTED;
3000#endif
3001}
3002
3003
3004/* SVGA_3D_CMD_DX_HINT 1218 */
3005static int vmsvga3dCmdDXHint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXHint const *pCmd, uint32_t cbCmd)
3006{
3007#ifdef VMSVGA3D_DX
3008ASMBreakpoint();
3009 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3010 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3011 return vmsvga3dDXHint(pThisCC, idDXContext);
3012#else
3013 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3014 return VERR_NOT_SUPPORTED;
3015#endif
3016}
3017
3018
3019/* SVGA_3D_CMD_DX_BUFFER_UPDATE 1219 */
3020static int vmsvga3dCmdDXBufferUpdate(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferUpdate const *pCmd, uint32_t cbCmd)
3021{
3022#ifdef VMSVGA3D_DX
3023ASMBreakpoint();
3024 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3025 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3026 return vmsvga3dDXBufferUpdate(pThisCC, idDXContext);
3027#else
3028 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3029 return VERR_NOT_SUPPORTED;
3030#endif
3031}
3032
3033
3034/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET 1220 */
3035static int vmsvga3dCmdDXSetVSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3036{
3037#ifdef VMSVGA3D_DX
3038ASMBreakpoint();
3039 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3040 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3041 return vmsvga3dDXSetVSConstantBufferOffset(pThisCC, idDXContext);
3042#else
3043 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3044 return VERR_NOT_SUPPORTED;
3045#endif
3046}
3047
3048
3049/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET 1221 */
3050static int vmsvga3dCmdDXSetPSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3051{
3052#ifdef VMSVGA3D_DX
3053ASMBreakpoint();
3054 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3055 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3056 return vmsvga3dDXSetPSConstantBufferOffset(pThisCC, idDXContext);
3057#else
3058 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3059 return VERR_NOT_SUPPORTED;
3060#endif
3061}
3062
3063
3064/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET 1222 */
3065static int vmsvga3dCmdDXSetGSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetGSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3066{
3067#ifdef VMSVGA3D_DX
3068ASMBreakpoint();
3069 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3070 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3071 return vmsvga3dDXSetGSConstantBufferOffset(pThisCC, idDXContext);
3072#else
3073 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3074 return VERR_NOT_SUPPORTED;
3075#endif
3076}
3077
3078
3079/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET 1223 */
3080static int vmsvga3dCmdDXSetHSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetHSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3081{
3082#ifdef VMSVGA3D_DX
3083ASMBreakpoint();
3084 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3085 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3086 return vmsvga3dDXSetHSConstantBufferOffset(pThisCC, idDXContext);
3087#else
3088 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3089 return VERR_NOT_SUPPORTED;
3090#endif
3091}
3092
3093
3094/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET 1224 */
3095static int vmsvga3dCmdDXSetDSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3096{
3097#ifdef VMSVGA3D_DX
3098ASMBreakpoint();
3099 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3100 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3101 return vmsvga3dDXSetDSConstantBufferOffset(pThisCC, idDXContext);
3102#else
3103 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3104 return VERR_NOT_SUPPORTED;
3105#endif
3106}
3107
3108
3109/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET 1225 */
3110static int vmsvga3dCmdDXSetCSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3111{
3112#ifdef VMSVGA3D_DX
3113ASMBreakpoint();
3114 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3115 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3116 return vmsvga3dDXSetCSConstantBufferOffset(pThisCC, idDXContext);
3117#else
3118 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3119 return VERR_NOT_SUPPORTED;
3120#endif
3121}
3122
3123
3124/* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER 1226 */
3125static int vmsvga3dCmdDXCondBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCondBindAllShader const *pCmd, uint32_t cbCmd)
3126{
3127#ifdef VMSVGA3D_DX
3128ASMBreakpoint();
3129 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3130 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3131 return vmsvga3dDXCondBindAllShader(pThisCC, idDXContext);
3132#else
3133 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3134 return VERR_NOT_SUPPORTED;
3135#endif
3136}
3137
3138
3139/* SVGA_3D_CMD_SCREEN_COPY 1227 */
3140static int vmsvga3dCmdScreenCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdScreenCopy const *pCmd, uint32_t cbCmd)
3141{
3142#ifdef VMSVGA3D_DX
3143ASMBreakpoint();
3144 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3145 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3146 return vmsvga3dScreenCopy(pThisCC, idDXContext);
3147#else
3148 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3149 return VERR_NOT_SUPPORTED;
3150#endif
3151}
3152
3153
3154/* SVGA_3D_CMD_GROW_OTABLE 1236 */
3155static int vmsvga3dCmdGrowOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdGrowOTable const *pCmd, uint32_t cbCmd)
3156{
3157#ifdef VMSVGA3D_DX
3158ASMBreakpoint();
3159 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3160 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3161 return vmsvga3dGrowOTable(pThisCC, idDXContext);
3162#else
3163 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3164 return VERR_NOT_SUPPORTED;
3165#endif
3166}
3167
3168
3169/* SVGA_3D_CMD_DX_GROW_COTABLE 1237 */
3170static int vmsvga3dCmdDXGrowCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGrowCOTable const *pCmd, uint32_t cbCmd)
3171{
3172#ifdef VMSVGA3D_DX
3173ASMBreakpoint();
3174 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3175 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3176 return vmsvga3dDXGrowCOTable(pThisCC, idDXContext);
3177#else
3178 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3179 return VERR_NOT_SUPPORTED;
3180#endif
3181}
3182
3183
3184/* SVGA_3D_CMD_INTRA_SURFACE_COPY 1238 */
3185static int vmsvga3dCmdIntraSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdIntraSurfaceCopy const *pCmd, uint32_t cbCmd)
3186{
3187#ifdef VMSVGA3D_DX
3188ASMBreakpoint();
3189 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3190 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3191 return vmsvga3dIntraSurfaceCopy(pThisCC, idDXContext);
3192#else
3193 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3194 return VERR_NOT_SUPPORTED;
3195#endif
3196}
3197
3198
3199/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 1239 */
3200static int vmsvga3dCmdDefineGBSurface_v3(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v3 const *pCmd, uint32_t cbCmd)
3201{
3202#ifdef VMSVGA3D_DX
3203ASMBreakpoint();
3204 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3205 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3206 return vmsvga3dDefineGBSurface_v3(pThisCC, idDXContext);
3207#else
3208 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3209 return VERR_NOT_SUPPORTED;
3210#endif
3211}
3212
3213
3214/* SVGA_3D_CMD_DX_RESOLVE_COPY 1240 */
3215static int vmsvga3dCmdDXResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXResolveCopy const *pCmd, uint32_t cbCmd)
3216{
3217#ifdef VMSVGA3D_DX
3218ASMBreakpoint();
3219 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3220 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3221 return vmsvga3dDXResolveCopy(pThisCC, idDXContext);
3222#else
3223 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3224 return VERR_NOT_SUPPORTED;
3225#endif
3226}
3227
3228
3229/* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY 1241 */
3230static int vmsvga3dCmdDXPredResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredResolveCopy const *pCmd, uint32_t cbCmd)
3231{
3232#ifdef VMSVGA3D_DX
3233ASMBreakpoint();
3234 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3235 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3236 return vmsvga3dDXPredResolveCopy(pThisCC, idDXContext);
3237#else
3238 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3239 return VERR_NOT_SUPPORTED;
3240#endif
3241}
3242
3243
3244/* SVGA_3D_CMD_DX_PRED_CONVERT_REGION 1242 */
3245static int vmsvga3dCmdDXPredConvertRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvertRegion const *pCmd, uint32_t cbCmd)
3246{
3247#ifdef VMSVGA3D_DX
3248ASMBreakpoint();
3249 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3250 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3251 return vmsvga3dDXPredConvertRegion(pThisCC, idDXContext);
3252#else
3253 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3254 return VERR_NOT_SUPPORTED;
3255#endif
3256}
3257
3258
3259/* SVGA_3D_CMD_DX_PRED_CONVERT 1243 */
3260static int vmsvga3dCmdDXPredConvert(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvert const *pCmd, uint32_t cbCmd)
3261{
3262#ifdef VMSVGA3D_DX
3263ASMBreakpoint();
3264 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3265 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3266 return vmsvga3dDXPredConvert(pThisCC, idDXContext);
3267#else
3268 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3269 return VERR_NOT_SUPPORTED;
3270#endif
3271}
3272
3273
3274/* SVGA_3D_CMD_WHOLE_SURFACE_COPY 1244 */
3275static int vmsvga3dCmdWholeSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWholeSurfaceCopy const *pCmd, uint32_t cbCmd)
3276{
3277#ifdef VMSVGA3D_DX
3278ASMBreakpoint();
3279 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3280 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3281 return vmsvga3dWholeSurfaceCopy(pThisCC, idDXContext);
3282#else
3283 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3284 return VERR_NOT_SUPPORTED;
3285#endif
3286}
3287
3288
3289/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW 1245 */
3290static int vmsvga3dCmdDXDefineUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineUAView const *pCmd, uint32_t cbCmd)
3291{
3292#ifdef VMSVGA3D_DX
3293ASMBreakpoint();
3294 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3295 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3296 return vmsvga3dDXDefineUAView(pThisCC, idDXContext);
3297#else
3298 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3299 return VERR_NOT_SUPPORTED;
3300#endif
3301}
3302
3303
3304/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW 1246 */
3305static int vmsvga3dCmdDXDestroyUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyUAView const *pCmd, uint32_t cbCmd)
3306{
3307#ifdef VMSVGA3D_DX
3308ASMBreakpoint();
3309 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3310 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3311 return vmsvga3dDXDestroyUAView(pThisCC, idDXContext);
3312#else
3313 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3314 return VERR_NOT_SUPPORTED;
3315#endif
3316}
3317
3318
3319/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT 1247 */
3320static int vmsvga3dCmdDXClearUAViewUint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewUint const *pCmd, uint32_t cbCmd)
3321{
3322#ifdef VMSVGA3D_DX
3323ASMBreakpoint();
3324 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3325 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3326 return vmsvga3dDXClearUAViewUint(pThisCC, idDXContext);
3327#else
3328 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3329 return VERR_NOT_SUPPORTED;
3330#endif
3331}
3332
3333
3334/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT 1248 */
3335static int vmsvga3dCmdDXClearUAViewFloat(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewFloat const *pCmd, uint32_t cbCmd)
3336{
3337#ifdef VMSVGA3D_DX
3338ASMBreakpoint();
3339 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3340 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3341 return vmsvga3dDXClearUAViewFloat(pThisCC, idDXContext);
3342#else
3343 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3344 return VERR_NOT_SUPPORTED;
3345#endif
3346}
3347
3348
3349/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT 1249 */
3350static int vmsvga3dCmdDXCopyStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCopyStructureCount const *pCmd, uint32_t cbCmd)
3351{
3352#ifdef VMSVGA3D_DX
3353ASMBreakpoint();
3354 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3355 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3356 return vmsvga3dDXCopyStructureCount(pThisCC, idDXContext);
3357#else
3358 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3359 return VERR_NOT_SUPPORTED;
3360#endif
3361}
3362
3363
3364/* SVGA_3D_CMD_DX_SET_UA_VIEWS 1250 */
3365static int vmsvga3dCmdDXSetUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetUAViews const *pCmd, uint32_t cbCmd)
3366{
3367#ifdef VMSVGA3D_DX
3368ASMBreakpoint();
3369 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3370 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3371 return vmsvga3dDXSetUAViews(pThisCC, idDXContext);
3372#else
3373 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3374 return VERR_NOT_SUPPORTED;
3375#endif
3376}
3377
3378
3379/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT 1251 */
3380static int vmsvga3dCmdDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd, uint32_t cbCmd)
3381{
3382#ifdef VMSVGA3D_DX
3383ASMBreakpoint();
3384 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3385 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3386 return vmsvga3dDXDrawIndexedInstancedIndirect(pThisCC, idDXContext);
3387#else
3388 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3389 return VERR_NOT_SUPPORTED;
3390#endif
3391}
3392
3393
3394/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT 1252 */
3395static int vmsvga3dCmdDXDrawInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstancedIndirect const *pCmd, uint32_t cbCmd)
3396{
3397#ifdef VMSVGA3D_DX
3398ASMBreakpoint();
3399 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3400 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3401 return vmsvga3dDXDrawInstancedIndirect(pThisCC, idDXContext);
3402#else
3403 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3404 return VERR_NOT_SUPPORTED;
3405#endif
3406}
3407
3408
3409/* SVGA_3D_CMD_DX_DISPATCH 1253 */
3410static int vmsvga3dCmdDXDispatch(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatch const *pCmd, uint32_t cbCmd)
3411{
3412#ifdef VMSVGA3D_DX
3413ASMBreakpoint();
3414 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3415 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3416 return vmsvga3dDXDispatch(pThisCC, idDXContext);
3417#else
3418 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3419 return VERR_NOT_SUPPORTED;
3420#endif
3421}
3422
3423
3424/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT 1254 */
3425static int vmsvga3dCmdDXDispatchIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatchIndirect const *pCmd, uint32_t cbCmd)
3426{
3427#ifdef VMSVGA3D_DX
3428ASMBreakpoint();
3429 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3430 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3431 return vmsvga3dDXDispatchIndirect(pThisCC, idDXContext);
3432#else
3433 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3434 return VERR_NOT_SUPPORTED;
3435#endif
3436}
3437
3438
3439/* SVGA_3D_CMD_WRITE_ZERO_SURFACE 1255 */
3440static int vmsvga3dCmdWriteZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWriteZeroSurface const *pCmd, uint32_t cbCmd)
3441{
3442#ifdef VMSVGA3D_DX
3443ASMBreakpoint();
3444 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3445 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3446 return vmsvga3dWriteZeroSurface(pThisCC, idDXContext);
3447#else
3448 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3449 return VERR_NOT_SUPPORTED;
3450#endif
3451}
3452
3453
3454/* SVGA_3D_CMD_HINT_ZERO_SURFACE 1256 */
3455static int vmsvga3dCmdHintZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdHintZeroSurface const *pCmd, uint32_t cbCmd)
3456{
3457#ifdef VMSVGA3D_DX
3458ASMBreakpoint();
3459 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3460 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3461 return vmsvga3dHintZeroSurface(pThisCC, idDXContext);
3462#else
3463 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3464 return VERR_NOT_SUPPORTED;
3465#endif
3466}
3467
3468
3469/* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER 1257 */
3470static int vmsvga3dCmdDXTransferToBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferToBuffer const *pCmd, uint32_t cbCmd)
3471{
3472#ifdef VMSVGA3D_DX
3473ASMBreakpoint();
3474 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3475 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3476 return vmsvga3dDXTransferToBuffer(pThisCC, idDXContext);
3477#else
3478 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3479 return VERR_NOT_SUPPORTED;
3480#endif
3481}
3482
3483
3484/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT 1258 */
3485static int vmsvga3dCmdDXSetStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStructureCount const *pCmd, uint32_t cbCmd)
3486{
3487#ifdef VMSVGA3D_DX
3488ASMBreakpoint();
3489 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3490 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3491 return vmsvga3dDXSetStructureCount(pThisCC, idDXContext);
3492#else
3493 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3494 return VERR_NOT_SUPPORTED;
3495#endif
3496}
3497
3498
3499/* SVGA_3D_CMD_LOGICOPS_BITBLT 1259 */
3500static int vmsvga3dCmdLogicOpsBitBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsBitBlt const *pCmd, uint32_t cbCmd)
3501{
3502#ifdef VMSVGA3D_DX
3503ASMBreakpoint();
3504 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3505 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3506 return vmsvga3dLogicOpsBitBlt(pThisCC, idDXContext);
3507#else
3508 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3509 return VERR_NOT_SUPPORTED;
3510#endif
3511}
3512
3513
3514/* SVGA_3D_CMD_LOGICOPS_TRANSBLT 1260 */
3515static int vmsvga3dCmdLogicOpsTransBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsTransBlt const *pCmd, uint32_t cbCmd)
3516{
3517#ifdef VMSVGA3D_DX
3518ASMBreakpoint();
3519 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3520 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3521 return vmsvga3dLogicOpsTransBlt(pThisCC, idDXContext);
3522#else
3523 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3524 return VERR_NOT_SUPPORTED;
3525#endif
3526}
3527
3528
3529/* SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1261 */
3530static int vmsvga3dCmdLogicOpsStretchBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsStretchBlt const *pCmd, uint32_t cbCmd)
3531{
3532#ifdef VMSVGA3D_DX
3533ASMBreakpoint();
3534 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3535 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3536 return vmsvga3dLogicOpsStretchBlt(pThisCC, idDXContext);
3537#else
3538 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3539 return VERR_NOT_SUPPORTED;
3540#endif
3541}
3542
3543
3544/* SVGA_3D_CMD_LOGICOPS_COLORFILL 1262 */
3545static int vmsvga3dCmdLogicOpsColorFill(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsColorFill const *pCmd, uint32_t cbCmd)
3546{
3547#ifdef VMSVGA3D_DX
3548ASMBreakpoint();
3549 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3550 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3551 return vmsvga3dLogicOpsColorFill(pThisCC, idDXContext);
3552#else
3553 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3554 return VERR_NOT_SUPPORTED;
3555#endif
3556}
3557
3558
3559/* SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1263 */
3560static int vmsvga3dCmdLogicOpsAlphaBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsAlphaBlend const *pCmd, uint32_t cbCmd)
3561{
3562#ifdef VMSVGA3D_DX
3563ASMBreakpoint();
3564 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3565 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3566 return vmsvga3dLogicOpsAlphaBlend(pThisCC, idDXContext);
3567#else
3568 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3569 return VERR_NOT_SUPPORTED;
3570#endif
3571}
3572
3573
3574/* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1264 */
3575static int vmsvga3dCmdLogicOpsClearTypeBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsClearTypeBlend const *pCmd, uint32_t cbCmd)
3576{
3577#ifdef VMSVGA3D_DX
3578ASMBreakpoint();
3579 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3580 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3581 return vmsvga3dLogicOpsClearTypeBlend(pThisCC, idDXContext);
3582#else
3583 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3584 return VERR_NOT_SUPPORTED;
3585#endif
3586}
3587
3588
3589/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 1267 */
3590static int vmsvga3dCmdDefineGBSurface_v4(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v4 const *pCmd, uint32_t cbCmd)
3591{
3592#ifdef VMSVGA3D_DX
3593ASMBreakpoint();
3594 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3595 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3596 return vmsvga3dDefineGBSurface_v4(pThisCC, idDXContext);
3597#else
3598 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3599 return VERR_NOT_SUPPORTED;
3600#endif
3601}
3602
3603
3604/* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS 1268 */
3605static int vmsvga3dCmdDXSetCSUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSUAViews const *pCmd, uint32_t cbCmd)
3606{
3607#ifdef VMSVGA3D_DX
3608ASMBreakpoint();
3609 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3610 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3611 return vmsvga3dDXSetCSUAViews(pThisCC, idDXContext);
3612#else
3613 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3614 return VERR_NOT_SUPPORTED;
3615#endif
3616}
3617
3618
3619/* SVGA_3D_CMD_DX_SET_MIN_LOD 1269 */
3620static int vmsvga3dCmdDXSetMinLOD(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetMinLOD const *pCmd, uint32_t cbCmd)
3621{
3622#ifdef VMSVGA3D_DX
3623ASMBreakpoint();
3624 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3625 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3626 return vmsvga3dDXSetMinLOD(pThisCC, idDXContext);
3627#else
3628 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3629 return VERR_NOT_SUPPORTED;
3630#endif
3631}
3632
3633
3634/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 1272 */
3635static int vmsvga3dCmdDXDefineDepthStencilView_v2(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd, uint32_t cbCmd)
3636{
3637#ifdef VMSVGA3D_DX
3638//ASMBreakpoint();
3639 RT_NOREF(cbCmd);
3640 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, pCmd);
3641#else
3642 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3643 return VERR_NOT_SUPPORTED;
3644#endif
3645}
3646
3647
3648/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB 1273 */
3649static int vmsvga3dCmdDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd, uint32_t cbCmd)
3650{
3651#ifdef VMSVGA3D_DX
3652ASMBreakpoint();
3653 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3654 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3655 return vmsvga3dDXDefineStreamOutputWithMob(pThisCC, idDXContext);
3656#else
3657 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3658 return VERR_NOT_SUPPORTED;
3659#endif
3660}
3661
3662
3663/* SVGA_3D_CMD_DX_SET_SHADER_IFACE 1274 */
3664static int vmsvga3dCmdDXSetShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderIface const *pCmd, uint32_t cbCmd)
3665{
3666#ifdef VMSVGA3D_DX
3667ASMBreakpoint();
3668 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3669 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3670 return vmsvga3dDXSetShaderIface(pThisCC, idDXContext);
3671#else
3672 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3673 return VERR_NOT_SUPPORTED;
3674#endif
3675}
3676
3677
3678/* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT 1275 */
3679static int vmsvga3dCmdDXBindStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindStreamOutput const *pCmd, uint32_t cbCmd)
3680{
3681#ifdef VMSVGA3D_DX
3682ASMBreakpoint();
3683 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3684 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3685 return vmsvga3dDXBindStreamOutput(pThisCC, idDXContext);
3686#else
3687 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3688 return VERR_NOT_SUPPORTED;
3689#endif
3690}
3691
3692
3693/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS 1276 */
3694static int vmsvga3dCmdSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdSurfaceStretchBltNonMSToMS const *pCmd, uint32_t cbCmd)
3695{
3696#ifdef VMSVGA3D_DX
3697ASMBreakpoint();
3698 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3699 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3700 return vmsvga3dSurfaceStretchBltNonMSToMS(pThisCC, idDXContext);
3701#else
3702 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3703 return VERR_NOT_SUPPORTED;
3704#endif
3705}
3706
3707
3708/* SVGA_3D_CMD_DX_BIND_SHADER_IFACE 1277 */
3709static int vmsvga3dCmdDXBindShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShaderIface const *pCmd, uint32_t cbCmd)
3710{
3711#ifdef VMSVGA3D_DX
3712ASMBreakpoint();
3713 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3714 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3715 return vmsvga3dDXBindShaderIface(pThisCC, idDXContext);
3716#else
3717 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3718 return VERR_NOT_SUPPORTED;
3719#endif
3720}
3721
3722
3723/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
3724 * Check that the 3D command has at least a_cbMin of payload bytes after the
3725 * header. Will break out of the switch if it doesn't.
3726 */
3727# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3728 if (1) { \
3729 AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
3730 RT_UNTRUSTED_VALIDATED_FENCE(); \
3731 } else do {} while (0)
3732
3733# define VMSVGA_3D_CMD_NOTIMPL() \
3734 if (1) { \
3735 AssertMsgFailed(("Not implemented %d %s\n", enmCmdId, vmsvgaR3FifoCmdToString(enmCmdId))); \
3736 } else do {} while (0)
3737
3738/** SVGA_3D_CMD_* handler.
3739 * This function parses the command and calls the corresponding command handler.
3740 *
3741 * @param pThis The shared VGA/VMSVGA state.
3742 * @param pThisCC The VGA/VMSVGA state for the current context.
3743 * @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
3744 * @param enmCmdId SVGA_3D_CMD_* command identifier.
3745 * @param cbCmd Size of the command in bytes.
3746 * @param pvCmd Pointer to the command.
3747 * @returns VBox status code if an error was detected parsing a command.
3748 */
3749int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, SVGAFifo3dCmdId enmCmdId, uint32_t cbCmd, void const *pvCmd)
3750{
3751 if (enmCmdId > SVGA_3D_CMD_MAX)
3752 {
3753 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
3754 ASSERT_GUEST_FAILED_RETURN(VERR_NOT_IMPLEMENTED);
3755 }
3756
3757 int rcParse = VINF_SUCCESS;
3758 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
3759
3760 switch (enmCmdId)
3761 {
3762 case SVGA_3D_CMD_SURFACE_DEFINE:
3763 {
3764 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)pvCmd;
3765 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3766 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefine);
3767
3768 SVGA3dCmdDefineSurface_v2 cmd;
3769 cmd.sid = pCmd->sid;
3770 cmd.surfaceFlags = pCmd->surfaceFlags;
3771 cmd.format = pCmd->format;
3772 memcpy(cmd.face, pCmd->face, sizeof(cmd.face));
3773 cmd.multisampleCount = 0;
3774 cmd.autogenFilter = SVGA3D_TEX_FILTER_NONE;
3775
3776 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3777 vmsvga3dCmdDefineSurface(pThisCC, &cmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
3778# ifdef DEBUG_GMR_ACCESS
3779 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
3780# endif
3781 break;
3782 }
3783
3784 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3785 {
3786 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)pvCmd;
3787 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3788 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefineV2);
3789
3790 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3791 vmsvga3dCmdDefineSurface(pThisCC, pCmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
3792# ifdef DEBUG_GMR_ACCESS
3793 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
3794# endif
3795 break;
3796 }
3797
3798 case SVGA_3D_CMD_SURFACE_DESTROY:
3799 {
3800 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)pvCmd;
3801 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3802 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDestroy);
3803
3804 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
3805 break;
3806 }
3807
3808 case SVGA_3D_CMD_SURFACE_COPY:
3809 {
3810 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)pvCmd;
3811 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3812 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceCopy);
3813
3814 uint32_t const cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3815 vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3816 break;
3817 }
3818
3819 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3820 {
3821 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)pvCmd;
3822 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3823 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceStretchBlt);
3824
3825 vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
3826 &pCmd->src, &pCmd->boxSrc, pCmd->mode);
3827 break;
3828 }
3829
3830 case SVGA_3D_CMD_SURFACE_DMA:
3831 {
3832 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)pvCmd;
3833 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3834 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDma);
3835
3836 uint64_t u64NanoTS = 0;
3837 if (LogRelIs3Enabled())
3838 u64NanoTS = RTTimeNanoTS();
3839 uint32_t const cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3840 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
3841 vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
3842 cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3843 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
3844 if (LogRelIs3Enabled())
3845 {
3846 if (cCopyBoxes)
3847 {
3848 SVGA3dCopyBox *pFirstBox = (SVGA3dCopyBox *)(pCmd + 1);
3849 LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
3850 (RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
3851 pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
3852 pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
3853 }
3854 }
3855 break;
3856 }
3857
3858 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3859 {
3860 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)pvCmd;
3861 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3862 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceScreen);
3863
3864 static uint64_t u64FrameStartNanoTS = 0;
3865 static uint64_t u64ElapsedPerSecNano = 0;
3866 static int cFrames = 0;
3867 uint64_t u64NanoTS = 0;
3868 if (LogRelIs3Enabled())
3869 u64NanoTS = RTTimeNanoTS();
3870 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3871 STAM_REL_PROFILE_START(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
3872 vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
3873 pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3874 STAM_REL_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
3875 if (LogRelIs3Enabled())
3876 {
3877 uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
3878 u64ElapsedPerSecNano += u64ElapsedNano;
3879
3880 SVGASignedRect *pFirstRect = cRects ? (SVGASignedRect *)(pCmd + 1) : &pCmd->destRect;
3881 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
3882 (u64ElapsedNano) / 1000ULL, cRects,
3883 pFirstRect->left, pFirstRect->top,
3884 pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
3885
3886 ++cFrames;
3887 if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
3888 {
3889 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
3890 cFrames, u64ElapsedPerSecNano / 1000ULL));
3891 u64FrameStartNanoTS = u64NanoTS;
3892 cFrames = 0;
3893 u64ElapsedPerSecNano = 0;
3894 }
3895 }
3896 break;
3897 }
3898
3899 case SVGA_3D_CMD_CONTEXT_DEFINE:
3900 {
3901 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)pvCmd;
3902 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3903 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDefine);
3904
3905 vmsvga3dContextDefine(pThisCC, pCmd->cid);
3906 break;
3907 }
3908
3909 case SVGA_3D_CMD_CONTEXT_DESTROY:
3910 {
3911 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)pvCmd;
3912 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3913 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDestroy);
3914
3915 vmsvga3dContextDestroy(pThisCC, pCmd->cid);
3916 break;
3917 }
3918
3919 case SVGA_3D_CMD_SETTRANSFORM:
3920 {
3921 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)pvCmd;
3922 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3923 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTransform);
3924
3925 vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
3926 break;
3927 }
3928
3929 case SVGA_3D_CMD_SETZRANGE:
3930 {
3931 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)pvCmd;
3932 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3933 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetZRange);
3934
3935 vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
3936 break;
3937 }
3938
3939 case SVGA_3D_CMD_SETRENDERSTATE:
3940 {
3941 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)pvCmd;
3942 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3943 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderState);
3944
3945 uint32_t const cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3946 vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3947 break;
3948 }
3949
3950 case SVGA_3D_CMD_SETRENDERTARGET:
3951 {
3952 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)pvCmd;
3953 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3954 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderTarget);
3955
3956 vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
3957 break;
3958 }
3959
3960 case SVGA_3D_CMD_SETTEXTURESTATE:
3961 {
3962 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)pvCmd;
3963 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3964 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTextureState);
3965
3966 uint32_t const cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3967 vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3968 break;
3969 }
3970
3971 case SVGA_3D_CMD_SETMATERIAL:
3972 {
3973 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)pvCmd;
3974 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3975 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetMaterial);
3976
3977 vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
3978 break;
3979 }
3980
3981 case SVGA_3D_CMD_SETLIGHTDATA:
3982 {
3983 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)pvCmd;
3984 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3985 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightData);
3986
3987 vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
3988 break;
3989 }
3990
3991 case SVGA_3D_CMD_SETLIGHTENABLED:
3992 {
3993 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)pvCmd;
3994 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3995 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightEnable);
3996
3997 vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
3998 break;
3999 }
4000
4001 case SVGA_3D_CMD_SETVIEWPORT:
4002 {
4003 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)pvCmd;
4004 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4005 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetViewPort);
4006
4007 vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4008 break;
4009 }
4010
4011 case SVGA_3D_CMD_SETCLIPPLANE:
4012 {
4013 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)pvCmd;
4014 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4015 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetClipPlane);
4016
4017 vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4018 break;
4019 }
4020
4021 case SVGA_3D_CMD_CLEAR:
4022 {
4023 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)pvCmd;
4024 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4025 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dClear);
4026
4027 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4028 vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4029 break;
4030 }
4031
4032 case SVGA_3D_CMD_PRESENT:
4033 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4034 {
4035 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)pvCmd;
4036 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4037 if (enmCmdId == SVGA_3D_CMD_PRESENT)
4038 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent);
4039 else
4040 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresentReadBack);
4041
4042 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4043 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4044 vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4045 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4046 break;
4047 }
4048
4049 case SVGA_3D_CMD_SHADER_DEFINE:
4050 {
4051 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)pvCmd;
4052 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4053 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDefine);
4054
4055 uint32_t const cbData = (cbCmd - sizeof(*pCmd));
4056 vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4057 break;
4058 }
4059
4060 case SVGA_3D_CMD_SHADER_DESTROY:
4061 {
4062 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)pvCmd;
4063 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4064 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDestroy);
4065
4066 vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4067 break;
4068 }
4069
4070 case SVGA_3D_CMD_SET_SHADER:
4071 {
4072 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)pvCmd;
4073 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4074 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShader);
4075
4076 vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4077 break;
4078 }
4079
4080 case SVGA_3D_CMD_SET_SHADER_CONST:
4081 {
4082 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)pvCmd;
4083 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4084 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShaderConst);
4085
4086 uint32_t const cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4087 vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4088 break;
4089 }
4090
4091 case SVGA_3D_CMD_DRAW_PRIMITIVES:
4092 {
4093 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)pvCmd;
4094 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4095 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDrawPrimitives);
4096
4097 ASSERT_GUEST_STMT_BREAK(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES, rcParse = VERR_INVALID_PARAMETER);
4098 ASSERT_GUEST_STMT_BREAK(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS, rcParse = VERR_INVALID_PARAMETER);
4099 uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4100 + pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4101 ASSERT_GUEST_STMT_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd), rcParse = VERR_INVALID_PARAMETER);
4102
4103 uint32_t const cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4104 ASSERT_GUEST_STMT_BREAK(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls, rcParse = VERR_INVALID_PARAMETER);
4105 RT_UNTRUSTED_VALIDATED_FENCE();
4106
4107 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
4108 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *)&pVertexDecl[pCmd->numVertexDecls];
4109 SVGA3dVertexDivisor *pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor *)&pNumRange[pCmd->numRanges] : NULL;
4110
4111 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4112 vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4113 pNumRange, cVertexDivisor, pVertexDivisor);
4114 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4115 break;
4116 }
4117
4118 case SVGA_3D_CMD_SETSCISSORRECT:
4119 {
4120 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)pvCmd;
4121 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4122 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetScissorRect);
4123
4124 vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4125 break;
4126 }
4127
4128 case SVGA_3D_CMD_BEGIN_QUERY:
4129 {
4130 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)pvCmd;
4131 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4132 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dBeginQuery);
4133
4134 vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4135 break;
4136 }
4137
4138 case SVGA_3D_CMD_END_QUERY:
4139 {
4140 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)pvCmd;
4141 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4142 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dEndQuery);
4143
4144 vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4145 break;
4146 }
4147
4148 case SVGA_3D_CMD_WAIT_FOR_QUERY:
4149 {
4150 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)pvCmd;
4151 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4152 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dWaitForQuery);
4153
4154 vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4155 break;
4156 }
4157
4158 case SVGA_3D_CMD_GENERATE_MIPMAPS:
4159 {
4160 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)pvCmd;
4161 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4162 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dGenerateMipmaps);
4163
4164 vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4165 break;
4166 }
4167
4168 case SVGA_3D_CMD_ACTIVATE_SURFACE:
4169 /* context id + surface id? */
4170 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dActivateSurface);
4171 break;
4172
4173 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4174 /* context id + surface id? */
4175 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDeactivateSurface);
4176 break;
4177
4178 /*
4179 *
4180 * VPGU10: SVGA_CAP_GBOBJECTS+ commands.
4181 *
4182 */
4183 case SVGA_3D_CMD_SCREEN_DMA:
4184 {
4185 SVGA3dCmdScreenDMA *pCmd = (SVGA3dCmdScreenDMA *)pvCmd;
4186 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4187 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4188 break;
4189 }
4190
4191 case SVGA_3D_CMD_DEAD1:
4192 case SVGA_3D_CMD_DEAD2:
4193 case SVGA_3D_CMD_DEAD12: /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
4194 case SVGA_3D_CMD_DEAD13: /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
4195 case SVGA_3D_CMD_DEAD14: /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
4196 case SVGA_3D_CMD_DEAD15: /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
4197 case SVGA_3D_CMD_DEAD16: /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
4198 case SVGA_3D_CMD_DEAD17: /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
4199 {
4200 VMSVGA_3D_CMD_NOTIMPL();
4201 break;
4202 }
4203
4204 case SVGA_3D_CMD_SET_OTABLE_BASE:
4205 {
4206 SVGA3dCmdSetOTableBase *pCmd = (SVGA3dCmdSetOTableBase *)pvCmd;
4207 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4208 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4209 break;
4210 }
4211
4212 case SVGA_3D_CMD_READBACK_OTABLE:
4213 {
4214 SVGA3dCmdReadbackOTable *pCmd = (SVGA3dCmdReadbackOTable *)pvCmd;
4215 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4216 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4217 break;
4218 }
4219
4220 case SVGA_3D_CMD_DEFINE_GB_MOB:
4221 {
4222 SVGA3dCmdDefineGBMob *pCmd = (SVGA3dCmdDefineGBMob *)pvCmd;
4223 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4224 vmsvga3dCmdDefineGBMob(pThisCC, pCmd);
4225 break;
4226 }
4227
4228 case SVGA_3D_CMD_DESTROY_GB_MOB:
4229 {
4230 SVGA3dCmdDestroyGBMob *pCmd = (SVGA3dCmdDestroyGBMob *)pvCmd;
4231 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4232 vmsvga3dCmdDestroyGBMob(pThisCC, pCmd);
4233 break;
4234 }
4235
4236 case SVGA_3D_CMD_DEAD3:
4237 {
4238 VMSVGA_3D_CMD_NOTIMPL();
4239 break;
4240 }
4241
4242 case SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING:
4243 {
4244 SVGA3dCmdUpdateGBMobMapping *pCmd = (SVGA3dCmdUpdateGBMobMapping *)pvCmd;
4245 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4246 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4247 break;
4248 }
4249
4250 case SVGA_3D_CMD_DEFINE_GB_SURFACE:
4251 {
4252 SVGA3dCmdDefineGBSurface *pCmd = (SVGA3dCmdDefineGBSurface *)pvCmd;
4253 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4254 vmsvga3dCmdDefineGBSurface(pThisCC, pCmd);
4255 break;
4256 }
4257
4258 case SVGA_3D_CMD_DESTROY_GB_SURFACE:
4259 {
4260 SVGA3dCmdDestroyGBSurface *pCmd = (SVGA3dCmdDestroyGBSurface *)pvCmd;
4261 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4262 vmsvga3dCmdDestroyGBSurface(pThisCC, pCmd);
4263 break;
4264 }
4265
4266 case SVGA_3D_CMD_BIND_GB_SURFACE:
4267 {
4268 SVGA3dCmdBindGBSurface *pCmd = (SVGA3dCmdBindGBSurface *)pvCmd;
4269 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4270 vmsvga3dCmdBindGBSurface(pThisCC, pCmd);
4271 break;
4272 }
4273
4274 case SVGA_3D_CMD_COND_BIND_GB_SURFACE:
4275 {
4276 SVGA3dCmdCondBindGBSurface *pCmd = (SVGA3dCmdCondBindGBSurface *)pvCmd;
4277 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4278 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4279 break;
4280 }
4281
4282 case SVGA_3D_CMD_UPDATE_GB_IMAGE:
4283 {
4284 SVGA3dCmdUpdateGBImage *pCmd = (SVGA3dCmdUpdateGBImage *)pvCmd;
4285 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4286 vmsvga3dCmdUpdateGBImage(pThisCC, idDXContext, pCmd);
4287 break;
4288 }
4289
4290 case SVGA_3D_CMD_UPDATE_GB_SURFACE:
4291 {
4292 SVGA3dCmdUpdateGBSurface *pCmd = (SVGA3dCmdUpdateGBSurface *)pvCmd;
4293 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4294 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4295 break;
4296 }
4297
4298 case SVGA_3D_CMD_READBACK_GB_IMAGE:
4299 {
4300 SVGA3dCmdReadbackGBImage *pCmd = (SVGA3dCmdReadbackGBImage *)pvCmd;
4301 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4302 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4303 break;
4304 }
4305
4306 case SVGA_3D_CMD_READBACK_GB_SURFACE:
4307 {
4308 SVGA3dCmdReadbackGBSurface *pCmd = (SVGA3dCmdReadbackGBSurface *)pvCmd;
4309 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4310 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4311 break;
4312 }
4313
4314 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE:
4315 {
4316 SVGA3dCmdInvalidateGBImage *pCmd = (SVGA3dCmdInvalidateGBImage *)pvCmd;
4317 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4318 vmsvga3dCmdInvalidateGBImage(pThisCC, pCmd);
4319 break;
4320 }
4321
4322 case SVGA_3D_CMD_INVALIDATE_GB_SURFACE:
4323 {
4324 SVGA3dCmdInvalidateGBSurface *pCmd = (SVGA3dCmdInvalidateGBSurface *)pvCmd;
4325 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4326 vmsvga3dCmdInvalidateGBSurface(pThisCC, pCmd);
4327 break;
4328 }
4329
4330 case SVGA_3D_CMD_DEFINE_GB_CONTEXT:
4331 {
4332 SVGA3dCmdDefineGBContext *pCmd = (SVGA3dCmdDefineGBContext *)pvCmd;
4333 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4334 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4335 break;
4336 }
4337
4338 case SVGA_3D_CMD_DESTROY_GB_CONTEXT:
4339 {
4340 SVGA3dCmdDestroyGBContext *pCmd = (SVGA3dCmdDestroyGBContext *)pvCmd;
4341 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4342 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4343 break;
4344 }
4345
4346 case SVGA_3D_CMD_BIND_GB_CONTEXT:
4347 {
4348 SVGA3dCmdBindGBContext *pCmd = (SVGA3dCmdBindGBContext *)pvCmd;
4349 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4350 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4351 break;
4352 }
4353
4354 case SVGA_3D_CMD_READBACK_GB_CONTEXT:
4355 {
4356 SVGA3dCmdReadbackGBContext *pCmd = (SVGA3dCmdReadbackGBContext *)pvCmd;
4357 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4358 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4359 break;
4360 }
4361
4362 case SVGA_3D_CMD_INVALIDATE_GB_CONTEXT:
4363 {
4364 SVGA3dCmdInvalidateGBContext *pCmd = (SVGA3dCmdInvalidateGBContext *)pvCmd;
4365 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4366 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4367 break;
4368 }
4369
4370 case SVGA_3D_CMD_DEFINE_GB_SHADER:
4371 {
4372 SVGA3dCmdDefineGBShader *pCmd = (SVGA3dCmdDefineGBShader *)pvCmd;
4373 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4374 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4375 break;
4376 }
4377
4378 case SVGA_3D_CMD_DESTROY_GB_SHADER:
4379 {
4380 SVGA3dCmdDestroyGBShader *pCmd = (SVGA3dCmdDestroyGBShader *)pvCmd;
4381 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4382 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4383 break;
4384 }
4385
4386 case SVGA_3D_CMD_BIND_GB_SHADER:
4387 {
4388 SVGA3dCmdBindGBShader *pCmd = (SVGA3dCmdBindGBShader *)pvCmd;
4389 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4390 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4391 break;
4392 }
4393
4394 case SVGA_3D_CMD_SET_OTABLE_BASE64:
4395 {
4396 SVGA3dCmdSetOTableBase64 *pCmd = (SVGA3dCmdSetOTableBase64 *)pvCmd;
4397 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4398 vmsvga3dCmdSetOTableBase64(pThisCC, pCmd);
4399 break;
4400 }
4401
4402 case SVGA_3D_CMD_BEGIN_GB_QUERY:
4403 {
4404 SVGA3dCmdBeginGBQuery *pCmd = (SVGA3dCmdBeginGBQuery *)pvCmd;
4405 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4406 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4407 break;
4408 }
4409
4410 case SVGA_3D_CMD_END_GB_QUERY:
4411 {
4412 SVGA3dCmdEndGBQuery *pCmd = (SVGA3dCmdEndGBQuery *)pvCmd;
4413 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4414 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4415 break;
4416 }
4417
4418 case SVGA_3D_CMD_WAIT_FOR_GB_QUERY:
4419 {
4420 SVGA3dCmdWaitForGBQuery *pCmd = (SVGA3dCmdWaitForGBQuery *)pvCmd;
4421 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4422 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4423 break;
4424 }
4425
4426 case SVGA_3D_CMD_NOP:
4427 {
4428 /* Apparently there is nothing to do. */
4429 break;
4430 }
4431
4432 case SVGA_3D_CMD_ENABLE_GART:
4433 {
4434 SVGA3dCmdEnableGart *pCmd = (SVGA3dCmdEnableGart *)pvCmd;
4435 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4436 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4437 break;
4438 }
4439
4440 case SVGA_3D_CMD_DISABLE_GART:
4441 {
4442 /* No corresponding SVGA3dCmd structure. */
4443 VMSVGA_3D_CMD_NOTIMPL();
4444 break;
4445 }
4446
4447 case SVGA_3D_CMD_MAP_MOB_INTO_GART:
4448 {
4449 SVGA3dCmdMapMobIntoGart *pCmd = (SVGA3dCmdMapMobIntoGart *)pvCmd;
4450 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4451 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4452 break;
4453 }
4454
4455 case SVGA_3D_CMD_UNMAP_GART_RANGE:
4456 {
4457 SVGA3dCmdUnmapGartRange *pCmd = (SVGA3dCmdUnmapGartRange *)pvCmd;
4458 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4459 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4460 break;
4461 }
4462
4463 case SVGA_3D_CMD_DEFINE_GB_SCREENTARGET:
4464 {
4465 SVGA3dCmdDefineGBScreenTarget *pCmd = (SVGA3dCmdDefineGBScreenTarget *)pvCmd;
4466 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4467 vmsvga3dCmdDefineGBScreenTarget(pThis, pThisCC, pCmd);
4468 break;
4469 }
4470
4471 case SVGA_3D_CMD_DESTROY_GB_SCREENTARGET:
4472 {
4473 SVGA3dCmdDestroyGBScreenTarget *pCmd = (SVGA3dCmdDestroyGBScreenTarget *)pvCmd;
4474 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4475 vmsvga3dCmdDestroyGBScreenTarget(pThis, pThisCC, pCmd);
4476 break;
4477 }
4478
4479 case SVGA_3D_CMD_BIND_GB_SCREENTARGET:
4480 {
4481 SVGA3dCmdBindGBScreenTarget *pCmd = (SVGA3dCmdBindGBScreenTarget *)pvCmd;
4482 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4483 vmsvga3dCmdBindGBScreenTarget(pThisCC, pCmd);
4484 break;
4485 }
4486
4487 case SVGA_3D_CMD_UPDATE_GB_SCREENTARGET:
4488 {
4489 SVGA3dCmdUpdateGBScreenTarget *pCmd = (SVGA3dCmdUpdateGBScreenTarget *)pvCmd;
4490 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4491 vmsvga3dCmdUpdateGBScreenTarget(pThisCC, pCmd);
4492 break;
4493 }
4494
4495 case SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL:
4496 {
4497 SVGA3dCmdReadbackGBImagePartial *pCmd = (SVGA3dCmdReadbackGBImagePartial *)pvCmd;
4498 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4499 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4500 break;
4501 }
4502
4503 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL:
4504 {
4505 SVGA3dCmdInvalidateGBImagePartial *pCmd = (SVGA3dCmdInvalidateGBImagePartial *)pvCmd;
4506 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4507 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4508 break;
4509 }
4510
4511 case SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE:
4512 {
4513 SVGA3dCmdSetGBShaderConstInline *pCmd = (SVGA3dCmdSetGBShaderConstInline *)pvCmd;
4514 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4515 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4516 break;
4517 }
4518
4519 case SVGA_3D_CMD_GB_SCREEN_DMA:
4520 {
4521 SVGA3dCmdGBScreenDMA *pCmd = (SVGA3dCmdGBScreenDMA *)pvCmd;
4522 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4523 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4524 break;
4525 }
4526
4527 case SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH:
4528 {
4529 SVGA3dCmdBindGBSurfaceWithPitch *pCmd = (SVGA3dCmdBindGBSurfaceWithPitch *)pvCmd;
4530 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4531 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4532 break;
4533 }
4534
4535 case SVGA_3D_CMD_GB_MOB_FENCE:
4536 {
4537 SVGA3dCmdGBMobFence *pCmd = (SVGA3dCmdGBMobFence *)pvCmd;
4538 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4539 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4540 break;
4541 }
4542
4543 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V2:
4544 {
4545 SVGA3dCmdDefineGBSurface_v2 *pCmd = (SVGA3dCmdDefineGBSurface_v2 *)pvCmd;
4546 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4547 vmsvga3dCmdDefineGBSurface_v2(pThisCC, pCmd);
4548 break;
4549 }
4550
4551 case SVGA_3D_CMD_DEFINE_GB_MOB64:
4552 {
4553 SVGA3dCmdDefineGBMob64 *pCmd = (SVGA3dCmdDefineGBMob64 *)pvCmd;
4554 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4555 vmsvga3dCmdDefineGBMob64(pThisCC, pCmd);
4556 break;
4557 }
4558
4559 case SVGA_3D_CMD_REDEFINE_GB_MOB64:
4560 {
4561 SVGA3dCmdRedefineGBMob64 *pCmd = (SVGA3dCmdRedefineGBMob64 *)pvCmd;
4562 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4563 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4564 break;
4565 }
4566
4567 case SVGA_3D_CMD_NOP_ERROR:
4568 {
4569 /* Apparently there is nothing to do. */
4570 break;
4571 }
4572
4573 case SVGA_3D_CMD_SET_VERTEX_STREAMS:
4574 {
4575 SVGA3dCmdSetVertexStreams *pCmd = (SVGA3dCmdSetVertexStreams *)pvCmd;
4576 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4577 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4578 break;
4579 }
4580
4581 case SVGA_3D_CMD_SET_VERTEX_DECLS:
4582 {
4583 SVGA3dCmdSetVertexDecls *pCmd = (SVGA3dCmdSetVertexDecls *)pvCmd;
4584 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4585 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4586 break;
4587 }
4588
4589 case SVGA_3D_CMD_SET_VERTEX_DIVISORS:
4590 {
4591 SVGA3dCmdSetVertexDivisors *pCmd = (SVGA3dCmdSetVertexDivisors *)pvCmd;
4592 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4593 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4594 break;
4595 }
4596
4597 case SVGA_3D_CMD_DRAW:
4598 {
4599 /* No corresponding SVGA3dCmd structure. */
4600 VMSVGA_3D_CMD_NOTIMPL();
4601 break;
4602 }
4603
4604 case SVGA_3D_CMD_DRAW_INDEXED:
4605 {
4606 /* No corresponding SVGA3dCmd structure. */
4607 VMSVGA_3D_CMD_NOTIMPL();
4608 break;
4609 }
4610
4611 case SVGA_3D_CMD_DX_DEFINE_CONTEXT:
4612 {
4613 SVGA3dCmdDXDefineContext *pCmd = (SVGA3dCmdDXDefineContext *)pvCmd;
4614 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4615 rcParse = vmsvga3dCmdDXDefineContext(pThisCC, pCmd, cbCmd);
4616 break;
4617 }
4618
4619 case SVGA_3D_CMD_DX_DESTROY_CONTEXT:
4620 {
4621 SVGA3dCmdDXDestroyContext *pCmd = (SVGA3dCmdDXDestroyContext *)pvCmd;
4622 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4623 rcParse = vmsvga3dCmdDXDestroyContext(pThisCC, pCmd, cbCmd);
4624 break;
4625 }
4626
4627 case SVGA_3D_CMD_DX_BIND_CONTEXT:
4628 {
4629 SVGA3dCmdDXBindContext *pCmd = (SVGA3dCmdDXBindContext *)pvCmd;
4630 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4631 rcParse = vmsvga3dCmdDXBindContext(pThisCC, pCmd, cbCmd);
4632 break;
4633 }
4634
4635 case SVGA_3D_CMD_DX_READBACK_CONTEXT:
4636 {
4637 SVGA3dCmdDXReadbackContext *pCmd = (SVGA3dCmdDXReadbackContext *)pvCmd;
4638 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4639 rcParse = vmsvga3dCmdDXReadbackContext(pThisCC, idDXContext, pCmd, cbCmd);
4640 break;
4641 }
4642
4643 case SVGA_3D_CMD_DX_INVALIDATE_CONTEXT:
4644 {
4645 SVGA3dCmdDXInvalidateContext *pCmd = (SVGA3dCmdDXInvalidateContext *)pvCmd;
4646 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4647 rcParse = vmsvga3dCmdDXInvalidateContext(pThisCC, idDXContext, pCmd, cbCmd);
4648 break;
4649 }
4650
4651 case SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER:
4652 {
4653 SVGA3dCmdDXSetSingleConstantBuffer *pCmd = (SVGA3dCmdDXSetSingleConstantBuffer *)pvCmd;
4654 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4655 rcParse = vmsvga3dCmdDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd, cbCmd);
4656 break;
4657 }
4658
4659 case SVGA_3D_CMD_DX_SET_SHADER_RESOURCES:
4660 {
4661 SVGA3dCmdDXSetShaderResources *pCmd = (SVGA3dCmdDXSetShaderResources *)pvCmd;
4662 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4663 rcParse = vmsvga3dCmdDXSetShaderResources(pThisCC, idDXContext, pCmd, cbCmd);
4664 break;
4665 }
4666
4667 case SVGA_3D_CMD_DX_SET_SHADER:
4668 {
4669 SVGA3dCmdDXSetShader *pCmd = (SVGA3dCmdDXSetShader *)pvCmd;
4670 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4671 rcParse = vmsvga3dCmdDXSetShader(pThisCC, idDXContext, pCmd, cbCmd);
4672 break;
4673 }
4674
4675 case SVGA_3D_CMD_DX_SET_SAMPLERS:
4676 {
4677 SVGA3dCmdDXSetSamplers *pCmd = (SVGA3dCmdDXSetSamplers *)pvCmd;
4678 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4679 rcParse = vmsvga3dCmdDXSetSamplers(pThisCC, idDXContext, pCmd, cbCmd);
4680 break;
4681 }
4682
4683 case SVGA_3D_CMD_DX_DRAW:
4684 {
4685 SVGA3dCmdDXDraw *pCmd = (SVGA3dCmdDXDraw *)pvCmd;
4686 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4687 rcParse = vmsvga3dCmdDXDraw(pThisCC, idDXContext, pCmd, cbCmd);
4688 break;
4689 }
4690
4691 case SVGA_3D_CMD_DX_DRAW_INDEXED:
4692 {
4693 SVGA3dCmdDXDrawIndexed *pCmd = (SVGA3dCmdDXDrawIndexed *)pvCmd;
4694 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4695 rcParse = vmsvga3dCmdDXDrawIndexed(pThisCC, idDXContext, pCmd, cbCmd);
4696 break;
4697 }
4698
4699 case SVGA_3D_CMD_DX_DRAW_INSTANCED:
4700 {
4701 SVGA3dCmdDXDrawInstanced *pCmd = (SVGA3dCmdDXDrawInstanced *)pvCmd;
4702 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4703 rcParse = vmsvga3dCmdDXDrawInstanced(pThisCC, idDXContext, pCmd, cbCmd);
4704 break;
4705 }
4706
4707 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED:
4708 {
4709 SVGA3dCmdDXDrawIndexedInstanced *pCmd = (SVGA3dCmdDXDrawIndexedInstanced *)pvCmd;
4710 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4711 rcParse = vmsvga3dCmdDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd, cbCmd);
4712 break;
4713 }
4714
4715 case SVGA_3D_CMD_DX_DRAW_AUTO:
4716 {
4717 SVGA3dCmdDXDrawAuto *pCmd = (SVGA3dCmdDXDrawAuto *)pvCmd;
4718 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4719 rcParse = vmsvga3dCmdDXDrawAuto(pThisCC, idDXContext, pCmd, cbCmd);
4720 break;
4721 }
4722
4723 case SVGA_3D_CMD_DX_SET_INPUT_LAYOUT:
4724 {
4725 SVGA3dCmdDXSetInputLayout *pCmd = (SVGA3dCmdDXSetInputLayout *)pvCmd;
4726 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4727 rcParse = vmsvga3dCmdDXSetInputLayout(pThisCC, idDXContext, pCmd, cbCmd);
4728 break;
4729 }
4730
4731 case SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS:
4732 {
4733 SVGA3dCmdDXSetVertexBuffers *pCmd = (SVGA3dCmdDXSetVertexBuffers *)pvCmd;
4734 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4735 rcParse = vmsvga3dCmdDXSetVertexBuffers(pThisCC, idDXContext, pCmd, cbCmd);
4736 break;
4737 }
4738
4739 case SVGA_3D_CMD_DX_SET_INDEX_BUFFER:
4740 {
4741 SVGA3dCmdDXSetIndexBuffer *pCmd = (SVGA3dCmdDXSetIndexBuffer *)pvCmd;
4742 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4743 rcParse = vmsvga3dCmdDXSetIndexBuffer(pThisCC, idDXContext, pCmd, cbCmd);
4744 break;
4745 }
4746
4747 case SVGA_3D_CMD_DX_SET_TOPOLOGY:
4748 {
4749 SVGA3dCmdDXSetTopology *pCmd = (SVGA3dCmdDXSetTopology *)pvCmd;
4750 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4751 rcParse = vmsvga3dCmdDXSetTopology(pThisCC, idDXContext, pCmd, cbCmd);
4752 break;
4753 }
4754
4755 case SVGA_3D_CMD_DX_SET_RENDERTARGETS:
4756 {
4757 SVGA3dCmdDXSetRenderTargets *pCmd = (SVGA3dCmdDXSetRenderTargets *)pvCmd;
4758 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4759 rcParse = vmsvga3dCmdDXSetRenderTargets(pThisCC, idDXContext, pCmd, cbCmd);
4760 break;
4761 }
4762
4763 case SVGA_3D_CMD_DX_SET_BLEND_STATE:
4764 {
4765 SVGA3dCmdDXSetBlendState *pCmd = (SVGA3dCmdDXSetBlendState *)pvCmd;
4766 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4767 rcParse = vmsvga3dCmdDXSetBlendState(pThisCC, idDXContext, pCmd, cbCmd);
4768 break;
4769 }
4770
4771 case SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE:
4772 {
4773 SVGA3dCmdDXSetDepthStencilState *pCmd = (SVGA3dCmdDXSetDepthStencilState *)pvCmd;
4774 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4775 rcParse = vmsvga3dCmdDXSetDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
4776 break;
4777 }
4778
4779 case SVGA_3D_CMD_DX_SET_RASTERIZER_STATE:
4780 {
4781 SVGA3dCmdDXSetRasterizerState *pCmd = (SVGA3dCmdDXSetRasterizerState *)pvCmd;
4782 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4783 rcParse = vmsvga3dCmdDXSetRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
4784 break;
4785 }
4786
4787 case SVGA_3D_CMD_DX_DEFINE_QUERY:
4788 {
4789 SVGA3dCmdDXDefineQuery *pCmd = (SVGA3dCmdDXDefineQuery *)pvCmd;
4790 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4791 rcParse = vmsvga3dCmdDXDefineQuery(pThisCC, idDXContext, pCmd, cbCmd);
4792 break;
4793 }
4794
4795 case SVGA_3D_CMD_DX_DESTROY_QUERY:
4796 {
4797 SVGA3dCmdDXDestroyQuery *pCmd = (SVGA3dCmdDXDestroyQuery *)pvCmd;
4798 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4799 rcParse = vmsvga3dCmdDXDestroyQuery(pThisCC, idDXContext, pCmd, cbCmd);
4800 break;
4801 }
4802
4803 case SVGA_3D_CMD_DX_BIND_QUERY:
4804 {
4805 SVGA3dCmdDXBindQuery *pCmd = (SVGA3dCmdDXBindQuery *)pvCmd;
4806 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4807 rcParse = vmsvga3dCmdDXBindQuery(pThisCC, idDXContext, pCmd, cbCmd);
4808 break;
4809 }
4810
4811 case SVGA_3D_CMD_DX_SET_QUERY_OFFSET:
4812 {
4813 SVGA3dCmdDXSetQueryOffset *pCmd = (SVGA3dCmdDXSetQueryOffset *)pvCmd;
4814 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4815 rcParse = vmsvga3dCmdDXSetQueryOffset(pThisCC, idDXContext, pCmd, cbCmd);
4816 break;
4817 }
4818
4819 case SVGA_3D_CMD_DX_BEGIN_QUERY:
4820 {
4821 SVGA3dCmdDXBeginQuery *pCmd = (SVGA3dCmdDXBeginQuery *)pvCmd;
4822 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4823 rcParse = vmsvga3dCmdDXBeginQuery(pThisCC, idDXContext, pCmd, cbCmd);
4824 break;
4825 }
4826
4827 case SVGA_3D_CMD_DX_END_QUERY:
4828 {
4829 SVGA3dCmdDXEndQuery *pCmd = (SVGA3dCmdDXEndQuery *)pvCmd;
4830 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4831 rcParse = vmsvga3dCmdDXEndQuery(pThisCC, idDXContext, pCmd, cbCmd);
4832 break;
4833 }
4834
4835 case SVGA_3D_CMD_DX_READBACK_QUERY:
4836 {
4837 SVGA3dCmdDXReadbackQuery *pCmd = (SVGA3dCmdDXReadbackQuery *)pvCmd;
4838 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4839 rcParse = vmsvga3dCmdDXReadbackQuery(pThisCC, idDXContext, pCmd, cbCmd);
4840 break;
4841 }
4842
4843 case SVGA_3D_CMD_DX_SET_PREDICATION:
4844 {
4845 SVGA3dCmdDXSetPredication *pCmd = (SVGA3dCmdDXSetPredication *)pvCmd;
4846 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4847 rcParse = vmsvga3dCmdDXSetPredication(pThisCC, idDXContext, pCmd, cbCmd);
4848 break;
4849 }
4850
4851 case SVGA_3D_CMD_DX_SET_SOTARGETS:
4852 {
4853 SVGA3dCmdDXSetSOTargets *pCmd = (SVGA3dCmdDXSetSOTargets *)pvCmd;
4854 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4855 rcParse = vmsvga3dCmdDXSetSOTargets(pThisCC, idDXContext, pCmd, cbCmd);
4856 break;
4857 }
4858
4859 case SVGA_3D_CMD_DX_SET_VIEWPORTS:
4860 {
4861 SVGA3dCmdDXSetViewports *pCmd = (SVGA3dCmdDXSetViewports *)pvCmd;
4862 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4863 rcParse = vmsvga3dCmdDXSetViewports(pThisCC, idDXContext, pCmd, cbCmd);
4864 break;
4865 }
4866
4867 case SVGA_3D_CMD_DX_SET_SCISSORRECTS:
4868 {
4869 SVGA3dCmdDXSetScissorRects *pCmd = (SVGA3dCmdDXSetScissorRects *)pvCmd;
4870 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4871 rcParse = vmsvga3dCmdDXSetScissorRects(pThisCC, idDXContext, pCmd, cbCmd);
4872 break;
4873 }
4874
4875 case SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW:
4876 {
4877 SVGA3dCmdDXClearRenderTargetView *pCmd = (SVGA3dCmdDXClearRenderTargetView *)pvCmd;
4878 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4879 rcParse = vmsvga3dCmdDXClearRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
4880 break;
4881 }
4882
4883 case SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW:
4884 {
4885 SVGA3dCmdDXClearDepthStencilView *pCmd = (SVGA3dCmdDXClearDepthStencilView *)pvCmd;
4886 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4887 rcParse = vmsvga3dCmdDXClearDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
4888 break;
4889 }
4890
4891 case SVGA_3D_CMD_DX_PRED_COPY_REGION:
4892 {
4893 SVGA3dCmdDXPredCopyRegion *pCmd = (SVGA3dCmdDXPredCopyRegion *)pvCmd;
4894 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4895 rcParse = vmsvga3dCmdDXPredCopyRegion(pThisCC, idDXContext, pCmd, cbCmd);
4896 break;
4897 }
4898
4899 case SVGA_3D_CMD_DX_PRED_COPY:
4900 {
4901 SVGA3dCmdDXPredCopy *pCmd = (SVGA3dCmdDXPredCopy *)pvCmd;
4902 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4903 rcParse = vmsvga3dCmdDXPredCopy(pThisCC, idDXContext, pCmd, cbCmd);
4904 break;
4905 }
4906
4907 case SVGA_3D_CMD_DX_PRESENTBLT:
4908 {
4909 SVGA3dCmdDXPresentBlt *pCmd = (SVGA3dCmdDXPresentBlt *)pvCmd;
4910 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4911 rcParse = vmsvga3dCmdDXPresentBlt(pThisCC, idDXContext, pCmd, cbCmd);
4912 break;
4913 }
4914
4915 case SVGA_3D_CMD_DX_GENMIPS:
4916 {
4917 SVGA3dCmdDXGenMips *pCmd = (SVGA3dCmdDXGenMips *)pvCmd;
4918 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4919 rcParse = vmsvga3dCmdDXGenMips(pThisCC, idDXContext, pCmd, cbCmd);
4920 break;
4921 }
4922
4923 case SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE:
4924 {
4925 SVGA3dCmdDXUpdateSubResource *pCmd = (SVGA3dCmdDXUpdateSubResource *)pvCmd;
4926 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4927 rcParse = vmsvga3dCmdDXUpdateSubResource(pThisCC, idDXContext, pCmd, cbCmd);
4928 break;
4929 }
4930
4931 case SVGA_3D_CMD_DX_READBACK_SUBRESOURCE:
4932 {
4933 SVGA3dCmdDXReadbackSubResource *pCmd = (SVGA3dCmdDXReadbackSubResource *)pvCmd;
4934 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4935 rcParse = vmsvga3dCmdDXReadbackSubResource(pThisCC, idDXContext, pCmd, cbCmd);
4936 break;
4937 }
4938
4939 case SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE:
4940 {
4941 SVGA3dCmdDXInvalidateSubResource *pCmd = (SVGA3dCmdDXInvalidateSubResource *)pvCmd;
4942 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4943 rcParse = vmsvga3dCmdDXInvalidateSubResource(pThisCC, idDXContext, pCmd, cbCmd);
4944 break;
4945 }
4946
4947 case SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW:
4948 {
4949 SVGA3dCmdDXDefineShaderResourceView *pCmd = (SVGA3dCmdDXDefineShaderResourceView *)pvCmd;
4950 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4951 rcParse = vmsvga3dCmdDXDefineShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
4952 break;
4953 }
4954
4955 case SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW:
4956 {
4957 SVGA3dCmdDXDestroyShaderResourceView *pCmd = (SVGA3dCmdDXDestroyShaderResourceView *)pvCmd;
4958 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4959 rcParse = vmsvga3dCmdDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
4960 break;
4961 }
4962
4963 case SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW:
4964 {
4965 SVGA3dCmdDXDefineRenderTargetView *pCmd = (SVGA3dCmdDXDefineRenderTargetView *)pvCmd;
4966 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4967 rcParse = vmsvga3dCmdDXDefineRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
4968 break;
4969 }
4970
4971 case SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW:
4972 {
4973 SVGA3dCmdDXDestroyRenderTargetView *pCmd = (SVGA3dCmdDXDestroyRenderTargetView *)pvCmd;
4974 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4975 rcParse = vmsvga3dCmdDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
4976 break;
4977 }
4978
4979 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW:
4980 {
4981 SVGA3dCmdDXDefineDepthStencilView *pCmd = (SVGA3dCmdDXDefineDepthStencilView *)pvCmd;
4982 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4983 rcParse = vmsvga3dCmdDXDefineDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
4984 break;
4985 }
4986
4987 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW:
4988 {
4989 SVGA3dCmdDXDestroyDepthStencilView *pCmd = (SVGA3dCmdDXDestroyDepthStencilView *)pvCmd;
4990 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4991 rcParse = vmsvga3dCmdDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
4992 break;
4993 }
4994
4995 case SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT:
4996 {
4997 SVGA3dCmdDXDefineElementLayout *pCmd = (SVGA3dCmdDXDefineElementLayout *)pvCmd;
4998 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4999 rcParse = vmsvga3dCmdDXDefineElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5000 break;
5001 }
5002
5003 case SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT:
5004 {
5005 SVGA3dCmdDXDestroyElementLayout *pCmd = (SVGA3dCmdDXDestroyElementLayout *)pvCmd;
5006 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5007 rcParse = vmsvga3dCmdDXDestroyElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5008 break;
5009 }
5010
5011 case SVGA_3D_CMD_DX_DEFINE_BLEND_STATE:
5012 {
5013 SVGA3dCmdDXDefineBlendState *pCmd = (SVGA3dCmdDXDefineBlendState *)pvCmd;
5014 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5015 rcParse = vmsvga3dCmdDXDefineBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5016 break;
5017 }
5018
5019 case SVGA_3D_CMD_DX_DESTROY_BLEND_STATE:
5020 {
5021 SVGA3dCmdDXDestroyBlendState *pCmd = (SVGA3dCmdDXDestroyBlendState *)pvCmd;
5022 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5023 rcParse = vmsvga3dCmdDXDestroyBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5024 break;
5025 }
5026
5027 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE:
5028 {
5029 SVGA3dCmdDXDefineDepthStencilState *pCmd = (SVGA3dCmdDXDefineDepthStencilState *)pvCmd;
5030 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5031 rcParse = vmsvga3dCmdDXDefineDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5032 break;
5033 }
5034
5035 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE:
5036 {
5037 SVGA3dCmdDXDestroyDepthStencilState *pCmd = (SVGA3dCmdDXDestroyDepthStencilState *)pvCmd;
5038 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5039 rcParse = vmsvga3dCmdDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5040 break;
5041 }
5042
5043 case SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE:
5044 {
5045 SVGA3dCmdDXDefineRasterizerState *pCmd = (SVGA3dCmdDXDefineRasterizerState *)pvCmd;
5046 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5047 rcParse = vmsvga3dCmdDXDefineRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5048 break;
5049 }
5050
5051 case SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE:
5052 {
5053 SVGA3dCmdDXDestroyRasterizerState *pCmd = (SVGA3dCmdDXDestroyRasterizerState *)pvCmd;
5054 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5055 rcParse = vmsvga3dCmdDXDestroyRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5056 break;
5057 }
5058
5059 case SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE:
5060 {
5061 SVGA3dCmdDXDefineSamplerState *pCmd = (SVGA3dCmdDXDefineSamplerState *)pvCmd;
5062 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5063 rcParse = vmsvga3dCmdDXDefineSamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5064 break;
5065 }
5066
5067 case SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE:
5068 {
5069 SVGA3dCmdDXDestroySamplerState *pCmd = (SVGA3dCmdDXDestroySamplerState *)pvCmd;
5070 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5071 rcParse = vmsvga3dCmdDXDestroySamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5072 break;
5073 }
5074
5075 case SVGA_3D_CMD_DX_DEFINE_SHADER:
5076 {
5077 SVGA3dCmdDXDefineShader *pCmd = (SVGA3dCmdDXDefineShader *)pvCmd;
5078 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5079 rcParse = vmsvga3dCmdDXDefineShader(pThisCC, idDXContext, pCmd, cbCmd);
5080 break;
5081 }
5082
5083 case SVGA_3D_CMD_DX_DESTROY_SHADER:
5084 {
5085 SVGA3dCmdDXDestroyShader *pCmd = (SVGA3dCmdDXDestroyShader *)pvCmd;
5086 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5087 rcParse = vmsvga3dCmdDXDestroyShader(pThisCC, idDXContext, pCmd, cbCmd);
5088 break;
5089 }
5090
5091 case SVGA_3D_CMD_DX_BIND_SHADER:
5092 {
5093 SVGA3dCmdDXBindShader *pCmd = (SVGA3dCmdDXBindShader *)pvCmd;
5094 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5095 rcParse = vmsvga3dCmdDXBindShader(pThisCC, idDXContext, pCmd, cbCmd);
5096 break;
5097 }
5098
5099 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT:
5100 {
5101 SVGA3dCmdDXDefineStreamOutput *pCmd = (SVGA3dCmdDXDefineStreamOutput *)pvCmd;
5102 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5103 rcParse = vmsvga3dCmdDXDefineStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5104 break;
5105 }
5106
5107 case SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT:
5108 {
5109 SVGA3dCmdDXDestroyStreamOutput *pCmd = (SVGA3dCmdDXDestroyStreamOutput *)pvCmd;
5110 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5111 rcParse = vmsvga3dCmdDXDestroyStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5112 break;
5113 }
5114
5115 case SVGA_3D_CMD_DX_SET_STREAMOUTPUT:
5116 {
5117 SVGA3dCmdDXSetStreamOutput *pCmd = (SVGA3dCmdDXSetStreamOutput *)pvCmd;
5118 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5119 rcParse = vmsvga3dCmdDXSetStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5120 break;
5121 }
5122
5123 case SVGA_3D_CMD_DX_SET_COTABLE:
5124 {
5125 SVGA3dCmdDXSetCOTable *pCmd = (SVGA3dCmdDXSetCOTable *)pvCmd;
5126 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5127 rcParse = vmsvga3dCmdDXSetCOTable(pThisCC, pCmd, cbCmd);
5128 break;
5129 }
5130
5131 case SVGA_3D_CMD_DX_READBACK_COTABLE:
5132 {
5133 SVGA3dCmdDXReadbackCOTable *pCmd = (SVGA3dCmdDXReadbackCOTable *)pvCmd;
5134 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5135 rcParse = vmsvga3dCmdDXReadbackCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5136 break;
5137 }
5138
5139 case SVGA_3D_CMD_DX_BUFFER_COPY:
5140 {
5141 SVGA3dCmdDXBufferCopy *pCmd = (SVGA3dCmdDXBufferCopy *)pvCmd;
5142 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5143 rcParse = vmsvga3dCmdDXBufferCopy(pThisCC, idDXContext, pCmd, cbCmd);
5144 break;
5145 }
5146
5147 case SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER:
5148 {
5149 SVGA3dCmdDXTransferFromBuffer *pCmd = (SVGA3dCmdDXTransferFromBuffer *)pvCmd;
5150 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5151 rcParse = vmsvga3dCmdDXTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5152 break;
5153 }
5154
5155 case SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK:
5156 {
5157 SVGA3dCmdDXSurfaceCopyAndReadback *pCmd = (SVGA3dCmdDXSurfaceCopyAndReadback *)pvCmd;
5158 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5159 rcParse = vmsvga3dCmdDXSurfaceCopyAndReadback(pThisCC, idDXContext, pCmd, cbCmd);
5160 break;
5161 }
5162
5163 case SVGA_3D_CMD_DX_MOVE_QUERY:
5164 {
5165 SVGA3dCmdDXMoveQuery *pCmd = (SVGA3dCmdDXMoveQuery *)pvCmd;
5166 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5167 rcParse = vmsvga3dCmdDXMoveQuery(pThisCC, idDXContext, pCmd, cbCmd);
5168 break;
5169 }
5170
5171 case SVGA_3D_CMD_DX_BIND_ALL_QUERY:
5172 {
5173 SVGA3dCmdDXBindAllQuery *pCmd = (SVGA3dCmdDXBindAllQuery *)pvCmd;
5174 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5175 rcParse = vmsvga3dCmdDXBindAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5176 break;
5177 }
5178
5179 case SVGA_3D_CMD_DX_READBACK_ALL_QUERY:
5180 {
5181 SVGA3dCmdDXReadbackAllQuery *pCmd = (SVGA3dCmdDXReadbackAllQuery *)pvCmd;
5182 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5183 rcParse = vmsvga3dCmdDXReadbackAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5184 break;
5185 }
5186
5187 case SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER:
5188 {
5189 SVGA3dCmdDXPredTransferFromBuffer *pCmd = (SVGA3dCmdDXPredTransferFromBuffer *)pvCmd;
5190 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5191 rcParse = vmsvga3dCmdDXPredTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5192 break;
5193 }
5194
5195 case SVGA_3D_CMD_DX_MOB_FENCE_64:
5196 {
5197 SVGA3dCmdDXMobFence64 *pCmd = (SVGA3dCmdDXMobFence64 *)pvCmd;
5198 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5199 rcParse = vmsvga3dCmdDXMobFence64(pThisCC, idDXContext, pCmd, cbCmd);
5200 break;
5201 }
5202
5203 case SVGA_3D_CMD_DX_BIND_ALL_SHADER:
5204 {
5205 SVGA3dCmdDXBindAllShader *pCmd = (SVGA3dCmdDXBindAllShader *)pvCmd;
5206 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5207 rcParse = vmsvga3dCmdDXBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5208 break;
5209 }
5210
5211 case SVGA_3D_CMD_DX_HINT:
5212 {
5213 SVGA3dCmdDXHint *pCmd = (SVGA3dCmdDXHint *)pvCmd;
5214 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5215 rcParse = vmsvga3dCmdDXHint(pThisCC, idDXContext, pCmd, cbCmd);
5216 break;
5217 }
5218
5219 case SVGA_3D_CMD_DX_BUFFER_UPDATE:
5220 {
5221 SVGA3dCmdDXBufferUpdate *pCmd = (SVGA3dCmdDXBufferUpdate *)pvCmd;
5222 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5223 rcParse = vmsvga3dCmdDXBufferUpdate(pThisCC, idDXContext, pCmd, cbCmd);
5224 break;
5225 }
5226
5227 case SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET:
5228 {
5229 SVGA3dCmdDXSetVSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetVSConstantBufferOffset *)pvCmd;
5230 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5231 rcParse = vmsvga3dCmdDXSetVSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5232 break;
5233 }
5234
5235 case SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET:
5236 {
5237 SVGA3dCmdDXSetPSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetPSConstantBufferOffset *)pvCmd;
5238 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5239 rcParse = vmsvga3dCmdDXSetPSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5240 break;
5241 }
5242
5243 case SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET:
5244 {
5245 SVGA3dCmdDXSetGSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetGSConstantBufferOffset *)pvCmd;
5246 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5247 rcParse = vmsvga3dCmdDXSetGSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5248 break;
5249 }
5250
5251 case SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET:
5252 {
5253 SVGA3dCmdDXSetHSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetHSConstantBufferOffset *)pvCmd;
5254 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5255 rcParse = vmsvga3dCmdDXSetHSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5256 break;
5257 }
5258
5259 case SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET:
5260 {
5261 SVGA3dCmdDXSetDSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetDSConstantBufferOffset *)pvCmd;
5262 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5263 rcParse = vmsvga3dCmdDXSetDSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5264 break;
5265 }
5266
5267 case SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET:
5268 {
5269 SVGA3dCmdDXSetCSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetCSConstantBufferOffset *)pvCmd;
5270 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5271 rcParse = vmsvga3dCmdDXSetCSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5272 break;
5273 }
5274
5275 case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER:
5276 {
5277 SVGA3dCmdDXCondBindAllShader *pCmd = (SVGA3dCmdDXCondBindAllShader *)pvCmd;
5278 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5279 rcParse = vmsvga3dCmdDXCondBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5280 break;
5281 }
5282
5283 case SVGA_3D_CMD_SCREEN_COPY:
5284 {
5285 SVGA3dCmdScreenCopy *pCmd = (SVGA3dCmdScreenCopy *)pvCmd;
5286 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5287 rcParse = vmsvga3dCmdScreenCopy(pThisCC, idDXContext, pCmd, cbCmd);
5288 break;
5289 }
5290
5291 case SVGA_3D_CMD_RESERVED1:
5292 {
5293 VMSVGA_3D_CMD_NOTIMPL();
5294 break;
5295 }
5296
5297 case SVGA_3D_CMD_RESERVED2:
5298 {
5299 VMSVGA_3D_CMD_NOTIMPL();
5300 break;
5301 }
5302
5303 case SVGA_3D_CMD_RESERVED3:
5304 {
5305 VMSVGA_3D_CMD_NOTIMPL();
5306 break;
5307 }
5308
5309 case SVGA_3D_CMD_RESERVED4:
5310 {
5311 VMSVGA_3D_CMD_NOTIMPL();
5312 break;
5313 }
5314
5315 case SVGA_3D_CMD_RESERVED5:
5316 {
5317 VMSVGA_3D_CMD_NOTIMPL();
5318 break;
5319 }
5320
5321 case SVGA_3D_CMD_RESERVED6:
5322 {
5323 VMSVGA_3D_CMD_NOTIMPL();
5324 break;
5325 }
5326
5327 case SVGA_3D_CMD_RESERVED7:
5328 {
5329 VMSVGA_3D_CMD_NOTIMPL();
5330 break;
5331 }
5332
5333 case SVGA_3D_CMD_RESERVED8:
5334 {
5335 VMSVGA_3D_CMD_NOTIMPL();
5336 break;
5337 }
5338
5339 case SVGA_3D_CMD_GROW_OTABLE:
5340 {
5341 SVGA3dCmdGrowOTable *pCmd = (SVGA3dCmdGrowOTable *)pvCmd;
5342 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5343 rcParse = vmsvga3dCmdGrowOTable(pThisCC, idDXContext, pCmd, cbCmd);
5344 break;
5345 }
5346
5347 case SVGA_3D_CMD_DX_GROW_COTABLE:
5348 {
5349 SVGA3dCmdDXGrowCOTable *pCmd = (SVGA3dCmdDXGrowCOTable *)pvCmd;
5350 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5351 rcParse = vmsvga3dCmdDXGrowCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5352 break;
5353 }
5354
5355 case SVGA_3D_CMD_INTRA_SURFACE_COPY:
5356 {
5357 SVGA3dCmdIntraSurfaceCopy *pCmd = (SVGA3dCmdIntraSurfaceCopy *)pvCmd;
5358 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5359 rcParse = vmsvga3dCmdIntraSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5360 break;
5361 }
5362
5363 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V3:
5364 {
5365 SVGA3dCmdDefineGBSurface_v3 *pCmd = (SVGA3dCmdDefineGBSurface_v3 *)pvCmd;
5366 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5367 rcParse = vmsvga3dCmdDefineGBSurface_v3(pThisCC, idDXContext, pCmd, cbCmd);
5368 break;
5369 }
5370
5371 case SVGA_3D_CMD_DX_RESOLVE_COPY:
5372 {
5373 SVGA3dCmdDXResolveCopy *pCmd = (SVGA3dCmdDXResolveCopy *)pvCmd;
5374 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5375 rcParse = vmsvga3dCmdDXResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5376 break;
5377 }
5378
5379 case SVGA_3D_CMD_DX_PRED_RESOLVE_COPY:
5380 {
5381 SVGA3dCmdDXPredResolveCopy *pCmd = (SVGA3dCmdDXPredResolveCopy *)pvCmd;
5382 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5383 rcParse = vmsvga3dCmdDXPredResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5384 break;
5385 }
5386
5387 case SVGA_3D_CMD_DX_PRED_CONVERT_REGION:
5388 {
5389 SVGA3dCmdDXPredConvertRegion *pCmd = (SVGA3dCmdDXPredConvertRegion *)pvCmd;
5390 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5391 rcParse = vmsvga3dCmdDXPredConvertRegion(pThisCC, idDXContext, pCmd, cbCmd);
5392 break;
5393 }
5394
5395 case SVGA_3D_CMD_DX_PRED_CONVERT:
5396 {
5397 SVGA3dCmdDXPredConvert *pCmd = (SVGA3dCmdDXPredConvert *)pvCmd;
5398 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5399 rcParse = vmsvga3dCmdDXPredConvert(pThisCC, idDXContext, pCmd, cbCmd);
5400 break;
5401 }
5402
5403 case SVGA_3D_CMD_WHOLE_SURFACE_COPY:
5404 {
5405 SVGA3dCmdWholeSurfaceCopy *pCmd = (SVGA3dCmdWholeSurfaceCopy *)pvCmd;
5406 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5407 rcParse = vmsvga3dCmdWholeSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5408 break;
5409 }
5410
5411 case SVGA_3D_CMD_DX_DEFINE_UA_VIEW:
5412 {
5413 SVGA3dCmdDXDefineUAView *pCmd = (SVGA3dCmdDXDefineUAView *)pvCmd;
5414 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5415 rcParse = vmsvga3dCmdDXDefineUAView(pThisCC, idDXContext, pCmd, cbCmd);
5416 break;
5417 }
5418
5419 case SVGA_3D_CMD_DX_DESTROY_UA_VIEW:
5420 {
5421 SVGA3dCmdDXDestroyUAView *pCmd = (SVGA3dCmdDXDestroyUAView *)pvCmd;
5422 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5423 rcParse = vmsvga3dCmdDXDestroyUAView(pThisCC, idDXContext, pCmd, cbCmd);
5424 break;
5425 }
5426
5427 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT:
5428 {
5429 SVGA3dCmdDXClearUAViewUint *pCmd = (SVGA3dCmdDXClearUAViewUint *)pvCmd;
5430 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5431 rcParse = vmsvga3dCmdDXClearUAViewUint(pThisCC, idDXContext, pCmd, cbCmd);
5432 break;
5433 }
5434
5435 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT:
5436 {
5437 SVGA3dCmdDXClearUAViewFloat *pCmd = (SVGA3dCmdDXClearUAViewFloat *)pvCmd;
5438 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5439 rcParse = vmsvga3dCmdDXClearUAViewFloat(pThisCC, idDXContext, pCmd, cbCmd);
5440 break;
5441 }
5442
5443 case SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT:
5444 {
5445 SVGA3dCmdDXCopyStructureCount *pCmd = (SVGA3dCmdDXCopyStructureCount *)pvCmd;
5446 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5447 rcParse = vmsvga3dCmdDXCopyStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5448 break;
5449 }
5450
5451 case SVGA_3D_CMD_DX_SET_UA_VIEWS:
5452 {
5453 SVGA3dCmdDXSetUAViews *pCmd = (SVGA3dCmdDXSetUAViews *)pvCmd;
5454 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5455 rcParse = vmsvga3dCmdDXSetUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5456 break;
5457 }
5458
5459 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT:
5460 {
5461 SVGA3dCmdDXDrawIndexedInstancedIndirect *pCmd = (SVGA3dCmdDXDrawIndexedInstancedIndirect *)pvCmd;
5462 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5463 rcParse = vmsvga3dCmdDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5464 break;
5465 }
5466
5467 case SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT:
5468 {
5469 SVGA3dCmdDXDrawInstancedIndirect *pCmd = (SVGA3dCmdDXDrawInstancedIndirect *)pvCmd;
5470 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5471 rcParse = vmsvga3dCmdDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5472 break;
5473 }
5474
5475 case SVGA_3D_CMD_DX_DISPATCH:
5476 {
5477 SVGA3dCmdDXDispatch *pCmd = (SVGA3dCmdDXDispatch *)pvCmd;
5478 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5479 rcParse = vmsvga3dCmdDXDispatch(pThisCC, idDXContext, pCmd, cbCmd);
5480 break;
5481 }
5482
5483 case SVGA_3D_CMD_DX_DISPATCH_INDIRECT:
5484 {
5485 SVGA3dCmdDXDispatchIndirect *pCmd = (SVGA3dCmdDXDispatchIndirect *)pvCmd;
5486 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5487 rcParse = vmsvga3dCmdDXDispatchIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5488 break;
5489 }
5490
5491 case SVGA_3D_CMD_WRITE_ZERO_SURFACE:
5492 {
5493 SVGA3dCmdWriteZeroSurface *pCmd = (SVGA3dCmdWriteZeroSurface *)pvCmd;
5494 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5495 rcParse = vmsvga3dCmdWriteZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5496 break;
5497 }
5498
5499 case SVGA_3D_CMD_HINT_ZERO_SURFACE:
5500 {
5501 SVGA3dCmdHintZeroSurface *pCmd = (SVGA3dCmdHintZeroSurface *)pvCmd;
5502 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5503 rcParse = vmsvga3dCmdHintZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5504 break;
5505 }
5506
5507 case SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER:
5508 {
5509 SVGA3dCmdDXTransferToBuffer *pCmd = (SVGA3dCmdDXTransferToBuffer *)pvCmd;
5510 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5511 rcParse = vmsvga3dCmdDXTransferToBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5512 break;
5513 }
5514
5515 case SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT:
5516 {
5517 SVGA3dCmdDXSetStructureCount *pCmd = (SVGA3dCmdDXSetStructureCount *)pvCmd;
5518 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5519 rcParse = vmsvga3dCmdDXSetStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5520 break;
5521 }
5522
5523 case SVGA_3D_CMD_LOGICOPS_BITBLT:
5524 {
5525 SVGA3dCmdLogicOpsBitBlt *pCmd = (SVGA3dCmdLogicOpsBitBlt *)pvCmd;
5526 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5527 rcParse = vmsvga3dCmdLogicOpsBitBlt(pThisCC, idDXContext, pCmd, cbCmd);
5528 break;
5529 }
5530
5531 case SVGA_3D_CMD_LOGICOPS_TRANSBLT:
5532 {
5533 SVGA3dCmdLogicOpsTransBlt *pCmd = (SVGA3dCmdLogicOpsTransBlt *)pvCmd;
5534 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5535 rcParse = vmsvga3dCmdLogicOpsTransBlt(pThisCC, idDXContext, pCmd, cbCmd);
5536 break;
5537 }
5538
5539 case SVGA_3D_CMD_LOGICOPS_STRETCHBLT:
5540 {
5541 SVGA3dCmdLogicOpsStretchBlt *pCmd = (SVGA3dCmdLogicOpsStretchBlt *)pvCmd;
5542 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5543 rcParse = vmsvga3dCmdLogicOpsStretchBlt(pThisCC, idDXContext, pCmd, cbCmd);
5544 break;
5545 }
5546
5547 case SVGA_3D_CMD_LOGICOPS_COLORFILL:
5548 {
5549 SVGA3dCmdLogicOpsColorFill *pCmd = (SVGA3dCmdLogicOpsColorFill *)pvCmd;
5550 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5551 rcParse = vmsvga3dCmdLogicOpsColorFill(pThisCC, idDXContext, pCmd, cbCmd);
5552 break;
5553 }
5554
5555 case SVGA_3D_CMD_LOGICOPS_ALPHABLEND:
5556 {
5557 SVGA3dCmdLogicOpsAlphaBlend *pCmd = (SVGA3dCmdLogicOpsAlphaBlend *)pvCmd;
5558 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5559 rcParse = vmsvga3dCmdLogicOpsAlphaBlend(pThisCC, idDXContext, pCmd, cbCmd);
5560 break;
5561 }
5562
5563 case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND:
5564 {
5565 SVGA3dCmdLogicOpsClearTypeBlend *pCmd = (SVGA3dCmdLogicOpsClearTypeBlend *)pvCmd;
5566 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5567 rcParse = vmsvga3dCmdLogicOpsClearTypeBlend(pThisCC, idDXContext, pCmd, cbCmd);
5568 break;
5569 }
5570
5571 case SVGA_3D_CMD_RESERVED2_1:
5572 {
5573 VMSVGA_3D_CMD_NOTIMPL();
5574 break;
5575 }
5576
5577 case SVGA_3D_CMD_RESERVED2_2:
5578 {
5579 VMSVGA_3D_CMD_NOTIMPL();
5580 break;
5581 }
5582
5583 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V4:
5584 {
5585 SVGA3dCmdDefineGBSurface_v4 *pCmd = (SVGA3dCmdDefineGBSurface_v4 *)pvCmd;
5586 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5587 rcParse = vmsvga3dCmdDefineGBSurface_v4(pThisCC, idDXContext, pCmd, cbCmd);
5588 break;
5589 }
5590
5591 case SVGA_3D_CMD_DX_SET_CS_UA_VIEWS:
5592 {
5593 SVGA3dCmdDXSetCSUAViews *pCmd = (SVGA3dCmdDXSetCSUAViews *)pvCmd;
5594 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5595 rcParse = vmsvga3dCmdDXSetCSUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5596 break;
5597 }
5598
5599 case SVGA_3D_CMD_DX_SET_MIN_LOD:
5600 {
5601 SVGA3dCmdDXSetMinLOD *pCmd = (SVGA3dCmdDXSetMinLOD *)pvCmd;
5602 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5603 rcParse = vmsvga3dCmdDXSetMinLOD(pThisCC, idDXContext, pCmd, cbCmd);
5604 break;
5605 }
5606
5607 case SVGA_3D_CMD_RESERVED2_3:
5608 {
5609 VMSVGA_3D_CMD_NOTIMPL();
5610 break;
5611 }
5612
5613 case SVGA_3D_CMD_RESERVED2_4:
5614 {
5615 VMSVGA_3D_CMD_NOTIMPL();
5616 break;
5617 }
5618
5619 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2:
5620 {
5621 SVGA3dCmdDXDefineDepthStencilView_v2 *pCmd = (SVGA3dCmdDXDefineDepthStencilView_v2 *)pvCmd;
5622 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5623 rcParse = vmsvga3dCmdDXDefineDepthStencilView_v2(pThisCC, idDXContext, pCmd, cbCmd);
5624 break;
5625 }
5626
5627 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB:
5628 {
5629 SVGA3dCmdDXDefineStreamOutputWithMob *pCmd = (SVGA3dCmdDXDefineStreamOutputWithMob *)pvCmd;
5630 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5631 rcParse = vmsvga3dCmdDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd, cbCmd);
5632 break;
5633 }
5634
5635 case SVGA_3D_CMD_DX_SET_SHADER_IFACE:
5636 {
5637 SVGA3dCmdDXSetShaderIface *pCmd = (SVGA3dCmdDXSetShaderIface *)pvCmd;
5638 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5639 rcParse = vmsvga3dCmdDXSetShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
5640 break;
5641 }
5642
5643 case SVGA_3D_CMD_DX_BIND_STREAMOUTPUT:
5644 {
5645 SVGA3dCmdDXBindStreamOutput *pCmd = (SVGA3dCmdDXBindStreamOutput *)pvCmd;
5646 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5647 rcParse = vmsvga3dCmdDXBindStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5648 break;
5649 }
5650
5651 case SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS:
5652 {
5653 SVGA3dCmdSurfaceStretchBltNonMSToMS *pCmd = (SVGA3dCmdSurfaceStretchBltNonMSToMS *)pvCmd;
5654 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5655 rcParse = vmsvga3dCmdSurfaceStretchBltNonMSToMS(pThisCC, idDXContext, pCmd, cbCmd);
5656 break;
5657 }
5658
5659 case SVGA_3D_CMD_DX_BIND_SHADER_IFACE:
5660 {
5661 SVGA3dCmdDXBindShaderIface *pCmd = (SVGA3dCmdDXBindShaderIface *)pvCmd;
5662 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5663 rcParse = vmsvga3dCmdDXBindShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
5664 break;
5665 }
5666
5667 /* Unsupported commands. */
5668 case SVGA_3D_CMD_DEAD4: /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
5669 case SVGA_3D_CMD_DEAD5: /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
5670 case SVGA_3D_CMD_DEAD6: /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
5671 case SVGA_3D_CMD_DEAD7: /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
5672 case SVGA_3D_CMD_DEAD8: /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
5673 case SVGA_3D_CMD_DEAD9: /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
5674 case SVGA_3D_CMD_DEAD10: /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
5675 case SVGA_3D_CMD_DEAD11: /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
5676 /* Prevent the compiler warning. */
5677 case SVGA_3D_CMD_LEGACY_BASE:
5678 case SVGA_3D_CMD_MAX:
5679 case SVGA_3D_CMD_FUTURE_MAX:
5680 /* No 'default' case */
5681 STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
5682 ASSERT_GUEST_MSG_FAILED(("enmCmdId=%d\n", enmCmdId));
5683 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
5684 rcParse = VERR_NOT_IMPLEMENTED;
5685 break;
5686 }
5687
5688 return VINF_SUCCESS;
5689// return rcParse;
5690}
5691# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
5692#endif /* VBOX_WITH_VMSVGA3D */
5693
5694
5695/*
5696 *
5697 * Handlers for FIFO commands.
5698 *
5699 * Every handler takes the following parameters:
5700 *
5701 * pThis The shared VGA/VMSVGA state.
5702 * pThisCC The VGA/VMSVGA state for ring-3.
5703 * pCmd The command data.
5704 */
5705
5706
5707/* SVGA_CMD_UPDATE */
5708void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
5709{
5710 RT_NOREF(pThis);
5711 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5712
5713 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
5714 Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
5715
5716 /** @todo Multiple screens? */
5717 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5718 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
5719 return;
5720
5721 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
5722}
5723
5724
5725/* SVGA_CMD_UPDATE_VERBOSE */
5726void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
5727{
5728 RT_NOREF(pThis);
5729 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5730
5731 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
5732 Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
5733
5734 /** @todo Multiple screens? */
5735 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5736 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
5737 return;
5738
5739 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
5740}
5741
5742
5743/* SVGA_CMD_RECT_FILL */
5744void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
5745{
5746 RT_NOREF(pThis, pCmd);
5747 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5748
5749 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
5750 Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
5751 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
5752}
5753
5754
5755/* SVGA_CMD_RECT_COPY */
5756void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
5757{
5758 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5759
5760 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
5761 Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
5762
5763 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5764 AssertPtrReturnVoid(pScreen);
5765
5766 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
5767 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
5768 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
5769 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
5770 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
5771 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
5772 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
5773
5774 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
5775 pCmd->width, pCmd->height, pThis->vram_size);
5776 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
5777}
5778
5779
5780/* SVGA_CMD_RECT_ROP_COPY */
5781void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
5782{
5783 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5784
5785 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
5786 Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
5787
5788 if (pCmd->rop != SVGA_ROP_COPY)
5789 {
5790 /* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
5791 * as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
5792 * respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
5793 * SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
5794 */
5795 LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
5796 pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
5797 return;
5798 }
5799
5800 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5801 AssertPtrReturnVoid(pScreen);
5802
5803 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
5804 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
5805 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
5806 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
5807 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
5808 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
5809 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
5810
5811 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
5812 pCmd->width, pCmd->height, pThis->vram_size);
5813 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
5814}
5815
5816
5817/* SVGA_CMD_DISPLAY_CURSOR */
5818void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
5819{
5820 RT_NOREF(pThis, pCmd);
5821 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5822
5823 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
5824 Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
5825 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
5826}
5827
5828
5829/* SVGA_CMD_MOVE_CURSOR */
5830void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
5831{
5832 RT_NOREF(pThis, pCmd);
5833 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5834
5835 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
5836 Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
5837 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
5838}
5839
5840
5841/* SVGA_CMD_DEFINE_CURSOR */
5842void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
5843{
5844 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5845
5846 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
5847 Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
5848 pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
5849
5850 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
5851 ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
5852 ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
5853 RT_UNTRUSTED_VALIDATED_FENCE();
5854
5855 uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
5856 uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
5857 uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
5858
5859 uint8_t const *pbSrcAndMask = (uint8_t const *)(pCmd + 1);
5860 uint8_t const *pbSrcXorMask = (uint8_t const *)(pCmd + 1) + cbSrcAndMask;
5861
5862 uint32_t const cx = pCmd->width;
5863 uint32_t const cy = pCmd->height;
5864
5865 /*
5866 * Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
5867 * The AND data uses 8-bit aligned scanlines.
5868 * The XOR data must be starting on a 32-bit boundrary.
5869 */
5870 uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
5871 uint32_t cbDstAndMask = cbDstAndLine * cy;
5872 uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
5873 uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
5874
5875 uint8_t *pbCopy = (uint8_t *)RTMemAlloc(cbCopy);
5876 AssertReturnVoid(pbCopy);
5877
5878 /* Convert the AND mask. */
5879 uint8_t *pbDst = pbCopy;
5880 uint8_t const *pbSrc = pbSrcAndMask;
5881 switch (pCmd->andMaskDepth)
5882 {
5883 case 1:
5884 if (cbSrcAndLine == cbDstAndLine)
5885 memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
5886 else
5887 {
5888 Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
5889 for (uint32_t y = 0; y < cy; y++)
5890 {
5891 memcpy(pbDst, pbSrc, cbDstAndLine);
5892 pbDst += cbDstAndLine;
5893 pbSrc += cbSrcAndLine;
5894 }
5895 }
5896 break;
5897 /* Should take the XOR mask into account for the multi-bit AND mask. */
5898 case 8:
5899 for (uint32_t y = 0; y < cy; y++)
5900 {
5901 for (uint32_t x = 0; x < cx; )
5902 {
5903 uint8_t bDst = 0;
5904 uint8_t fBit = 0x80;
5905 do
5906 {
5907 uintptr_t const idxPal = pbSrc[x] * 3;
5908 if ((( pThis->last_palette[idxPal]
5909 | (pThis->last_palette[idxPal] >> 8)
5910 | (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
5911 bDst |= fBit;
5912 fBit >>= 1;
5913 x++;
5914 } while (x < cx && (x & 7));
5915 pbDst[(x - 1) / 8] = bDst;
5916 }
5917 pbDst += cbDstAndLine;
5918 pbSrc += cbSrcAndLine;
5919 }
5920 break;
5921 case 15:
5922 for (uint32_t y = 0; y < cy; y++)
5923 {
5924 for (uint32_t x = 0; x < cx; )
5925 {
5926 uint8_t bDst = 0;
5927 uint8_t fBit = 0x80;
5928 do
5929 {
5930 if ((pbSrc[x * 2] | (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
5931 bDst |= fBit;
5932 fBit >>= 1;
5933 x++;
5934 } while (x < cx && (x & 7));
5935 pbDst[(x - 1) / 8] = bDst;
5936 }
5937 pbDst += cbDstAndLine;
5938 pbSrc += cbSrcAndLine;
5939 }
5940 break;
5941 case 16:
5942 for (uint32_t y = 0; y < cy; y++)
5943 {
5944 for (uint32_t x = 0; x < cx; )
5945 {
5946 uint8_t bDst = 0;
5947 uint8_t fBit = 0x80;
5948 do
5949 {
5950 if ((pbSrc[x * 2] | pbSrc[x * 2 + 1]) >= 0xfc)
5951 bDst |= fBit;
5952 fBit >>= 1;
5953 x++;
5954 } while (x < cx && (x & 7));
5955 pbDst[(x - 1) / 8] = bDst;
5956 }
5957 pbDst += cbDstAndLine;
5958 pbSrc += cbSrcAndLine;
5959 }
5960 break;
5961 case 24:
5962 for (uint32_t y = 0; y < cy; y++)
5963 {
5964 for (uint32_t x = 0; x < cx; )
5965 {
5966 uint8_t bDst = 0;
5967 uint8_t fBit = 0x80;
5968 do
5969 {
5970 if ((pbSrc[x * 3] | pbSrc[x * 3 + 1] | pbSrc[x * 3 + 2]) >= 0xfc)
5971 bDst |= fBit;
5972 fBit >>= 1;
5973 x++;
5974 } while (x < cx && (x & 7));
5975 pbDst[(x - 1) / 8] = bDst;
5976 }
5977 pbDst += cbDstAndLine;
5978 pbSrc += cbSrcAndLine;
5979 }
5980 break;
5981 case 32:
5982 for (uint32_t y = 0; y < cy; y++)
5983 {
5984 for (uint32_t x = 0; x < cx; )
5985 {
5986 uint8_t bDst = 0;
5987 uint8_t fBit = 0x80;
5988 do
5989 {
5990 if ((pbSrc[x * 4] | pbSrc[x * 4 + 1] | pbSrc[x * 4 + 2] | pbSrc[x * 4 + 3]) >= 0xfc)
5991 bDst |= fBit;
5992 fBit >>= 1;
5993 x++;
5994 } while (x < cx && (x & 7));
5995 pbDst[(x - 1) / 8] = bDst;
5996 }
5997 pbDst += cbDstAndLine;
5998 pbSrc += cbSrcAndLine;
5999 }
6000 break;
6001 default:
6002 RTMemFreeZ(pbCopy, cbCopy);
6003 AssertFailedReturnVoid();
6004 }
6005
6006 /* Convert the XOR mask. */
6007 uint32_t *pu32Dst = (uint32_t *)(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
6008 pbSrc = pbSrcXorMask;
6009 switch (pCmd->xorMaskDepth)
6010 {
6011 case 1:
6012 for (uint32_t y = 0; y < cy; y++)
6013 {
6014 for (uint32_t x = 0; x < cx; )
6015 {
6016 /* most significant bit is the left most one. */
6017 uint8_t bSrc = pbSrc[x / 8];
6018 do
6019 {
6020 *pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
6021 bSrc <<= 1;
6022 x++;
6023 } while ((x & 7) && x < cx);
6024 }
6025 pbSrc += cbSrcXorLine;
6026 }
6027 break;
6028 case 8:
6029 for (uint32_t y = 0; y < cy; y++)
6030 {
6031 for (uint32_t x = 0; x < cx; x++)
6032 {
6033 uint32_t u = pThis->last_palette[pbSrc[x]];
6034 *pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
6035 }
6036 pbSrc += cbSrcXorLine;
6037 }
6038 break;
6039 case 15: /* Src: RGB-5-5-5 */
6040 for (uint32_t y = 0; y < cy; y++)
6041 {
6042 for (uint32_t x = 0; x < cx; x++)
6043 {
6044 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6045 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6046 ((uValue >> 5) & 0x1f) << 3,
6047 ((uValue >> 10) & 0x1f) << 3, 0);
6048 }
6049 pbSrc += cbSrcXorLine;
6050 }
6051 break;
6052 case 16: /* Src: RGB-5-6-5 */
6053 for (uint32_t y = 0; y < cy; y++)
6054 {
6055 for (uint32_t x = 0; x < cx; x++)
6056 {
6057 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6058 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6059 ((uValue >> 5) & 0x3f) << 2,
6060 ((uValue >> 11) & 0x1f) << 3, 0);
6061 }
6062 pbSrc += cbSrcXorLine;
6063 }
6064 break;
6065 case 24:
6066 for (uint32_t y = 0; y < cy; y++)
6067 {
6068 for (uint32_t x = 0; x < cx; x++)
6069 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*3], pbSrc[x*3 + 1], pbSrc[x*3 + 2], 0);
6070 pbSrc += cbSrcXorLine;
6071 }
6072 break;
6073 case 32:
6074 for (uint32_t y = 0; y < cy; y++)
6075 {
6076 for (uint32_t x = 0; x < cx; x++)
6077 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*4], pbSrc[x*4 + 1], pbSrc[x*4 + 2], 0);
6078 pbSrc += cbSrcXorLine;
6079 }
6080 break;
6081 default:
6082 RTMemFreeZ(pbCopy, cbCopy);
6083 AssertFailedReturnVoid();
6084 }
6085
6086 /*
6087 * Pass it to the frontend/whatever.
6088 */
6089 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6090 cx, cy, pbCopy, cbCopy);
6091}
6092
6093
6094/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
6095void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
6096{
6097 RT_NOREF(pThis);
6098 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6099
6100 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
6101 Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
6102
6103 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
6104 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6105 RT_UNTRUSTED_VALIDATED_FENCE();
6106
6107 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
6108 uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
6109 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
6110 uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
6111 uint32_t cbCursorShape = cbAndMask + cbXorMask;
6112
6113 uint8_t *pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
6114 AssertPtrReturnVoid(pCursorCopy);
6115
6116 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
6117 memset(pCursorCopy, 0xff, cbAndMask);
6118 /* Colour data */
6119 memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
6120
6121 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6122 pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
6123}
6124
6125
6126/* SVGA_CMD_ESCAPE */
6127void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
6128{
6129 RT_NOREF(pThis);
6130 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6131
6132 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
6133
6134 if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
6135 {
6136 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
6137 RT_UNTRUSTED_VALIDATED_FENCE();
6138
6139 uint32_t const cmd = *(uint32_t *)(pCmd + 1);
6140 Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
6141
6142 switch (cmd)
6143 {
6144 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
6145 {
6146 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pCmd + 1);
6147 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
6148 RT_UNTRUSTED_VALIDATED_FENCE();
6149
6150 uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
6151
6152 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
6153 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
6154 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
6155 RT_NOREF_PV(pVideoCmd);
6156 break;
6157 }
6158
6159 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
6160 {
6161 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pCmd + 1);
6162 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
6163 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
6164 RT_NOREF_PV(pVideoCmd);
6165 break;
6166 }
6167
6168 default:
6169 Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
6170 break;
6171 }
6172 }
6173 else
6174 Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
6175}
6176
6177
6178/* SVGA_CMD_DEFINE_SCREEN */
6179void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
6180{
6181 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6182
6183 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
6184 Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
6185 pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
6186 pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
6187
6188 uint32_t const idScreen = pCmd->screen.id;
6189 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6190
6191 uint32_t const uWidth = pCmd->screen.size.width;
6192 ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
6193
6194 uint32_t const uHeight = pCmd->screen.size.height;
6195 ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
6196
6197 uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
6198 uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
6199 ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
6200
6201 uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
6202 ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
6203
6204 uint32_t const cbVram = pThis->vram_size - uScreenOffset;
6205 /* If we have a not zero pitch, then height can't exceed the available VRAM. */
6206 ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
6207 || (cbPitch > 0 && uHeight <= cbVram / cbPitch));
6208 RT_UNTRUSTED_VALIDATED_FENCE();
6209
6210 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6211 pScreen->fDefined = true;
6212 pScreen->fModified = true;
6213 pScreen->fuScreen = pCmd->screen.flags;
6214 pScreen->idScreen = idScreen;
6215 if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE | SVGA_SCREEN_BLANKING)))
6216 {
6217 /* Not blanked. */
6218 ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
6219 RT_UNTRUSTED_VALIDATED_FENCE();
6220
6221 pScreen->xOrigin = pCmd->screen.root.x;
6222 pScreen->yOrigin = pCmd->screen.root.y;
6223 pScreen->cWidth = uWidth;
6224 pScreen->cHeight = uHeight;
6225 pScreen->offVRAM = uScreenOffset;
6226 pScreen->cbPitch = cbPitch;
6227 pScreen->cBpp = 32;
6228 }
6229 else
6230 {
6231 /* Screen blanked. Keep old values. */
6232 }
6233
6234 pThis->svga.fGFBRegisters = false;
6235 vmsvgaR3ChangeMode(pThis, pThisCC);
6236
6237#ifdef VBOX_WITH_VMSVGA3D
6238 if (RT_LIKELY(pThis->svga.f3DEnabled))
6239 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
6240#endif
6241}
6242
6243
6244/* SVGA_CMD_DESTROY_SCREEN */
6245void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
6246{
6247 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6248
6249 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
6250 Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
6251
6252 uint32_t const idScreen = pCmd->screenId;
6253 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6254 RT_UNTRUSTED_VALIDATED_FENCE();
6255
6256 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6257 pScreen->fModified = true;
6258 pScreen->fDefined = false;
6259 pScreen->idScreen = idScreen;
6260
6261#ifdef VBOX_WITH_VMSVGA3D
6262 if (RT_LIKELY(pThis->svga.f3DEnabled))
6263 vmsvga3dDestroyScreen(pThisCC, pScreen);
6264#endif
6265 vmsvgaR3ChangeMode(pThis, pThisCC);
6266}
6267
6268
6269/* SVGA_CMD_DEFINE_GMRFB */
6270void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
6271{
6272 RT_NOREF(pThis);
6273 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6274
6275 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
6276 Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
6277 pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
6278
6279 pSvgaR3State->GMRFB.ptr = pCmd->ptr;
6280 pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
6281 pSvgaR3State->GMRFB.format = pCmd->format;
6282}
6283
6284
6285/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
6286void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
6287{
6288 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6289
6290 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
6291 Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
6292 pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
6293
6294 ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6295 RT_UNTRUSTED_VALIDATED_FENCE();
6296
6297 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
6298 AssertPtrReturnVoid(pScreen);
6299
6300 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
6301 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6302
6303 /* Clip destRect to the screen dimensions. */
6304 SVGASignedRect screenRect;
6305 screenRect.left = 0;
6306 screenRect.top = 0;
6307 screenRect.right = pScreen->cWidth;
6308 screenRect.bottom = pScreen->cHeight;
6309 SVGASignedRect clipRect = pCmd->destRect;
6310 vmsvgaR3ClipRect(&screenRect, &clipRect);
6311 RT_UNTRUSTED_VALIDATED_FENCE();
6312
6313 uint32_t const width = clipRect.right - clipRect.left;
6314 uint32_t const height = clipRect.bottom - clipRect.top;
6315
6316 if ( width == 0
6317 || height == 0)
6318 return; /* Nothing to do. */
6319
6320 int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
6321 int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
6322
6323 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6324 * Prepare parameters for vmsvgaR3GmrTransfer.
6325 */
6326 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6327
6328 /* Destination: host buffer which describes the screen 0 VRAM.
6329 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6330 */
6331 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6332 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6333 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6334 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6335 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6336 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6337 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6338 + cbScanline * clipRect.top;
6339 int32_t const cbHstPitch = cbScanline;
6340
6341 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6342 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6343 uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6344 + pSvgaR3State->GMRFB.bytesPerLine * srcy;
6345 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6346
6347 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
6348 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6349 gstPtr, offGst, cbGstPitch,
6350 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6351 AssertRC(rc);
6352 vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
6353}
6354
6355
6356/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
6357void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
6358{
6359 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6360
6361 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
6362 /* Note! This can fetch 3d render results as well!! */
6363 Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
6364 pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
6365
6366 ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6367 RT_UNTRUSTED_VALIDATED_FENCE();
6368
6369 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
6370 AssertPtrReturnVoid(pScreen);
6371
6372 /** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
6373 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6374
6375 /* Clip destRect to the screen dimensions. */
6376 SVGASignedRect screenRect;
6377 screenRect.left = 0;
6378 screenRect.top = 0;
6379 screenRect.right = pScreen->cWidth;
6380 screenRect.bottom = pScreen->cHeight;
6381 SVGASignedRect clipRect = pCmd->srcRect;
6382 vmsvgaR3ClipRect(&screenRect, &clipRect);
6383 RT_UNTRUSTED_VALIDATED_FENCE();
6384
6385 uint32_t const width = clipRect.right - clipRect.left;
6386 uint32_t const height = clipRect.bottom - clipRect.top;
6387
6388 if ( width == 0
6389 || height == 0)
6390 return; /* Nothing to do. */
6391
6392 int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
6393 int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
6394
6395 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6396 * Prepare parameters for vmsvgaR3GmrTransfer.
6397 */
6398 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6399
6400 /* Source: host buffer which describes the screen 0 VRAM.
6401 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6402 */
6403 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6404 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6405 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6406 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6407 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6408 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6409 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6410 + cbScanline * clipRect.top;
6411 int32_t const cbHstPitch = cbScanline;
6412
6413 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6414 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6415 uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6416 + pSvgaR3State->GMRFB.bytesPerLine * dsty;
6417 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6418
6419 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
6420 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6421 gstPtr, offGst, cbGstPitch,
6422 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6423 AssertRC(rc);
6424}
6425
6426
6427/* SVGA_CMD_ANNOTATION_FILL */
6428void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
6429{
6430 RT_NOREF(pThis);
6431 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6432
6433 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
6434 Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
6435
6436 pSvgaR3State->colorAnnotation = pCmd->color;
6437}
6438
6439
6440/* SVGA_CMD_ANNOTATION_COPY */
6441void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
6442{
6443 RT_NOREF(pThis, pCmd);
6444 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6445
6446 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
6447 Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
6448
6449 AssertFailed();
6450}
6451
6452
6453#ifdef VBOX_WITH_VMSVGA3D
6454/* SVGA_CMD_DEFINE_GMR2 */
6455void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
6456{
6457 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6458
6459 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
6460 Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
6461
6462 /* Validate current GMR id. */
6463 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6464 ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
6465 RT_UNTRUSTED_VALIDATED_FENCE();
6466
6467 if (!pCmd->numPages)
6468 {
6469 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
6470 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6471 }
6472 else
6473 {
6474 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6475 if (pGMR->cMaxPages)
6476 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
6477
6478 /* Not sure if we should always free the descriptor, but for simplicity
6479 we do so if the new size is smaller than the current. */
6480 /** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
6481 if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
6482 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6483
6484 pGMR->cMaxPages = pCmd->numPages;
6485 /* The rest is done by the REMAP_GMR2 command. */
6486 }
6487}
6488
6489
6490/* SVGA_CMD_REMAP_GMR2 */
6491void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
6492{
6493 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6494
6495 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
6496 Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
6497
6498 /* Validate current GMR id and size. */
6499 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6500 RT_UNTRUSTED_VALIDATED_FENCE();
6501 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6502 ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
6503 <= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
6504 ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
6505
6506 if (pCmd->numPages == 0)
6507 return;
6508 RT_UNTRUSTED_VALIDATED_FENCE();
6509
6510 /* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
6511 uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
6512
6513 /*
6514 * We flatten the existing descriptors into a page array, overwrite the
6515 * pages specified in this command and then recompress the descriptor.
6516 */
6517 /** @todo Optimize the GMR remap algorithm! */
6518
6519 /* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
6520 uint64_t *paNewPage64 = NULL;
6521 if (pGMR->paDesc)
6522 {
6523 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
6524
6525 paNewPage64 = (uint64_t *)RTMemAllocZ(cNewTotalPages * sizeof(uint64_t));
6526 AssertPtrReturnVoid(paNewPage64);
6527
6528 uint32_t idxPage = 0;
6529 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
6530 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
6531 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
6532 AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
6533 RT_UNTRUSTED_VALIDATED_FENCE();
6534 }
6535
6536 /* Free the old GMR if present. */
6537 if (pGMR->paDesc)
6538 RTMemFree(pGMR->paDesc);
6539
6540 /* Allocate the maximum amount possible (everything non-continuous) */
6541 PVMSVGAGMRDESCRIPTOR paDescs;
6542 pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
6543 AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
6544
6545 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
6546 {
6547 /** @todo */
6548 AssertFailed();
6549 pGMR->numDescriptors = 0;
6550 }
6551 else
6552 {
6553 uint32_t *paPages32 = (uint32_t *)(pCmd + 1);
6554 uint64_t *paPages64 = (uint64_t *)(pCmd + 1);
6555 bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
6556
6557 uint32_t cPages;
6558 if (paNewPage64)
6559 {
6560 /* Overwrite the old page array with the new page values. */
6561 if (fGCPhys64)
6562 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6563 paNewPage64[i] = paPages64[i - pCmd->offsetPages];
6564 else
6565 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6566 paNewPage64[i] = paPages32[i - pCmd->offsetPages];
6567
6568 /* Use the updated page array instead of the command data. */
6569 fGCPhys64 = true;
6570 paPages64 = paNewPage64;
6571 cPages = cNewTotalPages;
6572 }
6573 else
6574 cPages = pCmd->numPages;
6575
6576 /* The first page. */
6577 /** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
6578 * applied to paNewPage64. */
6579 RTGCPHYS GCPhys;
6580 if (fGCPhys64)
6581 GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6582 else
6583 GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
6584 paDescs[0].GCPhys = GCPhys;
6585 paDescs[0].numPages = 1;
6586
6587 /* Subsequent pages. */
6588 uint32_t iDescriptor = 0;
6589 for (uint32_t i = 1; i < cPages; i++)
6590 {
6591 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
6592 GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6593 else
6594 GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
6595
6596 /* Continuous physical memory? */
6597 if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
6598 {
6599 Assert(paDescs[iDescriptor].numPages);
6600 paDescs[iDescriptor].numPages++;
6601 Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
6602 }
6603 else
6604 {
6605 iDescriptor++;
6606 paDescs[iDescriptor].GCPhys = GCPhys;
6607 paDescs[iDescriptor].numPages = 1;
6608 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
6609 }
6610 }
6611
6612 pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
6613 Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
6614 pGMR->numDescriptors = iDescriptor + 1;
6615 }
6616
6617 if (paNewPage64)
6618 RTMemFree(paNewPage64);
6619}
6620
6621
6622/**
6623 * Free the specified GMR
6624 *
6625 * @param pThisCC The VGA/VMSVGA state for ring-3.
6626 * @param idGMR GMR id
6627 */
6628void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
6629{
6630 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6631
6632 /* Free the old descriptor if present. */
6633 PGMR pGMR = &pSVGAState->paGMR[idGMR];
6634 if ( pGMR->numDescriptors
6635 || pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
6636 {
6637# ifdef DEBUG_GMR_ACCESS
6638 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
6639# endif
6640
6641 Assert(pGMR->paDesc);
6642 RTMemFree(pGMR->paDesc);
6643 pGMR->paDesc = NULL;
6644 pGMR->numDescriptors = 0;
6645 pGMR->cbTotal = 0;
6646 pGMR->cMaxPages = 0;
6647 }
6648 Assert(!pGMR->cMaxPages);
6649 Assert(!pGMR->cbTotal);
6650}
6651#endif /* VBOX_WITH_VMSVGA3D */
6652
6653
6654/**
6655 * Copy between a GMR and a host memory buffer.
6656 *
6657 * @returns VBox status code.
6658 * @param pThis The shared VGA/VMSVGA instance data.
6659 * @param pThisCC The VGA/VMSVGA state for ring-3.
6660 * @param enmTransferType Transfer type (read/write)
6661 * @param pbHstBuf Host buffer pointer (valid)
6662 * @param cbHstBuf Size of host buffer (valid)
6663 * @param offHst Host buffer offset of the first scanline
6664 * @param cbHstPitch Destination buffer pitch
6665 * @param gstPtr GMR description
6666 * @param offGst Guest buffer offset of the first scanline
6667 * @param cbGstPitch Guest buffer pitch
6668 * @param cbWidth Width in bytes to copy
6669 * @param cHeight Number of scanllines to copy
6670 */
6671int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
6672 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
6673 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
6674 uint32_t cbWidth, uint32_t cHeight)
6675{
6676 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6677 PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
6678 int rc;
6679
6680 LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
6681 enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
6682 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6683 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
6684 AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
6685
6686 PGMR pGMR;
6687 uint32_t cbGmr; /* The GMR size in bytes. */
6688 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
6689 {
6690 pGMR = NULL;
6691 cbGmr = pThis->vram_size;
6692 }
6693 else
6694 {
6695 AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
6696 RT_UNTRUSTED_VALIDATED_FENCE();
6697 pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
6698 cbGmr = pGMR->cbTotal;
6699 }
6700
6701 /*
6702 * GMR
6703 */
6704 /* Calculate GMR offset of the data to be copied. */
6705 AssertMsgReturn(gstPtr.offset < cbGmr,
6706 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6707 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6708 VERR_INVALID_PARAMETER);
6709 RT_UNTRUSTED_VALIDATED_FENCE();
6710 AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
6711 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6712 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6713 VERR_INVALID_PARAMETER);
6714 RT_UNTRUSTED_VALIDATED_FENCE();
6715 uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
6716
6717 /* Verify that cbWidth is less than scanline and fits into the GMR. */
6718 uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
6719 AssertMsgReturn(cbGmrScanline != 0,
6720 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6721 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6722 VERR_INVALID_PARAMETER);
6723 RT_UNTRUSTED_VALIDATED_FENCE();
6724 AssertMsgReturn(cbWidth <= cbGmrScanline,
6725 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6726 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6727 VERR_INVALID_PARAMETER);
6728 AssertMsgReturn(cbWidth <= cbGmr - offGmr,
6729 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6730 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6731 VERR_INVALID_PARAMETER);
6732 RT_UNTRUSTED_VALIDATED_FENCE();
6733
6734 /* How many bytes are available for the data in the GMR. */
6735 uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
6736
6737 /* How many scanlines would fit into the available data. */
6738 uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
6739 uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
6740 if (cbWidth <= cbGmrLastScanline)
6741 ++cGmrScanlines;
6742
6743 if (cHeight > cGmrScanlines)
6744 cHeight = cGmrScanlines;
6745
6746 AssertMsgReturn(cHeight > 0,
6747 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6748 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6749 VERR_INVALID_PARAMETER);
6750 RT_UNTRUSTED_VALIDATED_FENCE();
6751
6752 /*
6753 * Host buffer.
6754 */
6755 AssertMsgReturn(offHst < cbHstBuf,
6756 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6757 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6758 VERR_INVALID_PARAMETER);
6759
6760 /* Verify that cbWidth is less than scanline and fits into the buffer. */
6761 uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
6762 AssertMsgReturn(cbHstScanline != 0,
6763 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6764 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6765 VERR_INVALID_PARAMETER);
6766 AssertMsgReturn(cbWidth <= cbHstScanline,
6767 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6768 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6769 VERR_INVALID_PARAMETER);
6770 AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
6771 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6772 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6773 VERR_INVALID_PARAMETER);
6774
6775 /* How many bytes are available for the data in the buffer. */
6776 uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
6777
6778 /* How many scanlines would fit into the available data. */
6779 uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
6780 uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
6781 if (cbWidth <= cbHstLastScanline)
6782 ++cHstScanlines;
6783
6784 if (cHeight > cHstScanlines)
6785 cHeight = cHstScanlines;
6786
6787 AssertMsgReturn(cHeight > 0,
6788 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6789 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6790 VERR_INVALID_PARAMETER);
6791
6792 uint8_t *pbHst = pbHstBuf + offHst;
6793
6794 /* Shortcut for the framebuffer. */
6795 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
6796 {
6797 uint8_t *pbGst = pThisCC->pbVRam + offGmr;
6798
6799 uint8_t const *pbSrc;
6800 int32_t cbSrcPitch;
6801 uint8_t *pbDst;
6802 int32_t cbDstPitch;
6803
6804 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
6805 {
6806 pbSrc = pbHst;
6807 cbSrcPitch = cbHstPitch;
6808 pbDst = pbGst;
6809 cbDstPitch = cbGstPitch;
6810 }
6811 else
6812 {
6813 pbSrc = pbGst;
6814 cbSrcPitch = cbGstPitch;
6815 pbDst = pbHst;
6816 cbDstPitch = cbHstPitch;
6817 }
6818
6819 if ( cbWidth == (uint32_t)cbGstPitch
6820 && cbGstPitch == cbHstPitch)
6821 {
6822 /* Entire scanlines, positive pitch. */
6823 memcpy(pbDst, pbSrc, cbWidth * cHeight);
6824 }
6825 else
6826 {
6827 for (uint32_t i = 0; i < cHeight; ++i)
6828 {
6829 memcpy(pbDst, pbSrc, cbWidth);
6830
6831 pbDst += cbDstPitch;
6832 pbSrc += cbSrcPitch;
6833 }
6834 }
6835 return VINF_SUCCESS;
6836 }
6837
6838 AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
6839 AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
6840
6841 PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
6842 uint32_t iDesc = 0; /* Index in the descriptor array. */
6843 uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
6844 uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
6845 uint8_t *pbHstScanline = pbHst; /* Host address of the scanline which is being copied. */
6846 for (uint32_t i = 0; i < cHeight; ++i)
6847 {
6848 uint32_t cbCurrentWidth = cbWidth;
6849 uint32_t offGmrCurrent = offGmrScanline;
6850 uint8_t *pbCurrentHost = pbHstScanline;
6851
6852 /* Find the right descriptor */
6853 while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
6854 {
6855 offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
6856 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
6857 ++iDesc;
6858 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
6859 }
6860
6861 while (cbCurrentWidth)
6862 {
6863 uint32_t cbToCopy;
6864
6865 if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
6866 {
6867 cbToCopy = cbCurrentWidth;
6868 }
6869 else
6870 {
6871 cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
6872 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
6873 }
6874
6875 RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
6876
6877 Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
6878
6879 /*
6880 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
6881 * guest-side VMSVGA driver seems to allocate non-DMA (physical memory) addresses,
6882 * see @bugref{9654#c75}.
6883 */
6884 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
6885 rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
6886 else
6887 rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
6888 AssertRCBreak(rc);
6889
6890 cbCurrentWidth -= cbToCopy;
6891 offGmrCurrent += cbToCopy;
6892 pbCurrentHost += cbToCopy;
6893
6894 /* Go to the next descriptor if there's anything left. */
6895 if (cbCurrentWidth)
6896 {
6897 offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
6898 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
6899 ++iDesc;
6900 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
6901 }
6902 }
6903
6904 offGmrScanline += cbGstPitch;
6905 pbHstScanline += cbHstPitch;
6906 }
6907
6908 return VINF_SUCCESS;
6909}
6910
6911
6912/**
6913 * Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
6914 *
6915 * @param pSizeSrc Source surface dimensions.
6916 * @param pSizeDest Destination surface dimensions.
6917 * @param pBox Coordinates to be clipped.
6918 */
6919void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox)
6920{
6921 /* Src x, w */
6922 if (pBox->srcx > pSizeSrc->width)
6923 pBox->srcx = pSizeSrc->width;
6924 if (pBox->w > pSizeSrc->width - pBox->srcx)
6925 pBox->w = pSizeSrc->width - pBox->srcx;
6926
6927 /* Src y, h */
6928 if (pBox->srcy > pSizeSrc->height)
6929 pBox->srcy = pSizeSrc->height;
6930 if (pBox->h > pSizeSrc->height - pBox->srcy)
6931 pBox->h = pSizeSrc->height - pBox->srcy;
6932
6933 /* Src z, d */
6934 if (pBox->srcz > pSizeSrc->depth)
6935 pBox->srcz = pSizeSrc->depth;
6936 if (pBox->d > pSizeSrc->depth - pBox->srcz)
6937 pBox->d = pSizeSrc->depth - pBox->srcz;
6938
6939 /* Dest x, w */
6940 if (pBox->x > pSizeDest->width)
6941 pBox->x = pSizeDest->width;
6942 if (pBox->w > pSizeDest->width - pBox->x)
6943 pBox->w = pSizeDest->width - pBox->x;
6944
6945 /* Dest y, h */
6946 if (pBox->y > pSizeDest->height)
6947 pBox->y = pSizeDest->height;
6948 if (pBox->h > pSizeDest->height - pBox->y)
6949 pBox->h = pSizeDest->height - pBox->y;
6950
6951 /* Dest z, d */
6952 if (pBox->z > pSizeDest->depth)
6953 pBox->z = pSizeDest->depth;
6954 if (pBox->d > pSizeDest->depth - pBox->z)
6955 pBox->d = pSizeDest->depth - pBox->z;
6956}
6957
6958
6959/**
6960 * Unsigned coordinates in pBox. Clip to [0; pSize).
6961 *
6962 * @param pSize Source surface dimensions.
6963 * @param pBox Coordinates to be clipped.
6964 */
6965void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox)
6966{
6967 /* x, w */
6968 if (pBox->x > pSize->width)
6969 pBox->x = pSize->width;
6970 if (pBox->w > pSize->width - pBox->x)
6971 pBox->w = pSize->width - pBox->x;
6972
6973 /* y, h */
6974 if (pBox->y > pSize->height)
6975 pBox->y = pSize->height;
6976 if (pBox->h > pSize->height - pBox->y)
6977 pBox->h = pSize->height - pBox->y;
6978
6979 /* z, d */
6980 if (pBox->z > pSize->depth)
6981 pBox->z = pSize->depth;
6982 if (pBox->d > pSize->depth - pBox->z)
6983 pBox->d = pSize->depth - pBox->z;
6984}
6985
6986
6987/**
6988 * Clip.
6989 *
6990 * @param pBound Bounding rectangle.
6991 * @param pRect Rectangle to be clipped.
6992 */
6993void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect)
6994{
6995 int32_t left;
6996 int32_t top;
6997 int32_t right;
6998 int32_t bottom;
6999
7000 /* Right order. */
7001 Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
7002 if (pRect->left < pRect->right)
7003 {
7004 left = pRect->left;
7005 right = pRect->right;
7006 }
7007 else
7008 {
7009 left = pRect->right;
7010 right = pRect->left;
7011 }
7012 if (pRect->top < pRect->bottom)
7013 {
7014 top = pRect->top;
7015 bottom = pRect->bottom;
7016 }
7017 else
7018 {
7019 top = pRect->bottom;
7020 bottom = pRect->top;
7021 }
7022
7023 if (left < pBound->left)
7024 left = pBound->left;
7025 if (right < pBound->left)
7026 right = pBound->left;
7027
7028 if (left > pBound->right)
7029 left = pBound->right;
7030 if (right > pBound->right)
7031 right = pBound->right;
7032
7033 if (top < pBound->top)
7034 top = pBound->top;
7035 if (bottom < pBound->top)
7036 bottom = pBound->top;
7037
7038 if (top > pBound->bottom)
7039 top = pBound->bottom;
7040 if (bottom > pBound->bottom)
7041 bottom = pBound->bottom;
7042
7043 pRect->left = left;
7044 pRect->right = right;
7045 pRect->top = top;
7046 pRect->bottom = bottom;
7047}
7048
7049
7050/**
7051 * Clip.
7052 *
7053 * @param pBound Bounding rectangle.
7054 * @param pRect Rectangle to be clipped.
7055 */
7056void vmsvgaR3Clip3dRect(SVGA3dRect const *pBound, SVGA3dRect RT_UNTRUSTED_GUEST *pRect)
7057{
7058 uint32_t const leftBound = pBound->x;
7059 uint32_t const rightBound = pBound->x + pBound->w;
7060 uint32_t const topBound = pBound->y;
7061 uint32_t const bottomBound = pBound->y + pBound->h;
7062
7063 uint32_t x = pRect->x;
7064 uint32_t y = pRect->y;
7065 uint32_t w = pRect->w;
7066 uint32_t h = pRect->h;
7067
7068 /* Make sure that right and bottom coordinates can be safely computed. */
7069 if (x > rightBound)
7070 x = rightBound;
7071 if (w > rightBound - x)
7072 w = rightBound - x;
7073 if (y > bottomBound)
7074 y = bottomBound;
7075 if (h > bottomBound - y)
7076 h = bottomBound - y;
7077
7078 /* Switch from x, y, w, h to left, top, right, bottom. */
7079 uint32_t left = x;
7080 uint32_t right = x + w;
7081 uint32_t top = y;
7082 uint32_t bottom = y + h;
7083
7084 /* A standard left, right, bottom, top clipping. */
7085 if (left < leftBound)
7086 left = leftBound;
7087 if (right < leftBound)
7088 right = leftBound;
7089
7090 if (left > rightBound)
7091 left = rightBound;
7092 if (right > rightBound)
7093 right = rightBound;
7094
7095 if (top < topBound)
7096 top = topBound;
7097 if (bottom < topBound)
7098 bottom = topBound;
7099
7100 if (top > bottomBound)
7101 top = bottomBound;
7102 if (bottom > bottomBound)
7103 bottom = bottomBound;
7104
7105 /* Back to x, y, w, h representation. */
7106 pRect->x = left;
7107 pRect->y = top;
7108 pRect->w = right - left;
7109 pRect->h = bottom - top;
7110}
7111
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