| 1 | ## @file UefiCpuPkg.dec
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| 2 | # This Package provides UEFI compatible CPU modules and libraries.
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| 3 | #
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| 4 | # Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>
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| 5 | #
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| 6 | # SPDX-License-Identifier: BSD-2-Clause-Patent
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| 7 | #
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| 8 | ##
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| 9 |
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| 10 | [Defines]
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| 11 | DEC_SPECIFICATION = 0x00010005
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| 12 | PACKAGE_NAME = UefiCpuPkg
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| 13 | PACKAGE_UNI_FILE = UefiCpuPkg.uni
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| 14 | PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23
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| 15 | PACKAGE_VERSION = 0.90
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| 16 |
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| 17 | [Includes]
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| 18 | Include
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| 19 |
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| 20 | [LibraryClasses]
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| 21 | ## @libraryclass Defines some routines that are generic for IA32 family CPU
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| 22 | ## to be UEFI specification compliant.
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| 23 | ##
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| 24 | UefiCpuLib|Include/Library/UefiCpuLib.h
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| 25 |
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| 26 | ## @libraryclass Defines some routines that are used to register/manage/program
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| 27 | ## CPU features.
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| 28 | ##
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| 29 | RegisterCpuFeaturesLib|Include/Library/RegisterCpuFeaturesLib.h
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| 30 |
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| 31 | [LibraryClasses.IA32, LibraryClasses.X64]
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| 32 | ## @libraryclass Provides functions to manage MTRR settings on IA32 and X64 CPUs.
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| 33 | ##
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| 34 | MtrrLib|Include/Library/MtrrLib.h
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| 35 |
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| 36 | ## @libraryclass Provides functions to manage the Local APIC on IA32 and X64 CPUs.
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| 37 | ##
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| 38 | LocalApicLib|Include/Library/LocalApicLib.h
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| 39 |
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| 40 | ## @libraryclass Provides platform specific initialization functions in the SEC phase.
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| 41 | ##
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| 42 | PlatformSecLib|Include/Library/PlatformSecLib.h
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| 43 |
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| 44 | ## @libraryclass Public include file for the SMM CPU Platform Hook Library.
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| 45 | ##
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| 46 | SmmCpuPlatformHookLib|Include/Library/SmmCpuPlatformHookLib.h
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| 47 |
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| 48 | ## @libraryclass Provides the CPU specific programming for PiSmmCpuDxeSmm module.
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| 49 | ##
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| 50 | SmmCpuFeaturesLib|Include/Library/SmmCpuFeaturesLib.h
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| 51 |
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| 52 | ## @libraryclass Provides functions to support MP services on CpuMpPei and CpuDxe module.
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| 53 | ##
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| 54 | MpInitLib|Include/Library/MpInitLib.h
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| 55 |
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| 56 | ## @libraryclass Provides function to support CcExit processing.
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| 57 | CcExitLib|Include/Library/CcExitLib.h
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| 58 |
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| 59 | ## @libraryclass Provides function to get CPU cache information.
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| 60 | CpuCacheInfoLib|Include/Library/CpuCacheInfoLib.h
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| 61 |
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| 62 | ## @libraryclass Provides function for loading microcode.
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| 63 | MicrocodeLib|Include/Library/MicrocodeLib.h
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| 64 |
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| 65 | ## @libraryclass Provides function for manipulating x86 paging structures.
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| 66 | CpuPageTableLib|Include/Library/CpuPageTableLib.h
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| 67 |
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| 68 | [Guids]
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| 69 | gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}
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| 70 | gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}
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| 71 |
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| 72 | ## Include/Guid/CpuFeaturesSetDone.h
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| 73 | gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}
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| 74 |
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| 75 | ## Include/Guid/CpuFeaturesInitDone.h
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| 76 | gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}
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| 77 |
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| 78 | ## Include/Guid/MicrocodePatchHob.h
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| 79 | gEdkiiMicrocodePatchHobGuid = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}
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| 80 |
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| 81 | [Protocols]
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| 82 | ## Include/Protocol/SmmCpuService.h
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| 83 | gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}
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| 84 | gEdkiiSmmCpuRendezvousProtocolGuid = { 0xaa00d50b, 0x4911, 0x428f, { 0xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }}
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| 85 |
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| 86 | ## Include/Protocol/SmMonitorInit.h
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| 87 | gEfiSmMonitorInitProtocolGuid = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}
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| 88 |
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| 89 | [Protocols.RISCV64]
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| 90 | #
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| 91 | # Protocols defined for RISC-V systems
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| 92 | #
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| 93 | ## Include/Protocol/RiscVBootProtocol.h
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| 94 | gRiscVEfiBootProtocolGuid = { 0xccd15fec, 0x6f73, 0x4eec, { 0x83, 0x95, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf }}
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| 95 |
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| 96 | #
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| 97 | # [Error.gUefiCpuPkgTokenSpaceGuid]
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| 98 | # 0x80000001 | Invalid value provided.
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| 99 | #
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| 100 |
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| 101 | [Ppis]
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| 102 | gEdkiiPeiMpServices2PpiGuid = { 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba}}
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| 103 |
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| 104 | ## Include/Ppi/ShadowMicrocode.h
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| 105 | gEdkiiPeiShadowMicrocodePpiGuid = { 0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 }}
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| 106 |
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| 107 | ## Include/Ppi/RepublishSecPpi.h
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| 108 | gRepublishSecPpiPpiGuid = { 0x27a71b1e, 0x73ee, 0x43d6, { 0xac, 0xe3, 0x52, 0x1a, 0x2d, 0xc5, 0xd0, 0x92 }}
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| 109 |
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| 110 | [PcdsFeatureFlag]
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| 111 | ## Indicates if SMM Profile will be enabled.
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| 112 | # If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.
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| 113 | # In X64 build, it could not be enabled when PcdCpuSmmRestrictedMemoryAccess is TRUE.
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| 114 | # In IA32 build, the page table memory is not marked as read-only when it is enabled.
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| 115 | # This PCD is only for validation purpose. It should be set to false in production.<BR><BR>
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| 116 | # TRUE - SMM Profile will be enabled.<BR>
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| 117 | # FALSE - SMM Profile will be disabled.<BR>
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| 118 | # @Prompt Enable SMM Profile.
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| 119 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109
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| 120 |
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| 121 | ## Indicates if the SMM profile log buffer is a ring buffer.
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| 122 | # If disabled, no additional log can be done when the buffer is full.<BR><BR>
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| 123 | # TRUE - the SMM profile log buffer is a ring buffer.<BR>
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| 124 | # FALSE - the SMM profile log buffer is a normal buffer.<BR>
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| 125 | # @Prompt The SMM profile log buffer is a ring buffer.
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| 126 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a
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| 127 |
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| 128 | ## Indicates if SMM Startup AP in a blocking fashion.
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| 129 | # TRUE - SMM Startup AP in a blocking fashion.<BR>
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| 130 | # FALSE - SMM Startup AP in a non-blocking fashion.<BR>
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| 131 | # @Prompt SMM Startup AP in a blocking fashion.
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| 132 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108
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| 133 |
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| 134 | ## Indicates if SMM Stack Guard will be enabled.
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| 135 | # If enabled, stack overflow in SMM can be caught, preventing chaotic consequences.<BR><BR>
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| 136 | # TRUE - SMM Stack Guard will be enabled.<BR>
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| 137 | # FALSE - SMM Stack Guard will be disabled.<BR>
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| 138 | # @Prompt Enable SMM Stack Guard.
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| 139 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|TRUE|BOOLEAN|0x1000001C
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| 140 |
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| 141 | ## Indicates if BSP election in SMM will be enabled.
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| 142 | # If enabled, a BSP will be dynamically elected among all processors in each SMI.
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| 143 | # Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>
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| 144 | # TRUE - BSP election in SMM will be enabled.<BR>
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| 145 | # FALSE - BSP election in SMM will be disabled.<BR>
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| 146 | # @Prompt Enable BSP election in SMM.
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| 147 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106
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| 148 |
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| 149 | ## Indicates if CPU SMM hot-plug will be enabled.<BR><BR>
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| 150 | # TRUE - SMM CPU hot-plug will be enabled.<BR>
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| 151 | # FALSE - SMM CPU hot-plug will be disabled.<BR>
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| 152 | # @Prompt SMM CPU hot-plug.
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| 153 | gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C
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| 154 |
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| 155 | ## Indicates if SMM Debug will be enabled.
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| 156 | # If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>
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| 157 | # TRUE - SMM Debug will be enabled.<BR>
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| 158 | # FALSE - SMM Debug will be disabled.<BR>
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| 159 | # @Prompt Enable SMM Debug.
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| 160 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B
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| 161 |
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| 162 | ## Indicates if lock SMM Feature Control MSR.<BR><BR>
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| 163 | # TRUE - SMM Feature Control MSR will be locked.<BR>
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| 164 | # FALSE - SMM Feature Control MSR will not be locked.<BR>
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| 165 | # @Prompt Lock SMM Feature Control MSR.
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| 166 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B
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| 167 |
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| 168 | ## Indicates if SMRR will be enabled.<BR><BR>
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| 169 | # TRUE - SMRR will be enabled.<BR>
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| 170 | # FALSE - SMRR will not be enabled.<BR>
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| 171 | # @Prompt Enable SMRR.
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| 172 | gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable|TRUE|BOOLEAN|0x3213210D
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| 173 |
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| 174 | ## Indicates if SmmFeatureControl will be enabled.<BR><BR>
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| 175 | # TRUE - SmmFeatureControl will be enabled.<BR>
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| 176 | # FALSE - SmmFeatureControl will not be enabled.<BR>
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| 177 | # @Prompt Support SmmFeatureControl.
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| 178 | gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable|TRUE|BOOLEAN|0x32132110
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| 179 |
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| 180 | [PcdsFixedAtBuild]
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| 181 | ## List of exception vectors which need switching stack.
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| 182 | # This PCD will only take into effect if PcdCpuStackGuard is enabled.
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| 183 | # By default exception #DD(8), #PF(14) are supported.
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| 184 | # @Prompt Specify exception vectors which need switching stack.
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| 185 | gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList|{0x08, 0x0E}|VOID*|0x30002000
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| 186 |
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| 187 | ## Size of good stack for an exception.
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| 188 | # This PCD will only take into effect if PcdCpuStackGuard is enabled.
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| 189 | # @Prompt Specify size of good stack of exception which need switching stack.
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| 190 | gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001
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| 191 |
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| 192 | ## Count of pre allocated SMM MP tokens per chunk.
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| 193 | # @Prompt Specify the count of pre allocated SMM MP tokens per chunk.
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| 194 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk|64|UINT32|0x30002002
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| 195 |
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| 196 | ## Area of memory where the SEV-ES work area block lives.
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| 197 | # @Prompt Configure the SEV-ES work area base
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| 198 | gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase|0x0|UINT32|0x30002005
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| 199 |
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| 200 | ## Size of teh area of memory where the SEV-ES work area block lives.
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| 201 | # @Prompt Configure the SEV-ES work area base
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| 202 | gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize|0x0|UINT32|0x30002006
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| 203 |
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| 204 | [PcdsFixedAtBuild, PcdsPatchableInModule]
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| 205 | ## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.
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| 206 | # @Prompt Configure base address of CPU Local APIC
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| 207 | # @Expression 0x80000001 | (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0
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| 208 | gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress|0xfee00000|UINT32|0x00000001
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| 209 |
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| 210 | ## Specifies delay value in microseconds after sending out an INIT IPI.
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| 211 | # @Prompt Configure delay value after send an INIT IPI
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| 212 | gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10000|UINT32|0x30000002
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| 213 |
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| 214 | ## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must
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| 215 | ## aligns the address on a 4-KByte boundary.
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| 216 | # @Prompt Configure stack size for Application Processor (AP)
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| 217 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x8000|UINT32|0x00000003
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| 218 |
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| 219 | ## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.
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| 220 | # @Prompt Stack size in the temporary RAM.
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| 221 | gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003
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| 222 |
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| 223 | ## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.
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| 224 | # @Prompt SMM profile data buffer size.
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| 225 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107
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| 226 |
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| 227 | ## Specifies stack size in bytes for each processor in SMM.
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| 228 | # @Prompt Processor stack size in SMM.
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| 229 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105
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| 230 |
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| 231 | ## Specifies shadow stack size in bytes for each processor in SMM.
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| 232 | # @Prompt Processor shadow stack size in SMM.
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| 233 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize|0x2000|UINT32|0x3213210E
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| 234 |
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| 235 | ## Indicates if SMM Code Access Check is enabled.
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| 236 | # If enabled, the SMM handler cannot execute the code outside SMM regions.
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| 237 | # This PCD is suggested to TRUE in production image.<BR><BR>
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| 238 | # TRUE - SMM Code Access Check will be enabled.<BR>
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| 239 | # FALSE - SMM Code Access Check will be disabled.<BR>
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| 240 | # @Prompt SMM Code Access Check.
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| 241 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013
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| 242 |
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| 243 | ## Specifies the number of variable MTRRs reserved for OS use. The default number of
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| 244 | # MTRRs reserved for OS use is 2.
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| 245 | # @Prompt Number of reserved variable MTRRs.
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| 246 | gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x2|UINT32|0x00000015
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| 247 |
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| 248 | ## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.
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| 249 | # @Prompt STM exception stack size.
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| 250 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize|0x1000|UINT32|0x32132111
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| 251 |
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| 252 | ## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.
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| 253 | # @Prompt MSEG size.
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| 254 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x200000|UINT32|0x32132112
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| 255 |
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| 256 | ## Specifies the supported CPU features bit in array.
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| 257 | # @Prompt Supported CPU features.
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| 258 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x00000016
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| 259 |
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| 260 | ## Specifies if CPU features will be initialized after SMM relocation.
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| 261 | # @Prompt If CPU features will be initialized after SMM relocation.
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| 262 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation|FALSE|BOOLEAN|0x0000001C
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| 263 |
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| 264 | ## Specifies if CPU features will be initialized during S3 resume.
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| 265 | # @Prompt If CPU features will be initialized during S3 resume.
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| 266 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D
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| 267 |
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| 268 | ## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.
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| 269 | # TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.
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| 270 | # Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 (25MHz)
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| 271 | # 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family = 24000000 (24MHz)
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| 272 | # Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH = 19200000 (19.2MHz)
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| 273 | # @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX
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| 274 | gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000|UINT64|0x32132113
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| 275 |
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| 276 | ## Specifies the periodic interval value in microseconds for the status check
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| 277 | # of APs for StartupAllAPs() and StartupThisAP() executed in non-blocking
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| 278 | # mode in DXE phase.
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| 279 | # @Prompt Periodic interval value in microseconds for AP status check in DXE.
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| 280 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds|100000|UINT32|0x0000001E
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| 281 |
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| 282 | [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
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| 283 | ## Specifies max supported number of Logical Processors.
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| 284 | # @Prompt Configure max supported number of Logical Processors
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| 285 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002
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| 286 | ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
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| 287 | # @Prompt Timeout for the BSP to detect all APs for the first time.
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| 288 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004
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| 289 | ## Specifies the number of Logical Processors that are available in the
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| 290 | # preboot environment after platform reset, including BSP and APs. Possible
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| 291 | # values:<BR><BR>
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| 292 | # zero (default) - PcdCpuBootLogicalProcessorNumber is ignored, and
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| 293 | # PcdCpuApInitTimeOutInMicroSeconds limits the initial AP
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| 294 | # detection by the BSP.<BR>
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| 295 | # nonzero - PcdCpuApInitTimeOutInMicroSeconds is ignored. The initial
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| 296 | # AP detection finishes only when the detected CPU count
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| 297 | # (BSP plus APs) reaches the value of
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| 298 | # PcdCpuBootLogicalProcessorNumber, regardless of how long
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| 299 | # that takes.<BR>
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| 300 | # @Prompt Number of Logical Processors available after platform reset.
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| 301 | gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber|0|UINT32|0x00000008
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| 302 | ## Specifies the base address of the first microcode Patch in the microcode Region.
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| 303 | # @Prompt Microcode Region base address.
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| 304 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005
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| 305 | ## Specifies the size of the microcode Region.
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| 306 | # @Prompt Microcode Region size.
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| 307 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006
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| 308 | ## Specifies the AP wait loop state during POST phase.
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| 309 | # The value is defined as below.<BR><BR>
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| 310 | # 1: Place AP in the Hlt-Loop state.<BR>
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| 311 | # 2: Place AP in the Mwait-Loop state.<BR>
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| 312 | # 3: Place AP in the Run-Loop state.<BR>
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| 313 | # @Prompt The AP wait loop state.
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| 314 | # @ValidRange 0x80000001 | 1 - 3
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| 315 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006
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| 316 | ## Specifies the AP target C-state for Mwait during POST phase.
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| 317 | # The default value 0 means C1 state.
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| 318 | # The value is defined as below.<BR><BR>
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| 319 | # @Prompt The specified AP target C-state for Mwait.
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| 320 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007
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| 321 |
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| 322 | ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.
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| 323 | # @Prompt AP synchronization timeout value in SMM.
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| 324 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104
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| 325 |
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| 326 | ## Indicates the CPU synchronization method used when processing an SMI.
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| 327 | # 0x00 - Traditional CPU synchronization method.<BR>
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| 328 | # 0x01 - Relaxed CPU synchronization method.<BR>
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| 329 | # @Prompt SMM CPU Synchronization Method.
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| 330 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014
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| 331 |
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| 332 | ## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.
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| 333 | # @Prompt The encoded values for target duty cycle modulation.
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| 334 | # @ValidRange 0x80000001 | 0 - 15
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| 335 | gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0x0|UINT8|0x0000001A
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| 336 |
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| 337 | ## Indicates if the current boot is a power-on reset.<BR><BR>
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| 338 | # TRUE - Current boot is a power-on reset.<BR>
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| 339 | # FALSE - Current boot is not a power-on reset.<BR>
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| 340 | # @Prompt Current boot is a power-on reset.
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| 341 | gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B
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| 342 |
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| 343 | [PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, PcdsDynamicEx.X64]
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| 344 | ## Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
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| 345 | # MMIO access is always allowed regardless of the value of this PCD.
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| 346 | # Loose of such restriction is only required by RAS components in X64 platforms.
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| 347 | # The PCD value is considered as constantly TRUE in IA32 platforms.
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| 348 | # When the PCD value is TRUE, page table is initialized to cover all memory spaces
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| 349 | # and the memory occupied by page table is protected by page table itself as read-only.
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| 350 | # In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).
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| 351 | # In X64 build, it could not be enabled also at the same time with heap guard feature for SMM
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| 352 | # (PcdHeapGuardPropertyMask in MdeModulePkg).
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| 353 | # In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)
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| 354 | # or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.
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| 355 | # TRUE - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.<BR>
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| 356 | # FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.<BR>
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| 357 | # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
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| 358 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
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| 359 |
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| 360 | [PcdsDynamic, PcdsDynamicEx]
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| 361 | ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
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| 362 | # @Prompt The pointer to a CPU S3 data buffer.
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| 363 | # @ValidList 0x80000001 | 0
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| 364 | gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010
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| 365 |
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| 366 | ## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.
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| 367 | # @Prompt The pointer to CPU Hot Plug Data.
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| 368 | # @ValidList 0x80000001 | 0
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| 369 | gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011
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| 370 |
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| 371 | ## Indicates processor feature capabilities, each bit corresponding to a specific feature.
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| 372 | # @Prompt Processor feature capabilities.
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| 373 | # @ValidList 0x80000001 | 0
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| 374 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000018
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| 375 |
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| 376 | ## As input, specifies user's desired settings for enabling/disabling processor features.
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| 377 | ## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.
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| 378 | # @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.
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| 379 | # @ValidList 0x80000001 | 0
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| 380 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019
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| 381 |
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| 382 | ## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>
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| 383 | # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
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| 384 | # This PCD is ignored if CPU processor trace is disabled.<BR><BR>
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| 385 | # Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>
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| 386 | # 0x0 - 4K.<BR>
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| 387 | # 0x1 - 8K.<BR>
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| 388 | # 0x2 - 16K.<BR>
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| 389 | # 0x3 - 32K.<BR>
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| 390 | # 0x4 - 64K.<BR>
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| 391 | # 0x5 - 128K.<BR>
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| 392 | # 0x6 - 256K.<BR>
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| 393 | # 0x7 - 512K.<BR>
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| 394 | # 0x8 - 1M.<BR>
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| 395 | # 0x9 - 2M.<BR>
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| 396 | # 0xA - 4M.<BR>
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|---|
| 397 | # 0xB - 8M.<BR>
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| 398 | # 0xC - 16M.<BR>
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| 399 | # 0xD - 32M.<BR>
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|---|
| 400 | # 0xE - 64M.<BR>
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|---|
| 401 | # 0xF - 128M.<BR>
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|---|
| 402 | # @Prompt The memory size used for processor trace if processor trace is enabled.
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| 403 | # @ValidRange 0x80000001 | 0 - 0xF
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| 404 | gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0|UINT32|0x60000012
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|---|
| 405 |
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|---|
| 406 | ## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>
|
|---|
| 407 | # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
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|---|
| 408 | # This PCD is ignored if CPU processor trace is disabled.<BR><BR>
|
|---|
| 409 | # Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>
|
|---|
| 410 | # 0 - Single Range output scheme.<BR>
|
|---|
| 411 | # 1 - ToPA(Table of physical address) scheme.<BR>
|
|---|
| 412 | # @Prompt The processor trace output scheme used when processor trace is enabled.
|
|---|
| 413 | # @ValidRange 0x80000001 | 0 - 1
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|---|
| 414 | gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015
|
|---|
| 415 |
|
|---|
| 416 | ## This dynamic PCD indicates whether SEV-ES is enabled
|
|---|
| 417 | # TRUE - SEV-ES is enabled
|
|---|
| 418 | # FALSE - SEV-ES is not enabled
|
|---|
| 419 | # @Prompt SEV-ES Status
|
|---|
| 420 | gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|FALSE|BOOLEAN|0x60000016
|
|---|
| 421 |
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|---|
| 422 | ## This dynamic PCD contains the hypervisor features value obtained through the GHCB HYPERVISOR
|
|---|
| 423 | # features VMGEXIT defined in the version 2 of GHCB spec.
|
|---|
| 424 | # @Prompt GHCB Hypervisor Features
|
|---|
| 425 | gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures|0x0|UINT64|0x60000018
|
|---|
| 426 |
|
|---|
| 427 | [UserExtensions.TianoCore."ExtraFiles"]
|
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| 428 | UefiCpuPkgExtra.uni
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