| 1 | ;------------------------------------------------------------------------------ ;
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| 2 | ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
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| 3 | ; This program and the accompanying materials
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| 4 | ; are licensed and made available under the terms and conditions of the BSD License
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| 5 | ; which accompanies this distribution. The full text of the license may be found at
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| 6 | ; http://opensource.org/licenses/bsd-license.php.
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| 7 | ;
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| 8 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 9 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 10 | ;
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| 11 | ; Module Name:
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| 12 | ;
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| 13 | ; SmiException.nasm
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| 14 | ;
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| 15 | ; Abstract:
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| 16 | ;
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| 17 | ; Exception handlers used in SM mode
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| 18 | ;
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| 19 | ;-------------------------------------------------------------------------------
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| 20 |
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| 21 | extern ASM_PFX(SmiPFHandler)
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| 22 |
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| 23 | global ASM_PFX(gcSmiIdtr)
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| 24 | global ASM_PFX(gcSmiGdtr)
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| 25 | global ASM_PFX(gcPsd)
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| 26 |
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| 27 | SECTION .data
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| 28 |
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| 29 | NullSeg: DQ 0 ; reserved by architecture
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| 30 | CodeSeg32:
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| 31 | DW -1 ; LimitLow
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| 32 | DW 0 ; BaseLow
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| 33 | DB 0 ; BaseMid
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| 34 | DB 0x9b
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| 35 | DB 0xcf ; LimitHigh
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| 36 | DB 0 ; BaseHigh
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| 37 | ProtModeCodeSeg32:
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| 38 | DW -1 ; LimitLow
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| 39 | DW 0 ; BaseLow
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| 40 | DB 0 ; BaseMid
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| 41 | DB 0x9b
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| 42 | DB 0xcf ; LimitHigh
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| 43 | DB 0 ; BaseHigh
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| 44 | ProtModeSsSeg32:
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| 45 | DW -1 ; LimitLow
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| 46 | DW 0 ; BaseLow
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| 47 | DB 0 ; BaseMid
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| 48 | DB 0x93
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| 49 | DB 0xcf ; LimitHigh
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| 50 | DB 0 ; BaseHigh
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| 51 | DataSeg32:
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| 52 | DW -1 ; LimitLow
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| 53 | DW 0 ; BaseLow
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| 54 | DB 0 ; BaseMid
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| 55 | DB 0x93
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| 56 | DB 0xcf ; LimitHigh
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| 57 | DB 0 ; BaseHigh
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| 58 | CodeSeg16:
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| 59 | DW -1
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| 60 | DW 0
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| 61 | DB 0
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| 62 | DB 0x9b
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| 63 | DB 0x8f
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| 64 | DB 0
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| 65 | DataSeg16:
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| 66 | DW -1
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| 67 | DW 0
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| 68 | DB 0
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| 69 | DB 0x93
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| 70 | DB 0x8f
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| 71 | DB 0
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| 72 | CodeSeg64:
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| 73 | DW -1 ; LimitLow
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| 74 | DW 0 ; BaseLow
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| 75 | DB 0 ; BaseMid
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| 76 | DB 0x9b
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| 77 | DB 0xaf ; LimitHigh
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| 78 | DB 0 ; BaseHigh
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| 79 | ; TSS Segment for X64 specially
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| 80 | TssSeg:
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| 81 | DW TSS_DESC_SIZE ; LimitLow
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| 82 | DW 0 ; BaseLow
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| 83 | DB 0 ; BaseMid
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| 84 | DB 0x89
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| 85 | DB 0x80 ; LimitHigh
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| 86 | DB 0 ; BaseHigh
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| 87 | DD 0 ; BaseUpper
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| 88 | DD 0 ; Reserved
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| 89 | GDT_SIZE equ $ - NullSeg
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| 90 |
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| 91 | ; Create TSS Descriptor just after GDT
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| 92 | TssDescriptor:
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| 93 | DD 0 ; Reserved
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| 94 | DQ 0 ; RSP0
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| 95 | DQ 0 ; RSP1
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| 96 | DQ 0 ; RSP2
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| 97 | DD 0 ; Reserved
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| 98 | DD 0 ; Reserved
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| 99 | DQ 0 ; IST1
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| 100 | DQ 0 ; IST2
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| 101 | DQ 0 ; IST3
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| 102 | DQ 0 ; IST4
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| 103 | DQ 0 ; IST5
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| 104 | DQ 0 ; IST6
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| 105 | DQ 0 ; IST7
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| 106 | DD 0 ; Reserved
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| 107 | DD 0 ; Reserved
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| 108 | DW 0 ; Reserved
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| 109 | DW 0 ; I/O Map Base Address
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| 110 | TSS_DESC_SIZE equ $ - TssDescriptor
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| 111 |
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| 112 | ;
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| 113 | ; This structure serves as a template for all processors.
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| 114 | ;
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| 115 | ASM_PFX(gcPsd):
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| 116 | DB 'PSDSIG '
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| 117 | DW PSD_SIZE
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| 118 | DW 2
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| 119 | DW 1 << 2
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| 120 | DW CODE_SEL
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| 121 | DW DATA_SEL
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| 122 | DW DATA_SEL
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| 123 | DW DATA_SEL
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| 124 | DW 0
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| 125 | DQ 0
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| 126 | DQ 0
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| 127 | DQ 0 ; fixed in InitializeMpServiceData()
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| 128 | DQ NullSeg
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| 129 | DD GDT_SIZE
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| 130 | DD 0
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| 131 | times 24 DB 0
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| 132 | DQ 0
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| 133 | PSD_SIZE equ $ - ASM_PFX(gcPsd)
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| 134 |
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| 135 | ;
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| 136 | ; CODE & DATA segments for SMM runtime
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| 137 | ;
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| 138 | CODE_SEL equ CodeSeg64 - NullSeg
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| 139 | DATA_SEL equ DataSeg32 - NullSeg
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| 140 | CODE32_SEL equ CodeSeg32 - NullSeg
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| 141 |
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| 142 | ASM_PFX(gcSmiGdtr):
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| 143 | DW GDT_SIZE - 1
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| 144 | DQ NullSeg
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| 145 |
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| 146 | ASM_PFX(gcSmiIdtr):
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| 147 | DW 0
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| 148 | DQ 0
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| 149 |
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| 150 | DEFAULT REL
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| 151 | SECTION .text
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| 152 |
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| 153 | ;------------------------------------------------------------------------------
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| 154 | ; _SmiExceptionEntryPoints is the collection of exception entrypoints followed
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| 155 | ; by a common exception handler.
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| 156 | ;
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| 157 | ; Stack frame would be as follows as specified in IA32 manuals:
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| 158 | ;
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| 159 | ; +---------------------+ <-- 16-byte aligned ensured by processor
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| 160 | ; + Old SS +
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| 161 | ; +---------------------+
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| 162 | ; + Old RSP +
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| 163 | ; +---------------------+
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| 164 | ; + RFlags +
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| 165 | ; +---------------------+
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| 166 | ; + CS +
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| 167 | ; +---------------------+
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| 168 | ; + RIP +
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| 169 | ; +---------------------+
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| 170 | ; + Error Code +
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| 171 | ; +---------------------+
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| 172 | ; + Vector Number +
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| 173 | ; +---------------------+
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| 174 | ; + RBP +
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| 175 | ; +---------------------+ <-- RBP, 16-byte aligned
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| 176 | ;
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| 177 | ; RSP set to odd multiple of 8 at @CommonEntryPoint means ErrCode PRESENT
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| 178 | ;------------------------------------------------------------------------------
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| 179 | global ASM_PFX(PageFaultIdtHandlerSmmProfile)
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| 180 | ASM_PFX(PageFaultIdtHandlerSmmProfile):
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| 181 | push 0xe ; Page Fault
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| 182 | test spl, 8 ; odd multiple of 8 => ErrCode present
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| 183 | jnz .0
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| 184 | push qword [rsp] ; duplicate INT# if no ErrCode
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| 185 | mov qword [rsp + 8], 0
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| 186 | .0:
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| 187 | push rbp
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| 188 | mov rbp, rsp
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| 189 |
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| 190 | ;
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| 191 | ; Since here the stack pointer is 16-byte aligned, so
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| 192 | ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
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| 193 | ; is 16-byte aligned
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| 194 | ;
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| 195 |
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| 196 | ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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| 197 | ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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| 198 | push r15
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| 199 | push r14
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| 200 | push r13
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| 201 | push r12
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| 202 | push r11
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| 203 | push r10
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| 204 | push r9
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| 205 | push r8
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| 206 | push rax
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| 207 | push rcx
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| 208 | push rdx
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| 209 | push rbx
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| 210 | push qword [rbp + 48] ; RSP
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| 211 | push qword [rbp] ; RBP
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| 212 | push rsi
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| 213 | push rdi
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| 214 |
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| 215 | ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
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| 216 | movzx rax, word [rbp + 56]
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| 217 | push rax ; for ss
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| 218 | movzx rax, word [rbp + 32]
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| 219 | push rax ; for cs
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| 220 | mov rax, ds
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| 221 | push rax
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| 222 | mov rax, es
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| 223 | push rax
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| 224 | mov rax, fs
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| 225 | push rax
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| 226 | mov rax, gs
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| 227 | push rax
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| 228 |
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| 229 | ;; UINT64 Rip;
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| 230 | push qword [rbp + 24]
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| 231 |
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| 232 | ;; UINT64 Gdtr[2], Idtr[2];
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| 233 | sub rsp, 16
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| 234 | sidt [rsp]
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| 235 | sub rsp, 16
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| 236 | sgdt [rsp]
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| 237 |
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| 238 | ;; UINT64 Ldtr, Tr;
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| 239 | xor rax, rax
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| 240 | str ax
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| 241 | push rax
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| 242 | sldt ax
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| 243 | push rax
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| 244 |
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| 245 | ;; UINT64 RFlags;
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| 246 | push qword [rbp + 40]
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| 247 |
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| 248 | ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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| 249 | mov rax, cr8
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| 250 | push rax
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| 251 | mov rax, cr4
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| 252 | or rax, 0x208
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| 253 | mov cr4, rax
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| 254 | push rax
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| 255 | mov rax, cr3
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| 256 | push rax
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| 257 | mov rax, cr2
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| 258 | push rax
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| 259 | xor rax, rax
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| 260 | push rax
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| 261 | mov rax, cr0
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| 262 | push rax
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| 263 |
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| 264 | ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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| 265 | mov rax, dr7
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| 266 | push rax
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| 267 | mov rax, dr6
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| 268 | push rax
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| 269 | mov rax, dr3
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| 270 | push rax
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| 271 | mov rax, dr2
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| 272 | push rax
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| 273 | mov rax, dr1
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| 274 | push rax
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| 275 | mov rax, dr0
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| 276 | push rax
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| 277 |
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| 278 | ;; FX_SAVE_STATE_X64 FxSaveState;
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| 279 |
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| 280 | sub rsp, 512
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| 281 | mov rdi, rsp
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| 282 | db 0xf, 0xae, 00000111y ;fxsave [rdi]
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| 283 |
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| 284 | ; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
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| 285 | cld
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| 286 |
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| 287 | ;; UINT32 ExceptionData;
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| 288 | push qword [rbp + 16]
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| 289 |
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| 290 | ;; call into exception handler
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| 291 | mov rcx, [rbp + 8]
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| 292 | lea rax, [ASM_PFX(SmiPFHandler)]
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| 293 |
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| 294 | ;; Prepare parameter and call
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| 295 | mov rdx, rsp
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| 296 | ;
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| 297 | ; Per X64 calling convention, allocate maximum parameter stack space
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| 298 | ; and make sure RSP is 16-byte aligned
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| 299 | ;
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| 300 | sub rsp, 4 * 8 + 8
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| 301 | call rax
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| 302 | add rsp, 4 * 8 + 8
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| 303 | jmp .1
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| 304 |
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| 305 | .1:
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| 306 | ;; UINT64 ExceptionData;
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| 307 | add rsp, 8
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| 308 |
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| 309 | ;; FX_SAVE_STATE_X64 FxSaveState;
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| 310 |
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| 311 | mov rsi, rsp
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| 312 | db 0xf, 0xae, 00001110y ; fxrstor [rsi]
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| 313 | add rsp, 512
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| 314 |
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| 315 | ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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| 316 | ;; Skip restoration of DRx registers to support debuggers
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| 317 | ;; that set breakpoints in interrupt/exception context
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| 318 | add rsp, 8 * 6
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| 319 |
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| 320 | ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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| 321 | pop rax
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| 322 | mov cr0, rax
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| 323 | add rsp, 8 ; not for Cr1
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| 324 | pop rax
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| 325 | mov cr2, rax
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| 326 | pop rax
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| 327 | mov cr3, rax
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| 328 | pop rax
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| 329 | mov cr4, rax
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| 330 | pop rax
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| 331 | mov cr8, rax
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| 332 |
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| 333 | ;; UINT64 RFlags;
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| 334 | pop qword [rbp + 40]
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| 335 |
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| 336 | ;; UINT64 Ldtr, Tr;
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| 337 | ;; UINT64 Gdtr[2], Idtr[2];
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| 338 | ;; Best not let anyone mess with these particular registers...
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| 339 | add rsp, 48
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| 340 |
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| 341 | ;; UINT64 Rip;
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| 342 | pop qword [rbp + 24]
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| 343 |
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| 344 | ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
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| 345 | pop rax
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| 346 | ; mov gs, rax ; not for gs
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| 347 | pop rax
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| 348 | ; mov fs, rax ; not for fs
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| 349 | ; (X64 will not use fs and gs, so we do not restore it)
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| 350 | pop rax
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| 351 | mov es, rax
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| 352 | pop rax
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| 353 | mov ds, rax
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| 354 | pop qword [rbp + 32] ; for cs
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| 355 | pop qword [rbp + 56] ; for ss
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| 356 |
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| 357 | ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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| 358 | ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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| 359 | pop rdi
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| 360 | pop rsi
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| 361 | add rsp, 8 ; not for rbp
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| 362 | pop qword [rbp + 48] ; for rsp
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| 363 | pop rbx
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| 364 | pop rdx
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| 365 | pop rcx
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| 366 | pop rax
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| 367 | pop r8
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| 368 | pop r9
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| 369 | pop r10
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| 370 | pop r11
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| 371 | pop r12
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| 372 | pop r13
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| 373 | pop r14
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| 374 | pop r15
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| 375 |
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| 376 | mov rsp, rbp
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| 377 |
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| 378 | ; Enable TF bit after page fault handler runs
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| 379 | bts dword [rsp + 40], 8 ;RFLAGS
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| 380 |
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| 381 | pop rbp
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| 382 | add rsp, 16 ; skip INT# & ErrCode
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| 383 | iretq
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| 384 |
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