| 1 | #------------------------------------------------------------------------------
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| 2 | #
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| 3 | # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
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| 4 | # This program and the accompanying materials
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| 5 | # are licensed and made available under the terms and conditions of the BSD License
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| 6 | # which accompanies this distribution. The full text of the license may be found at
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| 7 | # http://opensource.org/licenses/bsd-license.php.
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| 8 | #
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| 9 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 10 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 11 | #
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| 12 | # Module Name:
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| 13 | #
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| 14 | # SmiEntry.S
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| 15 | #
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| 16 | # Abstract:
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| 17 | #
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| 18 | # Code template of the SMI handler for a particular processor
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| 19 | #
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| 20 | #------------------------------------------------------------------------------
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| 21 |
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| 22 | ASM_GLOBAL ASM_PFX(gcSmiHandlerTemplate)
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| 23 | ASM_GLOBAL ASM_PFX(gcSmiHandlerSize)
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| 24 | ASM_GLOBAL ASM_PFX(gSmiCr3)
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| 25 | ASM_GLOBAL ASM_PFX(gSmiStack)
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| 26 | ASM_GLOBAL ASM_PFX(gSmbase)
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| 27 | ASM_GLOBAL ASM_PFX(mXdSupported)
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| 28 | ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr)
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| 29 |
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| 30 | .equ MSR_IA32_MISC_ENABLE, 0x1A0
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| 31 | .equ MSR_EFER, 0xc0000080
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| 32 | .equ MSR_EFER_XD, 0x800
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| 33 |
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| 34 | #
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| 35 | # Constants relating to PROCESSOR_SMM_DESCRIPTOR
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| 36 | #
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| 37 | .equ DSC_OFFSET, 0xfb00
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| 38 | .equ DSC_GDTPTR, 0x30
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| 39 | .equ DSC_GDTSIZ, 0x38
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| 40 | .equ DSC_CS, 14
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| 41 | .equ DSC_DS, 16
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| 42 | .equ DSC_SS, 18
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| 43 | .equ DSC_OTHERSEG, 20
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| 44 | #
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| 45 | # Constants relating to CPU State Save Area
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| 46 | #
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| 47 | .equ SSM_DR6, 0xffd0
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| 48 | .equ SSM_DR7, 0xffc8
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| 49 |
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| 50 | .equ PROTECT_MODE_CS, 0x08
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| 51 | .equ PROTECT_MODE_DS, 0x20
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| 52 | .equ LONG_MODE_CS, 0x38
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| 53 | .equ TSS_SEGMENT, 0x40
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| 54 | .equ GDT_SIZE, 0x50
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| 55 |
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| 56 | .text
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| 57 |
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| 58 | ASM_PFX(gcSmiHandlerTemplate):
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| 59 |
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| 60 | _SmiEntryPoint:
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| 61 | #
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| 62 | # The encoding of BX in 16-bit addressing mode is the same as of RDI in 64-
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| 63 | # bit addressing mode. And that coincidence has been used in the following
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| 64 | # "64-bit like" 16-bit code. Be aware that once RDI is referenced as a
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| 65 | # base address register, it is actually BX that is referenced.
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| 66 | #
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| 67 | .byte 0xbb # mov bx, imm16
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| 68 | .word _GdtDesc - _SmiEntryPoint + 0x8000
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| 69 | #
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| 70 | # fix GDT descriptor
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| 71 | #
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| 72 | .byte 0x2e,0xa1 # mov ax, cs:[offset16]
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| 73 | .word DSC_OFFSET + DSC_GDTSIZ
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| 74 | .byte 0x48 # dec ax
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| 75 | .byte 0x2e
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| 76 | movl %eax, (%rdi) # mov cs:[bx], ax
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| 77 | .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
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| 78 | .word DSC_OFFSET + DSC_GDTPTR
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| 79 | .byte 0x2e
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| 80 | movw %ax, 2(%rdi)
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| 81 | .byte 0x66,0x2e
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| 82 | lgdt (%rdi)
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| 83 | #
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| 84 | # Patch ProtectedMode Segment
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| 85 | #
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| 86 | .byte 0xb8
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| 87 | .word PROTECT_MODE_CS
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| 88 | .byte 0x2e
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| 89 | movl %eax, -2(%rdi)
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| 90 | #
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| 91 | # Patch ProtectedMode entry
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| 92 | #
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| 93 | .byte 0x66, 0xbf # mov edi, SMBASE
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| 94 | ASM_PFX(gSmbase): .space 4
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| 95 | lea ((ProtectedMode - _SmiEntryPoint) + 0x8000)(%edi), %ax
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| 96 | .byte 0x2e
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| 97 | movw %ax, -6(%rdi)
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| 98 | #
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| 99 | # Switch into ProtectedMode
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| 100 | #
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| 101 | movq %cr0, %rbx
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| 102 | .byte 0x66
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| 103 | andl $0x9ffafff3, %ebx
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| 104 | .byte 0x66
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| 105 | orl $0x00000023, %ebx
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| 106 |
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| 107 | movq %rbx, %cr0
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| 108 | .byte 0x66, 0xea
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| 109 | .space 6
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| 110 |
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| 111 | _GdtDesc: .space 6
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| 112 |
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| 113 | ProtectedMode:
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| 114 | movw $PROTECT_MODE_DS, %ax
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| 115 | movl %eax, %ds
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| 116 | movl %eax, %es
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| 117 | movl %eax, %fs
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| 118 | movl %eax, %gs
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| 119 | movl %eax, %ss
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| 120 | .byte 0xbc # mov esp, imm32
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| 121 | ASM_PFX(gSmiStack): .space 4
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| 122 | jmp ProtFlatMode
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| 123 |
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| 124 | ProtFlatMode:
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| 125 | .byte 0xb8
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| 126 | ASM_PFX(gSmiCr3): .space 4
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| 127 | movq %rax, %cr3
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| 128 | movl $0x668,%eax # as cr4.PGE is not set here, refresh cr3
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| 129 | movq %rax, %cr4 # in PreModifyMtrrs() to flush TLB.
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| 130 | # Load TSS
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| 131 | subl $8, %esp # reserve room in stack
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| 132 | sgdt (%rsp)
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| 133 | movl 2(%rsp), %eax # eax = GDT base
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| 134 | addl $8, %esp
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| 135 | movb $0x89, %dl
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| 136 | movb %dl, (TSS_SEGMENT + 5)(%rax) # clear busy flag
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| 137 | movl $TSS_SEGMENT, %eax
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| 138 | ltr %ax
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| 139 |
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| 140 | # enable NXE if supported
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| 141 | .byte 0xb0 # mov al, imm8
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| 142 | ASM_PFX(mXdSupported): .byte 1
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| 143 | cmpb $0, %al
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| 144 | jz SkipNxe
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| 145 | #
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| 146 | # Check XD disable bit
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| 147 | #
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| 148 | movl $MSR_IA32_MISC_ENABLE, %ecx
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| 149 | rdmsr
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| 150 | subl $4, %esp
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| 151 | pushq %rdx # save MSR_IA32_MISC_ENABLE[63-32]
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| 152 | testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
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| 153 | jz L13
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| 154 | andw $0x0FFFB, %dx # clear XD Disable bit if it is set
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| 155 | wrmsr
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| 156 | L13:
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| 157 | movl $MSR_EFER, %ecx
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| 158 | rdmsr
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| 159 | orw $MSR_EFER_XD,%ax # enable NXE
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| 160 | wrmsr
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| 161 | jmp NxeDone
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| 162 | SkipNxe:
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| 163 | subl $8, %esp
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| 164 | NxeDone:
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| 165 |
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| 166 | #
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| 167 | # Switch to LongMode
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| 168 | #
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| 169 | pushq $LONG_MODE_CS # push cs hardcore here
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| 170 | call Base # push return address for retf later
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| 171 | Base:
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| 172 | addl $(LongMode - Base), (%rsp) # offset for far retf, seg is the 1st arg
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| 173 |
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| 174 | movl $MSR_EFER, %ecx
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| 175 | rdmsr
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| 176 | orb $1,%ah # enable LME
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| 177 | wrmsr
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| 178 | movq %cr0, %rbx
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| 179 | orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
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| 180 | movq %rbx, %cr0
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| 181 | retf
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| 182 | LongMode: # long mode (64-bit code) starts here
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| 183 | movabsq $ASM_PFX(gSmiHandlerIdtr), %rax
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| 184 | lidt (%rax)
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| 185 | lea (DSC_OFFSET)(%rdi), %ebx
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| 186 | movw DSC_DS(%rbx), %ax
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| 187 | movl %eax,%ds
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| 188 | movw DSC_OTHERSEG(%rbx), %ax
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| 189 | movl %eax,%es
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| 190 | movl %eax,%fs
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| 191 | movl %eax,%gs
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| 192 | movw DSC_SS(%rbx), %ax
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| 193 | movl %eax,%ss
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| 194 | # jmp _SmiHandler ; instruction is not needed
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| 195 |
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| 196 | _SmiHandler:
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| 197 | movq 8(%rsp), %rbx
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| 198 | # Save FP registers
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| 199 |
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| 200 | subq $0x200, %rsp
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| 201 | .byte 0x48 # FXSAVE64
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| 202 | fxsave (%rsp)
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| 203 |
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| 204 | addq $-0x20, %rsp
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| 205 |
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| 206 | movq %rbx, %rcx
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| 207 | movabsq $ASM_PFX(CpuSmmDebugEntry), %rax
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| 208 | call *%rax
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| 209 |
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| 210 | movq %rbx, %rcx
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| 211 | movabsq $ASM_PFX(SmiRendezvous), %rax
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| 212 | call *%rax
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| 213 |
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| 214 | movq %rbx, %rcx
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| 215 | movabsq $ASM_PFX(CpuSmmDebugExit), %rax
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| 216 | call *%rax
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| 217 |
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| 218 | addq $0x20, %rsp
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| 219 |
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| 220 | #
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| 221 | # Restore FP registers
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| 222 | #
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| 223 | .byte 0x48 # FXRSTOR64
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| 224 | fxrstor (%rsp)
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| 225 |
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| 226 | addq $0x200, %rsp
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| 227 |
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| 228 | movabsq $ASM_PFX(mXdSupported), %rax
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| 229 | movb (%rax), %al
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| 230 | cmpb $0, %al
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| 231 | jz L16
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| 232 | popq %rdx # get saved MSR_IA32_MISC_ENABLE[63-32]
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| 233 | testl $BIT2, %edx
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| 234 | jz L16
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| 235 | movl $MSR_IA32_MISC_ENABLE, %ecx
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| 236 | rdmsr
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| 237 | orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
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| 238 | wrmsr
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| 239 |
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| 240 | L16:
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| 241 | rsm
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| 242 |
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| 243 | ASM_PFX(gcSmiHandlerSize): .word . - _SmiEntryPoint
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