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source: vbox/trunk/src/VBox/Devices/EFI/FirmwareNew/MdePkg/Include/Protocol/I2cHost.h@ 80721

Last change on this file since 80721 was 80721, checked in by vboxsync, 6 years ago

Devices/EFI/FirmwareNew: Start upgrade process to edk2-stable201908 (compiles on Windows and works to some extent), bugref:4643

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1/** @file
2 I2C Host Protocol as defined in the PI 1.3 specification.
3
4 This protocol provides callers with the ability to do I/O transactions
5 to all of the devices on the I2C bus.
6
7 Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
8 SPDX-License-Identifier: BSD-2-Clause-Patent
9
10 @par Revision Reference:
11 This protocol is from PI Version 1.3.
12
13**/
14
15#ifndef __I2C_HOST_H__
16#define __I2C_HOST_H__
17
18#include <Pi/PiI2c.h>
19
20#define EFI_I2C_HOST_PROTOCOL_GUID { 0xa5aab9e3, 0xc727, 0x48cd, { 0x8b, 0xbf, 0x42, 0x72, 0x33, 0x85, 0x49, 0x48 }}
21
22///
23/// I2C Host Protocol
24///
25/// The I2C bus driver uses the services of the EFI_I2C_HOST_PROTOCOL
26/// to produce an instance of the EFI_I2C_IO_PROTOCOL for each I2C
27/// device on an I2C bus.
28///
29/// The EFI_I2C_HOST_PROTOCOL exposes an asynchronous interface to
30/// callers to perform transactions to any device on the I2C bus.
31/// Internally, the I2C host protocol manages the flow of the I2C
32/// transactions to the host controller, keeping them in FIFO order.
33/// Prior to each transaction, the I2C host protocol ensures that the
34/// switches and multiplexers are properly configured. The I2C host
35/// protocol then starts the transaction on the host controller using
36/// the EFI_I2C_MASTER_PROTOCOL.
37///
38typedef struct _EFI_I2C_HOST_PROTOCOL EFI_I2C_HOST_PROTOCOL;
39
40
41/**
42 Queue an I2C transaction for execution on the I2C controller.
43
44 This routine must be called at or below TPL_NOTIFY. For
45 synchronous requests this routine must be called at or below
46 TPL_CALLBACK.
47
48 The I2C host protocol uses the concept of I2C bus configurations
49 to describe the I2C bus. An I2C bus configuration is defined as
50 a unique setting of the multiplexers and switches in the I2C bus
51 which enable access to one or more I2C devices. When using a
52 switch to divide a bus, due to bus frequency differences, the
53 I2C bus configuration management protocol defines an I2C bus
54 configuration for the I2C devices on each side of the switch.
55 When using a multiplexer, the I2C bus configuration management
56 defines an I2C bus configuration for each of the selector values
57 required to control the multiplexer. See Figure 1 in the I2C -bus
58 specification and user manual for a complex I2C bus configuration.
59
60 The I2C host protocol processes all transactions in FIFO order.
61 Prior to performing the transaction, the I2C host protocol calls
62 EnableI2cBusConfiguration to reconfigure the switches and
63 multiplexers in the I2C bus enabling access to the specified I2C
64 device. The EnableI2cBusConfiguration also selects the I2C bus
65 frequency for the I2C device. After the I2C bus is configured,
66 the I2C host protocol calls the I2C master protocol to start the
67 I2C transaction.
68
69 When Event is NULL, QueueRequest() operates synchronously and
70 returns the I2C completion status as its return value.
71
72 When Event is not NULL, QueueRequest() synchronously returns
73 EFI_SUCCESS indicating that the asynchronously I2C transaction was
74 queued. The values above are returned in the buffer pointed to by
75 I2cStatus upon the completion of the I2C transaction when I2cStatus
76 is not NULL.
77
78 @param[in] This Pointer to an EFI_I2C_HOST_PROTOCOL structure.
79 @param[in] I2cBusConfiguration I2C bus configuration to access the I2C
80 device
81 @param[in] SlaveAddress Address of the device on the I2C bus. Set
82 the I2C_ADDRESSING_10_BIT when using 10-bit
83 addresses, clear this bit for 7-bit addressing.
84 Bits 0-6 are used for 7-bit I2C slave addresses
85 and bits 0-9 are used for 10-bit I2C slave
86 addresses.
87 @param[in] Event Event to signal for asynchronous transactions,
88 NULL for synchronous transactions
89 @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure
90 describing the I2C transaction
91 @param[out] I2cStatus Optional buffer to receive the I2C transaction
92 completion status
93
94 @retval EFI_SUCCESS The asynchronous transaction was successfully
95 queued when Event is not NULL.
96 @retval EFI_SUCCESS The transaction completed successfully when
97 Event is NULL.
98 @retval EFI_BAD_BUFFER_SIZE The RequestPacket->LengthInBytes value is
99 too large.
100 @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the
101 transaction.
102 @retval EFI_INVALID_PARAMETER RequestPacket is NULL
103 @retval EFI_NOT_FOUND Reserved bit set in the SlaveAddress parameter
104 @retval EFI_NO_MAPPING Invalid I2cBusConfiguration value
105 @retval EFI_NO_RESPONSE The I2C device is not responding to the slave
106 address. EFI_DEVICE_ERROR will be returned
107 if the controller cannot distinguish when the
108 NACK occurred.
109 @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C transaction
110 @retval EFI_UNSUPPORTED The controller does not support the requested
111 transaction.
112
113**/
114typedef
115EFI_STATUS
116(EFIAPI *EFI_I2C_HOST_PROTOCOL_QUEUE_REQUEST) (
117 IN CONST EFI_I2C_HOST_PROTOCOL *This,
118 IN UINTN I2cBusConfiguration,
119 IN UINTN SlaveAddress,
120 IN EFI_EVENT Event OPTIONAL,
121 IN EFI_I2C_REQUEST_PACKET *RequestPacket,
122 OUT EFI_STATUS *I2cStatus OPTIONAL
123 );
124
125///
126/// I2C Host Protocol
127///
128struct _EFI_I2C_HOST_PROTOCOL {
129 ///
130 /// Queue an I2C transaction for execution on the I2C bus
131 ///
132 EFI_I2C_HOST_PROTOCOL_QUEUE_REQUEST QueueRequest;
133
134 ///
135 /// Pointer to an EFI_I2C_CONTROLLER_CAPABILITIES data structure
136 /// containing the capabilities of the I2C host controller.
137 ///
138 CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;
139};
140
141///
142/// Reference to variable defined in the .DEC file
143///
144extern EFI_GUID gEfiI2cHostProtocolGuid;
145
146#endif // __I2C_HOST_H__
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