1 | /** @file
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2 | EFI MM Access PPI definition.
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3 |
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4 | This PPI is used to control the visibility of the MMRAM on the platform.
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5 | The EFI_PEI_MM_ACCESS_PPI abstracts the location and characteristics of MMRAM. The
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6 | principal functionality found in the memory controller includes the following:
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7 | - Exposing the MMRAM to all non-MM agents, or the "open" state
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8 | - Shrouding the MMRAM to all but the MM agents, or the "closed" state
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9 | - Preserving the system integrity, or "locking" the MMRAM, such that the settings cannot be
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10 | perturbed by either boot service or runtime agents
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11 |
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12 | Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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13 | SPDX-License-Identifier: BSD-2-Clause-Patent
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14 |
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15 | @par Revision Reference:
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16 | This PPI is introduced in PI Version 1.5.
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17 |
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18 | **/
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19 |
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20 | #ifndef _MM_ACCESS_PPI_H_
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21 | #define _MM_ACCESS_PPI_H_
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22 |
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23 | #define EFI_PEI_MM_ACCESS_PPI_GUID \
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24 | { 0x268f33a9, 0xcccd, 0x48be, { 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 }}
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25 |
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26 | typedef struct _EFI_PEI_MM_ACCESS_PPI EFI_PEI_MM_ACCESS_PPI;
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27 |
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28 | /**
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29 | Opens the MMRAM area to be accessible by a PEIM.
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30 |
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31 | This function "opens" MMRAM so that it is visible while not inside of MM. The function should
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32 | return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM. The function
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33 | should return EFI_DEVICE_ERROR if the MMRAM configuration is locked.
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34 |
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35 | @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
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36 | @param This The EFI_PEI_MM_ACCESS_PPI instance.
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37 | @param DescriptorIndex The region of MMRAM to Open.
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38 |
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39 | @retval EFI_SUCCESS The operation was successful.
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40 | @retval EFI_UNSUPPORTED The system does not support opening and closing of MMRAM.
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41 | @retval EFI_DEVICE_ERROR MMRAM cannot be opened, perhaps because it is locked.
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42 |
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43 | **/
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44 | typedef
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45 | EFI_STATUS
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46 | (EFIAPI *EFI_PEI_MM_OPEN)(
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47 | IN EFI_PEI_SERVICES **PeiServices,
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48 | IN EFI_PEI_MM_ACCESS_PPI *This,
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49 | IN UINTN DescriptorIndex
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50 | );
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51 |
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52 | /**
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53 | Inhibits access to the MMRAM.
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54 |
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55 | This function "closes" MMRAM so that it is not visible while outside of MM. The function should
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56 | return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM.
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57 |
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58 | @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
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59 | @param This The EFI_PEI_MM_ACCESS_PPI instance.
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60 | @param DescriptorIndex The region of MMRAM to Close.
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61 |
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62 | @retval EFI_SUCCESS The operation was successful.
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63 | @retval EFI_UNSUPPORTED The system does not support opening and closing of MMRAM.
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64 | @retval EFI_DEVICE_ERROR MMRAM cannot be closed.
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65 |
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66 | **/
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67 | typedef
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68 | EFI_STATUS
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69 | (EFIAPI *EFI_PEI_MM_CLOSE)(
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70 | IN EFI_PEI_SERVICES **PeiServices,
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71 | IN EFI_PEI_MM_ACCESS_PPI *This,
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72 | IN UINTN DescriptorIndex
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73 | );
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74 |
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75 | /**
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76 | This function prohibits access to the MMRAM region. This function is usually implemented such
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77 | that it is a write-once operation.
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78 |
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79 | @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
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80 | @param This The EFI_PEI_MM_ACCESS_PPI instance.
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81 | @param DescriptorIndex The region of MMRAM to Lock.
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82 |
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83 | @retval EFI_SUCCESS The operation was successful.
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84 | @retval EFI_UNSUPPORTED The system does not support opening and closing of MMRAM.
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85 |
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86 | **/
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87 | typedef
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88 | EFI_STATUS
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89 | (EFIAPI *EFI_PEI_MM_LOCK)(
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90 | IN EFI_PEI_SERVICES **PeiServices,
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91 | IN EFI_PEI_MM_ACCESS_PPI *This,
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92 | IN UINTN DescriptorIndex
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93 | );
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94 |
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95 | /**
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96 | Queries the memory controller for the possible regions that will support MMRAM.
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97 |
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98 | This function describes the MMRAM regions.
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99 | This data structure forms the contract between the MM_ACCESS and MM_IPL drivers. There is an
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100 | ambiguity when any MMRAM region is remapped. For example, on some chipsets, some MMRAM
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101 | regions can be initialized at one physical address but is later accessed at another processor address.
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102 | There is currently no way for the MM IPL driver to know that it must use two different addresses
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103 | depending on what it is trying to do. As a result, initial configuration and loading can use the
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104 | physical address PhysicalStart while MMRAM is open. However, once the region has been
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105 | closed and needs to be accessed by agents in MM, the CpuStart address must be used.
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106 | This PPI publishes the available memory that the chipset can shroud for the use of installing code.
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107 | These regions serve the dual purpose of describing which regions have been open, closed, or locked.
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108 | In addition, these regions may include overlapping memory ranges, depending on the chipset
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109 | implementation. The latter might include a chipset that supports T-SEG, where memory near the top
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110 | of the physical DRAM can be allocated for MMRAM too.
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111 | The key thing to note is that the regions that are described by the PPI are a subset of the capabilities
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112 | of the hardware.
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113 |
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114 | @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
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115 | @param This The EFI_PEI_MM_ACCESS_PPI instance.
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116 | @param MmramMapSize A pointer to the size, in bytes, of the MmramMemoryMap buffer. On input, this value is
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117 | the size of the buffer that is allocated by the caller. On output, it is the size of the
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118 | buffer that was returned by the firmware if the buffer was large enough, or, if the
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119 | buffer was too small, the size of the buffer that is needed to contain the map.
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120 | @param MmramMap A pointer to the buffer in which firmware places the current memory map. The map is
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121 | an array of EFI_MMRAM_DESCRIPTORs
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122 |
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123 | @retval EFI_SUCCESS The chipset supported the given resource.
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124 | @retval EFI_BUFFER_TOO_SMALL The MmramMap parameter was too small. The current
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125 | buffer size needed to hold the memory map is returned in
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126 | MmramMapSize.
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127 |
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128 | **/
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129 | typedef
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130 | EFI_STATUS
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131 | (EFIAPI *EFI_PEI_MM_CAPABILITIES)(
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132 | IN EFI_PEI_SERVICES **PeiServices,
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133 | IN EFI_PEI_MM_ACCESS_PPI *This,
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134 | IN OUT UINTN *MmramMapSize,
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135 | IN OUT EFI_MMRAM_DESCRIPTOR *MmramMap
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136 | );
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137 |
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138 | ///
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139 | /// EFI MM Access PPI is used to control the visibility of the MMRAM on the platform.
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140 | /// It abstracts the location and characteristics of MMRAM. The platform should report
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141 | /// all MMRAM via EFI_PEI_MM_ACCESS_PPI. The expectation is that the north bridge or
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142 | /// memory controller would publish this PPI.
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143 | ///
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144 | struct _EFI_PEI_MM_ACCESS_PPI {
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145 | EFI_PEI_MM_OPEN Open;
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146 | EFI_PEI_MM_CLOSE Close;
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147 | EFI_PEI_MM_LOCK Lock;
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148 | EFI_PEI_MM_CAPABILITIES GetCapabilities;
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149 | BOOLEAN LockState;
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150 | BOOLEAN OpenState;
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151 | };
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152 |
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153 | extern EFI_GUID gEfiPeiMmAccessPpiGuid;
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154 |
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155 | #endif
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