| 1 | /** @file
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| 2 |
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| 3 | Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>
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| 4 | SPDX-License-Identifier: BSD-2-Clause-Patent
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| 5 |
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| 6 | **/
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| 7 |
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| 8 | #ifndef _FSP_GLOBAL_DATA_H_
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| 9 | #define _FSP_GLOBAL_DATA_H_
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| 10 |
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| 11 | #include <FspEas.h>
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| 12 |
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| 13 | #define FSP_IN_API_MODE 0
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| 14 | #define FSP_IN_DISPATCH_MODE 1
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| 15 | #define FSP_GLOBAL_DATA_VERSION 0x3
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| 16 |
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| 17 | #pragma pack(1)
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| 18 |
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| 19 | typedef enum {
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| 20 | TempRamInitApiIndex,
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| 21 | FspInitApiIndex,
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| 22 | NotifyPhaseApiIndex,
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| 23 | FspMemoryInitApiIndex,
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| 24 | TempRamExitApiIndex,
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| 25 | FspSiliconInitApiIndex,
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| 26 | FspMultiPhaseSiInitApiIndex,
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| 27 | FspSmmInitApiIndex,
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| 28 | FspMultiPhaseMemInitApiIndex,
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| 29 | FspApiIndexMax
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| 30 | } FSP_API_INDEX;
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| 31 |
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| 32 | typedef struct {
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| 33 | VOID *DataPtr;
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| 34 | UINTN MicrocodeRegionBase;
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| 35 | UINTN MicrocodeRegionSize;
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| 36 | UINTN CodeRegionBase;
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| 37 | UINTN CodeRegionSize;
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| 38 | UINTN Reserved;
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| 39 | } FSP_PLAT_DATA;
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| 40 |
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| 41 | #define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')
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| 42 | #define FSP_PERFORMANCE_DATA_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', 'F')
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| 43 | #define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF
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| 44 |
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| 45 | typedef struct {
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| 46 | UINT32 Signature;
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| 47 | UINT8 Version;
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| 48 | UINT8 Reserved1[3];
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| 49 | ///
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| 50 | /// Offset 0x08
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| 51 | ///
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| 52 | UINTN CoreStack;
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| 53 | VOID *SmmInitUpdPtr;
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| 54 | ///
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| 55 | /// IA32: Offset 0x10; X64: Offset 0x18
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| 56 | ///
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| 57 | UINT32 StatusCode;
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| 58 | UINT8 ApiIdx;
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| 59 | ///
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| 60 | /// 0: FSP in API mode; 1: FSP in DISPATCH mode
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| 61 | ///
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| 62 | UINT8 FspMode;
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| 63 | UINT8 OnSeparateStack;
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| 64 | UINT8 Reserved2;
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| 65 | UINT32 NumberOfPhases;
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| 66 | UINT32 PhasesExecuted;
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| 67 | UINT32 Reserved3[8];
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| 68 | ///
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| 69 | /// IA32: Offset 0x40; X64: Offset 0x48
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| 70 | /// Start of UINTN and pointer section
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| 71 | /// All UINTN and pointer members are put in this section
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| 72 | /// for maintaining natural alignment for both IA32 and X64 builds.
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| 73 | ///
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| 74 | FSP_PLAT_DATA PlatformData;
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| 75 | VOID *TempRamInitUpdPtr;
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| 76 | VOID *MemoryInitUpdPtr;
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| 77 | VOID *SiliconInitUpdPtr;
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| 78 | ///
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| 79 | /// IA32: Offset 0x64; X64: Offset 0x90
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| 80 | /// To store function parameters pointer
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| 81 | /// so it can be retrieved after stack switched.
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| 82 | ///
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| 83 | VOID *FunctionParameterPtr;
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| 84 | FSP_INFO_HEADER *FspInfoHeader;
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| 85 | VOID *UpdDataPtr;
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| 86 | VOID *FspHobListPtr;
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| 87 | VOID *VariableRequestParameterPtr;
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| 88 | ///
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| 89 | /// End of UINTN and pointer section
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| 90 | /// At this point, next field offset must be either *0h or *8h to
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| 91 | /// meet natural alignment requirement.
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| 92 | ///
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| 93 | UINT8 Reserved4[16];
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| 94 | UINT32 PerfSig;
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| 95 | UINT16 PerfLen;
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| 96 | UINT16 Reserved5;
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| 97 | UINT32 PerfIdx;
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| 98 | UINT32 Reserved6;
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| 99 | UINT64 PerfData[32];
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| 100 | } FSP_GLOBAL_DATA;
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| 101 |
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| 102 | #pragma pack()
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| 103 |
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| 104 | #endif
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