| 1 | ## @file UefiCpuPkg.dec
|
|---|
| 2 | # This Package provides UEFI compatible CPU modules and libraries.
|
|---|
| 3 | #
|
|---|
| 4 | # Copyright (c) 2007 - 2023, Intel Corporation. All rights reserved.<BR>
|
|---|
| 5 | # Copyright (C) 2023 - 2024, Advanced Micro Devices, Inc. All rights reserved.<BR>
|
|---|
| 6 | # Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
|
|---|
| 7 | #
|
|---|
| 8 | # SPDX-License-Identifier: BSD-2-Clause-Patent
|
|---|
| 9 | #
|
|---|
| 10 | ##
|
|---|
| 11 |
|
|---|
| 12 | [Defines]
|
|---|
| 13 | DEC_SPECIFICATION = 0x00010005
|
|---|
| 14 | PACKAGE_NAME = UefiCpuPkg
|
|---|
| 15 | PACKAGE_UNI_FILE = UefiCpuPkg.uni
|
|---|
| 16 | PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23
|
|---|
| 17 | PACKAGE_VERSION = 0.90
|
|---|
| 18 |
|
|---|
| 19 | [Includes]
|
|---|
| 20 | Include
|
|---|
| 21 |
|
|---|
| 22 | [LibraryClasses]
|
|---|
| 23 | ## @libraryclass Defines some routines that are used to register/manage/program
|
|---|
| 24 | ## CPU features.
|
|---|
| 25 | ##
|
|---|
| 26 | RegisterCpuFeaturesLib|Include/Library/RegisterCpuFeaturesLib.h
|
|---|
| 27 |
|
|---|
| 28 | [LibraryClasses.IA32, LibraryClasses.X64]
|
|---|
| 29 | ## @libraryclass Provides functions to manage MTRR settings on IA32 and X64 CPUs.
|
|---|
| 30 | ##
|
|---|
| 31 | MtrrLib|Include/Library/MtrrLib.h
|
|---|
| 32 |
|
|---|
| 33 | ## @libraryclass Provides functions to manage the Local APIC on IA32 and X64 CPUs.
|
|---|
| 34 | ##
|
|---|
| 35 | LocalApicLib|Include/Library/LocalApicLib.h
|
|---|
| 36 |
|
|---|
| 37 | ## @libraryclass Provides platform specific initialization functions in the SEC phase.
|
|---|
| 38 | ##
|
|---|
| 39 | PlatformSecLib|Include/Library/PlatformSecLib.h
|
|---|
| 40 |
|
|---|
| 41 | ## @libraryclass Public include file for the SMM CPU Platform Hook Library.
|
|---|
| 42 | ##
|
|---|
| 43 | SmmCpuPlatformHookLib|Include/Library/SmmCpuPlatformHookLib.h
|
|---|
| 44 |
|
|---|
| 45 | ## @libraryclass Provides the CPU specific programming for PiSmmCpuDxeSmm module.
|
|---|
| 46 | ##
|
|---|
| 47 | SmmCpuFeaturesLib|Include/Library/SmmCpuFeaturesLib.h
|
|---|
| 48 |
|
|---|
| 49 | ## @libraryclass Provides functions to support MP services on CpuMpPei and CpuDxe module.
|
|---|
| 50 | ##
|
|---|
| 51 | MpInitLib|Include/Library/MpInitLib.h
|
|---|
| 52 |
|
|---|
| 53 | ## @libraryclass Provides function to support CcExit processing.
|
|---|
| 54 | CcExitLib|Include/Library/CcExitLib.h
|
|---|
| 55 |
|
|---|
| 56 | ## @libraryclass Provides function to support AmdSvsm processing.
|
|---|
| 57 | AmdSvsmLib|Include/Library/AmdSvsmLib.h
|
|---|
| 58 |
|
|---|
| 59 | ## @libraryclass Provides function to get CPU cache information.
|
|---|
| 60 | CpuCacheInfoLib|Include/Library/CpuCacheInfoLib.h
|
|---|
| 61 |
|
|---|
| 62 | ## @libraryclass Provides function for loading microcode.
|
|---|
| 63 | MicrocodeLib|Include/Library/MicrocodeLib.h
|
|---|
| 64 |
|
|---|
| 65 | ## @libraryclass Provides function for manipulating x86 paging structures.
|
|---|
| 66 | CpuPageTableLib|Include/Library/CpuPageTableLib.h
|
|---|
| 67 |
|
|---|
| 68 | ## @libraryclass Provides functions for manipulating smram savestate registers.
|
|---|
| 69 | MmSaveStateLib|Include/Library/MmSaveStateLib.h
|
|---|
| 70 |
|
|---|
| 71 | ## @libraryclass Provides functions for SMM CPU Sync Operation.
|
|---|
| 72 | SmmCpuSyncLib|Include/Library/SmmCpuSyncLib.h
|
|---|
| 73 |
|
|---|
| 74 | ## @libraryclass Provides functions for SMM Relocation Operation.
|
|---|
| 75 | SmmRelocationLib|Include/Library/SmmRelocationLib.h
|
|---|
| 76 |
|
|---|
| 77 | [LibraryClasses.RISCV64]
|
|---|
| 78 | ## @libraryclass Provides functions to manage MMU features on RISCV64 CPUs.
|
|---|
| 79 | ##
|
|---|
| 80 | RiscVMmuLib|Include/Library/BaseRiscVMmuLib.h
|
|---|
| 81 |
|
|---|
| 82 | [LibraryClasses.LoongArch64]
|
|---|
| 83 | ## @libraryclass Provides functions for the memory management unit.
|
|---|
| 84 | CpuMmuLib|Include/Library/CpuMmuLib.h
|
|---|
| 85 |
|
|---|
| 86 | [Guids]
|
|---|
| 87 | gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}
|
|---|
| 88 | gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}
|
|---|
| 89 |
|
|---|
| 90 | ## Include/Guid/CpuFeaturesSetDone.h
|
|---|
| 91 | gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}
|
|---|
| 92 |
|
|---|
| 93 | ## Include/Guid/CpuFeaturesInitDone.h
|
|---|
| 94 | gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}
|
|---|
| 95 |
|
|---|
| 96 | ## Include/Guid/MicrocodePatchHob.h
|
|---|
| 97 | gEdkiiMicrocodePatchHobGuid = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}
|
|---|
| 98 |
|
|---|
| 99 | ## Include/Guid/SmmBaseHob.h
|
|---|
| 100 | gSmmBaseHobGuid = { 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73 }}
|
|---|
| 101 |
|
|---|
| 102 | ## Include/Guid/MpInformation2.h
|
|---|
| 103 | gMpInformation2HobGuid = { 0x417a7f64, 0xf4e9, 0x4b32, {0x84, 0x6a, 0x5c, 0xc4, 0xd8, 0x62, 0x18, 0x79 }}
|
|---|
| 104 |
|
|---|
| 105 | ## Include/Guid/ProcessorResourceHob.h
|
|---|
| 106 | gProcessorResourceHobGuid = { 0xb855c7fe, 0xa758, 0x701f, { 0xa7, 0x30, 0x87, 0xf3, 0x9c, 0x03, 0x46, 0x7e }}
|
|---|
| 107 | #
|
|---|
| 108 | ## Include/Guid/GhcbApicIds.h
|
|---|
| 109 | gGhcbApicIdsGuid = { 0xbc964338, 0xee39, 0x4fc8, { 0xa2, 0x24, 0x10, 0x10, 0x8b, 0x17, 0x80, 0x1b }}
|
|---|
| 110 |
|
|---|
| 111 | [Protocols]
|
|---|
| 112 | ## Include/Protocol/SmmCpuService.h
|
|---|
| 113 | gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}
|
|---|
| 114 | gEdkiiSmmCpuRendezvousProtocolGuid = { 0xaa00d50b, 0x4911, 0x428f, { 0xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }}
|
|---|
| 115 |
|
|---|
| 116 | ## Include/Protocol/SmMonitorInit.h
|
|---|
| 117 | gEfiSmMonitorInitProtocolGuid = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}
|
|---|
| 118 |
|
|---|
| 119 | [Protocols.RISCV64]
|
|---|
| 120 | #
|
|---|
| 121 | # Protocols defined for RISC-V systems
|
|---|
| 122 | #
|
|---|
| 123 | ## Include/Protocol/RiscVBootProtocol.h
|
|---|
| 124 | gRiscVEfiBootProtocolGuid = { 0xccd15fec, 0x6f73, 0x4eec, { 0x83, 0x95, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf }}
|
|---|
| 125 |
|
|---|
| 126 | #
|
|---|
| 127 | # [Error.gUefiCpuPkgTokenSpaceGuid]
|
|---|
| 128 | # 0x80000001 | Invalid value provided.
|
|---|
| 129 | #
|
|---|
| 130 |
|
|---|
| 131 | [Ppis]
|
|---|
| 132 | gEdkiiPeiMpServices2PpiGuid = { 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba}}
|
|---|
| 133 |
|
|---|
| 134 | ## Include/Ppi/ShadowMicrocode.h
|
|---|
| 135 | gEdkiiPeiShadowMicrocodePpiGuid = { 0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 }}
|
|---|
| 136 |
|
|---|
| 137 | ## Include/Ppi/RepublishSecPpi.h
|
|---|
| 138 | gRepublishSecPpiPpiGuid = { 0x27a71b1e, 0x73ee, 0x43d6, { 0xac, 0xe3, 0x52, 0x1a, 0x2d, 0xc5, 0xd0, 0x92 }}
|
|---|
| 139 |
|
|---|
| 140 | [PcdsFeatureFlag]
|
|---|
| 141 | ## Indicates if SMM Profile will be enabled.
|
|---|
| 142 | # If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.
|
|---|
| 143 | # In X64 build, it could not be enabled when PcdCpuSmmRestrictedMemoryAccess is TRUE.
|
|---|
| 144 | # In IA32 build, the page table memory is not marked as read-only when it is enabled.
|
|---|
| 145 | # This PCD is only for validation purpose. It should be set to false in production.<BR><BR>
|
|---|
| 146 | # TRUE - SMM Profile will be enabled.<BR>
|
|---|
| 147 | # FALSE - SMM Profile will be disabled.<BR>
|
|---|
| 148 | # @Prompt Enable SMM Profile.
|
|---|
| 149 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109
|
|---|
| 150 |
|
|---|
| 151 | ## Indicates if the SMM profile log buffer is a ring buffer.
|
|---|
| 152 | # If disabled, no additional log can be done when the buffer is full.<BR><BR>
|
|---|
| 153 | # TRUE - the SMM profile log buffer is a ring buffer.<BR>
|
|---|
| 154 | # FALSE - the SMM profile log buffer is a normal buffer.<BR>
|
|---|
| 155 | # @Prompt The SMM profile log buffer is a ring buffer.
|
|---|
| 156 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a
|
|---|
| 157 |
|
|---|
| 158 | ## Indicates if SMM Startup AP in a blocking fashion.
|
|---|
| 159 | # TRUE - SMM Startup AP in a blocking fashion.<BR>
|
|---|
| 160 | # FALSE - SMM Startup AP in a non-blocking fashion.<BR>
|
|---|
| 161 | # @Prompt SMM Startup AP in a blocking fashion.
|
|---|
| 162 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108
|
|---|
| 163 |
|
|---|
| 164 | ## Indicates if SMM Stack Guard will be enabled.
|
|---|
| 165 | # If enabled, stack overflow in SMM can be caught, preventing chaotic consequences.<BR><BR>
|
|---|
| 166 | # TRUE - SMM Stack Guard will be enabled.<BR>
|
|---|
| 167 | # FALSE - SMM Stack Guard will be disabled.<BR>
|
|---|
| 168 | # @Prompt Enable SMM Stack Guard.
|
|---|
| 169 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|TRUE|BOOLEAN|0x1000001C
|
|---|
| 170 |
|
|---|
| 171 | ## Indicates if BSP election in SMM will be enabled.
|
|---|
| 172 | # If enabled, a BSP will be dynamically elected among all processors in each SMI.
|
|---|
| 173 | # Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>
|
|---|
| 174 | # TRUE - BSP election in SMM will be enabled.<BR>
|
|---|
| 175 | # FALSE - BSP election in SMM will be disabled.<BR>
|
|---|
| 176 | # @Prompt Enable BSP election in SMM.
|
|---|
| 177 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106
|
|---|
| 178 |
|
|---|
| 179 | ## Indicates if CPU SMM hot-plug will be enabled.<BR><BR>
|
|---|
| 180 | # TRUE - SMM CPU hot-plug will be enabled.<BR>
|
|---|
| 181 | # FALSE - SMM CPU hot-plug will be disabled.<BR>
|
|---|
| 182 | # @Prompt SMM CPU hot-plug.
|
|---|
| 183 | gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C
|
|---|
| 184 |
|
|---|
| 185 | ## Indicates if SMM Debug will be enabled.
|
|---|
| 186 | # If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>
|
|---|
| 187 | # TRUE - SMM Debug will be enabled.<BR>
|
|---|
| 188 | # FALSE - SMM Debug will be disabled.<BR>
|
|---|
| 189 | # @Prompt Enable SMM Debug.
|
|---|
| 190 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B
|
|---|
| 191 |
|
|---|
| 192 | ## Indicates if lock SMM Feature Control MSR.<BR><BR>
|
|---|
| 193 | # TRUE - SMM Feature Control MSR will be locked.<BR>
|
|---|
| 194 | # FALSE - SMM Feature Control MSR will not be locked.<BR>
|
|---|
| 195 | # @Prompt Lock SMM Feature Control MSR.
|
|---|
| 196 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B
|
|---|
| 197 |
|
|---|
| 198 | ## Indicates if SMRR will be enabled.<BR><BR>
|
|---|
| 199 | # TRUE - SMRR will be enabled.<BR>
|
|---|
| 200 | # FALSE - SMRR will not be enabled.<BR>
|
|---|
| 201 | # @Prompt Enable SMRR.
|
|---|
| 202 | gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable|TRUE|BOOLEAN|0x3213210D
|
|---|
| 203 |
|
|---|
| 204 | ## Indicates if SmmFeatureControl will be enabled.<BR><BR>
|
|---|
| 205 | # TRUE - SmmFeatureControl will be enabled.<BR>
|
|---|
| 206 | # FALSE - SmmFeatureControl will not be enabled.<BR>
|
|---|
| 207 | # @Prompt Support SmmFeatureControl.
|
|---|
| 208 | gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable|TRUE|BOOLEAN|0x32132110
|
|---|
| 209 |
|
|---|
| 210 | ## Indicates if SMM perf logging in APs will be enabled.<BR><BR>
|
|---|
| 211 | # TRUE - SMM perf logging in APs will be enabled.<BR>
|
|---|
| 212 | # FALSE - SMM perf logging in APs will not be enabled.<BR>
|
|---|
| 213 | # @Prompt Enable SMM perf logging in APs.
|
|---|
| 214 | gUefiCpuPkgTokenSpaceGuid.PcdSmmApPerfLogEnable|TRUE|BOOLEAN|0x32132114
|
|---|
| 215 |
|
|---|
| 216 | [PcdsFixedAtBuild]
|
|---|
| 217 | ## List of exception vectors which need switching stack.
|
|---|
| 218 | # This PCD will only take into effect if PcdCpuStackGuard is enabled.
|
|---|
| 219 | # By default exception #DD(8), #PF(14) are supported.
|
|---|
| 220 | # @Prompt Specify exception vectors which need switching stack.
|
|---|
| 221 | gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList|{0x08, 0x0E}|VOID*|0x30002000
|
|---|
| 222 |
|
|---|
| 223 | ## Size of good stack for an exception.
|
|---|
| 224 | # This PCD will only take into effect if PcdCpuStackGuard is enabled.
|
|---|
| 225 | # @Prompt Specify size of good stack of exception which need switching stack.
|
|---|
| 226 | gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001
|
|---|
| 227 |
|
|---|
| 228 | ## Count of pre allocated SMM MP tokens per chunk.
|
|---|
| 229 | # @Prompt Specify the count of pre allocated SMM MP tokens per chunk.
|
|---|
| 230 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk|64|UINT32|0x30002002
|
|---|
| 231 |
|
|---|
| 232 | ## Area of memory where the SEV-ES work area block lives.
|
|---|
| 233 | # @Prompt Configure the SEV-ES work area base
|
|---|
| 234 | gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase|0x0|UINT32|0x30002005
|
|---|
| 235 |
|
|---|
| 236 | ## Size of teh area of memory where the SEV-ES work area block lives.
|
|---|
| 237 | # @Prompt Configure the SEV-ES work area base
|
|---|
| 238 | gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize|0x0|UINT32|0x30002006
|
|---|
| 239 |
|
|---|
| 240 | ## Determining APs' first-time wakeup by SIPI or INIT-SIPI-SIPI.
|
|---|
| 241 | # Following a power-up or RESET of an MP system, The APs complete a
|
|---|
| 242 | # minimal self-configuration, then wait for a startup signal (a SIPI
|
|---|
| 243 | # message) from the BSP processor.
|
|---|
| 244 | #
|
|---|
| 245 | # TRUE - Broadcast SIPI.
|
|---|
| 246 | # FALSE - Broadcast INIT-SIPI-SIPI.
|
|---|
| 247 | #
|
|---|
| 248 | # @Prompt BSP Broadcast Method for the first-time wakeup of APs
|
|---|
| 249 | gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi|TRUE|BOOLEAN|0x30002007
|
|---|
| 250 |
|
|---|
| 251 | [PcdsFixedAtBuild, PcdsPatchableInModule]
|
|---|
| 252 | ## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.
|
|---|
| 253 | # @Prompt Configure base address of CPU Local APIC
|
|---|
| 254 | # @Expression 0x80000001 | (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0
|
|---|
| 255 | gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress|0xfee00000|UINT32|0x00000001
|
|---|
| 256 |
|
|---|
| 257 | ## Specifies delay value in microseconds after sending out an INIT IPI.
|
|---|
| 258 | # @Prompt Configure delay value after send an INIT IPI
|
|---|
| 259 | gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10000|UINT32|0x30000002
|
|---|
| 260 |
|
|---|
| 261 | ## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must
|
|---|
| 262 | ## aligns the address on a 4-KByte boundary.
|
|---|
| 263 | # @Prompt Configure stack size for Application Processor (AP)
|
|---|
| 264 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x8000|UINT32|0x00000003
|
|---|
| 265 |
|
|---|
| 266 | ## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.
|
|---|
| 267 | # @Prompt Stack size in the temporary RAM.
|
|---|
| 268 | gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003
|
|---|
| 269 |
|
|---|
| 270 | ## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.
|
|---|
| 271 | # @Prompt SMM profile data buffer size.
|
|---|
| 272 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107
|
|---|
| 273 |
|
|---|
| 274 | ## Specifies stack size in bytes for each processor in SMM.
|
|---|
| 275 | # @Prompt Processor stack size in SMM.
|
|---|
| 276 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105
|
|---|
| 277 |
|
|---|
| 278 | ## Specifies shadow stack size in bytes for each processor in SMM.
|
|---|
| 279 | # @Prompt Processor shadow stack size in SMM.
|
|---|
| 280 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize|0x2000|UINT32|0x3213210E
|
|---|
| 281 |
|
|---|
| 282 | ## Indicates if SMM Code Access Check is enabled.
|
|---|
| 283 | # If enabled, the SMM handler cannot execute the code outside SMM regions.
|
|---|
| 284 | # This PCD is suggested to TRUE in production image.<BR><BR>
|
|---|
| 285 | # TRUE - SMM Code Access Check will be enabled.<BR>
|
|---|
| 286 | # FALSE - SMM Code Access Check will be disabled.<BR>
|
|---|
| 287 | # @Prompt SMM Code Access Check.
|
|---|
| 288 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013
|
|---|
| 289 |
|
|---|
| 290 | ## Specifies the number of variable MTRRs reserved for OS use. The default number of
|
|---|
| 291 | # MTRRs reserved for OS use is 2.
|
|---|
| 292 | # @Prompt Number of reserved variable MTRRs.
|
|---|
| 293 | gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x2|UINT32|0x00000015
|
|---|
| 294 |
|
|---|
| 295 | ## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.
|
|---|
| 296 | # @Prompt STM exception stack size.
|
|---|
| 297 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize|0x1000|UINT32|0x32132111
|
|---|
| 298 |
|
|---|
| 299 | ## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.
|
|---|
| 300 | # @Prompt MSEG size.
|
|---|
| 301 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x200000|UINT32|0x32132112
|
|---|
| 302 |
|
|---|
| 303 | ## Specifies the supported CPU features bit in array.
|
|---|
| 304 | # @Prompt Supported CPU features.
|
|---|
| 305 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x00000016
|
|---|
| 306 |
|
|---|
| 307 | ## Specifies if CPU features will be initialized after SMM relocation.
|
|---|
| 308 | # @Prompt If CPU features will be initialized after SMM relocation.
|
|---|
| 309 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation|FALSE|BOOLEAN|0x0000001C
|
|---|
| 310 |
|
|---|
| 311 | ## Specifies if CPU features will be initialized during S3 resume.
|
|---|
| 312 | # @Prompt If CPU features will be initialized during S3 resume.
|
|---|
| 313 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D
|
|---|
| 314 |
|
|---|
| 315 | ## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.
|
|---|
| 316 | # TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.
|
|---|
| 317 | # Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 (25MHz)
|
|---|
| 318 | # 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family = 24000000 (24MHz)
|
|---|
| 319 | # Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH = 19200000 (19.2MHz)
|
|---|
| 320 | # @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX
|
|---|
| 321 | gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000|UINT64|0x32132113
|
|---|
| 322 |
|
|---|
| 323 | ## Specifies the periodic interval value in microseconds for the status check
|
|---|
| 324 | # of APs for StartupAllAPs() and StartupThisAP() executed in non-blocking
|
|---|
| 325 | # mode in DXE phase.
|
|---|
| 326 | # @Prompt Periodic interval value in microseconds for AP status check in DXE.
|
|---|
| 327 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds|100000|UINT32|0x0000001E
|
|---|
| 328 |
|
|---|
| 329 | [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
|
|---|
| 330 | ## Specifies max supported number of Logical Processors.
|
|---|
| 331 | # @Prompt Configure max supported number of Logical Processors
|
|---|
| 332 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002
|
|---|
| 333 | ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
|
|---|
| 334 | # @Prompt Timeout for the BSP to detect all APs for the first time.
|
|---|
| 335 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004
|
|---|
| 336 | ## Specifies the number of Logical Processors that are available in the
|
|---|
| 337 | # preboot environment after platform reset, including BSP and APs. Possible
|
|---|
| 338 | # values:<BR><BR>
|
|---|
| 339 | # zero (default) - PcdCpuBootLogicalProcessorNumber is ignored, and
|
|---|
| 340 | # PcdCpuApInitTimeOutInMicroSeconds limits the initial AP
|
|---|
| 341 | # detection by the BSP.<BR>
|
|---|
| 342 | # nonzero - PcdCpuApInitTimeOutInMicroSeconds is ignored. The initial
|
|---|
| 343 | # AP detection finishes only when the detected CPU count
|
|---|
| 344 | # (BSP plus APs) reaches the value of
|
|---|
| 345 | # PcdCpuBootLogicalProcessorNumber, regardless of how long
|
|---|
| 346 | # that takes.<BR>
|
|---|
| 347 | # @Prompt Number of Logical Processors available after platform reset.
|
|---|
| 348 | gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber|0|UINT32|0x00000008
|
|---|
| 349 | ## Specifies the base address of the first microcode Patch in the microcode Region.
|
|---|
| 350 | # @Prompt Microcode Region base address.
|
|---|
| 351 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005
|
|---|
| 352 | ## Specifies the size of the microcode Region.
|
|---|
| 353 | # @Prompt Microcode Region size.
|
|---|
| 354 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006
|
|---|
| 355 | ## Specifies the AP wait loop state during POST phase.
|
|---|
| 356 | # The value is defined as below.<BR><BR>
|
|---|
| 357 | # 1: Place AP in the Hlt-Loop state.<BR>
|
|---|
| 358 | # 2: Place AP in the Mwait-Loop state.<BR>
|
|---|
| 359 | # 3: Place AP in the Run-Loop state.<BR>
|
|---|
| 360 | # @Prompt The AP wait loop state.
|
|---|
| 361 | # @ValidRange 0x80000001 | 1 - 3
|
|---|
| 362 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006
|
|---|
| 363 | ## Specifies the AP target C-state for Mwait during POST phase.
|
|---|
| 364 | # The default value 0 means C1 state.
|
|---|
| 365 | # The value is defined as below.<BR><BR>
|
|---|
| 366 | # @Prompt The specified AP target C-state for Mwait.
|
|---|
| 367 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007
|
|---|
| 368 |
|
|---|
| 369 | ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.
|
|---|
| 370 | # @Prompt AP synchronization timeout value in SMM.
|
|---|
| 371 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104
|
|---|
| 372 |
|
|---|
| 373 | ## Indicates the CPU synchronization method used when processing an SMI.
|
|---|
| 374 | # 0x00 - Traditional CPU synchronization method.<BR>
|
|---|
| 375 | # 0x01 - Relaxed CPU synchronization method.<BR>
|
|---|
| 376 | # @Prompt SMM CPU Synchronization Method.
|
|---|
| 377 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014
|
|---|
| 378 |
|
|---|
| 379 | ## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.
|
|---|
| 380 | # @Prompt The encoded values for target duty cycle modulation.
|
|---|
| 381 | # @ValidRange 0x80000001 | 0 - 15
|
|---|
| 382 | gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0x0|UINT8|0x0000001A
|
|---|
| 383 |
|
|---|
| 384 | ## Indicates if the current boot is a power-on reset.<BR><BR>
|
|---|
| 385 | # TRUE - Current boot is a power-on reset.<BR>
|
|---|
| 386 | # FALSE - Current boot is not a power-on reset.<BR>
|
|---|
| 387 | # @Prompt Current boot is a power-on reset.
|
|---|
| 388 | gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B
|
|---|
| 389 |
|
|---|
| 390 | ## This PCD indicates whether CPU processor trace is enabled on BSP only when CPU processor trace is enabled.<BR><BR>
|
|---|
| 391 | # This PCD is ignored if CPU processor trace is disabled.<BR><BR>
|
|---|
| 392 | # TRUE - CPU processor trace is enabled on BSP only.<BR>
|
|---|
| 393 | # FASLE - CPU processor trace is enabled on all CPU.<BR>
|
|---|
| 394 | # @Prompt Enable CPU processor trace only on BSP.
|
|---|
| 395 | gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceBspOnly|FALSE|BOOLEAN|0x60000019
|
|---|
| 396 |
|
|---|
| 397 | ## This PCD indicates if enable performance collecting when CPU processor trace is enabled.<BR><BR>
|
|---|
| 398 | # CYC/TSC timing packets will be generated to collect performance data if this PCD is TRUE.
|
|---|
| 399 | # This PCD is ignored if CPU processor trace is disabled.<BR><BR>
|
|---|
| 400 | # TRUE - Performance collecting will be enabled in processor trace.<BR>
|
|---|
| 401 | # FASLE - Performance collecting will be disabled in processor trace.<BR>
|
|---|
| 402 | # @Prompt Enable performance collecting when processor trace is enabled.
|
|---|
| 403 | gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTracePerformanceCollecting|FALSE|BOOLEAN|0x60000020
|
|---|
| 404 |
|
|---|
| 405 | [PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, PcdsDynamicEx.X64]
|
|---|
| 406 | ## Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
|
|---|
| 407 | # MMIO access is always allowed regardless of the value of this PCD.
|
|---|
| 408 | # Loose of such restriction is only required by RAS components in X64 platforms.
|
|---|
| 409 | # The PCD value is considered as constantly TRUE in IA32 platforms.
|
|---|
| 410 | # When the PCD value is TRUE, page table is initialized to cover all memory spaces
|
|---|
| 411 | # and the memory occupied by page table is protected by page table itself as read-only.
|
|---|
| 412 | # In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).
|
|---|
| 413 | # In X64 build, it could not be enabled also at the same time with heap guard feature for SMM
|
|---|
| 414 | # (PcdHeapGuardPropertyMask in MdeModulePkg).
|
|---|
| 415 | # In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)
|
|---|
| 416 | # or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.
|
|---|
| 417 | # TRUE - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.<BR>
|
|---|
| 418 | # FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.<BR>
|
|---|
| 419 | # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
|
|---|
| 420 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
|
|---|
| 421 |
|
|---|
| 422 | [PcdsFixedAtBuild.RISCV64]
|
|---|
| 423 | ## Indicate the maximum SATP mode allowed.
|
|---|
| 424 | # 0 - Bare mode.
|
|---|
| 425 | # 8 - 39bit mode.
|
|---|
| 426 | # 9 - 48bit mode.
|
|---|
| 427 | # 10 - 57bit mode.
|
|---|
| 428 | gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|10|UINT32|0x60000021
|
|---|
| 429 |
|
|---|
| 430 | [PcdsFixedAtBuild.LOONGARCH64, PcdsPatchableInModule.LOONGARCH64, PcdsDynamic.LOONGARCH64, PcdsDynamicEx.LOONGARCH64]
|
|---|
| 431 | ## This PCD Contains the pointer to a CPU exception vector base address.
|
|---|
| 432 | # @Prompt The pointer to a CPU exception vector base address.
|
|---|
| 433 | gUefiCpuPkgTokenSpaceGuid.PcdLoongArchExceptionVectorBaseAddress|0x0|UINT64|0x60000022
|
|---|
| 434 |
|
|---|
| 435 | [PcdsDynamic, PcdsDynamicEx]
|
|---|
| 436 | ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
|
|---|
| 437 | # @Prompt The pointer to a CPU S3 data buffer.
|
|---|
| 438 | # @ValidList 0x80000001 | 0
|
|---|
| 439 | gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010
|
|---|
| 440 |
|
|---|
| 441 | ## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.
|
|---|
| 442 | # @Prompt The pointer to CPU Hot Plug Data.
|
|---|
| 443 | # @ValidList 0x80000001 | 0
|
|---|
| 444 | gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011
|
|---|
| 445 |
|
|---|
| 446 | ## Indicates processor feature capabilities, each bit corresponding to a specific feature.
|
|---|
| 447 | # @Prompt Processor feature capabilities.
|
|---|
| 448 | # @ValidList 0x80000001 | 0
|
|---|
| 449 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000018
|
|---|
| 450 |
|
|---|
| 451 | ## As input, specifies user's desired settings for enabling/disabling processor features.
|
|---|
| 452 | ## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.
|
|---|
| 453 | # @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.
|
|---|
| 454 | # @ValidList 0x80000001 | 0
|
|---|
| 455 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019
|
|---|
| 456 |
|
|---|
| 457 | ## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>
|
|---|
| 458 | # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
|
|---|
| 459 | # This PCD is ignored if CPU processor trace is disabled.<BR><BR>
|
|---|
| 460 | # Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>
|
|---|
| 461 | # 0x0 - 4K.<BR>
|
|---|
| 462 | # 0x1 - 8K.<BR>
|
|---|
| 463 | # 0x2 - 16K.<BR>
|
|---|
| 464 | # 0x3 - 32K.<BR>
|
|---|
| 465 | # 0x4 - 64K.<BR>
|
|---|
| 466 | # 0x5 - 128K.<BR>
|
|---|
| 467 | # 0x6 - 256K.<BR>
|
|---|
| 468 | # 0x7 - 512K.<BR>
|
|---|
| 469 | # 0x8 - 1M.<BR>
|
|---|
| 470 | # 0x9 - 2M.<BR>
|
|---|
| 471 | # 0xA - 4M.<BR>
|
|---|
| 472 | # 0xB - 8M.<BR>
|
|---|
| 473 | # 0xC - 16M.<BR>
|
|---|
| 474 | # 0xD - 32M.<BR>
|
|---|
| 475 | # 0xE - 64M.<BR>
|
|---|
| 476 | # 0xF - 128M.<BR>
|
|---|
| 477 | # @Prompt The memory size used for processor trace if processor trace is enabled.
|
|---|
| 478 | # @ValidRange 0x80000001 | 0 - 0xF
|
|---|
| 479 | gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0|UINT32|0x60000012
|
|---|
| 480 |
|
|---|
| 481 | ## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>
|
|---|
| 482 | # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
|
|---|
| 483 | # This PCD is ignored if CPU processor trace is disabled.<BR><BR>
|
|---|
| 484 | # Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>
|
|---|
| 485 | # 0 - Single Range output scheme.<BR>
|
|---|
| 486 | # 1 - ToPA(Table of physical address) scheme.<BR>
|
|---|
| 487 | # @Prompt The processor trace output scheme used when processor trace is enabled.
|
|---|
| 488 | # @ValidRange 0x80000001 | 0 - 1
|
|---|
| 489 | gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015
|
|---|
| 490 |
|
|---|
| 491 | ## This dynamic PCD indicates whether SEV-ES is enabled
|
|---|
| 492 | # TRUE - SEV-ES is enabled
|
|---|
| 493 | # FALSE - SEV-ES is not enabled
|
|---|
| 494 | # @Prompt SEV-ES Status
|
|---|
| 495 | gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|FALSE|BOOLEAN|0x60000016
|
|---|
| 496 |
|
|---|
| 497 | ## This dynamic PCD contains the hypervisor features value obtained through the GHCB HYPERVISOR
|
|---|
| 498 | # features VMGEXIT defined in the version 2 of GHCB spec.
|
|---|
| 499 | # @Prompt GHCB Hypervisor Features
|
|---|
| 500 | gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures|0x0|UINT64|0x60000018
|
|---|
| 501 |
|
|---|
| 502 | [UserExtensions.TianoCore."ExtraFiles"]
|
|---|
| 503 | UefiCpuPkgExtra.uni
|
|---|
