1 | /** @file
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2 | Implementation specific to the SmmCpuFeatureLib library instance
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3 | for AMD based platforms.
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4 |
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5 | Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
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6 | Copyright (c) Microsoft Corporation.<BR>
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7 | Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
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8 | SPDX-License-Identifier: BSD-2-Clause-Patent
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9 |
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10 | **/
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11 |
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12 | #include <Library/SmmCpuFeaturesLib.h>
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13 | #include <Uefi/UefiBaseType.h>
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14 | #include <Register/Amd/SmramSaveStateMap.h>
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15 | #include <Library/BaseLib.h>
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16 | #include <Library/DebugLib.h>
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17 | #include <Library/MmSaveStateLib.h>
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18 |
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19 | // EFER register LMA bit
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20 | #define LMA BIT10
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21 |
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22 | // Machine Specific Registers (MSRs)
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23 | #define SMMADDR_ADDRESS 0xC0010112ul
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24 | #define SMMMASK_ADDRESS 0xC0010113ul
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25 | #define EFER_ADDRESS 0XC0000080ul
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26 |
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27 | // The mode of the CPU at the time an SMI occurs
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28 | STATIC UINT8 mSmmSaveStateRegisterLma;
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29 |
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30 | /**
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31 | Performs library initialization.
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32 |
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33 | This initialization function contains common functionality shared betwen all
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34 | library instance constructors.
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35 |
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36 | **/
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37 | VOID
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38 | CpuFeaturesLibInitialization (
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39 | VOID
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40 | )
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41 | {
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42 | UINT32 LMAValue;
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43 |
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44 | LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA;
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45 | mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;
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46 | if (LMAValue) {
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47 | mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
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48 | }
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49 | }
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50 |
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51 | /**
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52 | Called during the very first SMI into System Management Mode to initialize
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53 | CPU features, including SMBASE, for the currently executing CPU. Since this
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54 | is the first SMI, the SMRAM Save State Map is at the default address of
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55 | AMD_SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing
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56 | CPU is specified by CpuIndex and CpuIndex can be used to access information
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57 | about the currently executing CPU in the ProcessorInfo array and the
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58 | HotPlugCpuData data structure.
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59 |
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60 | @param[in] CpuIndex The index of the CPU to initialize. The value
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61 | must be between 0 and the NumberOfCpus field in
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62 | the System Management System Table (SMST).
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63 | @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that
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64 | was elected as monarch during System Management
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65 | Mode initialization.
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66 | FALSE if the CpuIndex is not the index of the CPU
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67 | that was elected as monarch during System
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68 | Management Mode initialization.
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69 | @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION
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70 | structures. ProcessorInfo[CpuIndex] contains the
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71 | information for the currently executing CPU.
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72 | @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that
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73 | contains the ApidId and SmBase arrays.
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74 | **/
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75 | VOID
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76 | EFIAPI
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77 | SmmCpuFeaturesInitializeProcessor (
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78 | IN UINTN CpuIndex,
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79 | IN BOOLEAN IsMonarch,
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80 | IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,
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81 | IN CPU_HOT_PLUG_DATA *CpuHotPlugData
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82 | )
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83 | {
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84 | AMD_SMRAM_SAVE_STATE_MAP *CpuState;
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85 | UINT32 LMAValue;
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86 |
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87 | //
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88 | // Configure SMBASE.
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89 | //
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90 | CpuState = (AMD_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
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91 | CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
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92 |
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93 | // Re-initialize the value of mSmmSaveStateRegisterLma flag which might have been changed in PiCpuSmmDxeSmm Driver
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94 | // Entry point, to make sure correct value on AMD platform is assigned to be used by SmmCpuFeaturesLib.
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95 | LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA;
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96 | mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;
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97 | if (LMAValue) {
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98 | mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
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99 | }
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100 |
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101 | //
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102 | // If SMRR is supported, then program SMRR base/mask MSRs.
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103 | // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI.
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104 | // The code that initializes SMM environment is running in normal mode
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105 | // from SMRAM region. If SMRR is enabled here, then the SMRAM region
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106 | // is protected and the normal mode code execution will fail.
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107 | //
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108 | if (FeaturePcdGet (PcdSmrrEnable)) {
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109 | //
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110 | // SMRR size cannot be less than 4-KBytes
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111 | // SMRR size must be of length 2^n
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112 | // SMRR base alignment cannot be less than SMRR length
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113 | //
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114 | if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||
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115 | (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||
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116 | ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase))
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117 | {
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118 | //
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119 | // Print message and halt if CPU is Monarch
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120 | //
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121 | if (IsMonarch) {
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122 | DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));
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123 | CpuDeadLoop ();
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124 | }
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125 | } else {
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126 | AsmWriteMsr64 (SMMADDR_ADDRESS, CpuHotPlugData->SmrrBase);
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127 | AsmWriteMsr64 (SMMMASK_ADDRESS, ((~(UINT64)(CpuHotPlugData->SmrrSize - 1)) | 0x6600));
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128 | }
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129 | }
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130 | }
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131 |
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132 | /**
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133 | This function updates the SMRAM save state on the currently executing CPU
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134 | to resume execution at a specific address after an RSM instruction. This
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135 | function must evaluate the SMRAM save state to determine the execution mode
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136 | the RSM instruction resumes and update the resume execution address with
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137 | either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart
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138 | flag in the SMRAM save state must always be cleared. This function returns
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139 | the value of the instruction pointer from the SMRAM save state that was
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140 | replaced. If this function returns 0, then the SMRAM save state was not
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141 | modified.
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142 |
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143 | This function is called during the very first SMI on each CPU after
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144 | SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
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145 | to signal that the SMBASE of each CPU has been updated before the default
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146 | SMBASE address is used for the first SMI to the next CPU.
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147 |
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148 | @param[in] CpuIndex The index of the CPU to hook. The value
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149 | must be between 0 and the NumberOfCpus
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150 | field in the System Management System Table
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151 | (SMST).
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152 | @param[in] CpuState Pointer to SMRAM Save State Map for the
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153 | currently executing CPU.
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154 | @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
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155 | 32-bit execution mode from 64-bit SMM.
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156 | @param[in] NewInstructionPointer Instruction pointer to use if resuming to
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157 | same execution mode as SMM.
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158 |
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159 | @retval 0 This function did modify the SMRAM save state.
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160 | @retval > 0 The original instruction pointer value from the SMRAM save state
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161 | before it was replaced.
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162 | **/
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163 | UINT64
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164 | EFIAPI
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165 | SmmCpuFeaturesHookReturnFromSmm (
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166 | IN UINTN CpuIndex,
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167 | IN SMRAM_SAVE_STATE_MAP *CpuState,
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168 | IN UINT64 NewInstructionPointer32,
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169 | IN UINT64 NewInstructionPointer
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170 | )
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171 | {
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172 | UINT64 OriginalInstructionPointer;
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173 | AMD_SMRAM_SAVE_STATE_MAP *AmdCpuState;
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174 |
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175 | AmdCpuState = (AMD_SMRAM_SAVE_STATE_MAP *)CpuState;
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176 |
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177 | if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
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178 | OriginalInstructionPointer = (UINT64)AmdCpuState->x86._EIP;
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179 | AmdCpuState->x86._EIP = (UINT32)NewInstructionPointer;
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180 | //
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181 | // Clear the auto HALT restart flag so the RSM instruction returns
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182 | // program control to the instruction following the HLT instruction.
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183 | //
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184 | if ((AmdCpuState->x86.AutoHALTRestart & BIT0) != 0) {
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185 | AmdCpuState->x86.AutoHALTRestart &= ~BIT0;
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186 | }
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187 | } else {
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188 | OriginalInstructionPointer = AmdCpuState->x64._RIP;
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189 | if ((AmdCpuState->x64.EFER & LMA) == 0) {
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190 | AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer32;
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191 | } else {
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192 | AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer;
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193 | }
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194 |
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195 | //
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196 | // Clear the auto HALT restart flag so the RSM instruction returns
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197 | // program control to the instruction following the HLT instruction.
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198 | //
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199 | if ((AmdCpuState->x64.AutoHALTRestart & BIT0) != 0) {
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200 | AmdCpuState->x64.AutoHALTRestart &= ~BIT0;
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201 | }
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202 | }
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203 |
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204 | return OriginalInstructionPointer;
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205 | }
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206 |
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207 | /**
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208 | Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is
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209 | returned, then a custom SMI handler is not provided by this library,
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210 | and the default SMI handler must be used.
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211 |
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212 | @retval 0 Use the default SMI handler.
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213 | @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()
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214 | The caller is required to allocate enough SMRAM for each CPU to
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215 | support the size of the custom SMI handler.
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216 | **/
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217 | UINTN
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218 | EFIAPI
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219 | SmmCpuFeaturesGetSmiHandlerSize (
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220 | VOID
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221 | )
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222 | {
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223 | return 0;
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224 | }
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225 |
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226 | /**
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227 | Install a custom SMI handler for the CPU specified by CpuIndex. This function
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228 | is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater
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229 | than zero and is called by the CPU that was elected as monarch during System
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230 | Management Mode initialization.
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231 |
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232 | @param[in] CpuIndex The index of the CPU to install the custom SMI handler.
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233 | The value must be between 0 and the NumberOfCpus field
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234 | in the System Management System Table (SMST).
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235 | @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
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236 | @param[in] SmiStack The stack to use when an SMI is processed by the
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237 | the CPU specified by CpuIndex.
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238 | @param[in] StackSize The size, in bytes, if the stack used when an SMI is
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239 | processed by the CPU specified by CpuIndex.
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240 | @param[in] GdtBase The base address of the GDT to use when an SMI is
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241 | processed by the CPU specified by CpuIndex.
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242 | @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
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243 | processed by the CPU specified by CpuIndex.
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244 | @param[in] IdtBase The base address of the IDT to use when an SMI is
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245 | processed by the CPU specified by CpuIndex.
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246 | @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
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247 | processed by the CPU specified by CpuIndex.
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248 | @param[in] Cr3 The base address of the page tables to use when an SMI
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249 | is processed by the CPU specified by CpuIndex.
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250 | **/
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251 | VOID
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252 | EFIAPI
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253 | SmmCpuFeaturesInstallSmiHandler (
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254 | IN UINTN CpuIndex,
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255 | IN UINT32 SmBase,
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256 | IN VOID *SmiStack,
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257 | IN UINTN StackSize,
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258 | IN UINTN GdtBase,
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259 | IN UINTN GdtSize,
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260 | IN UINTN IdtBase,
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261 | IN UINTN IdtSize,
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262 | IN UINT32 Cr3
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263 | )
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264 | {
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265 | }
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266 |
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267 | /**
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268 | Determines if MTRR registers must be configured to set SMRAM cache-ability
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269 | when executing in System Management Mode.
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270 |
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271 | @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.
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272 | @retval FALSE MTRR registers do not need to be configured to set SMRAM
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273 | cache-ability.
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274 | **/
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275 | BOOLEAN
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276 | EFIAPI
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277 | SmmCpuFeaturesNeedConfigureMtrrs (
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278 | VOID
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279 | )
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280 | {
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281 | return FALSE;
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282 | }
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283 |
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284 | /**
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285 | Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
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286 | returns TRUE.
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287 | **/
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288 | VOID
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289 | EFIAPI
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290 | SmmCpuFeaturesDisableSmrr (
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291 | VOID
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292 | )
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293 | {
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294 | }
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295 |
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296 | /**
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297 | Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
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298 | returns TRUE.
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299 | **/
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300 | VOID
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301 | EFIAPI
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302 | SmmCpuFeaturesReenableSmrr (
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303 | VOID
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304 | )
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305 | {
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306 | }
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307 |
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308 | /**
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309 | Processor specific hook point each time a CPU enters System Management Mode.
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310 |
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311 | @param[in] CpuIndex The index of the CPU that has entered SMM. The value
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312 | must be between 0 and the NumberOfCpus field in the
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313 | System Management System Table (SMST).
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314 | **/
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315 | VOID
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316 | EFIAPI
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317 | SmmCpuFeaturesRendezvousEntry (
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318 | IN UINTN CpuIndex
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319 | )
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320 | {
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321 | }
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322 |
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323 | /**
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324 | Returns the current value of the SMM register for the specified CPU.
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325 | If the SMM register is not supported, then 0 is returned.
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326 |
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327 | @param[in] CpuIndex The index of the CPU to read the SMM register. The
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328 | value must be between 0 and the NumberOfCpus field in
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329 | the System Management System Table (SMST).
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330 | @param[in] RegName Identifies the SMM register to read.
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331 |
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332 | @return The value of the SMM register specified by RegName from the CPU
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333 | specified by CpuIndex.
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334 | **/
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335 | UINT64
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336 | EFIAPI
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337 | SmmCpuFeaturesGetSmmRegister (
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338 | IN UINTN CpuIndex,
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339 | IN SMM_REG_NAME RegName
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340 | )
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341 | {
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342 | return 0;
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343 | }
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344 |
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345 | /**
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346 | Sets the value of an SMM register on a specified CPU.
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347 | If the SMM register is not supported, then no action is performed.
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348 |
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349 | @param[in] CpuIndex The index of the CPU to write the SMM register. The
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350 | value must be between 0 and the NumberOfCpus field in
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351 | the System Management System Table (SMST).
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352 | @param[in] RegName Identifies the SMM register to write.
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353 | registers are read-only.
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354 | @param[in] Value The value to write to the SMM register.
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355 | **/
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356 | VOID
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357 | EFIAPI
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358 | SmmCpuFeaturesSetSmmRegister (
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359 | IN UINTN CpuIndex,
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360 | IN SMM_REG_NAME RegName,
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361 | IN UINT64 Value
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362 | )
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363 | {
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364 | }
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365 |
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366 | /**
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367 | Check to see if an SMM register is supported by a specified CPU.
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368 |
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369 | @param[in] CpuIndex The index of the CPU to check for SMM register support.
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370 | The value must be between 0 and the NumberOfCpus field
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371 | in the System Management System Table (SMST).
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372 | @param[in] RegName Identifies the SMM register to check for support.
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373 |
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374 | @retval TRUE The SMM register specified by RegName is supported by the CPU
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375 | specified by CpuIndex.
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376 | @retval FALSE The SMM register specified by RegName is not supported by the
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377 | CPU specified by CpuIndex.
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378 | **/
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379 | BOOLEAN
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380 | EFIAPI
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381 | SmmCpuFeaturesIsSmmRegisterSupported (
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382 | IN UINTN CpuIndex,
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383 | IN SMM_REG_NAME RegName
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384 | )
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385 | {
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386 | return FALSE;
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387 | }
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