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1/** @file
2 The CPU specific programming for PiSmmCpuDxeSmm module.
3
4 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
5
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7**/
8
9#include <IndustryStandard/Q35MchIch9.h>
10#include <Library/BaseLib.h>
11#include <Library/BaseMemoryLib.h>
12#include <Library/DebugLib.h>
13#include <Library/MemEncryptSevLib.h>
14#include <Library/MemoryAllocationLib.h>
15#include <Library/PcdLib.h>
16#include <Library/SafeIntLib.h>
17#include <Library/SmmCpuFeaturesLib.h>
18#include <Library/SmmServicesTableLib.h>
19#include <Library/UefiBootServicesTableLib.h>
20#include <Pcd/CpuHotEjectData.h>
21#include <PiSmm.h>
22#include <Register/Intel/SmramSaveStateMap.h>
23#include <Register/QemuSmramSaveStateMap.h>
24
25//
26// EFER register LMA bit
27//
28#define LMA BIT10
29
30/**
31 The constructor function
32
33 @param[in] ImageHandle The firmware allocated handle for the EFI image.
34 @param[in] SystemTable A pointer to the EFI System Table.
35
36 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
37
38**/
39EFI_STATUS
40EFIAPI
41SmmCpuFeaturesLibConstructor (
42 IN EFI_HANDLE ImageHandle,
43 IN EFI_SYSTEM_TABLE *SystemTable
44 )
45{
46 //
47 // No need to program SMRRs on our virtual platform.
48 //
49 return EFI_SUCCESS;
50}
51
52/**
53 Called during the very first SMI into System Management Mode to initialize
54 CPU features, including SMBASE, for the currently executing CPU. Since this
55 is the first SMI, the SMRAM Save State Map is at the default address of
56 SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing
57 CPU is specified by CpuIndex and CpuIndex can be used to access information
58 about the currently executing CPU in the ProcessorInfo array and the
59 HotPlugCpuData data structure.
60
61 @param[in] CpuIndex The index of the CPU to initialize. The value
62 must be between 0 and the NumberOfCpus field in
63 the System Management System Table (SMST).
64 @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that
65 was elected as monarch during System Management
66 Mode initialization.
67 FALSE if the CpuIndex is not the index of the CPU
68 that was elected as monarch during System
69 Management Mode initialization.
70 @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION
71 structures. ProcessorInfo[CpuIndex] contains the
72 information for the currently executing CPU.
73 @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that
74 contains the ApidId and SmBase arrays.
75**/
76VOID
77EFIAPI
78SmmCpuFeaturesInitializeProcessor (
79 IN UINTN CpuIndex,
80 IN BOOLEAN IsMonarch,
81 IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,
82 IN CPU_HOT_PLUG_DATA *CpuHotPlugData
83 )
84{
85 QEMU_SMRAM_SAVE_STATE_MAP *CpuState;
86
87 //
88 // Configure SMBASE.
89 //
90 CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(
91 SMM_DEFAULT_SMBASE +
92 SMRAM_SAVE_STATE_MAP_OFFSET
93 );
94 if ((CpuState->x86.SMMRevId & 0xFFFF) == 0) {
95 CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
96 } else {
97 CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
98 }
99
100 //
101 // No need to program SMRRs on our virtual platform.
102 //
103}
104
105/**
106 This function updates the SMRAM save state on the currently executing CPU
107 to resume execution at a specific address after an RSM instruction. This
108 function must evaluate the SMRAM save state to determine the execution mode
109 the RSM instruction resumes and update the resume execution address with
110 either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart
111 flag in the SMRAM save state must always be cleared. This function returns
112 the value of the instruction pointer from the SMRAM save state that was
113 replaced. If this function returns 0, then the SMRAM save state was not
114 modified.
115
116 This function is called during the very first SMI on each CPU after
117 SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
118 to signal that the SMBASE of each CPU has been updated before the default
119 SMBASE address is used for the first SMI to the next CPU.
120
121 @param[in] CpuIndex The index of the CPU to hook. The value
122 must be between 0 and the NumberOfCpus
123 field in the System Management System
124 Table (SMST).
125 @param[in] CpuState Pointer to SMRAM Save State Map for the
126 currently executing CPU.
127 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
128 32-bit execution mode from 64-bit SMM.
129 @param[in] NewInstructionPointer Instruction pointer to use if resuming to
130 same execution mode as SMM.
131
132 @retval 0 This function did modify the SMRAM save state.
133 @retval > 0 The original instruction pointer value from the SMRAM save state
134 before it was replaced.
135**/
136UINT64
137EFIAPI
138SmmCpuFeaturesHookReturnFromSmm (
139 IN UINTN CpuIndex,
140 IN SMRAM_SAVE_STATE_MAP *CpuState,
141 IN UINT64 NewInstructionPointer32,
142 IN UINT64 NewInstructionPointer
143 )
144{
145 UINT64 OriginalInstructionPointer;
146 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
147
148 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState;
149 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
150 OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;
151 CpuSaveState->x86._EIP = (UINT32)NewInstructionPointer;
152 //
153 // Clear the auto HALT restart flag so the RSM instruction returns
154 // program control to the instruction following the HLT instruction.
155 //
156 if ((CpuSaveState->x86.AutoHALTRestart & BIT0) != 0) {
157 CpuSaveState->x86.AutoHALTRestart &= ~BIT0;
158 }
159 } else {
160 OriginalInstructionPointer = CpuSaveState->x64._RIP;
161 if ((CpuSaveState->x64.IA32_EFER & LMA) == 0) {
162 CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer32;
163 } else {
164 CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer;
165 }
166 //
167 // Clear the auto HALT restart flag so the RSM instruction returns
168 // program control to the instruction following the HLT instruction.
169 //
170 if ((CpuSaveState->x64.AutoHALTRestart & BIT0) != 0) {
171 CpuSaveState->x64.AutoHALTRestart &= ~BIT0;
172 }
173 }
174 return OriginalInstructionPointer;
175}
176
177STATIC CPU_HOT_EJECT_DATA *mCpuHotEjectData = NULL;
178
179/**
180 Initialize mCpuHotEjectData if PcdCpuMaxLogicalProcessorNumber > 1.
181
182 Also setup the corresponding PcdCpuHotEjectDataAddress.
183**/
184STATIC
185VOID
186InitCpuHotEjectData (
187 VOID
188 )
189{
190 UINTN Size;
191 UINT32 Idx;
192 UINT32 MaxNumberOfCpus;
193 RETURN_STATUS PcdStatus;
194
195 MaxNumberOfCpus = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
196 if (MaxNumberOfCpus == 1) {
197 return;
198 }
199
200 //
201 // We allocate CPU_HOT_EJECT_DATA and CPU_HOT_EJECT_DATA->QemuSelectorMap[]
202 // in a single allocation, and explicitly align the QemuSelectorMap[] (which
203 // is a UINT64 array) at its natural boundary.
204 // Accordingly, allocate:
205 // sizeof(*mCpuHotEjectData) + (MaxNumberOfCpus * sizeof(UINT64))
206 // and, add sizeof(UINT64) - 1 to use as padding if needed.
207 //
208
209 if (RETURN_ERROR (SafeUintnMult (MaxNumberOfCpus, sizeof (UINT64), &Size)) ||
210 RETURN_ERROR (SafeUintnAdd (Size, sizeof (*mCpuHotEjectData), &Size)) ||
211 RETURN_ERROR (SafeUintnAdd (Size, sizeof (UINT64) - 1, &Size))) {
212 DEBUG ((DEBUG_ERROR, "%a: invalid CPU_HOT_EJECT_DATA\n", __FUNCTION__));
213 goto Fatal;
214 }
215
216 mCpuHotEjectData = AllocatePool (Size);
217 if (mCpuHotEjectData == NULL) {
218 ASSERT (mCpuHotEjectData != NULL);
219 goto Fatal;
220 }
221
222 mCpuHotEjectData->Handler = NULL;
223 mCpuHotEjectData->ArrayLength = MaxNumberOfCpus;
224
225 mCpuHotEjectData->QemuSelectorMap = ALIGN_POINTER (mCpuHotEjectData + 1,
226 sizeof (UINT64));
227 //
228 // We use mCpuHotEjectData->QemuSelectorMap to map
229 // ProcessorNum -> QemuSelector. Initialize to invalid values.
230 //
231 for (Idx = 0; Idx < mCpuHotEjectData->ArrayLength; Idx++) {
232 mCpuHotEjectData->QemuSelectorMap[Idx] = CPU_EJECT_QEMU_SELECTOR_INVALID;
233 }
234
235 //
236 // Expose address of CPU Hot eject Data structure
237 //
238 PcdStatus = PcdSet64S (PcdCpuHotEjectDataAddress,
239 (UINTN)(VOID *)mCpuHotEjectData);
240 ASSERT_RETURN_ERROR (PcdStatus);
241
242 return;
243
244Fatal:
245 CpuDeadLoop ();
246}
247
248/**
249 Hook point in normal execution mode that allows the one CPU that was elected
250 as monarch during System Management Mode initialization to perform additional
251 initialization actions immediately after all of the CPUs have processed their
252 first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE
253 into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().
254**/
255VOID
256EFIAPI
257SmmCpuFeaturesSmmRelocationComplete (
258 VOID
259 )
260{
261 EFI_STATUS Status;
262 UINTN MapPagesBase;
263 UINTN MapPagesCount;
264
265
266 InitCpuHotEjectData ();
267
268 if (!MemEncryptSevIsEnabled ()) {
269 return;
270 }
271
272 //
273 // Now that SMBASE relocation is complete, re-encrypt the original SMRAM save
274 // state map's container pages, and release the pages to DXE. (The pages were
275 // allocated in PlatformPei.)
276 //
277 Status = MemEncryptSevLocateInitialSmramSaveStateMapPages (
278 &MapPagesBase,
279 &MapPagesCount
280 );
281 ASSERT_EFI_ERROR (Status);
282
283 Status = MemEncryptSevSetPageEncMask (
284 0, // Cr3BaseAddress -- use current CR3
285 MapPagesBase, // BaseAddress
286 MapPagesCount, // NumPages
287 TRUE // Flush
288 );
289 if (EFI_ERROR (Status)) {
290 DEBUG ((DEBUG_ERROR, "%a: MemEncryptSevSetPageEncMask(): %r\n",
291 __FUNCTION__, Status));
292 ASSERT (FALSE);
293 CpuDeadLoop ();
294 }
295
296 ZeroMem ((VOID *)MapPagesBase, EFI_PAGES_TO_SIZE (MapPagesCount));
297
298 if (PcdGetBool (PcdQ35SmramAtDefaultSmbase)) {
299 //
300 // The initial SMRAM Save State Map has been covered as part of a larger
301 // reserved memory allocation in PlatformPei's InitializeRamRegions(). That
302 // allocation is supposed to survive into OS runtime; we must not release
303 // any part of it. Only re-assert the containment here.
304 //
305 ASSERT (SMM_DEFAULT_SMBASE <= MapPagesBase);
306 ASSERT (
307 (MapPagesBase + EFI_PAGES_TO_SIZE (MapPagesCount) <=
308 SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE)
309 );
310 } else {
311 Status = gBS->FreePages (MapPagesBase, MapPagesCount);
312 ASSERT_EFI_ERROR (Status);
313 }
314}
315
316/**
317 Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is
318 returned, then a custom SMI handler is not provided by this library,
319 and the default SMI handler must be used.
320
321 @retval 0 Use the default SMI handler.
322 @retval > 0 Use the SMI handler installed by
323 SmmCpuFeaturesInstallSmiHandler(). The caller is required to
324 allocate enough SMRAM for each CPU to support the size of the
325 custom SMI handler.
326**/
327UINTN
328EFIAPI
329SmmCpuFeaturesGetSmiHandlerSize (
330 VOID
331 )
332{
333 return 0;
334}
335
336/**
337 Install a custom SMI handler for the CPU specified by CpuIndex. This
338 function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size
339 is greater than zero and is called by the CPU that was elected as monarch
340 during System Management Mode initialization.
341
342 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.
343 The value must be between 0 and the NumberOfCpus field
344 in the System Management System Table (SMST).
345 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
346 @param[in] SmiStack The stack to use when an SMI is processed by the
347 the CPU specified by CpuIndex.
348 @param[in] StackSize The size, in bytes, if the stack used when an SMI is
349 processed by the CPU specified by CpuIndex.
350 @param[in] GdtBase The base address of the GDT to use when an SMI is
351 processed by the CPU specified by CpuIndex.
352 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
353 processed by the CPU specified by CpuIndex.
354 @param[in] IdtBase The base address of the IDT to use when an SMI is
355 processed by the CPU specified by CpuIndex.
356 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
357 processed by the CPU specified by CpuIndex.
358 @param[in] Cr3 The base address of the page tables to use when an SMI
359 is processed by the CPU specified by CpuIndex.
360**/
361VOID
362EFIAPI
363SmmCpuFeaturesInstallSmiHandler (
364 IN UINTN CpuIndex,
365 IN UINT32 SmBase,
366 IN VOID *SmiStack,
367 IN UINTN StackSize,
368 IN UINTN GdtBase,
369 IN UINTN GdtSize,
370 IN UINTN IdtBase,
371 IN UINTN IdtSize,
372 IN UINT32 Cr3
373 )
374{
375}
376
377/**
378 Determines if MTRR registers must be configured to set SMRAM cache-ability
379 when executing in System Management Mode.
380
381 @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.
382 @retval FALSE MTRR registers do not need to be configured to set SMRAM
383 cache-ability.
384**/
385BOOLEAN
386EFIAPI
387SmmCpuFeaturesNeedConfigureMtrrs (
388 VOID
389 )
390{
391 return FALSE;
392}
393
394/**
395 Disable SMRR register if SMRR is supported and
396 SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.
397**/
398VOID
399EFIAPI
400SmmCpuFeaturesDisableSmrr (
401 VOID
402 )
403{
404 //
405 // No SMRR support, nothing to do
406 //
407}
408
409/**
410 Enable SMRR register if SMRR is supported and
411 SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.
412**/
413VOID
414EFIAPI
415SmmCpuFeaturesReenableSmrr (
416 VOID
417 )
418{
419 //
420 // No SMRR support, nothing to do
421 //
422}
423
424/**
425 Processor specific hook point each time a CPU enters System Management Mode.
426
427 @param[in] CpuIndex The index of the CPU that has entered SMM. The value
428 must be between 0 and the NumberOfCpus field in the
429 System Management System Table (SMST).
430**/
431VOID
432EFIAPI
433SmmCpuFeaturesRendezvousEntry (
434 IN UINTN CpuIndex
435 )
436{
437 //
438 // No SMRR support, nothing to do
439 //
440}
441
442/**
443 Processor specific hook point each time a CPU exits System Management Mode.
444
445 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value
446 must be between 0 and the NumberOfCpus field in the
447 System Management System Table (SMST).
448**/
449VOID
450EFIAPI
451SmmCpuFeaturesRendezvousExit (
452 IN UINTN CpuIndex
453 )
454{
455 //
456 // We only call the Handler if CPU hot-eject is enabled
457 // (PcdCpuMaxLogicalProcessorNumber > 1), and hot-eject is needed
458 // in this SMI exit (otherwise mCpuHotEjectData->Handler is not armed.)
459 //
460
461 if (mCpuHotEjectData != NULL) {
462 CPU_HOT_EJECT_HANDLER Handler;
463
464 //
465 // As the comment above mentions, mCpuHotEjectData->Handler might be
466 // written to on the BSP as part of handling of the CPU-ejection.
467 //
468 // We know that any initial assignment to mCpuHotEjectData->Handler
469 // (on the BSP, in the CpuHotplugMmi() context) is ordered-before the
470 // load below, since it is guaranteed to happen before the
471 // control-dependency of the BSP's SMI exit signal -- by way of a store
472 // to AllCpusInSync (on the BSP, in BspHandler()) and the corresponding
473 // AllCpusInSync loop (on the APs, in SmiRendezvous()) which depends on
474 // that store.
475 //
476 // This guarantees that these pieces of code can never execute
477 // simultaneously. In addition, we ensure that the following load is
478 // ordered-after the AllCpusInSync loop by using a MemoryFence() with
479 // acquire semantics.
480 //
481 MemoryFence();
482
483 Handler = mCpuHotEjectData->Handler;
484
485 if (Handler != NULL) {
486 Handler (CpuIndex);
487 }
488 }
489}
490
491/**
492 Check to see if an SMM register is supported by a specified CPU.
493
494 @param[in] CpuIndex The index of the CPU to check for SMM register support.
495 The value must be between 0 and the NumberOfCpus field
496 in the System Management System Table (SMST).
497 @param[in] RegName Identifies the SMM register to check for support.
498
499 @retval TRUE The SMM register specified by RegName is supported by the CPU
500 specified by CpuIndex.
501 @retval FALSE The SMM register specified by RegName is not supported by the
502 CPU specified by CpuIndex.
503**/
504BOOLEAN
505EFIAPI
506SmmCpuFeaturesIsSmmRegisterSupported (
507 IN UINTN CpuIndex,
508 IN SMM_REG_NAME RegName
509 )
510{
511 ASSERT (RegName == SmmRegFeatureControl);
512 return FALSE;
513}
514
515/**
516 Returns the current value of the SMM register for the specified CPU.
517 If the SMM register is not supported, then 0 is returned.
518
519 @param[in] CpuIndex The index of the CPU to read the SMM register. The
520 value must be between 0 and the NumberOfCpus field in
521 the System Management System Table (SMST).
522 @param[in] RegName Identifies the SMM register to read.
523
524 @return The value of the SMM register specified by RegName from the CPU
525 specified by CpuIndex.
526**/
527UINT64
528EFIAPI
529SmmCpuFeaturesGetSmmRegister (
530 IN UINTN CpuIndex,
531 IN SMM_REG_NAME RegName
532 )
533{
534 //
535 // This is called for SmmRegSmmDelayed, SmmRegSmmBlocked, SmmRegSmmEnable.
536 // The last of these should actually be SmmRegSmmDisable, so we can just
537 // return FALSE.
538 //
539 return 0;
540}
541
542/**
543 Sets the value of an SMM register on a specified CPU.
544 If the SMM register is not supported, then no action is performed.
545
546 @param[in] CpuIndex The index of the CPU to write the SMM register. The
547 value must be between 0 and the NumberOfCpus field in
548 the System Management System Table (SMST).
549 @param[in] RegName Identifies the SMM register to write.
550 registers are read-only.
551 @param[in] Value The value to write to the SMM register.
552**/
553VOID
554EFIAPI
555SmmCpuFeaturesSetSmmRegister (
556 IN UINTN CpuIndex,
557 IN SMM_REG_NAME RegName,
558 IN UINT64 Value
559 )
560{
561 ASSERT (FALSE);
562}
563
564///
565/// Macro used to simplify the lookup table entries of type
566/// CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
567///
568#define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)
569
570///
571/// Macro used to simplify the lookup table entries of type
572/// CPU_SMM_SAVE_STATE_REGISTER_RANGE
573///
574#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }
575
576///
577/// Structure used to describe a range of registers
578///
579typedef struct {
580 EFI_SMM_SAVE_STATE_REGISTER Start;
581 EFI_SMM_SAVE_STATE_REGISTER End;
582 UINTN Length;
583} CPU_SMM_SAVE_STATE_REGISTER_RANGE;
584
585///
586/// Structure used to build a lookup table to retrieve the widths and offsets
587/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
588///
589
590#define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1
591
592typedef struct {
593 UINT8 Width32;
594 UINT8 Width64;
595 UINT16 Offset32;
596 UINT16 Offset64Lo;
597 UINT16 Offset64Hi;
598 BOOLEAN Writeable;
599} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
600
601///
602/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
603/// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
604///
605STATIC CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {
606 SMM_REGISTER_RANGE (
607 EFI_SMM_SAVE_STATE_REGISTER_GDTBASE,
608 EFI_SMM_SAVE_STATE_REGISTER_LDTINFO
609 ),
610 SMM_REGISTER_RANGE (
611 EFI_SMM_SAVE_STATE_REGISTER_ES,
612 EFI_SMM_SAVE_STATE_REGISTER_RIP
613 ),
614 SMM_REGISTER_RANGE (
615 EFI_SMM_SAVE_STATE_REGISTER_RFLAGS,
616 EFI_SMM_SAVE_STATE_REGISTER_CR4
617 ),
618 { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }
619};
620
621///
622/// Lookup table used to retrieve the widths and offsets associated with each
623/// supported EFI_SMM_SAVE_STATE_REGISTER value
624///
625STATIC CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
626 {
627 0, // Width32
628 0, // Width64
629 0, // Offset32
630 0, // Offset64Lo
631 0, // Offset64Hi
632 FALSE // Writeable
633 }, // Reserved
634
635 //
636 // CPU Save State registers defined in PI SMM CPU Protocol.
637 //
638 {
639 0, // Width32
640 8, // Width64
641 0, // Offset32
642 SMM_CPU_OFFSET (x64._GDTRBase), // Offset64Lo
643 SMM_CPU_OFFSET (x64._GDTRBase) + 4, // Offset64Hi
644 FALSE // Writeable
645 }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
646
647 {
648 0, // Width32
649 8, // Width64
650 0, // Offset32
651 SMM_CPU_OFFSET (x64._IDTRBase), // Offset64Lo
652 SMM_CPU_OFFSET (x64._IDTRBase) + 4, // Offset64Hi
653 FALSE // Writeable
654 }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
655
656 {
657 0, // Width32
658 8, // Width64
659 0, // Offset32
660 SMM_CPU_OFFSET (x64._LDTRBase), // Offset64Lo
661 SMM_CPU_OFFSET (x64._LDTRBase) + 4, // Offset64Hi
662 FALSE // Writeable
663 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
664
665 {
666 0, // Width32
667 0, // Width64
668 0, // Offset32
669 SMM_CPU_OFFSET (x64._GDTRLimit), // Offset64Lo
670 SMM_CPU_OFFSET (x64._GDTRLimit) + 4, // Offset64Hi
671 FALSE // Writeable
672 }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
673
674 {
675 0, // Width32
676 0, // Width64
677 0, // Offset32
678 SMM_CPU_OFFSET (x64._IDTRLimit), // Offset64Lo
679 SMM_CPU_OFFSET (x64._IDTRLimit) + 4, // Offset64Hi
680 FALSE // Writeable
681 }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
682
683 {
684 0, // Width32
685 0, // Width64
686 0, // Offset32
687 SMM_CPU_OFFSET (x64._LDTRLimit), // Offset64Lo
688 SMM_CPU_OFFSET (x64._LDTRLimit) + 4, // Offset64Hi
689 FALSE // Writeable
690 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
691
692 {
693 0, // Width32
694 0, // Width64
695 0, // Offset32
696 0, // Offset64Lo
697 0 + 4, // Offset64Hi
698 FALSE // Writeable
699 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
700
701 {
702 4, // Width32
703 4, // Width64
704 SMM_CPU_OFFSET (x86._ES), // Offset32
705 SMM_CPU_OFFSET (x64._ES), // Offset64Lo
706 0, // Offset64Hi
707 FALSE // Writeable
708 }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
709
710 {
711 4, // Width32
712 4, // Width64
713 SMM_CPU_OFFSET (x86._CS), // Offset32
714 SMM_CPU_OFFSET (x64._CS), // Offset64Lo
715 0, // Offset64Hi
716 FALSE // Writeable
717 }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
718
719 {
720 4, // Width32
721 4, // Width64
722 SMM_CPU_OFFSET (x86._SS), // Offset32
723 SMM_CPU_OFFSET (x64._SS), // Offset64Lo
724 0, // Offset64Hi
725 FALSE // Writeable
726 }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
727
728 {
729 4, // Width32
730 4, // Width64
731 SMM_CPU_OFFSET (x86._DS), // Offset32
732 SMM_CPU_OFFSET (x64._DS), // Offset64Lo
733 0, // Offset64Hi
734 FALSE // Writeable
735 }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
736
737 {
738 4, // Width32
739 4, // Width64
740 SMM_CPU_OFFSET (x86._FS), // Offset32
741 SMM_CPU_OFFSET (x64._FS), // Offset64Lo
742 0, // Offset64Hi
743 FALSE // Writeable
744 }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
745
746 {
747 4, // Width32
748 4, // Width64
749 SMM_CPU_OFFSET (x86._GS), // Offset32
750 SMM_CPU_OFFSET (x64._GS), // Offset64Lo
751 0, // Offset64Hi
752 FALSE // Writeable
753 }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
754
755 {
756 0, // Width32
757 4, // Width64
758 0, // Offset32
759 SMM_CPU_OFFSET (x64._LDTR), // Offset64Lo
760 0, // Offset64Hi
761 FALSE // Writeable
762 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
763
764 {
765 4, // Width32
766 4, // Width64
767 SMM_CPU_OFFSET (x86._TR), // Offset32
768 SMM_CPU_OFFSET (x64._TR), // Offset64Lo
769 0, // Offset64Hi
770 FALSE // Writeable
771 }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
772
773 {
774 4, // Width32
775 8, // Width64
776 SMM_CPU_OFFSET (x86._DR7), // Offset32
777 SMM_CPU_OFFSET (x64._DR7), // Offset64Lo
778 SMM_CPU_OFFSET (x64._DR7) + 4, // Offset64Hi
779 FALSE // Writeable
780 }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28
781
782 {
783 4, // Width32
784 8, // Width64
785 SMM_CPU_OFFSET (x86._DR6), // Offset32
786 SMM_CPU_OFFSET (x64._DR6), // Offset64Lo
787 SMM_CPU_OFFSET (x64._DR6) + 4, // Offset64Hi
788 FALSE // Writeable
789 }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29
790
791 {
792 0, // Width32
793 8, // Width64
794 0, // Offset32
795 SMM_CPU_OFFSET (x64._R8), // Offset64Lo
796 SMM_CPU_OFFSET (x64._R8) + 4, // Offset64Hi
797 TRUE // Writeable
798 }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
799
800 {
801 0, // Width32
802 8, // Width64
803 0, // Offset32
804 SMM_CPU_OFFSET (x64._R9), // Offset64Lo
805 SMM_CPU_OFFSET (x64._R9) + 4, // Offset64Hi
806 TRUE // Writeable
807 }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
808
809 {
810 0, // Width32
811 8, // Width64
812 0, // Offset32
813 SMM_CPU_OFFSET (x64._R10), // Offset64Lo
814 SMM_CPU_OFFSET (x64._R10) + 4, // Offset64Hi
815 TRUE // Writeable
816 }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
817
818 {
819 0, // Width32
820 8, // Width64
821 0, // Offset32
822 SMM_CPU_OFFSET (x64._R11), // Offset64Lo
823 SMM_CPU_OFFSET (x64._R11) + 4, // Offset64Hi
824 TRUE // Writeable
825 }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
826
827 {
828 0, // Width32
829 8, // Width64
830 0, // Offset32
831 SMM_CPU_OFFSET (x64._R12), // Offset64Lo
832 SMM_CPU_OFFSET (x64._R12) + 4, // Offset64Hi
833 TRUE // Writeable
834 }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
835
836 {
837 0, // Width32
838 8, // Width64
839 0, // Offset32
840 SMM_CPU_OFFSET (x64._R13), // Offset64Lo
841 SMM_CPU_OFFSET (x64._R13) + 4, // Offset64Hi
842 TRUE // Writeable
843 }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
844
845 {
846 0, // Width32
847 8, // Width64
848 0, // Offset32
849 SMM_CPU_OFFSET (x64._R14), // Offset64Lo
850 SMM_CPU_OFFSET (x64._R14) + 4, // Offset64Hi
851 TRUE // Writeable
852 }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
853
854 {
855 0, // Width32
856 8, // Width64
857 0, // Offset32
858 SMM_CPU_OFFSET (x64._R15), // Offset64Lo
859 SMM_CPU_OFFSET (x64._R15) + 4, // Offset64Hi
860 TRUE // Writeable
861 }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
862
863 {
864 4, // Width32
865 8, // Width64
866 SMM_CPU_OFFSET (x86._EAX), // Offset32
867 SMM_CPU_OFFSET (x64._RAX), // Offset64Lo
868 SMM_CPU_OFFSET (x64._RAX) + 4, // Offset64Hi
869 TRUE // Writeable
870 }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38
871
872 {
873 4, // Width32
874 8, // Width64
875 SMM_CPU_OFFSET (x86._EBX), // Offset32
876 SMM_CPU_OFFSET (x64._RBX), // Offset64Lo
877 SMM_CPU_OFFSET (x64._RBX) + 4, // Offset64Hi
878 TRUE // Writeable
879 }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
880
881 {
882 4, // Width32
883 8, // Width64
884 SMM_CPU_OFFSET (x86._ECX), // Offset32
885 SMM_CPU_OFFSET (x64._RCX), // Offset64Lo
886 SMM_CPU_OFFSET (x64._RCX) + 4, // Offset64Hi
887 TRUE // Writeable
888 }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40
889
890 {
891 4, // Width32
892 8, // Width64
893 SMM_CPU_OFFSET (x86._EDX), // Offset32
894 SMM_CPU_OFFSET (x64._RDX), // Offset64Lo
895 SMM_CPU_OFFSET (x64._RDX) + 4, // Offset64Hi
896 TRUE // Writeable
897 }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41
898
899 {
900 4, // Width32
901 8, // Width64
902 SMM_CPU_OFFSET (x86._ESP), // Offset32
903 SMM_CPU_OFFSET (x64._RSP), // Offset64Lo
904 SMM_CPU_OFFSET (x64._RSP) + 4, // Offset64Hi
905 TRUE // Writeable
906 }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42
907
908 {
909 4, // Width32
910 8, // Width64
911 SMM_CPU_OFFSET (x86._EBP), // Offset32
912 SMM_CPU_OFFSET (x64._RBP), // Offset64Lo
913 SMM_CPU_OFFSET (x64._RBP) + 4, // Offset64Hi
914 TRUE // Writeable
915 }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43
916
917 {
918 4, // Width32
919 8, // Width64
920 SMM_CPU_OFFSET (x86._ESI), // Offset32
921 SMM_CPU_OFFSET (x64._RSI), // Offset64Lo
922 SMM_CPU_OFFSET (x64._RSI) + 4, // Offset64Hi
923 TRUE // Writeable
924 }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44
925
926 {
927 4, // Width32
928 8, // Width64
929 SMM_CPU_OFFSET (x86._EDI), // Offset32
930 SMM_CPU_OFFSET (x64._RDI), // Offset64Lo
931 SMM_CPU_OFFSET (x64._RDI) + 4, // Offset64Hi
932 TRUE // Writeable
933 }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45
934
935 {
936 4, // Width32
937 8, // Width64
938 SMM_CPU_OFFSET (x86._EIP), // Offset32
939 SMM_CPU_OFFSET (x64._RIP), // Offset64Lo
940 SMM_CPU_OFFSET (x64._RIP) + 4, // Offset64Hi
941 TRUE // Writeable
942 }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46
943
944 {
945 4, // Width32
946 8, // Width64
947 SMM_CPU_OFFSET (x86._EFLAGS), // Offset32
948 SMM_CPU_OFFSET (x64._RFLAGS), // Offset64Lo
949 SMM_CPU_OFFSET (x64._RFLAGS) + 4, // Offset64Hi
950 TRUE // Writeable
951 }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
952
953 {
954 4, // Width32
955 8, // Width64
956 SMM_CPU_OFFSET (x86._CR0), // Offset32
957 SMM_CPU_OFFSET (x64._CR0), // Offset64Lo
958 SMM_CPU_OFFSET (x64._CR0) + 4, // Offset64Hi
959 FALSE // Writeable
960 }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
961
962 {
963 4, // Width32
964 8, // Width64
965 SMM_CPU_OFFSET (x86._CR3), // Offset32
966 SMM_CPU_OFFSET (x64._CR3), // Offset64Lo
967 SMM_CPU_OFFSET (x64._CR3) + 4, // Offset64Hi
968 FALSE // Writeable
969 }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
970
971 {
972 0, // Width32
973 4, // Width64
974 0, // Offset32
975 SMM_CPU_OFFSET (x64._CR4), // Offset64Lo
976 SMM_CPU_OFFSET (x64._CR4) + 4, // Offset64Hi
977 FALSE // Writeable
978 }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
979};
980
981//
982// No support for I/O restart
983//
984
985/**
986 Read information from the CPU save state.
987
988 @param Register Specifies the CPU register to read form the save state.
989
990 @retval 0 Register is not valid
991 @retval >0 Index into mSmmCpuWidthOffset[] associated with Register
992
993**/
994STATIC
995UINTN
996GetRegisterIndex (
997 IN EFI_SMM_SAVE_STATE_REGISTER Register
998 )
999{
1000 UINTN Index;
1001 UINTN Offset;
1002
1003 for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX;
1004 mSmmCpuRegisterRanges[Index].Length != 0;
1005 Index++) {
1006 if (Register >= mSmmCpuRegisterRanges[Index].Start &&
1007 Register <= mSmmCpuRegisterRanges[Index].End) {
1008 return Register - mSmmCpuRegisterRanges[Index].Start + Offset;
1009 }
1010 Offset += mSmmCpuRegisterRanges[Index].Length;
1011 }
1012 return 0;
1013}
1014
1015/**
1016 Read a CPU Save State register on the target processor.
1017
1018 This function abstracts the differences that whether the CPU Save State
1019 register is in the IA32 CPU Save State Map or X64 CPU Save State Map.
1020
1021 This function supports reading a CPU Save State register in SMBase relocation
1022 handler.
1023
1024 @param[in] CpuIndex Specifies the zero-based index of the CPU save
1025 state.
1026 @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
1027 @param[in] Width The number of bytes to read from the CPU save
1028 state.
1029 @param[out] Buffer Upon return, this holds the CPU register value
1030 read from the save state.
1031
1032 @retval EFI_SUCCESS The register was read from Save State.
1033 @retval EFI_NOT_FOUND The register is not defined for the Save State
1034 of Processor.
1035 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
1036
1037**/
1038STATIC
1039EFI_STATUS
1040ReadSaveStateRegisterByIndex (
1041 IN UINTN CpuIndex,
1042 IN UINTN RegisterIndex,
1043 IN UINTN Width,
1044 OUT VOID *Buffer
1045 )
1046{
1047 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
1048
1049 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
1050
1051 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
1052 //
1053 // If 32-bit mode width is zero, then the specified register can not be
1054 // accessed
1055 //
1056 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
1057 return EFI_NOT_FOUND;
1058 }
1059
1060 //
1061 // If Width is bigger than the 32-bit mode width, then the specified
1062 // register can not be accessed
1063 //
1064 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
1065 return EFI_INVALID_PARAMETER;
1066 }
1067
1068 //
1069 // Write return buffer
1070 //
1071 ASSERT(CpuSaveState != NULL);
1072 CopyMem (
1073 Buffer,
1074 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,
1075 Width
1076 );
1077 } else {
1078 //
1079 // If 64-bit mode width is zero, then the specified register can not be
1080 // accessed
1081 //
1082 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
1083 return EFI_NOT_FOUND;
1084 }
1085
1086 //
1087 // If Width is bigger than the 64-bit mode width, then the specified
1088 // register can not be accessed
1089 //
1090 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
1091 return EFI_INVALID_PARAMETER;
1092 }
1093
1094 //
1095 // Write lower 32-bits of return buffer
1096 //
1097 CopyMem (
1098 Buffer,
1099 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,
1100 MIN (4, Width)
1101 );
1102 if (Width >= 4) {
1103 //
1104 // Write upper 32-bits of return buffer
1105 //
1106 CopyMem (
1107 (UINT8 *)Buffer + 4,
1108 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,
1109 Width - 4
1110 );
1111 }
1112 }
1113 return EFI_SUCCESS;
1114}
1115
1116/**
1117 Read an SMM Save State register on the target processor. If this function
1118 returns EFI_UNSUPPORTED, then the caller is responsible for reading the
1119 SMM Save Sate register.
1120
1121 @param[in] CpuIndex The index of the CPU to read the SMM Save State. The
1122 value must be between 0 and the NumberOfCpus field in
1123 the System Management System Table (SMST).
1124 @param[in] Register The SMM Save State register to read.
1125 @param[in] Width The number of bytes to read from the CPU save state.
1126 @param[out] Buffer Upon return, this holds the CPU register value read
1127 from the save state.
1128
1129 @retval EFI_SUCCESS The register was read from Save State.
1130 @retval EFI_INVALID_PARAMTER Buffer is NULL.
1131 @retval EFI_UNSUPPORTED This function does not support reading
1132 Register.
1133**/
1134EFI_STATUS
1135EFIAPI
1136SmmCpuFeaturesReadSaveStateRegister (
1137 IN UINTN CpuIndex,
1138 IN EFI_SMM_SAVE_STATE_REGISTER Register,
1139 IN UINTN Width,
1140 OUT VOID *Buffer
1141 )
1142{
1143 UINTN RegisterIndex;
1144 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
1145
1146 //
1147 // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA
1148 //
1149 if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
1150 //
1151 // Only byte access is supported for this register
1152 //
1153 if (Width != 1) {
1154 return EFI_INVALID_PARAMETER;
1155 }
1156
1157 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
1158
1159 //
1160 // Check CPU mode
1161 //
1162 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
1163 *(UINT8 *)Buffer = 32;
1164 } else {
1165 *(UINT8 *)Buffer = 64;
1166 }
1167
1168 return EFI_SUCCESS;
1169 }
1170
1171 //
1172 // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO
1173 //
1174 if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
1175 return EFI_NOT_FOUND;
1176 }
1177
1178 //
1179 // Convert Register to a register lookup table index. Let
1180 // PiSmmCpuDxeSmm implement other special registers (currently
1181 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
1182 //
1183 RegisterIndex = GetRegisterIndex (Register);
1184 if (RegisterIndex == 0) {
1185 return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?
1186 EFI_NOT_FOUND :
1187 EFI_UNSUPPORTED);
1188 }
1189
1190 return ReadSaveStateRegisterByIndex (CpuIndex, RegisterIndex, Width, Buffer);
1191}
1192
1193/**
1194 Writes an SMM Save State register on the target processor. If this function
1195 returns EFI_UNSUPPORTED, then the caller is responsible for writing the
1196 SMM Save Sate register.
1197
1198 @param[in] CpuIndex The index of the CPU to write the SMM Save State. The
1199 value must be between 0 and the NumberOfCpus field in
1200 the System Management System Table (SMST).
1201 @param[in] Register The SMM Save State register to write.
1202 @param[in] Width The number of bytes to write to the CPU save state.
1203 @param[in] Buffer Upon entry, this holds the new CPU register value.
1204
1205 @retval EFI_SUCCESS The register was written to Save State.
1206 @retval EFI_INVALID_PARAMTER Buffer is NULL.
1207 @retval EFI_UNSUPPORTED This function does not support writing
1208 Register.
1209**/
1210EFI_STATUS
1211EFIAPI
1212SmmCpuFeaturesWriteSaveStateRegister (
1213 IN UINTN CpuIndex,
1214 IN EFI_SMM_SAVE_STATE_REGISTER Register,
1215 IN UINTN Width,
1216 IN CONST VOID *Buffer
1217 )
1218{
1219 UINTN RegisterIndex;
1220 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
1221
1222 //
1223 // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored
1224 //
1225 if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
1226 return EFI_SUCCESS;
1227 }
1228
1229 //
1230 // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported
1231 //
1232 if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
1233 return EFI_NOT_FOUND;
1234 }
1235
1236 //
1237 // Convert Register to a register lookup table index. Let
1238 // PiSmmCpuDxeSmm implement other special registers (currently
1239 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
1240 //
1241 RegisterIndex = GetRegisterIndex (Register);
1242 if (RegisterIndex == 0) {
1243 return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?
1244 EFI_NOT_FOUND :
1245 EFI_UNSUPPORTED);
1246 }
1247
1248 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
1249
1250 //
1251 // Do not write non-writable SaveState, because it will cause exception.
1252 //
1253 if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {
1254 return EFI_UNSUPPORTED;
1255 }
1256
1257 //
1258 // Check CPU mode
1259 //
1260 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
1261 //
1262 // If 32-bit mode width is zero, then the specified register can not be
1263 // accessed
1264 //
1265 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
1266 return EFI_NOT_FOUND;
1267 }
1268
1269 //
1270 // If Width is bigger than the 32-bit mode width, then the specified
1271 // register can not be accessed
1272 //
1273 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
1274 return EFI_INVALID_PARAMETER;
1275 }
1276 //
1277 // Write SMM State register
1278 //
1279 ASSERT (CpuSaveState != NULL);
1280 CopyMem (
1281 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,
1282 Buffer,
1283 Width
1284 );
1285 } else {
1286 //
1287 // If 64-bit mode width is zero, then the specified register can not be
1288 // accessed
1289 //
1290 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
1291 return EFI_NOT_FOUND;
1292 }
1293
1294 //
1295 // If Width is bigger than the 64-bit mode width, then the specified
1296 // register can not be accessed
1297 //
1298 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
1299 return EFI_INVALID_PARAMETER;
1300 }
1301
1302 //
1303 // Write lower 32-bits of SMM State register
1304 //
1305 CopyMem (
1306 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,
1307 Buffer,
1308 MIN (4, Width)
1309 );
1310 if (Width >= 4) {
1311 //
1312 // Write upper 32-bits of SMM State register
1313 //
1314 CopyMem (
1315 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,
1316 (UINT8 *)Buffer + 4,
1317 Width - 4
1318 );
1319 }
1320 }
1321 return EFI_SUCCESS;
1322}
1323
1324/**
1325 This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
1326 notification is completely processed.
1327**/
1328VOID
1329EFIAPI
1330SmmCpuFeaturesCompleteSmmReadyToLock (
1331 VOID
1332 )
1333{
1334}
1335
1336/**
1337 This API provides a method for a CPU to allocate a specific region for
1338 storing page tables.
1339
1340 This API can be called more once to allocate memory for page tables.
1341
1342 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns
1343 a pointer to the allocated buffer. The buffer returned is aligned on a 4KB
1344 boundary. If Pages is 0, then NULL is returned. If there is not enough
1345 memory remaining to satisfy the request, then NULL is returned.
1346
1347 This function can also return NULL if there is no preference on where the
1348 page tables are allocated in SMRAM.
1349
1350 @param Pages The number of 4 KB pages to allocate.
1351
1352 @return A pointer to the allocated buffer for page tables.
1353 @retval NULL Fail to allocate a specific region for storing page tables,
1354 Or there is no preference on where the page tables are
1355 allocated in SMRAM.
1356
1357**/
1358VOID *
1359EFIAPI
1360SmmCpuFeaturesAllocatePageTableMemory (
1361 IN UINTN Pages
1362 )
1363{
1364 return NULL;
1365}
1366
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