1 | /** @file
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2 | OVMF's instance of the PCI Host Bridge Library.
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3 |
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4 | Copyright (C) 2016, Red Hat, Inc.
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5 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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6 |
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7 | SPDX-License-Identifier: BSD-2-Clause-Patent
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8 |
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9 | **/
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10 | #include <IndustryStandard/Pci.h> // PCI_MAX_BUS
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11 | #include <IndustryStandard/Q35MchIch9.h> // INTEL_Q35_MCH_DEVIC...
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12 | #include <Library/BaseMemoryLib.h> // ZeroMem()
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13 | #include <Library/PcdLib.h> // PcdGet64()
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14 | #include <Library/PciHostBridgeLib.h> // PCI_ROOT_BRIDGE_APE...
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15 | #include <Library/PciHostBridgeUtilityLib.h> // PciHostBridgeUtilit...
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16 | #include <Protocol/PciHostBridgeResourceAllocation.h> // EFI_PCI_HOST_BRIDGE...
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17 | #include <Protocol/PciRootBridgeIo.h> // EFI_PCI_ATTRIBUTE_I...
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18 |
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19 | STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture = { MAX_UINT64, 0 };
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20 |
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21 | /**
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22 | Return all the root bridge instances in an array.
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23 |
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24 | @param Count Return the count of root bridge instances.
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25 |
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26 | @return All the root bridge instances in an array.
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27 | The array should be passed into PciHostBridgeFreeRootBridges()
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28 | when it's not used.
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29 | **/
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30 | PCI_ROOT_BRIDGE *
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31 | EFIAPI
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32 | PciHostBridgeGetRootBridges (
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33 | UINTN *Count
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34 | )
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35 | {
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36 | UINT64 Attributes;
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37 | UINT64 AllocationAttributes;
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38 | PCI_ROOT_BRIDGE_APERTURE Io;
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39 | PCI_ROOT_BRIDGE_APERTURE Mem;
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40 | PCI_ROOT_BRIDGE_APERTURE MemAbove4G;
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41 |
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42 | ZeroMem (&Io, sizeof (Io));
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43 | ZeroMem (&Mem, sizeof (Mem));
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44 | ZeroMem (&MemAbove4G, sizeof (MemAbove4G));
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45 |
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46 | Attributes = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |
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47 | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
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48 | EFI_PCI_ATTRIBUTE_ISA_IO_16 |
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49 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
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50 | EFI_PCI_ATTRIBUTE_VGA_MEMORY |
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51 | EFI_PCI_ATTRIBUTE_VGA_IO_16 |
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52 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
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53 |
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54 | AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;
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55 | if (PcdGet64 (PcdPciMmio64Size) > 0) {
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56 | AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
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57 | MemAbove4G.Base = PcdGet64 (PcdPciMmio64Base);
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58 | MemAbove4G.Limit = PcdGet64 (PcdPciMmio64Base) +
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59 | PcdGet64 (PcdPciMmio64Size) - 1;
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60 | } else {
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61 | CopyMem (&MemAbove4G, &mNonExistAperture, sizeof (mNonExistAperture));
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62 | }
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63 |
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64 | Io.Base = PcdGet64 (PcdPciIoBase);
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65 | Io.Limit = PcdGet64 (PcdPciIoBase) + (PcdGet64 (PcdPciIoSize) - 1);
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66 | Mem.Base = PcdGet64 (PcdPciMmio32Base);
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67 | Mem.Limit = PcdGet64 (PcdPciMmio32Base) + (PcdGet64 (PcdPciMmio32Size) - 1);
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68 |
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69 | return PciHostBridgeUtilityGetRootBridges (
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70 | Count,
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71 | Attributes,
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72 | AllocationAttributes,
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73 | FALSE,
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74 | PcdGet16 (PcdOvmfHostBridgePciDevId) != INTEL_Q35_MCH_DEVICE_ID,
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75 | 0,
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76 | PCI_MAX_BUS,
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77 | &Io,
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78 | &Mem,
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79 | &MemAbove4G,
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80 | &mNonExistAperture,
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81 | &mNonExistAperture
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82 | );
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83 | }
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84 |
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85 | /**
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86 | Free the root bridge instances array returned from
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87 | PciHostBridgeGetRootBridges().
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88 |
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89 | @param The root bridge instances array.
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90 | @param The count of the array.
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91 | **/
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92 | VOID
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93 | EFIAPI
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94 | PciHostBridgeFreeRootBridges (
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95 | PCI_ROOT_BRIDGE *Bridges,
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96 | UINTN Count
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97 | )
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98 | {
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99 | PciHostBridgeUtilityFreeRootBridges (Bridges, Count);
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100 | }
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101 |
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102 | /**
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103 | Inform the platform that the resource conflict happens.
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104 |
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105 | @param HostBridgeHandle Handle of the Host Bridge.
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106 | @param Configuration Pointer to PCI I/O and PCI memory resource
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107 | descriptors. The Configuration contains the resources
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108 | for all the root bridges. The resource for each root
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109 | bridge is terminated with END descriptor and an
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110 | additional END is appended indicating the end of the
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111 | entire resources. The resource descriptor field
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112 | values follow the description in
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113 | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
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114 | .SubmitResources().
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115 | **/
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116 | VOID
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117 | EFIAPI
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118 | PciHostBridgeResourceConflict (
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119 | EFI_HANDLE HostBridgeHandle,
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120 | VOID *Configuration
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121 | )
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122 | {
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123 | PciHostBridgeUtilityResourceConflict (Configuration);
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124 | }
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