| 1 | /** @file
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| 2 | Various register numbers and value bits based on the following publications:
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| 3 | - Intel(R) datasheet 316966-002
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| 4 | - Intel(R) datasheet 316972-004
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| 5 |
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| 6 | Copyright (C) 2015, Red Hat, Inc.
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| 7 | Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>
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| 8 |
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| 9 | SPDX-License-Identifier: BSD-2-Clause-Patent
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| 10 | **/
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| 11 |
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| 12 | #ifndef __Q35_MCH_ICH9_H__
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| 13 | #define __Q35_MCH_ICH9_H__
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| 14 |
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| 15 | #include <Library/PciLib.h>
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| 16 | #include <Uefi/UefiBaseType.h>
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| 17 | #include <Uefi/UefiSpec.h>
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| 18 | #include <Protocol/PciRootBridgeIo.h>
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| 19 |
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| 20 | //
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| 21 | // Host Bridge Device ID (DID) value for Q35/MCH
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| 22 | //
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| 23 | #define INTEL_Q35_MCH_DEVICE_ID 0x29C0
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| 24 |
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| 25 | //
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| 26 | // B/D/F/Type: 0/0/0/PCI
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| 27 | //
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| 28 | #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))
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| 29 |
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| 30 | #define MCH_EXT_TSEG_MB 0x50
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| 31 | #define MCH_EXT_TSEG_MB_QUERY 0xFFFF
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| 32 |
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| 33 | #define MCH_GGC 0x52
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| 34 | #define MCH_GGC_IVD BIT1
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| 35 |
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| 36 | #define MCH_PCIEXBAR_LOW 0x60
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| 37 | #define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF
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| 38 | #define MCH_PCIEXBAR_BUS_FF 0
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| 39 | #define MCH_PCIEXBAR_EN BIT0
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| 40 |
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| 41 | #define MCH_PCIEXBAR_HIGH 0x64
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| 42 | #define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0
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| 43 |
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| 44 | #define MCH_PAM0 0x90
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| 45 | #define MCH_PAM1 0x91
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| 46 | #define MCH_PAM2 0x92
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| 47 | #define MCH_PAM3 0x93
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| 48 | #define MCH_PAM4 0x94
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| 49 | #define MCH_PAM5 0x95
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| 50 | #define MCH_PAM6 0x96
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| 51 |
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| 52 | #define MCH_DEFAULT_SMBASE_CTL 0x9C
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| 53 | #define MCH_DEFAULT_SMBASE_QUERY 0xFF
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| 54 | #define MCH_DEFAULT_SMBASE_IN_RAM 0x01
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| 55 | #define MCH_DEFAULT_SMBASE_LCK 0x02
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| 56 | #define MCH_DEFAULT_SMBASE_SIZE SIZE_128KB
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| 57 |
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| 58 | #define MCH_SMRAM 0x9D
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| 59 | #define MCH_SMRAM_D_LCK BIT4
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| 60 | #define MCH_SMRAM_G_SMRAME BIT3
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| 61 |
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| 62 | #define MCH_ESMRAMC 0x9E
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| 63 | #define MCH_ESMRAMC_H_SMRAME BIT7
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| 64 | #define MCH_ESMRAMC_E_SMERR BIT6
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| 65 | #define MCH_ESMRAMC_SM_CACHE BIT5
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| 66 | #define MCH_ESMRAMC_SM_L1 BIT4
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| 67 | #define MCH_ESMRAMC_SM_L2 BIT3
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| 68 | #define MCH_ESMRAMC_TSEG_EXT (BIT2 | BIT1)
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| 69 | #define MCH_ESMRAMC_TSEG_8MB BIT2
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| 70 | #define MCH_ESMRAMC_TSEG_2MB BIT1
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| 71 | #define MCH_ESMRAMC_TSEG_1MB 0
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| 72 | #define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1)
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| 73 | #define MCH_ESMRAMC_T_EN BIT0
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| 74 |
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| 75 | #define MCH_GBSM 0xA4
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| 76 | #define MCH_GBSM_MB_SHIFT 20
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| 77 |
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| 78 | #define MCH_BGSM 0xA8
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| 79 | #define MCH_BGSM_MB_SHIFT 20
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| 80 |
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| 81 | #define MCH_TSEGMB 0xAC
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| 82 | #define MCH_TSEGMB_MB_SHIFT 20
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| 83 |
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| 84 | #define MCH_TOLUD 0xB0
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| 85 | #define MCH_TOLUD_MB_SHIFT 4
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| 86 |
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| 87 | //
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| 88 | // B/D/F/Type: 0/0x1f/0/PCI
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| 89 | //
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| 90 | #define POWER_MGMT_REGISTER_Q35(Offset) \
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| 91 | PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset))
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| 92 |
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| 93 | #define POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS(Offset) \
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| 94 | EFI_PCI_ADDRESS (0, 0x1f, 0, (Offset))
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| 95 |
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| 96 | #define ICH9_PMBASE 0x40
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| 97 | #define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
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| 98 | BIT10 | BIT9 | BIT8 | BIT7)
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| 99 |
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| 100 | #define ICH9_ACPI_CNTL 0x44
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| 101 | #define ICH9_ACPI_CNTL_ACPI_EN BIT7
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| 102 |
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| 103 | #define ICH9_GEN_PMCON_1 0xA0
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| 104 | #define ICH9_GEN_PMCON_1_SMI_LOCK BIT4
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| 105 |
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| 106 | #define ICH9_RCBA 0xF0
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| 107 | #define ICH9_RCBA_EN BIT0
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| 108 |
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| 109 | //
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| 110 | // IO ports
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| 111 | //
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| 112 | #define ICH9_APM_CNT 0xB2
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| 113 | #define ICH9_APM_CNT_CPU_HOTPLUG 0x04
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| 114 | #define ICH9_APM_STS 0xB3
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| 115 |
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| 116 | #define ICH9_CPU_HOTPLUG_BASE 0x0CD8
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| 117 |
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| 118 | //
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| 119 | // IO ports relative to PMBASE
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| 120 | //
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| 121 | #define ICH9_PMBASE_OFS_SMI_EN 0x30
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| 122 | #define ICH9_SMI_EN_APMC_EN BIT5
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| 123 | #define ICH9_SMI_EN_GBL_SMI_EN BIT0
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| 124 |
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| 125 | #define ICH9_ROOT_COMPLEX_BASE 0xFED1C000
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| 126 |
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| 127 | #endif
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