| 1 | /** @file
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| 2 | Definitions for network adapter card.
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| 3 |
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| 4 | Copyright (c) 2006 - 2007, Intel Corporation. All rights reserved.<BR>
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| 5 | This program and the accompanying materials
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| 6 | are licensed and made available under the terms and conditions of the BSD License
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| 7 | which accompanies this distribution. The full text of the license may be found at
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| 8 | http://opensource.org/licenses/bsd-license.php
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| 9 |
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| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 12 |
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| 13 | **/
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| 14 |
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| 15 | #ifndef _E100B_H_
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| 16 | #define _E100B_H_
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| 17 |
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| 18 | // pci config offsets:
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| 19 |
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| 20 | #define RX_BUFFER_COUNT 32
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| 21 | #define TX_BUFFER_COUNT 32
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| 22 |
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| 23 | #define PCI_VENDOR_ID_INTEL 0x8086
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| 24 | #define PCI_DEVICE_ID_INTEL_82557 0x1229
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| 25 | #define D100_VENDOR_ID 0x8086
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| 26 | #define D100_DEVICE_ID 0x1229
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| 27 | #define D102_DEVICE_ID 0x2449
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| 28 |
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| 29 | #define ICH3_DEVICE_ID_1 0x1031
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| 30 | #define ICH3_DEVICE_ID_2 0x1032
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| 31 | #define ICH3_DEVICE_ID_3 0x1033
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| 32 | #define ICH3_DEVICE_ID_4 0x1034
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| 33 | #define ICH3_DEVICE_ID_5 0x1035
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| 34 | #define ICH3_DEVICE_ID_6 0x1036
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| 35 | #define ICH3_DEVICE_ID_7 0x1037
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| 36 | #define ICH3_DEVICE_ID_8 0x1038
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| 37 |
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| 38 | #define SPEEDO_DEVICE_ID 0x1227
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| 39 | #define SPLASH1_DEVICE_ID 0x1226
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| 40 |
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| 41 |
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| 42 | // bit fields for the command
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| 43 | #define PCI_COMMAND_MASTER 0x04 // bit 2
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| 44 | #define PCI_COMMAND_IO 0x01 // bit 0
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| 45 | #define PCI_COMMAND 0x04
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| 46 | #define PCI_LATENCY_TIMER 0x0D
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| 47 |
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| 48 | #define ETHER_MAC_ADDR_LEN 6
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| 49 | #ifdef AVL_XXX
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| 50 | #define ETHER_HEADER_LEN 14
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| 51 | // media interface type
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| 52 | // #define INTERFACE_TYPE "
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| 53 |
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| 54 | // Hardware type values
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| 55 | #define HW_ETHER_TYPE 1
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| 56 | #define HW_EXPERIMENTAL_ETHER_TYPE 2
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| 57 | #define HW_IEEE_TYPE 6
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| 58 | #define HW_ARCNET_TYPE 7
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| 59 |
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| 60 | #endif // AVL_XXX
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| 61 |
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| 62 | #define MAX_ETHERNET_PKT_SIZE 1514 // including eth header
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| 63 | #define RX_BUFFER_SIZE 1536 // including crc and padding
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| 64 | #define TX_BUFFER_SIZE 64
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| 65 | #define ETH_MTU 1500 // does not include ethernet header length
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| 66 |
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| 67 | #define SPEEDO3_TOTAL_SIZE 0x20
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| 68 |
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| 69 | #pragma pack(1)
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| 70 |
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| 71 | typedef struct eth {
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| 72 | UINT8 dest_addr[PXE_HWADDR_LEN_ETHER];
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| 73 | UINT8 src_addr[PXE_HWADDR_LEN_ETHER];
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| 74 | UINT16 type;
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| 75 | } EtherHeader;
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| 76 |
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| 77 | #pragma pack(1)
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| 78 | typedef struct CONFIG_HEADER {
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| 79 | UINT16 VendorID;
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| 80 | UINT16 DeviceID;
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| 81 | UINT16 Command;
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| 82 | UINT16 Status;
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| 83 | UINT16 RevID;
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| 84 | UINT16 ClassID;
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| 85 | UINT8 CacheLineSize;
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| 86 | UINT8 LatencyTimer;
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| 87 | UINT8 HeaderType; // must be zero to impose this structure...
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| 88 | UINT8 BIST; // built-in self test
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| 89 | UINT32 BaseAddressReg_0; // memory mapped address
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| 90 | UINT32 BaseAddressReg_1; //io mapped address, Base IO address
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| 91 | UINT32 BaseAddressReg_2; // option rom address
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| 92 | UINT32 BaseAddressReg_3;
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| 93 | UINT32 BaseAddressReg_4;
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| 94 | UINT32 BaseAddressReg_5;
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| 95 | UINT32 CardBusCISPtr;
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| 96 | UINT16 SubVendorID;
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| 97 | UINT16 SubSystemID;
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| 98 | UINT32 ExpansionROMBaseAddr;
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| 99 | UINT8 CapabilitiesPtr;
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| 100 | UINT8 reserved1;
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| 101 | UINT16 Reserved2;
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| 102 | UINT32 Reserved3;
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| 103 | UINT8 int_line;
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| 104 | UINT8 int_pin;
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| 105 | UINT8 Min_gnt;
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| 106 | UINT8 Max_lat;
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| 107 | } PCI_CONFIG_HEADER;
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| 108 | #pragma pack()
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| 109 |
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| 110 | //-------------------------------------------------------------------------
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| 111 | // Offsets to the various registers.
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| 112 | // All accesses need not be longword aligned.
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| 113 | //-------------------------------------------------------------------------
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| 114 | enum speedo_offsets {
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| 115 | SCBStatus = 0, SCBCmd = 2, // Rx/Command Unit command and status.
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| 116 | SCBPointer = 4, // General purpose pointer.
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| 117 | SCBPort = 8, // Misc. commands and operands.
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| 118 | SCBflash = 12, SCBeeprom = 14, // EEPROM and flash memory control.
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| 119 | SCBCtrlMDI = 16, // MDI interface control.
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| 120 | SCBEarlyRx = 20, // Early receive byte count.
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| 121 | SCBEarlyRxInt = 24, SCBFlowCtrlReg = 25, SCBPmdr = 27,
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| 122 | // offsets for general control registers (GCRs)
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| 123 | SCBGenCtrl = 28, SCBGenStatus = 29, SCBGenCtrl2 = 30, SCBRsvd = 31
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| 124 | };
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| 125 |
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| 126 | #define GCR2_EEPROM_ACCESS_SEMAPHORE 0x80 // bit offset into the gcr2
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| 127 |
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| 128 | //-------------------------------------------------------------------------
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| 129 | // Action commands - Commands that can be put in a command list entry.
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| 130 | //-------------------------------------------------------------------------
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| 131 | enum commands {
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| 132 | CmdNOp = 0, CmdIASetup = 1, CmdConfigure = 2, CmdMulticastList = 3,
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| 133 | CmdTx = 4, CmdTDR = 5, CmdDump = 6, CmdDiagnose = 7,
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| 134 | CmdSuspend = 0x4000, /* Suspend after completion. */
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| 135 | CmdIntr = 0x2000, /* Interrupt after completion. */
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| 136 | CmdTxFlex = 0x0008 /* Use "Flexible mode" for CmdTx command. */
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| 137 | };
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| 138 |
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| 139 | //-------------------------------------------------------------------------
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| 140 | // port commands
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| 141 | //-------------------------------------------------------------------------
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| 142 | #define PORT_RESET 0
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| 143 | #define PORT_SELF_TEST 1
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| 144 | #define POR_SELECTIVE_RESET 2
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| 145 | #define PORT_DUMP_POINTER 2
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| 146 |
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| 147 | //-------------------------------------------------------------------------
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| 148 | // SCB Command Word bit definitions
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| 149 | //-------------------------------------------------------------------------
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| 150 | //- CUC fields
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| 151 | #define CU_START 0x0010
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| 152 | #define CU_RESUME 0x0020
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| 153 | #define CU_STATSADDR 0x0040
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| 154 | #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
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| 155 | #define CU_CMD_BASE 0x0060 /* Base address to add to add CU commands. */
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| 156 | #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
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| 157 |
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| 158 | //- RUC fields
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| 159 | #define RX_START 0x0001
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| 160 | #define RX_RESUME 0x0002
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| 161 | #define RX_ABORT 0x0004
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| 162 | #define RX_ADDR_LOAD 0x0006 /* load ru_base_reg */
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| 163 | #define RX_RESUMENR 0x0007
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| 164 |
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| 165 | // Interrupt fields (assuming byte addressing)
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| 166 | #define INT_MASK 0x0100
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| 167 | #define DRVR_INT 0x0200 /* Driver generated interrupt. */
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| 168 |
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| 169 | //- CB Status Word
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| 170 | #define CMD_STATUS_COMPLETE 0x8000
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| 171 | #define RX_STATUS_COMPLETE 0x8000
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| 172 | #define CMD_STATUS_MASK 0xF000
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| 173 |
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| 174 | //-------------------------------------------------------------------------
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| 175 | //- SCB Status bits:
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| 176 | // Interrupts are ACKed by writing to the upper 6 interrupt bits
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| 177 | //-------------------------------------------------------------------------
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| 178 | #define SCB_STATUS_MASK 0xFC00 // bits 2-7 - STATUS/ACK Mask
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| 179 | #define SCB_STATUS_CX_TNO 0x8000 // BIT_15 - CX or TNO Interrupt
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| 180 | #define SCB_STATUS_FR 0x4000 // BIT_14 - FR Interrupt
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| 181 | #define SCB_STATUS_CNA 0x2000 // BIT_13 - CNA Interrupt
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| 182 | #define SCB_STATUS_RNR 0x1000 // BIT_12 - RNR Interrupt
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| 183 | #define SCB_STATUS_MDI 0x0800 // BIT_11 - MDI R/W Done Interrupt
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| 184 | #define SCB_STATUS_SWI 0x0400 // BIT_10 - SWI Interrupt
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| 185 |
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| 186 | // CU STATUS: bits 6 & 7
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| 187 | #define SCB_STATUS_CU_MASK 0x00C0 // bits 6 & 7
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| 188 | #define SCB_STATUS_CU_IDLE 0x0000 // 00
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| 189 | #define SCB_STATUS_CU_SUSPEND 0x0040 // 01
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| 190 | #define SCB_STATUS_CU_ACTIVE 0x0080 // 10
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| 191 |
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| 192 | // RU STATUS: bits 2-5
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| 193 | #define SCB_RUS_IDLE 0x0000
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| 194 | #define SCB_RUS_SUSPENDED 0x0004 // bit 2
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| 195 | #define SCB_RUS_NO_RESOURCES 0x0008 // bit 3
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| 196 | #define SCB_RUS_READY 0x0010 // bit 4
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| 197 |
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| 198 | //-------------------------------------------------------------------------
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| 199 | // Bit Mask definitions
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| 200 | //-------------------------------------------------------------------------
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| 201 | #define BIT_0 0x0001
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| 202 | #define BIT_1 0x0002
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| 203 | #define BIT_2 0x0004
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| 204 | #define BIT_3 0x0008
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| 205 | #define BIT_4 0x0010
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| 206 | #define BIT_5 0x0020
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| 207 | #define BIT_6 0x0040
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| 208 | #define BIT_7 0x0080
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| 209 | #define BIT_8 0x0100
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| 210 | #define BIT_9 0x0200
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| 211 | #define BIT_10 0x0400
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| 212 | #define BIT_11 0x0800
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| 213 | #define BIT_12 0x1000
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| 214 | #define BIT_13 0x2000
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| 215 | #define BIT_14 0x4000
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| 216 | #define BIT_15 0x8000
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| 217 | #define BIT_24 0x01000000
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| 218 | #define BIT_28 0x10000000
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| 219 |
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| 220 |
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| 221 | //-------------------------------------------------------------------------
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| 222 | // MDI Control register bit definitions
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| 223 | //-------------------------------------------------------------------------
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| 224 | #define MDI_DATA_MASK BIT_0_15 // MDI Data port
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| 225 | #define MDI_REG_ADDR BIT_16_20 // which MDI register to read/write
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| 226 | #define MDI_PHY_ADDR BIT_21_25 // which PHY to read/write
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| 227 | #define MDI_PHY_OPCODE BIT_26_27 // which PHY to read/write
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| 228 | #define MDI_PHY_READY BIT_28 // PHY is ready for another MDI cycle
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| 229 | #define MDI_PHY_INT_ENABLE BIT_29 // Assert INT at MDI cycle completion
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| 230 |
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| 231 | #define BIT_0_2 0x0007
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| 232 | #define BIT_0_3 0x000F
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| 233 | #define BIT_0_4 0x001F
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| 234 | #define BIT_0_5 0x003F
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| 235 | #define BIT_0_6 0x007F
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| 236 | #define BIT_0_7 0x00FF
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| 237 | #define BIT_0_8 0x01FF
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| 238 | #define BIT_0_13 0x3FFF
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| 239 | #define BIT_0_15 0xFFFF
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| 240 | #define BIT_1_2 0x0006
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| 241 | #define BIT_1_3 0x000E
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| 242 | #define BIT_2_5 0x003C
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| 243 | #define BIT_3_4 0x0018
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| 244 | #define BIT_4_5 0x0030
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| 245 | #define BIT_4_6 0x0070
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| 246 | #define BIT_4_7 0x00F0
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| 247 | #define BIT_5_7 0x00E0
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| 248 | #define BIT_5_9 0x03E0
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| 249 | #define BIT_5_12 0x1FE0
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| 250 | #define BIT_5_15 0xFFE0
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| 251 | #define BIT_6_7 0x00c0
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| 252 | #define BIT_7_11 0x0F80
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| 253 | #define BIT_8_10 0x0700
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| 254 | #define BIT_9_13 0x3E00
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| 255 | #define BIT_12_15 0xF000
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| 256 |
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| 257 | #define BIT_16_20 0x001F0000
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| 258 | #define BIT_21_25 0x03E00000
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| 259 | #define BIT_26_27 0x0C000000
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| 260 |
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| 261 | //-------------------------------------------------------------------------
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| 262 | // MDI Control register opcode definitions
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| 263 | //-------------------------------------------------------------------------
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| 264 | #define MDI_WRITE 1 // Phy Write
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| 265 | #define MDI_READ 2 // Phy read
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| 266 |
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| 267 | //-------------------------------------------------------------------------
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| 268 | // PHY 100 MDI Register/Bit Definitions
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| 269 | //-------------------------------------------------------------------------
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| 270 | // MDI register set
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| 271 | #define MDI_CONTROL_REG 0x00 // MDI control register
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| 272 | #define MDI_STATUS_REG 0x01 // MDI Status regiser
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| 273 | #define PHY_ID_REG_1 0x02 // Phy indentification reg (word 1)
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| 274 | #define PHY_ID_REG_2 0x03 // Phy indentification reg (word 2)
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| 275 | #define AUTO_NEG_ADVERTISE_REG 0x04 // Auto-negotiation advertisement
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| 276 | #define AUTO_NEG_LINK_PARTNER_REG 0x05 // Auto-negotiation link partner ability
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| 277 | #define AUTO_NEG_EXPANSION_REG 0x06 // Auto-negotiation expansion
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| 278 | #define AUTO_NEG_NEXT_PAGE_REG 0x07 // Auto-negotiation next page transmit
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| 279 | #define EXTENDED_REG_0 0x10 // Extended reg 0 (Phy 100 modes)
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| 280 | #define EXTENDED_REG_1 0x14 // Extended reg 1 (Phy 100 error indications)
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| 281 | #define NSC_CONG_CONTROL_REG 0x17 // National (TX) congestion control
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| 282 | #define NSC_SPEED_IND_REG 0x19 // National (TX) speed indication
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| 283 |
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| 284 | // MDI Control register bit definitions
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| 285 | #define MDI_CR_COLL_TEST_ENABLE BIT_7 // Collision test enable
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| 286 | #define MDI_CR_FULL_HALF BIT_8 // FDX =1, half duplex =0
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| 287 | #define MDI_CR_RESTART_AUTO_NEG BIT_9 // Restart auto negotiation
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| 288 | #define MDI_CR_ISOLATE BIT_10 // Isolate PHY from MII
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| 289 | #define MDI_CR_POWER_DOWN BIT_11 // Power down
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| 290 | #define MDI_CR_AUTO_SELECT BIT_12 // Auto speed select enable
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| 291 | #define MDI_CR_10_100 BIT_13 // 0 = 10Mbs, 1 = 100Mbs
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| 292 | #define MDI_CR_LOOPBACK BIT_14 // 0 = normal, 1 = loopback
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| 293 | #define MDI_CR_RESET BIT_15 // 0 = normal, 1 = PHY reset
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| 294 |
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| 295 | // MDI Status register bit definitions
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| 296 | #define MDI_SR_EXT_REG_CAPABLE BIT_0 // Extended register capabilities
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| 297 | #define MDI_SR_JABBER_DETECT BIT_1 // Jabber detected
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| 298 | #define MDI_SR_LINK_STATUS BIT_2 // Link Status -- 1 = link
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| 299 | #define MDI_SR_AUTO_SELECT_CAPABLE BIT_3 // Auto speed select capable
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| 300 | #define MDI_SR_REMOTE_FAULT_DETECT BIT_4 // Remote fault detect
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| 301 | #define MDI_SR_AUTO_NEG_COMPLETE BIT_5 // Auto negotiation complete
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| 302 | #define MDI_SR_10T_HALF_DPX BIT_11 // 10BaseT Half Duplex capable
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| 303 | #define MDI_SR_10T_FULL_DPX BIT_12 // 10BaseT full duplex capable
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| 304 | #define MDI_SR_TX_HALF_DPX BIT_13 // TX Half Duplex capable
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| 305 | #define MDI_SR_TX_FULL_DPX BIT_14 // TX full duplex capable
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| 306 | #define MDI_SR_T4_CAPABLE BIT_15 // T4 capable
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| 307 |
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| 308 | // Auto-Negotiation advertisement register bit definitions
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| 309 | #define NWAY_AD_SELCTOR_FIELD BIT_0_4 // identifies supported protocol
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| 310 | #define NWAY_AD_ABILITY BIT_5_12 // technologies that are supported
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| 311 | #define NWAY_AD_10T_HALF_DPX BIT_5 // 10BaseT Half Duplex capable
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| 312 | #define NWAY_AD_10T_FULL_DPX BIT_6 // 10BaseT full duplex capable
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| 313 | #define NWAY_AD_TX_HALF_DPX BIT_7 // TX Half Duplex capable
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| 314 | #define NWAY_AD_TX_FULL_DPX BIT_8 // TX full duplex capable
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| 315 | #define NWAY_AD_T4_CAPABLE BIT_9 // T4 capable
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| 316 | #define NWAY_AD_REMOTE_FAULT BIT_13 // indicates local remote fault
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| 317 | #define NWAY_AD_RESERVED BIT_14 // reserved
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| 318 | #define NWAY_AD_NEXT_PAGE BIT_15 // Next page (not supported)
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| 319 |
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| 320 | // Auto-Negotiation link partner ability register bit definitions
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| 321 | #define NWAY_LP_SELCTOR_FIELD BIT_0_4 // identifies supported protocol
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| 322 | #define NWAY_LP_ABILITY BIT_5_9 // technologies that are supported
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| 323 | #define NWAY_LP_REMOTE_FAULT BIT_13 // indicates partner remote fault
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| 324 | #define NWAY_LP_ACKNOWLEDGE BIT_14 // acknowledge
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| 325 | #define NWAY_LP_NEXT_PAGE BIT_15 // Next page (not supported)
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| 326 |
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| 327 | // Auto-Negotiation expansion register bit definitions
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| 328 | #define NWAY_EX_LP_NWAY BIT_0 // link partner is NWAY
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| 329 | #define NWAY_EX_PAGE_RECEIVED BIT_1 // link code word received
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| 330 | #define NWAY_EX_NEXT_PAGE_ABLE BIT_2 // local is next page able
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| 331 | #define NWAY_EX_LP_NEXT_PAGE_ABLE BIT_3 // partner is next page able
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| 332 | #define NWAY_EX_PARALLEL_DET_FLT BIT_4 // parallel detection fault
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| 333 | #define NWAY_EX_RESERVED BIT_5_15 // reserved
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| 334 |
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| 335 |
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| 336 | // PHY 100 Extended Register 0 bit definitions
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| 337 | #define PHY_100_ER0_FDX_INDIC BIT_0 // 1 = FDX, 0 = half duplex
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| 338 | #define PHY_100_ER0_SPEED_INDIC BIT_1 // 1 = 100mbs, 0= 10mbs
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| 339 | #define PHY_100_ER0_WAKE_UP BIT_2 // Wake up DAC
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| 340 | #define PHY_100_ER0_RESERVED BIT_3_4 // Reserved
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| 341 | #define PHY_100_ER0_REV_CNTRL BIT_5_7 // Revsion control (A step = 000)
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| 342 | #define PHY_100_ER0_FORCE_FAIL BIT_8 // Force Fail is enabled
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| 343 | #define PHY_100_ER0_TEST BIT_9_13 // Revsion control (A step = 000)
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| 344 | #define PHY_100_ER0_LINKDIS BIT_14 // Link integrity test is disabled
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| 345 | #define PHY_100_ER0_JABDIS BIT_15 // Jabber function is disabled
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| 346 |
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| 347 |
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| 348 | // PHY 100 Extended Register 1 bit definitions
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| 349 | #define PHY_100_ER1_RESERVED BIT_0_8 // Reserved
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| 350 | #define PHY_100_ER1_CH2_DET_ERR BIT_9 // Channel 2 EOF detection error
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| 351 | #define PHY_100_ER1_MANCH_CODE_ERR BIT_10 // Manchester code error
|
|---|
| 352 | #define PHY_100_ER1_EOP_ERR BIT_11 // EOP error
|
|---|
| 353 | #define PHY_100_ER1_BAD_CODE_ERR BIT_12 // bad code error
|
|---|
| 354 | #define PHY_100_ER1_INV_CODE_ERR BIT_13 // invalid code error
|
|---|
| 355 | #define PHY_100_ER1_DC_BAL_ERR BIT_14 // DC balance error
|
|---|
| 356 | #define PHY_100_ER1_PAIR_SKEW_ERR BIT_15 // Pair skew error
|
|---|
| 357 |
|
|---|
| 358 | // National Semiconductor TX phy congestion control register bit definitions
|
|---|
| 359 | #define NSC_TX_CONG_TXREADY BIT_10 // Makes TxReady an input
|
|---|
| 360 | #define NSC_TX_CONG_ENABLE BIT_8 // Enables congestion control
|
|---|
| 361 | #define NSC_TX_CONG_F_CONNECT BIT_5 // Enables congestion control
|
|---|
| 362 |
|
|---|
| 363 | // National Semiconductor TX phy speed indication register bit definitions
|
|---|
| 364 | #define NSC_TX_SPD_INDC_SPEED BIT_6 // 0 = 100mb, 1=10mb
|
|---|
| 365 |
|
|---|
| 366 | //-------------------------------------------------------------------------
|
|---|
| 367 | // Phy related constants
|
|---|
| 368 | //-------------------------------------------------------------------------
|
|---|
| 369 | #define PHY_503 0
|
|---|
| 370 | #define PHY_100_A 0x000003E0
|
|---|
| 371 | #define PHY_100_C 0x035002A8
|
|---|
| 372 | #define PHY_TX_ID 0x015002A8
|
|---|
| 373 | #define PHY_NSC_TX 0x5c002000
|
|---|
| 374 | #define PHY_OTHER 0xFFFF
|
|---|
| 375 |
|
|---|
| 376 | #define PHY_MODEL_REV_ID_MASK 0xFFF0FFFF
|
|---|
| 377 | #define PARALLEL_DETECT 0
|
|---|
| 378 | #define N_WAY 1
|
|---|
| 379 |
|
|---|
| 380 | #define RENEGOTIATE_TIME 35 // (3.5 Seconds)
|
|---|
| 381 |
|
|---|
| 382 | #define CONNECTOR_AUTO 0
|
|---|
| 383 | #define CONNECTOR_TPE 1
|
|---|
| 384 | #define CONNECTOR_MII 2
|
|---|
| 385 |
|
|---|
| 386 | //-------------------------------------------------------------------------
|
|---|
| 387 |
|
|---|
| 388 | /* The Speedo3 Rx and Tx frame/buffer descriptors. */
|
|---|
| 389 | #pragma pack(1)
|
|---|
| 390 | struct CB_Header { /* A generic descriptor. */
|
|---|
| 391 | UINT16 status; /* Offset 0. */
|
|---|
| 392 | UINT16 command; /* Offset 2. */
|
|---|
| 393 | UINT32 link; /* struct descriptor * */
|
|---|
| 394 | };
|
|---|
| 395 |
|
|---|
| 396 | /* transmit command block structure */
|
|---|
| 397 | #pragma pack(1)
|
|---|
| 398 | typedef struct s_TxCB {
|
|---|
| 399 | struct CB_Header cb_header;
|
|---|
| 400 | UINT32 PhysTBDArrayAddres; /* address of an array that contains
|
|---|
| 401 | physical TBD pointers */
|
|---|
| 402 | UINT16 ByteCount; /* immediate data count = 0 always */
|
|---|
| 403 | UINT8 Threshold;
|
|---|
| 404 | UINT8 TBDCount;
|
|---|
| 405 | UINT8 ImmediateData[TX_BUFFER_SIZE];
|
|---|
| 406 | /* following fields are not seen by the 82557 */
|
|---|
| 407 | struct TBD {
|
|---|
| 408 | UINT32 phys_buf_addr;
|
|---|
| 409 | UINT32 buf_len;
|
|---|
| 410 | } TBDArray[MAX_XMIT_FRAGMENTS];
|
|---|
| 411 | UINT32 PhysArrayAddr; /* in case the one in the header is lost */
|
|---|
| 412 | UINT32 PhysTCBAddress; /* for this TCB */
|
|---|
| 413 | struct s_TxCB *NextTCBVirtualLinkPtr;
|
|---|
| 414 | struct s_TxCB *PrevTCBVirtualLinkPtr;
|
|---|
| 415 | UINT64 free_data_ptr; // to be given to the upper layer when this xmit completes1
|
|---|
| 416 | }TxCB;
|
|---|
| 417 |
|
|---|
| 418 | /* The Speedo3 Rx and Tx buffer descriptors. */
|
|---|
| 419 | #pragma pack(1)
|
|---|
| 420 | typedef struct s_RxFD { /* Receive frame descriptor. */
|
|---|
| 421 | struct CB_Header cb_header;
|
|---|
| 422 | UINT32 rx_buf_addr; /* VOID * */
|
|---|
| 423 | UINT16 ActualCount;
|
|---|
| 424 | UINT16 RFDSize;
|
|---|
| 425 | UINT8 RFDBuffer[RX_BUFFER_SIZE];
|
|---|
| 426 | UINT8 forwarded;
|
|---|
| 427 | UINT8 junk[3];
|
|---|
| 428 | }RxFD;
|
|---|
| 429 |
|
|---|
| 430 | /* Elements of the RxFD.status word. */
|
|---|
| 431 | #define RX_COMPLETE 0x8000
|
|---|
| 432 | #define RX_FRAME_OK 0x2000
|
|---|
| 433 |
|
|---|
| 434 | /* Elements of the dump_statistics block. This block must be lword aligned. */
|
|---|
| 435 | #pragma pack(1)
|
|---|
| 436 | struct speedo_stats {
|
|---|
| 437 | UINT32 tx_good_frames;
|
|---|
| 438 | UINT32 tx_coll16_errs;
|
|---|
| 439 | UINT32 tx_late_colls;
|
|---|
| 440 | UINT32 tx_underruns;
|
|---|
| 441 | UINT32 tx_lost_carrier;
|
|---|
| 442 | UINT32 tx_deferred;
|
|---|
| 443 | UINT32 tx_one_colls;
|
|---|
| 444 | UINT32 tx_multi_colls;
|
|---|
| 445 | UINT32 tx_total_colls;
|
|---|
| 446 | UINT32 rx_good_frames;
|
|---|
| 447 | UINT32 rx_crc_errs;
|
|---|
| 448 | UINT32 rx_align_errs;
|
|---|
| 449 | UINT32 rx_resource_errs;
|
|---|
| 450 | UINT32 rx_overrun_errs;
|
|---|
| 451 | UINT32 rx_colls_errs;
|
|---|
| 452 | UINT32 rx_runt_errs;
|
|---|
| 453 | UINT32 done_marker;
|
|---|
| 454 | };
|
|---|
| 455 | #pragma pack()
|
|---|
| 456 |
|
|---|
| 457 |
|
|---|
| 458 | struct Krn_Mem{
|
|---|
| 459 | RxFD rx_ring[RX_BUFFER_COUNT];
|
|---|
| 460 | TxCB tx_ring[TX_BUFFER_COUNT];
|
|---|
| 461 | struct speedo_stats statistics;
|
|---|
| 462 | };
|
|---|
| 463 | #define MEMORY_NEEDED sizeof(struct Krn_Mem)
|
|---|
| 464 |
|
|---|
| 465 | /* The parameters for a CmdConfigure operation.
|
|---|
| 466 | There are so many options that it would be difficult to document each bit.
|
|---|
| 467 | We mostly use the default or recommended settings.
|
|---|
| 468 | */
|
|---|
| 469 |
|
|---|
| 470 | /*
|
|---|
| 471 | *--------------------------------------------------------------------------
|
|---|
| 472 | * Configuration CB Parameter Bit Definitions
|
|---|
| 473 | *--------------------------------------------------------------------------
|
|---|
| 474 | */
|
|---|
| 475 | // - Byte 0 (Default Value = 16h)
|
|---|
| 476 | #define CFIG_BYTE_COUNT 0x16 // 22 Configuration Bytes
|
|---|
| 477 |
|
|---|
| 478 | //- Byte 1 (Default Value = 88h)
|
|---|
| 479 | #define CFIG_TXRX_FIFO_LIMIT 0x88
|
|---|
| 480 |
|
|---|
| 481 | //- Byte 2 (Default Value = 0)
|
|---|
| 482 | #define CFIG_ADAPTIVE_IFS 0
|
|---|
| 483 |
|
|---|
| 484 | //- Byte 3 (Default Value = 0, ALWAYS. This byte is RESERVED)
|
|---|
| 485 | #define CFIG_RESERVED 0
|
|---|
| 486 |
|
|---|
| 487 | //- Byte 4 (Default Value = 0. Default implies that Rx DMA cannot be
|
|---|
| 488 | //- preempted).
|
|---|
| 489 | #define CFIG_RXDMA_BYTE_COUNT 0
|
|---|
| 490 |
|
|---|
| 491 | //- Byte 5 (Default Value = 80h. Default implies that Tx DMA cannot be
|
|---|
| 492 | //- preempted. However, setting these counters is enabled.)
|
|---|
| 493 | #define CFIG_DMBC_ENABLE 0x80
|
|---|
| 494 |
|
|---|
| 495 | //- Byte 6 (Default Value = 33h. Late SCB enabled, No TNO interrupts,
|
|---|
| 496 | //- CNA interrupts and do not save bad frames.)
|
|---|
| 497 | #define CFIG_LATE_SCB 1 // BIT 0
|
|---|
| 498 | #define CFIG_TNO_INTERRUPT 0x4 // BIT 2
|
|---|
| 499 | #define CFIG_CI_INTERRUPT 0x8 // BIT 3
|
|---|
| 500 | #define CFIG_SAVE_BAD_FRAMES 0x80 // BIT_7
|
|---|
| 501 |
|
|---|
| 502 | //- Byte 7 (Default Value = 7h. Discard short frames automatically and
|
|---|
| 503 | //- attempt upto 3 retries on transmit.)
|
|---|
| 504 | #define CFIG_DISCARD_SHORTRX 0x00001
|
|---|
| 505 | #define CFIG_URUN_RETRY BIT_1 OR BIT_2
|
|---|
| 506 |
|
|---|
| 507 | //- Byte 8 (Default Value = 1. Enable MII mode.)
|
|---|
| 508 | #define CFIG_503_MII BIT_0
|
|---|
| 509 |
|
|---|
| 510 | //- Byte 9 (Default Value = 0, ALWAYS)
|
|---|
| 511 |
|
|---|
| 512 | //- Byte 10 (Default Value = 2Eh)
|
|---|
| 513 | #define CFIG_NSAI BIT_3
|
|---|
| 514 | #define CFIG_PREAMBLE_LENGTH BIT_5 ;- Bit 5-4 = 1-0
|
|---|
| 515 | #define CFIG_NO_LOOPBACK 0
|
|---|
| 516 | #define CFIG_INTERNAL_LOOPBACK BIT_6
|
|---|
| 517 | #define CFIG_EXT_LOOPBACK BIT_7
|
|---|
| 518 | #define CFIG_EXT_PIN_LOOPBACK BIT_6 OR BIT_7
|
|---|
| 519 |
|
|---|
| 520 | //- Byte 11 (Default Value = 0)
|
|---|
| 521 | #define CFIG_LINEAR_PRIORITY 0
|
|---|
| 522 |
|
|---|
| 523 | //- Byte 12 (Default Value = 60h)
|
|---|
| 524 | #define CFIG_LPRIORITY_MODE 0
|
|---|
| 525 | #define CFIG_IFS 6 ;- 6 * 16 = 96
|
|---|
| 526 |
|
|---|
| 527 | //- Byte 13 (Default Value = 0, ALWAYS)
|
|---|
| 528 |
|
|---|
| 529 | //- Byte 14 (Default Value = 0F2h, ALWAYS)
|
|---|
| 530 |
|
|---|
| 531 | //- Byte 15 (Default Value = E8h)
|
|---|
| 532 | #define CFIG_PROMISCUOUS_MODE BIT_0
|
|---|
| 533 | #define CFIG_BROADCAST_DISABLE BIT_1
|
|---|
| 534 | #define CFIG_CRS_CDT BIT_7
|
|---|
| 535 |
|
|---|
| 536 | //- Byte 16 (Default Value = 0, ALWAYS)
|
|---|
| 537 |
|
|---|
| 538 | //- Byte 17 (Default Value = 40h, ALWAYS)
|
|---|
| 539 |
|
|---|
| 540 | //- Byte 18 (Default Value = F2h)
|
|---|
| 541 | #define CFIG_STRIPPING BIT_0
|
|---|
| 542 | #define CFIG_PADDING BIT_1
|
|---|
| 543 | #define CFIG_RX_CRC_TRANSFER BIT_2
|
|---|
| 544 |
|
|---|
| 545 | //- Byte 19 (Default Value = 80h)
|
|---|
| 546 | #define CFIG_FORCE_FDX BIT_6
|
|---|
| 547 | #define CFIG_FDX_PIN_ENABLE BIT_7
|
|---|
| 548 |
|
|---|
| 549 | //- Byte 20 (Default Value = 3Fh)
|
|---|
| 550 | #define CFIG_MULTI_IA BIT_6
|
|---|
| 551 |
|
|---|
| 552 | //- Byte 21 (Default Value = 05)
|
|---|
| 553 | #define CFIG_MC_ALL BIT_3
|
|---|
| 554 |
|
|---|
| 555 | /*-----------------------------------------------------------------------*/
|
|---|
| 556 | #define D102_REVID 0x0b
|
|---|
| 557 |
|
|---|
| 558 | #define HALF_DUPLEX 1
|
|---|
| 559 | #define FULL_DUPLEX 2
|
|---|
| 560 |
|
|---|
| 561 | typedef struct s_data_instance {
|
|---|
| 562 |
|
|---|
| 563 | UINT16 State; // stopped, started or initialized
|
|---|
| 564 | UINT16 Bus;
|
|---|
| 565 | UINT8 Device;
|
|---|
| 566 | UINT8 Function;
|
|---|
| 567 | UINT16 VendorID;
|
|---|
| 568 | UINT16 DeviceID;
|
|---|
| 569 | UINT16 RevID;
|
|---|
| 570 | UINT16 SubVendorID;
|
|---|
| 571 | UINT16 SubSystemID;
|
|---|
| 572 |
|
|---|
| 573 | UINT8 PermNodeAddress[PXE_MAC_LENGTH];
|
|---|
| 574 | UINT8 CurrentNodeAddress[PXE_MAC_LENGTH];
|
|---|
| 575 | UINT8 BroadcastNodeAddress[PXE_MAC_LENGTH];
|
|---|
| 576 | UINT32 Config[MAX_PCI_CONFIG_LEN];
|
|---|
| 577 | UINT32 NVData[MAX_EEPROM_LEN];
|
|---|
| 578 |
|
|---|
| 579 | UINT32 ioaddr;
|
|---|
| 580 | UINT32 flash_addr;
|
|---|
| 581 |
|
|---|
| 582 | UINT16 LinkSpeed; // actual link speed setting
|
|---|
| 583 | UINT16 LinkSpeedReq; // requested (forced) link speed
|
|---|
| 584 | UINT8 DuplexReq; // requested duplex
|
|---|
| 585 | UINT8 Duplex; // Duplex set
|
|---|
| 586 | UINT8 CableDetect; // 1 to detect and 0 not to detect the cable
|
|---|
| 587 | UINT8 LoopBack;
|
|---|
| 588 |
|
|---|
| 589 | UINT16 TxBufCnt;
|
|---|
| 590 | UINT16 TxBufSize;
|
|---|
| 591 | UINT16 RxBufCnt;
|
|---|
| 592 | UINT16 RxBufSize;
|
|---|
| 593 | UINT32 RxTotals;
|
|---|
| 594 | UINT32 TxTotals;
|
|---|
| 595 |
|
|---|
| 596 | UINT16 int_mask;
|
|---|
| 597 | UINT16 Int_Status;
|
|---|
| 598 | UINT16 PhyRecord[2]; // primary and secondary PHY record registers from eeprom
|
|---|
| 599 | UINT8 PhyAddress;
|
|---|
| 600 | UINT8 int_num;
|
|---|
| 601 | UINT16 NVData_Len;
|
|---|
| 602 | UINT32 MemoryLength;
|
|---|
| 603 |
|
|---|
| 604 | RxFD *rx_ring; // array of rx buffers
|
|---|
| 605 | TxCB *tx_ring; // array of tx buffers
|
|---|
| 606 | struct speedo_stats *statistics;
|
|---|
| 607 | TxCB *FreeTxHeadPtr;
|
|---|
| 608 | TxCB *FreeTxTailPtr;
|
|---|
| 609 | RxFD *RFDTailPtr;
|
|---|
| 610 |
|
|---|
| 611 | UINT64 rx_phy_addr; // physical addresses
|
|---|
| 612 | UINT64 tx_phy_addr;
|
|---|
| 613 | UINT64 stat_phy_addr;
|
|---|
| 614 | UINT64 MemoryPtr;
|
|---|
| 615 | UINT64 Mapped_MemoryPtr;
|
|---|
| 616 |
|
|---|
| 617 | UINT64 xmit_done[TX_BUFFER_COUNT << 1]; // circular buffer
|
|---|
| 618 | UINT16 xmit_done_head; // index into the xmit_done array
|
|---|
| 619 | UINT16 xmit_done_tail; // where are we filling now (index into xmit_done)
|
|---|
| 620 | UINT16 cur_rx_ind; // current RX Q head index
|
|---|
| 621 | UINT16 FreeCBCount;
|
|---|
| 622 |
|
|---|
| 623 | BOOLEAN in_interrupt;
|
|---|
| 624 | BOOLEAN in_transmit;
|
|---|
| 625 | BOOLEAN Receive_Started;
|
|---|
| 626 | UINT8 Rx_Filter;
|
|---|
| 627 | UINT8 VersionFlag; // UNDI30 or UNDI31??
|
|---|
| 628 | UINT8 rsvd[3];
|
|---|
| 629 |
|
|---|
| 630 | struct mc{
|
|---|
| 631 | UINT16 reserved [3]; // padding for this structure to make it 8 byte aligned
|
|---|
| 632 | UINT16 list_len;
|
|---|
| 633 | UINT8 mc_list[MAX_MCAST_ADDRESS_CNT][PXE_MAC_LENGTH]; // 8*32 is the size
|
|---|
| 634 | } mcast_list;
|
|---|
| 635 |
|
|---|
| 636 | UINT64 Unique_ID;
|
|---|
| 637 |
|
|---|
| 638 | EFI_PCI_IO_PROTOCOL *Io_Function;
|
|---|
| 639 | //
|
|---|
| 640 | // Original PCI attributes
|
|---|
| 641 | //
|
|---|
| 642 | UINT64 OriginalPciAttributes;
|
|---|
| 643 |
|
|---|
| 644 | VOID (*Delay_30)(UINTN); // call back routine
|
|---|
| 645 | VOID (*Virt2Phys_30)(UINT64 virtual_addr, UINT64 physical_ptr); // call back routine
|
|---|
| 646 | VOID (*Block_30)(UINT32 enable); // call back routine
|
|---|
| 647 | VOID (*Mem_Io_30)(UINT8 read_write, UINT8 len, UINT64 port, UINT64 buf_addr);
|
|---|
| 648 | VOID (*Delay)(UINT64, UINTN); // call back routine
|
|---|
| 649 | VOID (*Virt2Phys)(UINT64 unq_id, UINT64 virtual_addr, UINT64 physical_ptr); // call back routine
|
|---|
| 650 | VOID (*Block)(UINT64 unq_id, UINT32 enable); // call back routine
|
|---|
| 651 | VOID (*Mem_Io)(UINT64 unq_id, UINT8 read_write, UINT8 len, UINT64 port,
|
|---|
| 652 | UINT64 buf_addr);
|
|---|
| 653 | VOID (*Map_Mem)(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
|
|---|
| 654 | UINT32 Direction, UINT64 mapped_addr);
|
|---|
| 655 | VOID (*UnMap_Mem)(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
|
|---|
| 656 | UINT32 Direction, UINT64 mapped_addr);
|
|---|
| 657 | VOID (*Sync_Mem)(UINT64 unq_id, UINT64 virtual_addr,
|
|---|
| 658 | UINT32 size, UINT32 Direction, UINT64 mapped_addr);
|
|---|
| 659 | } NIC_DATA_INSTANCE;
|
|---|
| 660 |
|
|---|
| 661 | #pragma pack(1)
|
|---|
| 662 | struct MC_CB_STRUCT{
|
|---|
| 663 | UINT16 count;
|
|---|
| 664 | UINT8 m_list[MAX_MCAST_ADDRESS_CNT][ETHER_MAC_ADDR_LEN];
|
|---|
| 665 | };
|
|---|
| 666 | #pragma pack()
|
|---|
| 667 |
|
|---|
| 668 | #define FOUR_GIGABYTE (UINT64)0x100000000ULL
|
|---|
| 669 |
|
|---|
| 670 | #endif
|
|---|
| 671 |
|
|---|
