VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/MsixCommon.cpp@ 71768

Last change on this file since 71768 was 71768, checked in by vboxsync, 7 years ago

Msi: Some R3 prefixes and some clenaup.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 11.0 KB
Line 
1/* $Id: MsixCommon.cpp 71768 2018-04-09 14:10:52Z vboxsync $ */
2/** @file
3 * MSI-X support routines
4 */
5
6/*
7 * Copyright (C) 2010-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19#define LOG_GROUP LOG_GROUP_DEV_PCI
20#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
21#include <VBox/pci.h>
22#include <VBox/msi.h>
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/log.h>
25#include <VBox/vmm/mm.h>
26
27#include <iprt/assert.h>
28
29#include "MsiCommon.h"
30#include "PciInline.h"
31
32typedef struct
33{
34 uint32_t u32MsgAddressLo;
35 uint32_t u32MsgAddressHi;
36 uint32_t u32MsgData;
37 uint32_t u32VectorControl;
38} MsixTableRecord;
39AssertCompileSize(MsixTableRecord, VBOX_MSIX_ENTRY_SIZE);
40
41
42/** @todo use accessors so that raw PCI devices work correctly with MSI-X. */
43DECLINLINE(uint16_t) msixGetMessageControl(PPDMPCIDEV pDev)
44{
45 return PCIDevGetWord(pDev, pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL);
46}
47
48DECLINLINE(bool) msixIsEnabled(PPDMPCIDEV pDev)
49{
50 return (msixGetMessageControl(pDev) & VBOX_PCI_MSIX_FLAGS_ENABLE) != 0;
51}
52
53DECLINLINE(bool) msixIsMasked(PPDMPCIDEV pDev)
54{
55 return (msixGetMessageControl(pDev) & VBOX_PCI_MSIX_FLAGS_FUNCMASK) != 0;
56}
57
58DECLINLINE(uint16_t) msixTableSize(PPDMPCIDEV pDev)
59{
60 return (msixGetMessageControl(pDev) & 0x3ff) + 1;
61}
62
63DECLINLINE(uint8_t*) msixGetPageOffset(PPDMPCIDEV pDev, uint32_t off)
64{
65 return (uint8_t*)pDev->Int.s.CTX_SUFF(pMsixPage) + off;
66}
67
68DECLINLINE(MsixTableRecord*) msixGetVectorRecord(PPDMPCIDEV pDev, uint32_t iVector)
69{
70 return (MsixTableRecord*)msixGetPageOffset(pDev, iVector * VBOX_MSIX_ENTRY_SIZE);
71}
72
73DECLINLINE(RTGCPHYS) msixGetMsiAddress(PPDMPCIDEV pDev, uint32_t iVector)
74{
75 MsixTableRecord* pRec = msixGetVectorRecord(pDev, iVector);
76 return RT_MAKE_U64(pRec->u32MsgAddressLo & ~UINT32_C(0x3), pRec->u32MsgAddressHi);
77}
78
79DECLINLINE(uint32_t) msixGetMsiData(PPDMPCIDEV pDev, uint32_t iVector)
80{
81 return msixGetVectorRecord(pDev, iVector)->u32MsgData;
82}
83
84DECLINLINE(uint32_t) msixIsVectorMasked(PPDMPCIDEV pDev, uint32_t iVector)
85{
86 return (msixGetVectorRecord(pDev, iVector)->u32VectorControl & 0x1) != 0;
87}
88
89DECLINLINE(uint8_t*) msixPendingByte(PPDMPCIDEV pDev, uint32_t iVector)
90{
91 return msixGetPageOffset(pDev, pDev->Int.s.offMsixPba + iVector / 8);
92}
93
94DECLINLINE(void) msixSetPending(PPDMPCIDEV pDev, uint32_t iVector)
95{
96 *msixPendingByte(pDev, iVector) |= (1 << (iVector & 0x7));
97}
98
99DECLINLINE(void) msixClearPending(PPDMPCIDEV pDev, uint32_t iVector)
100{
101 *msixPendingByte(pDev, iVector) &= ~(1 << (iVector & 0x7));
102}
103
104DECLINLINE(bool) msixIsPending(PPDMPCIDEV pDev, uint32_t iVector)
105{
106 return (*msixPendingByte(pDev, iVector) & (1 << (iVector & 0x7))) != 0;
107}
108
109static void msixCheckPendingVector(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, uint32_t iVector)
110{
111 if (msixIsPending(pDev, iVector) && !msixIsVectorMasked(pDev, iVector))
112 MsixNotify(pDevIns, pPciHlp, pDev, iVector, 1 /* iLevel */, 0 /*uTagSrc*/);
113}
114
115#ifdef IN_RING3
116
117PDMBOTHCBDECL(int) msixR3MMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
118{
119 LogFlowFunc(("\n"));
120
121 uint32_t off = (uint32_t)(GCPhysAddr & 0xffff);
122 PPDMPCIDEV pPciDev = (PPDMPCIDEV)pvUser;
123
124 /// @todo qword accesses?
125 RT_NOREF(pDevIns);
126 AssertMsgReturn(cb == 4,
127 ("MSI-X must be accessed with 4-byte reads"),
128 VERR_INTERNAL_ERROR);
129 AssertMsgReturn(off < pPciDev->Int.s.cbMsixRegion,
130 ("Out of bounds access for the MSI-X region\n"),
131 VINF_IOM_MMIO_UNUSED_FF);
132
133 *(uint32_t *)pv = *(uint32_t *)msixGetPageOffset(pPciDev, off);
134 return VINF_SUCCESS;
135}
136
137PDMBOTHCBDECL(int) msixR3MMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
138{
139 LogFlowFunc(("\n"));
140
141 PPDMPCIDEV pPciDev = (PPDMPCIDEV)pvUser;
142 uint32_t off = (uint32_t)(GCPhysAddr & 0xffff);
143
144 /// @todo qword accesses?
145 AssertMsgReturn(cb == 4,
146 ("MSI-X must be accessed with 4-byte reads"),
147 VERR_INTERNAL_ERROR);
148 AssertMsgReturn(off < pPciDev->Int.s.offMsixPba,
149 ("Trying to write to PBA\n"),
150 VINF_IOM_MMIO_UNUSED_FF);
151
152 *(uint32_t *)msixGetPageOffset(pPciDev, off) = *(uint32_t *)pv;
153
154 msixCheckPendingVector(pDevIns, (PCPDMPCIHLP)pPciDev->Int.s.pPciBusPtrR3, pPciDev, off / VBOX_MSIX_ENTRY_SIZE);
155 return VINF_SUCCESS;
156}
157
158/**
159 * @callback_method_impl{FNPCIIOREGIONMAP}
160 */
161static DECLCALLBACK(int) msixR3Map(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
162 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
163{
164 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
165 NOREF(iRegion); NOREF(enmType);
166
167 int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, pPciDev,
168 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
169 msixR3MMIOWrite, msixR3MMIORead, "MSI-X tables");
170
171 if (RT_FAILURE(rc))
172 return rc;
173
174 return VINF_SUCCESS;
175}
176
177int MsixR3Init(PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, PPDMMSIREG pMsiReg)
178{
179 if (pMsiReg->cMsixVectors == 0)
180 return VINF_SUCCESS;
181
182 /* We cannot init MSI-X on raw devices yet. */
183 Assert(!pciDevIsPassthrough(pDev));
184
185 uint16_t cVectors = pMsiReg->cMsixVectors;
186 uint8_t iCapOffset = pMsiReg->iMsixCapOffset;
187 uint8_t iNextOffset = pMsiReg->iMsixNextOffset;
188 uint8_t iBar = pMsiReg->iMsixBar;
189
190 AssertMsgReturn(cVectors <= VBOX_MSIX_MAX_ENTRIES,
191 ("Too many MSI-X vectors: %d\n", cVectors),
192 VERR_TOO_MUCH_DATA);
193 AssertMsgReturn(iBar <= 5,
194 ("Using wrong BAR for MSI-X: %d\n", iBar),
195 VERR_INVALID_PARAMETER);
196
197 Assert(iCapOffset != 0 && iCapOffset < 0xff && iNextOffset < 0xff);
198
199 int rc = VINF_SUCCESS;
200 uint16_t cbPba = cVectors / 8;
201 if (cVectors % 8)
202 cbPba++;
203 uint16_t cbMsixRegion = RT_ALIGN_T(cVectors * sizeof(MsixTableRecord) + cbPba, _4K, uint16_t);
204
205 /* If device is passthrough, BAR is registered using common mechanism. */
206 if (!pciDevIsPassthrough(pDev))
207 {
208 rc = PDMDevHlpPCIIORegionRegister(pDev->Int.s.CTX_SUFF(pDevIns), iBar, cbMsixRegion, PCI_ADDRESS_SPACE_MEM, msixR3Map);
209 if (RT_FAILURE (rc))
210 return rc;
211 }
212
213 uint16_t offTable = 0;
214 uint16_t offPBA = cVectors * sizeof(MsixTableRecord);
215
216 pDev->Int.s.u8MsixCapOffset = iCapOffset;
217 pDev->Int.s.u8MsixCapSize = VBOX_MSIX_CAP_SIZE;
218 pDev->Int.s.cbMsixRegion = cbMsixRegion;
219 pDev->Int.s.offMsixPba = offPBA;
220 PVM pVM = PDMDevHlpGetVM(pDev->Int.s.CTX_SUFF(pDevIns));
221
222 pDev->Int.s.pMsixPageR3 = NULL;
223
224 rc = MMHyperAlloc(pVM, cbMsixRegion, 1, MM_TAG_PDM_DEVICE_USER, (void **)&pDev->Int.s.pMsixPageR3);
225 if (RT_FAILURE(rc) || (pDev->Int.s.pMsixPageR3 == NULL))
226 return VERR_NO_VM_MEMORY;
227 RT_BZERO(pDev->Int.s.pMsixPageR3, cbMsixRegion);
228 pDev->Int.s.pMsixPageR0 = MMHyperR3ToR0(pVM, pDev->Int.s.pMsixPageR3);
229 pDev->Int.s.pMsixPageRC = MMHyperR3ToRC(pVM, pDev->Int.s.pMsixPageR3);
230
231 /* R3 PCI helper */
232 pDev->Int.s.pPciBusPtrR3 = pPciHlp;
233
234 PCIDevSetByte(pDev, iCapOffset + 0, VBOX_PCI_CAP_ID_MSIX);
235 PCIDevSetByte(pDev, iCapOffset + 1, iNextOffset); /* next */
236 PCIDevSetWord(pDev, iCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL, cVectors - 1);
237
238 PCIDevSetDWord(pDev, iCapOffset + VBOX_MSIX_TABLE_BIROFFSET, offTable | iBar);
239 PCIDevSetDWord(pDev, iCapOffset + VBOX_MSIX_PBA_BIROFFSET, offPBA | iBar);
240
241 pciDevSetMsixCapable(pDev);
242
243 return VINF_SUCCESS;
244}
245#endif
246
247bool MsixIsEnabled(PPDMPCIDEV pDev)
248{
249 return pciDevIsMsixCapable(pDev) && msixIsEnabled(pDev);
250}
251
252void MsixNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, int iVector, int iLevel, uint32_t uTagSrc)
253{
254 AssertMsg(msixIsEnabled(pDev), ("Must be enabled to use that"));
255
256 Assert(pPciHlp->pfnIoApicSendMsi != NULL);
257
258 /* We only trigger MSI-X on level up */
259 if ((iLevel & PDM_IRQ_LEVEL_HIGH) == 0)
260 {
261 return;
262 }
263
264 // if this vector is somehow disabled
265 if (msixIsMasked(pDev) || msixIsVectorMasked(pDev, iVector))
266 {
267 // mark pending bit
268 msixSetPending(pDev, iVector);
269 return;
270 }
271
272 // clear pending bit
273 msixClearPending(pDev, iVector);
274
275 RTGCPHYS GCAddr = msixGetMsiAddress(pDev, iVector);
276 uint32_t u32Value = msixGetMsiData(pDev, iVector);
277
278 pPciHlp->pfnIoApicSendMsi(pDevIns, GCAddr, u32Value, uTagSrc);
279}
280
281DECLINLINE(bool) msixBitJustCleared(uint32_t uOldValue,
282 uint32_t uNewValue,
283 uint32_t uMask)
284{
285 return (!!(uOldValue & uMask) && !(uNewValue & uMask));
286}
287
288static void msixCheckPendingVectors(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev)
289{
290 for (uint32_t i = 0; i < msixTableSize(pDev); i++)
291 msixCheckPendingVector(pDevIns, pPciHlp, pDev, i);
292}
293
294
295void MsixR3PciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, uint32_t u32Address, uint32_t val, unsigned len)
296{
297 int32_t iOff = u32Address - pDev->Int.s.u8MsixCapOffset;
298 Assert(iOff >= 0 && (pciDevIsMsixCapable(pDev) && iOff < pDev->Int.s.u8MsixCapSize));
299
300 Log2(("MsixR3PciConfigWrite: %d <- %x (%d)\n", iOff, val, len));
301
302 uint32_t uAddr = u32Address;
303 uint8_t u8NewVal;
304 bool fJustEnabled = false;
305
306 for (uint32_t i = 0; i < len; i++)
307 {
308 uint32_t reg = i + iOff;
309 uint8_t u8Val = (uint8_t)val;
310 switch (reg)
311 {
312 case 0: /* Capability ID, ro */
313 case 1: /* Next pointer, ro */
314 break;
315 case VBOX_MSIX_CAP_MESSAGE_CONTROL:
316 /* don't change read-only bits: 0-7 */
317 break;
318 case VBOX_MSIX_CAP_MESSAGE_CONTROL + 1:
319 {
320 /* don't change read-only bits 8-13 */
321 u8NewVal = (u8Val & UINT8_C(~0x3f)) | (pDev->abConfig[uAddr] & UINT8_C(0x3f));
322 /* If just enabled globally - check pending vectors */
323 fJustEnabled |= msixBitJustCleared(pDev->abConfig[uAddr], u8NewVal, VBOX_PCI_MSIX_FLAGS_ENABLE >> 8);
324 fJustEnabled |= msixBitJustCleared(pDev->abConfig[uAddr], u8NewVal, VBOX_PCI_MSIX_FLAGS_FUNCMASK >> 8);
325 pDev->abConfig[uAddr] = u8NewVal;
326 break;
327 }
328 default:
329 /* other fields read-only too */
330 break;
331 }
332 uAddr++;
333 val >>= 8;
334 }
335
336 if (fJustEnabled)
337 msixCheckPendingVectors(pDevIns, pPciHlp, pDev);
338}
339
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