VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/MsiCommon.cpp@ 43831

Last change on this file since 43831 was 40907, checked in by vboxsync, 13 years ago

Working on tracking IRQs for tracing and logging purposes.
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File size: 10.0 KB
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1/* $Id: MsiCommon.cpp 40907 2012-04-13 20:50:14Z vboxsync $ */
2/** @file
3 * MSI support routines
4 */
5
6/*
7 * Copyright (C) 2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17#define LOG_GROUP LOG_GROUP_DEV_PCI
18/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
19#define PCI_INCLUDE_PRIVATE
20#include <VBox/pci.h>
21#include <VBox/msi.h>
22#include <VBox/vmm/pdmdev.h>
23#include <VBox/log.h>
24
25#include "MsiCommon.h"
26
27/** @todo: use accessors so that raw PCI devices work correctly with MSI. */
28DECLINLINE(uint16_t) msiGetMessageControl(PPCIDEVICE pDev)
29{
30 return PCIDevGetWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL);
31}
32
33DECLINLINE(bool) msiIs64Bit(PPCIDEVICE pDev)
34{
35 return pciDevIsMsi64Capable(pDev);
36}
37
38DECLINLINE(uint32_t*) msiGetMaskBits(PPCIDEVICE pDev)
39{
40 uint8_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_MASK_BITS_64 : VBOX_MSI_CAP_MASK_BITS_32;
41 iOff += pDev->Int.s.u8MsiCapOffset;
42 return (uint32_t*)(pDev->config + iOff);
43}
44
45DECLINLINE(uint32_t*) msiGetPendingBits(PPCIDEVICE pDev)
46{
47 uint8_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_PENDING_BITS_64 : VBOX_MSI_CAP_PENDING_BITS_32;
48 iOff += pDev->Int.s.u8MsiCapOffset;
49 return (uint32_t*)(pDev->config + iOff);
50}
51
52DECLINLINE(bool) msiIsEnabled(PPCIDEVICE pDev)
53{
54 return (msiGetMessageControl(pDev) & VBOX_PCI_MSI_FLAGS_ENABLE) != 0;
55}
56
57DECLINLINE(uint8_t) msiGetMme(PPCIDEVICE pDev)
58{
59 return (msiGetMessageControl(pDev) & VBOX_PCI_MSI_FLAGS_QSIZE) >> 4;
60}
61
62DECLINLINE(RTGCPHYS) msiGetMsiAddress(PPCIDEVICE pDev)
63{
64 if (msiIs64Bit(pDev))
65 {
66 uint32_t lo = PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_LO);
67 uint32_t hi = PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_HI);
68 return RT_MAKE_U64(lo, hi);
69 }
70 else
71 {
72 return PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_32);
73 }
74}
75
76DECLINLINE(uint32_t) msiGetMsiData(PPCIDEVICE pDev, int32_t iVector)
77{
78 int16_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_MESSAGE_DATA_64 : VBOX_MSI_CAP_MESSAGE_DATA_32;
79 uint16_t lo = PCIDevGetWord(pDev, pDev->Int.s.u8MsiCapOffset + iOff);
80
81 // vector encoding into lower bits of message data
82 uint8_t bits = msiGetMme(pDev);
83 uint16_t uMask = ((1 << bits) - 1);
84 lo &= ~uMask;
85 lo |= iVector & uMask;
86
87 return RT_MAKE_U32(lo, 0);
88}
89
90DECLINLINE(bool) msiBitJustCleared(uint32_t uOldValue,
91 uint32_t uNewValue,
92 uint32_t uMask)
93{
94 return (!!(uOldValue & uMask) && !(uNewValue & uMask));
95}
96
97DECLINLINE(bool) msiBitJustSet(uint32_t uOldValue,
98 uint32_t uNewValue,
99 uint32_t uMask)
100{
101 return (!(uOldValue & uMask) && !!(uNewValue & uMask));
102}
103
104#ifdef IN_RING3
105void MsiPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev,
106 uint32_t u32Address, uint32_t val, unsigned len)
107{
108 int32_t iOff = u32Address - pDev->Int.s.u8MsiCapOffset;
109 Assert(iOff >= 0 && (pciDevIsMsiCapable(pDev) && iOff < pDev->Int.s.u8MsiCapSize));
110
111 Log2(("MsiPciConfigWrite: %d <- %x (%d)\n", iOff, val, len));
112
113 uint32_t uAddr = u32Address;
114 bool f64Bit = msiIs64Bit(pDev);
115
116 for (uint32_t i = 0; i < len; i++)
117 {
118 uint32_t reg = i + iOff;
119 uint8_t u8Val = (uint8_t)val;
120 switch (reg)
121 {
122 case 0: /* Capability ID, ro */
123 case 1: /* Next pointer, ro */
124 break;
125 case VBOX_MSI_CAP_MESSAGE_CONTROL:
126 /* don't change read-only bits: 1-3,7 */
127 u8Val &= UINT8_C(~0x8e);
128 pDev->config[uAddr] = u8Val | (pDev->config[uAddr] & UINT8_C(0x8e));
129 break;
130 case VBOX_MSI_CAP_MESSAGE_CONTROL + 1:
131 /* don't change read-only bit 8, and reserved 9-15 */
132 break;
133 default:
134 if (pDev->config[uAddr] != u8Val)
135 {
136 int32_t maskUpdated = -1;
137
138 /* If we're enabling masked vector, and have pending messages
139 for this vector, we have to send this message now */
140 if ( !f64Bit
141 && (reg >= VBOX_MSI_CAP_MASK_BITS_32)
142 && (reg < VBOX_MSI_CAP_MASK_BITS_32 + 4)
143 )
144 {
145 maskUpdated = reg - VBOX_MSI_CAP_MASK_BITS_32;
146 }
147 if ( f64Bit
148 && (reg >= VBOX_MSI_CAP_MASK_BITS_64)
149 && (reg < VBOX_MSI_CAP_MASK_BITS_64 + 4)
150 )
151 {
152 maskUpdated = reg - VBOX_MSI_CAP_MASK_BITS_64;
153 }
154
155 if (maskUpdated != -1 && msiIsEnabled(pDev))
156 {
157 uint32_t* puPending = msiGetPendingBits(pDev);
158 for (int iBitNum = 0; iBitNum < 8; iBitNum++)
159 {
160 int32_t iBit = 1 << iBitNum;
161 uint32_t uVector = maskUpdated*8 + iBitNum;
162
163 if (msiBitJustCleared(pDev->config[uAddr], u8Val, iBit))
164 {
165 Log(("msi: mask updated bit %d@%x (%d)\n", iBitNum, uAddr, maskUpdated));
166
167 /* To ensure that we're no longer masked */
168 pDev->config[uAddr] &= ~iBit;
169 if ((*puPending & (1 << uVector)) != 0)
170 {
171 Log(("msi: notify earlier masked pending vector: %d\n", uVector));
172 MsiNotify(pDevIns, pPciHlp, pDev, uVector, PDM_IRQ_LEVEL_HIGH, 0 /*uTagSrc*/);
173 }
174 }
175 if (msiBitJustSet(pDev->config[uAddr], u8Val, iBit))
176 {
177 Log(("msi: mask vector: %d\n", uVector));
178 }
179 }
180 }
181
182 pDev->config[uAddr] = u8Val;
183 }
184 }
185 uAddr++;
186 val >>= 8;
187 }
188}
189
190uint32_t MsiPciConfigRead (PPDMDEVINS pDevIns, PPCIDEVICE pDev, uint32_t u32Address, unsigned len)
191{
192 int32_t iOff = u32Address - pDev->Int.s.u8MsiCapOffset;
193
194 Assert(iOff >= 0 && (pciDevIsMsiCapable(pDev) && iOff < pDev->Int.s.u8MsiCapSize));
195 uint32_t rv = 0;
196
197 switch (len)
198 {
199 case 1:
200 rv = PCIDevGetByte(pDev, u32Address);
201 break;
202 case 2:
203 rv = PCIDevGetWord(pDev, u32Address);
204 break;
205 case 4:
206 rv = PCIDevGetDWord(pDev, u32Address);
207 break;
208 default:
209 Assert(false);
210 }
211
212 Log2(("MsiPciConfigRead: %d (%d) -> %x\n", iOff, len, rv));
213
214 return rv;
215}
216
217int MsiInit(PPCIDEVICE pDev, PPDMMSIREG pMsiReg)
218{
219 if (pMsiReg->cMsiVectors == 0)
220 return VINF_SUCCESS;
221
222 /* We cannot init MSI on raw devices yet. */
223 Assert(!pciDevIsPassthrough(pDev));
224
225 uint16_t cVectors = pMsiReg->cMsiVectors;
226 uint8_t iCapOffset = pMsiReg->iMsiCapOffset;
227 uint8_t iNextOffset = pMsiReg->iMsiNextOffset;
228 bool f64bit = pMsiReg->fMsi64bit;
229 uint16_t iFlags = 0;
230 int iMmc;
231
232 /* Compute multiple-message capable bitfield */
233 for (iMmc = 0; iMmc < 6; iMmc++)
234 {
235 if ((1 << iMmc) >= cVectors)
236 break;
237 }
238
239 if ((cVectors > VBOX_MSI_MAX_ENTRIES) || (1 << iMmc) < cVectors)
240 return VERR_TOO_MUCH_DATA;
241
242 Assert(iCapOffset != 0 && iCapOffset < 0xff && iNextOffset < 0xff);
243
244 /* We always support per-vector masking */
245 iFlags |= VBOX_PCI_MSI_FLAGS_MASKBIT | iMmc;
246 if (f64bit)
247 iFlags |= VBOX_PCI_MSI_FLAGS_64BIT;
248 /* How many vectors we're capable of */
249 iFlags |= iMmc;
250
251 pDev->Int.s.u8MsiCapOffset = iCapOffset;
252 pDev->Int.s.u8MsiCapSize = f64bit ? VBOX_MSI_CAP_SIZE_64 : VBOX_MSI_CAP_SIZE_32;
253
254 PCIDevSetByte(pDev, iCapOffset + 0, VBOX_PCI_CAP_ID_MSI);
255 PCIDevSetByte(pDev, iCapOffset + 1, iNextOffset); /* next */
256 PCIDevSetWord(pDev, iCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL, iFlags);
257
258 *msiGetMaskBits(pDev) = 0;
259 *msiGetPendingBits(pDev) = 0;
260
261 pciDevSetMsiCapable(pDev);
262
263 return VINF_SUCCESS;
264}
265
266#endif /* IN_RING3 */
267
268
269bool MsiIsEnabled(PPCIDEVICE pDev)
270{
271 return pciDevIsMsiCapable(pDev) && msiIsEnabled(pDev);
272}
273
274void MsiNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, int iVector, int iLevel, uint32_t uTagSrc)
275{
276 AssertMsg(msiIsEnabled(pDev), ("Must be enabled to use that"));
277
278 uint32_t uMask = *msiGetMaskBits(pDev);
279 uint32_t* puPending = msiGetPendingBits(pDev);
280
281 LogFlow(("MsiNotify: %d pending=%x mask=%x\n", iVector, *puPending, uMask));
282
283 /* We only trigger MSI on level up */
284 if ((iLevel & PDM_IRQ_LEVEL_HIGH) == 0)
285 {
286 /* @todo: maybe clear pending interrupts on level down? */
287#if 0
288 *puPending &= ~(1<<iVector);
289 LogFlow(("msi: clear pending %d, now %x\n", iVector, *puPending));
290#endif
291 return;
292 }
293
294 if ((uMask & (1<<iVector)) != 0)
295 {
296 *puPending |= (1<<iVector);
297 LogFlow(("msi: %d is masked, mark pending, now %x\n", iVector, *puPending));
298 return;
299 }
300
301 RTGCPHYS GCAddr = msiGetMsiAddress(pDev);
302 uint32_t u32Value = msiGetMsiData(pDev, iVector);
303
304 *puPending &= ~(1<<iVector);
305
306 Assert(pPciHlp->pfnIoApicSendMsi != NULL);
307 pPciHlp->pfnIoApicSendMsi(pDevIns, GCAddr, u32Value, uTagSrc);
308}
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