VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/MsiCommon.cpp@ 36562

Last change on this file since 36562 was 36562, checked in by vboxsync, 14 years ago

PCI: better logging, try to play nice with MSI
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 9.7 KB
Line 
1/* $Id: MsiCommon.cpp 36562 2011-04-05 13:56:34Z vboxsync $ */
2/** @file
3 * MSI support routines
4 */
5
6/*
7 * Copyright (C) 2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17#define LOG_GROUP LOG_GROUP_DEV_PCI
18/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
19#define PCI_INCLUDE_PRIVATE
20#include <VBox/pci.h>
21#include <VBox/msi.h>
22#include <VBox/vmm/pdmdev.h>
23#include <VBox/log.h>
24
25#include "MsiCommon.h"
26
27DECLINLINE(uint16_t) msiGetMessageControl(PPCIDEVICE pDev)
28{
29 return PCIDevGetWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL);
30}
31
32DECLINLINE(bool) msiIs64Bit(PPCIDEVICE pDev)
33{
34 return pciDevIsMsi64Capable(pDev);
35}
36
37DECLINLINE(uint32_t*) msiGetMaskBits(PPCIDEVICE pDev)
38{
39 uint8_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_MASK_BITS_64 : VBOX_MSI_CAP_MASK_BITS_32;
40 iOff += pDev->Int.s.u8MsiCapOffset;
41 return (uint32_t*)(pDev->config + iOff);
42}
43
44DECLINLINE(uint32_t*) msiGetPendingBits(PPCIDEVICE pDev)
45{
46 uint8_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_PENDING_BITS_64 : VBOX_MSI_CAP_PENDING_BITS_32;
47 iOff += pDev->Int.s.u8MsiCapOffset;
48 return (uint32_t*)(pDev->config + iOff);
49}
50
51DECLINLINE(bool) msiIsEnabled(PPCIDEVICE pDev)
52{
53 return (msiGetMessageControl(pDev) & VBOX_PCI_MSI_FLAGS_ENABLE) != 0;
54}
55
56DECLINLINE(uint8_t) msiGetMme(PPCIDEVICE pDev)
57{
58 return (msiGetMessageControl(pDev) & VBOX_PCI_MSI_FLAGS_QSIZE) >> 4;
59}
60
61DECLINLINE(RTGCPHYS) msiGetMsiAddress(PPCIDEVICE pDev)
62{
63 if (msiIs64Bit(pDev))
64 {
65 uint32_t lo = PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_LO);
66 uint32_t hi = PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_HI);
67 return RT_MAKE_U64(lo, hi);
68 }
69 else
70 {
71 return PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_32);
72 }
73}
74
75DECLINLINE(uint32_t) msiGetMsiData(PPCIDEVICE pDev, int32_t iVector)
76{
77 int16_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_MESSAGE_DATA_64 : VBOX_MSI_CAP_MESSAGE_DATA_32;
78 uint16_t lo = PCIDevGetWord(pDev, pDev->Int.s.u8MsiCapOffset + iOff);
79
80 // vector encoding into lower bits of message data
81 uint8_t bits = msiGetMme(pDev);
82 uint16_t uMask = ((1 << bits) - 1);
83 lo &= ~uMask;
84 lo |= iVector & uMask;
85
86 return RT_MAKE_U32(lo, 0);
87}
88
89DECLINLINE(bool) msiBitJustCleared(uint32_t uOldValue,
90 uint32_t uNewValue,
91 uint32_t uMask)
92{
93 return (!!(uOldValue & uMask) && !(uNewValue & uMask));
94}
95
96DECLINLINE(bool) msiBitJustSet(uint32_t uOldValue,
97 uint32_t uNewValue,
98 uint32_t uMask)
99{
100 return (!(uOldValue & uMask) && !!(uNewValue & uMask));
101}
102
103
104void MsiPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, uint32_t u32Address, uint32_t val, unsigned len)
105{
106 int32_t iOff = u32Address - pDev->Int.s.u8MsiCapOffset;
107 Assert(iOff >= 0 && (pciDevIsMsiCapable(pDev) && iOff < pDev->Int.s.u8MsiCapSize));
108
109 Log2(("MsiPciConfigWrite: %d <- %x (%d)\n", iOff, val, len));
110
111 uint32_t uAddr = u32Address;
112 bool f64Bit = msiIs64Bit(pDev);
113
114 for (uint32_t i = 0; i < len; i++)
115 {
116 uint32_t reg = i + iOff;
117 uint8_t u8Val = (uint8_t)val;
118 switch (reg)
119 {
120 case 0: /* Capability ID, ro */
121 case 1: /* Next pointer, ro */
122 break;
123 case VBOX_MSI_CAP_MESSAGE_CONTROL:
124 /* don't change read-only bits: 1-3,7 */
125 u8Val &= UINT8_C(~0x8e);
126 pDev->config[uAddr] = u8Val | (pDev->config[uAddr] & UINT8_C(0x8e));
127 break;
128 case VBOX_MSI_CAP_MESSAGE_CONTROL + 1:
129 /* don't change read-only bit 8, and reserved 9-15 */
130 break;
131 default:
132 if (pDev->config[uAddr] != u8Val)
133 {
134 int32_t maskUpdated = -1;
135
136 /* If we're enabling masked vector, and have pending messages
137 for this vector, we have to send this message now */
138 if ( !f64Bit
139 && (reg >= VBOX_MSI_CAP_MASK_BITS_32)
140 && (reg < VBOX_MSI_CAP_MASK_BITS_32 + 4)
141 )
142 {
143 maskUpdated = reg - VBOX_MSI_CAP_MASK_BITS_32;
144 }
145 if ( f64Bit
146 && (reg >= VBOX_MSI_CAP_MASK_BITS_64)
147 && (reg < VBOX_MSI_CAP_MASK_BITS_64 + 4)
148 )
149 {
150 maskUpdated = reg - VBOX_MSI_CAP_MASK_BITS_64;
151 }
152
153 if (maskUpdated != -1 && msiIsEnabled(pDev))
154 {
155 uint32_t* puPending = msiGetPendingBits(pDev);
156 for (int iBitNum = 0; iBitNum < 8; iBitNum++)
157 {
158 int32_t iBit = 1 << iBitNum;
159 uint32_t uVector = maskUpdated*8 + iBitNum;
160
161 if (msiBitJustCleared(pDev->config[uAddr], u8Val, iBit))
162 {
163 Log(("msi: mask updated bit %d@%x (%d)\n", iBitNum, uAddr, maskUpdated));
164
165 /* To ensure that we're no longer masked */
166 pDev->config[uAddr] &= ~iBit;
167 if ((*puPending & (1 << uVector)) != 0)
168 {
169 Log(("msi: notify earlier masked pending vector: %d\n", uVector));
170 MsiNotify(pDevIns, pPciHlp, pDev, uVector, PDM_IRQ_LEVEL_HIGH);
171 }
172 }
173 if (msiBitJustSet(pDev->config[uAddr], u8Val, iBit))
174 {
175 Log(("msi: mask vector: %d\n", uVector));
176 }
177 }
178 }
179
180 pDev->config[uAddr] = u8Val;
181 }
182 }
183 uAddr++;
184 val >>= 8;
185 }
186}
187
188uint32_t MsiPciConfigRead (PPDMDEVINS pDevIns, PPCIDEVICE pDev, uint32_t u32Address, unsigned len)
189{
190 int32_t iOff = u32Address - pDev->Int.s.u8MsiCapOffset;
191
192 Assert(iOff >= 0 && (pciDevIsMsiCapable(pDev) && iOff < pDev->Int.s.u8MsiCapSize));
193 uint32_t rv = 0;
194
195 switch (len)
196 {
197 case 1:
198 rv = PCIDevGetByte(pDev, u32Address);
199 break;
200 case 2:
201 rv = PCIDevGetWord(pDev, u32Address);
202 break;
203 case 4:
204 rv = PCIDevGetDWord(pDev, u32Address);
205 break;
206 default:
207 Assert(false);
208 }
209
210 Log2(("MsiPciConfigRead: %d (%d) -> %x\n", iOff, len, rv));
211
212 return rv;
213}
214
215
216int MsiInit(PPCIDEVICE pDev, PPDMMSIREG pMsiReg)
217{
218 if (pMsiReg->cMsiVectors == 0)
219 return VINF_SUCCESS;
220
221 uint16_t cVectors = pMsiReg->cMsiVectors;
222 uint8_t iCapOffset = pMsiReg->iMsiCapOffset;
223 uint8_t iNextOffset = pMsiReg->iMsiNextOffset;
224 bool f64bit = pMsiReg->fMsi64bit;
225 uint16_t iFlags = 0;
226 int iMmc;
227
228 /* Compute multiple-message capable bitfield */
229 for (iMmc = 0; iMmc < 6; iMmc++)
230 {
231 if ((1 << iMmc) >= cVectors)
232 break;
233 }
234
235 if ((cVectors > VBOX_MSI_MAX_ENTRIES) || (1 << iMmc) < cVectors)
236 return VERR_TOO_MUCH_DATA;
237
238 Assert(iCapOffset != 0 && iCapOffset < 0xff && iNextOffset < 0xff);
239
240 /* We always support per-vector masking */
241 iFlags |= VBOX_PCI_MSI_FLAGS_MASKBIT | iMmc;
242 if (f64bit)
243 iFlags |= VBOX_PCI_MSI_FLAGS_64BIT;
244 /* How many vectors we're capable of */
245 iFlags |= iMmc;
246
247 pDev->Int.s.u8MsiCapOffset = iCapOffset;
248 pDev->Int.s.u8MsiCapSize = f64bit ? VBOX_MSI_CAP_SIZE_64 : VBOX_MSI_CAP_SIZE_32;
249
250 PCIDevSetByte(pDev, iCapOffset + 0, VBOX_PCI_CAP_ID_MSI);
251 PCIDevSetByte(pDev, iCapOffset + 1, iNextOffset); /* next */
252 PCIDevSetWord(pDev, iCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL, iFlags);
253
254 *msiGetMaskBits(pDev) = 0;
255 *msiGetPendingBits(pDev) = 0;
256
257 pciDevSetMsiCapable(pDev);
258
259 return VINF_SUCCESS;
260}
261
262
263bool MsiIsEnabled(PPCIDEVICE pDev)
264{
265 return pciDevIsMsiCapable(pDev) && msiIsEnabled(pDev);
266}
267
268void MsiNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, int iVector, int iLevel)
269{
270 AssertMsg(msiIsEnabled(pDev), ("Must be enabled to use that"));
271
272 uint32_t uMask = *msiGetMaskBits(pDev);
273 uint32_t* puPending = msiGetPendingBits(pDev);
274
275 LogFlow(("MsiNotify: %d pending=%x mask=%x\n", iVector, *puPending, uMask));
276
277 /* We only trigger MSI on level up */
278 if ((iLevel & PDM_IRQ_LEVEL_HIGH) == 0)
279 {
280 /* @todo: maybe clear pending interrupts on level down? */
281#if 0
282 *puPending &= ~(1<<iVector);
283 LogFlow(("msi: clear pending %d, now %x\n", iVector, *puPending));
284#endif
285 return;
286 }
287
288 if ((uMask & (1<<iVector)) != 0)
289 {
290 *puPending |= (1<<iVector);
291 LogFlow(("msi: %d is masked, mark pending, now %x\n", iVector, *puPending));
292 return;
293 }
294
295 RTGCPHYS GCAddr = msiGetMsiAddress(pDev);
296 uint32_t u32Value = msiGetMsiData(pDev, iVector);
297
298 *puPending &= ~(1<<iVector);
299
300 Assert(pPciHlp->pfnIoApicSendMsi != NULL);
301 pPciHlp->pfnIoApicSendMsi(pDevIns, GCAddr, u32Value);
302}
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