| 1 | /* $Id: DevPciInternal.h 96407 2022-08-22 17:43:14Z vboxsync $ */
|
|---|
| 2 | /** @file
|
|---|
| 3 | * DevPCI - Common Internal Header.
|
|---|
| 4 | */
|
|---|
| 5 |
|
|---|
| 6 | /*
|
|---|
| 7 | * Copyright (C) 2010-2022 Oracle and/or its affiliates.
|
|---|
| 8 | *
|
|---|
| 9 | * This file is part of VirtualBox base platform packages, as
|
|---|
| 10 | * available from https://www.virtualbox.org.
|
|---|
| 11 | *
|
|---|
| 12 | * This program is free software; you can redistribute it and/or
|
|---|
| 13 | * modify it under the terms of the GNU General Public License
|
|---|
| 14 | * as published by the Free Software Foundation, in version 3 of the
|
|---|
| 15 | * License.
|
|---|
| 16 | *
|
|---|
| 17 | * This program is distributed in the hope that it will be useful, but
|
|---|
| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
|
|---|
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|---|
| 20 | * General Public License for more details.
|
|---|
| 21 | *
|
|---|
| 22 | * You should have received a copy of the GNU General Public License
|
|---|
| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
|
|---|
| 24 | *
|
|---|
| 25 | * SPDX-License-Identifier: GPL-3.0-only
|
|---|
| 26 | */
|
|---|
| 27 |
|
|---|
| 28 | #ifndef VBOX_INCLUDED_SRC_Bus_DevPciInternal_h
|
|---|
| 29 | #define VBOX_INCLUDED_SRC_Bus_DevPciInternal_h
|
|---|
| 30 | #ifndef RT_WITHOUT_PRAGMA_ONCE
|
|---|
| 31 | # pragma once
|
|---|
| 32 | #endif
|
|---|
| 33 |
|
|---|
| 34 | #ifndef PDMPCIDEV_INCLUDE_PRIVATE
|
|---|
| 35 | # define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
|
|---|
| 36 | #endif
|
|---|
| 37 | #include <VBox/vmm/pdmdev.h>
|
|---|
| 38 |
|
|---|
| 39 |
|
|---|
| 40 | /**
|
|---|
| 41 | * PCI bus shared instance data (common to both PCI buses).
|
|---|
| 42 | *
|
|---|
| 43 | * The PCI device for the bus is always the first one (PDMDEVINSR3::apPciDevs[0]).
|
|---|
| 44 | */
|
|---|
| 45 | typedef struct DEVPCIBUS
|
|---|
| 46 | {
|
|---|
| 47 | /** Bus number. */
|
|---|
| 48 | uint32_t iBus;
|
|---|
| 49 | /** Number of bridges attached to the bus. */
|
|---|
| 50 | uint32_t cBridges;
|
|---|
| 51 | /** Start device number - always zero (only for DevPCI source compat). */
|
|---|
| 52 | uint32_t iDevSearch;
|
|---|
| 53 | /** Set if PIIX3 type. */
|
|---|
| 54 | uint32_t fTypePiix3 : 1;
|
|---|
| 55 | /** Set if ICH9 type. */
|
|---|
| 56 | uint32_t fTypeIch9 : 1;
|
|---|
| 57 | /** Set if this is a pure bridge, i.e. not part of DEVPCIGLOBALS struct. */
|
|---|
| 58 | uint32_t fPureBridge : 1;
|
|---|
| 59 | /** Reserved for future config flags. */
|
|---|
| 60 | uint32_t uReservedConfigFlags : 29;
|
|---|
| 61 |
|
|---|
| 62 | /** Array of bridges attached to the bus. */
|
|---|
| 63 | R3PTRTYPE(PPDMPCIDEV *) papBridgesR3;
|
|---|
| 64 | /** Cache line align apDevices. */
|
|---|
| 65 | uint32_t au32Alignment1[HC_ARCH_BITS == 32 ? 3 + 8 : 2 + 8];
|
|---|
| 66 | /** Array of PCI devices. We assume 32 slots, each with 8 functions. */
|
|---|
| 67 | R3PTRTYPE(PPDMPCIDEV) apDevices[256];
|
|---|
| 68 | } DEVPCIBUS;
|
|---|
| 69 | /** Pointer to PCI bus shared instance data. */
|
|---|
| 70 | typedef DEVPCIBUS *PDEVPCIBUS;
|
|---|
| 71 |
|
|---|
| 72 | /**
|
|---|
| 73 | * PCI bus ring-3 instance data (common to both PCI buses).
|
|---|
| 74 | */
|
|---|
| 75 | typedef struct DEVPCIBUSR3
|
|---|
| 76 | {
|
|---|
| 77 | /** R3 pointer to the device instance. */
|
|---|
| 78 | PPDMDEVINSR3 pDevInsR3;
|
|---|
| 79 | /** Pointer to the PCI R3 helpers. */
|
|---|
| 80 | PCPDMPCIHLPR3 pPciHlpR3;
|
|---|
| 81 | } DEVPCIBUSR3;
|
|---|
| 82 | /** Pointer to PCI bus ring-3 instance data. */
|
|---|
| 83 | typedef DEVPCIBUSR3 *PDEVPCIBUSR3;
|
|---|
| 84 |
|
|---|
| 85 | /**
|
|---|
| 86 | * PCI bus ring-0 instance data (common to both PCI buses).
|
|---|
| 87 | */
|
|---|
| 88 | typedef struct DEVPCIBUSR0
|
|---|
| 89 | {
|
|---|
| 90 | /** R0 pointer to the device instance. */
|
|---|
| 91 | PPDMDEVINSR0 pDevInsR0;
|
|---|
| 92 | /** Pointer to the PCI R0 helpers. */
|
|---|
| 93 | PCPDMPCIHLPR0 pPciHlpR0;
|
|---|
| 94 | } DEVPCIBUSR0;
|
|---|
| 95 | /** Pointer to PCI bus ring-0 instance data. */
|
|---|
| 96 | typedef DEVPCIBUSR0 *PDEVPCIBUSR0;
|
|---|
| 97 |
|
|---|
| 98 | /**
|
|---|
| 99 | * PCI bus raw-mode instance data (common to both PCI buses).
|
|---|
| 100 | */
|
|---|
| 101 | typedef struct DEVPCIBUSRC
|
|---|
| 102 | {
|
|---|
| 103 | /** R0 pointer to the device instance. */
|
|---|
| 104 | PPDMDEVINSRC pDevInsRC;
|
|---|
| 105 | /** Pointer to the PCI raw-mode helpers. */
|
|---|
| 106 | PCPDMPCIHLPRC pPciHlpRC;
|
|---|
| 107 | } DEVPCIBUSRC;
|
|---|
| 108 | /** Pointer to PCI bus raw-mode instance data. */
|
|---|
| 109 | typedef DEVPCIBUSRC *PDEVPCIBUSRC;
|
|---|
| 110 |
|
|---|
| 111 | /** DEVPCIBUSR3, DEVPCIBUSR0 or DEVPCIBUSRC depending on context. */
|
|---|
| 112 | typedef CTX_SUFF(DEVPCIBUS) DEVPCIBUSCC;
|
|---|
| 113 | /** PDEVPCIBUSR3, PDEVPCIBUSR0 or PDEVPCIBUSRC depending on context. */
|
|---|
| 114 | typedef CTX_SUFF(PDEVPCIBUS) PDEVPCIBUSCC;
|
|---|
| 115 |
|
|---|
| 116 |
|
|---|
| 117 | /** @def DEVPCI_APIC_IRQ_PINS
|
|---|
| 118 | * Number of pins for interrupts if the APIC is used.
|
|---|
| 119 | */
|
|---|
| 120 | #define DEVPCI_APIC_IRQ_PINS 8
|
|---|
| 121 | /** @def DEVPCI_LEGACY_IRQ_PINS
|
|---|
| 122 | * Number of pins for interrupts (PIRQ#0...PIRQ#3).
|
|---|
| 123 | * @remarks Labling this "legacy" might be a bit off...
|
|---|
| 124 | */
|
|---|
| 125 | #define DEVPCI_LEGACY_IRQ_PINS 4
|
|---|
| 126 |
|
|---|
| 127 |
|
|---|
| 128 | /**
|
|---|
| 129 | * PCI Globals - This is the host-to-pci bridge and the root bus, shared data.
|
|---|
| 130 | *
|
|---|
| 131 | * @note Only used by the root bus, not the bridges.
|
|---|
| 132 | */
|
|---|
| 133 | typedef struct DEVPCIROOT
|
|---|
| 134 | {
|
|---|
| 135 | /** PCI bus which is attached to the host-to-PCI bridge.
|
|---|
| 136 | * @note This must come first so we can share more code with the bridges! */
|
|---|
| 137 | DEVPCIBUS PciBus;
|
|---|
| 138 |
|
|---|
| 139 | /** I/O APIC usage flag (always true of ICH9, see constructor). */
|
|---|
| 140 | bool fUseIoApic;
|
|---|
| 141 | /** Reserved for future config flags. */
|
|---|
| 142 | bool afFutureFlags[3+4+8];
|
|---|
| 143 | /** Physical address of PCI config space MMIO region. */
|
|---|
| 144 | uint64_t u64PciConfigMMioAddress;
|
|---|
| 145 | /** Length of PCI config space MMIO region. */
|
|---|
| 146 | uint64_t u64PciConfigMMioLength;
|
|---|
| 147 |
|
|---|
| 148 | /** I/O APIC irq levels */
|
|---|
| 149 | volatile uint32_t auPciApicIrqLevels[DEVPCI_APIC_IRQ_PINS];
|
|---|
| 150 | /** Value latched in Configuration Address Port (0CF8h) */
|
|---|
| 151 | uint32_t uConfigReg;
|
|---|
| 152 | /** Alignment padding. */
|
|---|
| 153 | uint32_t u32Alignment1;
|
|---|
| 154 | /** Members only used by the PIIX3 code variant.
|
|---|
| 155 | * (The PCI device for the PCI-to-ISA bridge is PDMDEVINSR3::apPciDevs[1].) */
|
|---|
| 156 | struct
|
|---|
| 157 | {
|
|---|
| 158 | /** ACPI IRQ level */
|
|---|
| 159 | uint32_t iAcpiIrqLevel;
|
|---|
| 160 | /** ACPI PIC IRQ */
|
|---|
| 161 | int32_t iAcpiIrq;
|
|---|
| 162 | /** Irq levels for the four PCI Irqs.
|
|---|
| 163 | * These count how many devices asserted the IRQ line. If greater 0 an IRQ
|
|---|
| 164 | * is sent to the guest. If it drops to 0 the IRQ is deasserted.
|
|---|
| 165 | * @remarks Labling this "legacy" might be a bit off...
|
|---|
| 166 | */
|
|---|
| 167 | volatile uint32_t auPciLegacyIrqLevels[DEVPCI_LEGACY_IRQ_PINS];
|
|---|
| 168 | } Piix3;
|
|---|
| 169 |
|
|---|
| 170 | /** The address I/O port handle. */
|
|---|
| 171 | IOMIOPORTHANDLE hIoPortAddress;
|
|---|
| 172 | /** The data I/O port handle. */
|
|---|
| 173 | IOMIOPORTHANDLE hIoPortData;
|
|---|
| 174 | /** The magic I/O port handle. */
|
|---|
| 175 | IOMIOPORTHANDLE hIoPortMagic;
|
|---|
| 176 | /** The MCFG MMIO region. */
|
|---|
| 177 | IOMMMIOHANDLE hMmioMcfg;
|
|---|
| 178 |
|
|---|
| 179 | #if 1 /* Will be moved into the BIOS "soon". */
|
|---|
| 180 | /** Current bus number - obsolete (still used by DevPCI, but merge will fix that). */
|
|---|
| 181 | uint8_t uPciBiosBus;
|
|---|
| 182 | uint8_t abAlignment2[7];
|
|---|
| 183 | /** The next I/O port address which the PCI BIOS will use. */
|
|---|
| 184 | uint32_t uPciBiosIo;
|
|---|
| 185 | /** The next MMIO address which the PCI BIOS will use. */
|
|---|
| 186 | uint32_t uPciBiosMmio;
|
|---|
| 187 | /** The next 64-bit MMIO address which the PCI BIOS will use. */
|
|---|
| 188 | uint64_t uPciBiosMmio64;
|
|---|
| 189 | #endif
|
|---|
| 190 |
|
|---|
| 191 | } DEVPCIROOT;
|
|---|
| 192 | /** Pointer to PCI device globals. */
|
|---|
| 193 | typedef DEVPCIROOT *PDEVPCIROOT;
|
|---|
| 194 | /** Converts a PCI bus device instance pointer to a DEVPCIBUS pointer. */
|
|---|
| 195 | #define DEVINS_2_DEVPCIBUS(pDevIns) (&PDMINS_2_DATA(pDevIns, PDEVPCIROOT)->PciBus)
|
|---|
| 196 | /** Converts a pointer to a PCI bus instance to a DEVPCIROOT pointer. */
|
|---|
| 197 | #define DEVPCIBUS_2_DEVPCIROOT(pPciBus) RT_FROM_MEMBER(pPciBus, DEVPCIROOT, PciBus)
|
|---|
| 198 |
|
|---|
| 199 |
|
|---|
| 200 | /** @def PCI_LOCK_RET
|
|---|
| 201 | * Acquires the PDM lock. This is a NOP if locking is disabled. */
|
|---|
| 202 | #define PCI_LOCK_RET(pDevIns, rcBusy) \
|
|---|
| 203 | do { \
|
|---|
| 204 | int const rcLock = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rcBusy); \
|
|---|
| 205 | if (rcLock == VINF_SUCCESS) \
|
|---|
| 206 | { /* likely */ } \
|
|---|
| 207 | else \
|
|---|
| 208 | return rcLock; \
|
|---|
| 209 | } while (0)
|
|---|
| 210 | /** @def PCI_UNLOCK
|
|---|
| 211 | * Releases the PDM lock. This is a NOP if locking is disabled. */
|
|---|
| 212 | #define PCI_UNLOCK(pDevIns) \
|
|---|
| 213 | PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
|
|---|
| 214 |
|
|---|
| 215 |
|
|---|
| 216 | DECLHIDDEN(PPDMDEVINS) devpcibridgeCommonSetIrqRootWalk(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq,
|
|---|
| 217 | PDEVPCIBUS *ppBus, uint8_t *puDevFnBridge, int *piIrqPinBridge);
|
|---|
| 218 |
|
|---|
| 219 | #ifdef IN_RING3
|
|---|
| 220 |
|
|---|
| 221 | DECLCALLBACK(void) devpciR3InfoPci(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs);
|
|---|
| 222 | DECLCALLBACK(void) devpciR3InfoPciIrq(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs);
|
|---|
| 223 | DECLCALLBACK(int) devpciR3CommonRegisterDevice(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
|
|---|
| 224 | uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName);
|
|---|
| 225 | DECLCALLBACK(int) devpcibridgeR3CommonRegisterDevice(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
|
|---|
| 226 | uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName);
|
|---|
| 227 | DECLCALLBACK(int) devpciR3CommonIORegionRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
|
|---|
| 228 | RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
|
|---|
| 229 | uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap);
|
|---|
| 230 | DECLCALLBACK(void) devpciR3CommonInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
|
|---|
| 231 | PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite);
|
|---|
| 232 | DECLCALLBACK(VBOXSTRICTRC) devpciR3CommonConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
|
|---|
| 233 | uint32_t uAddress, unsigned cb, uint32_t *pu32Value);
|
|---|
| 234 | DECLHIDDEN(VBOXSTRICTRC) devpciR3CommonConfigReadWorker(PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb, uint32_t *pu32Value);
|
|---|
| 235 | DECLCALLBACK(VBOXSTRICTRC) devpciR3CommonConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
|
|---|
| 236 | uint32_t uAddress, unsigned cb, uint32_t u32Value);
|
|---|
| 237 | DECLHIDDEN(VBOXSTRICTRC) devpciR3CommonConfigWriteWorker(PPDMDEVINS pDevIns, PDEVPCIBUSCC pBusCC,
|
|---|
| 238 | PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb, uint32_t u32Value);
|
|---|
| 239 | void devpciR3CommonRestoreConfig(PPDMDEVINS pDevIns, PPDMPCIDEV pDev, uint8_t const *pbSrcConfig);
|
|---|
| 240 | int devpciR3CommonRestoreRegions(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, PPDMPCIDEV pPciDev, PPCIIOREGION paIoRegions, bool fNewState);
|
|---|
| 241 | void devpciR3ResetDevice(PPDMDEVINS pDevIns, PPDMPCIDEV pDev);
|
|---|
| 242 | void devpciR3BiosInitSetRegionAddress(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, int iRegion, uint64_t addr);
|
|---|
| 243 | uint32_t devpciR3GetCfg(PPDMPCIDEV pPciDev, int32_t iRegister, int cb);
|
|---|
| 244 | void devpciR3SetCfg(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32, int cb);
|
|---|
| 245 |
|
|---|
| 246 | DECLINLINE(uint8_t) devpciR3GetByte(PPDMPCIDEV pPciDev, int32_t iRegister)
|
|---|
| 247 | {
|
|---|
| 248 | return (uint8_t)devpciR3GetCfg(pPciDev, iRegister, 1);
|
|---|
| 249 | }
|
|---|
| 250 |
|
|---|
| 251 | DECLINLINE(uint16_t) devpciR3GetWord(PPDMPCIDEV pPciDev, int32_t iRegister)
|
|---|
| 252 | {
|
|---|
| 253 | return (uint16_t)devpciR3GetCfg(pPciDev, iRegister, 2);
|
|---|
| 254 | }
|
|---|
| 255 |
|
|---|
| 256 | DECLINLINE(uint32_t) devpciR3GetDWord(PPDMPCIDEV pPciDev, int32_t iRegister)
|
|---|
| 257 | {
|
|---|
| 258 | return (uint32_t)devpciR3GetCfg(pPciDev, iRegister, 4);
|
|---|
| 259 | }
|
|---|
| 260 |
|
|---|
| 261 | DECLINLINE(void) devpciR3SetByte(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int32_t iRegister, uint8_t u8)
|
|---|
| 262 | {
|
|---|
| 263 | devpciR3SetCfg(pDevIns, pPciDev, iRegister, u8, 1);
|
|---|
| 264 | }
|
|---|
| 265 |
|
|---|
| 266 | DECLINLINE(void) devpciR3SetWord(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int32_t iRegister, uint16_t u16)
|
|---|
| 267 | {
|
|---|
| 268 | devpciR3SetCfg(pDevIns, pPciDev, iRegister, u16, 2);
|
|---|
| 269 | }
|
|---|
| 270 |
|
|---|
| 271 | DECLINLINE(void) devpciR3SetDWord(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32)
|
|---|
| 272 | {
|
|---|
| 273 | devpciR3SetCfg(pDevIns, pPciDev, iRegister, u32, 4);
|
|---|
| 274 | }
|
|---|
| 275 |
|
|---|
| 276 | #endif /* IN_RING3 */
|
|---|
| 277 |
|
|---|
| 278 | #endif /* !VBOX_INCLUDED_SRC_Bus_DevPciInternal_h */
|
|---|
| 279 |
|
|---|
