VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevPciInternal.h@ 99771

Last change on this file since 99771 was 99750, checked in by vboxsync, 19 months ago

Devices/Bus: Started a basic PCI bus implementation suitable for ARMv8, devices are detected by a Linux guest but interrupts don't work right now. The implementation shares most code with ICH9 PCI device, bugref:10445
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File size: 13.4 KB
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1/* $Id: DevPciInternal.h 99750 2023-05-11 13:37:24Z vboxsync $ */
2/** @file
3 * DevPCI - Common Internal Header.
4 */
5
6/*
7 * Copyright (C) 2010-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VBOX_INCLUDED_SRC_Bus_DevPciInternal_h
29#define VBOX_INCLUDED_SRC_Bus_DevPciInternal_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#ifndef PDMPCIDEV_INCLUDE_PRIVATE
35# define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
36#endif
37#include <VBox/vmm/pdmdev.h>
38
39#include "PciInline.h"
40
41
42/**
43 * Supported PCI bus types.
44 */
45typedef enum DEVPCIBUSTYPE
46{
47 /** The usual invalid type. */
48 DEVPCIBUSTYPE_INVALID = 0,
49 /** PIIX3 PCI bus type. */
50 DEVPCIBUSTYPE_PIIX3,
51 /** ICH9 PCI bus type. */
52 DEVPCIBUSTYPE_ICH9,
53 /** Generic ECAM PCI bus type. */
54 DEVPCIBUSTYPE_GENERIC_ECAM,
55 /** 32bit blowup. */
56 DEVPCIBUSTYPE_32BIT_HACK = 0x7fffffff
57} DEVPCIBUSTYPE;
58
59
60/**
61 * PCI bus shared instance data (common to both PCI buses).
62 *
63 * The PCI device for the bus is always the first one (PDMDEVINSR3::apPciDevs[0]).
64 */
65typedef struct DEVPCIBUS
66{
67 /** Bus number. */
68 uint32_t iBus;
69 /** Number of bridges attached to the bus. */
70 uint32_t cBridges;
71 /** Start device number - always zero (only for DevPCI source compat). */
72 uint32_t iDevSearch;
73 /** PCI Bus type. */
74 DEVPCIBUSTYPE enmType;
75 /** Set if this is a pure bridge, i.e. not part of DEVPCIGLOBALS struct. */
76 uint32_t fPureBridge : 1;
77 /** Reserved for future config flags. */
78 uint32_t uReservedConfigFlags : 31;
79
80 /** Array of bridges attached to the bus. */
81 R3PTRTYPE(PPDMPCIDEV *) papBridgesR3;
82 /** Cache line align apDevices. */
83 uint32_t au32Alignment1[HC_ARCH_BITS == 32 ? 2 + 8 : 8];
84 /** Array of PCI devices. We assume 32 slots, each with 8 functions. */
85 R3PTRTYPE(PPDMPCIDEV) apDevices[256];
86} DEVPCIBUS;
87/** Pointer to PCI bus shared instance data. */
88typedef DEVPCIBUS *PDEVPCIBUS;
89AssertCompileMemberAlignment(DEVPCIBUS, apDevices, 64);
90
91
92/**
93 * PCI bus ring-3 instance data (common to both PCI buses).
94 */
95typedef struct DEVPCIBUSR3
96{
97 /** R3 pointer to the device instance. */
98 PPDMDEVINSR3 pDevInsR3;
99 /** Pointer to the PCI R3 helpers. */
100 PCPDMPCIHLPR3 pPciHlpR3;
101} DEVPCIBUSR3;
102/** Pointer to PCI bus ring-3 instance data. */
103typedef DEVPCIBUSR3 *PDEVPCIBUSR3;
104
105/**
106 * PCI bus ring-0 instance data (common to both PCI buses).
107 */
108typedef struct DEVPCIBUSR0
109{
110 /** R0 pointer to the device instance. */
111 PPDMDEVINSR0 pDevInsR0;
112 /** Pointer to the PCI R0 helpers. */
113 PCPDMPCIHLPR0 pPciHlpR0;
114} DEVPCIBUSR0;
115/** Pointer to PCI bus ring-0 instance data. */
116typedef DEVPCIBUSR0 *PDEVPCIBUSR0;
117
118/**
119 * PCI bus raw-mode instance data (common to both PCI buses).
120 */
121typedef struct DEVPCIBUSRC
122{
123 /** R0 pointer to the device instance. */
124 PPDMDEVINSRC pDevInsRC;
125 /** Pointer to the PCI raw-mode helpers. */
126 PCPDMPCIHLPRC pPciHlpRC;
127} DEVPCIBUSRC;
128/** Pointer to PCI bus raw-mode instance data. */
129typedef DEVPCIBUSRC *PDEVPCIBUSRC;
130
131/** DEVPCIBUSR3, DEVPCIBUSR0 or DEVPCIBUSRC depending on context. */
132typedef CTX_SUFF(DEVPCIBUS) DEVPCIBUSCC;
133/** PDEVPCIBUSR3, PDEVPCIBUSR0 or PDEVPCIBUSRC depending on context. */
134typedef CTX_SUFF(PDEVPCIBUS) PDEVPCIBUSCC;
135
136
137/** @def DEVPCI_APIC_IRQ_PINS
138 * Number of pins for interrupts if the APIC is used.
139 */
140#define DEVPCI_APIC_IRQ_PINS 8
141/** @def DEVPCI_LEGACY_IRQ_PINS
142 * Number of pins for interrupts (PIRQ#0...PIRQ#3).
143 * @remarks Labling this "legacy" might be a bit off...
144 */
145#define DEVPCI_LEGACY_IRQ_PINS 4
146
147
148/**
149 * PCI Globals - This is the host-to-pci bridge and the root bus, shared data.
150 *
151 * @note Only used by the root bus, not the bridges.
152 */
153typedef struct DEVPCIROOT
154{
155 /** PCI bus which is attached to the host-to-PCI bridge.
156 * @note This must come first so we can share more code with the bridges! */
157 DEVPCIBUS PciBus;
158
159 /** I/O APIC usage flag (always true of ICH9, see constructor). */
160 bool fUseIoApic;
161 /** Reserved for future config flags. */
162 bool afFutureFlags[3+4+8];
163 /** Physical address of PCI config space MMIO region. */
164 uint64_t u64PciConfigMMioAddress;
165 /** Length of PCI config space MMIO region. */
166 uint64_t u64PciConfigMMioLength;
167 /** Physical address of PCI PIO emulation MMIO region. */
168 RTGCPHYS GCPhysMmioPioEmuBase;
169 /** Length of PCI PIO emulation MMIO region. */
170 RTGCPHYS GCPhysMmioPioEmuSize;
171
172
173 /** I/O APIC irq levels */
174 volatile uint32_t auPciApicIrqLevels[DEVPCI_APIC_IRQ_PINS];
175 /** Value latched in Configuration Address Port (0CF8h) */
176 uint32_t uConfigReg;
177 /** Alignment padding. */
178 uint32_t u32Alignment1;
179 /** Members only used by the PIIX3 code variant.
180 * (The PCI device for the PCI-to-ISA bridge is PDMDEVINSR3::apPciDevs[1].) */
181 struct
182 {
183 /** ACPI IRQ level */
184 uint32_t iAcpiIrqLevel;
185 /** ACPI PIC IRQ */
186 int32_t iAcpiIrq;
187 /** Irq levels for the four PCI Irqs.
188 * These count how many devices asserted the IRQ line. If greater 0 an IRQ
189 * is sent to the guest. If it drops to 0 the IRQ is deasserted.
190 * @remarks Labling this "legacy" might be a bit off...
191 */
192 volatile uint32_t auPciLegacyIrqLevels[DEVPCI_LEGACY_IRQ_PINS];
193 } Piix3;
194
195 /** The address I/O port handle. */
196 IOMIOPORTHANDLE hIoPortAddress;
197 /** The data I/O port handle. */
198 IOMIOPORTHANDLE hIoPortData;
199 /** The magic I/O port handle. */
200 IOMIOPORTHANDLE hIoPortMagic;
201 /** The MCFG MMIO region. */
202 IOMMMIOHANDLE hMmioMcfg;
203 /** The PIO emulation MMIO region. */
204 IOMMMIOHANDLE hMmioPioEmu;
205
206#if 1 /* Will be moved into the BIOS "soon". */
207 /** Current bus number - obsolete (still used by DevPCI, but merge will fix that). */
208 uint8_t uPciBiosBus;
209 uint8_t abAlignment2[7];
210 /** The next I/O port address which the PCI BIOS will use. */
211 uint32_t uPciBiosIo;
212 /** The next MMIO address which the PCI BIOS will use. */
213 uint32_t uPciBiosMmio;
214 /** The next 64-bit MMIO address which the PCI BIOS will use. */
215 uint64_t uPciBiosMmio64;
216#endif
217
218} DEVPCIROOT;
219/** Pointer to PCI device globals. */
220typedef DEVPCIROOT *PDEVPCIROOT;
221/** Converts a PCI bus device instance pointer to a DEVPCIBUS pointer. */
222#define DEVINS_2_DEVPCIBUS(pDevIns) (&PDMINS_2_DATA(pDevIns, PDEVPCIROOT)->PciBus)
223/** Converts a pointer to a PCI bus instance to a DEVPCIROOT pointer. */
224#define DEVPCIBUS_2_DEVPCIROOT(pPciBus) RT_FROM_MEMBER(pPciBus, DEVPCIROOT, PciBus)
225
226
227/** @def PCI_LOCK_RET
228 * Acquires the PDM lock. This is a NOP if locking is disabled. */
229#define PCI_LOCK_RET(pDevIns, rcBusy) \
230 do { \
231 int const rcLock = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rcBusy); \
232 if (rcLock == VINF_SUCCESS) \
233 { /* likely */ } \
234 else \
235 return rcLock; \
236 } while (0)
237/** @def PCI_UNLOCK
238 * Releases the PDM lock. This is a NOP if locking is disabled. */
239#define PCI_UNLOCK(pDevIns) \
240 PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
241
242
243DECLHIDDEN(PPDMDEVINS) devpcibridgeCommonSetIrqRootWalk(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq,
244 PDEVPCIBUS *ppBus, uint8_t *puDevFnBridge, int *piIrqPinBridge);
245
246DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) devpciCommonMcfgMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb);
247DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) devpciCommonMcfgMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb);
248
249
250#ifdef IN_RING3
251
252# ifndef VBOX_DEVICE_STRUCT_TESTCASE
253DECLCALLBACK(void) devpciR3InfoPci(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs);
254DECLCALLBACK(void) devpciR3InfoPciIrq(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs);
255DECLCALLBACK(int) devpciR3CommonRegisterDevice(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
256 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName);
257DECLCALLBACK(int) devpcibridgeR3CommonRegisterDevice(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
258 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName);
259DECLCALLBACK(int) devpciR3CommonIORegionRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
260 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
261 uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap);
262DECLCALLBACK(void) devpciR3CommonInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
263 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite);
264DECLCALLBACK(VBOXSTRICTRC) devpciR3CommonConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
265 uint32_t uAddress, unsigned cb, uint32_t *pu32Value);
266DECLHIDDEN(VBOXSTRICTRC) devpciR3CommonConfigReadWorker(PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb, uint32_t *pu32Value);
267DECLCALLBACK(VBOXSTRICTRC) devpciR3CommonConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
268 uint32_t uAddress, unsigned cb, uint32_t u32Value);
269DECLHIDDEN(VBOXSTRICTRC) devpciR3CommonConfigWriteWorker(PPDMDEVINS pDevIns, PDEVPCIBUSCC pBusCC,
270 PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb, uint32_t u32Value);
271void devpciR3CommonRestoreConfig(PPDMDEVINS pDevIns, PPDMPCIDEV pDev, uint8_t const *pbSrcConfig);
272int devpciR3CommonRestoreRegions(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, PPDMPCIDEV pPciDev, PPCIIOREGION paIoRegions, bool fNewState);
273void devpciR3ResetDevice(PPDMDEVINS pDevIns, PPDMPCIDEV pDev);
274void devpciR3BiosInitSetRegionAddress(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, int iRegion, uint64_t addr);
275uint32_t devpciR3GetCfg(PPDMPCIDEV pPciDev, int32_t iRegister, int cb);
276void devpciR3SetCfg(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32, int cb);
277DECLHIDDEN(void) devpciR3CommonResetBridge(PPDMDEVINS pDevIns);
278DECL_HIDDEN_CALLBACK(int) devpciR3CommonSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM);
279DECL_HIDDEN_CALLBACK(int) devpciR3CommonLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
280
281
282DECLINLINE(uint8_t) devpciR3GetByte(PPDMPCIDEV pPciDev, int32_t iRegister)
283{
284 return (uint8_t)devpciR3GetCfg(pPciDev, iRegister, 1);
285}
286
287DECLINLINE(uint16_t) devpciR3GetWord(PPDMPCIDEV pPciDev, int32_t iRegister)
288{
289 return (uint16_t)devpciR3GetCfg(pPciDev, iRegister, 2);
290}
291
292DECLINLINE(uint32_t) devpciR3GetDWord(PPDMPCIDEV pPciDev, int32_t iRegister)
293{
294 return (uint32_t)devpciR3GetCfg(pPciDev, iRegister, 4);
295}
296
297DECLINLINE(void) devpciR3SetByte(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int32_t iRegister, uint8_t u8)
298{
299 devpciR3SetCfg(pDevIns, pPciDev, iRegister, u8, 1);
300}
301
302DECLINLINE(void) devpciR3SetWord(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int32_t iRegister, uint16_t u16)
303{
304 devpciR3SetCfg(pDevIns, pPciDev, iRegister, u16, 2);
305}
306
307DECLINLINE(void) devpciR3SetDWord(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32)
308{
309 devpciR3SetCfg(pDevIns, pPciDev, iRegister, u32, 4);
310}
311
312
313DECLINLINE(PPDMPCIDEV) devpciR3FindBridge(PDEVPCIBUS pBus, uint8_t uBus)
314{
315 /* Search for a fitting bridge. */
316 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
317 {
318 /*
319 * Examine secondary and subordinate bus number.
320 * If the target bus is in the range we pass the request on to the bridge.
321 */
322 PPDMPCIDEV pBridge = pBus->papBridgesR3[iBridge];
323 AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
324 ("Device is not a PCI bridge but on the list of PCI bridges\n"));
325 /* safe, only needs to go to the config space array */
326 uint32_t uSecondary = PDMPciDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS);
327 /* safe, only needs to go to the config space array */
328 uint32_t uSubordinate = PDMPciDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS);
329 Log3Func(("bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, uBus, uSecondary, uSubordinate));
330 if (uBus >= uSecondary && uBus <= uSubordinate)
331 return pBridge;
332 }
333
334 /* Nothing found. */
335 return NULL;
336}
337# endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
338
339#endif /* IN_RING3 */
340
341#endif /* !VBOX_INCLUDED_SRC_Bus_DevPciInternal_h */
342
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