DevPciIch9.cpp@ 71136

Last change on this file since 71136 was 70182, checked in by vboxsync, 7 years ago
devpciR3UpdateMappings: Made PCI MMIO work again with NT 3.51 after some certifiable paranoia broke it in r102718. Not logging the rejection of due to this paranoia attack is something so infuriatingly careless I'm beyond words. Wasted many hours of my time.
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File size: 146.7 KB

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1	/* $Id: DevPciIch9.cpp 70182 2017-12-17 13:49:51Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation device.
4	*
5	* @remarks We'll be slowly promoting the code in this file to common PCI bus
6	* code. Function without 'static' and using 'devpci' as prefix is
7	* also used by DevPCI.cpp and have a prototype in DevPciInternal.h.
8	*
9	* For the time being the DevPciMerge1.cpp.h file will remain separate,
10	* due to 5.1. We can merge it into this one later in the dev cycle.
11	*
12	* DO NOT use the PDMPciDev* or PCIDev* family of functions in this
13	* file except in the two callbacks for config space access (and the
14	* functions which are used exclusively by that code) and the two
15	* device constructors when setting up the config space for the
16	* bridges. Everything else need extremely careful review. Using
17	* them elsewhere (especially in the init code) causes weird failures
18	* with PCI passthrough, as it would only update the array of
19	* (emulated) config space, but not talk to the actual device (needs
20	* invoking the respective callback).
21	*/
22
23	/*
24	* Copyright (C) 2010-2017 Oracle Corporation
25	*
26	* This file is part of VirtualBox Open Source Edition (OSE), as
27	* available from http://www.virtualbox.org. This file is free software;
28	* you can redistribute it and/or modify it under the terms of the GNU
29	* General Public License (GPL) as published by the Free Software
30	* Foundation, in version 2 as it comes in the "COPYING" file of the
31	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
32	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
33	*/
34
35
36	/*********************************************************************************************************************************
37	* Header Files *
38	*********************************************************************************************************************************/
39	#define LOG_GROUP LOG_GROUP_DEV_PCI
40	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
41	#include <VBox/vmm/pdmpcidev.h>
42
43	#include <VBox/msi.h>
44	#include <VBox/vmm/pdmdev.h>
45	#include <VBox/vmm/mm.h>
46	#include <iprt/asm.h>
47	#include <iprt/assert.h>
48	#include <iprt/string.h>
49	#ifdef IN_RING3
50	# include <iprt/mem.h>
51	# include <iprt/uuid.h>
52	#endif
53
54	#include "PciInline.h"
55	#include "VBoxDD.h"
56	#include "MsiCommon.h"
57	#include "DevPciInternal.h"
58
59
60	/*********************************************************************************************************************************
61	* Structures and Typedefs *
62	*********************************************************************************************************************************/
63	/**
64	* PCI configuration space address.
65	*/
66	typedef struct
67	{
68	uint8_t iBus;
69	uint8_t iDeviceFunc;
70	uint16_t iRegister;
71	} PciAddress;
72
73
74	/*********************************************************************************************************************************
75	* Defined Constants And Macros *
76	*********************************************************************************************************************************/
77	/** Saved state version of the ICH9 PCI bus device. */
78	#define VBOX_ICH9PCI_SAVED_STATE_VERSION VBOX_ICH9PCI_SAVED_STATE_VERSION_REGION_SIZES
79	/** Adds I/O region types and sizes for dealing changes in resource regions. */
80	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_REGION_SIZES 3
81	/** This appears to be the first state we need to care about. */
82	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
83	/** This is apparently not supported or has a grossly incomplete state, juding
84	* from hints in the code. */
85	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
86
87	/** Invalid PCI region mapping address. */
88	#define INVALID_PCI_ADDRESS UINT32_MAX
89
90
91	/*********************************************************************************************************************************
92	* Internal Functions *
93	*********************************************************************************************************************************/
94	/* Prototypes */
95	static void ich9pciSetIrqInternal(PDEVPCIROOT pPciRoot, uint8_t uDevFn, PPDMPCIDEV pPciDev,
96	int iIrq, int iLevel, uint32_t uTagSrc);
97	#ifdef IN_RING3
98	static int ich9pciFakePCIBIOS(PPDMDEVINS pDevIns);
99	DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PDEVPCIBUS pBus, uint8_t uBus);
100	static void ich9pciBiosInitAllDevicesOnBus(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus);
101	static bool ich9pciBiosInitAllDevicesPrefetchableOnBus(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, bool fUse64Bit, bool fDryrun);
102	#endif
103
104
105	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
106	// mapping, we take n=6 approach
107	DECLINLINE(void) ich9pciPhysToPciAddr(PDEVPCIROOT pPciRoot, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
108	{
109	NOREF(pPciRoot);
110	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<6) - 1);
111	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
112	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
113	}
114
115	DECLINLINE(void) ich9pciStateToPciAddr(PDEVPCIROOT pPciRoot, RTGCPHYS addr, PciAddress* pPciAddr)
116	{
117	pPciAddr->iBus = (pPciRoot->uConfigReg >> 16) & 0xff;
118	pPciAddr->iDeviceFunc = (pPciRoot->uConfigReg >> 8) & 0xff;
119	pPciAddr->iRegister = (pPciRoot->uConfigReg & 0xfc) \| (addr & 3);
120	}
121
122	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
123	{
124	LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
125	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
126	}
127
128	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
129	{
130	/*
131	* The PCI-to-PCI bridge specification defines how the interrupt pins
132	* are routed from the secondary to the primary bus (see chapter 9).
133	* iIrq gives the interrupt pin the pci device asserted.
134	* We change iIrq here according to the spec and call the SetIrq function
135	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
136	*/
137	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
138	PPDMPCIDEV pPciDevBus = pPciDev;
139	int iIrqPinBridge = iIrq;
140	uint8_t uDevFnBridge = 0;
141
142	/* Walk the chain until we reach the host bus. */
143	do
144	{
145	uDevFnBridge = pBus->PciDev.uDevFn;
146	iIrqPinBridge = ((pPciDevBus->uDevFn >> 3) + iIrqPinBridge) & 3;
147
148	/* Get the parent. */
149	pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
150	pPciDevBus = &pBus->PciDev;
151	} while (pBus->iBus != 0);
152
153	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
154	ich9pciSetIrqInternal(DEVPCIBUS_2_DEVPCIROOT(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
155	}
156
157
158	#ifdef IN_RING3
159
160	/**
161	* Port I/O Handler for Fake PCI BIOS trigger OUT operations at 0410h
162	*
163	* @returns VBox status code.
164	*
165	* @param pDevIns ICH9 device instance.
166	* @param pvUser User argument - ignored.
167	* @param uPort Port number used for the OUT operation.
168	* @param u32 The value to output.
169	* @param cb The value size in bytes.
170	*/
171	DECLCALLBACK(int) ich9pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
172	{
173	RT_NOREF2(pvUser, uPort);
174	LogFlowFunc(("Port=%#x u32=%#x cb=%d\n", uPort, u32, cb));
175	if (cb == 4)
176	{
177	if (u32 == UINT32_C(19200509)) // Richard Adams
178	{
179	int rc = ich9pciFakePCIBIOS(pDevIns);
180	AssertRC(rc);
181	}
182	}
183
184	return VINF_SUCCESS;
185	}
186
187
188	/**
189	* Port I/O Handler for Fake PCI BIOS trigger IN operations at 0410h
190	*
191	* @returns VBox status code.
192	*
193	* @param pDevIns ICH9 device instance.
194	* @param pvUser User argument - ignored.
195	* @param uPort Port number used for the IN operation.
196	* @param pu32 Where to store the result.
197	* @param cb Number of bytes read.
198	*/
199	DECLCALLBACK(int) ich9pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
200	{
201	RT_NOREF5(pDevIns, pvUser, uPort, pu32, cb);
202	LogFunc(("Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", uPort, cb));
203	return VERR_IOM_IOPORT_UNUSED;
204	}
205
206	#endif /* IN_RING3 */
207
208
209	/**
210	* Port I/O Handler for PCI address OUT operations.
211	*
212	* Emulates writes to Configuration Address Port at 0CF8h for
213	* Configuration Mechanism #1.
214	*
215	* @returns VBox status code.
216	*
217	* @param pDevIns ICH9 device instance.
218	* @param pvUser User argument - ignored.
219	* @param uPort Port number used for the OUT operation.
220	* @param u32 The value to output.
221	* @param cb The value size in bytes.
222	*/
223	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
224	{
225	LogFlowFunc(("Port=%#x u32=%#x cb=%d\n", uPort, u32, cb));
226	RT_NOREF2(uPort, pvUser);
227	if (cb == 4)
228	{
229	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
230
231	/*
232	* bits [1:0] are hard-wired, read-only and must return zeroes
233	* when read.
234	*/
235	u32 &= ~3;
236
237	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
238	pThis->uConfigReg = u32;
239	PCI_UNLOCK(pDevIns);
240	}
241
242	return VINF_SUCCESS;
243	}
244
245
246	/**
247	* Port I/O Handler for PCI address IN operations.
248	*
249	* Emulates reads from Configuration Address Port at 0CF8h for
250	* Configuration Mechanism #1.
251	*
252	* @returns VBox status code.
253	*
254	* @param pDevIns ICH9 device instance.
255	* @param pvUser User argument - ignored.
256	* @param uPort Port number used for the IN operation.
257	* @param pu32 Where to store the result.
258	* @param cb Number of bytes read.
259	*/
260	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
261	{
262	RT_NOREF2(uPort, pvUser);
263	if (cb == 4)
264	{
265	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
266
267	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
268	*pu32 = pThis->uConfigReg;
269	PCI_UNLOCK(pDevIns);
270
271	LogFlowFunc(("Port=%#x cb=%d -> %#x\n", uPort, cb, *pu32));
272	return VINF_SUCCESS;
273	}
274
275	LogFunc(("Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", uPort, cb));
276	return VERR_IOM_IOPORT_UNUSED;
277	}
278
279
280	/*
281	* Perform configuration space write.
282	*/
283	static int ich9pciConfigWrite(PDEVPCIROOT pPciRoot, PciAddress* pAddr,
284	uint32_t val, int cb, int rcReschedule)
285	{
286	int rc = VINF_SUCCESS;
287	#ifdef IN_RING3
288	NOREF(rcReschedule);
289	#else
290	RT_NOREF2(val, cb);
291	#endif
292
293	if (pAddr->iBus != 0) /* forward to subordinate bus */
294	{
295	if (pPciRoot->PciBus.cBridges)
296	{
297	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! r=klaus don't think that it can work, since the config space access callback only works in R3 */
298	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pPciRoot->PciBus, pAddr->iBus);
299	if (pBridgeDevice)
300	{
301	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
302	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), pAddr->iBus, pAddr->iDeviceFunc,
303	pAddr->iRegister, val, cb);
304	}
305	#else
306	rc = rcReschedule;
307	#endif
308	}
309	}
310	else /* forward to directly connected device */
311	{
312	R3PTRTYPE(PDMPCIDEV *) pPciDev = pPciRoot->PciBus.apDevices[pAddr->iDeviceFunc];
313	if (pPciDev)
314	{
315	#ifdef IN_RING3
316	rc = VBOXSTRICTRC_TODO(pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev,
317	pAddr->iRegister, val, cb));
318	#else
319	rc = rcReschedule;
320	#endif
321	}
322	}
323
324	Log2Func(("%02x:%02x.%d reg %x(%d) %x %Rrc\n",
325	pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister, cb, val, rc));
326	return rc;
327	}
328
329
330	/**
331	* Port I/O Handler for PCI data OUT operations.
332	*
333	* Emulates writes to Configuration Data Port at 0CFCh for
334	* Configuration Mechanism #1.
335	*
336	* @returns VBox status code.
337	*
338	* @param pDevIns ICH9 device instance.
339	* @param pvUser User argument - ignored.
340	* @param uPort Port number used for the OUT operation.
341	* @param u32 The value to output.
342	* @param cb The value size in bytes.
343	*/
344	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
345	{
346	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
347	LogFlowFunc(("Port=%#x u32=%#x cb=%d (config=%#10x)\n", uPort, u32, cb, pThis->uConfigReg));
348	NOREF(pvUser);
349	int rc = VINF_SUCCESS;
350	if (!(uPort % cb))
351	{
352	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
353
354	do
355	{
356	/* Configuration space mapping enabled? */
357	if (!(pThis->uConfigReg & (1 << 31)))
358	break;
359
360	/* Decode target device from Configuration Address Port */
361	PciAddress aPciAddr;
362	ich9pciStateToPciAddr(pThis, uPort, &aPciAddr);
363
364	/* Perform configuration space write */
365	rc = ich9pciConfigWrite(pThis, &aPciAddr, u32, cb, VINF_IOM_R3_IOPORT_WRITE);
366	} while (0);
367
368	PCI_UNLOCK(pDevIns);
369	}
370	else
371	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", uPort, u32, cb));
372	return rc;
373	}
374
375
376	/*
377	* Perform configuration space read.
378	*/
379	static int ich9pciConfigRead(PDEVPCIROOT pPciRoot, PciAddress* pPciAddr, int cb,
380	uint32_t *pu32, int rcReschedule)
381	{
382	int rc = VINF_SUCCESS;
383	#ifdef IN_RING3
384	NOREF(rcReschedule);
385	#else
386	NOREF(cb);
387	#endif
388
389	if (pPciAddr->iBus != 0) /* forward to subordinate bus */
390	{
391	if (pPciRoot->PciBus.cBridges)
392	{
393	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! r=klaus don't think that it can work, since the config space access callback only works in R3 */
394	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pPciRoot->PciBus, pPciAddr->iBus);
395	if (pBridgeDevice)
396	{
397	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
398	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), pPciAddr->iBus,
399	pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
400	}
401	else
402	*pu32 = 0xffffffff;
403	#else
404	rc = rcReschedule;
405	#endif
406	}
407	else
408	*pu32 = 0xffffffff;
409	}
410	else /* forward to directly connected device */
411	{
412	R3PTRTYPE(PDMPCIDEV *) pPciDev = pPciRoot->PciBus.apDevices[pPciAddr->iDeviceFunc];
413	if (pPciDev)
414	{
415	#ifdef IN_RING3
416	*pu32 = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, pPciAddr->iRegister, cb);
417	#else
418	rc = rcReschedule;
419	#endif
420	}
421	else
422	*pu32 = 0xffffffff;
423	}
424
425	Log3Func(("%02x:%02x.%d reg %x(%d) gave %x %Rrc\n",
426	pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister, cb, *pu32, rc));
427	return rc;
428	}
429
430
431	/**
432	* Port I/O Handler for PCI data IN operations.
433	*
434	* Emulates reads from Configuration Data Port at 0CFCh for
435	* Configuration Mechanism #1.
436	*
437	* @returns VBox status code.
438	*
439	* @param pDevIns ICH9 device instance.
440	* @param pvUser User argument - ignored.
441	* @param uPort Port number used for the IN operation.
442	* @param pu32 Where to store the result.
443	* @param cb Number of bytes read.
444	*/
445	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
446	{
447	NOREF(pvUser);
448	int rc = VINF_SUCCESS;
449	if (!(uPort % cb))
450	{
451	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
452	*pu32 = 0xffffffff;
453
454	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
455
456	do
457	{
458	/* Configuration space mapping enabled? */
459	if (!(pThis->uConfigReg & (1 << 31)))
460	{
461	rc = VINF_SUCCESS;
462	break;
463	}
464
465	/* Decode target device and configuration space register */
466	PciAddress aPciAddr;
467	ich9pciStateToPciAddr(pThis, uPort, &aPciAddr);
468
469	/* Perform configuration space read */
470	rc = ich9pciConfigRead(pThis, &aPciAddr, cb, pu32, VINF_IOM_R3_IOPORT_READ);
471	} while (0);
472
473	PCI_UNLOCK(pDevIns);
474
475	LogFlowFunc(("Port=%#x cb=%#x (config=%#10x) -> %#x (%Rrc)\n", uPort, cb, *pu32, pThis->uConfigReg, rc));
476	return rc;
477	}
478	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", uPort, cb));
479	return VERR_IOM_IOPORT_UNUSED;
480	}
481
482
483	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
484	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
485	{
486	return (irq_num + uSlot) & 7;
487	}
488
489	#ifdef IN_RING3
490
491	/* return the global irq number corresponding to a given device irq
492	pin. We could also use the bus number to have a more precise
493	mapping. This is the implementation note described in the PCI spec chapter 2.2.6 */
494	DECLINLINE(int) ich9pciSlotGetPirq(uint8_t uBus, uint8_t uDevFn, uint8_t uIrqNum)
495	{
496	NOREF(uBus);
497	int iSlotAddend = (uDevFn >> 3) - 1;
498	return (uIrqNum + iSlotAddend) & 3;
499	}
500
501	/* irqs corresponding to PCI irqs A-D, must match pci_irq_list in pcibios.inc */
502	/** @todo r=klaus inconsistent! ich9 doesn't implement PIRQ yet, so both needs to be addressed and tested thoroughly. */
503	static const uint8_t aPciIrqs[4] = { 11, 10, 9, 5 };
504
505	#endif /* IN_RING3 */
506
507	/* Add one more level up request on APIC input line */
508	DECLINLINE(void) ich9pciApicLevelUp(PDEVPCIROOT pPciRoot, int irq_num)
509	{
510	ASMAtomicIncU32(&pPciRoot->auPciApicIrqLevels[irq_num]);
511	}
512
513	/* Remove one level up request on APIC input line */
514	DECLINLINE(void) ich9pciApicLevelDown(PDEVPCIROOT pPciRoot, int irq_num)
515	{
516	ASMAtomicDecU32(&pPciRoot->auPciApicIrqLevels[irq_num]);
517	}
518
519	static void ich9pciApicSetIrq(PDEVPCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel,
520	uint32_t uTagSrc, int iForcedIrq)
521	{
522	/* This is only allowed to be called with a pointer to the root bus. */
523	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
524
525	if (iForcedIrq == -1)
526	{
527	int apic_irq, apic_level;
528	PDEVPCIROOT pPciRoot = DEVPCIBUS_2_DEVPCIROOT(pBus);
529	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
530
531	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
532	ich9pciApicLevelUp(pPciRoot, irq_num);
533	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
534	ich9pciApicLevelDown(pPciRoot, irq_num);
535
536	apic_irq = irq_num + 0x10;
537	apic_level = pPciRoot->auPciApicIrqLevels[irq_num] != 0;
538	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x\n",
539	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
540	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
541
542	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
543	{
544	/*
545	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
546	* PDM_IRQ_LEVEL_HIGH bit set
547	*/
548	ich9pciApicLevelDown(pPciRoot, irq_num);
549	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
550	apic_level = pPciRoot->auPciApicIrqLevels[irq_num] != 0;
551	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x (flop)\n",
552	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
553	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
554	}
555	} else {
556	Log3Func(("(forced) %s: irq_num1=%d level=%d acpi_irq=%d uTagSrc=%#x\n",
557	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iForcedIrq, uTagSrc));
558	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel, uTagSrc);
559	}
560	}
561
562	static void ich9pciSetIrqInternal(PDEVPCIROOT pPciRoot, uint8_t uDevFn, PPDMPCIDEV pPciDev,
563	int iIrq, int iLevel, uint32_t uTagSrc)
564	{
565	/* If MSI or MSI-X is enabled, PCI INTx# signals are disabled regardless of the PCI command
566	* register interrupt bit state.
567	* PCI 3.0 (section 6.8) forbids MSI and MSI-X to be enabled at the same time and makes
568	* that undefined behavior. We check for MSI first, then MSI-X.
569	*/
570	if (MsiIsEnabled(pPciDev))
571	{
572	Assert(!MsixIsEnabled(pPciDev)); /* Not allowed -- see note above. */
573	LogFlowFunc(("PCI Dev %p : MSI\n", pPciDev));
574	PPDMDEVINS pDevIns = pPciRoot->PciBus.CTX_SUFF(pDevIns);
575	MsiNotify(pDevIns, pPciRoot->PciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
576	return;
577	}
578
579	if (MsixIsEnabled(pPciDev))
580	{
581	LogFlowFunc(("PCI Dev %p : MSI-X\n", pPciDev));
582	PPDMDEVINS pDevIns = pPciRoot->PciBus.CTX_SUFF(pDevIns);
583	MsixNotify(pDevIns, pPciRoot->PciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
584	return;
585	}
586
587	PDEVPCIBUS pBus = &pPciRoot->PciBus;
588	/* safe, only needs to go to the config space array */
589	const bool fIsAcpiDevice = PDMPciDevGetDeviceId(pPciDev) == 0x7113;
590
591	LogFlowFunc(("PCI Dev %p : IRQ\n", pPciDev));
592	/* Check if the state changed. */
593	if (pPciDev->Int.s.uIrqPinState != iLevel)
594	{
595	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
596
597	/** @todo r=klaus: implement PIRQ handling (if APIC isn't active). Needed for legacy OSes which don't use the APIC stuff. */
598
599	/* Send interrupt to I/O APIC only now. */
600	if (fIsAcpiDevice)
601	/*
602	* ACPI needs special treatment since SCI is hardwired and
603	* should not be affected by PCI IRQ routing tables at the
604	* same time SCI IRQ is shared in PCI sense hence this
605	* kludge (i.e. we fetch the hardwired value from ACPIs
606	* PCI device configuration space).
607	*/
608	/* safe, only needs to go to the config space array */
609	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, uTagSrc, PDMPciDevGetInterruptLine(pPciDev));
610	else
611	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, uTagSrc, -1);
612	}
613	}
614
615
616	/**
617	* Memory mapped I/O Handler for write operations.
618	*
619	* Emulates writes to configuration space.
620	*
621	* @returns VBox status code.
622	*
623	* @param pDevIns The device instance.
624	* @param pvUser User argument.
625	* @param GCPhysAddr Physical address (in GC) where the read starts.
626	* @param pv Where to fetch the result.
627	* @param cb Number of bytes to write.
628	* @remarks Caller enters the device critical section.
629	*/
630	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
631	{
632	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
633	uint32_t u32 = 0;
634	NOREF(pvUser);
635
636	Log2Func(("%RGp(%d) \n", GCPhysAddr, cb));
637
638	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_WRITE);
639
640	/* Decode target device and configuration space register */
641	PciAddress aDest;
642	ich9pciPhysToPciAddr(pPciRoot, GCPhysAddr, &aDest);
643
644	switch (cb)
645	{
646	case 1:
647	u32 = (uint8_t)pv;
648	break;
649	case 2:
650	u32 = (uint16_t)pv;
651	break;
652	case 4:
653	u32 = (uint32_t)pv;
654	break;
655	default:
656	Assert(false);
657	break;
658	}
659
660	/* Perform configuration space write */
661	int rc = ich9pciConfigWrite(pPciRoot, &aDest, u32, cb, VINF_IOM_R3_MMIO_WRITE);
662	PCI_UNLOCK(pDevIns);
663
664	return rc;
665	}
666
667
668	/**
669	* Memory mapped I/O Handler for read operations.
670	*
671	* Emulates reads from configuration space.
672	*
673	* @returns VBox status code.
674	*
675	* @param pDevIns The device instance.
676	* @param pvUser User argument.
677	* @param GCPhysAddr Physical address (in GC) where the read starts.
678	* @param pv Where to store the result.
679	* @param cb Number of bytes read.
680	* @remarks Caller enters the device critical section.
681	*/
682	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
683	{
684	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
685	uint32_t rv;
686	NOREF(pvUser);
687
688	LogFlowFunc(("%RGp(%d) \n", GCPhysAddr, cb));
689
690	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_READ);
691
692	/* Decode target device and configuration space register */
693	PciAddress aDest;
694	ich9pciPhysToPciAddr(pPciRoot, GCPhysAddr, &aDest);
695
696	/* Perform configuration space read */
697	int rc = ich9pciConfigRead(pPciRoot, &aDest, cb, &rv, VINF_IOM_R3_MMIO_READ);
698
699	if (RT_SUCCESS(rc))
700	{
701	switch (cb)
702	{
703	case 1:
704	(uint8_t)pv = (uint8_t)rv;
705	break;
706	case 2:
707	(uint16_t)pv = (uint16_t)rv;
708	break;
709	case 4:
710	(uint32_t)pv = (uint32_t)rv;
711	break;
712	default:
713	Assert(false);
714	break;
715	}
716	}
717	PCI_UNLOCK(pDevIns);
718
719	return rc;
720	}
721
722	#ifdef IN_RING3
723
724	/*
725	* Include code we share with the other PCI bus implementation.
726	*
727	* Note! No #ifdefs, use instant data booleans/flags/whatever. Goal is to
728	* completely merge these files! File #1 contains code we write, where
729	* as a possible file #2 contains external code if there's any left.
730	*/
731	# include "DevPciMerge1.cpp.h"
732
733
734	DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PDEVPCIBUS pBus, uint8_t uBus)
735	{
736	/* Search for a fitting bridge. */
737	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
738	{
739	/*
740	* Examine secondary and subordinate bus number.
741	* If the target bus is in the range we pass the request on to the bridge.
742	*/
743	PPDMPCIDEV pBridge = pBus->papBridgesR3[iBridge];
744	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
745	("Device is not a PCI bridge but on the list of PCI bridges\n"));
746	/* safe, only needs to go to the config space array */
747	uint32_t uSecondary = PDMPciDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS);
748	/* safe, only needs to go to the config space array */
749	uint32_t uSubordinate = PDMPciDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS);
750	Log3Func(("bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, uBus, uSecondary, uSubordinate));
751	if (uBus >= uSecondary && uBus <= uSubordinate)
752	return pBridge;
753	}
754
755	/* Nothing found. */
756	return NULL;
757	}
758
759	uint32_t devpciR3GetCfg(PPDMPCIDEV pPciDev, int32_t iRegister, int cb)
760	{
761	return pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, iRegister, cb);
762	}
763
764	DECLINLINE(uint32_t) devpciGetRegionReg(int iRegion)
765	{
766	return iRegion == VBOX_PCI_ROM_SLOT
767	? VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
768	}
769
770	void devpciR3SetCfg(PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32, int cb)
771	{
772	pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, iRegister, u32, cb);
773	}
774
775
776	/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
777
778
779	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
780	{
781	NOREF(pDevIns);
782	int rc;
783
784	rc = MsiInit(pPciDev, pMsiReg);
785	if (RT_FAILURE(rc))
786	return rc;
787
788	rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
789	if (RT_FAILURE(rc))
790	return rc;
791
792	return VINF_SUCCESS;
793	}
794
795
796	/**
797	* @interface_method_impl{PDMPCIBUSREG,pfnIORegionRegisterR3}
798	*/
799	DECLCALLBACK(int) devpciR3CommonIORegionRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iRegion, RTGCPHYS cbRegion,
800	PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
801	{
802	NOREF(pDevIns);
803
804	/*
805	* Validate.
806	*/
807	AssertMsgReturn( enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR32)
808	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR32)
809	\|\| enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR64)
810	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR64)
811	\|\| enmType == PCI_ADDRESS_SPACE_IO
812	,
813	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
814	VERR_INVALID_PARAMETER);
815	AssertMsgReturn((unsigned)iRegion < VBOX_PCI_NUM_REGIONS,
816	("Invalid iRegion=%d VBOX_PCI_NUM_REGIONS=%d\n", iRegion, VBOX_PCI_NUM_REGIONS),
817	VERR_INVALID_PARAMETER);
818	int iLastSet = ASMBitLastSetU64(cbRegion);
819	AssertMsgReturn( iLastSet != 0
820	&& RT_BIT_64(iLastSet - 1) == cbRegion,
821	("Invalid cbRegion=%RGp iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
822	VERR_INVALID_PARAMETER);
823
824	LogFunc(("%s region %d size %RGp type %x\n", pPciDev->pszNameR3, iRegion, cbRegion, enmType));
825
826	/* Make sure that we haven't marked this region as continuation of 64-bit region. */
827	Assert(pPciDev->Int.s.aIORegions[iRegion].type != 0xff);
828
829	/*
830	* Register the I/O region.
831	*/
832	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
833	pRegion->addr = INVALID_PCI_ADDRESS;
834	pRegion->size = cbRegion;
835	pRegion->type = enmType;
836	pRegion->map_func = pfnCallback;
837
838	if ((enmType & PCI_ADDRESS_SPACE_BAR64) != 0)
839	{
840	/* VBOX_PCI_BASE_ADDRESS_5 and VBOX_PCI_ROM_ADDRESS are excluded. */
841	AssertMsgReturn(iRegion < VBOX_PCI_NUM_REGIONS - 2,
842	("Region %d cannot be 64-bit\n", iRegion),
843	VERR_INVALID_PARAMETER);
844	/* Mark next region as continuation of this one. */
845	pPciDev->Int.s.aIORegions[iRegion + 1].type = 0xff;
846	}
847
848	/* Set type in the PCI config space. */
849	AssertCompile(PCI_ADDRESS_SPACE_MEM == 0);
850	AssertCompile(PCI_ADDRESS_SPACE_IO == 1);
851	AssertCompile(PCI_ADDRESS_SPACE_BAR64 == RT_BIT_32(2));
852	AssertCompile(PCI_ADDRESS_SPACE_MEM_PREFETCH == RT_BIT_32(3));
853	uint32_t u32Value = (uint32_t)enmType & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH);
854	/* safe, only needs to go to the config space array */
855	PDMPciDevSetDWord(pPciDev, devpciGetRegionReg(iRegion), u32Value);
856
857	return VINF_SUCCESS;
858	}
859
860
861	/**
862	* @interface_method_impl{PDMPCIBUSREG,pfnSetConfigCallbacksR3}
863	*/
864	DECLCALLBACK(void) devpciR3CommonSetConfigCallbacks(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
865	PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
866	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
867	{
868	NOREF(pDevIns);
869
870	if (ppfnReadOld)
871	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
872	pPciDev->Int.s.pfnConfigRead = pfnRead;
873
874	if (ppfnWriteOld)
875	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
876	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
877	}
878
879
880	static int ich9pciR3CommonSaveExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM)
881	{
882	/*
883	* Iterate thru all the devices.
884	*/
885	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
886	{
887	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
888	if (pDev)
889	{
890	/* Device position */
891	SSMR3PutU32(pSSM, uDevFn);
892	/* PCI config registers */
893	SSMR3PutMem(pSSM, pDev->abConfig, sizeof(pDev->abConfig));
894
895	/* Device flags */
896	int rc = SSMR3PutU32(pSSM, pDev->Int.s.fFlags);
897	if (RT_FAILURE(rc))
898	return rc;
899
900	/* IRQ pin state */
901	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
902	if (RT_FAILURE(rc))
903	return rc;
904
905	/* MSI info */
906	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
907	if (RT_FAILURE(rc))
908	return rc;
909	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
910	if (RT_FAILURE(rc))
911	return rc;
912
913	/* MSI-X info */
914	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
915	if (RT_FAILURE(rc))
916	return rc;
917	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
918	if (RT_FAILURE(rc))
919	return rc;
920
921	/* Save MSI-X page state */
922	if (pDev->Int.s.u8MsixCapOffset != 0)
923	{
924	Assert(pDev->Int.s.pMsixPageR3 != NULL);
925	SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
926	if (RT_FAILURE(rc))
927	return rc;
928	}
929
930	/* Save the type an size of all the regions. */
931	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
932	{
933	SSMR3PutU8(pSSM, pDev->Int.s.aIORegions[iRegion].type);
934	rc = SSMR3PutU64(pSSM, pDev->Int.s.aIORegions[iRegion].size);
935	AssertRCReturn(rc, rc);
936	}
937	}
938	}
939	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
940	}
941
942	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
943	{
944	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
945
946	/*
947	* Bus state data.
948	*/
949	SSMR3PutU32(pSSM, pThis->uConfigReg);
950
951	/*
952	* Save IRQ states.
953	*/
954	for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
955	SSMR3PutU32(pSSM, pThis->auPciApicIrqLevels[i]);
956
957	SSMR3PutU32(pSSM, UINT32_MAX); /* separator */
958
959	return ich9pciR3CommonSaveExec(&pThis->PciBus, pSSM);
960	}
961
962
963	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
964	{
965	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
966	return ich9pciR3CommonSaveExec(pThis, pSSM);
967	}
968
969
970	static DECLCALLBACK(void) ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t uBus, uint8_t uDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
971	{
972	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
973
974	LogFlowFunc(("pDevIns=%p uBus=%d uDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, uBus, uDevice, u32Address, u32Value, cb));
975
976	/* If the current bus is not the target bus search for the bus which contains the device. */
977	/* safe, only needs to go to the config space array */
978	if (uBus != PDMPciDevGetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS))
979	{
980	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(pBus, uBus);
981	if (pBridgeDevice)
982	{
983	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
984	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), uBus, uDevice,
985	u32Address, u32Value, cb);
986	}
987	}
988	else
989	{
990	/* This is the target bus, pass the write to the device. */
991	PPDMPCIDEV pPciDev = pBus->apDevices[uDevice];
992	if (pPciDev)
993	{
994	LogFunc(("%s: addr=%02x val=%08x len=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
995	/** @todo return rc */
996	pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, u32Value, cb);
997	}
998	}
999	}
1000
1001	static DECLCALLBACK(uint32_t) ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t uBus, uint8_t uDevice, uint32_t u32Address, unsigned cb)
1002	{
1003	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1004	uint32_t u32Value;
1005
1006	LogFlowFunc(("pDevIns=%p uBus=%d uDevice=%d u32Address=%u cb=%d\n", pDevIns, uBus, uDevice, u32Address, cb));
1007
1008	/* If the current bus is not the target bus search for the bus which contains the device. */
1009	/* safe, only needs to go to the config space array */
1010	if (uBus != PDMPciDevGetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS))
1011	{
1012	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(pBus, uBus);
1013	if (pBridgeDevice)
1014	{
1015	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1016	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), uBus, uDevice,
1017	u32Address, cb);
1018	}
1019	else
1020	u32Value = 0xffffffff;
1021	}
1022	else
1023	{
1024	/* This is the target bus, pass the read to the device. */
1025	PPDMPCIDEV pPciDev = pBus->apDevices[uDevice];
1026	if (pPciDev)
1027	{
1028	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb);
1029	LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
1030	}
1031	else
1032	u32Value = 0xffffffff;
1033	}
1034
1035	return u32Value;
1036	}
1037
1038
1039
1040	/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
1041
1042
1043	/**
1044	* Common routine for restoring the config registers of a PCI device.
1045	*
1046	* @param pDev The PCI device.
1047	* @param pbSrcConfig The configuration register values to be loaded.
1048	*/
1049	void devpciR3CommonRestoreConfig(PPDMPCIDEV pDev, uint8_t const *pbSrcConfig)
1050	{
1051	/*
1052	* This table defines the fields for normal devices and bridge devices, and
1053	* the order in which they need to be restored.
1054	*/
1055	static const struct PciField
1056	{
1057	uint8_t off;
1058	uint8_t cb;
1059	uint8_t fWritable;
1060	uint8_t fBridge;
1061	const char *pszName;
1062	} s_aFields[] =
1063	{
1064	/* off,cb,fW,fB, pszName */
1065	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1066	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1067	{ 0x06, 2, 1, 3, "STATUS" },
1068	{ 0x08, 1, 0, 3, "REVISION_ID" },
1069	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1070	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1071	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1072	{ 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },
1073	{ 0x0d, 1, 1, 3, "LATENCY_TIMER" },
1074	{ 0x0e, 1, 0, 3, "HEADER_TYPE" },
1075	{ 0x0f, 1, 1, 3, "BIST" },
1076	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1077	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1078	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1079	{ 0x18, 1, 1, 2, "PRIMARY_BUS" },
1080	{ 0x19, 1, 1, 2, "SECONDARY_BUS" },
1081	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" },
1082	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" },
1083	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1084	{ 0x1c, 1, 1, 2, "IO_BASE" },
1085	{ 0x1d, 1, 1, 2, "IO_LIMIT" },
1086	{ 0x1e, 2, 1, 2, "SEC_STATUS" },
1087	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1088	{ 0x20, 2, 1, 2, "MEMORY_BASE" },
1089	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" },
1090	{ 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1091	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" },
1092	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" },
1093	{ 0x28, 4, 0, 1, "CARDBUS_CIS" },
1094	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" },
1095	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },
1096	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },
1097	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" },
1098	{ 0x30, 4, 1, 1, "ROM_ADDRESS" },
1099	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" },
1100	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" },
1101	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" },
1102	{ 0x38, 4, 1, 1, "RESERVED_38" },
1103	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" },
1104	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" },
1105	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" },
1106	{ 0x3e, 1, 0, 1, "MIN_GNT" },
1107	{ 0x3e, 2, 1, 2, "BRIDGE_CONTROL" },
1108	{ 0x3f, 1, 0, 1, "MAX_LAT" },
1109	/* The COMMAND register must come last as it requires the ADDRESS
1110	registers to be restored before we pretent to change it from 0 to
1111	whatever value the guest assigned it. */
1112	{ 0x04, 2, 1, 3, "COMMAND" },
1113	};
1114
1115	#ifdef RT_STRICT
1116	/* Check that we've got full register coverage. */
1117	uint32_t bmDevice[0x40 / 32];
1118	uint32_t bmBridge[0x40 / 32];
1119	RT_ZERO(bmDevice);
1120	RT_ZERO(bmBridge);
1121	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1122	{
1123	uint8_t off = s_aFields[i].off;
1124	uint8_t cb = s_aFields[i].cb;
1125	uint8_t f = s_aFields[i].fBridge;
1126	while (cb-- > 0)
1127	{
1128	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1129	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1130	if (f & 1) ASMBitSet(bmDevice, off);
1131	if (f & 2) ASMBitSet(bmBridge, off);
1132	off++;
1133	}
1134	}
1135	for (uint32_t off = 0; off < 0x40; off++)
1136	{
1137	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1138	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1139	}
1140	#endif
1141
1142	/*
1143	* Loop thru the fields covering the 64 bytes of standard registers.
1144	*/
1145	uint8_t const fBridge = pciDevIsPci2PciBridge(pDev) ? 2 : 1;
1146	Assert(!pciDevIsPassthrough(pDev));
1147	uint8_t *pbDstConfig = &pDev->abConfig[0];
1148
1149	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1150	if (s_aFields[i].fBridge & fBridge)
1151	{
1152	uint8_t const off = s_aFields[i].off;
1153	uint8_t const cb = s_aFields[i].cb;
1154	uint32_t u32Src;
1155	uint32_t u32Dst;
1156	switch (cb)
1157	{
1158	case 1:
1159	u32Src = pbSrcConfig[off];
1160	u32Dst = pbDstConfig[off];
1161	break;
1162	case 2:
1163	u32Src = (uint16_t const )&pbSrcConfig[off];
1164	u32Dst = (uint16_t const )&pbDstConfig[off];
1165	break;
1166	case 4:
1167	u32Src = (uint32_t const )&pbSrcConfig[off];
1168	u32Dst = (uint32_t const )&pbDstConfig[off];
1169	break;
1170	default:
1171	AssertFailed();
1172	continue;
1173	}
1174
1175	if ( u32Src != u32Dst
1176	\|\| off == VBOX_PCI_COMMAND)
1177	{
1178	if (u32Src != u32Dst)
1179	{
1180	if (!s_aFields[i].fWritable)
1181	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1182	pDev->pszNameR3, pDev->Int.s.CTX_SUFF(pDevIns)->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1183	else
1184	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1185	pDev->pszNameR3, pDev->Int.s.CTX_SUFF(pDevIns)->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1186	}
1187	if (off == VBOX_PCI_COMMAND)
1188	/* safe, only needs to go to the config space array */
1189	PDMPciDevSetCommand(pDev, 0); /* For remapping, see pciR3CommonLoadExec/ich9pciR3CommonLoadExec. */
1190	pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, off, u32Src, cb);
1191	}
1192	}
1193
1194	/*
1195	* The device dependent registers.
1196	*
1197	* We will not use ConfigWrite here as we have no clue about the size
1198	* of the registers, so the device is responsible for correctly
1199	* restoring functionality governed by these registers.
1200	*/
1201	for (uint32_t off = 0x40; off < sizeof(pDev->abConfig); off++)
1202	if (pbDstConfig[off] != pbSrcConfig[off])
1203	{
1204	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1205	pDev->pszNameR3, pDev->Int.s.CTX_SUFF(pDevIns)->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1206	pbDstConfig[off] = pbSrcConfig[off];
1207	}
1208	}
1209
1210
1211	/**
1212	* @callback_method_impl{FNPCIIOREGIONOLDSETTER}
1213	*/
1214	static DECLCALLBACK(int) devpciR3CommonRestoreOldSetRegion(PPDMPCIDEV pPciDev, uint32_t iRegion,
1215	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType)
1216	{
1217	AssertLogRelReturn(iRegion < RT_ELEMENTS(pPciDev->Int.s.aIORegions), VERR_INVALID_PARAMETER);
1218	pPciDev->Int.s.aIORegions[iRegion].type = enmType;
1219	pPciDev->Int.s.aIORegions[iRegion].size = cbRegion;
1220	return VINF_SUCCESS;
1221	}
1222
1223
1224	/**
1225	* Checks for and deals with changes in resource sizes and types.
1226	*
1227	* @returns VBox status code.
1228	* @param pSSM The Saved state handle.
1229	* @param pPciDev The PCI device in question.
1230	* @param paIoRegions I/O regions with the size and type fields from
1231	* the saved state.
1232	* @param fNewState Set if this is a new state with I/O region sizes
1233	* and types, clear if old one.
1234	*/
1235	int devpciR3CommonRestoreRegions(PSSMHANDLE pSSM, PPDMPCIDEV pPciDev, PPCIIOREGION paIoRegions, bool fNewState)
1236	{
1237	int rc;
1238	if (fNewState)
1239	{
1240	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
1241	{
1242	if ( pPciDev->Int.s.aIORegions[iRegion].type != paIoRegions[iRegion].type
1243	\|\| pPciDev->Int.s.aIORegions[iRegion].size != paIoRegions[iRegion].size)
1244	{
1245	AssertLogRelMsgFailed(("PCI: %8s/%u: region #%u size/type load change: %#RGp/%#x -> %#RGp/%#x\n",
1246	pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, iRegion,
1247	pPciDev->Int.s.aIORegions[iRegion].size, pPciDev->Int.s.aIORegions[iRegion].type,
1248	paIoRegions[iRegion].size, paIoRegions[iRegion].type));
1249	if (pPciDev->pfnRegionLoadChangeHookR3)
1250	{
1251	rc = pPciDev->pfnRegionLoadChangeHookR3(pPciDev->Int.s.pDevInsR3, pPciDev, iRegion, paIoRegions[iRegion].size,
1252	(PCIADDRESSSPACE)paIoRegions[iRegion].type, NULL /pfnOldSetter/);
1253	if (RT_FAILURE(rc))
1254	return SSMR3SetLoadError(pSSM, rc, RT_SRC_POS,
1255	N_("Device %s/%u failed to respond to region #%u size/type changing from %#RGp/%#x to %#RGp/%#x: %Rrc"),
1256	pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, iRegion,
1257	pPciDev->Int.s.aIORegions[iRegion].size, pPciDev->Int.s.aIORegions[iRegion].type,
1258	paIoRegions[iRegion].size, paIoRegions[iRegion].type, rc);
1259	}
1260	pPciDev->Int.s.aIORegions[iRegion].type = paIoRegions[iRegion].type;
1261	pPciDev->Int.s.aIORegions[iRegion].size = paIoRegions[iRegion].size;
1262	}
1263	}
1264	}
1265	/* Old saved state without sizes and types. Do a special hook call to give
1266	devices with changes a chance to adjust resources back to old values. */
1267	else if (pPciDev->pfnRegionLoadChangeHookR3)
1268	{
1269	rc = pPciDev->pfnRegionLoadChangeHookR3(pPciDev->Int.s.pDevInsR3, pPciDev, UINT32_MAX, RTGCPHYS_MAX, (PCIADDRESSSPACE)-1,
1270	devpciR3CommonRestoreOldSetRegion);
1271	if (RT_FAILURE(rc))
1272	return SSMR3SetLoadError(pSSM, rc, RT_SRC_POS, N_("Device %s/%u failed to resize its resources: %Rrc"),
1273	pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, rc);
1274	}
1275	return VINF_SUCCESS;
1276	}
1277
1278
1279	/**
1280	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1281	*
1282	* @returns VBox status code.
1283	* @param pBus The bus which data is being loaded.
1284	* @param pSSM The saved state handle.
1285	* @param uVersion The data version.
1286	* @param uPass The pass.
1287	*/
1288	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1289	{
1290	uint32_t u32;
1291	int rc;
1292
1293	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1294	if ( uVersion < VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
1295	\|\| uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION)
1296	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1297
1298	/*
1299	* Iterate thru all the devices and write 0 to the COMMAND register so
1300	* that all the memory is unmapped before we start restoring the saved
1301	* mapping locations.
1302	*
1303	* The register value is restored afterwards so we can do proper
1304	* LogRels in devpciR3CommonRestoreConfig.
1305	*/
1306	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1307	{
1308	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1309	if (pDev)
1310	{
1311	/* safe, only needs to go to the config space array */
1312	uint16_t u16 = PDMPciDevGetCommand(pDev);
1313	pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, VBOX_PCI_COMMAND, 0, 2);
1314	/* safe, only needs to go to the config space array */
1315	PDMPciDevSetCommand(pDev, u16);
1316	/* safe, only needs to go to the config space array */
1317	Assert(PDMPciDevGetCommand(pDev) == u16);
1318	}
1319	}
1320
1321	void *pvMsixPage = RTMemTmpAllocZ(0x1000);
1322	AssertReturn(pvMsixPage, VERR_NO_TMP_MEMORY);
1323
1324	/*
1325	* Iterate all the devices.
1326	*/
1327	for (uint32_t uDevFn = 0;; uDevFn++)
1328	{
1329	/* index / terminator */
1330	rc = SSMR3GetU32(pSSM, &u32);
1331	if (RT_FAILURE(rc))
1332	break;
1333	if (u32 == (uint32_t)~0)
1334	break;
1335	AssertMsgBreak(u32 < RT_ELEMENTS(pBus->apDevices) && u32 >= uDevFn, ("u32=%#x uDevFn=%#x\n", u32, uDevFn));
1336
1337	/* skip forward to the device checking that no new devices are present. */
1338	PPDMPCIDEV pDev;
1339	for (; uDevFn < u32; uDevFn++)
1340	{
1341	pDev = pBus->apDevices[uDevFn];
1342	if (pDev)
1343	{
1344	/* safe, only needs to go to the config space array */
1345	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", uDevFn, pDev->pszNameR3,
1346	PDMPciDevGetVendorId(pDev), PDMPciDevGetDeviceId(pDev)));
1347	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1348	{
1349	/* safe, only needs to go to the config space array */
1350	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1351	uDevFn, pDev->pszNameR3, PDMPciDevGetVendorId(pDev), PDMPciDevGetDeviceId(pDev));
1352	break;
1353	}
1354	}
1355	}
1356	if (RT_FAILURE(rc))
1357	break;
1358
1359	/* get the data */
1360	PDMPCIDEV DevTmp;
1361	RT_ZERO(DevTmp);
1362	DevTmp.Int.s.fFlags = 0;
1363	DevTmp.Int.s.u8MsiCapOffset = 0;
1364	DevTmp.Int.s.u8MsiCapSize = 0;
1365	DevTmp.Int.s.u8MsixCapOffset = 0;
1366	DevTmp.Int.s.u8MsixCapSize = 0;
1367	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1368	SSMR3GetMem(pSSM, DevTmp.abConfig, sizeof(DevTmp.abConfig));
1369
1370	SSMR3GetU32(pSSM, &DevTmp.Int.s.fFlags);
1371	SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1372	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1373	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1374	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1375	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1376	if (RT_FAILURE(rc))
1377	break;
1378
1379	/* Load MSI-X page state */
1380	if (DevTmp.Int.s.u8MsixCapOffset != 0)
1381	{
1382	Assert(pvMsixPage != NULL);
1383	rc = SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1384	if (RT_FAILURE(rc))
1385	break;
1386	}
1387
1388	/* Load the region types and sizes. */
1389	if (uVersion >= VBOX_ICH9PCI_SAVED_STATE_VERSION_REGION_SIZES)
1390	{
1391	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
1392	{
1393	SSMR3GetU8(pSSM, &DevTmp.Int.s.aIORegions[iRegion].type);
1394	rc = SSMR3GetU64(pSSM, &DevTmp.Int.s.aIORegions[iRegion].size);
1395	AssertLogRelRCReturn(rc, rc);
1396	}
1397	}
1398
1399	/*
1400	* Check that it's still around.
1401	*/
1402	pDev = pBus->apDevices[uDevFn];
1403	if (!pDev)
1404	{
1405	/* safe, only needs to go to the config space array */
1406	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", uDevFn,
1407	PDMPciDevGetVendorId(&DevTmp), PDMPciDevGetDeviceId(&DevTmp)));
1408	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1409	{
1410	/* safe, only needs to go to the config space array */
1411	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1412	uDevFn, PDMPciDevGetVendorId(&DevTmp), PDMPciDevGetDeviceId(&DevTmp));
1413	break;
1414	}
1415	continue;
1416	}
1417
1418	/* match the vendor id assuming that this will never be changed. */
1419	/* safe, only needs to go to the config space array */
1420	if (PDMPciDevGetVendorId(&DevTmp) != PDMPciDevGetVendorId(pDev))
1421	{
1422	/* safe, only needs to go to the config space array */
1423	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1424	uDevFn, pDev->pszNameR3, PDMPciDevGetVendorId(&DevTmp), PDMPciDevGetVendorId(pDev));
1425	break;
1426	}
1427
1428	/* commit the loaded device config. */
1429	rc = devpciR3CommonRestoreRegions(pSSM, pDev, DevTmp.Int.s.aIORegions,
1430	uVersion >= VBOX_ICH9PCI_SAVED_STATE_VERSION_REGION_SIZES);
1431	if (RT_FAILURE(rc))
1432	break;
1433	Assert(!pciDevIsPassthrough(pDev));
1434	devpciR3CommonRestoreConfig(pDev, &DevTmp.abConfig[0]);
1435
1436	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1437	pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1438	pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1439	pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1440	pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1441	if (DevTmp.Int.s.u8MsixCapSize != 0)
1442	{
1443	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1444	Assert(pDev->Int.s.cbMsixRegion != 0);
1445	memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, pDev->Int.s.cbMsixRegion);
1446	}
1447	}
1448
1449	RTMemTmpFree(pvMsixPage);
1450
1451	return rc;
1452	}
1453
1454	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1455	{
1456	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1457	PDEVPCIBUS pBus = &pThis->PciBus;
1458	uint32_t u32;
1459	int rc;
1460
1461	/* We ignore this version as there's no saved state with it anyway */
1462	if (uVersion <= VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1463	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1464	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION)
1465	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1466
1467	/*
1468	* Bus state data.
1469	*/
1470	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1471
1472	/*
1473	* Load IRQ states.
1474	*/
1475	for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
1476	SSMR3GetU32(pSSM, (uint32_t*)&pThis->auPciApicIrqLevels[i]);
1477
1478	/* separator */
1479	rc = SSMR3GetU32(pSSM, &u32);
1480	if (RT_FAILURE(rc))
1481	return rc;
1482	if (u32 != (uint32_t)~0)
1483	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1484
1485	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1486	}
1487
1488	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1489	{
1490	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1491	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1492	}
1493
1494
1495
1496	/* -=-=-=-=-=- Fake PCI BIOS Init -=-=-=-=-=- */
1497
1498
1499	void devpciR3BiosInitSetRegionAddress(PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, int iRegion, uint64_t addr)
1500	{
1501	NOREF(pBus);
1502	uint32_t uReg = devpciGetRegionReg(iRegion);
1503
1504	/* Read memory type first. */
1505	uint8_t uResourceType = devpciR3GetByte(pPciDev, uReg);
1506	bool f64Bit = (uResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
1507	== PCI_ADDRESS_SPACE_BAR64;
1508
1509	Log(("Set region address: %02x:%02x.%d region %d address=%RX64%s\n",
1510	pBus->iBus, pPciDev->uDevFn >> 3, pPciDev->uDevFn & 7, iRegion, addr, f64Bit ? " (64-bit)" : ""));
1511
1512	/* Write address of the device. */
1513	devpciR3SetDWord(pPciDev, uReg, (uint32_t)addr);
1514	if (f64Bit)
1515	devpciR3SetDWord(pPciDev, uReg + 4, (uint32_t)(addr >> 32));
1516	}
1517
1518
1519	static void ich9pciBiosInitBridge(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus)
1520	{
1521	PPDMPCIDEV pBridge = &pBus->PciDev;
1522	Log(("BIOS init bridge: %02x:%02x.%d\n", pBus->iBus, pBridge->uDevFn >> 3, pBridge->uDevFn & 7));
1523
1524	/*
1525	* The I/O range for the bridge must be aligned to a 4KB boundary.
1526	* This does not change anything really as the access to the device is not going
1527	* through the bridge but we want to be compliant to the spec.
1528	*/
1529	if ((pPciRoot->uPciBiosIo % _4K) != 0)
1530	{
1531	pPciRoot->uPciBiosIo = RT_ALIGN_32(pPciRoot->uPciBiosIo, _4K);
1532	LogFunc(("Aligned I/O start address. New address %#x\n", pPciRoot->uPciBiosIo));
1533	}
1534	devpciR3SetByte(pBridge, VBOX_PCI_IO_BASE, (pPciRoot->uPciBiosIo >> 8) & 0xf0);
1535
1536	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1537	if ((pPciRoot->uPciBiosMmio % _1M) != 0)
1538	{
1539	pPciRoot->uPciBiosMmio = RT_ALIGN_32(pPciRoot->uPciBiosMmio, _1M);
1540	LogFunc(("Aligned MMIO start address. New address %#x\n", pPciRoot->uPciBiosMmio));
1541	}
1542	devpciR3SetWord(pBridge, VBOX_PCI_MEMORY_BASE, (pPciRoot->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
1543
1544	/* Save values to compare later to. */
1545	uint32_t u32IoAddressBase = pPciRoot->uPciBiosIo;
1546	uint32_t u32MMIOAddressBase = pPciRoot->uPciBiosMmio;
1547
1548	/* Init all devices behind the bridge (recursing to further buses). */
1549	ich9pciBiosInitAllDevicesOnBus(pPciRoot, pBus);
1550
1551	/*
1552	* Set I/O limit register. If there is no device with I/O space behind the
1553	* bridge we set a lower value than in the base register.
1554	*/
1555	if (u32IoAddressBase != pPciRoot->uPciBiosIo)
1556	{
1557	/* Need again alignment to a 4KB boundary. */
1558	pPciRoot->uPciBiosIo = RT_ALIGN_32(pPciRoot->uPciBiosIo, _4K);
1559	devpciR3SetByte(pBridge, VBOX_PCI_IO_LIMIT, ((pPciRoot->uPciBiosIo - 1) >> 8) & 0xf0);
1560	}
1561	else
1562	{
1563	devpciR3SetByte(pBridge, VBOX_PCI_IO_BASE, 0xf0);
1564	devpciR3SetByte(pBridge, VBOX_PCI_IO_LIMIT, 0x00);
1565	}
1566
1567	/* Same with the MMIO limit register but with 1MB boundary here. */
1568	if (u32MMIOAddressBase != pPciRoot->uPciBiosMmio)
1569	{
1570	pPciRoot->uPciBiosMmio = RT_ALIGN_32(pPciRoot->uPciBiosMmio, _1M);
1571	devpciR3SetWord(pBridge, VBOX_PCI_MEMORY_LIMIT, ((pPciRoot->uPciBiosMmio - 1) >> 16) & UINT32_C(0xfff0));
1572	}
1573	else
1574	{
1575	devpciR3SetWord(pBridge, VBOX_PCI_MEMORY_BASE, 0xfff0);
1576	devpciR3SetWord(pBridge, VBOX_PCI_MEMORY_LIMIT, 0x0000);
1577	}
1578
1579	/*
1580	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1581	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1582	* the base register than in the limit register.
1583	*/
1584	devpciR3SetWord(pBridge, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
1585	devpciR3SetWord(pBridge, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0000);
1586	devpciR3SetDWord(pBridge, VBOX_PCI_PREF_BASE_UPPER32, 0x00000000);
1587	devpciR3SetDWord(pBridge, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00000000);
1588	}
1589
1590	static int ich9pciBiosInitDeviceGetRegions(PPDMPCIDEV pPciDev)
1591	{
1592	uint8_t uHeaderType = devpciR3GetByte(pPciDev, VBOX_PCI_HEADER_TYPE) & 0x7f;
1593	if (uHeaderType == 0x00)
1594	/* Ignore ROM region here, which is included in VBOX_PCI_NUM_REGIONS. */
1595	return VBOX_PCI_NUM_REGIONS - 1;
1596	else if (uHeaderType == 0x01)
1597	/* PCI bridges have 2 BARs. */
1598	return 2;
1599	else
1600	{
1601	AssertMsgFailed(("invalid header type %#x\n", uHeaderType));
1602	return 0;
1603	}
1604	}
1605
1606	static void ich9pciBiosInitDeviceBARs(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev)
1607	{
1608	int cRegions = ich9pciBiosInitDeviceGetRegions(pPciDev);
1609	bool fSuppressMem = false;
1610	bool fActiveMemRegion = false;
1611	bool fActiveIORegion = false;
1612	for (int iRegion = 0; iRegion < cRegions; iRegion++)
1613	{
1614	uint32_t u32Address = devpciGetRegionReg(iRegion);
1615
1616	/* Calculate size - we write all 1s into the BAR, and then evaluate which bits
1617	are cleared. */
1618	uint8_t u8ResourceType = devpciR3GetByte(pPciDev, u32Address);
1619
1620	bool fPrefetch = (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_IO)))
1621	== PCI_ADDRESS_SPACE_MEM_PREFETCH;
1622	bool f64Bit = (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
1623	== PCI_ADDRESS_SPACE_BAR64;
1624	bool fIsPio = ((u8ResourceType & PCI_ADDRESS_SPACE_IO) == PCI_ADDRESS_SPACE_IO);
1625	uint64_t cbRegSize64 = 0;
1626
1627	/* Hack: initialize prefetchable BARs for devices on the root bus
1628	* early, but for all other prefetchable BARs do it after the
1629	* non-prefetchable BARs are initialized on all buses. */
1630	if (fPrefetch && pBus->iBus != 0)
1631	{
1632	fSuppressMem = true;
1633	if (f64Bit)
1634	iRegion++; /* skip next region */
1635	continue;
1636	}
1637
1638	if (f64Bit)
1639	{
1640	devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0xffffffff));
1641	devpciR3SetDWord(pPciDev, u32Address+4, UINT32_C(0xffffffff));
1642	cbRegSize64 = RT_MAKE_U64(devpciR3GetDWord(pPciDev, u32Address),
1643	devpciR3GetDWord(pPciDev, u32Address+4));
1644	cbRegSize64 &= ~UINT64_C(0x0f);
1645	cbRegSize64 = (~cbRegSize64) + 1;
1646
1647	/* No 64-bit PIO regions possible. */
1648	#ifndef DEBUG_bird /* EFI triggers this for DevAHCI. */
1649	AssertMsg((u8ResourceType & PCI_ADDRESS_SPACE_IO) == 0, ("type=%#x rgn=%d\n", u8ResourceType, iRegion));
1650	#endif
1651	}
1652	else
1653	{
1654	uint32_t cbRegSize32;
1655	devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0xffffffff));
1656	cbRegSize32 = devpciR3GetDWord(pPciDev, u32Address);
1657
1658	/* Clear resource information depending on resource type. */
1659	if (fIsPio) /* PIO */
1660	cbRegSize32 &= ~UINT32_C(0x01);
1661	else /* MMIO */
1662	cbRegSize32 &= ~UINT32_C(0x0f);
1663
1664	/*
1665	* Invert all bits and add 1 to get size of the region.
1666	* (From PCI implementation note)
1667	*/
1668	if (fIsPio && (cbRegSize32 & UINT32_C(0xffff0000)) == 0)
1669	cbRegSize32 = (~(cbRegSize32 \| UINT32_C(0xffff0000))) + 1;
1670	else
1671	cbRegSize32 = (~cbRegSize32) + 1;
1672
1673	cbRegSize64 = cbRegSize32;
1674	}
1675	Log2Func(("Size of region %u for device %d on bus %d is %lld\n", iRegion, pPciDev->uDevFn, pBus->iBus, cbRegSize64));
1676
1677	if (cbRegSize64)
1678	{
1679	/* Try 32-bit base first. */
1680	uint32_t* paddr = fIsPio ? &pPciRoot->uPciBiosIo : &pPciRoot->uPciBiosMmio;
1681	uint64_t uNew = *paddr;
1682	/* Align starting address to region size. */
1683	uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
1684	if (fIsPio)
1685	uNew &= UINT32_C(0xffff);
1686	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
1687	if ( !uNew
1688	\|\| (uNew <= UINT32_C(0xffffffff) && uNew + cbRegSize64 - 1 >= UINT32_C(0xfec00000))
1689	\|\| uNew >= _4G)
1690	{
1691	/* Only prefetchable regions can be placed above 4GB, as the
1692	* address decoder for non-prefetchable addresses in bridges
1693	* is limited to 32 bits. */
1694	if (f64Bit && fPrefetch)
1695	{
1696	/* Map a 64-bit region above 4GB. */
1697	Assert(!fIsPio);
1698	uNew = pPciRoot->uPciBiosMmio64;
1699	/* Align starting address to region size. */
1700	uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
1701	LogFunc(("Start address of 64-bit MMIO region %u/%u is %#llx\n", iRegion, iRegion + 1, uNew));
1702	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, iRegion, uNew);
1703	fActiveMemRegion = true;
1704	pPciRoot->uPciBiosMmio64 = uNew + cbRegSize64;
1705	Log2Func(("New 64-bit address is %#llx\n", pPciRoot->uPciBiosMmio64));
1706	}
1707	else
1708	{
1709	uint16_t uVendor = devpciR3GetWord(pPciDev, VBOX_PCI_VENDOR_ID);
1710	uint16_t uDevice = devpciR3GetWord(pPciDev, VBOX_PCI_DEVICE_ID);
1711	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
1712	iRegion, pBus->iBus, pPciDev->uDevFn >> 3, pPciDev->uDevFn & 7, uVendor, uDevice)); /** @todo make this a VM start failure later. */
1713	/* Undo the mapping mess caused by the size probing. */
1714	devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0));
1715	}
1716	}
1717	else
1718	{
1719	LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), iRegion, uNew));
1720	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, iRegion, uNew);
1721	if (fIsPio)
1722	fActiveIORegion = true;
1723	else
1724	fActiveMemRegion = true;
1725	*paddr = uNew + cbRegSize64;
1726	Log2Func(("New 32-bit address is %#x\n", *paddr));
1727	}
1728
1729	if (f64Bit)
1730	iRegion++; /* skip next region */
1731	}
1732	}
1733
1734	/* Update the command word appropriately. */
1735	uint16_t uCmd = devpciR3GetWord(pPciDev, VBOX_PCI_COMMAND);
1736	if (fActiveMemRegion && !fSuppressMem)
1737	uCmd \|= VBOX_PCI_COMMAND_MEMORY; /* Enable MMIO access. */
1738	if (fActiveIORegion)
1739	uCmd \|= VBOX_PCI_COMMAND_IO; /* Enable I/O space access. */
1740	devpciR3SetWord(pPciDev, VBOX_PCI_COMMAND, uCmd);
1741	}
1742
1743	static bool ich9pciBiosInitDevicePrefetchableBARs(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, bool fUse64Bit, bool fDryrun)
1744	{
1745	int cRegions = ich9pciBiosInitDeviceGetRegions(pPciDev);
1746	bool fActiveMemRegion = false;
1747	for (int iRegion = 0; iRegion < cRegions; iRegion++)
1748	{
1749	uint32_t u32Address = devpciGetRegionReg(iRegion);
1750	uint8_t u8ResourceType = devpciR3GetByte(pPciDev, u32Address);
1751	bool fPrefetch = (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_IO)))
1752	== PCI_ADDRESS_SPACE_MEM_PREFETCH;
1753	bool f64Bit = (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
1754	== PCI_ADDRESS_SPACE_BAR64;
1755	uint64_t cbRegSize64 = 0;
1756
1757	/* Everything besides prefetchable regions has been set up already. */
1758	if (!fPrefetch)
1759	continue;
1760
1761	if (f64Bit)
1762	{
1763	devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0xffffffff));
1764	devpciR3SetDWord(pPciDev, u32Address+4, UINT32_C(0xffffffff));
1765	cbRegSize64 = RT_MAKE_U64(devpciR3GetDWord(pPciDev, u32Address),
1766	devpciR3GetDWord(pPciDev, u32Address+4));
1767	cbRegSize64 &= ~UINT64_C(0x0f);
1768	cbRegSize64 = (~cbRegSize64) + 1;
1769	}
1770	else
1771	{
1772	uint32_t cbRegSize32;
1773	devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0xffffffff));
1774	cbRegSize32 = devpciR3GetDWord(pPciDev, u32Address);
1775	cbRegSize32 &= ~UINT32_C(0x0f);
1776	cbRegSize32 = (~cbRegSize32) + 1;
1777
1778	cbRegSize64 = cbRegSize32;
1779	}
1780	Log2Func(("Size of region %u for device %d on bus %d is %lld\n", iRegion, pPciDev->uDevFn, pBus->iBus, cbRegSize64));
1781
1782	if (cbRegSize64)
1783	{
1784	uint64_t uNew;
1785	if (!fUse64Bit)
1786	{
1787	uNew = pPciRoot->uPciBiosMmio;
1788	/* Align starting address to region size. */
1789	uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
1790	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. Okay for BIOS. */
1791	if ( !uNew
1792	\|\| (uNew <= UINT32_C(0xffffffff) && uNew + cbRegSize64 - 1 >= UINT32_C(0xfec00000))
1793	\|\| uNew >= _4G)
1794	{
1795	Log2Func(("region #%u: Rejecting address range: %#x LB %#RX64\n", iRegion, uNew, cbRegSize64));
1796	Assert(fDryrun);
1797	return true;
1798	}
1799	if (!fDryrun)
1800	{
1801	LogFunc(("Start address of MMIO region %u is %#x\n", iRegion, uNew));
1802	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, iRegion, uNew);
1803	fActiveMemRegion = true;
1804	}
1805	pPciRoot->uPciBiosMmio = uNew + cbRegSize64;
1806	}
1807	else
1808	{
1809	/* Can't handle 32-bit BARs when forcing 64-bit allocs. */
1810	if (!f64Bit)
1811	{
1812	Assert(fDryrun);
1813	return true;
1814	}
1815	uNew = pPciRoot->uPciBiosMmio64;
1816	/* Align starting address to region size. */
1817	uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
1818	pPciRoot->uPciBiosMmio64 = uNew + cbRegSize64;
1819	if (!fDryrun)
1820	{
1821	LogFunc(("Start address of 64-bit MMIO region %u/%u is %#llx\n", iRegion, iRegion + 1, uNew));
1822	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, iRegion, uNew);
1823	fActiveMemRegion = true;
1824	}
1825	}
1826
1827	if (f64Bit)
1828	iRegion++; /* skip next region */
1829	}
1830	}
1831
1832	if (!fDryrun)
1833	{
1834	/* Update the command word appropriately. */
1835	uint16_t uCmd = devpciR3GetWord(pPciDev, VBOX_PCI_COMMAND);
1836	if (fActiveMemRegion)
1837	uCmd \|= VBOX_PCI_COMMAND_MEMORY; /* Enable MMIO access. */
1838	devpciR3SetWord(pPciDev, VBOX_PCI_COMMAND, uCmd);
1839	}
1840	else
1841	Assert(!fActiveMemRegion);
1842
1843	return false;
1844	}
1845
1846	static bool ich9pciBiosInitBridgePrefetchable(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, bool fUse64Bit, bool fDryrun)
1847	{
1848	PPDMPCIDEV pBridge = &pBus->PciDev;
1849	Log(("BIOS init bridge (prefetch): %02x:%02x.%d use64bit=%d dryrun=%d\n", pBus->iBus, pBridge->uDevFn >> 3, pBridge->uDevFn & 7, fUse64Bit, fDryrun));
1850
1851	pPciRoot->uPciBiosMmio = RT_ALIGN_32(pPciRoot->uPciBiosMmio, _1M);
1852	pPciRoot->uPciBiosMmio64 = RT_ALIGN_64(pPciRoot->uPciBiosMmio64, _1M);
1853
1854	/* Save values to compare later to. */
1855	uint32_t u32MMIOAddressBase = pPciRoot->uPciBiosMmio;
1856	uint64_t u64MMIOAddressBase = pPciRoot->uPciBiosMmio64;
1857
1858	/* Init all devices behind the bridge (recursing to further buses). */
1859	bool fRes = ich9pciBiosInitAllDevicesPrefetchableOnBus(pPciRoot, pBus, fUse64Bit, fDryrun);
1860	if (fDryrun)
1861	return fRes;
1862	Assert(!fRes);
1863
1864	/* Set prefetchable MMIO limit register with 1MB boundary. */
1865	uint64_t uBase, uLimit;
1866	if (fUse64Bit)
1867	{
1868	if (u64MMIOAddressBase == pPciRoot->uPciBiosMmio64)
1869	return false;
1870	uBase = u64MMIOAddressBase;
1871	uLimit = RT_ALIGN_64(pPciRoot->uPciBiosMmio64, _1M) - 1;
1872	}
1873	else
1874	{
1875	if (u32MMIOAddressBase == pPciRoot->uPciBiosMmio)
1876	return false;
1877	uBase = u32MMIOAddressBase;
1878	uLimit = RT_ALIGN_32(pPciRoot->uPciBiosMmio, _1M) - 1;
1879	}
1880	devpciR3SetDWord(pBridge, VBOX_PCI_PREF_BASE_UPPER32, uBase >> 32);
1881	devpciR3SetWord(pBridge, VBOX_PCI_PREF_MEMORY_BASE, (uint32_t)(uBase >> 16) & UINT32_C(0xfff0));
1882	devpciR3SetDWord(pBridge, VBOX_PCI_PREF_LIMIT_UPPER32, uLimit >> 32);
1883	devpciR3SetWord(pBridge, VBOX_PCI_PREF_MEMORY_LIMIT, (uint32_t)(uLimit >> 16) & UINT32_C(0xfff0));
1884
1885	return false;
1886	}
1887
1888	static bool ich9pciBiosInitAllDevicesPrefetchableOnBus(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, bool fUse64Bit, bool fDryrun)
1889	{
1890	/* First pass: assign resources to all devices. */
1891	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1892	{
1893	PPDMPCIDEV pPciDev = pBus->apDevices[uDevFn];
1894
1895	/* check if device is present */
1896	if (!pPciDev)
1897	continue;
1898
1899	Log(("BIOS init device (prefetch): %02x:%02x.%d\n", pBus->iBus, uDevFn >> 3, uDevFn & 7));
1900
1901	/* prefetchable memory mappings */
1902	bool fRes = ich9pciBiosInitDevicePrefetchableBARs(pPciRoot, pBus, pPciDev, fUse64Bit, fDryrun);
1903	if (fRes)
1904	{
1905	Assert(fDryrun);
1906	return fRes;
1907	}
1908	}
1909
1910	/* Second pass: handle bridges recursively. */
1911	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1912	{
1913	PPDMPCIDEV pBridge = pBus->papBridgesR3[iBridge];
1914	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
1915	("Device is not a PCI bridge but on the list of PCI bridges\n"));
1916	PDEVPCIBUS pChildBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
1917
1918	bool fRes = ich9pciBiosInitBridgePrefetchable(pPciRoot, pChildBus, fUse64Bit, fDryrun);
1919	if (fRes)
1920	{
1921	Assert(fDryrun);
1922	return fRes;
1923	}
1924	}
1925	return false;
1926	}
1927
1928	static void ich9pciBiosInitAllDevicesOnBus(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus)
1929	{
1930	/* First pass: assign resources to all devices and map the interrupt. */
1931	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1932	{
1933	PPDMPCIDEV pPciDev = pBus->apDevices[uDevFn];
1934
1935	/* check if device is present */
1936	if (!pPciDev)
1937	continue;
1938
1939	Log(("BIOS init device: %02x:%02x.%d\n", pBus->iBus, uDevFn >> 3, uDevFn & 7));
1940
1941	/* default memory mappings */
1942	ich9pciBiosInitDeviceBARs(pPciRoot, pBus, pPciDev);
1943	uint16_t uDevClass = devpciR3GetWord(pPciDev, VBOX_PCI_CLASS_DEVICE);
1944	switch (uDevClass)
1945	{
1946	case 0x0101:
1947	/* IDE controller */
1948	devpciR3SetWord(pPciDev, 0x40, 0x8000); /* enable IDE0 */
1949	devpciR3SetWord(pPciDev, 0x42, 0x8000); /* enable IDE1 */
1950	break;
1951	case 0x0300:
1952	{
1953	/* VGA controller */
1954
1955	/* NB: Default Bochs VGA LFB address is 0xE0000000. Old guest
1956	* software may break if the framebuffer isn't mapped there.
1957	*/
1958
1959	/*
1960	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1961	* only the framebuffer (i.e., a memory region) is explicitly registered via
1962	* ich9pciSetRegionAddress, so don't forget to enable I/O decoding.
1963	*/
1964	uint16_t uCmd = devpciR3GetWord(pPciDev, VBOX_PCI_COMMAND);
1965	devpciR3SetWord(pPciDev, VBOX_PCI_COMMAND, uCmd \| VBOX_PCI_COMMAND_IO);
1966	break;
1967	}
1968	default:
1969	break;
1970	}
1971
1972	/* map the interrupt */
1973	uint8_t iPin = devpciR3GetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN);
1974	if (iPin != 0)
1975	{
1976	iPin--;
1977
1978	/* We need to go up to the host bus to see which irq pin this
1979	* device will use there. See logic in ich9pcibridgeSetIrq().
1980	*/
1981	for (PDEVPCIBUS pParent = pBus; pParent->iBus != 0; pParent = pParent->PciDev.Int.s.pBusR3)
1982	{
1983	/* Get the pin the device would assert on the bridge. */
1984	iPin = ((pParent->PciDev.uDevFn >> 3) + iPin) & 3;
1985	}
1986
1987	int iIrq = aPciIrqs[ich9pciSlotGetPirq(pBus->iBus, uDevFn, iPin)];
1988	Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
1989	iPin, iIrq, pBus->iBus, uDevFn>>3, uDevFn&7));
1990	devpciR3SetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE, iIrq);
1991	}
1992	}
1993
1994	/* Second pass: handle bridges recursively. */
1995	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1996	{
1997	PPDMPCIDEV pBridge = pBus->papBridgesR3[iBridge];
1998	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
1999	("Device is not a PCI bridge but on the list of PCI bridges\n"));
2000	PDEVPCIBUS pChildBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
2001
2002	ich9pciBiosInitBridge(pPciRoot, pChildBus);
2003	}
2004
2005	/* Third pass (only for bus 0): set up prefetchable BARs recursively. */
2006	if (pBus->iBus == 0)
2007	{
2008	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2009	{
2010	PPDMPCIDEV pBridge = pBus->papBridgesR3[iBridge];
2011	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
2012	("Device is not a PCI bridge but on the list of PCI bridges\n"));
2013	PDEVPCIBUS pChildBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
2014
2015	Log(("BIOS init prefetchable memory behind bridge: %02x:%02x.%d\n", pChildBus->iBus, pBridge->uDevFn >> 3, pBridge->uDevFn & 7));
2016	/* Save values for the prefetchable dryruns. */
2017	uint32_t u32MMIOAddressBase = pPciRoot->uPciBiosMmio;
2018	uint64_t u64MMIOAddressBase = pPciRoot->uPciBiosMmio64;
2019
2020	bool fProbe = ich9pciBiosInitBridgePrefetchable(pPciRoot, pChildBus, false /* fUse64Bit /, true / fDryrun */);
2021	pPciRoot->uPciBiosMmio = u32MMIOAddressBase;
2022	pPciRoot->uPciBiosMmio64 = u64MMIOAddressBase;
2023	if (fProbe)
2024	{
2025	fProbe = ich9pciBiosInitBridgePrefetchable(pPciRoot, pChildBus, true /* fUse64Bit /, true / fDryrun */);
2026	pPciRoot->uPciBiosMmio = u32MMIOAddressBase;
2027	pPciRoot->uPciBiosMmio64 = u64MMIOAddressBase;
2028	if (fProbe)
2029	LogRel(("PCI: unresolvable prefetchable memory behind bridge %02x:%02x.%d\n", pChildBus->iBus, pBridge->uDevFn >> 3, pBridge->uDevFn & 7));
2030	else
2031	ich9pciBiosInitBridgePrefetchable(pPciRoot, pChildBus, true /* fUse64Bit /, false / fDryrun */);
2032	}
2033	else
2034	ich9pciBiosInitBridgePrefetchable(pPciRoot, pChildBus, false /* fUse64Bit /, false / fDryrun */);
2035	}
2036	}
2037	}
2038
2039	/**
2040	* Initializes bridges registers used for routing.
2041	*
2042	* We ASSUME PDM bus assignments are the same as the PCI bus assignments and
2043	* will complain if we find any conflicts. This because it is just soo much
2044	* simpler to have the two numbers match one another by default.
2045	*
2046	* @returns Max subordinate bus number.
2047	* @param pPciRoot Global device instance data used to generate unique bus numbers.
2048	* @param pBus The PCI bus to initialize.
2049	* @param pbmUsed Pointer to a 32-bit bitmap tracking which device
2050	* (ranges) has been used.
2051	* @param uBusPrimary The primary bus number the bus is connected to.
2052	*/
2053	static uint8_t ich9pciBiosInitBridgeTopology(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, uint32_t *pbmUsed, uint8_t uBusPrimary)
2054	{
2055	PPDMPCIDEV pBridgeDev = &pBus->PciDev;
2056
2057	/* Check if the PDM bus assignment makes sense. */
2058	AssertLogRelMsg(!(*pbmUsed & RT_BIT_32(pBus->iBus)),
2059	("PCIBIOS: Bad PCI bridge config! Conflict for bus %#x. Make sure to instantiate bridges for a sub-trees in sequence!\n",
2060	pBus->iBus));
2061	*pbmUsed \|= RT_BIT_32(pBus->iBus);
2062
2063	/* Set only if we are not on the root bus, it has no primary bus attached. */
2064	if (pBus->iBus != 0)
2065	{
2066	devpciR3SetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, uBusPrimary);
2067	devpciR3SetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, pBus->iBus);
2068	/* Since the subordinate bus value can only be finalized once we
2069	* finished recursing through everything behind the bridge, the only
2070	* solution is temporarily configuring the subordinate to the maximum
2071	* possible value. This makes sure that the config space accesses work
2072	* (for our own sloppy emulation it apparently doesn't matter, but
2073	* this is vital for real PCI bridges/devices in passthrough mode). */
2074	devpciR3SetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, 0xff);
2075	}
2076
2077	uint8_t uMaxSubNum = pBus->iBus;
2078	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2079	{
2080	PPDMPCIDEV pBridge = pBus->papBridgesR3[iBridge];
2081	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
2082	("Device is not a PCI bridge but on the list of PCI bridges\n"));
2083	PDEVPCIBUS pChildBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
2084	uint8_t uMaxChildSubBus = ich9pciBiosInitBridgeTopology(pPciRoot, pChildBus, pbmUsed, pBus->iBus);
2085	uMaxSubNum = RT_MAX(uMaxSubNum, uMaxChildSubBus);
2086	}
2087
2088	if (pBus->iBus != 0)
2089	devpciR3SetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, uMaxSubNum);
2090	for (uint32_t i = pBus->iBus; i <= uMaxSubNum; i++)
2091	*pbmUsed \|= RT_BIT_32(i);
2092
2093	/* Make sure that transactions are able to get through the bridge. Not
2094	* strictly speaking necessary this early (before any device is set up),
2095	* but on the other hand it can't hurt either. */
2096	if (pBus->iBus != 0)
2097	devpciR3SetWord(pBridgeDev, VBOX_PCI_COMMAND,
2098	VBOX_PCI_COMMAND_IO
2099	\| VBOX_PCI_COMMAND_MEMORY
2100	\| VBOX_PCI_COMMAND_MASTER);
2101
2102	/* safe, only needs to go to the config space array */
2103	Log2Func(("for bus %p: primary=%d secondary=%d subordinate=%d\n",
2104	pBus,
2105	PDMPciDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
2106	PDMPciDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
2107	PDMPciDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS)
2108	));
2109
2110	return uMaxSubNum;
2111	}
2112
2113
2114	/**
2115	* Worker for Fake PCI BIOS config
2116	*
2117	* @returns VBox status code.
2118	*
2119	* @param pDevIns ICH9 device instance.
2120	*/
2121	static int ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
2122	{
2123	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
2124	PVM pVM = PDMDevHlpGetVM(pDevIns);
2125	uint32_t const cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
2126	uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
2127
2128	LogRel(("PCI: setting up topology, resources and interrupts\n"));
2129
2130	/** @todo r=klaus this needs to do the same elcr magic as DevPCI.cpp, as the BIOS can't be trusted to do the right thing. Of course it's more difficult than with the old code, as there are bridges to be handled. The interrupt routing needs to be taken into account. Also I highly suspect that the chipset has 8 interrupt lines which we might be able to use for handling things on the root bus better (by treating them as devices on the mainboard). */
2131
2132	/*
2133	* Set the start addresses.
2134	*/
2135	pPciRoot->uPciBiosBus = 0;
2136	pPciRoot->uPciBiosIo = 0xd000;
2137	pPciRoot->uPciBiosMmio = cbBelow4GB;
2138	pPciRoot->uPciBiosMmio64 = cbAbove4GB + _4G;
2139
2140	/* NB: Assume that if PCI controller MMIO range is enabled, it is below the beginning of the memory hole. */
2141	if (pPciRoot->u64PciConfigMMioAddress)
2142	{
2143	AssertRelease(pPciRoot->u64PciConfigMMioAddress >= cbBelow4GB);
2144	pPciRoot->uPciBiosMmio = pPciRoot->u64PciConfigMMioAddress + pPciRoot->u64PciConfigMMioLength;
2145	}
2146	Log(("cbBelow4GB: %#RX32, uPciBiosMmio: %#RX64, cbAbove4GB: %#RX64, uPciBiosMmio64=%#RX64\n",
2147	cbBelow4GB, pPciRoot->uPciBiosMmio, cbAbove4GB, pPciRoot->uPciBiosMmio64));
2148
2149	/*
2150	* Assign bridge topology, for further routing to work.
2151	*/
2152	PDEVPCIBUS pBus = &pPciRoot->PciBus;
2153	AssertLogRel(pBus->iBus == 0);
2154	uint32_t bmUsed = 0;
2155	ich9pciBiosInitBridgeTopology(pPciRoot, pBus, &bmUsed, 0);
2156
2157	/*
2158	* Init all devices on bus 0 (recursing to further buses).
2159	*/
2160	ich9pciBiosInitAllDevicesOnBus(pPciRoot, pBus);
2161
2162	return VINF_SUCCESS;
2163	}
2164
2165
2166	/* -=-=-=-=-=- PCI Config Space -=-=-=-=-=- */
2167
2168
2169	/**
2170	* @callback_method_impl{PFNPCICONFIGREAD, Default config space read callback.}
2171	*/
2172	DECLCALLBACK(uint32_t) devpciR3CommonDefaultConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb)
2173	{
2174	NOREF(pDevIns);
2175
2176	uint32_t uValue;
2177	if (uAddress + cb <= 256)
2178	{
2179	switch (cb)
2180	{
2181	case 1:
2182	/* safe, only needs to go to the config space array */
2183	uValue = PDMPciDevGetByte(pPciDev, uAddress);
2184	break;
2185	case 2:
2186	/* safe, only needs to go to the config space array */
2187	uValue = PDMPciDevGetWord(pPciDev, uAddress);
2188	break;
2189	case 4:
2190	/* safe, only needs to go to the config space array */
2191	uValue = PDMPciDevGetDWord(pPciDev, uAddress);
2192	break;
2193	default:
2194	AssertFailed();
2195	uValue = 0;
2196	break;
2197	}
2198
2199	#ifdef LOG_ENABLED
2200	if ( pciDevIsMsiCapable(pPciDev)
2201	&& uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset < (uint32_t)pPciDev->Int.s.u8MsiCapSize )
2202	Log2Func(("MSI CAP: %#x LB %u -> %#x\n", uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset, cb, uValue));
2203	else if ( pciDevIsMsixCapable(pPciDev)
2204	&& uAddress - (uint32_t)pPciDev->Int.s.u8MsixCapOffset < (uint32_t)pPciDev->Int.s.u8MsixCapSize)
2205	Log2Func(("MSI-X CAP: %#x LB %u -> %#x\n", uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset, cb, uValue));
2206	#endif
2207	}
2208	else
2209	{
2210	if (uAddress + cb < _4K)
2211	LogRel(("PCI: %8s/%u: Read from extended register %d fallen back to generic code\n",
2212	pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, uAddress));
2213	else
2214	AssertFailed();
2215	uValue = 0;
2216	}
2217	return uValue;
2218	}
2219
2220
2221	/**
2222	* Worker for devpciR3ResetDevice and devpciR3UpdateMappings that unmaps a region.
2223	*
2224	* @returns VBox status code.
2225	* @param pDev The PCI device.
2226	* @param iRegion The region to unmap.
2227	*/
2228	static int devpciR3UnmapRegion(PPDMPCIDEV pDev, int iRegion)
2229	{
2230	PCIIORegion *pRegion = &pDev->Int.s.aIORegions[iRegion];
2231	AssertReturn(pRegion->size != 0, VINF_SUCCESS);
2232
2233	int rc;
2234	if (pRegion->addr == INVALID_PCI_ADDRESS)
2235	rc = VINF_SUCCESS;
2236	else
2237	{
2238	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2239	{
2240	/* Port IO */
2241	rc = PDMDevHlpIOPortDeregister(pDev->Int.s.pDevInsR3, pRegion->addr, pRegion->size);
2242	AssertRC(rc);
2243	}
2244	else
2245	{
2246	PDEVPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
2247	RTGCPHYS GCPhysBase = pRegion->addr;
2248	if (pBus->pPciHlpR3->pfnIsMMIOExBase(pBus->pDevInsR3, pDev->Int.s.pDevInsR3, GCPhysBase))
2249	{
2250	/* unmap it. */
2251	rc = pRegion->map_func(pDev->Int.s.pDevInsR3, pDev, iRegion,
2252	NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
2253	AssertRC(rc);
2254	rc = PDMDevHlpMMIOExUnmap(pDev->Int.s.pDevInsR3, pDev, iRegion, GCPhysBase);
2255	}
2256	else
2257	rc = PDMDevHlpMMIODeregister(pDev->Int.s.pDevInsR3, GCPhysBase, pRegion->size);
2258	AssertRC(rc);
2259	}
2260	pRegion->addr = INVALID_PCI_ADDRESS;
2261	}
2262	return rc;
2263	}
2264
2265
2266	/**
2267	* Worker for devpciR3CommonDefaultConfigWrite that updates BAR and ROM mappings.
2268	*
2269	* @returns VINF_SUCCESS of DBGFSTOP result.
2270	* @param pPciDev The PCI device to update the mappings for.
2271	* @param fP2PBridge Whether this is a PCI to PCI bridge or not.
2272	*/
2273	static VBOXSTRICTRC devpciR3UpdateMappings(PPDMPCIDEV pPciDev, bool fP2PBridge)
2274	{
2275	/* safe, only needs to go to the config space array */
2276	uint16_t const u16Cmd = PDMPciDevGetWord(pPciDev, VBOX_PCI_COMMAND);
2277	Log4(("devpciR3UpdateMappings: dev %u/%u (%s): u16Cmd=%#x\n",
2278	pPciDev->uDevFn >> VBOX_PCI_DEVFN_DEV_SHIFT, pPciDev->uDevFn & VBOX_PCI_DEVFN_FUN_MASK, pPciDev->pszNameR3, u16Cmd));
2279	for (unsigned iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
2280	{
2281	/* Skip over BAR2..BAR5 for bridges, as they have a different meaning there. */
2282	if (fP2PBridge && iRegion >= 2 && iRegion <= 5)
2283	continue;
2284	PCIIORegion *pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2285	uint64_t const cbRegion = pRegion->size;
2286	if (cbRegion != 0)
2287	{
2288	uint32_t const offCfgReg = devpciGetRegionReg(iRegion);
2289	bool const f64Bit = (pRegion->type & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
2290	== PCI_ADDRESS_SPACE_BAR64;
2291	uint64_t uNew = INVALID_PCI_ADDRESS;
2292
2293	/*
2294	* Port I/O region. Check if mapped and within 1..65535 range.
2295	*/
2296	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2297	{
2298	if (u16Cmd & VBOX_PCI_COMMAND_IO)
2299	{
2300	/* safe, only needs to go to the config space array */
2301	uint32_t uIoBase = PDMPciDevGetDWord(pPciDev, offCfgReg);
2302	uIoBase &= ~(uint32_t)(cbRegion - 1);
2303
2304	uint64_t uLast = cbRegion - 1 + uIoBase;
2305	if ( uLast < _64K
2306	&& uIoBase < uLast
2307	&& uIoBase > 0)
2308	uNew = uIoBase;
2309	else
2310	Log4(("devpciR3UpdateMappings: dev %u/%u (%s): region #%u: Disregarding invalid I/O port range: %#RX32..%#RX64\n",
2311	pPciDev->uDevFn >> VBOX_PCI_DEVFN_DEV_SHIFT, pPciDev->uDevFn & VBOX_PCI_DEVFN_FUN_MASK,
2312	pPciDev->pszNameR3, iRegion, uIoBase, uLast));
2313	}
2314	}
2315	/*
2316	* MMIO or ROM. Check ROM enable bit and range.
2317	*
2318	* Note! We exclude the I/O-APIC/HPET/ROM area at the end of the first 4GB to
2319	* prevent the (fake) PCI BIOS and others from making a mess. Pure paranoia.
2320	* Additionally addresses with the top 32 bits all set are excluded, to
2321	* catch silly OSes which probe 64-bit BARs without disabling the
2322	* corresponding transactions.
2323	*
2324	* Update: The pure paranoia above broke NT 3.51, so it was changed to only
2325	* exclude the 64KB BIOS mapping at the top. NT 3.51 excludes the
2326	* top 256KB, btw.
2327	*/
2328	/** @todo Query upper boundrary from CPUM and PGMPhysRom instead of making
2329	* incorrect assumptions. */
2330	else if (u16Cmd & VBOX_PCI_COMMAND_MEMORY)
2331	{
2332	/* safe, only needs to go to the config space array */
2333	uint64_t uMemBase = PDMPciDevGetDWord(pPciDev, offCfgReg);
2334	if (f64Bit)
2335	{
2336	Assert(iRegion < VBOX_PCI_ROM_SLOT);
2337	/* safe, only needs to go to the config space array */
2338	uMemBase \|= (uint64_t)PDMPciDevGetDWord(pPciDev, offCfgReg + 4) << 32;
2339	}
2340	if ( iRegion != PCI_ROM_SLOT
2341	\|\| (uMemBase & RT_BIT_32(0))) /* ROM enable bit. */
2342	{
2343	uMemBase &= ~(cbRegion - 1);
2344
2345	uint64_t uLast = uMemBase + cbRegion - 1;
2346	if ( uMemBase < uLast
2347	&& uMemBase > 0)
2348	{
2349	if ( ( uMemBase > UINT32_C(0xffffffff)
2350	\|\| uLast < UINT32_C(0xffff0000) ) /* UINT32_C(0xfec00000) - breaks NT3.51! */
2351	&& uMemBase < UINT64_C(0xffffffff00000000) )
2352	uNew = uMemBase;
2353	else
2354	Log(("devpciR3UpdateMappings: dev %u/%u (%s): region #%u: Rejecting address range: %#RX64..%#RX64!\n",
2355	pPciDev->uDevFn >> VBOX_PCI_DEVFN_DEV_SHIFT, pPciDev->uDevFn & VBOX_PCI_DEVFN_FUN_MASK,
2356	pPciDev->pszNameR3, iRegion, uMemBase, uLast));
2357	}
2358	else
2359	Log2(("devpciR3UpdateMappings: dev %u/%u (%s): region #%u: Disregarding invalid address range: %#RX64..%#RX64\n",
2360	pPciDev->uDevFn >> VBOX_PCI_DEVFN_DEV_SHIFT, pPciDev->uDevFn & VBOX_PCI_DEVFN_FUN_MASK,
2361	pPciDev->pszNameR3, iRegion, uMemBase, uLast));
2362	}
2363	}
2364
2365	/*
2366	* Do real unmapping and/or mapping if the address change.
2367	*/
2368	Log4(("devpciR3UpdateMappings: dev %u/%u (%s): iRegion=%u addr=%#RX64 uNew=%#RX64\n",
2369	pPciDev->uDevFn >> VBOX_PCI_DEVFN_DEV_SHIFT, pPciDev->uDevFn & VBOX_PCI_DEVFN_FUN_MASK, pPciDev->pszNameR3,
2370	iRegion, pRegion->addr, uNew));
2371	if (uNew != pRegion->addr)
2372	{
2373	LogRel2(("PCI: config dev %u/%u (%s) BAR%i: %#RX64 -> %#RX64 (LB %RX64 (%RU64))\n",
2374	pPciDev->uDevFn >> VBOX_PCI_DEVFN_DEV_SHIFT, pPciDev->uDevFn & VBOX_PCI_DEVFN_FUN_MASK,
2375	pPciDev->pszNameR3, iRegion, pRegion->addr, uNew, cbRegion, cbRegion));
2376
2377	devpciR3UnmapRegion(pPciDev, iRegion);
2378	pRegion->addr = uNew;
2379	if (uNew != INVALID_PCI_ADDRESS)
2380	{
2381	int rc = pRegion->map_func(pPciDev->Int.s.pDevInsR3, pPciDev, iRegion, uNew, cbRegion,
2382	(PCIADDRESSSPACE)(pRegion->type));
2383	AssertRC(rc);
2384	}
2385	}
2386
2387	if (f64Bit)
2388	iRegion++;
2389	}
2390	/* else: size == 0: unused region */
2391	}
2392
2393	return VINF_SUCCESS;
2394	}
2395
2396
2397	/**
2398	* Worker for devpciR3CommonDefaultConfigWrite that write a byte to a BAR.
2399	*
2400	* @param pPciDev The PCI device.
2401	* @param iRegion The region.
2402	* @param off The BAR offset.
2403	* @param bVal The byte to write.
2404	*/
2405	DECLINLINE(void) devpciR3WriteBarByte(PPDMPCIDEV pPciDev, uint32_t iRegion, uint32_t off, uint8_t bVal)
2406	{
2407	PCIIORegion *pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2408	Log3Func(("region=%d off=%d val=%#x size=%#llx\n", iRegion, off, bVal, pRegion->size));
2409	Assert(off <= 3);
2410
2411	/* Check if we're writing to upper part of 64-bit BAR. */
2412	if (pRegion->type == 0xff)
2413	{
2414	AssertLogRelReturnVoid(iRegion > 0 && iRegion < VBOX_PCI_ROM_SLOT);
2415	pRegion--;
2416	iRegion--;
2417	off += 4;
2418	Assert(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
2419	}
2420
2421	/* Ignore zero sized regions (they don't exist). */
2422	if (pRegion->size != 0)
2423	{
2424	uint32_t uAddr = devpciGetRegionReg(iRegion) + off;
2425	Assert((pRegion->size & (pRegion->size - 1)) == 0); /* Region size must be power of two. */
2426	uint8_t bMask = ( (pRegion->size - 1) >> (off * 8) ) & 0xff;
2427	if (off == 0)
2428	bMask \|= (pRegion->type & PCI_ADDRESS_SPACE_IO)
2429	? (1 << 2) - 1 /* 2 lowest bits for IO region */ :
2430	(1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
2431
2432	/* safe, only needs to go to the config space array */
2433	uint8_t bOld = PDMPciDevGetByte(pPciDev, uAddr) & bMask;
2434	bVal = (bOld & bMask) \| (bVal & ~bMask);
2435
2436	Log3Func(("%x changed to %x\n", bOld, bVal));
2437
2438	/* safe, only needs to go to the config space array */
2439	PDMPciDevSetByte(pPciDev, uAddr, bVal);
2440	}
2441	}
2442
2443
2444	/**
2445	* Checks if the given configuration byte is writable.
2446	*
2447	* @returns true if writable, false if not
2448	* @param uAddress The config space byte byte.
2449	* @param bHeaderType The device header byte.
2450	*/
2451	DECLINLINE(bool) devpciR3IsConfigByteWritable(uint32_t uAddress, uint8_t bHeaderType)
2452	{
2453	switch (bHeaderType)
2454	{
2455	case 0x00: /* normal device */
2456	case 0x80: /* multi-function device */
2457	switch (uAddress)
2458	{
2459	/* Read-only registers. */
2460	case VBOX_PCI_VENDOR_ID:
2461	case VBOX_PCI_VENDOR_ID+1:
2462	case VBOX_PCI_DEVICE_ID:
2463	case VBOX_PCI_DEVICE_ID+1:
2464	case VBOX_PCI_REVISION_ID:
2465	case VBOX_PCI_CLASS_PROG:
2466	case VBOX_PCI_CLASS_SUB:
2467	case VBOX_PCI_CLASS_BASE:
2468	case VBOX_PCI_HEADER_TYPE:
2469	case VBOX_PCI_SUBSYSTEM_VENDOR_ID:
2470	case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
2471	case VBOX_PCI_SUBSYSTEM_ID:
2472	case VBOX_PCI_SUBSYSTEM_ID+1:
2473	case VBOX_PCI_ROM_ADDRESS:
2474	case VBOX_PCI_ROM_ADDRESS+1:
2475	case VBOX_PCI_ROM_ADDRESS+2:
2476	case VBOX_PCI_ROM_ADDRESS+3:
2477	case VBOX_PCI_CAPABILITY_LIST:
2478	case VBOX_PCI_INTERRUPT_PIN:
2479	return false;
2480	/* Other registers can be written. */
2481	default:
2482	return true;
2483	}
2484	break;
2485	case 0x01: /* PCI-PCI bridge */
2486	switch (uAddress)
2487	{
2488	/* Read-only registers. */
2489	case VBOX_PCI_VENDOR_ID:
2490	case VBOX_PCI_VENDOR_ID+1:
2491	case VBOX_PCI_DEVICE_ID:
2492	case VBOX_PCI_DEVICE_ID+1:
2493	case VBOX_PCI_REVISION_ID:
2494	case VBOX_PCI_CLASS_PROG:
2495	case VBOX_PCI_CLASS_SUB:
2496	case VBOX_PCI_CLASS_BASE:
2497	case VBOX_PCI_HEADER_TYPE:
2498	case VBOX_PCI_ROM_ADDRESS_BR:
2499	case VBOX_PCI_ROM_ADDRESS_BR+1:
2500	case VBOX_PCI_ROM_ADDRESS_BR+2:
2501	case VBOX_PCI_ROM_ADDRESS_BR+3:
2502	case VBOX_PCI_INTERRUPT_PIN:
2503	return false;
2504	/* Other registers can be written. */
2505	default:
2506	return true;
2507	}
2508	break;
2509	default:
2510	AssertMsgFailed(("Unknown header type %#x\n", bHeaderType));
2511	return false;
2512	}
2513	}
2514
2515
2516	/**
2517	* @callback_method_impl{PFNPCICONFIGWRITE,
2518	* Default config space write callback.}
2519	*
2520	* See paragraph 7.5 of PCI Express specification (p. 349) for
2521	* definition of registers and their writability policy.
2522	*/
2523	DECLCALLBACK(VBOXSTRICTRC) devpciR3CommonDefaultConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
2524	uint32_t uAddress, uint32_t u32Value, unsigned cb)
2525	{
2526	NOREF(pDevIns);
2527	Assert(cb <= 4);
2528	VBOXSTRICTRC rcRet = VINF_SUCCESS;
2529
2530	if (uAddress + cb <= 256)
2531	{
2532	/*
2533	* MSI and MSI-X capabilites needs to be handled separately.
2534	*/
2535	if ( pciDevIsMsiCapable(pPciDev)
2536	&& uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset < (uint32_t)pPciDev->Int.s.u8MsiCapSize)
2537	MsiPciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2538	pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2539	pPciDev, uAddress, u32Value, cb);
2540	else if ( pciDevIsMsixCapable(pPciDev)
2541	&& uAddress - (uint32_t)pPciDev->Int.s.u8MsixCapOffset < (uint32_t)pPciDev->Int.s.u8MsixCapSize)
2542	MsixPciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2543	pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2544	pPciDev, uAddress, u32Value, cb);
2545	else
2546	{
2547	/*
2548	* Handle the writes byte-by-byte to catch all possible cases.
2549	*
2550	* Note! Real hardware may not necessarily handle non-dword writes like
2551	* we do here and even produce erratic behavior. We don't (yet)
2552	* try emulate that.
2553	*/
2554	uint8_t const bHeaderType = devpciR3GetByte(pPciDev, VBOX_PCI_HEADER_TYPE);
2555	bool const fP2PBridge = bHeaderType == 0x01; /* PCI-PCI bridge */
2556	bool fUpdateMappings = false;
2557	while (cb-- > 0)
2558	{
2559	bool fWritable = devpciR3IsConfigByteWritable(uAddress, bHeaderType);
2560	uint8_t bVal = (uint8_t)u32Value;
2561	bool fRom = false;
2562	switch (uAddress)
2563	{
2564	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
2565	if (fWritable)
2566	{
2567	/* safe, only needs to go to the config space array */
2568	PDMPciDevSetByte(pPciDev, uAddress, bVal);
2569	fUpdateMappings = true;
2570	}
2571	break;
2572
2573	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
2574	if (fWritable)
2575	{
2576	/* don't change reserved bits (11-15) */
2577	bVal &= ~UINT8_C(0xf8);
2578	/* safe, only needs to go to the config space array */
2579	PDMPciDevSetByte(pPciDev, uAddress, bVal);
2580	fUpdateMappings = true;
2581	}
2582	break;
2583
2584	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
2585	/* don't change read-only bits => actually all lower bits are read-only */
2586	bVal &= ~UINT8_C(0xff);
2587	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
2588	pPciDev->abConfig[uAddress] &= ~bVal;
2589	break;
2590
2591	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
2592	/* don't change read-only bits */
2593	bVal &= ~UINT8_C(0x06);
2594	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
2595	pPciDev->abConfig[uAddress] &= ~bVal;
2596	break;
2597
2598	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3:
2599	fRom = true;
2600	RT_FALL_THRU();
2601	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
2602	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
2603	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
2604	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
2605	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
2606	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
2607	/* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
2608	if (!fP2PBridge)
2609	{
2610	uint32_t iRegion = fRom ? VBOX_PCI_ROM_SLOT : (uAddress - VBOX_PCI_BASE_ADDRESS_0) >> 2;
2611	devpciR3WriteBarByte(pPciDev, iRegion, uAddress & 0x3, bVal);
2612	fUpdateMappings = true;
2613	break;
2614	}
2615	else if (uAddress < VBOX_PCI_BASE_ADDRESS_2 \|\| uAddress > VBOX_PCI_BASE_ADDRESS_5+3)
2616	{
2617	/* PCI bridges have only BAR0, BAR1 and ROM */
2618	uint32_t iRegion = fRom ? VBOX_PCI_ROM_SLOT : (uAddress - VBOX_PCI_BASE_ADDRESS_0) >> 2;
2619	devpciR3WriteBarByte(pPciDev, iRegion, uAddress & 0x3, bVal);
2620	fUpdateMappings = true;
2621	break;
2622	}
2623	else if ( uAddress == VBOX_PCI_IO_BASE
2624	\|\| uAddress == VBOX_PCI_IO_LIMIT
2625	\|\| uAddress == VBOX_PCI_MEMORY_BASE
2626	\|\| uAddress == VBOX_PCI_MEMORY_LIMIT
2627	\|\| uAddress == VBOX_PCI_PREF_MEMORY_BASE
2628	\|\| uAddress == VBOX_PCI_PREF_MEMORY_LIMIT)
2629	{
2630	/* All bridge address decoders have the low 4 bits
2631	* as readonly, and all but the prefetchable ones
2632	* have the low 4 bits as 0 (the prefetchable have
2633	* it as 1 to show the 64-bit decoder support. */
2634	bVal &= 0xf0;
2635	if ( uAddress == VBOX_PCI_PREF_MEMORY_BASE
2636	\|\| uAddress == VBOX_PCI_PREF_MEMORY_LIMIT)
2637	bVal \|= 0x01;
2638	}
2639	/* (bridge config space which isn't a BAR) */
2640	RT_FALL_THRU();
2641	default:
2642	if (fWritable)
2643	/* safe, only needs to go to the config space array */
2644	PDMPciDevSetByte(pPciDev, uAddress, bVal);
2645	break;
2646	}
2647	uAddress++;
2648	u32Value >>= 8;
2649	}
2650
2651	/*
2652	* Update the region mappings if anything changed related to them (command, BARs, ROM).
2653	*/
2654	if (fUpdateMappings)
2655	rcRet = devpciR3UpdateMappings(pPciDev, fP2PBridge);
2656	}
2657	}
2658	else if (uAddress + cb <= _4K)
2659	LogRel(("PCI: %8s/%u: Write to extended register %d fallen back to generic code\n",
2660	pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, uAddress));
2661	else
2662	AssertMsgFailed(("Write after end of PCI config space\n"));
2663
2664	return rcRet;
2665	}
2666
2667
2668	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
2669
2670	/**
2671	* Indents an info line.
2672	* @param pHlp The info helper.
2673	* @param iIndentLvl The desired indentation level.
2674	*/
2675	static void devpciR3InfoIndent(PCDBGFINFOHLP pHlp, unsigned iIndentLvl)
2676	{
2677	for (unsigned i = 0; i < iIndentLvl; i++)
2678	pHlp->pfnPrintf(pHlp, " ");
2679	}
2680
2681	static const char *devpciR3InInfoPciBusClassName(uint8_t iBaseClass)
2682	{
2683	static const char *s_szBaseClass[] =
2684	{
2685	/* 00h */ "unknown",
2686	/* 01h */ "mass storage controller",
2687	/* 02h */ "network controller",
2688	/* 03h */ "display controller",
2689	/* 04h */ "multimedia controller",
2690	/* 05h */ "memory controller",
2691	/* 06h */ "bridge device",
2692	/* 07h */ "simple communication controllers",
2693	/* 08h */ "base system peripherals",
2694	/* 09h */ "input devices",
2695	/* 0Ah */ "docking stations",
2696	/* 0Bh */ "processors",
2697	/* 0Ch */ "serial bus controllers",
2698	/* 0Dh */ "wireless controller",
2699	/* 0Eh */ "intelligent I/O controllers",
2700	/* 0Fh */ "satellite communication controllers",
2701	/* 10h */ "encryption/decryption controllers",
2702	/* 11h */ "data acquisition and signal processing controllers"
2703	};
2704	if (iBaseClass < RT_ELEMENTS(s_szBaseClass))
2705	return s_szBaseClass[iBaseClass];
2706	if (iBaseClass < 0xFF)
2707	return "reserved";
2708	return "device does not fit in any defined classes";
2709	}
2710
2711
2712	/**
2713	* Recursive worker for devpciR3InfoPci.
2714	*
2715	* @param pBus The bus to show info for.
2716	* @param pHlp The info helpers.
2717	* @param iIndentLvl The indentation level.
2718	* @param fRegisters Whether to show device registers or not.
2719	*/
2720	static void devpciR3InfoPciBus(PDEVPCIBUS pBus, PCDBGFINFOHLP pHlp, unsigned iIndentLvl, bool fRegisters)
2721	{
2722	/* This has to use the callbacks for accuracy reasons. Otherwise it can get
2723	* confusing in the passthrough case or when the callbacks for some device
2724	* are doing something non-trivial (like implementing an indirect
2725	* passthrough approach), because then the abConfig array is an imprecise
2726	* cache needed for efficiency (so that certain reads can be done from
2727	* R0/RC), but far from authoritative or what the guest would see. */
2728
2729	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
2730	{
2731	PPDMPCIDEV pPciDev = pBus->apDevices[uDevFn];
2732	if (pPciDev != NULL)
2733	{
2734	devpciR3InfoIndent(pHlp, iIndentLvl);
2735
2736	/*
2737	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2738	* as host driver handles real devices interrupts.
2739	*/
2740	pHlp->pfnPrintf(pHlp, "%02x:%02x.%d %s%s: %04x-%04x %s%s%s",
2741	pBus->iBus, (uDevFn >> 3) & 0xff, uDevFn & 0x7,
2742	pPciDev->pszNameR3,
2743	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2744	devpciR3GetWord(pPciDev, VBOX_PCI_VENDOR_ID), devpciR3GetWord(pPciDev, VBOX_PCI_DEVICE_ID),
2745	pBus->fTypeIch9 ? "ICH9" : pBus->fTypePiix3 ? "PIIX3" : "?type?",
2746	pciDevIsMsiCapable(pPciDev) ? " MSI" : "",
2747	pciDevIsMsixCapable(pPciDev) ? " MSI-X" : ""
2748	);
2749	if (devpciR3GetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2750	{
2751	pHlp->pfnPrintf(pHlp, " IRQ%d", devpciR3GetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2752	pHlp->pfnPrintf(pHlp, " (INTA#->IRQ%d)", 0x10 + ich9pciSlot2ApicIrq(uDevFn >> 3, 0));
2753	}
2754	pHlp->pfnPrintf(pHlp, "\n");
2755	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2756	uint8_t uClassBase = devpciR3GetByte(pPciDev, VBOX_PCI_CLASS_BASE);
2757	uint8_t uClassSub = devpciR3GetByte(pPciDev, VBOX_PCI_CLASS_SUB);
2758	pHlp->pfnPrintf(pHlp, "Class base/sub: %02x%02x (%s)\n",
2759	uClassBase, uClassSub, devpciR3InInfoPciBusClassName(uClassBase));
2760
2761	if (pciDevIsMsiCapable(pPciDev) \|\| pciDevIsMsixCapable(pPciDev))
2762	{
2763	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2764
2765	if (pciDevIsMsiCapable(pPciDev))
2766	pHlp->pfnPrintf(pHlp, "MSI: %s ", MsiIsEnabled(pPciDev) ? "on" : "off");
2767
2768	if (pciDevIsMsixCapable(pPciDev))
2769	pHlp->pfnPrintf(pHlp, "MSI-X: %s ", MsixIsEnabled(pPciDev) ? "on" : "off");
2770
2771	pHlp->pfnPrintf(pHlp, "\n");
2772	}
2773
2774	for (unsigned iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
2775	{
2776	PCIIORegion const *pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2777	uint64_t const cbRegion = pRegion->size;
2778
2779	if (cbRegion == 0)
2780	continue;
2781
2782	uint32_t uAddr = devpciR3GetDWord(pPciDev, devpciGetRegionReg(iRegion));
2783	const char * pszDesc;
2784	char szDescBuf[128];
2785
2786	bool f64Bit = (pRegion->type & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
2787	== PCI_ADDRESS_SPACE_BAR64;
2788	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2789	{
2790	pszDesc = "IO";
2791	uAddr &= ~0x3;
2792	}
2793	else
2794	{
2795	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2796	f64Bit ? "64" : "32",
2797	pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH ? " PREFETCH" : "");
2798	pszDesc = szDescBuf;
2799	uAddr &= ~0xf;
2800	}
2801
2802	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2803	pHlp->pfnPrintf(pHlp, "%s region #%u: ", pszDesc, iRegion);
2804	if (f64Bit)
2805	{
2806	uint32_t u32High = devpciR3GetDWord(pPciDev, devpciGetRegionReg(iRegion+1));
2807	uint64_t u64Addr = RT_MAKE_U64(uAddr, u32High);
2808	pHlp->pfnPrintf(pHlp, "%RX64..%RX64\n", u64Addr, u64Addr + cbRegion - 1);
2809	iRegion++;
2810	}
2811	else
2812	pHlp->pfnPrintf(pHlp, "%x..%x\n", uAddr, uAddr + (uint32_t)cbRegion - 1);
2813	}
2814
2815	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2816	uint16_t iCmd = devpciR3GetWord(pPciDev, VBOX_PCI_COMMAND);
2817	uint16_t iStatus = devpciR3GetWord(pPciDev, VBOX_PCI_STATUS);
2818	pHlp->pfnPrintf(pHlp, "Command: %04x, Status: %04x\n", iCmd, iStatus);
2819	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2820	pHlp->pfnPrintf(pHlp, "Bus master: %s\n", iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2821	if (iCmd != PDMPciDevGetCommand(pPciDev))
2822	{
2823	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2824	pHlp->pfnPrintf(pHlp, "CACHE INCONSISTENCY: Command: %04x\n", PDMPciDevGetCommand(pPciDev));
2825	}
2826
2827	if (fRegisters)
2828	{
2829	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2830	pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2831	for (unsigned iReg = 0; iReg < 0x100; )
2832	{
2833	unsigned iPerLine = 0x10;
2834	Assert(0x100 % iPerLine == 0);
2835	devpciR3InfoIndent(pHlp, iIndentLvl + 3);
2836
2837	while (iPerLine-- > 0)
2838	pHlp->pfnPrintf(pHlp, "%02x ", devpciR3GetByte(pPciDev, iReg++));
2839	pHlp->pfnPrintf(pHlp, "\n");
2840	}
2841	}
2842	}
2843	}
2844
2845	if (pBus->cBridges > 0)
2846	{
2847	devpciR3InfoIndent(pHlp, iIndentLvl);
2848	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2849	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2850	{
2851	PDEVPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
2852	uint8_t uPrimary = devpciR3GetByte(&pBusSub->PciDev, VBOX_PCI_PRIMARY_BUS);
2853	uint8_t uSecondary = devpciR3GetByte(&pBusSub->PciDev, VBOX_PCI_SECONDARY_BUS);
2854	uint8_t uSubordinate = devpciR3GetByte(&pBusSub->PciDev, VBOX_PCI_SUBORDINATE_BUS);
2855	devpciR3InfoIndent(pHlp, iIndentLvl);
2856	pHlp->pfnPrintf(pHlp, "%02x:%02x.%d: bridge topology: primary=%d secondary=%d subordinate=%d\n",
2857	uPrimary, pBusSub->PciDev.uDevFn >> 3, pBusSub->PciDev.uDevFn & 7,
2858	uPrimary, uSecondary, uSubordinate);
2859	if ( uPrimary != PDMPciDevGetByte(&pBusSub->PciDev, VBOX_PCI_PRIMARY_BUS)
2860	\|\| uSecondary != PDMPciDevGetByte(&pBusSub->PciDev, VBOX_PCI_SECONDARY_BUS)
2861	\|\| uSubordinate != PDMPciDevGetByte(&pBusSub->PciDev, VBOX_PCI_SUBORDINATE_BUS))
2862	{
2863	devpciR3InfoIndent(pHlp, iIndentLvl);
2864	pHlp->pfnPrintf(pHlp, "CACHE INCONSISTENCY: primary=%d secondary=%d subordinate=%d\n",
2865	PDMPciDevGetByte(&pBusSub->PciDev, VBOX_PCI_PRIMARY_BUS),
2866	PDMPciDevGetByte(&pBusSub->PciDev, VBOX_PCI_SECONDARY_BUS),
2867	PDMPciDevGetByte(&pBusSub->PciDev, VBOX_PCI_SUBORDINATE_BUS));
2868	}
2869	devpciR3InfoIndent(pHlp, iIndentLvl);
2870	pHlp->pfnPrintf(pHlp, "behind bridge: ");
2871	uint8_t uIoBase = devpciR3GetByte(&pBusSub->PciDev, VBOX_PCI_IO_BASE);
2872	uint8_t uIoLimit = devpciR3GetByte(&pBusSub->PciDev, VBOX_PCI_IO_LIMIT);
2873	pHlp->pfnPrintf(pHlp, "I/O %#06x..%#06x",
2874	(uIoBase & 0xf0) << 8,
2875	(uIoLimit & 0xf0) << 8 \| 0xfff);
2876	if (uIoBase > uIoLimit)
2877	pHlp->pfnPrintf(pHlp, " (IGNORED)");
2878	pHlp->pfnPrintf(pHlp, "\n");
2879	devpciR3InfoIndent(pHlp, iIndentLvl);
2880	pHlp->pfnPrintf(pHlp, "behind bridge: ");
2881	uint32_t uMemoryBase = devpciR3GetWord(&pBusSub->PciDev, VBOX_PCI_MEMORY_BASE);
2882	uint32_t uMemoryLimit = devpciR3GetWord(&pBusSub->PciDev, VBOX_PCI_MEMORY_LIMIT);
2883	pHlp->pfnPrintf(pHlp, "memory %#010x..%#010x",
2884	(uMemoryBase & 0xfff0) << 16,
2885	(uMemoryLimit & 0xfff0) << 16 \| 0xfffff);
2886	if (uMemoryBase > uMemoryLimit)
2887	pHlp->pfnPrintf(pHlp, " (IGNORED)");
2888	pHlp->pfnPrintf(pHlp, "\n");
2889	devpciR3InfoIndent(pHlp, iIndentLvl);
2890	pHlp->pfnPrintf(pHlp, "behind bridge: ");
2891	uint32_t uPrefMemoryRegBase = devpciR3GetWord(&pBusSub->PciDev, VBOX_PCI_PREF_MEMORY_BASE);
2892	uint32_t uPrefMemoryRegLimit = devpciR3GetWord(&pBusSub->PciDev, VBOX_PCI_PREF_MEMORY_LIMIT);
2893	uint64_t uPrefMemoryBase = (uPrefMemoryRegBase & 0xfff0) << 16;
2894	uint64_t uPrefMemoryLimit = (uPrefMemoryRegLimit & 0xfff0) << 16 \| 0xfffff;
2895	if ( (uPrefMemoryRegBase & 0xf) == 1
2896	&& (uPrefMemoryRegLimit & 0xf) == 1)
2897	{
2898	uPrefMemoryBase \|= (uint64_t)devpciR3GetDWord(&pBusSub->PciDev, VBOX_PCI_PREF_BASE_UPPER32) << 32;
2899	uPrefMemoryLimit \|= (uint64_t)devpciR3GetDWord(&pBusSub->PciDev, VBOX_PCI_PREF_LIMIT_UPPER32) << 32;
2900	pHlp->pfnPrintf(pHlp, "64-bit ");
2901	}
2902	else
2903	pHlp->pfnPrintf(pHlp, "32-bit ");
2904	pHlp->pfnPrintf(pHlp, "prefetch memory %#018llx..%#018llx", uPrefMemoryBase, uPrefMemoryLimit);
2905	if (uPrefMemoryBase > uPrefMemoryLimit)
2906	pHlp->pfnPrintf(pHlp, " (IGNORED)");
2907	pHlp->pfnPrintf(pHlp, "\n");
2908	devpciR3InfoPciBus(pBusSub, pHlp, iIndentLvl + 1, fRegisters);
2909	}
2910	}
2911	}
2912
2913
2914	/**
2915	* @callback_method_impl{FNDBGFHANDLERDEV, 'pci'}
2916	*/
2917	DECLCALLBACK(void) devpciR3InfoPci(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2918	{
2919	PDEVPCIBUS pBus = DEVINS_2_DEVPCIBUS(pDevIns);
2920
2921	if (pszArgs == NULL \|\| !*pszArgs \|\| !strcmp(pszArgs, "basic"))
2922	devpciR3InfoPciBus(pBus, pHlp, 0 /iIndentLvl/, false /fRegisters/);
2923	else if (!strcmp(pszArgs, "verbose"))
2924	devpciR3InfoPciBus(pBus, pHlp, 0 /iIndentLvl/, true /fRegisters/);
2925	else
2926	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2927	}
2928
2929
2930	/**
2931	* @callback_method_impl{FNDBGFHANDLERDEV, 'pciirq'}
2932	*/
2933	DECLCALLBACK(void) devpciR3InfoPciIrq(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2934	{
2935	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
2936	NOREF(pszArgs);
2937
2938	pHlp->pfnPrintf(pHlp, "PCI I/O APIC IRQ levels:\n");
2939	for (int i = 0; i < DEVPCI_APIC_IRQ_PINS; ++i)
2940	pHlp->pfnPrintf(pHlp, " IRQ%02d: %u\n", 0x10 + i, pPciRoot->auPciApicIrqLevels[i]);
2941	}
2942
2943
2944	/**
2945	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2946	*/
2947	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2948	{
2949	RT_NOREF1(iInstance);
2950	Assert(iInstance == 0);
2951	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2952
2953	/*
2954	* Validate and read configuration.
2955	*/
2956	if (!CFGMR3AreValuesValid(pCfg,
2957	"IOAPIC\0"
2958	"GCEnabled\0"
2959	"R0Enabled\0"
2960	"McfgBase\0"
2961	"McfgLength\0"
2962	))
2963	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2964
2965	/* query whether we got an IOAPIC */
2966	bool fUseIoApic;
2967	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2968	if (RT_FAILURE(rc))
2969	return PDMDEV_SET_ERROR(pDevIns, rc,
2970	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2971
2972	/* check if RC code is enabled. */
2973	bool fGCEnabled;
2974	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2975	if (RT_FAILURE(rc))
2976	return PDMDEV_SET_ERROR(pDevIns, rc,
2977	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2978	/* check if R0 code is enabled. */
2979	bool fR0Enabled;
2980	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2981	if (RT_FAILURE(rc))
2982	return PDMDEV_SET_ERROR(pDevIns, rc,
2983	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2984
2985	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2986
2987	/*
2988	* Init data.
2989	*/
2990	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
2991	PDEVPCIBUS pBus = &pPciRoot->PciBus;
2992	/* Zero out everything */
2993	memset(pPciRoot, 0, sizeof(*pPciRoot));
2994	/* And fill values */
2995	if (!fUseIoApic)
2996	return PDMDEV_SET_ERROR(pDevIns, rc,
2997	N_("Must use IO-APIC with ICH9 chipset"));
2998	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pPciRoot->u64PciConfigMMioAddress, 0);
2999	if (RT_FAILURE(rc))
3000	return PDMDEV_SET_ERROR(pDevIns, rc,
3001	N_("Configuration error: Failed to read \"McfgBase\""));
3002	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pPciRoot->u64PciConfigMMioLength, 0);
3003	if (RT_FAILURE(rc))
3004	return PDMDEV_SET_ERROR(pDevIns, rc,
3005	N_("Configuration error: Failed to read \"McfgLength\""));
3006
3007	pPciRoot->fUseIoApic = fUseIoApic;
3008	pPciRoot->pDevInsR3 = pDevIns;
3009	pPciRoot->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3010	pPciRoot->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3011
3012	pPciRoot->PciBus.fTypePiix3 = false;
3013	pPciRoot->PciBus.fTypeIch9 = true;
3014	pPciRoot->PciBus.fPureBridge = false;
3015	pPciRoot->PciBus.pDevInsR3 = pDevIns;
3016	pPciRoot->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3017	pPciRoot->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3018	pPciRoot->PciBus.papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pPciRoot->PciBus.apDevices));
3019	AssertLogRelReturn(pPciRoot->PciBus.papBridgesR3, VERR_NO_MEMORY);
3020
3021	/*
3022	* Register bus
3023	*/
3024	PDMPCIBUSREG PciBusReg;
3025	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
3026	PciBusReg.pfnRegisterR3 = pciR3MergedRegister;
3027	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
3028	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
3029	PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
3030	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
3031	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
3032	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
3033	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
3034	if (RT_FAILURE(rc))
3035	return PDMDEV_SET_ERROR(pDevIns, rc,
3036	N_("Failed to register ourselves as a PCI Bus"));
3037	Assert(pBus->iBus == 0);
3038	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
3039	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3040	N_("PCI helper version mismatch; got %#x expected %#x"),
3041	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
3042
3043	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
3044	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
3045
3046	/*
3047	* Fill in PCI configs and add them to the bus.
3048	*/
3049	/** @todo Disabled for now because this causes error messages with Linux guests.
3050	* The guest loads the x38_edac device which tries to map a memory region
3051	* using an address given at place 0x48 - 0x4f in the PCI config space.
3052	* This fails. because we don't register such a region.
3053	*/
3054	#if 0
3055	/* Host bridge device */
3056	PDMPciDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
3057	PDMPciDevSetDeviceId( &pBus->PciDev, 0x29e0); /* Desktop */
3058	PDMPciDevSetRevisionId(&pBus->PciDev, 0x01); /* rev. 01 */
3059	PDMPciDevSetClassBase( &pBus->PciDev, 0x06); /* bridge */
3060	PDMPciDevSetClassSub( &pBus->PciDev, 0x00); /* Host/PCI bridge */
3061	PDMPciDevSetClassProg( &pBus->PciDev, 0x00); /* Host/PCI bridge */
3062	PDMPciDevSetHeaderType(&pBus->PciDev, 0x00); /* bridge */
3063	PDMPciDevSetWord(&pBus->PciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
3064
3065	pBus->PciDev.pDevIns = pDevIns;
3066	/* We register Host<->PCI controller on the bus */
3067	ich9pciRegisterInternal(pBus, 0, &pBus->PciDev, "dram");
3068	#endif
3069
3070	/*
3071	* Register I/O ports and save state.
3072	*/
3073	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
3074	if (RT_FAILURE(rc))
3075	return rc;
3076	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
3077	if (RT_FAILURE(rc))
3078	return rc;
3079	if (fGCEnabled)
3080	{
3081	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
3082	if (RT_FAILURE(rc))
3083	return rc;
3084	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
3085	if (RT_FAILURE(rc))
3086	return rc;
3087	}
3088	if (fR0Enabled)
3089	{
3090	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
3091	if (RT_FAILURE(rc))
3092	return rc;
3093	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
3094	if (RT_FAILURE(rc))
3095	return rc;
3096	}
3097
3098	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0410, 1, NULL, ich9pciR3IOPortMagicPCIWrite, ich9pciR3IOPortMagicPCIRead, NULL, NULL, "ICH9 (Fake PCI BIOS trigger)");
3099	if (RT_FAILURE(rc))
3100	return rc;
3101
3102	if (pPciRoot->u64PciConfigMMioAddress != 0)
3103	{
3104	rc = PDMDevHlpMMIORegister(pDevIns, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength, NULL /pvUser/,
3105	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
3106	ich9pciMcfgMMIOWrite, ich9pciMcfgMMIORead, "MCFG ranges");
3107	AssertMsgRCReturn(rc, ("rc=%Rrc %#llx/%#llx\n", rc, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength), rc);
3108
3109	if (fGCEnabled)
3110	{
3111	rc = PDMDevHlpMMIORegisterRC(pDevIns, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength,
3112	NIL_RTRCPTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
3113	AssertRCReturn(rc, rc);
3114	}
3115
3116
3117	if (fR0Enabled)
3118	{
3119	rc = PDMDevHlpMMIORegisterR0(pDevIns, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength,
3120	NIL_RTR0PTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
3121	AssertRCReturn(rc, rc);
3122	}
3123	}
3124
3125	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION,
3126	sizeof(pBus) + 16128, "pgm",
3127	NULL, NULL, NULL,
3128	NULL, ich9pciR3SaveExec, NULL,
3129	NULL, ich9pciR3LoadExec, NULL);
3130	if (RT_FAILURE(rc))
3131	return rc;
3132
3133
3134	/** @todo other chipset devices shall be registered too */
3135
3136	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
3137	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
3138	devpciR3InfoPci);
3139	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", devpciR3InfoPciIrq);
3140
3141	return VINF_SUCCESS;
3142	}
3143
3144
3145	/**
3146	* @interface_method_impl{PDMDEVREG,pfnDestruct}
3147	*/
3148	static DECLCALLBACK(int) ich9pciDestruct(PPDMDEVINS pDevIns)
3149	{
3150	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
3151	if (pPciRoot->PciBus.papBridgesR3)
3152	{
3153	PDMDevHlpMMHeapFree(pDevIns, pPciRoot->PciBus.papBridgesR3);
3154	pPciRoot->PciBus.papBridgesR3 = NULL;
3155	}
3156	return VINF_SUCCESS;
3157	}
3158
3159
3160	void devpciR3ResetDevice(PPDMPCIDEV pDev)
3161	{
3162	/* Clear regions */
3163	for (int iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
3164	{
3165	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
3166	if (pRegion->size == 0)
3167	continue;
3168	bool const f64Bit = (pRegion->type & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
3169	== PCI_ADDRESS_SPACE_BAR64;
3170
3171	devpciR3UnmapRegion(pDev, iRegion);
3172
3173	if (f64Bit)
3174	iRegion++;
3175	}
3176
3177	if (pciDevIsPassthrough(pDev))
3178	{
3179	// no reset handler - we can do what we need in PDM reset handler
3180	/// @todo is it correct?
3181	}
3182	else
3183	{
3184	devpciR3SetWord(pDev, VBOX_PCI_COMMAND,
3185	devpciR3GetWord(pDev, VBOX_PCI_COMMAND)
3186	& ~(VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY \|
3187	VBOX_PCI_COMMAND_MASTER \| VBOX_PCI_COMMAND_SPECIAL \|
3188	VBOX_PCI_COMMAND_PARITY \| VBOX_PCI_COMMAND_SERR \|
3189	VBOX_PCI_COMMAND_FAST_BACK \| VBOX_PCI_COMMAND_INTX_DISABLE));
3190
3191	/* Bridge device reset handlers processed later */
3192	if (!pciDevIsPci2PciBridge(pDev))
3193	{
3194	devpciR3SetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
3195	devpciR3SetByte(pDev, VBOX_PCI_INTERRUPT_LINE, 0x0);
3196	}
3197
3198	/* Reset MSI message control. */
3199	if (pciDevIsMsiCapable(pDev))
3200	{
3201	devpciR3SetWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL,
3202	devpciR3GetWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL) & 0xff8e);
3203	}
3204
3205	/* Reset MSI-X message control. */
3206	if (pciDevIsMsixCapable(pDev))
3207	{
3208	devpciR3SetWord(pDev, pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL,
3209	devpciR3GetWord(pDev, pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL) & 0x3fff);
3210	}
3211	}
3212	}
3213
3214	/**
3215	* Returns the PCI express encoding for the given PCI Express Device/Port type string.
3216	*
3217	* @returns PCI express encoding.
3218	* @param pszExpressPortType The string identifier for the port/device type.
3219	*/
3220	static uint8_t ich9pcibridgeR3GetExpressPortTypeFromString(const char *pszExpressPortType)
3221	{
3222	if (!RTStrCmp(pszExpressPortType, "EndPtDev"))
3223	return VBOX_PCI_EXP_TYPE_ENDPOINT;
3224	else if (!RTStrCmp(pszExpressPortType, "LegEndPtDev"))
3225	return VBOX_PCI_EXP_TYPE_LEG_END;
3226	else if (!RTStrCmp(pszExpressPortType, "RootCmplxRootPort"))
3227	return VBOX_PCI_EXP_TYPE_ROOT_PORT;
3228	else if (!RTStrCmp(pszExpressPortType, "ExpressSwUpstream"))
3229	return VBOX_PCI_EXP_TYPE_UPSTREAM;
3230	else if (!RTStrCmp(pszExpressPortType, "ExpressSwDownstream"))
3231	return VBOX_PCI_EXP_TYPE_DOWNSTREAM;
3232	else if (!RTStrCmp(pszExpressPortType, "Express2PciBridge"))
3233	return VBOX_PCI_EXP_TYPE_PCI_BRIDGE;
3234	else if (!RTStrCmp(pszExpressPortType, "Pci2ExpressBridge"))
3235	return VBOX_PCI_EXP_TYPE_PCIE_BRIDGE;
3236	else if (!RTStrCmp(pszExpressPortType, "RootCmplxIntEp"))
3237	return VBOX_PCI_EXP_TYPE_ROOT_INT_EP;
3238	else if (!RTStrCmp(pszExpressPortType, "RootCmplxEc"))
3239	return VBOX_PCI_EXP_TYPE_ROOT_EC;
3240
3241	AssertLogRelMsgFailedReturn(("Unknown express port type specified"), VBOX_PCI_EXP_TYPE_ROOT_INT_EP);
3242	}
3243
3244	/**
3245	* Recursive worker for ich9pciReset.
3246	*
3247	* @param pDevIns ICH9 bridge (root or PCI-to-PCI) instance.
3248	*/
3249	static void ich9pciResetBridge(PPDMDEVINS pDevIns)
3250	{
3251	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
3252
3253	/* PCI-specific reset for each device. */
3254	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
3255	{
3256	if (pBus->apDevices[uDevFn])
3257	devpciR3ResetDevice(pBus->apDevices[uDevFn]);
3258	}
3259
3260	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
3261	{
3262	if (pBus->papBridgesR3[iBridge])
3263	ich9pciResetBridge(pBus->papBridgesR3[iBridge]->Int.s.CTX_SUFF(pDevIns));
3264	}
3265
3266	/* Reset topology config for non-root bridge. Last thing to do, otherwise
3267	* the secondary and subordinate are instantly unreachable. */
3268	if (pBus->iBus != 0)
3269	{
3270	devpciR3SetByte(&pBus->PciDev, VBOX_PCI_PRIMARY_BUS, 0);
3271	devpciR3SetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS, 0);
3272	devpciR3SetByte(&pBus->PciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
3273	/* Not resetting the address decoders of the bridge to 0, since the
3274	* PCI-to-PCI Bridge spec says that there is no default value. */
3275	}
3276	}
3277
3278
3279	/**
3280	* @interface_method_impl{PDMDEVREG,pfnReset}
3281	*/
3282	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
3283	{
3284	/* Reset everything under the root bridge. */
3285	ich9pciResetBridge(pDevIns);
3286	}
3287
3288
3289	/**
3290	* @interface_method_impl{PDMDEVREG,pfnRelocate}
3291	*/
3292	DECLCALLBACK(void) devpciR3BusRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
3293	{
3294	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
3295
3296	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3297	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
3298
3299	/* Relocate RC pointers for the attached pci devices. */
3300	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
3301	{
3302	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
3303	if (pDev)
3304	{
3305	pDev->Int.s.pBusRC += offDelta;
3306	if (pDev->Int.s.pMsixPageRC)
3307	pDev->Int.s.pMsixPageRC += offDelta;
3308	}
3309	}
3310	}
3311
3312
3313	/**
3314	* @interface_method_impl{PDMDEVREG,pfnRelocate}
3315	*/
3316	DECLCALLBACK(void) devpciR3RootRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
3317	{
3318	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
3319	pPciRoot->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3320
3321	AssertCompileMemberOffset(DEVPCIROOT, PciBus, 0);
3322	devpciR3BusRelocate(pDevIns, offDelta);
3323	}
3324
3325
3326	/**
3327	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
3328	*/
3329	static DECLCALLBACK(void ) ich9pcibridgeQueryInterface(PPDMIBASE pInterface, const char pszIID)
3330	{
3331	PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
3332	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
3333	/* Special access to the PDMPCIDEV structure of a ich9pcibridge instance. */
3334	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
3335	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIICH9BRIDGEPDMPCIDEV, &pBus->PciDev);
3336	return NULL;
3337	}
3338
3339
3340	/**
3341	* @interface_method_impl{PDMDEVREG,pfnConstruct}
3342	*/
3343	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
3344	int iInstance,
3345	PCFGMNODE pCfg)
3346	{
3347	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3348
3349	/*
3350	* Validate and read configuration.
3351	*/
3352	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0" "ExpressEnabled\0" "ExpressPortType\0"))
3353	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
3354
3355	/* check if RC code is enabled. */
3356	bool fGCEnabled;
3357	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
3358	if (RT_FAILURE(rc))
3359	return PDMDEV_SET_ERROR(pDevIns, rc,
3360	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
3361
3362	/* check if R0 code is enabled. */
3363	bool fR0Enabled;
3364	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
3365	if (RT_FAILURE(rc))
3366	return PDMDEV_SET_ERROR(pDevIns, rc,
3367	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
3368	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
3369
3370	/* check if we're supposed to implement a PCIe bridge. */
3371	bool fExpress;
3372	rc = CFGMR3QueryBoolDef(pCfg, "ExpressEnabled", &fExpress, false);
3373	if (RT_FAILURE(rc))
3374	return PDMDEV_SET_ERROR(pDevIns, rc,
3375	N_("Configuration error: Failed to query boolean value \"ExpressEnabled\""));
3376
3377	char *pszExpressPortType;
3378	rc = CFGMR3QueryStringAllocDef(pCfg, "ExpressPortType",
3379	&pszExpressPortType, "RootCmplxIntEp");
3380	if (RT_FAILURE(rc))
3381	return PDMDEV_SET_ERROR(pDevIns, rc,
3382	N_("LsiLogic configuration error: failed to read \"ExpressPortType\" as string"));
3383
3384	uint8_t uExpressPortType = ich9pcibridgeR3GetExpressPortTypeFromString(pszExpressPortType);
3385	MMR3HeapFree(pszExpressPortType);
3386
3387	pDevIns->IBase.pfnQueryInterface = ich9pcibridgeQueryInterface;
3388
3389	/*
3390	* Init data and register the PCI bus.
3391	*/
3392	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
3393	pBus->fTypePiix3 = false;
3394	pBus->fTypeIch9 = true;
3395	pBus->fPureBridge = true;
3396	pBus->pDevInsR3 = pDevIns;
3397	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3398	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3399	/** @todo r=klaus figure out how to extend this to allow PCIe config space
3400	* extension, which increases the config space from 256 bytes to 4K. */
3401	pBus->papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pBus->apDevices));
3402	AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
3403
3404	PDMPCIBUSREG PciBusReg;
3405	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
3406	PciBusReg.pfnRegisterR3 = pcibridgeR3MergedRegisterDevice;
3407	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
3408	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
3409	PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
3410	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
3411	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
3412	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
3413	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
3414	if (RT_FAILURE(rc))
3415	return PDMDEV_SET_ERROR(pDevIns, rc,
3416	N_("Failed to register ourselves as a PCI Bus"));
3417	Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
3418	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
3419	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3420	N_("PCI helper version mismatch; got %#x expected %#x"),
3421	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
3422
3423	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
3424	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
3425	LogRel(("PCI: Registered bridge instance #%u as PDM bus no %u.\n", iInstance, pBus->iBus));
3426
3427
3428	/* Disable default device locking. */
3429	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3430	AssertRCReturn(rc, rc);
3431
3432	/*
3433	* Fill in PCI configs and add them to the bus.
3434	*/
3435	PDMPciDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
3436	if (fExpress)
3437	{
3438	PDMPciDevSetDeviceId(&pBus->PciDev, 0x29e1); /* 82X38/X48 Express Host-Primary PCI Express Bridge. */
3439	PDMPciDevSetRevisionId(&pBus->PciDev, 0x01);
3440	}
3441	else
3442	{
3443	PDMPciDevSetDeviceId(&pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
3444	PDMPciDevSetRevisionId(&pBus->PciDev, 0xf2);
3445	}
3446	PDMPciDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
3447	PDMPciDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
3448	if (fExpress)
3449	PDMPciDevSetClassProg(&pBus->PciDev, 0x00); /* Normal decoding. */
3450	else
3451	PDMPciDevSetClassProg(&pBus->PciDev, 0x01); /* Supports subtractive decoding. */
3452	PDMPciDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
3453	if (fExpress)
3454	{
3455	PDMPciDevSetCommand(&pBus->PciDev, VBOX_PCI_COMMAND_SERR);
3456	PDMPciDevSetStatus(&pBus->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* Has capabilities. */
3457	PDMPciDevSetByte(&pBus->PciDev, VBOX_PCI_CACHE_LINE_SIZE, 8); /* 32 bytes */
3458	/* PCI Express */
3459	PDMPciDevSetByte(&pBus->PciDev, 0xa0 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
3460	PDMPciDevSetByte(&pBus->PciDev, 0xa0 + 1, 0); /* next */
3461	PDMPciDevSetWord(&pBus->PciDev, 0xa0 + 2,
3462	/* version */ 0x2
3463	\| (uExpressPortType << 4));
3464	PDMPciDevSetDWord(&pBus->PciDev, 0xa0 + 4, VBOX_PCI_EXP_DEVCAP_RBE); /* Device capabilities. */
3465	PDMPciDevSetWord(&pBus->PciDev, 0xa0 + 8, 0x0000); /* Device control. */
3466	PDMPciDevSetWord(&pBus->PciDev, 0xa0 + 10, 0x0000); /* Device status. */
3467	PDMPciDevSetDWord(&pBus->PciDev, 0xa0 + 12,
3468	/* Max Link Speed */ 2
3469	\| /* Maximum Link Width */ (16 << 4)
3470	\| /* Active State Power Management (ASPM) Sopport */ (0 << 10)
3471	\| VBOX_PCI_EXP_LNKCAP_LBNC
3472	\| /* Port Number / ((2 + iInstance) << 24)); / Link capabilities. */
3473	PDMPciDevSetWord(&pBus->PciDev, 0xa0 + 16, VBOX_PCI_EXP_LNKCTL_CLOCK); /* Link control. */
3474	PDMPciDevSetWord(&pBus->PciDev, 0xa0 + 18,
3475	/* Current Link Speed */ 2
3476	\| /* Negotiated Link Width */ (16 << 4)
3477	\| VBOX_PCI_EXP_LNKSTA_SL_CLK); /* Link status. */
3478	PDMPciDevSetDWord(&pBus->PciDev, 0xa0 + 20,
3479	/* Slot Power Limit Value */ (75 << 7)
3480	\| /* Physical Slot Number / (0 << 19)); / Slot capabilities. */
3481	PDMPciDevSetWord(&pBus->PciDev, 0xa0 + 24, 0x0000); /* Slot control. */
3482	PDMPciDevSetWord(&pBus->PciDev, 0xa0 + 26, 0x0000); /* Slot status. */
3483	PDMPciDevSetWord(&pBus->PciDev, 0xa0 + 28, 0x0000); /* Root control. */
3484	PDMPciDevSetWord(&pBus->PciDev, 0xa0 + 30, 0x0000); /* Root capabilities. */
3485	PDMPciDevSetDWord(&pBus->PciDev, 0xa0 + 32, 0x00000000); /* Root status. */
3486	PDMPciDevSetDWord(&pBus->PciDev, 0xa0 + 36, 0x00000000); /* Device capabilities 2. */
3487	PDMPciDevSetWord(&pBus->PciDev, 0xa0 + 40, 0x0000); /* Device control 2. */
3488	PDMPciDevSetWord(&pBus->PciDev, 0xa0 + 42, 0x0000); /* Device status 2. */
3489	PDMPciDevSetDWord(&pBus->PciDev, 0xa0 + 44,
3490	/* Supported Link Speeds Vector / (2 << 1)); / Link capabilities 2. */
3491	PDMPciDevSetWord(&pBus->PciDev, 0xa0 + 48,
3492	/* Target Link Speed / 2); / Link control 2. */
3493	PDMPciDevSetWord(&pBus->PciDev, 0xa0 + 50, 0x0000); /* Link status 2. */
3494	PDMPciDevSetDWord(&pBus->PciDev, 0xa0 + 52, 0x00000000); /* Slot capabilities 2. */
3495	PDMPciDevSetWord(&pBus->PciDev, 0xa0 + 56, 0x0000); /* Slot control 2. */
3496	PDMPciDevSetWord(&pBus->PciDev, 0xa0 + 58, 0x0000); /* Slot status 2. */
3497	PDMPciDevSetCapabilityList(&pBus->PciDev, 0xa0);
3498	}
3499	else
3500	{
3501	PDMPciDevSetCommand(&pBus->PciDev, 0x00);
3502	PDMPciDevSetStatus(&pBus->PciDev, 0x20); /* 66MHz Capable. */
3503	}
3504	PDMPciDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
3505
3506	/*
3507	* This device does not generate interrupts. Interrupt delivery from
3508	* devices attached to the bus is unaffected.
3509	*/
3510	PDMPciDevSetInterruptPin (&pBus->PciDev, 0x00);
3511
3512	if (fExpress)
3513	{
3514	/** @todo r=klaus set up the PCIe config space beyond the old 256 byte
3515	* limit, containing additional capability descriptors. */
3516	}
3517
3518	/*
3519	* Register this PCI bridge. The called function will take care on which bus we will get registered.
3520	*/
3521	rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->PciDev, PDMPCIDEVREG_CFG_PRIMARY, PDMPCIDEVREG_F_PCI_BRIDGE,
3522	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "ich9pcibridge");
3523	if (RT_FAILURE(rc))
3524	return rc;
3525	pBus->PciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
3526	pBus->PciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
3527
3528	/*
3529	* Register SSM handlers. We use the same saved state version as for the host bridge
3530	* to make changes easier.
3531	*/
3532	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION,
3533	sizeof(pBus) + 16128,
3534	"pgm" /* before */,
3535	NULL, NULL, NULL,
3536	NULL, ich9pcibridgeR3SaveExec, NULL,
3537	NULL, ich9pcibridgeR3LoadExec, NULL);
3538	if (RT_FAILURE(rc))
3539	return rc;
3540
3541
3542	return VINF_SUCCESS;
3543	}
3544
3545	/**
3546	* @interface_method_impl{PDMDEVREG,pfnDestruct}
3547	*/
3548	static DECLCALLBACK(int) ich9pcibridgeDestruct(PPDMDEVINS pDevIns)
3549	{
3550	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
3551	if (pBus->papBridgesR3)
3552	{
3553	PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
3554	pBus->papBridgesR3 = NULL;
3555	}
3556	return VINF_SUCCESS;
3557	}
3558
3559
3560
3561	/**
3562	* The PCI bus device registration structure.
3563	*/
3564	const PDMDEVREG g_DevicePciIch9 =
3565	{
3566	/* u32Version */
3567	PDM_DEVREG_VERSION,
3568	/* szName */
3569	"ich9pci",
3570	/* szRCMod */
3571	"VBoxDDRC.rc",
3572	/* szR0Mod */
3573	"VBoxDDR0.r0",
3574	/* pszDescription */
3575	"ICH9 PCI bridge",
3576	/* fFlags */
3577	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
3578	/* fClass */
3579	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
3580	/* cMaxInstances */
3581	1,
3582	/* cbInstance */
3583	sizeof(DEVPCIROOT),
3584	/* pfnConstruct */
3585	ich9pciConstruct,
3586	/* pfnDestruct */
3587	ich9pciDestruct,
3588	/* pfnRelocate */
3589	devpciR3RootRelocate,
3590	/* pfnMemSetup */
3591	NULL,
3592	/* pfnPowerOn */
3593	NULL,
3594	/* pfnReset */
3595	ich9pciReset,
3596	/* pfnSuspend */
3597	NULL,
3598	/* pfnResume */
3599	NULL,
3600	/* pfnAttach */
3601	NULL,
3602	/* pfnDetach */
3603	NULL,
3604	/* pfnQueryInterface */
3605	NULL,
3606	/* pfnInitComplete */
3607	NULL,
3608	/* pfnPowerOff */
3609	NULL,
3610	/* pfnSoftReset */
3611	NULL,
3612	/* u32VersionEnd */
3613	PDM_DEVREG_VERSION
3614	};
3615
3616	/**
3617	* The device registration structure
3618	* for the PCI-to-PCI bridge.
3619	*/
3620	const PDMDEVREG g_DevicePciIch9Bridge =
3621	{
3622	/* u32Version */
3623	PDM_DEVREG_VERSION,
3624	/* szName */
3625	"ich9pcibridge",
3626	/* szRCMod */
3627	"VBoxDDRC.rc",
3628	/* szR0Mod */
3629	"VBoxDDR0.r0",
3630	/* pszDescription */
3631	"ICH9 PCI to PCI bridge",
3632	/* fFlags */
3633	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
3634	/* fClass */
3635	PDM_DEVREG_CLASS_BUS_PCI,
3636	/* cMaxInstances */
3637	~0U,
3638	/* cbInstance */
3639	sizeof(DEVPCIBUS),
3640	/* pfnConstruct */
3641	ich9pcibridgeConstruct,
3642	/* pfnDestruct */
3643	ich9pcibridgeDestruct,
3644	/* pfnRelocate */
3645	devpciR3BusRelocate,
3646	/* pfnMemSetup */
3647	NULL,
3648	/* pfnPowerOn */
3649	NULL,
3650	/* pfnReset */
3651	NULL, /* Must be NULL, to make sure only bus driver handles reset */
3652	/* pfnSuspend */
3653	NULL,
3654	/* pfnResume */
3655	NULL,
3656	/* pfnAttach */
3657	NULL,
3658	/* pfnDetach */
3659	NULL,
3660	/* pfnQueryInterface */
3661	NULL,
3662	/* pfnInitComplete */
3663	NULL,
3664	/* pfnPowerOff */
3665	NULL,
3666	/* pfnSoftReset */
3667	NULL,
3668	/* u32VersionEnd */
3669	PDM_DEVREG_VERSION
3670	};
3671
3672	#endif /* IN_RING3 */
3673

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 71136

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