DevPciIch9.cpp@ 63478

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1	/* $Id: DevPciIch9.cpp 63478 2016-08-15 14:04:10Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation device.
4	*
5	* @note bird: I've cleaned up DevPCI.cpp to some extent, this file has not
6	* be cleaned up and because of pending code merge.
7	*/
8
9	/*
10	* Copyright (C) 2010-2016 Oracle Corporation
11	*
12	* This file is part of VirtualBox Open Source Edition (OSE), as
13	* available from http://www.virtualbox.org. This file is free software;
14	* you can redistribute it and/or modify it under the terms of the GNU
15	* General Public License (GPL) as published by the Free Software
16	* Foundation, in version 2 as it comes in the "COPYING" file of the
17	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19	*/
20
21
22	/*********************************************************************************************************************************
23	* Header Files *
24	*********************************************************************************************************************************/
25	#define LOG_GROUP LOG_GROUP_DEV_PCI
26	/* Hack to get PCIDEVICEINT declared at the right point - include "PCIInternal.h". */
27	#define PCI_INCLUDE_PRIVATE
28	#define PCIBus ICH9PCIBus
29	#include <VBox/pci.h>
30	#include <VBox/msi.h>
31	#include <VBox/vmm/pdmdev.h>
32	#include <iprt/asm.h>
33	#include <iprt/assert.h>
34	#include <iprt/string.h>
35	#ifdef IN_RING3
36	#include <iprt/alloc.h>
37	#endif
38
39	#include "VBoxDD.h"
40	#include "MsiCommon.h"
41
42
43	/*********************************************************************************************************************************
44	* Structures and Typedefs *
45	*********************************************************************************************************************************/
46	/**
47	* PCI Bus instance.
48	*/
49	typedef struct ICH9PCIBus
50	{
51	/** Bus number. */
52	int32_t iBus;
53	/** Number of bridges attached to the bus. */
54	uint32_t cBridges;
55
56	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
57	R3PTRTYPE(PPCIDEVICE) apDevices[256];
58	/** Array of bridges attached to the bus. */
59	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
60
61	/** R3 pointer to the device instance. */
62	PPDMDEVINSR3 pDevInsR3;
63	/** Pointer to the PCI R3 helpers. */
64	PCPDMPCIHLPR3 pPciHlpR3;
65
66	/** R0 pointer to the device instance. */
67	PPDMDEVINSR0 pDevInsR0;
68	/** Pointer to the PCI R0 helpers. */
69	PCPDMPCIHLPR0 pPciHlpR0;
70
71	/** RC pointer to the device instance. */
72	PPDMDEVINSRC pDevInsRC;
73	/** Pointer to the PCI RC helpers. */
74	PCPDMPCIHLPRC pPciHlpRC;
75
76	/** The PCI device for the PCI bridge. */
77	PCIDEVICE aPciDev;
78
79	} ICH9PCIBUS, *PICH9PCIBUS;
80
81
82	/** @def PCI_APIC_IRQ_PINS
83	* Number of pins for interrupts if the APIC is used.
84	*/
85	#define PCI_APIC_IRQ_PINS 8
86
87	/**
88	* PCI Globals - This is the host-to-pci bridge and the root bus.
89	*/
90	typedef struct
91	{
92	/** R3 pointer to the device instance. */
93	PPDMDEVINSR3 pDevInsR3;
94	/** R0 pointer to the device instance. */
95	PPDMDEVINSR0 pDevInsR0;
96	/** RC pointer to the device instance. */
97	PPDMDEVINSRC pDevInsRC;
98
99	#if HC_ARCH_BITS == 64
100	uint32_t Alignment0;
101	#endif
102
103	/** Value latched in Configuration Address Port (0CF8h) */
104	uint32_t uConfigReg;
105
106	/** I/O APIC irq levels */
107	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
108
109	#if 1 /* Will be moved into the BIOS soon. */
110	/** The next I/O port address which the PCI BIOS will use. */
111	uint32_t uPciBiosIo;
112	/** The next MMIO address which the PCI BIOS will use. */
113	uint32_t uPciBiosMmio;
114	/** Actual bus number. */
115	uint8_t uBus;
116	#endif
117	/** Physical address of PCI config space MMIO region. */
118	uint64_t u64PciConfigMMioAddress;
119	/** Length of PCI config space MMIO region. */
120	uint64_t u64PciConfigMMioLength;
121
122	/** PCI bus which is attached to the host-to-PCI bridge. */
123	ICH9PCIBUS aPciBus;
124	} ICH9PCIGLOBALS, *PICH9PCIGLOBALS;
125
126
127	/**
128	* PCI configuration space address.
129	*/
130	typedef struct
131	{
132	uint8_t iBus;
133	uint8_t iDeviceFunc;
134	uint16_t iRegister;
135	} PciAddress;
136
137	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
138
139
140	/*********************************************************************************************************************************
141	* Defined Constants And Macros *
142	*********************************************************************************************************************************/
143
144	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
145	* Saved state version of the ICH9 PCI bus device.
146	*/
147	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
148	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
149	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
150
151	/** Converts a bus instance pointer to a device instance pointer. */
152	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
153	/** Converts a device instance pointer to a ICH9PCIGLOBALS pointer. */
154	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PICH9PCIGLOBALS)(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)))
155	/** Converts a device instance pointer to a PCIBUS pointer. */
156	#define DEVINS_2_PCIBUS(pDevIns) ((PICH9PCIBUS)(&PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)->aPciBus))
157	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer. */
158	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PICH9PCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(ICH9PCIGLOBALS, aPciBus)) )
159
160	/** @def PCI_LOCK
161	* Acquires the PDM lock. This is a NOP if locking is disabled. */
162	/** @def PCI_UNLOCK
163	* Releases the PDM lock. This is a NOP if locking is disabled. */
164	#define PCI_LOCK(pDevIns, rc) \
165	do { \
166	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
167	if (rc2 != VINF_SUCCESS) \
168	return rc2; \
169	} while (0)
170	#define PCI_UNLOCK(pDevIns) \
171	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
172
173	/* Prototypes */
174	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev,
175	int iIrq, int iLevel, uint32_t uTagSrc);
176	#ifdef IN_RING3
177	static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
178	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
179	static void ich9pciUpdateMappings(PCIDevice *pDev);
180	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
181	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus);
182	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn);
183	#endif
184
185	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
186	// mapping, we take n=6 approach
187	DECLINLINE(void) ich9pciPhysToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
188	{
189	NOREF(pGlobals);
190	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<6) - 1);
191	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
192	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
193	}
194
195	DECLINLINE(void) ich9pciStateToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
196	{
197	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
198	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
199	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
200	}
201
202	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
203	{
204	LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
205	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc);
206	}
207
208	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
209	{
210	/*
211	* The PCI-to-PCI bridge specification defines how the interrupt pins
212	* are routed from the secondary to the primary bus (see chapter 9).
213	* iIrq gives the interrupt pin the pci device asserted.
214	* We change iIrq here according to the spec and call the SetIrq function
215	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
216	*/
217	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
218	PPCIDEVICE pPciDevBus = pPciDev;
219	int iIrqPinBridge = iIrq;
220	uint8_t uDevFnBridge = 0;
221
222	/* Walk the chain until we reach the host bus. */
223	do
224	{
225	uDevFnBridge = pBus->aPciDev.devfn;
226	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
227
228	/* Get the parent. */
229	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
230	pPciDevBus = &pBus->aPciDev;
231	} while (pBus->iBus != 0);
232
233	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
234	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
235	}
236
237
238	/**
239	* Port I/O Handler for PCI address OUT operations.
240	*
241	* Emulates writes to Configuration Address Port at 0CF8h for
242	* Configuration Mechanism #1.
243	*
244	* @returns VBox status code.
245	*
246	* @param pDevIns ICH9 device instance.
247	* @param pvUser User argument - ignored.
248	* @param uPort Port number used for the OUT operation.
249	* @param u32 The value to output.
250	* @param cb The value size in bytes.
251	*/
252	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
253	{
254	LogFlow(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
255	RT_NOREF2(Port, pvUser);
256	if (cb == 4)
257	{
258	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
259
260	/*
261	* bits [1:0] are hard-wired, read-only and must return zeroes
262	* when read.
263	*/
264	u32 &= ~3;
265
266	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
267	pThis->uConfigReg = u32;
268	PCI_UNLOCK(pDevIns);
269	}
270
271	return VINF_SUCCESS;
272	}
273
274
275	/**
276	* Port I/O Handler for PCI address IN operations.
277	*
278	* Emulates reads from Configuration Address Port at 0CF8h for
279	* Configuration Mechanism #1.
280	*
281	* @returns VBox status code.
282	*
283	* @param pDevIns ICH9 device instance.
284	* @param pvUser User argument - ignored.
285	* @param uPort Port number used for the IN operation.
286	* @param pu32 Where to store the result.
287	* @param cb Number of bytes read.
288	*/
289	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
290	{
291	RT_NOREF2(Port, pvUser);
292	if (cb == 4)
293	{
294	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
295
296	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
297	*pu32 = pThis->uConfigReg;
298	PCI_UNLOCK(pDevIns);
299
300	LogFlow(("ich9pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
301	return VINF_SUCCESS;
302	}
303
304	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
305	return VERR_IOM_IOPORT_UNUSED;
306	}
307
308
309	/*
310	* Perform configuration space write.
311	*/
312	static int ich9pciDataWriteAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pAddr,
313	uint32_t val, int cb, int rcReschedule)
314	{
315	int rc = VINF_SUCCESS;
316	#ifdef IN_RING3
317	NOREF(rcReschedule);
318	#else
319	RT_NOREF2(val, cb);
320	#endif
321
322	if (pAddr->iBus != 0) /* forward to subordinate bus */
323	{
324	if (pGlobals->aPciBus.cBridges)
325	{
326	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
327	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
328	if (pBridgeDevice)
329	{
330	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
331	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc,
332	pAddr->iRegister, val, cb);
333	}
334	#else
335	rc = rcReschedule;
336	#endif
337	}
338	}
339	else /* forward to directly connected device */
340	{
341	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
342	if (aDev)
343	{
344	#ifdef IN_RING3
345	aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, cb);
346	#else
347	rc = rcReschedule;
348	#endif
349	}
350	}
351
352	Log2(("ich9pciDataWriteAddr: %02x:%02x:%02x reg %x(%d) %x %Rrc\n",
353	pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister,
354	cb, val, rc));
355	return rc;
356	}
357
358
359	/*
360	* Decode value latched in Configuration Address Port and perform
361	* requsted write to the target configuration space register.
362	*
363	* XXX: This code should be probably moved to its only caller
364	* (ich9pciIOPortDataWrite) to avoid prolifiration of confusingly
365	* similarly named functions.
366	*/
367	static int ich9pciDataWrite(PICH9PCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
368	{
369	LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
370
371	/* Configuration space mapping enabled? */
372	if (!(pGlobals->uConfigReg & (1 << 31)))
373	return VINF_SUCCESS;
374
375	/* Decode target device and configuration space register */
376	PciAddress aPciAddr;
377	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
378
379	/* Perform configuration space write */
380	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VINF_IOM_R3_IOPORT_WRITE);
381	}
382
383
384	/**
385	* Port I/O Handler for PCI data OUT operations.
386	*
387	* Emulates writes to Configuration Data Port at 0CFCh for
388	* Configuration Mechanism #1.
389	*
390	* @returns VBox status code.
391	*
392	* @param pDevIns ICH9 device instance.
393	* @param pvUser User argument - ignored.
394	* @param uPort Port number used for the OUT operation.
395	* @param u32 The value to output.
396	* @param cb The value size in bytes.
397	*/
398	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
399	{
400	LogFlow(("ich9pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
401	NOREF(pvUser);
402	int rc = VINF_SUCCESS;
403	if (!(Port % cb))
404	{
405	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
406
407	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
408	rc = ich9pciDataWrite(pThis, Port, u32, cb);
409	PCI_UNLOCK(pDevIns);
410	}
411	else
412	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
413	return rc;
414	}
415
416
417	static void ich9pciNoMem(void* ptr, int cb)
418	{
419	for (int i = 0; i < cb; i++)
420	((uint8_t*)ptr)[i] = 0xff;
421	}
422
423
424	/*
425	* Perform configuration space read.
426	*/
427	static int ich9pciDataReadAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pPciAddr, int cb,
428	uint32_t *pu32, int rcReschedule)
429	{
430	int rc = VINF_SUCCESS;
431	#ifdef IN_RING3
432	NOREF(rcReschedule);
433	#endif
434
435	if (pPciAddr->iBus != 0) /* forward to subordinate bus */
436	{
437	if (pGlobals->aPciBus.cBridges)
438	{
439	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
440	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
441	if (pBridgeDevice)
442	{
443	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
444	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
445	}
446	else
447	ich9pciNoMem(pu32, cb);
448	#else
449	rc = rcReschedule;
450	#endif
451	}
452	else
453	ich9pciNoMem(pu32, cb);
454	}
455	else /* forward to directly connected device */
456	{
457	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
458	if (aDev)
459	{
460	#ifdef IN_RING3
461	*pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, cb);
462	#else
463	rc = rcReschedule;
464	#endif
465	}
466	else
467	ich9pciNoMem(pu32, cb);
468	}
469
470	Log3(("ich9pciDataReadAddr: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n",
471	pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister,
472	cb, *pu32, rc));
473	return rc;
474	}
475
476
477	/*
478	* Decode value latched in Configuration Address Port and perform
479	* requsted read from the target configuration space register.
480	*
481	* XXX: This code should be probably moved to its only caller
482	* (ich9pciIOPortDataRead) to avoid prolifiration of confusingly
483	* similarly named functions.
484	*/
485	static int ich9pciDataRead(PICH9PCIGLOBALS pGlobals, uint32_t addr, int cb, uint32_t *pu32)
486	{
487	LogFlow(("ich9pciDataRead: config=%x cb=%d\n", pGlobals->uConfigReg, cb));
488
489	*pu32 = 0xffffffff;
490
491	/* Configuration space mapping enabled? */
492	if (!(pGlobals->uConfigReg & (1 << 31)))
493	return VINF_SUCCESS;
494
495	/* Decode target device and configuration space register */
496	PciAddress aPciAddr;
497	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
498
499	/* Perform configuration space read */
500	return ich9pciDataReadAddr(pGlobals, &aPciAddr, cb, pu32, VINF_IOM_R3_IOPORT_READ);
501	}
502
503
504	/**
505	* Port I/O Handler for PCI data IN operations.
506	*
507	* Emulates reads from Configuration Data Port at 0CFCh for
508	* Configuration Mechanism #1.
509	*
510	* @returns VBox status code.
511	*
512	* @param pDevIns ICH9 device instance.
513	* @param pvUser User argument - ignored.
514	* @param uPort Port number used for the IN operation.
515	* @param pu32 Where to store the result.
516	* @param cb Number of bytes read.
517	*/
518	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
519	{
520	NOREF(pvUser);
521	if (!(Port % cb))
522	{
523	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
524
525	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
526	int rc = ich9pciDataRead(pThis, Port, cb, pu32);
527	PCI_UNLOCK(pDevIns);
528
529	LogFlow(("ich9pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
530	return rc;
531	}
532	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
533	return VERR_IOM_IOPORT_UNUSED;
534	}
535
536
537	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
538	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
539	{
540	return (irq_num + uSlot) & 7;
541	}
542
543	#ifdef IN_RING3
544
545	/* return the global irq number corresponding to a given device irq
546	pin. We could also use the bus number to have a more precise
547	mapping. This is the implementation note described in the PCI spec chapter 2.2.6 */
548	DECLINLINE(int) ich9pciSlotGetPirq(uint8_t uBus, uint8_t uDevFn, int iIrqNum)
549	{
550	NOREF(uBus);
551	int iSlotAddend = (uDevFn >> 3) - 1;
552	return (iIrqNum + iSlotAddend) & 3;
553	}
554
555	/* irqs corresponding to PCI irqs A-D, must match pci_irq_list in rombios.c */
556	static const uint8_t aPciIrqs[4] = { 11, 10, 9, 5 };
557
558	#endif /* IN_RING3 */
559
560	/* Add one more level up request on APIC input line */
561	DECLINLINE(void) ich9pciApicLevelUp(PICH9PCIGLOBALS pGlobals, int irq_num)
562	{
563	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
564	}
565
566	/* Remove one level up request on APIC input line */
567	DECLINLINE(void) ich9pciApicLevelDown(PICH9PCIGLOBALS pGlobals, int irq_num)
568	{
569	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
570	}
571
572	static void ich9pciApicSetIrq(PICH9PCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel,
573	uint32_t uTagSrc, int iForcedIrq)
574	{
575	/* This is only allowed to be called with a pointer to the root bus. */
576	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
577
578	if (iForcedIrq == -1)
579	{
580	int apic_irq, apic_level;
581	PICH9PCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
582	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
583
584	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
585	ich9pciApicLevelUp(pGlobals, irq_num);
586	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
587	ich9pciApicLevelDown(pGlobals, irq_num);
588
589	apic_irq = irq_num + 0x10;
590	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
591	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x\n",
592	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
593	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
594
595	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
596	{
597	/*
598	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
599	* PDM_IRQ_LEVEL_HIGH bit set
600	*/
601	ich9pciApicLevelDown(pGlobals, irq_num);
602	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
603	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
604	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x (flop)\n",
605	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
606	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
607	}
608	} else {
609	Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d uTagSrc=%#x\n",
610	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq, uTagSrc));
611	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel, uTagSrc);
612	}
613	}
614
615	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev,
616	int iIrq, int iLevel, uint32_t uTagSrc)
617	{
618	/* If MSI or MSI-X is enabled, PCI INTx# signals are disabled regardless of the PCI command
619	* register interrupt bit state.
620	* PCI 3.0 (section 6.8) forbids MSI and MSI-X to be enabled at the same time and makes
621	* that undefined behavior. We check for MSI first, then MSI-X.
622	*/
623	if (MsiIsEnabled(pPciDev))
624	{
625	Assert(!MsixIsEnabled(pPciDev)); /* Not allowed -- see note above. */
626	LogFlowFunc(("PCI Dev %p : MSI\n", pPciDev));
627	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
628	MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
629	return;
630	}
631
632	if (MsixIsEnabled(pPciDev))
633	{
634	LogFlowFunc(("PCI Dev %p : MSI-X\n", pPciDev));
635	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
636	MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
637	return;
638	}
639
640	PICH9PCIBUS pBus = &pGlobals->aPciBus;
641	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
642
643	LogFlowFunc(("PCI Dev %p : IRQ\n", pPciDev));
644	/* Check if the state changed. */
645	if (pPciDev->Int.s.uIrqPinState != iLevel)
646	{
647	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
648
649	/* Send interrupt to I/O APIC only now. */
650	if (fIsAcpiDevice)
651	/*
652	* ACPI needs special treatment since SCI is hardwired and
653	* should not be affected by PCI IRQ routing tables at the
654	* same time SCI IRQ is shared in PCI sense hence this
655	* kludge (i.e. we fetch the hardwired value from ACPIs
656	* PCI device configuration space).
657	*/
658	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, uTagSrc, PCIDevGetInterruptLine(pPciDev));
659	else
660	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, uTagSrc, -1);
661	}
662	}
663
664
665	/**
666	* Memory mapped I/O Handler for write operations.
667	*
668	* Emulates writes to configuration space.
669	*
670	* @returns VBox status code.
671	*
672	* @param pDevIns The device instance.
673	* @param pvUser User argument.
674	* @param GCPhysAddr Physical address (in GC) where the read starts.
675	* @param pv Where to fetch the result.
676	* @param cb Number of bytes to write.
677	* @remarks Caller enters the device critical section.
678	*/
679	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
680	{
681	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
682	uint32_t u32 = 0;
683	NOREF(pvUser);
684
685	Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
686
687	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_WRITE);
688
689	/* Decode target device and configuration space register */
690	PciAddress aDest;
691	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
692
693	switch (cb)
694	{
695	case 1:
696	u32 = (uint8_t)pv;
697	break;
698	case 2:
699	u32 = (uint16_t)pv;
700	break;
701	case 4:
702	u32 = (uint32_t)pv;
703	break;
704	default:
705	Assert(false);
706	break;
707	}
708
709	/* Perform configuration space write */
710	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb, VINF_IOM_R3_MMIO_WRITE);
711	PCI_UNLOCK(pDevIns);
712
713	return rc;
714	}
715
716
717	/**
718	* Memory mapped I/O Handler for read operations.
719	*
720	* Emulates reads from configuration space.
721	*
722	* @returns VBox status code.
723	*
724	* @param pDevIns The device instance.
725	* @param pvUser User argument.
726	* @param GCPhysAddr Physical address (in GC) where the read starts.
727	* @param pv Where to store the result.
728	* @param cb Number of bytes read.
729	* @remarks Caller enters the device critical section.
730	*/
731	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
732	{
733	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
734	uint32_t rv;
735	NOREF(pvUser);
736
737	LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
738
739	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_READ);
740
741	/* Decode target device and configuration space register */
742	PciAddress aDest;
743	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
744
745	/* Perform configuration space read */
746	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv, VINF_IOM_R3_MMIO_READ);
747
748	if (RT_SUCCESS(rc))
749	{
750	switch (cb)
751	{
752	case 1:
753	(uint8_t)pv = (uint8_t)rv;
754	break;
755	case 2:
756	(uint16_t)pv = (uint16_t)rv;
757	break;
758	case 4:
759	(uint32_t)pv = (uint32_t)rv;
760	break;
761	default:
762	Assert(false);
763	break;
764	}
765	}
766	PCI_UNLOCK(pDevIns);
767
768	return rc;
769	}
770
771	#ifdef IN_RING3
772
773	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus)
774	{
775	/* Search for a fitting bridge. */
776	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
777	{
778	/*
779	* Examine secondary and subordinate bus number.
780	* If the target bus is in the range we pass the request on to the bridge.
781	*/
782	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
783	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
784	("Device is not a PCI bridge but on the list of PCI bridges\n"));
785	uint32_t uSecondary = PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS);
786	uint32_t uSubordinate = PCIDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS);
787	Log3(("ich9pciFindBridge on bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, iBus, uSecondary, uSubordinate));
788	if (iBus >= uSecondary && iBus <= uSubordinate)
789	return pBridge;
790	}
791
792	/* Nothing found. */
793	return NULL;
794	}
795
796	static uint32_t ich9pciGetCfg(PCIDevice* aDev, int32_t iRegister, int cb)
797	{
798	return aDev->Int.s.pfnConfigRead(aDev, iRegister, cb);
799	}
800
801	static uint8_t ich9pciGetByte(PCIDevice* aDev, int32_t iRegister)
802	{
803	return (uint8_t)ich9pciGetCfg(aDev, iRegister, 1);
804	}
805
806	static uint16_t ich9pciGetWord(PCIDevice* aDev, int32_t iRegister)
807	{
808	return (uint16_t)ich9pciGetCfg(aDev, iRegister, 2);
809	}
810
811	static uint32_t ich9pciGetDWord(PCIDevice* aDev, int32_t iRegister)
812	{
813	return (uint32_t)ich9pciGetCfg(aDev, iRegister, 4);
814	}
815
816	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
817	{
818	return (iRegion == VBOX_PCI_ROM_SLOT) ?
819	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
820	}
821
822	#define INVALID_PCI_ADDRESS ~0U
823
824	static int ich9pciUnmapRegion(PPCIDEVICE pDev, int iRegion)
825	{
826	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
827	int rc = VINF_SUCCESS;
828	PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
829
830	Assert (pRegion->size != 0);
831
832	if (pRegion->addr != INVALID_PCI_ADDRESS)
833	{
834	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
835	{
836	/* Port IO */
837	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
838	AssertRC(rc);
839	}
840	else
841	{
842	RTGCPHYS GCPhysBase = pRegion->addr;
843	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
844	{
845	/* unmap it. */
846	rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
847	AssertRC(rc);
848	rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
849	}
850	else
851	rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
852	}
853
854	pRegion->addr = INVALID_PCI_ADDRESS;
855	}
856
857	return rc;
858	}
859
860	static void ich9pciUpdateMappings(PCIDevice* pDev)
861	{
862	uint64_t uLast, uNew;
863
864	int iCmd = ich9pciGetWord(pDev, VBOX_PCI_COMMAND);
865	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
866	{
867	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
868	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
869	int64_t iRegionSize = pRegion->size;
870	int rc;
871
872	if (iRegionSize == 0)
873	continue;
874
875	bool f64Bit = (pRegion->type & PCI_ADDRESS_SPACE_BAR64) != 0;
876
877	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
878	{
879	/* port IO region */
880	if (iCmd & PCI_COMMAND_IOACCESS)
881	{
882	/* IO access allowed */
883	uNew = ich9pciGetDWord(pDev, uConfigReg);
884	uNew &= ~(iRegionSize - 1);
885	uLast = uNew + iRegionSize - 1;
886	/* only 64K ioports on PC */
887	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
888	uNew = INVALID_PCI_ADDRESS;
889	} else
890	uNew = INVALID_PCI_ADDRESS;
891	}
892	else
893	{
894	/* MMIO region */
895	if (iCmd & PCI_COMMAND_MEMACCESS)
896	{
897	uNew = ich9pciGetDWord(pDev, uConfigReg);
898
899	if (f64Bit)
900	{
901	uNew \|= ((uint64_t)ich9pciGetDWord(pDev, uConfigReg+4)) << 32;
902	/** @todo r=klaus Is this really true? Needs to be fixed properly. */
903	if (uNew > UINT64_C(0x0000010000000000))
904	{
905	/* Workaround for REM being unhapping with mapping very long 64-bit addresses */
906	LogRel(("Ignoring too long 64-bit BAR: %llx\n", uNew));
907	uNew = INVALID_PCI_ADDRESS;
908	}
909	}
910
911	/* the ROM slot has a specific enable bit */
912	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
913	uNew = INVALID_PCI_ADDRESS;
914	else
915	{
916	uNew &= ~(iRegionSize - 1);
917	uLast = uNew + iRegionSize - 1;
918	/* NOTE: we do not support wrapping */
919	/* XXX: as we cannot support really dynamic
920	mappings, we handle specific values as invalid
921	mappings. */
922	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
923	if (uLast <= uNew \|\| uNew == 0 \|\| (uNew <= UINT32_C(0xffffffff) && uLast >= UINT32_C(0xfec00000)))
924	uNew = INVALID_PCI_ADDRESS;
925	}
926	} else
927	uNew = INVALID_PCI_ADDRESS;
928	}
929	LogRel2(("PCI: config dev %u/%u BAR%i uOld=%#018llx uNew=%#018llx size=%llu\n", pDev->devfn >> 3, pDev->devfn & 7, iRegion, pRegion->addr, uNew, pRegion->size));
930	/* now do the real mapping */
931	if (uNew != pRegion->addr)
932	{
933	if (pRegion->addr != INVALID_PCI_ADDRESS)
934	ich9pciUnmapRegion(pDev, iRegion);
935
936	pRegion->addr = uNew;
937	if (pRegion->addr != INVALID_PCI_ADDRESS)
938	{
939
940	/* finally, map the region */
941	rc = pRegion->map_func(pDev, iRegion,
942	pRegion->addr, pRegion->size,
943	(PCIADDRESSSPACE)(pRegion->type));
944	AssertRC(rc);
945	}
946	}
947
948	if (f64Bit)
949	iRegion++;
950	}
951	}
952
953	static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
954	{
955	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
956
957	/*
958	* Check input.
959	*/
960	if ( !pszName
961	\|\| !pPciDev
962	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices)
963	)
964	{
965	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
966	return VERR_INVALID_PARAMETER;
967	}
968
969	/*
970	* Register the device.
971	*/
972	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
973	}
974
975
976	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
977	{
978	NOREF(pDevIns);
979	int rc;
980
981	rc = MsiInit(pPciDev, pMsiReg);
982	if (RT_FAILURE(rc))
983	return rc;
984
985	rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
986	if (RT_FAILURE(rc))
987	return rc;
988
989	return VINF_SUCCESS;
990	}
991
992
993	static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
994	{
995
996	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
997
998	/*
999	* Check input.
1000	*/
1001	if ( !pszName
1002	\|\| !pPciDev
1003	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices))
1004	{
1005	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1006	return VERR_INVALID_PARAMETER;
1007	}
1008
1009	/*
1010	* Register the device.
1011	*/
1012	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
1013	}
1014
1015	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1016	{
1017	NOREF(pDevIns);
1018
1019	/*
1020	* Validate.
1021	*/
1022	AssertMsgReturn( enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR32)
1023	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR32)
1024	\|\| enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR64)
1025	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR64)
1026	\|\| enmType == PCI_ADDRESS_SPACE_IO
1027	,
1028	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1029	VERR_INVALID_PARAMETER);
1030	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1031	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1032	VERR_INVALID_PARAMETER);
1033	int iLastSet = ASMBitLastSetU32(cbRegion);
1034	AssertMsgReturn( iLastSet != 0
1035	&& RT_BIT_32(iLastSet - 1) == cbRegion,
1036	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1037	VERR_INVALID_PARAMETER);
1038
1039	Log(("ich9pciIORegionRegister: %s region %d size %d type %x\n",
1040	pPciDev->name, iRegion, cbRegion, enmType));
1041
1042	/* Make sure that we haven't marked this region as continuation of 64-bit region. */
1043	Assert(pPciDev->Int.s.aIORegions[iRegion].type != 0xff);
1044
1045	/*
1046	* Register the I/O region.
1047	*/
1048	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1049	pRegion->addr = INVALID_PCI_ADDRESS;
1050	pRegion->size = cbRegion;
1051	pRegion->type = enmType;
1052	pRegion->map_func = pfnCallback;
1053
1054	if ((enmType & PCI_ADDRESS_SPACE_BAR64) != 0)
1055	{
1056	/* VBOX_PCI_BASE_ADDRESS_5 and VBOX_PCI_ROM_ADDRESS are excluded. */
1057	AssertMsgReturn(iRegion < (PCI_NUM_REGIONS-2),
1058	("Region %d cannot be 64-bit\n", iRegion),
1059	VERR_INVALID_PARAMETER);
1060	/* Mark next region as continuation of this one. */
1061	pPciDev->Int.s.aIORegions[iRegion+1].type = 0xff;
1062	}
1063
1064	/* Set type in the PCI config space. */
1065	uint32_t u32Value = ((uint32_t)enmType) & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH);
1066	PCIDevSetDWord(pPciDev, ich9pciGetRegionReg(iRegion), u32Value);
1067
1068	return VINF_SUCCESS;
1069	}
1070
1071	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1072	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1073	{
1074	NOREF(pDevIns);
1075
1076	if (ppfnReadOld)
1077	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1078	pPciDev->Int.s.pfnConfigRead = pfnRead;
1079
1080	if (ppfnWriteOld)
1081	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1082	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1083	}
1084
1085	static int ich9pciR3CommonSaveExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM)
1086	{
1087	/*
1088	* Iterate thru all the devices.
1089	*/
1090	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1091	{
1092	PPCIDEVICE pDev = pBus->apDevices[i];
1093	if (pDev)
1094	{
1095	/* Device position */
1096	SSMR3PutU32(pSSM, i);
1097	/* PCI config registers */
1098	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1099
1100	/* Device flags */
1101	int rc = SSMR3PutU32(pSSM, pDev->Int.s.fFlags);
1102	if (RT_FAILURE(rc))
1103	return rc;
1104
1105	/* IRQ pin state */
1106	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1107	if (RT_FAILURE(rc))
1108	return rc;
1109
1110	/* MSI info */
1111	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
1112	if (RT_FAILURE(rc))
1113	return rc;
1114	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
1115	if (RT_FAILURE(rc))
1116	return rc;
1117
1118	/* MSI-X info */
1119	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
1120	if (RT_FAILURE(rc))
1121	return rc;
1122	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
1123	if (RT_FAILURE(rc))
1124	return rc;
1125	/* Save MSI-X page state */
1126	if (pDev->Int.s.u8MsixCapOffset != 0)
1127	{
1128	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1129	SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
1130	if (RT_FAILURE(rc))
1131	return rc;
1132	}
1133	}
1134	}
1135	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1136	}
1137
1138	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1139	{
1140	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1141
1142	/*
1143	* Bus state data.
1144	*/
1145	SSMR3PutU32(pSSM, pThis->uConfigReg);
1146
1147	/*
1148	* Save IRQ states.
1149	*/
1150	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1151	SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
1152
1153	SSMR3PutU32(pSSM, UINT32_MAX); /* separator */
1154
1155	return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
1156	}
1157
1158
1159	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1160	{
1161	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1162	return ich9pciR3CommonSaveExec(pThis, pSSM);
1163	}
1164
1165
1166	static DECLCALLBACK(void) ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1167	{
1168	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1169
1170	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1171
1172	/* If the current bus is not the target bus search for the bus which contains the device. */
1173	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1174	{
1175	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1176	if (pBridgeDevice)
1177	{
1178	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1179	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
1180	}
1181	}
1182	else
1183	{
1184	/* This is the target bus, pass the write to the device. */
1185	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1186	if (pPciDev)
1187	{
1188	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1189	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
1190	}
1191	}
1192	}
1193
1194	static DECLCALLBACK(uint32_t) ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1195	{
1196	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1197	uint32_t u32Value;
1198
1199	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1200
1201	/* If the current bus is not the target bus search for the bus which contains the device. */
1202	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1203	{
1204	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1205	if (pBridgeDevice)
1206	{
1207	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1208	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
1209	}
1210	else
1211	ich9pciNoMem(&u32Value, 4);
1212	}
1213	else
1214	{
1215	/* This is the target bus, pass the read to the device. */
1216	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1217	if (pPciDev)
1218	{
1219	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
1220	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1221	}
1222	else
1223	ich9pciNoMem(&u32Value, 4);
1224	}
1225
1226	return u32Value;
1227	}
1228
1229
1230	/**
1231	* Common routine for restoring the config registers of a PCI device.
1232	*
1233	* @param pDev The PCI device.
1234	* @param pbSrcConfig The configuration register values to be loaded.
1235	* @param fIsBridge Whether this is a bridge device or not.
1236	*/
1237	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1238	{
1239	/*
1240	* This table defines the fields for normal devices and bridge devices, and
1241	* the order in which they need to be restored.
1242	*/
1243	static const struct PciField
1244	{
1245	uint8_t off;
1246	uint8_t cb;
1247	uint8_t fWritable;
1248	uint8_t fBridge;
1249	const char *pszName;
1250	} s_aFields[] =
1251	{
1252	/* off,cb,fW,fB, pszName */
1253	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1254	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1255	{ 0x06, 2, 1, 3, "STATUS" },
1256	{ 0x08, 1, 0, 3, "REVISION_ID" },
1257	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1258	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1259	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1260	{ 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },
1261	{ 0x0d, 1, 1, 3, "LATENCY_TIMER" },
1262	{ 0x0e, 1, 0, 3, "HEADER_TYPE" },
1263	{ 0x0f, 1, 1, 3, "BIST" },
1264	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1265	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1266	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1267	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1268	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1269	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1270	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1271	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1272	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1273	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1274	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1275	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1276	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1277	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1278	{ 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1279	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1280	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1281	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1282	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1283	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1284	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1285	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1286	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1287	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1288	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1289	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1290	{ 0x38, 4, 1, 1, "RESERVED_38" }, // ???
1291	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1292	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1293	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1294	{ 0x3e, 1, 0, 1, "MIN_GNT" },
1295	{ 0x3e, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1296	{ 0x3f, 1, 0, 1, "MAX_LAT" },
1297	/* The COMMAND register must come last as it requires the ADDRESS
1298	registers to be restored before we pretent to change it from 0 to
1299	whatever value the guest assigned it. */
1300	{ 0x04, 2, 1, 3, "COMMAND" },
1301	};
1302
1303	#ifdef RT_STRICT
1304	/* Check that we've got full register coverage. */
1305	uint32_t bmDevice[0x40 / 32];
1306	uint32_t bmBridge[0x40 / 32];
1307	RT_ZERO(bmDevice);
1308	RT_ZERO(bmBridge);
1309	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1310	{
1311	uint8_t off = s_aFields[i].off;
1312	uint8_t cb = s_aFields[i].cb;
1313	uint8_t f = s_aFields[i].fBridge;
1314	while (cb-- > 0)
1315	{
1316	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1317	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1318	if (f & 1) ASMBitSet(bmDevice, off);
1319	if (f & 2) ASMBitSet(bmBridge, off);
1320	off++;
1321	}
1322	}
1323	for (uint32_t off = 0; off < 0x40; off++)
1324	{
1325	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1326	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1327	}
1328	#endif
1329
1330	/*
1331	* Loop thru the fields covering the 64 bytes of standard registers.
1332	*/
1333	uint8_t const fBridge = fIsBridge ? 2 : 1;
1334	Assert(!pciDevIsPassthrough(pDev));
1335	uint8_t *pbDstConfig = &pDev->config[0];
1336
1337	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1338	if (s_aFields[i].fBridge & fBridge)
1339	{
1340	uint8_t const off = s_aFields[i].off;
1341	uint8_t const cb = s_aFields[i].cb;
1342	uint32_t u32Src;
1343	uint32_t u32Dst;
1344	switch (cb)
1345	{
1346	case 1:
1347	u32Src = pbSrcConfig[off];
1348	u32Dst = pbDstConfig[off];
1349	break;
1350	case 2:
1351	u32Src = (uint16_t const )&pbSrcConfig[off];
1352	u32Dst = (uint16_t const )&pbDstConfig[off];
1353	break;
1354	case 4:
1355	u32Src = (uint32_t const )&pbSrcConfig[off];
1356	u32Dst = (uint32_t const )&pbDstConfig[off];
1357	break;
1358	default:
1359	AssertFailed();
1360	continue;
1361	}
1362
1363	if ( u32Src != u32Dst
1364	\|\| off == VBOX_PCI_COMMAND)
1365	{
1366	if (u32Src != u32Dst)
1367	{
1368	if (!s_aFields[i].fWritable)
1369	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1370	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1371	else
1372	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1373	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1374	}
1375	if (off == VBOX_PCI_COMMAND)
1376	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1377	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1378	}
1379	}
1380
1381	/*
1382	* The device dependent registers.
1383	*
1384	* We will not use ConfigWrite here as we have no clue about the size
1385	* of the registers, so the device is responsible for correctly
1386	* restoring functionality governed by these registers.
1387	*/
1388	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1389	if (pbDstConfig[off] != pbSrcConfig[off])
1390	{
1391	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1392	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1393	pbDstConfig[off] = pbSrcConfig[off];
1394	}
1395	}
1396
1397	/**
1398	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1399	*
1400	* @returns VBox status code.
1401	* @param pBus The bus which data is being loaded.
1402	* @param pSSM The saved state handle.
1403	* @param uVersion The data version.
1404	* @param uPass The pass.
1405	*/
1406	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1407	{
1408	uint32_t u32;
1409	uint32_t i;
1410	int rc;
1411
1412	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1413	if (uVersion != VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT)
1414	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1415
1416	/*
1417	* Iterate thru all the devices and write 0 to the COMMAND register so
1418	* that all the memory is unmapped before we start restoring the saved
1419	* mapping locations.
1420	*
1421	* The register value is restored afterwards so we can do proper
1422	* LogRels in pciR3CommonRestoreConfig.
1423	*/
1424	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1425	{
1426	PPCIDEVICE pDev = pBus->apDevices[i];
1427	if (pDev)
1428	{
1429	uint16_t u16 = PCIDevGetCommand(pDev);
1430	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1431	PCIDevSetCommand(pDev, u16);
1432	Assert(PCIDevGetCommand(pDev) == u16);
1433	}
1434	}
1435
1436	void *pvMsixPage = RTMemTmpAllocZ(0x1000);
1437	AssertReturn(pvMsixPage, VERR_NO_TMP_MEMORY);
1438
1439	/*
1440	* Iterate all the devices.
1441	*/
1442	for (i = 0;; i++)
1443	{
1444	PPCIDEVICE pDev;
1445	PCIDEVICE DevTmp;
1446
1447	/* index / terminator */
1448	rc = SSMR3GetU32(pSSM, &u32);
1449	if (RT_FAILURE(rc))
1450	break;
1451	if (u32 == (uint32_t)~0)
1452	break;
1453	AssertMsgBreak(u32 < RT_ELEMENTS(pBus->apDevices) && u32 >= i, ("u32=%#x i=%#x\n", u32, i));
1454
1455	/* skip forward to the device checking that no new devices are present. */
1456	for (; i < u32; i++)
1457	{
1458	pDev = pBus->apDevices[i];
1459	if (pDev)
1460	{
1461	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1462	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1463	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1464	{
1465	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1466	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1467	break;
1468	}
1469	}
1470	}
1471	if (RT_FAILURE(rc))
1472	break;
1473
1474	/* get the data */
1475	DevTmp.Int.s.fFlags = 0;
1476	DevTmp.Int.s.u8MsiCapOffset = 0;
1477	DevTmp.Int.s.u8MsiCapSize = 0;
1478	DevTmp.Int.s.u8MsixCapOffset = 0;
1479	DevTmp.Int.s.u8MsixCapSize = 0;
1480	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1481	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1482
1483	SSMR3GetU32(pSSM, &DevTmp.Int.s.fFlags);
1484	SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1485	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1486	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1487	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1488	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1489	if (RT_FAILURE(rc))
1490	break;
1491
1492	/* Load MSI-X page state */
1493	if (DevTmp.Int.s.u8MsixCapOffset != 0)
1494	{
1495	Assert(pvMsixPage != NULL);
1496	rc = SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1497	if (RT_FAILURE(rc))
1498	break;
1499	}
1500
1501	/* check that it's still around. */
1502	pDev = pBus->apDevices[i];
1503	if (!pDev)
1504	{
1505	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1506	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1507	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1508	{
1509	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1510	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1511	break;
1512	}
1513	continue;
1514	}
1515
1516	/* match the vendor id assuming that this will never be changed. */
1517	if (PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1518	{
1519	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1520	i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1521	break;
1522	}
1523
1524	/* commit the loaded device config. */
1525	Assert(!pciDevIsPassthrough(pDev));
1526	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1527
1528	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1529	pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1530	pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1531	pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1532	pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1533	if (DevTmp.Int.s.u8MsixCapSize != 0)
1534	{
1535	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1536	memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1537	}
1538	}
1539
1540	RTMemTmpFree(pvMsixPage);
1541
1542	return rc;
1543	}
1544
1545	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1546	{
1547	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1548	PICH9PCIBUS pBus = &pThis->aPciBus;
1549	uint32_t u32;
1550	int rc;
1551
1552	/* We ignore this version as there's no saved state with it anyway */
1553	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1554	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1555	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1556	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1557
1558	/*
1559	* Bus state data.
1560	*/
1561	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1562
1563	/*
1564	* Load IRQ states.
1565	*/
1566	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1567	SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1568
1569	/* separator */
1570	rc = SSMR3GetU32(pSSM, &u32);
1571	if (RT_FAILURE(rc))
1572	return rc;
1573	if (u32 != (uint32_t)~0)
1574	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1575
1576	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1577	}
1578
1579	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1580	{
1581	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1582	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1583	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1584	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1585	}
1586
1587
1588	/*
1589	* Perform imeediate read of configuration space register.
1590	* Cannot be rescheduled, as already in R3.
1591	*/
1592	static uint32_t ich9pciConfigRead(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1593	{
1594	PciAddress aPciAddr;
1595	aPciAddr.iBus = uBus;
1596	aPciAddr.iDeviceFunc = uDevFn;
1597	aPciAddr.iRegister = addr;
1598
1599	uint32_t u32Val;
1600	int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR);
1601	AssertRC(rc);
1602
1603	return u32Val;
1604	}
1605
1606
1607	/*
1608	* Perform imeediate write to configuration space register.
1609	* Cannot be rescheduled, as already in R3.
1610	*/
1611	static void ich9pciConfigWrite(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1612	{
1613	PciAddress aPciAddr;
1614	aPciAddr.iBus = uBus;
1615	aPciAddr.iDeviceFunc = uDevFn;
1616	aPciAddr.iRegister = addr;
1617
1618	int rc = ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VERR_INTERNAL_ERROR);
1619	AssertRC(rc);
1620	}
1621
1622
1623	static void ich9pciSetRegionAddress(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
1624	{
1625	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1626
1627	/* Read memory type first. */
1628	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1629
1630	Log(("Set region address: %02x:%02x.%d region %d address=%lld\n",
1631	uBus, uDevFn >> 3, uDevFn & 7, iRegion, addr));
1632
1633	bool f64Bit = (uResourceType & PCI_ADDRESS_SPACE_BAR64) != 0;
1634
1635	/* Write address of the device. */
1636	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, (uint32_t)addr, 4);
1637	if (f64Bit)
1638	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg + 4, (uint32_t)(addr >> 32), 4);
1639	}
1640
1641
1642	static void ich9pciBiosInitBridge(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1643	{
1644	Log(("BIOS init bridge: %02x::%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1645
1646	/*
1647	* The I/O range for the bridge must be aligned to a 4KB boundary.
1648	* This does not change anything really as the access to the device is not going
1649	* through the bridge but we want to be compliant to the spec.
1650	*/
1651	if ((pGlobals->uPciBiosIo % 4096) != 0)
1652	{
1653	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1654	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1655	}
1656	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1657
1658	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1659	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1660	{
1661	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1662	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1663	}
1664	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1665
1666	/* Save values to compare later to. */
1667	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1668	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1669	uint8_t uBridgeBus = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, 1);
1670
1671	/* Init devices behind the bridge and possibly other bridges as well. */
1672	for (int iDev = 0; iDev <= 255; iDev++)
1673	ich9pciBiosInitDevice(pGlobals, uBridgeBus, iDev);
1674
1675	/*
1676	* Set I/O limit register. If there is no device with I/O space behind the bridge
1677	* we set a lower value than in the base register.
1678	* The result with a real bridge is that no I/O transactions are passed to the secondary
1679	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1680	*/
1681	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1682	{
1683	/* The upper boundary must be one byte less than a 4KB boundary. */
1684	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1685	}
1686
1687	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1688
1689	/* Same with the MMIO limit register but with 1MB boundary here. */
1690	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1691	{
1692	/* The upper boundary must be one byte less than a 1MB boundary. */
1693	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1694	}
1695	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1696
1697	/*
1698	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1699	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1700	* the base register than in the limit register.
1701	*/
1702	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1703	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1704	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1705	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1706	}
1707
1708	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1709	{
1710	uint16_t uDevClass, uVendor, uDevice;
1711	uint8_t uCmd;
1712
1713	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1714	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1715	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1716
1717	/* If device is present */
1718	if (uVendor == 0xffff)
1719	return;
1720
1721	Log(("BIOS init device: %02x:%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1722
1723	switch (uDevClass)
1724	{
1725	case 0x0101:
1726	/* IDE controller */
1727	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1728	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1729	goto default_map;
1730	break;
1731	case 0x0300:
1732	/* VGA controller */
1733	if (uVendor != 0x80ee)
1734	goto default_map;
1735	/* VGA: map frame buffer to default Bochs VBE address */
1736	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0xE0000000);
1737	/*
1738	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1739	* only the framebuffer (i.e., a memory region) is explicitly registered via
1740	* ich9pciSetRegionAddress, so don't forget to enable I/O decoding.
1741	*/
1742	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1743	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1744	uCmd \| PCI_COMMAND_IOACCESS \| PCI_COMMAND_MEMACCESS,
1745	1);
1746	break;
1747	case 0x0604:
1748	/* PCI-to-PCI bridge. */
1749	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1750	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn);
1751	break;
1752	default:
1753	default_map:
1754	{
1755	/* default memory mappings */
1756	bool fActiveMemRegion = false;
1757	bool fActiveIORegion = false;
1758	/*
1759	* We ignore ROM region here.
1760	*/
1761	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1762	{
1763	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1764
1765	/* Calculate size - we write all 1s into the BAR, and then evaluate which bits
1766	are cleared. */
1767	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1768
1769	bool f64bit = (u8ResourceType & PCI_ADDRESS_SPACE_BAR64) != 0;
1770	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1771	uint64_t cbRegSize64 = 0;
1772
1773	if (f64bit)
1774	{
1775	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1776	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0xffffffff), 4);
1777	cbRegSize64 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1778	cbRegSize64 \|= ((uint64_t)ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address+4, 4) << 32);
1779	cbRegSize64 &= ~UINT64_C(0x0f);
1780	cbRegSize64 = (~cbRegSize64) + 1;
1781
1782	/* No 64-bit PIO regions possible. */
1783	#ifndef DEBUG_bird /* EFI triggers this for DevAHCI. */
1784	AssertMsg((u8ResourceType & PCI_COMMAND_IOACCESS) == 0, ("type=%#x rgn=%d\n", u8ResourceType, iRegion));
1785	#endif
1786	}
1787	else
1788	{
1789	uint32_t cbRegSize32;
1790	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1791	cbRegSize32 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1792
1793	/* Clear resource information depending on resource type. */
1794	if (fIsPio) /* PIO */
1795	cbRegSize32 &= ~UINT32_C(0x01);
1796	else /* MMIO */
1797	cbRegSize32 &= ~UINT32_C(0x0f);
1798
1799	/*
1800	* Invert all bits and add 1 to get size of the region.
1801	* (From PCI implementation note)
1802	*/
1803	if (fIsPio && (cbRegSize32 & UINT32_C(0xffff0000)) == 0)
1804	cbRegSize32 = (~(cbRegSize32 \| UINT32_C(0xffff0000))) + 1;
1805	else
1806	cbRegSize32 = (~cbRegSize32) + 1;
1807
1808	cbRegSize64 = cbRegSize32;
1809	}
1810	#ifndef DEBUG_bird /* EFI triggers this for DevAHCI. */
1811	Assert(cbRegSize64 == (uint32_t)cbRegSize64);
1812	#endif
1813	Log2(("%s: Size of region %u for device %d on bus %d is %lld\n", __FUNCTION__, iRegion, uDevFn, uBus, cbRegSize64));
1814
1815	if (cbRegSize64)
1816	{
1817	/** @todo r=klaus make this code actually handle 64-bit BARs, especially MMIO which can't possibly fit into the memory hole. */
1818	uint32_t cbRegSize32 = (uint32_t)cbRegSize64;
1819	uint32_t* paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1820	uint32_t uNew = *paddr;
1821	uNew = (uNew + cbRegSize32 - 1) & ~(cbRegSize32 - 1);
1822	if (fIsPio)
1823	uNew &= UINT32_C(0xffff);
1824	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
1825	if (!uNew \|\| (uNew <= UINT32_C(0xffffffff) && uNew + cbRegSize32 - 1 >= UINT32_C(0xfec00000)))
1826	{
1827	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
1828	iRegion, uBus, uDevFn >> 3, uDevFn & 7, uVendor, uDevice)); /** @todo make this a VM start failure later. */
1829	/* Undo the mapping mess caused by the size probing. */
1830	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0), 4);
1831	if (f64bit)
1832	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0), 4);
1833	}
1834	else
1835	{
1836	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, uNew));
1837	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
1838	if (fIsPio)
1839	fActiveIORegion = true;
1840	else
1841	fActiveMemRegion = true;
1842	*paddr = uNew + cbRegSize32;
1843	Log2(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1844	}
1845
1846	if (f64bit)
1847	iRegion++; /* skip next region */
1848	}
1849	}
1850
1851	/* Update the command word appropriately. */
1852	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1853	if (fActiveMemRegion)
1854	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1855	if (fActiveIORegion)
1856	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1857	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1858	break;
1859	}
1860	}
1861
1862	/* map the interrupt */
1863	uint32_t iPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1864	if (iPin != 0)
1865	{
1866	iPin--;
1867
1868	if (uBus != 0)
1869	{
1870	/* Find bus this device attached to. */
1871	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1872	while (1)
1873	{
1874	PPCIDEVICE pBridge = ich9pciFindBridge(pBus, uBus);
1875	if (!pBridge)
1876	{
1877	Assert(false);
1878	break;
1879	}
1880	if (uBus == PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS))
1881	{
1882	/* OK, found bus this device attached to. */
1883	break;
1884	}
1885	pBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1886	}
1887
1888	/* We need to go up to the host bus to see which irq pin this
1889	* device will use there. See logic in ich9pcibridgeSetIrq().
1890	*/
1891	while (pBus->iBus != 0)
1892	{
1893	/* Get the pin the device would assert on the bridge. */
1894	iPin = ((pBus->aPciDev.devfn >> 3) + iPin) & 3;
1895	pBus = pBus->aPciDev.Int.s.pBusR3;
1896	};
1897	}
1898
1899	int iIrq = aPciIrqs[ich9pciSlotGetPirq(uBus, uDevFn, iPin)];
1900	Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
1901	iPin, iIrq, uBus, uDevFn>>3, uDevFn&7));
1902	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
1903	}
1904	}
1905
1906	/**
1907	* Initializes bridges registers used for routing.
1908	*
1909	* @returns nothing.
1910	* @param pGlobals Global device instance data used to generate unique bus numbers.
1911	* @param pBus The PCI bus to initialize.
1912	* @param uBusPrimary The primary bus number the bus is connected to.
1913	* @param uBusSecondary The secondary bus number, i.e. the bus number behind the bridge.
1914	*/
1915	static void ich9pciInitBridgeTopology(PICH9PCIGLOBALS pGlobals, PICH9PCIBUS pBus, unsigned uBusPrimary,
1916	unsigned uBusSecondary)
1917	{
1918	PPCIDEVICE pBridgeDev = &pBus->aPciDev;
1919
1920	/* Set only if we are not on the root bus, it has no primary bus attached. */
1921	if (uBusSecondary != 0)
1922	{
1923	PCIDevSetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, uBusPrimary);
1924	PCIDevSetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, uBusSecondary);
1925	}
1926
1927	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1928	{
1929	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
1930	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
1931	("Device is not a PCI bridge but on the list of PCI bridges\n"));
1932	PICH9PCIBUS pChildBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1933	pGlobals->uBus++;
1934	ich9pciInitBridgeTopology(pGlobals, pChildBus, uBusSecondary, pGlobals->uBus);
1935	}
1936	PCIDevSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1937	Log2(("ich9pciInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
1938	pBus,
1939	PCIDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
1940	PCIDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
1941	PCIDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS)
1942	));
1943	}
1944
1945
1946	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1947	{
1948	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1949
1950	/*
1951	* Set the start addresses.
1952	*/
1953	pGlobals->uPciBiosIo = 0xd000;
1954	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
1955	pGlobals->uBus = 0;
1956
1957	/*
1958	* Assign bridge topology, for further routing to work.
1959	*/
1960	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1961	ich9pciInitBridgeTopology(pGlobals, pBus, 0, 0);
1962
1963	/*
1964	* Init the devices.
1965	*/
1966	for (int i = 0; i < 256; i++)
1967	ich9pciBiosInitDevice(pGlobals, 0, i);
1968
1969	return VINF_SUCCESS;
1970	}
1971
1972
1973	/*
1974	* Configuration space read callback (PCIDEVICEINT::pfnConfigRead) for
1975	* connected devices.
1976	*/
1977	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len)
1978	{
1979	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1980	{
1981	LogRel(("PCI: %8s/%u: Read from extended register %d fallen back to generic code\n",
1982	aDev->name, aDev->pDevIns->iInstance, u32Address));
1983	return 0;
1984	}
1985
1986	AssertMsgReturn(u32Address + len <= 256, ("Read after the end of PCI config space\n"),
1987	0);
1988	if ( pciDevIsMsiCapable(aDev)
1989	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1990	&& (u32Address < (unsigned)(aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize))
1991	)
1992	{
1993	return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1994	}
1995
1996	if ( pciDevIsMsixCapable(aDev)
1997	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
1998	&& (u32Address < (unsigned)(aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize))
1999	)
2000	{
2001	return MsixPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
2002	}
2003
2004	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
2005	0);
2006	switch (len)
2007	{
2008	case 1:
2009	return PCIDevGetByte(aDev, u32Address);
2010	case 2:
2011	return PCIDevGetWord(aDev, u32Address);
2012	case 4:
2013	return PCIDevGetDWord(aDev, u32Address);
2014	default:
2015	Assert(false);
2016	return 0;
2017	}
2018	}
2019
2020
2021	DECLINLINE(void) ich9pciWriteBarByte(PCIDevice *aDev, int iRegion, int iOffset, uint8_t u8Val)
2022	{
2023	PCIIORegion * pRegion = &aDev->Int.s.aIORegions[iRegion];
2024	int64_t iRegionSize = pRegion->size;
2025
2026	Log3(("ich9pciWriteBarByte: region=%d off=%d val=%x size=%d\n",
2027	iRegion, iOffset, u8Val, iRegionSize));
2028
2029	if (iOffset > 3)
2030	Assert((pRegion->type & PCI_ADDRESS_SPACE_BAR64) != 0);
2031
2032	/* Check if we're writing to upper part of 64-bit BAR. */
2033	if (pRegion->type == 0xff)
2034	{
2035	ich9pciWriteBarByte(aDev, iRegion-1, iOffset+4, u8Val);
2036	return;
2037	}
2038
2039	/* Region doesn't exist */
2040	if (iRegionSize == 0)
2041	return;
2042
2043	uint32_t uAddr = ich9pciGetRegionReg(iRegion) + iOffset;
2044	/* Region size must be power of two */
2045	Assert((iRegionSize & (iRegionSize - 1)) == 0);
2046	uint8_t uMask = ((iRegionSize - 1) >> (iOffset*8) ) & 0xff;
2047
2048	if (iOffset == 0)
2049	{
2050	uMask \|= (pRegion->type & PCI_ADDRESS_SPACE_IO) ?
2051	(1 << 2) - 1 /* 2 lowest bits for IO region */ :
2052	(1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
2053
2054	}
2055
2056	uint8_t u8Old = PCIDevGetByte(aDev, uAddr) & uMask;
2057	u8Val = (u8Old & uMask) \| (u8Val & ~uMask);
2058
2059	Log3(("ich9pciWriteBarByte: was %x writing %x\n", u8Old, u8Val));
2060
2061	PCIDevSetByte(aDev, uAddr, u8Val);
2062	}
2063
2064
2065	/**
2066	* Configuration space write callback (PCIDEVICEINT::pfnConfigWrite)
2067	* for connected devices.
2068	*
2069	* See paragraph 7.5 of PCI Express specification (p. 349) for
2070	* definition of registers and their writability policy.
2071	*/
2072	static DECLCALLBACK(void) ich9pciConfigWriteDev(PCIDevice *aDev, uint32_t u32Address,
2073	uint32_t val, unsigned len)
2074	{
2075	Assert(len <= 4);
2076
2077	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
2078	{
2079	LogRel(("PCI: %8s/%u: Write to extended register %d fallen back to generic code\n",
2080	aDev->name, aDev->pDevIns->iInstance, u32Address));
2081	return;
2082	}
2083
2084	AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
2085
2086	if ( pciDevIsMsiCapable(aDev)
2087	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
2088	&& (u32Address < (unsigned)(aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize))
2089	)
2090	{
2091	MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2092	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2093	aDev, u32Address, val, len);
2094	return;
2095	}
2096
2097	if ( pciDevIsMsixCapable(aDev)
2098	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
2099	&& (u32Address < (unsigned)(aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize))
2100	)
2101	{
2102	MsixPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2103	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2104	aDev, u32Address, val, len);
2105	return;
2106	}
2107
2108	uint32_t addr = u32Address;
2109	bool fUpdateMappings = false;
2110	bool fP2PBridge = false;
2111	/bool fPassthrough = pciDevIsPassthrough(aDev);/
2112	uint8_t u8HeaderType = ich9pciGetByte(aDev, VBOX_PCI_HEADER_TYPE);
2113
2114	for (uint32_t i = 0; i < len; i++)
2115	{
2116	bool fWritable = false;
2117	bool fRom = false;
2118	switch (u8HeaderType)
2119	{
2120	case 0x00: /* normal device */
2121	case 0x80: /* multi-function device */
2122	switch (addr)
2123	{
2124	/* Read-only registers */
2125	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2126	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2127	case VBOX_PCI_REVISION_ID:
2128	case VBOX_PCI_CLASS_PROG:
2129	case VBOX_PCI_CLASS_SUB:
2130	case VBOX_PCI_CLASS_BASE:
2131	case VBOX_PCI_HEADER_TYPE:
2132	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
2133	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
2134	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
2135	case VBOX_PCI_CAPABILITY_LIST:
2136	case VBOX_PCI_INTERRUPT_PIN:
2137	fWritable = false;
2138	break;
2139	/* Others can be written */
2140	default:
2141	fWritable = true;
2142	break;
2143	}
2144	break;
2145	case 0x01: /* PCI-PCI bridge */
2146	fP2PBridge = true;
2147	switch (addr)
2148	{
2149	/* Read-only registers */
2150	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2151	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2152	case VBOX_PCI_REVISION_ID:
2153	case VBOX_PCI_CLASS_PROG:
2154	case VBOX_PCI_CLASS_SUB:
2155	case VBOX_PCI_CLASS_BASE:
2156	case VBOX_PCI_HEADER_TYPE:
2157	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
2158	case VBOX_PCI_INTERRUPT_PIN:
2159	fWritable = false;
2160	break;
2161	default:
2162	fWritable = true;
2163	break;
2164	}
2165	break;
2166	default:
2167	AssertMsgFailed(("Unknown header type %x\n", PCIDevGetHeaderType(aDev)));
2168	fWritable = false;
2169	break;
2170	}
2171
2172	uint8_t u8Val = (uint8_t)val;
2173	switch (addr)
2174	{
2175	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
2176	fUpdateMappings = true;
2177	goto default_case;
2178	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
2179	/* don't change reserved bits (11-15) */
2180	u8Val &= ~UINT32_C(0xf8);
2181	fUpdateMappings = true;
2182	goto default_case;
2183	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
2184	/* don't change read-only bits => actually all lower bits are read-only */
2185	u8Val &= ~UINT32_C(0xff);
2186	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
2187	aDev->config[addr] &= ~u8Val;
2188	break;
2189	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
2190	/* don't change read-only bits */
2191	u8Val &= ~UINT32_C(0x06);
2192	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
2193	aDev->config[addr] &= ~u8Val;
2194	break;
2195	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3:
2196	fRom = true;
2197	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
2198	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
2199	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
2200	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
2201	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
2202	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
2203	{
2204	/* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
2205	if (fP2PBridge)
2206	goto default_case;
2207	else
2208	{
2209	int iRegion = fRom ? VBOX_PCI_ROM_SLOT : (addr - VBOX_PCI_BASE_ADDRESS_0) >> 2;
2210	int iOffset = addr & 0x3;
2211	ich9pciWriteBarByte(aDev, iRegion, iOffset, u8Val);
2212	fUpdateMappings = true;
2213	}
2214	break;
2215	}
2216	default:
2217	default_case:
2218	if (fWritable)
2219	PCIDevSetByte(aDev, addr, u8Val);
2220	}
2221	addr++;
2222	val >>= 8;
2223	}
2224
2225	if (fUpdateMappings)
2226	/* if the command/base address register is modified, we must modify the mappings */
2227	ich9pciUpdateMappings(aDev);
2228	}
2229
2230	static bool assignPosition(PICH9PCIBUS pBus, PPCIDEVICE pPciDev, const char pszName, int iDevFn, PciAddress aPosition)
2231	{
2232	NOREF(pszName);
2233	aPosition->iBus = 0;
2234	aPosition->iDeviceFunc = iDevFn;
2235	aPosition->iRegister = 0; /* N/A */
2236
2237	/* Explicit slot request */
2238	if (iDevFn >= 0 && iDevFn < (int)RT_ELEMENTS(pBus->apDevices))
2239	return true;
2240
2241	int iStartPos = 0;
2242
2243	/* Otherwise when assigning a slot, we need to make sure all its functions are available */
2244	for (int iPos = iStartPos; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
2245	{
2246	if ( !pBus->apDevices[iPos]
2247	&& !pBus->apDevices[iPos + 1]
2248	&& !pBus->apDevices[iPos + 2]
2249	&& !pBus->apDevices[iPos + 3]
2250	&& !pBus->apDevices[iPos + 4]
2251	&& !pBus->apDevices[iPos + 5]
2252	&& !pBus->apDevices[iPos + 6]
2253	&& !pBus->apDevices[iPos + 7])
2254	{
2255	pciDevClearRequestedDevfunc(pPciDev);
2256	aPosition->iDeviceFunc = iPos;
2257	return true;
2258	}
2259	}
2260
2261	return false;
2262	}
2263
2264	#ifdef SOME_UNUSED_FUNCTION
2265	static bool hasHardAssignedDevsInSlot(PICH9PCIBUS pBus, int iSlot)
2266	{
2267	PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
2268
2269	return (aSlot[0] && pciDevIsRequestedDevfunc(aSlot[0]))
2270	\|\| (aSlot[1] && pciDevIsRequestedDevfunc(aSlot[1]))
2271	\|\| (aSlot[2] && pciDevIsRequestedDevfunc(aSlot[2]))
2272	\|\| (aSlot[3] && pciDevIsRequestedDevfunc(aSlot[3]))
2273	\|\| (aSlot[4] && pciDevIsRequestedDevfunc(aSlot[4]))
2274	\|\| (aSlot[5] && pciDevIsRequestedDevfunc(aSlot[5]))
2275	\|\| (aSlot[6] && pciDevIsRequestedDevfunc(aSlot[6]))
2276	\|\| (aSlot[7] && pciDevIsRequestedDevfunc(aSlot[7]))
2277	;
2278	}
2279	#endif
2280
2281	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
2282	{
2283	PciAddress aPosition;
2284	aPosition.iBus = 0;
2285	aPosition.iDeviceFunc = 0;
2286	aPosition.iRegister = 0;
2287
2288	/*
2289	* Find device position
2290	*/
2291	if (!assignPosition(pBus, pPciDev, pszName, iDev, &aPosition))
2292	{
2293	AssertMsgFailed(("Couldn't asssign position!\n"));
2294	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2295	}
2296
2297	AssertMsgReturn(aPosition.iBus == 0,
2298	("Assigning behind the bridge not implemented yet\n"),
2299	VERR_PDM_TOO_PCI_MANY_DEVICES);
2300
2301
2302	iDev = aPosition.iDeviceFunc;
2303	/*
2304	* Check if we can really take this slot, possibly by relocating
2305	* its current habitant, if it wasn't hard assigned too.
2306	*/
2307	if (pciDevIsRequestedDevfunc(pPciDev) &&
2308	pBus->apDevices[iDev] &&
2309	pciDevIsRequestedDevfunc(pBus->apDevices[iDev]))
2310	{
2311	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
2312	pszName, pBus->apDevices[iDev]->name, iDev));
2313	return VERR_INTERNAL_ERROR;
2314	}
2315
2316	if (pBus->apDevices[iDev])
2317	{
2318	/* if we got here, we shall (and usually can) relocate the device */
2319	bool assigned = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name, -1, &aPosition);
2320	AssertMsgReturn(aPosition.iBus == 0,
2321	("Assigning behind the bridge not implemented yet\n"),
2322	VERR_PDM_TOO_PCI_MANY_DEVICES);
2323	int iRelDev = aPosition.iDeviceFunc;
2324	if (!assigned \|\| iRelDev == iDev)
2325	{
2326	AssertMsgFailed(("Couldn't find free spot!\n"));
2327	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2328	}
2329	/* Copy device function by function to its new position */
2330	for (int i = 0; i < 8; i++)
2331	{
2332	if (!pBus->apDevices[iDev + i])
2333	continue;
2334	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
2335	pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
2336	pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
2337	pBus->apDevices[iDev + i] = NULL;
2338	}
2339	}
2340
2341	/*
2342	* Fill in device information.
2343	*/
2344	pPciDev->devfn = iDev;
2345	pPciDev->name = pszName;
2346	pPciDev->Int.s.pBusR3 = pBus;
2347	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2348	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2349	pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
2350	pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
2351	pBus->apDevices[iDev] = pPciDev;
2352	if (pciDevIsPci2PciBridge(pPciDev))
2353	{
2354	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2355	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2356	("device is a bridge but does not implement read/write functions\n"));
2357	Log2(("Setting bridge %d on bus %p\n", pBus->cBridges, pBus));
2358	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2359	pBus->cBridges++;
2360	}
2361
2362	Log(("PCI: Registered device %d function %d on bus %d (%#x) '%s'.\n",
2363	iDev >> 3, iDev & 7, pBus->iBus, 0x80000000 \| (iDev << 8), pszName));
2364
2365	return VINF_SUCCESS;
2366	}
2367
2368	static void printIndent(PCDBGFINFOHLP pHlp, int iIndent)
2369	{
2370	for (int i = 0; i < iIndent; i++)
2371	{
2372	pHlp->pfnPrintf(pHlp, " ");
2373	}
2374	}
2375
2376	static void ich9pciBusInfo(PICH9PCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
2377	{
2378	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2379	{
2380	PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2381	if (pPciDev != NULL)
2382	{
2383	printIndent(pHlp, iIndent);
2384
2385	/*
2386	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2387	* as host driver handles real devices interrupts.
2388	*/
2389	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x",
2390	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2391	pPciDev->name,
2392	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2393	ich9pciGetWord(pPciDev, VBOX_PCI_VENDOR_ID), ich9pciGetWord(pPciDev, VBOX_PCI_DEVICE_ID)
2394	);
2395	if (ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2396	{
2397	pHlp->pfnPrintf(pHlp, " IRQ%d", ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2398	pHlp->pfnPrintf(pHlp, " (INTA#->IRQ%d)", 0x10 + ich9pciSlot2ApicIrq(iDev >> 3, 0));
2399	}
2400	pHlp->pfnPrintf(pHlp, "\n");
2401
2402	if (pciDevIsMsiCapable(pPciDev) \|\| pciDevIsMsixCapable(pPciDev))
2403	{
2404	printIndent(pHlp, iIndent + 2);
2405
2406	if (pciDevIsMsiCapable(pPciDev))
2407	pHlp->pfnPrintf(pHlp, "MSI:%s ", MsiIsEnabled(pPciDev) ? "on" : "off");
2408
2409	if (pciDevIsMsixCapable(pPciDev))
2410	pHlp->pfnPrintf(pHlp, "MSI-X:%s ", MsixIsEnabled(pPciDev) ? "on" : "off");
2411
2412	pHlp->pfnPrintf(pHlp, "\n");
2413	}
2414
2415	uint16_t iCmd = ich9pciGetWord(pPciDev, VBOX_PCI_COMMAND);
2416	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
2417	{
2418	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2419	{
2420	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2421	uint64_t iRegionSize = pRegion->size;
2422
2423	if (iRegionSize == 0)
2424	continue;
2425
2426	uint32_t u32Addr = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion));
2427	const char * pszDesc;
2428	char szDescBuf[128];
2429
2430	bool f64Bit = !!(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
2431	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2432	{
2433	pszDesc = "IO";
2434	u32Addr &= ~0x3;
2435	}
2436	else
2437	{
2438	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2439	f64Bit ? "64" : "32",
2440	(pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
2441	pszDesc = szDescBuf;
2442	u32Addr &= ~0xf;
2443	}
2444
2445	printIndent(pHlp, iIndent + 2);
2446	pHlp->pfnPrintf(pHlp, "%s region #%d: %x..%x\n",
2447	pszDesc, iRegion, u32Addr, u32Addr+iRegionSize);
2448	if (f64Bit)
2449	iRegion++;
2450	}
2451	}
2452
2453	printIndent(pHlp, iIndent + 2);
2454	uint16_t iStatus = ich9pciGetWord(pPciDev, VBOX_PCI_STATUS);
2455	pHlp->pfnPrintf(pHlp, "Command: %04X, Status: %04X\n",
2456	iCmd, iStatus);
2457	printIndent(pHlp, iIndent + 2);
2458	pHlp->pfnPrintf(pHlp, "Bus master: %s\n",
2459	iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2460
2461	if (fRegisters)
2462	{
2463	printIndent(pHlp, iIndent + 2);
2464	pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2465	for (int iReg = 0; iReg < 0x100; )
2466	{
2467	int iPerLine = 0x10;
2468	Assert (0x100 % iPerLine == 0);
2469	printIndent(pHlp, iIndent + 3);
2470
2471	while (iPerLine-- > 0)
2472	{
2473	pHlp->pfnPrintf(pHlp, "%02x ", ich9pciGetByte(pPciDev, iReg++));
2474	}
2475	pHlp->pfnPrintf(pHlp, "\n");
2476	}
2477	}
2478	}
2479	}
2480
2481	if (pBus->cBridges > 0)
2482	{
2483	printIndent(pHlp, iIndent);
2484	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2485	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2486	{
2487	PICH9PCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PICH9PCIBUS);
2488	ich9pciBusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2489	}
2490	}
2491	}
2492
2493	/**
2494	* Info handler, device version.
2495	*
2496	* @param pDevIns Device instance which registered the info.
2497	* @param pHlp Callback functions for doing output.
2498	* @param pszArgs Argument string. Optional and specific to the handler.
2499	*/
2500	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2501	{
2502	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2503
2504	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2505	{
2506	ich9pciBusInfo(pBus, pHlp, 0, false);
2507	}
2508	else if (!strcmp(pszArgs, "verbose"))
2509	{
2510	ich9pciBusInfo(pBus, pHlp, 0, true);
2511	}
2512	else
2513	{
2514	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2515	}
2516	}
2517
2518
2519	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2520	{
2521	RT_NOREF1(iInstance);
2522	Assert(iInstance == 0);
2523	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2524
2525	/*
2526	* Validate and read configuration.
2527	*/
2528	if (!CFGMR3AreValuesValid(pCfg,
2529	"IOAPIC\0"
2530	"GCEnabled\0"
2531	"R0Enabled\0"
2532	"McfgBase\0"
2533	"McfgLength\0"
2534	))
2535	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2536
2537	/* query whether we got an IOAPIC */
2538	bool fUseIoApic;
2539	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2540	if (RT_FAILURE(rc))
2541	return PDMDEV_SET_ERROR(pDevIns, rc,
2542	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2543
2544	/* check if RC code is enabled. */
2545	bool fGCEnabled;
2546	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2547	if (RT_FAILURE(rc))
2548	return PDMDEV_SET_ERROR(pDevIns, rc,
2549	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2550	/* check if R0 code is enabled. */
2551	bool fR0Enabled;
2552	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2553	if (RT_FAILURE(rc))
2554	return PDMDEV_SET_ERROR(pDevIns, rc,
2555	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2556
2557	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2558
2559	/*
2560	* Init data.
2561	*/
2562	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2563	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2564	/* Zero out everything */
2565	memset(pGlobals, 0, sizeof(*pGlobals));
2566	/* And fill values */
2567	if (!fUseIoApic)
2568	return PDMDEV_SET_ERROR(pDevIns, rc,
2569	N_("Must use IO-APIC with ICH9 chipset"));
2570	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2571	if (RT_FAILURE(rc))
2572	return PDMDEV_SET_ERROR(pDevIns, rc,
2573	N_("Configuration error: Failed to read \"McfgBase\""));
2574	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2575	if (RT_FAILURE(rc))
2576	return PDMDEV_SET_ERROR(pDevIns, rc,
2577	N_("Configuration error: Failed to read \"McfgLength\""));
2578
2579	pGlobals->pDevInsR3 = pDevIns;
2580	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2581	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2582
2583	pGlobals->aPciBus.pDevInsR3 = pDevIns;
2584	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2585	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2586	pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2587
2588	/*
2589	* Register bus
2590	*/
2591	PDMPCIBUSREG PciBusReg;
2592	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2593	PciBusReg.pfnRegisterR3 = ich9pciRegister;
2594	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2595	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2596	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2597	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2598	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2599	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2600	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2601	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2602	if (RT_FAILURE(rc))
2603	return PDMDEV_SET_ERROR(pDevIns, rc,
2604	N_("Failed to register ourselves as a PCI Bus"));
2605	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2606	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2607	N_("PCI helper version mismatch; got %#x expected %#x"),
2608	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2609
2610	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2611	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2612
2613	/*
2614	* Fill in PCI configs and add them to the bus.
2615	*/
2616	/** @todo: Disabled for now because this causes error messages with Linux guests.
2617	* The guest loads the x38_edac device which tries to map a memory region
2618	* using an address given at place 0x48 - 0x4f in the PCi config space.
2619	* This fails. because we don't register such a region.
2620	*/
2621	#if 0
2622	/* Host bridge device */
2623	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2624	PCIDevSetDeviceId( &pBus->aPciDev, 0x29e0); /* Desktop */
2625	PCIDevSetRevisionId(&pBus->aPciDev, 0x01); /* rev. 01 */
2626	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2627	PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2628	PCIDevSetClassProg( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2629	PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* bridge */
2630	PCIDevSetWord(&pBus->aPciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
2631
2632	pBus->aPciDev.pDevIns = pDevIns;
2633	/* We register Host<->PCI controller on the bus */
2634	ich9pciRegisterInternal(pBus, 0, &pBus->aPciDev, "dram");
2635	#endif
2636
2637	/*
2638	* Register I/O ports and save state.
2639	*/
2640	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2641	if (RT_FAILURE(rc))
2642	return rc;
2643	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2644	if (RT_FAILURE(rc))
2645	return rc;
2646	if (fGCEnabled)
2647	{
2648	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2649	if (RT_FAILURE(rc))
2650	return rc;
2651	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2652	if (RT_FAILURE(rc))
2653	return rc;
2654	}
2655	if (fR0Enabled)
2656	{
2657	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2658	if (RT_FAILURE(rc))
2659	return rc;
2660	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2661	if (RT_FAILURE(rc))
2662	return rc;
2663	}
2664
2665	if (pGlobals->u64PciConfigMMioAddress != 0)
2666	{
2667	rc = PDMDevHlpMMIORegister(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength, NULL /pvUser/,
2668	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
2669	ich9pciMcfgMMIOWrite, ich9pciMcfgMMIORead, "MCFG ranges");
2670	AssertMsgRCReturn(rc, ("rc=%Rrc %#llx/%#llx\n", rc, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength), rc);
2671
2672	if (fGCEnabled)
2673	{
2674	rc = PDMDevHlpMMIORegisterRC(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2675	NIL_RTRCPTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2676	AssertRCReturn(rc, rc);
2677	}
2678
2679
2680	if (fR0Enabled)
2681	{
2682	rc = PDMDevHlpMMIORegisterR0(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2683	NIL_RTR0PTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2684	AssertRCReturn(rc, rc);
2685	}
2686	}
2687
2688	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2689	sizeof(pBus) + 16128, "pgm",
2690	NULL, NULL, NULL,
2691	NULL, ich9pciR3SaveExec, NULL,
2692	NULL, ich9pciR3LoadExec, NULL);
2693	if (RT_FAILURE(rc))
2694	return rc;
2695
2696
2697	/** @todo: other chipset devices shall be registered too */
2698
2699	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. Recognizes 'basic' or 'verbose' "
2700	"as arguments, defaults to 'basic'.", ich9pciInfo);
2701
2702	return VINF_SUCCESS;
2703	}
2704
2705	static void ich9pciResetDevice(PPCIDEVICE pDev)
2706	{
2707	/* Clear regions */
2708	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2709	{
2710	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
2711	if (pRegion->size == 0)
2712	continue;
2713
2714	ich9pciUnmapRegion(pDev, iRegion);
2715	}
2716
2717	if (pciDevIsPassthrough(pDev))
2718	{
2719	// no reset handler - we can do what we need in PDM reset handler
2720	// @todo: is it correct?
2721	}
2722	else
2723	{
2724	PCIDevSetCommand(pDev,
2725	PCIDevGetCommand(pDev)
2726	&
2727	~(VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY \|
2728	VBOX_PCI_COMMAND_MASTER \| VBOX_PCI_COMMAND_SPECIAL \|
2729	VBOX_PCI_COMMAND_PARITY \| VBOX_PCI_COMMAND_SERR \|
2730	VBOX_PCI_COMMAND_FAST_BACK \| VBOX_PCI_COMMAND_INTX_DISABLE));
2731
2732	/* Bridge device reset handlers processed later */
2733	if (!pciDevIsPci2PciBridge(pDev))
2734	{
2735	PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2736	PCIDevSetInterruptLine(pDev, 0x0);
2737	}
2738
2739	/* Reset MSI message control. */
2740	if (pciDevIsMsiCapable(pDev))
2741	{
2742	/* Extracted from MsiPciConfigWrite(). */
2743	pDev->config[pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL] &= 0x8e;
2744	}
2745
2746	/* Reset MSI-X message control. */
2747	if (pciDevIsMsixCapable(pDev))
2748	{
2749	/* Extracted from MsixPciConfigWrite(); no side effects. */
2750	pDev->config[pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL + 1] &= 0x3f;
2751	}
2752	}
2753	}
2754
2755
2756	/**
2757	* @copydoc FNPDMDEVRESET
2758	*/
2759	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2760	{
2761	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2762	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2763
2764	/* PCI-specific reset for each device. */
2765	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2766	{
2767	if (pBus->apDevices[i])
2768	ich9pciResetDevice(pBus->apDevices[i]);
2769	}
2770
2771	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2772	{
2773	if (pBus->papBridgesR3[iBridge])
2774	ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->pDevIns);
2775	}
2776
2777	ich9pciFakePCIBIOS(pDevIns);
2778	}
2779
2780	static void ich9pciRelocateDevice(PPCIDEVICE pDev, RTGCINTPTR offDelta)
2781	{
2782	if (pDev)
2783	{
2784	pDev->Int.s.pBusRC += offDelta;
2785	if (pDev->Int.s.pMsixPageRC)
2786	pDev->Int.s.pMsixPageRC += offDelta;
2787	}
2788	}
2789
2790	/**
2791	* @copydoc FNPDMDEVRELOCATE
2792	*/
2793	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2794	{
2795	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2796	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2797	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2798
2799	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2800	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2801
2802	/* Relocate RC pointers for the attached pci devices. */
2803	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2804	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2805
2806	}
2807
2808	/**
2809	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2810	*/
2811	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2812	int iInstance,
2813	PCFGMNODE pCfg)
2814	{
2815	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2816
2817	/*
2818	* Validate and read configuration.
2819	*/
2820	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2821	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2822
2823	/* check if RC code is enabled. */
2824	bool fGCEnabled;
2825	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2826	if (RT_FAILURE(rc))
2827	return PDMDEV_SET_ERROR(pDevIns, rc,
2828	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2829
2830	/* check if R0 code is enabled. */
2831	bool fR0Enabled;
2832	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2833	if (RT_FAILURE(rc))
2834	return PDMDEV_SET_ERROR(pDevIns, rc,
2835	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2836	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2837
2838	/*
2839	* Init data and register the PCI bus.
2840	*/
2841	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2842	pBus->pDevInsR3 = pDevIns;
2843	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2844	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2845	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->apDevices));
2846
2847	PDMPCIBUSREG PciBusReg;
2848	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2849	PciBusReg.pfnRegisterR3 = ich9pcibridgeRegister;
2850	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2851	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2852	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2853	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2854	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2855	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2856	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2857	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2858	if (RT_FAILURE(rc))
2859	return PDMDEV_SET_ERROR(pDevIns, rc,
2860	N_("Failed to register ourselves as a PCI Bus"));
2861	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2862	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2863	N_("PCI helper version mismatch; got %#x expected %#x"),
2864	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2865
2866	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2867	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2868
2869	/* Disable default device locking. */
2870	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2871	AssertRCReturn(rc, rc);
2872
2873	/*
2874	* Fill in PCI configs and add them to the bus.
2875	*/
2876	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2877	PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2878	PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2879	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2880	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2881	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2882	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2883	PCIDevSetCommand( &pBus->aPciDev, 0x00);
2884	PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2885	PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2886
2887	/*
2888	* This device does not generate interrupts. Interrupt delivery from
2889	* devices attached to the bus is unaffected.
2890	*/
2891	PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2892
2893	pBus->aPciDev.pDevIns = pDevIns;
2894
2895	/* Bridge-specific data */
2896	pciDevSetPci2PciBridge(&pBus->aPciDev);
2897	pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2898	pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2899
2900	/*
2901	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2902	*/
2903	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2904	if (RT_FAILURE(rc))
2905	return rc;
2906
2907	/*
2908	* The iBus property doesn't really represent the bus number
2909	* because the guest and the BIOS can choose different bus numbers
2910	* for them.
2911	* The bus number is mainly for the setIrq function to indicate
2912	* when the host bus is reached which will have iBus = 0.
2913	* That's why the + 1.
2914	*/
2915	pBus->iBus = iInstance + 1;
2916
2917	/*
2918	* Register SSM handlers. We use the same saved state version as for the host bridge
2919	* to make changes easier.
2920	*/
2921	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2922	sizeof(pBus) + 16128,
2923	"pgm" /* before */,
2924	NULL, NULL, NULL,
2925	NULL, ich9pcibridgeR3SaveExec, NULL,
2926	NULL, ich9pcibridgeR3LoadExec, NULL);
2927	if (RT_FAILURE(rc))
2928	return rc;
2929
2930
2931	return VINF_SUCCESS;
2932	}
2933
2934	/**
2935	* @copydoc FNPDMDEVRESET
2936	*/
2937	static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
2938	{
2939	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2940
2941	/* Reset config space to default values. */
2942	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2943	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2944	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2945
2946	/* PCI-specific reset for each device. */
2947	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2948	{
2949	if (pBus->apDevices[i])
2950	ich9pciResetDevice(pBus->apDevices[i]);
2951	}
2952	}
2953
2954
2955	/**
2956	* @copydoc FNPDMDEVRELOCATE
2957	*/
2958	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2959	{
2960	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2961	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2962
2963	/* Relocate RC pointers for the attached pci devices. */
2964	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2965	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2966	}
2967
2968	/**
2969	* The PCI bus device registration structure.
2970	*/
2971	const PDMDEVREG g_DevicePciIch9 =
2972	{
2973	/* u32Version */
2974	PDM_DEVREG_VERSION,
2975	/* szName */
2976	"ich9pci",
2977	/* szRCMod */
2978	"VBoxDDRC.rc",
2979	/* szR0Mod */
2980	"VBoxDDR0.r0",
2981	/* pszDescription */
2982	"ICH9 PCI bridge",
2983	/* fFlags */
2984	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2985	/* fClass */
2986	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2987	/* cMaxInstances */
2988	1,
2989	/* cbInstance */
2990	sizeof(ICH9PCIGLOBALS),
2991	/* pfnConstruct */
2992	ich9pciConstruct,
2993	/* pfnDestruct */
2994	NULL,
2995	/* pfnRelocate */
2996	ich9pciRelocate,
2997	/* pfnMemSetup */
2998	NULL,
2999	/* pfnPowerOn */
3000	NULL,
3001	/* pfnReset */
3002	ich9pciReset,
3003	/* pfnSuspend */
3004	NULL,
3005	/* pfnResume */
3006	NULL,
3007	/* pfnAttach */
3008	NULL,
3009	/* pfnDetach */
3010	NULL,
3011	/* pfnQueryInterface */
3012	NULL,
3013	/* pfnInitComplete */
3014	NULL,
3015	/* pfnPowerOff */
3016	NULL,
3017	/* pfnSoftReset */
3018	NULL,
3019	/* u32VersionEnd */
3020	PDM_DEVREG_VERSION
3021	};
3022
3023	/**
3024	* The device registration structure
3025	* for the PCI-to-PCI bridge.
3026	*/
3027	const PDMDEVREG g_DevicePciIch9Bridge =
3028	{
3029	/* u32Version */
3030	PDM_DEVREG_VERSION,
3031	/* szName */
3032	"ich9pcibridge",
3033	/* szRCMod */
3034	"VBoxDDRC.rc",
3035	/* szR0Mod */
3036	"VBoxDDR0.r0",
3037	/* pszDescription */
3038	"ICH9 PCI to PCI bridge",
3039	/* fFlags */
3040	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
3041	/* fClass */
3042	PDM_DEVREG_CLASS_BUS_PCI,
3043	/* cMaxInstances */
3044	~0U,
3045	/* cbInstance */
3046	sizeof(ICH9PCIBUS),
3047	/* pfnConstruct */
3048	ich9pcibridgeConstruct,
3049	/* pfnDestruct */
3050	NULL,
3051	/* pfnRelocate */
3052	ich9pcibridgeRelocate,
3053	/* pfnMemSetup */
3054	NULL,
3055	/* pfnPowerOn */
3056	NULL,
3057	/* pfnReset */
3058	NULL, /* Must be NULL, to make sure only bus driver handles reset */
3059	/* pfnSuspend */
3060	NULL,
3061	/* pfnResume */
3062	NULL,
3063	/* pfnAttach */
3064	NULL,
3065	/* pfnDetach */
3066	NULL,
3067	/* pfnQueryInterface */
3068	NULL,
3069	/* pfnInitComplete */
3070	NULL,
3071	/* pfnPowerOff */
3072	NULL,
3073	/* pfnSoftReset */
3074	NULL,
3075	/* u32VersionEnd */
3076	PDM_DEVREG_VERSION
3077	};
3078
3079	#endif /* IN_RING3 */
3080	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 63478

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