DevPciIch9.cpp@ 63009

Last change on this file since 63009 was 62889, checked in by vboxsync, 8 years ago
Devices: warnings
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 113.1 KB

Line
1	/* $Id: DevPciIch9.cpp 62889 2016-08-02 22:34:46Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation device.
4	*
5	* @note bird: I've cleaned up DevPCI.cpp to some extent, this file has not
6	* be cleaned up and because of pending code merge.
7	*/
8
9	/*
10	* Copyright (C) 2010-2016 Oracle Corporation
11	*
12	* This file is part of VirtualBox Open Source Edition (OSE), as
13	* available from http://www.virtualbox.org. This file is free software;
14	* you can redistribute it and/or modify it under the terms of the GNU
15	* General Public License (GPL) as published by the Free Software
16	* Foundation, in version 2 as it comes in the "COPYING" file of the
17	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19	*/
20
21
22	/*********************************************************************************************************************************
23	* Header Files *
24	*********************************************************************************************************************************/
25	#define LOG_GROUP LOG_GROUP_DEV_PCI
26	/* Hack to get PCIDEVICEINT declared at the right point - include "PCIInternal.h". */
27	#define PCI_INCLUDE_PRIVATE
28	#define PCIBus ICH9PCIBus
29	#include <VBox/pci.h>
30	#include <VBox/msi.h>
31	#include <VBox/vmm/pdmdev.h>
32	#include <iprt/asm.h>
33	#include <iprt/assert.h>
34	#include <iprt/string.h>
35	#ifdef IN_RING3
36	#include <iprt/alloc.h>
37	#endif
38
39	#include "VBoxDD.h"
40	#include "MsiCommon.h"
41
42
43	/*********************************************************************************************************************************
44	* Structures and Typedefs *
45	*********************************************************************************************************************************/
46	/**
47	* PCI Bus instance.
48	*/
49	typedef struct ICH9PCIBus
50	{
51	/** Bus number. */
52	int32_t iBus;
53	/** Number of bridges attached to the bus. */
54	uint32_t cBridges;
55
56	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
57	R3PTRTYPE(PPCIDEVICE) apDevices[256];
58	/** Array of bridges attached to the bus. */
59	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
60
61	/** R3 pointer to the device instance. */
62	PPDMDEVINSR3 pDevInsR3;
63	/** Pointer to the PCI R3 helpers. */
64	PCPDMPCIHLPR3 pPciHlpR3;
65
66	/** R0 pointer to the device instance. */
67	PPDMDEVINSR0 pDevInsR0;
68	/** Pointer to the PCI R0 helpers. */
69	PCPDMPCIHLPR0 pPciHlpR0;
70
71	/** RC pointer to the device instance. */
72	PPDMDEVINSRC pDevInsRC;
73	/** Pointer to the PCI RC helpers. */
74	PCPDMPCIHLPRC pPciHlpRC;
75
76	/** The PCI device for the PCI bridge. */
77	PCIDEVICE aPciDev;
78
79	} ICH9PCIBUS, *PICH9PCIBUS;
80
81
82	/** @def PCI_APIC_IRQ_PINS
83	* Number of pins for interrupts if the APIC is used.
84	*/
85	#define PCI_APIC_IRQ_PINS 8
86
87	/**
88	* PCI Globals - This is the host-to-pci bridge and the root bus.
89	*/
90	typedef struct
91	{
92	/** R3 pointer to the device instance. */
93	PPDMDEVINSR3 pDevInsR3;
94	/** R0 pointer to the device instance. */
95	PPDMDEVINSR0 pDevInsR0;
96	/** RC pointer to the device instance. */
97	PPDMDEVINSRC pDevInsRC;
98
99	#if HC_ARCH_BITS == 64
100	uint32_t Alignment0;
101	#endif
102
103	/** Value latched in Configuration Address Port (0CF8h) */
104	uint32_t uConfigReg;
105
106	/** I/O APIC irq levels */
107	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
108
109	#if 1 /* Will be moved into the BIOS soon. */
110	/** The next I/O port address which the PCI BIOS will use. */
111	uint32_t uPciBiosIo;
112	/** The next MMIO address which the PCI BIOS will use. */
113	uint32_t uPciBiosMmio;
114	/** Actual bus number. */
115	uint8_t uBus;
116	#endif
117	/** Physical address of PCI config space MMIO region. */
118	uint64_t u64PciConfigMMioAddress;
119	/** Length of PCI config space MMIO region. */
120	uint64_t u64PciConfigMMioLength;
121
122	/** PCI bus which is attached to the host-to-PCI bridge. */
123	ICH9PCIBUS aPciBus;
124	} ICH9PCIGLOBALS, *PICH9PCIGLOBALS;
125
126
127	/**
128	* PCI configuration space address.
129	*/
130	typedef struct
131	{
132	uint8_t iBus;
133	uint8_t iDeviceFunc;
134	uint16_t iRegister;
135	} PciAddress;
136
137	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
138
139
140	/*********************************************************************************************************************************
141	* Defined Constants And Macros *
142	*********************************************************************************************************************************/
143
144	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
145	* Saved state version of the ICH9 PCI bus device.
146	*/
147	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
148	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
149	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
150
151	/** Converts a bus instance pointer to a device instance pointer. */
152	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
153	/** Converts a device instance pointer to a ICH9PCIGLOBALS pointer. */
154	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PICH9PCIGLOBALS)(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)))
155	/** Converts a device instance pointer to a PCIBUS pointer. */
156	#define DEVINS_2_PCIBUS(pDevIns) ((PICH9PCIBUS)(&PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)->aPciBus))
157	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer. */
158	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PICH9PCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(ICH9PCIGLOBALS, aPciBus)) )
159
160	/** @def PCI_LOCK
161	* Acquires the PDM lock. This is a NOP if locking is disabled. */
162	/** @def PCI_UNLOCK
163	* Releases the PDM lock. This is a NOP if locking is disabled. */
164	#define PCI_LOCK(pDevIns, rc) \
165	do { \
166	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
167	if (rc2 != VINF_SUCCESS) \
168	return rc2; \
169	} while (0)
170	#define PCI_UNLOCK(pDevIns) \
171	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
172
173	/* Prototypes */
174	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev,
175	int iIrq, int iLevel, uint32_t uTagSrc);
176	#ifdef IN_RING3
177	static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
178	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
179	static void ich9pciUpdateMappings(PCIDevice *pDev);
180	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
181	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus);
182	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn);
183	#endif
184
185	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
186	// mapping, we take n=6 approach
187	DECLINLINE(void) ich9pciPhysToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
188	{
189	NOREF(pGlobals);
190	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<6) - 1);
191	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
192	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
193	}
194
195	DECLINLINE(void) ich9pciStateToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
196	{
197	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
198	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
199	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
200	}
201
202	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
203	{
204	LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
205	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc);
206	}
207
208	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
209	{
210	/*
211	* The PCI-to-PCI bridge specification defines how the interrupt pins
212	* are routed from the secondary to the primary bus (see chapter 9).
213	* iIrq gives the interrupt pin the pci device asserted.
214	* We change iIrq here according to the spec and call the SetIrq function
215	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
216	*/
217	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
218	PPCIDEVICE pPciDevBus = pPciDev;
219	int iIrqPinBridge = iIrq;
220	uint8_t uDevFnBridge = 0;
221
222	/* Walk the chain until we reach the host bus. */
223	do
224	{
225	uDevFnBridge = pBus->aPciDev.devfn;
226	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
227
228	/* Get the parent. */
229	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
230	pPciDevBus = &pBus->aPciDev;
231	} while (pBus->iBus != 0);
232
233	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
234	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
235	}
236
237
238	/**
239	* Port I/O Handler for PCI address OUT operations.
240	*
241	* Emulates writes to Configuration Address Port at 0CF8h for
242	* Configuration Mechanism #1.
243	*
244	* @returns VBox status code.
245	*
246	* @param pDevIns ICH9 device instance.
247	* @param pvUser User argument - ignored.
248	* @param uPort Port number used for the OUT operation.
249	* @param u32 The value to output.
250	* @param cb The value size in bytes.
251	*/
252	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
253	{
254	LogFlow(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
255	RT_NOREF2(Port, pvUser);
256	if (cb == 4)
257	{
258	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
259
260	/*
261	* bits [1:0] are hard-wired, read-only and must return zeroes
262	* when read.
263	*/
264	u32 &= ~3;
265
266	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
267	pThis->uConfigReg = u32;
268	PCI_UNLOCK(pDevIns);
269	}
270
271	return VINF_SUCCESS;
272	}
273
274
275	/**
276	* Port I/O Handler for PCI address IN operations.
277	*
278	* Emulates reads from Configuration Address Port at 0CF8h for
279	* Configuration Mechanism #1.
280	*
281	* @returns VBox status code.
282	*
283	* @param pDevIns ICH9 device instance.
284	* @param pvUser User argument - ignored.
285	* @param uPort Port number used for the IN operation.
286	* @param pu32 Where to store the result.
287	* @param cb Number of bytes read.
288	*/
289	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
290	{
291	RT_NOREF2(Port, pvUser);
292	if (cb == 4)
293	{
294	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
295
296	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
297	*pu32 = pThis->uConfigReg;
298	PCI_UNLOCK(pDevIns);
299
300	LogFlow(("ich9pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
301	return VINF_SUCCESS;
302	}
303
304	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
305	return VERR_IOM_IOPORT_UNUSED;
306	}
307
308
309	/*
310	* Perform configuration space write.
311	*/
312	static int ich9pciDataWriteAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pAddr,
313	uint32_t val, int cb, int rcReschedule)
314	{
315	int rc = VINF_SUCCESS;
316	#ifdef IN_RING3
317	NOREF(rcReschedule);
318	#else
319	RT_NOREF2(val, cb);
320	#endif
321
322	if (pAddr->iBus != 0) /* forward to subordinate bus */
323	{
324	if (pGlobals->aPciBus.cBridges)
325	{
326	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
327	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
328	if (pBridgeDevice)
329	{
330	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
331	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc,
332	pAddr->iRegister, val, cb);
333	}
334	#else
335	rc = rcReschedule;
336	#endif
337	}
338	}
339	else /* forward to directly connected device */
340	{
341	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
342	if (aDev)
343	{
344	#ifdef IN_RING3
345	aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, cb);
346	#else
347	rc = rcReschedule;
348	#endif
349	}
350	}
351
352	Log2(("ich9pciDataWriteAddr: %02x:%02x:%02x reg %x(%d) %x %Rrc\n",
353	pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister,
354	cb, val, rc));
355	return rc;
356	}
357
358
359	/*
360	* Decode value latched in Configuration Address Port and perform
361	* requsted write to the target configuration space register.
362	*
363	* XXX: This code should be probably moved to its only caller
364	* (ich9pciIOPortDataWrite) to avoid prolifiration of confusingly
365	* similarly named functions.
366	*/
367	static int ich9pciDataWrite(PICH9PCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
368	{
369	LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
370
371	/* Configuration space mapping enabled? */
372	if (!(pGlobals->uConfigReg & (1 << 31)))
373	return VINF_SUCCESS;
374
375	/* Decode target device and configuration space register */
376	PciAddress aPciAddr;
377	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
378
379	/* Perform configuration space write */
380	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VINF_IOM_R3_IOPORT_WRITE);
381	}
382
383
384	/**
385	* Port I/O Handler for PCI data OUT operations.
386	*
387	* Emulates writes to Configuration Data Port at 0CFCh for
388	* Configuration Mechanism #1.
389	*
390	* @returns VBox status code.
391	*
392	* @param pDevIns ICH9 device instance.
393	* @param pvUser User argument - ignored.
394	* @param uPort Port number used for the OUT operation.
395	* @param u32 The value to output.
396	* @param cb The value size in bytes.
397	*/
398	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
399	{
400	LogFlow(("ich9pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
401	NOREF(pvUser);
402	int rc = VINF_SUCCESS;
403	if (!(Port % cb))
404	{
405	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
406
407	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
408	rc = ich9pciDataWrite(pThis, Port, u32, cb);
409	PCI_UNLOCK(pDevIns);
410	}
411	else
412	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
413	return rc;
414	}
415
416
417	static void ich9pciNoMem(void* ptr, int cb)
418	{
419	for (int i = 0; i < cb; i++)
420	((uint8_t*)ptr)[i] = 0xff;
421	}
422
423
424	/*
425	* Perform configuration space read.
426	*/
427	static int ich9pciDataReadAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pPciAddr, int cb,
428	uint32_t *pu32, int rcReschedule)
429	{
430	int rc = VINF_SUCCESS;
431	#ifdef IN_RING3
432	NOREF(rcReschedule);
433	#endif
434
435	if (pPciAddr->iBus != 0) /* forward to subordinate bus */
436	{
437	if (pGlobals->aPciBus.cBridges)
438	{
439	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
440	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
441	if (pBridgeDevice)
442	{
443	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
444	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
445	}
446	else
447	ich9pciNoMem(pu32, cb);
448	#else
449	rc = rcReschedule;
450	#endif
451	}
452	else
453	ich9pciNoMem(pu32, cb);
454	}
455	else /* forward to directly connected device */
456	{
457	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
458	if (aDev)
459	{
460	#ifdef IN_RING3
461	*pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, cb);
462	#else
463	rc = rcReschedule;
464	#endif
465	}
466	else
467	ich9pciNoMem(pu32, cb);
468	}
469
470	Log3(("ich9pciDataReadAddr: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n",
471	pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister,
472	cb, *pu32, rc));
473	return rc;
474	}
475
476
477	/*
478	* Decode value latched in Configuration Address Port and perform
479	* requsted read from the target configuration space register.
480	*
481	* XXX: This code should be probably moved to its only caller
482	* (ich9pciIOPortDataRead) to avoid prolifiration of confusingly
483	* similarly named functions.
484	*/
485	static int ich9pciDataRead(PICH9PCIGLOBALS pGlobals, uint32_t addr, int cb, uint32_t *pu32)
486	{
487	LogFlow(("ich9pciDataRead: config=%x cb=%d\n", pGlobals->uConfigReg, cb));
488
489	*pu32 = 0xffffffff;
490
491	/* Configuration space mapping enabled? */
492	if (!(pGlobals->uConfigReg & (1 << 31)))
493	return VINF_SUCCESS;
494
495	/* Decode target device and configuration space register */
496	PciAddress aPciAddr;
497	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
498
499	/* Perform configuration space read */
500	return ich9pciDataReadAddr(pGlobals, &aPciAddr, cb, pu32, VINF_IOM_R3_IOPORT_READ);
501	}
502
503
504	/**
505	* Port I/O Handler for PCI data IN operations.
506	*
507	* Emulates reads from Configuration Data Port at 0CFCh for
508	* Configuration Mechanism #1.
509	*
510	* @returns VBox status code.
511	*
512	* @param pDevIns ICH9 device instance.
513	* @param pvUser User argument - ignored.
514	* @param uPort Port number used for the IN operation.
515	* @param pu32 Where to store the result.
516	* @param cb Number of bytes read.
517	*/
518	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
519	{
520	NOREF(pvUser);
521	if (!(Port % cb))
522	{
523	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
524
525	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
526	int rc = ich9pciDataRead(pThis, Port, cb, pu32);
527	PCI_UNLOCK(pDevIns);
528
529	LogFlow(("ich9pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
530	return rc;
531	}
532	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
533	return VERR_IOM_IOPORT_UNUSED;
534	}
535
536
537	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
538	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
539	{
540	return (irq_num + uSlot) & 7;
541	}
542
543	/* return the global irq number corresponding to a given device irq
544	pin. We could also use the bus number to have a more precise
545	mapping. This is the implementation note described in the PCI spec chapter 2.2.6 */
546	DECLINLINE(int) ich9pciSlotGetPirq(uint8_t uBus, uint8_t uDevFn, int iIrqNum)
547	{
548	NOREF(uBus);
549	int iSlotAddend = (uDevFn >> 3) - 1;
550	return (iIrqNum + iSlotAddend) & 3;
551	}
552
553	/* irqs corresponding to PCI irqs A-D, must match pci_irq_list in rombios.c */
554	static const uint8_t aPciIrqs[4] = { 11, 10, 9, 5 };
555
556	/* Add one more level up request on APIC input line */
557	DECLINLINE(void) ich9pciApicLevelUp(PICH9PCIGLOBALS pGlobals, int irq_num)
558	{
559	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
560	}
561
562	/* Remove one level up request on APIC input line */
563	DECLINLINE(void) ich9pciApicLevelDown(PICH9PCIGLOBALS pGlobals, int irq_num)
564	{
565	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
566	}
567
568	static void ich9pciApicSetIrq(PICH9PCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel,
569	uint32_t uTagSrc, int iForcedIrq)
570	{
571	/* This is only allowed to be called with a pointer to the root bus. */
572	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
573
574	if (iForcedIrq == -1)
575	{
576	int apic_irq, apic_level;
577	PICH9PCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
578	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
579
580	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
581	ich9pciApicLevelUp(pGlobals, irq_num);
582	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
583	ich9pciApicLevelDown(pGlobals, irq_num);
584
585	apic_irq = irq_num + 0x10;
586	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
587	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x\n",
588	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
589	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
590
591	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
592	{
593	/*
594	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
595	* PDM_IRQ_LEVEL_HIGH bit set
596	*/
597	ich9pciApicLevelDown(pGlobals, irq_num);
598	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
599	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
600	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x (flop)\n",
601	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
602	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
603	}
604	} else {
605	Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d uTagSrc=%#x\n",
606	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq, uTagSrc));
607	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel, uTagSrc);
608	}
609	}
610
611	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev,
612	int iIrq, int iLevel, uint32_t uTagSrc)
613	{
614	/* If MSI or MSI-X is enabled, PCI INTx# signals are disabled regardless of the PCI command
615	* register interrupt bit state.
616	* PCI 3.0 (section 6.8) forbids MSI and MSI-X to be enabled at the same time and makes
617	* that undefined behavior. We check for MSI first, then MSI-X.
618	*/
619	if (MsiIsEnabled(pPciDev))
620	{
621	Assert(!MsixIsEnabled(pPciDev)); /* Not allowed -- see note above. */
622	LogFlowFunc(("PCI Dev %p : MSI\n", pPciDev));
623	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
624	MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
625	return;
626	}
627
628	if (MsixIsEnabled(pPciDev))
629	{
630	LogFlowFunc(("PCI Dev %p : MSI-X\n", pPciDev));
631	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
632	MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
633	return;
634	}
635
636	PICH9PCIBUS pBus = &pGlobals->aPciBus;
637	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
638
639	LogFlowFunc(("PCI Dev %p : IRQ\n", pPciDev));
640	/* Check if the state changed. */
641	if (pPciDev->Int.s.uIrqPinState != iLevel)
642	{
643	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
644
645	/* Send interrupt to I/O APIC only now. */
646	if (fIsAcpiDevice)
647	/*
648	* ACPI needs special treatment since SCI is hardwired and
649	* should not be affected by PCI IRQ routing tables at the
650	* same time SCI IRQ is shared in PCI sense hence this
651	* kludge (i.e. we fetch the hardwired value from ACPIs
652	* PCI device configuration space).
653	*/
654	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, uTagSrc, PCIDevGetInterruptLine(pPciDev));
655	else
656	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, uTagSrc, -1);
657	}
658	}
659
660
661	/**
662	* Memory mapped I/O Handler for write operations.
663	*
664	* Emulates writes to configuration space.
665	*
666	* @returns VBox status code.
667	*
668	* @param pDevIns The device instance.
669	* @param pvUser User argument.
670	* @param GCPhysAddr Physical address (in GC) where the read starts.
671	* @param pv Where to fetch the result.
672	* @param cb Number of bytes to write.
673	* @remarks Caller enters the device critical section.
674	*/
675	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
676	{
677	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
678	uint32_t u32 = 0;
679	NOREF(pvUser);
680
681	Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
682
683	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_WRITE);
684
685	/* Decode target device and configuration space register */
686	PciAddress aDest;
687	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
688
689	switch (cb)
690	{
691	case 1:
692	u32 = (uint8_t)pv;
693	break;
694	case 2:
695	u32 = (uint16_t)pv;
696	break;
697	case 4:
698	u32 = (uint32_t)pv;
699	break;
700	default:
701	Assert(false);
702	break;
703	}
704
705	/* Perform configuration space write */
706	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb, VINF_IOM_R3_MMIO_WRITE);
707	PCI_UNLOCK(pDevIns);
708
709	return rc;
710	}
711
712
713	/**
714	* Memory mapped I/O Handler for read operations.
715	*
716	* Emulates reads from configuration space.
717	*
718	* @returns VBox status code.
719	*
720	* @param pDevIns The device instance.
721	* @param pvUser User argument.
722	* @param GCPhysAddr Physical address (in GC) where the read starts.
723	* @param pv Where to store the result.
724	* @param cb Number of bytes read.
725	* @remarks Caller enters the device critical section.
726	*/
727	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
728	{
729	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
730	uint32_t rv;
731	NOREF(pvUser);
732
733	LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
734
735	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_READ);
736
737	/* Decode target device and configuration space register */
738	PciAddress aDest;
739	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
740
741	/* Perform configuration space read */
742	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv, VINF_IOM_R3_MMIO_READ);
743
744	if (RT_SUCCESS(rc))
745	{
746	switch (cb)
747	{
748	case 1:
749	(uint8_t)pv = (uint8_t)rv;
750	break;
751	case 2:
752	(uint16_t)pv = (uint16_t)rv;
753	break;
754	case 4:
755	(uint32_t)pv = (uint32_t)rv;
756	break;
757	default:
758	Assert(false);
759	break;
760	}
761	}
762	PCI_UNLOCK(pDevIns);
763
764	return rc;
765	}
766
767	#ifdef IN_RING3
768
769	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus)
770	{
771	/* Search for a fitting bridge. */
772	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
773	{
774	/*
775	* Examine secondary and subordinate bus number.
776	* If the target bus is in the range we pass the request on to the bridge.
777	*/
778	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
779	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
780	("Device is not a PCI bridge but on the list of PCI bridges\n"));
781	uint32_t uSecondary = PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS);
782	uint32_t uSubordinate = PCIDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS);
783	Log3(("ich9pciFindBridge on bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, iBus, uSecondary, uSubordinate));
784	if (iBus >= uSecondary && iBus <= uSubordinate)
785	return pBridge;
786	}
787
788	/* Nothing found. */
789	return NULL;
790	}
791
792	static uint32_t ich9pciGetCfg(PCIDevice* aDev, int32_t iRegister, int cb)
793	{
794	return aDev->Int.s.pfnConfigRead(aDev, iRegister, cb);
795	}
796
797	static uint8_t ich9pciGetByte(PCIDevice* aDev, int32_t iRegister)
798	{
799	return (uint8_t)ich9pciGetCfg(aDev, iRegister, 1);
800	}
801
802	static uint16_t ich9pciGetWord(PCIDevice* aDev, int32_t iRegister)
803	{
804	return (uint16_t)ich9pciGetCfg(aDev, iRegister, 2);
805	}
806
807	static uint32_t ich9pciGetDWord(PCIDevice* aDev, int32_t iRegister)
808	{
809	return (uint32_t)ich9pciGetCfg(aDev, iRegister, 4);
810	}
811
812	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
813	{
814	return (iRegion == VBOX_PCI_ROM_SLOT) ?
815	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
816	}
817
818	#define INVALID_PCI_ADDRESS ~0U
819
820	static int ich9pciUnmapRegion(PPCIDEVICE pDev, int iRegion)
821	{
822	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
823	int rc = VINF_SUCCESS;
824	PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
825
826	Assert (pRegion->size != 0);
827
828	if (pRegion->addr != INVALID_PCI_ADDRESS)
829	{
830	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
831	{
832	/* Port IO */
833	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
834	AssertRC(rc);
835	}
836	else
837	{
838	RTGCPHYS GCPhysBase = pRegion->addr;
839	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
840	{
841	/* unmap it. */
842	rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
843	AssertRC(rc);
844	rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
845	}
846	else
847	rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
848	}
849
850	pRegion->addr = INVALID_PCI_ADDRESS;
851	}
852
853	return rc;
854	}
855
856	static void ich9pciUpdateMappings(PCIDevice* pDev)
857	{
858	uint64_t uLast, uNew;
859
860	int iCmd = ich9pciGetWord(pDev, VBOX_PCI_COMMAND);
861	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
862	{
863	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
864	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
865	int64_t iRegionSize = pRegion->size;
866	int rc;
867
868	if (iRegionSize == 0)
869	continue;
870
871	bool f64Bit = (pRegion->type & PCI_ADDRESS_SPACE_BAR64) != 0;
872
873	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
874	{
875	/* port IO region */
876	if (iCmd & PCI_COMMAND_IOACCESS)
877	{
878	/* IO access allowed */
879	uNew = ich9pciGetDWord(pDev, uConfigReg);
880	uNew &= ~(iRegionSize - 1);
881	uLast = uNew + iRegionSize - 1;
882	/* only 64K ioports on PC */
883	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
884	uNew = INVALID_PCI_ADDRESS;
885	} else
886	uNew = INVALID_PCI_ADDRESS;
887	}
888	else
889	{
890	/* MMIO region */
891	if (iCmd & PCI_COMMAND_MEMACCESS)
892	{
893	uNew = ich9pciGetDWord(pDev, uConfigReg);
894
895	if (f64Bit)
896	{
897	uNew \|= ((uint64_t)ich9pciGetDWord(pDev, uConfigReg+4)) << 32;
898	/** @todo r=klaus Is this really true? Needs to be fixed properly. */
899	if (uNew > UINT64_C(0x0000010000000000))
900	{
901	/* Workaround for REM being unhapping with mapping very long 64-bit addresses */
902	LogRel(("Ignoring too long 64-bit BAR: %llx\n", uNew));
903	uNew = INVALID_PCI_ADDRESS;
904	}
905	}
906
907	/* the ROM slot has a specific enable bit */
908	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
909	uNew = INVALID_PCI_ADDRESS;
910	else
911	{
912	uNew &= ~(iRegionSize - 1);
913	uLast = uNew + iRegionSize - 1;
914	/* NOTE: we do not support wrapping */
915	/* XXX: as we cannot support really dynamic
916	mappings, we handle specific values as invalid
917	mappings. */
918	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
919	if (uLast <= uNew \|\| uNew == 0 \|\| (uNew <= UINT32_C(0xffffffff) && uLast >= UINT32_C(0xfec00000)))
920	uNew = INVALID_PCI_ADDRESS;
921	}
922	} else
923	uNew = INVALID_PCI_ADDRESS;
924	}
925	LogRel2(("PCI: config dev %u/%u BAR%i uOld=%#018llx uNew=%#018llx size=%llu\n", pDev->devfn >> 3, pDev->devfn & 7, iRegion, pRegion->addr, uNew, pRegion->size));
926	/* now do the real mapping */
927	if (uNew != pRegion->addr)
928	{
929	if (pRegion->addr != INVALID_PCI_ADDRESS)
930	ich9pciUnmapRegion(pDev, iRegion);
931
932	pRegion->addr = uNew;
933	if (pRegion->addr != INVALID_PCI_ADDRESS)
934	{
935
936	/* finally, map the region */
937	rc = pRegion->map_func(pDev, iRegion,
938	pRegion->addr, pRegion->size,
939	(PCIADDRESSSPACE)(pRegion->type));
940	AssertRC(rc);
941	}
942	}
943
944	if (f64Bit)
945	iRegion++;
946	}
947	}
948
949	static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
950	{
951	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
952
953	/*
954	* Check input.
955	*/
956	if ( !pszName
957	\|\| !pPciDev
958	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices)
959	)
960	{
961	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
962	return VERR_INVALID_PARAMETER;
963	}
964
965	/*
966	* Register the device.
967	*/
968	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
969	}
970
971
972	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
973	{
974	NOREF(pDevIns);
975	int rc;
976
977	rc = MsiInit(pPciDev, pMsiReg);
978	if (RT_FAILURE(rc))
979	return rc;
980
981	rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
982	if (RT_FAILURE(rc))
983	return rc;
984
985	return VINF_SUCCESS;
986	}
987
988
989	static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
990	{
991
992	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
993
994	/*
995	* Check input.
996	*/
997	if ( !pszName
998	\|\| !pPciDev
999	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices))
1000	{
1001	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1002	return VERR_INVALID_PARAMETER;
1003	}
1004
1005	/*
1006	* Register the device.
1007	*/
1008	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
1009	}
1010
1011	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1012	{
1013	NOREF(pDevIns);
1014
1015	/*
1016	* Validate.
1017	*/
1018	AssertMsgReturn( enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR32)
1019	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR32)
1020	\|\| enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR64)
1021	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR64)
1022	\|\| enmType == PCI_ADDRESS_SPACE_IO
1023	,
1024	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1025	VERR_INVALID_PARAMETER);
1026	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1027	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1028	VERR_INVALID_PARAMETER);
1029	int iLastSet = ASMBitLastSetU32(cbRegion);
1030	AssertMsgReturn( iLastSet != 0
1031	&& RT_BIT_32(iLastSet - 1) == cbRegion,
1032	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1033	VERR_INVALID_PARAMETER);
1034
1035	Log(("ich9pciIORegionRegister: %s region %d size %d type %x\n",
1036	pPciDev->name, iRegion, cbRegion, enmType));
1037
1038	/* Make sure that we haven't marked this region as continuation of 64-bit region. */
1039	Assert(pPciDev->Int.s.aIORegions[iRegion].type != 0xff);
1040
1041	/*
1042	* Register the I/O region.
1043	*/
1044	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1045	pRegion->addr = INVALID_PCI_ADDRESS;
1046	pRegion->size = cbRegion;
1047	pRegion->type = enmType;
1048	pRegion->map_func = pfnCallback;
1049
1050	if ((enmType & PCI_ADDRESS_SPACE_BAR64) != 0)
1051	{
1052	/* VBOX_PCI_BASE_ADDRESS_5 and VBOX_PCI_ROM_ADDRESS are excluded. */
1053	AssertMsgReturn(iRegion < (PCI_NUM_REGIONS-2),
1054	("Region %d cannot be 64-bit\n", iRegion),
1055	VERR_INVALID_PARAMETER);
1056	/* Mark next region as continuation of this one. */
1057	pPciDev->Int.s.aIORegions[iRegion+1].type = 0xff;
1058	}
1059
1060	/* Set type in the PCI config space. */
1061	uint32_t u32Value = ((uint32_t)enmType) & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH);
1062	PCIDevSetDWord(pPciDev, ich9pciGetRegionReg(iRegion), u32Value);
1063
1064	return VINF_SUCCESS;
1065	}
1066
1067	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1068	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1069	{
1070	NOREF(pDevIns);
1071
1072	if (ppfnReadOld)
1073	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1074	pPciDev->Int.s.pfnConfigRead = pfnRead;
1075
1076	if (ppfnWriteOld)
1077	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1078	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1079	}
1080
1081	static int ich9pciR3CommonSaveExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM)
1082	{
1083	/*
1084	* Iterate thru all the devices.
1085	*/
1086	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1087	{
1088	PPCIDEVICE pDev = pBus->apDevices[i];
1089	if (pDev)
1090	{
1091	/* Device position */
1092	SSMR3PutU32(pSSM, i);
1093	/* PCI config registers */
1094	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1095
1096	/* Device flags */
1097	int rc = SSMR3PutU32(pSSM, pDev->Int.s.fFlags);
1098	if (RT_FAILURE(rc))
1099	return rc;
1100
1101	/* IRQ pin state */
1102	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1103	if (RT_FAILURE(rc))
1104	return rc;
1105
1106	/* MSI info */
1107	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
1108	if (RT_FAILURE(rc))
1109	return rc;
1110	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
1111	if (RT_FAILURE(rc))
1112	return rc;
1113
1114	/* MSI-X info */
1115	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
1116	if (RT_FAILURE(rc))
1117	return rc;
1118	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
1119	if (RT_FAILURE(rc))
1120	return rc;
1121	/* Save MSI-X page state */
1122	if (pDev->Int.s.u8MsixCapOffset != 0)
1123	{
1124	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1125	SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
1126	if (RT_FAILURE(rc))
1127	return rc;
1128	}
1129	}
1130	}
1131	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1132	}
1133
1134	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1135	{
1136	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1137
1138	/*
1139	* Bus state data.
1140	*/
1141	SSMR3PutU32(pSSM, pThis->uConfigReg);
1142
1143	/*
1144	* Save IRQ states.
1145	*/
1146	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1147	SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
1148
1149	SSMR3PutU32(pSSM, UINT32_MAX); /* separator */
1150
1151	return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
1152	}
1153
1154
1155	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1156	{
1157	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1158	return ich9pciR3CommonSaveExec(pThis, pSSM);
1159	}
1160
1161
1162	static DECLCALLBACK(void) ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1163	{
1164	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1165
1166	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1167
1168	/* If the current bus is not the target bus search for the bus which contains the device. */
1169	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1170	{
1171	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1172	if (pBridgeDevice)
1173	{
1174	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1175	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
1176	}
1177	}
1178	else
1179	{
1180	/* This is the target bus, pass the write to the device. */
1181	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1182	if (pPciDev)
1183	{
1184	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1185	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
1186	}
1187	}
1188	}
1189
1190	static DECLCALLBACK(uint32_t) ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1191	{
1192	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1193	uint32_t u32Value;
1194
1195	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1196
1197	/* If the current bus is not the target bus search for the bus which contains the device. */
1198	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1199	{
1200	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1201	if (pBridgeDevice)
1202	{
1203	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1204	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
1205	}
1206	else
1207	ich9pciNoMem(&u32Value, 4);
1208	}
1209	else
1210	{
1211	/* This is the target bus, pass the read to the device. */
1212	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1213	if (pPciDev)
1214	{
1215	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
1216	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1217	}
1218	else
1219	ich9pciNoMem(&u32Value, 4);
1220	}
1221
1222	return u32Value;
1223	}
1224
1225
1226	/**
1227	* Common routine for restoring the config registers of a PCI device.
1228	*
1229	* @param pDev The PCI device.
1230	* @param pbSrcConfig The configuration register values to be loaded.
1231	* @param fIsBridge Whether this is a bridge device or not.
1232	*/
1233	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1234	{
1235	/*
1236	* This table defines the fields for normal devices and bridge devices, and
1237	* the order in which they need to be restored.
1238	*/
1239	static const struct PciField
1240	{
1241	uint8_t off;
1242	uint8_t cb;
1243	uint8_t fWritable;
1244	uint8_t fBridge;
1245	const char *pszName;
1246	} s_aFields[] =
1247	{
1248	/* off,cb,fW,fB, pszName */
1249	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1250	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1251	{ 0x06, 2, 1, 3, "STATUS" },
1252	{ 0x08, 1, 0, 3, "REVISION_ID" },
1253	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1254	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1255	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1256	{ 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },
1257	{ 0x0d, 1, 1, 3, "LATENCY_TIMER" },
1258	{ 0x0e, 1, 0, 3, "HEADER_TYPE" },
1259	{ 0x0f, 1, 1, 3, "BIST" },
1260	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1261	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1262	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1263	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1264	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1265	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1266	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1267	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1268	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1269	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1270	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1271	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1272	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1273	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1274	{ 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1275	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1276	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1277	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1278	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1279	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1280	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1281	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1282	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1283	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1284	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1285	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1286	{ 0x38, 4, 1, 1, "RESERVED_38" }, // ???
1287	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1288	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1289	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1290	{ 0x3e, 1, 0, 1, "MIN_GNT" },
1291	{ 0x3e, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1292	{ 0x3f, 1, 0, 1, "MAX_LAT" },
1293	/* The COMMAND register must come last as it requires the ADDRESS
1294	registers to be restored before we pretent to change it from 0 to
1295	whatever value the guest assigned it. */
1296	{ 0x04, 2, 1, 3, "COMMAND" },
1297	};
1298
1299	#ifdef RT_STRICT
1300	/* Check that we've got full register coverage. */
1301	uint32_t bmDevice[0x40 / 32];
1302	uint32_t bmBridge[0x40 / 32];
1303	RT_ZERO(bmDevice);
1304	RT_ZERO(bmBridge);
1305	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1306	{
1307	uint8_t off = s_aFields[i].off;
1308	uint8_t cb = s_aFields[i].cb;
1309	uint8_t f = s_aFields[i].fBridge;
1310	while (cb-- > 0)
1311	{
1312	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1313	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1314	if (f & 1) ASMBitSet(bmDevice, off);
1315	if (f & 2) ASMBitSet(bmBridge, off);
1316	off++;
1317	}
1318	}
1319	for (uint32_t off = 0; off < 0x40; off++)
1320	{
1321	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1322	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1323	}
1324	#endif
1325
1326	/*
1327	* Loop thru the fields covering the 64 bytes of standard registers.
1328	*/
1329	uint8_t const fBridge = fIsBridge ? 2 : 1;
1330	Assert(!pciDevIsPassthrough(pDev));
1331	uint8_t *pbDstConfig = &pDev->config[0];
1332
1333	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1334	if (s_aFields[i].fBridge & fBridge)
1335	{
1336	uint8_t const off = s_aFields[i].off;
1337	uint8_t const cb = s_aFields[i].cb;
1338	uint32_t u32Src;
1339	uint32_t u32Dst;
1340	switch (cb)
1341	{
1342	case 1:
1343	u32Src = pbSrcConfig[off];
1344	u32Dst = pbDstConfig[off];
1345	break;
1346	case 2:
1347	u32Src = (uint16_t const )&pbSrcConfig[off];
1348	u32Dst = (uint16_t const )&pbDstConfig[off];
1349	break;
1350	case 4:
1351	u32Src = (uint32_t const )&pbSrcConfig[off];
1352	u32Dst = (uint32_t const )&pbDstConfig[off];
1353	break;
1354	default:
1355	AssertFailed();
1356	continue;
1357	}
1358
1359	if ( u32Src != u32Dst
1360	\|\| off == VBOX_PCI_COMMAND)
1361	{
1362	if (u32Src != u32Dst)
1363	{
1364	if (!s_aFields[i].fWritable)
1365	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1366	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1367	else
1368	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1369	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1370	}
1371	if (off == VBOX_PCI_COMMAND)
1372	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1373	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1374	}
1375	}
1376
1377	/*
1378	* The device dependent registers.
1379	*
1380	* We will not use ConfigWrite here as we have no clue about the size
1381	* of the registers, so the device is responsible for correctly
1382	* restoring functionality governed by these registers.
1383	*/
1384	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1385	if (pbDstConfig[off] != pbSrcConfig[off])
1386	{
1387	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1388	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1389	pbDstConfig[off] = pbSrcConfig[off];
1390	}
1391	}
1392
1393	/**
1394	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1395	*
1396	* @returns VBox status code.
1397	* @param pBus The bus which data is being loaded.
1398	* @param pSSM The saved state handle.
1399	* @param uVersion The data version.
1400	* @param uPass The pass.
1401	*/
1402	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1403	{
1404	uint32_t u32;
1405	uint32_t i;
1406	int rc;
1407
1408	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1409	if (uVersion != VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT)
1410	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1411
1412	/*
1413	* Iterate thru all the devices and write 0 to the COMMAND register so
1414	* that all the memory is unmapped before we start restoring the saved
1415	* mapping locations.
1416	*
1417	* The register value is restored afterwards so we can do proper
1418	* LogRels in pciR3CommonRestoreConfig.
1419	*/
1420	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1421	{
1422	PPCIDEVICE pDev = pBus->apDevices[i];
1423	if (pDev)
1424	{
1425	uint16_t u16 = PCIDevGetCommand(pDev);
1426	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1427	PCIDevSetCommand(pDev, u16);
1428	Assert(PCIDevGetCommand(pDev) == u16);
1429	}
1430	}
1431
1432	void *pvMsixPage = RTMemTmpAllocZ(0x1000);
1433	AssertReturn(pvMsixPage, VERR_NO_TMP_MEMORY);
1434
1435	/*
1436	* Iterate all the devices.
1437	*/
1438	for (i = 0;; i++)
1439	{
1440	PPCIDEVICE pDev;
1441	PCIDEVICE DevTmp;
1442
1443	/* index / terminator */
1444	rc = SSMR3GetU32(pSSM, &u32);
1445	if (RT_FAILURE(rc))
1446	break;
1447	if (u32 == (uint32_t)~0)
1448	break;
1449	AssertMsgBreak(u32 < RT_ELEMENTS(pBus->apDevices) && u32 >= i, ("u32=%#x i=%#x\n", u32, i));
1450
1451	/* skip forward to the device checking that no new devices are present. */
1452	for (; i < u32; i++)
1453	{
1454	pDev = pBus->apDevices[i];
1455	if (pDev)
1456	{
1457	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1458	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1459	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1460	{
1461	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1462	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1463	break;
1464	}
1465	}
1466	}
1467	if (RT_FAILURE(rc))
1468	break;
1469
1470	/* get the data */
1471	DevTmp.Int.s.fFlags = 0;
1472	DevTmp.Int.s.u8MsiCapOffset = 0;
1473	DevTmp.Int.s.u8MsiCapSize = 0;
1474	DevTmp.Int.s.u8MsixCapOffset = 0;
1475	DevTmp.Int.s.u8MsixCapSize = 0;
1476	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1477	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1478
1479	SSMR3GetU32(pSSM, &DevTmp.Int.s.fFlags);
1480	SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1481	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1482	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1483	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1484	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1485	if (RT_FAILURE(rc))
1486	break;
1487
1488	/* Load MSI-X page state */
1489	if (DevTmp.Int.s.u8MsixCapOffset != 0)
1490	{
1491	Assert(pvMsixPage != NULL);
1492	rc = SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1493	if (RT_FAILURE(rc))
1494	break;
1495	}
1496
1497	/* check that it's still around. */
1498	pDev = pBus->apDevices[i];
1499	if (!pDev)
1500	{
1501	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1502	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1503	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1504	{
1505	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1506	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1507	break;
1508	}
1509	continue;
1510	}
1511
1512	/* match the vendor id assuming that this will never be changed. */
1513	if (PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1514	{
1515	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1516	i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1517	break;
1518	}
1519
1520	/* commit the loaded device config. */
1521	Assert(!pciDevIsPassthrough(pDev));
1522	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1523
1524	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1525	pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1526	pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1527	pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1528	pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1529	if (DevTmp.Int.s.u8MsixCapSize != 0)
1530	{
1531	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1532	memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1533	}
1534	}
1535
1536	RTMemTmpFree(pvMsixPage);
1537
1538	return rc;
1539	}
1540
1541	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1542	{
1543	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1544	PICH9PCIBUS pBus = &pThis->aPciBus;
1545	uint32_t u32;
1546	int rc;
1547
1548	/* We ignore this version as there's no saved state with it anyway */
1549	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1550	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1551	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1552	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1553
1554	/*
1555	* Bus state data.
1556	*/
1557	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1558
1559	/*
1560	* Load IRQ states.
1561	*/
1562	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1563	SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1564
1565	/* separator */
1566	rc = SSMR3GetU32(pSSM, &u32);
1567	if (RT_FAILURE(rc))
1568	return rc;
1569	if (u32 != (uint32_t)~0)
1570	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1571
1572	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1573	}
1574
1575	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1576	{
1577	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1578	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1579	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1580	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1581	}
1582
1583
1584	/*
1585	* Perform imeediate read of configuration space register.
1586	* Cannot be rescheduled, as already in R3.
1587	*/
1588	static uint32_t ich9pciConfigRead(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1589	{
1590	PciAddress aPciAddr;
1591	aPciAddr.iBus = uBus;
1592	aPciAddr.iDeviceFunc = uDevFn;
1593	aPciAddr.iRegister = addr;
1594
1595	uint32_t u32Val;
1596	int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR);
1597	AssertRC(rc);
1598
1599	return u32Val;
1600	}
1601
1602
1603	/*
1604	* Perform imeediate write to configuration space register.
1605	* Cannot be rescheduled, as already in R3.
1606	*/
1607	static void ich9pciConfigWrite(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1608	{
1609	PciAddress aPciAddr;
1610	aPciAddr.iBus = uBus;
1611	aPciAddr.iDeviceFunc = uDevFn;
1612	aPciAddr.iRegister = addr;
1613
1614	int rc = ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VERR_INTERNAL_ERROR);
1615	AssertRC(rc);
1616	}
1617
1618
1619	static void ich9pciSetRegionAddress(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
1620	{
1621	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1622
1623	/* Read memory type first. */
1624	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1625
1626	Log(("Set region address: %02x:%02x.%d region %d address=%lld\n",
1627	uBus, uDevFn >> 3, uDevFn & 7, iRegion, addr));
1628
1629	bool f64Bit = (uResourceType & PCI_ADDRESS_SPACE_BAR64) != 0;
1630
1631	/* Write address of the device. */
1632	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, (uint32_t)addr, 4);
1633	if (f64Bit)
1634	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg + 4, (uint32_t)(addr >> 32), 4);
1635	}
1636
1637
1638	static void ich9pciBiosInitBridge(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1639	{
1640	Log(("BIOS init bridge: %02x::%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1641
1642	/*
1643	* The I/O range for the bridge must be aligned to a 4KB boundary.
1644	* This does not change anything really as the access to the device is not going
1645	* through the bridge but we want to be compliant to the spec.
1646	*/
1647	if ((pGlobals->uPciBiosIo % 4096) != 0)
1648	{
1649	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1650	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1651	}
1652	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1653
1654	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1655	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1656	{
1657	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1658	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1659	}
1660	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1661
1662	/* Save values to compare later to. */
1663	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1664	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1665	uint8_t uBridgeBus = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, 1);
1666
1667	/* Init devices behind the bridge and possibly other bridges as well. */
1668	for (int iDev = 0; iDev <= 255; iDev++)
1669	ich9pciBiosInitDevice(pGlobals, uBridgeBus, iDev);
1670
1671	/*
1672	* Set I/O limit register. If there is no device with I/O space behind the bridge
1673	* we set a lower value than in the base register.
1674	* The result with a real bridge is that no I/O transactions are passed to the secondary
1675	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1676	*/
1677	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1678	{
1679	/* The upper boundary must be one byte less than a 4KB boundary. */
1680	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1681	}
1682
1683	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1684
1685	/* Same with the MMIO limit register but with 1MB boundary here. */
1686	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1687	{
1688	/* The upper boundary must be one byte less than a 1MB boundary. */
1689	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1690	}
1691	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1692
1693	/*
1694	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1695	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1696	* the base register than in the limit register.
1697	*/
1698	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1699	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1700	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1701	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1702	}
1703
1704	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1705	{
1706	uint16_t uDevClass, uVendor, uDevice;
1707	uint8_t uCmd;
1708
1709	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1710	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1711	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1712
1713	/* If device is present */
1714	if (uVendor == 0xffff)
1715	return;
1716
1717	Log(("BIOS init device: %02x:%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1718
1719	switch (uDevClass)
1720	{
1721	case 0x0101:
1722	/* IDE controller */
1723	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1724	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1725	goto default_map;
1726	break;
1727	case 0x0300:
1728	/* VGA controller */
1729	if (uVendor != 0x80ee)
1730	goto default_map;
1731	/* VGA: map frame buffer to default Bochs VBE address */
1732	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0xE0000000);
1733	/*
1734	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1735	* only the framebuffer (i.e., a memory region) is explicitly registered via
1736	* ich9pciSetRegionAddress, so don't forget to enable I/O decoding.
1737	*/
1738	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1739	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1740	uCmd \| PCI_COMMAND_IOACCESS \| PCI_COMMAND_MEMACCESS,
1741	1);
1742	break;
1743	case 0x0604:
1744	/* PCI-to-PCI bridge. */
1745	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1746	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn);
1747	break;
1748	default:
1749	default_map:
1750	{
1751	/* default memory mappings */
1752	bool fActiveMemRegion = false;
1753	bool fActiveIORegion = false;
1754	/*
1755	* We ignore ROM region here.
1756	*/
1757	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1758	{
1759	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1760
1761	/* Calculate size - we write all 1s into the BAR, and then evaluate which bits
1762	are cleared. */
1763	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1764
1765	bool f64bit = (u8ResourceType & PCI_ADDRESS_SPACE_BAR64) != 0;
1766	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1767	uint64_t cbRegSize64 = 0;
1768
1769	if (f64bit)
1770	{
1771	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1772	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0xffffffff), 4);
1773	cbRegSize64 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1774	cbRegSize64 \|= ((uint64_t)ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address+4, 4) << 32);
1775	cbRegSize64 &= ~UINT64_C(0x0f);
1776	cbRegSize64 = (~cbRegSize64) + 1;
1777
1778	/* No 64-bit PIO regions possible. */
1779	#ifndef DEBUG_bird /* EFI triggers this for DevAHCI. */
1780	AssertMsg((u8ResourceType & PCI_COMMAND_IOACCESS) == 0, ("type=%#x rgn=%d\n", u8ResourceType, iRegion));
1781	#endif
1782	}
1783	else
1784	{
1785	uint32_t cbRegSize32;
1786	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1787	cbRegSize32 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1788
1789	/* Clear resource information depending on resource type. */
1790	if (fIsPio) /* PIO */
1791	cbRegSize32 &= ~UINT32_C(0x01);
1792	else /* MMIO */
1793	cbRegSize32 &= ~UINT32_C(0x0f);
1794
1795	/*
1796	* Invert all bits and add 1 to get size of the region.
1797	* (From PCI implementation note)
1798	*/
1799	if (fIsPio && (cbRegSize32 & UINT32_C(0xffff0000)) == 0)
1800	cbRegSize32 = (~(cbRegSize32 \| UINT32_C(0xffff0000))) + 1;
1801	else
1802	cbRegSize32 = (~cbRegSize32) + 1;
1803
1804	cbRegSize64 = cbRegSize32;
1805	}
1806	#ifndef DEBUG_bird /* EFI triggers this for DevAHCI. */
1807	Assert(cbRegSize64 == (uint32_t)cbRegSize64);
1808	#endif
1809	Log2(("%s: Size of region %u for device %d on bus %d is %lld\n", __FUNCTION__, iRegion, uDevFn, uBus, cbRegSize64));
1810
1811	if (cbRegSize64)
1812	{
1813	/** @todo r=klaus make this code actually handle 64-bit BARs, especially MMIO which can't possibly fit into the memory hole. */
1814	uint32_t cbRegSize32 = (uint32_t)cbRegSize64;
1815	uint32_t* paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1816	uint32_t uNew = *paddr;
1817	uNew = (uNew + cbRegSize32 - 1) & ~(cbRegSize32 - 1);
1818	if (fIsPio)
1819	uNew &= UINT32_C(0xffff);
1820	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
1821	if (!uNew \|\| (uNew <= UINT32_C(0xffffffff) && uNew + cbRegSize32 - 1 >= UINT32_C(0xfec00000)))
1822	{
1823	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
1824	iRegion, uBus, uDevFn >> 3, uDevFn & 7, uVendor, uDevice)); /** @todo make this a VM start failure later. */
1825	/* Undo the mapping mess caused by the size probing. */
1826	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0), 4);
1827	if (f64bit)
1828	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0), 4);
1829	}
1830	else
1831	{
1832	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, uNew));
1833	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
1834	if (fIsPio)
1835	fActiveIORegion = true;
1836	else
1837	fActiveMemRegion = true;
1838	*paddr = uNew + cbRegSize32;
1839	Log2(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1840	}
1841
1842	if (f64bit)
1843	iRegion++; /* skip next region */
1844	}
1845	}
1846
1847	/* Update the command word appropriately. */
1848	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1849	if (fActiveMemRegion)
1850	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1851	if (fActiveIORegion)
1852	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1853	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1854	break;
1855	}
1856	}
1857
1858	/* map the interrupt */
1859	uint32_t iPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1860	if (iPin != 0)
1861	{
1862	iPin--;
1863
1864	if (uBus != 0)
1865	{
1866	/* Find bus this device attached to. */
1867	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1868	while (1)
1869	{
1870	PPCIDEVICE pBridge = ich9pciFindBridge(pBus, uBus);
1871	if (!pBridge)
1872	{
1873	Assert(false);
1874	break;
1875	}
1876	if (uBus == PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS))
1877	{
1878	/* OK, found bus this device attached to. */
1879	break;
1880	}
1881	pBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1882	}
1883
1884	/* We need to go up to the host bus to see which irq pin this
1885	* device will use there. See logic in ich9pcibridgeSetIrq().
1886	*/
1887	while (pBus->iBus != 0)
1888	{
1889	/* Get the pin the device would assert on the bridge. */
1890	iPin = ((pBus->aPciDev.devfn >> 3) + iPin) & 3;
1891	pBus = pBus->aPciDev.Int.s.pBusR3;
1892	};
1893	}
1894
1895	int iIrq = aPciIrqs[ich9pciSlotGetPirq(uBus, uDevFn, iPin)];
1896	Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
1897	iPin, iIrq, uBus, uDevFn>>3, uDevFn&7));
1898	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
1899	}
1900	}
1901
1902	/**
1903	* Initializes bridges registers used for routing.
1904	*
1905	* @returns nothing.
1906	* @param pGlobals Global device instance data used to generate unique bus numbers.
1907	* @param pBus The PCI bus to initialize.
1908	* @param uBusPrimary The primary bus number the bus is connected to.
1909	* @param uBusSecondary The secondary bus number, i.e. the bus number behind the bridge.
1910	*/
1911	static void ich9pciInitBridgeTopology(PICH9PCIGLOBALS pGlobals, PICH9PCIBUS pBus, unsigned uBusPrimary,
1912	unsigned uBusSecondary)
1913	{
1914	PPCIDEVICE pBridgeDev = &pBus->aPciDev;
1915
1916	/* Set only if we are not on the root bus, it has no primary bus attached. */
1917	if (uBusSecondary != 0)
1918	{
1919	PCIDevSetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, uBusPrimary);
1920	PCIDevSetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, uBusSecondary);
1921	}
1922
1923	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1924	{
1925	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
1926	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
1927	("Device is not a PCI bridge but on the list of PCI bridges\n"));
1928	PICH9PCIBUS pChildBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1929	pGlobals->uBus++;
1930	ich9pciInitBridgeTopology(pGlobals, pChildBus, uBusSecondary, pGlobals->uBus);
1931	}
1932	PCIDevSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1933	Log2(("ich9pciInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
1934	pBus,
1935	PCIDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
1936	PCIDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
1937	PCIDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS)
1938	));
1939	}
1940
1941
1942	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1943	{
1944	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1945
1946	/*
1947	* Set the start addresses.
1948	*/
1949	pGlobals->uPciBiosIo = 0xd000;
1950	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
1951	pGlobals->uBus = 0;
1952
1953	/*
1954	* Assign bridge topology, for further routing to work.
1955	*/
1956	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1957	ich9pciInitBridgeTopology(pGlobals, pBus, 0, 0);
1958
1959	/*
1960	* Init the devices.
1961	*/
1962	for (int i = 0; i < 256; i++)
1963	ich9pciBiosInitDevice(pGlobals, 0, i);
1964
1965	return VINF_SUCCESS;
1966	}
1967
1968
1969	/*
1970	* Configuration space read callback (PCIDEVICEINT::pfnConfigRead) for
1971	* connected devices.
1972	*/
1973	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len)
1974	{
1975	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1976	{
1977	LogRel(("PCI: %8s/%u: Read from extended register %d fallen back to generic code\n",
1978	aDev->name, aDev->pDevIns->iInstance, u32Address));
1979	return 0;
1980	}
1981
1982	AssertMsgReturn(u32Address + len <= 256, ("Read after the end of PCI config space\n"),
1983	0);
1984	if ( pciDevIsMsiCapable(aDev)
1985	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1986	&& (u32Address < (unsigned)(aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize))
1987	)
1988	{
1989	return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1990	}
1991
1992	if ( pciDevIsMsixCapable(aDev)
1993	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
1994	&& (u32Address < (unsigned)(aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize))
1995	)
1996	{
1997	return MsixPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1998	}
1999
2000	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
2001	0);
2002	switch (len)
2003	{
2004	case 1:
2005	return PCIDevGetByte(aDev, u32Address);
2006	case 2:
2007	return PCIDevGetWord(aDev, u32Address);
2008	case 4:
2009	return PCIDevGetDWord(aDev, u32Address);
2010	default:
2011	Assert(false);
2012	return 0;
2013	}
2014	}
2015
2016
2017	DECLINLINE(void) ich9pciWriteBarByte(PCIDevice *aDev, int iRegion, int iOffset, uint8_t u8Val)
2018	{
2019	PCIIORegion * pRegion = &aDev->Int.s.aIORegions[iRegion];
2020	int64_t iRegionSize = pRegion->size;
2021
2022	Log3(("ich9pciWriteBarByte: region=%d off=%d val=%x size=%d\n",
2023	iRegion, iOffset, u8Val, iRegionSize));
2024
2025	if (iOffset > 3)
2026	Assert((pRegion->type & PCI_ADDRESS_SPACE_BAR64) != 0);
2027
2028	/* Check if we're writing to upper part of 64-bit BAR. */
2029	if (pRegion->type == 0xff)
2030	{
2031	ich9pciWriteBarByte(aDev, iRegion-1, iOffset+4, u8Val);
2032	return;
2033	}
2034
2035	/* Region doesn't exist */
2036	if (iRegionSize == 0)
2037	return;
2038
2039	uint32_t uAddr = ich9pciGetRegionReg(iRegion) + iOffset;
2040	/* Region size must be power of two */
2041	Assert((iRegionSize & (iRegionSize - 1)) == 0);
2042	uint8_t uMask = ((iRegionSize - 1) >> (iOffset*8) ) & 0xff;
2043
2044	if (iOffset == 0)
2045	{
2046	uMask \|= (pRegion->type & PCI_ADDRESS_SPACE_IO) ?
2047	(1 << 2) - 1 /* 2 lowest bits for IO region */ :
2048	(1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
2049
2050	}
2051
2052	uint8_t u8Old = PCIDevGetByte(aDev, uAddr) & uMask;
2053	u8Val = (u8Old & uMask) \| (u8Val & ~uMask);
2054
2055	Log3(("ich9pciWriteBarByte: was %x writing %x\n", u8Old, u8Val));
2056
2057	PCIDevSetByte(aDev, uAddr, u8Val);
2058	}
2059
2060
2061	/**
2062	* Configuration space write callback (PCIDEVICEINT::pfnConfigWrite)
2063	* for connected devices.
2064	*
2065	* See paragraph 7.5 of PCI Express specification (p. 349) for
2066	* definition of registers and their writability policy.
2067	*/
2068	static DECLCALLBACK(void) ich9pciConfigWriteDev(PCIDevice *aDev, uint32_t u32Address,
2069	uint32_t val, unsigned len)
2070	{
2071	Assert(len <= 4);
2072
2073	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
2074	{
2075	LogRel(("PCI: %8s/%u: Write to extended register %d fallen back to generic code\n",
2076	aDev->name, aDev->pDevIns->iInstance, u32Address));
2077	return;
2078	}
2079
2080	AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
2081
2082	if ( pciDevIsMsiCapable(aDev)
2083	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
2084	&& (u32Address < (unsigned)(aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize))
2085	)
2086	{
2087	MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2088	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2089	aDev, u32Address, val, len);
2090	return;
2091	}
2092
2093	if ( pciDevIsMsixCapable(aDev)
2094	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
2095	&& (u32Address < (unsigned)(aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize))
2096	)
2097	{
2098	MsixPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2099	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2100	aDev, u32Address, val, len);
2101	return;
2102	}
2103
2104	uint32_t addr = u32Address;
2105	bool fUpdateMappings = false;
2106	bool fP2PBridge = false;
2107	/bool fPassthrough = pciDevIsPassthrough(aDev);/
2108	uint8_t u8HeaderType = ich9pciGetByte(aDev, VBOX_PCI_HEADER_TYPE);
2109
2110	for (uint32_t i = 0; i < len; i++)
2111	{
2112	bool fWritable = false;
2113	bool fRom = false;
2114	switch (u8HeaderType)
2115	{
2116	case 0x00: /* normal device */
2117	case 0x80: /* multi-function device */
2118	switch (addr)
2119	{
2120	/* Read-only registers */
2121	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2122	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2123	case VBOX_PCI_REVISION_ID:
2124	case VBOX_PCI_CLASS_PROG:
2125	case VBOX_PCI_CLASS_SUB:
2126	case VBOX_PCI_CLASS_BASE:
2127	case VBOX_PCI_HEADER_TYPE:
2128	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
2129	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
2130	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
2131	case VBOX_PCI_CAPABILITY_LIST:
2132	case VBOX_PCI_INTERRUPT_PIN:
2133	fWritable = false;
2134	break;
2135	/* Others can be written */
2136	default:
2137	fWritable = true;
2138	break;
2139	}
2140	break;
2141	case 0x01: /* PCI-PCI bridge */
2142	fP2PBridge = true;
2143	switch (addr)
2144	{
2145	/* Read-only registers */
2146	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2147	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2148	case VBOX_PCI_REVISION_ID:
2149	case VBOX_PCI_CLASS_PROG:
2150	case VBOX_PCI_CLASS_SUB:
2151	case VBOX_PCI_CLASS_BASE:
2152	case VBOX_PCI_HEADER_TYPE:
2153	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
2154	case VBOX_PCI_INTERRUPT_PIN:
2155	fWritable = false;
2156	break;
2157	default:
2158	fWritable = true;
2159	break;
2160	}
2161	break;
2162	default:
2163	AssertMsgFailed(("Unknown header type %x\n", PCIDevGetHeaderType(aDev)));
2164	fWritable = false;
2165	break;
2166	}
2167
2168	uint8_t u8Val = (uint8_t)val;
2169	switch (addr)
2170	{
2171	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
2172	fUpdateMappings = true;
2173	goto default_case;
2174	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
2175	/* don't change reserved bits (11-15) */
2176	u8Val &= ~UINT32_C(0xf8);
2177	fUpdateMappings = true;
2178	goto default_case;
2179	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
2180	/* don't change read-only bits => actually all lower bits are read-only */
2181	u8Val &= ~UINT32_C(0xff);
2182	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
2183	aDev->config[addr] &= ~u8Val;
2184	break;
2185	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
2186	/* don't change read-only bits */
2187	u8Val &= ~UINT32_C(0x06);
2188	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
2189	aDev->config[addr] &= ~u8Val;
2190	break;
2191	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3:
2192	fRom = true;
2193	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
2194	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
2195	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
2196	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
2197	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
2198	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
2199	{
2200	/* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
2201	if (fP2PBridge)
2202	goto default_case;
2203	else
2204	{
2205	int iRegion = fRom ? VBOX_PCI_ROM_SLOT : (addr - VBOX_PCI_BASE_ADDRESS_0) >> 2;
2206	int iOffset = addr & 0x3;
2207	ich9pciWriteBarByte(aDev, iRegion, iOffset, u8Val);
2208	fUpdateMappings = true;
2209	}
2210	break;
2211	}
2212	default:
2213	default_case:
2214	if (fWritable)
2215	PCIDevSetByte(aDev, addr, u8Val);
2216	}
2217	addr++;
2218	val >>= 8;
2219	}
2220
2221	if (fUpdateMappings)
2222	/* if the command/base address register is modified, we must modify the mappings */
2223	ich9pciUpdateMappings(aDev);
2224	}
2225
2226	static bool assignPosition(PICH9PCIBUS pBus, PPCIDEVICE pPciDev, const char pszName, int iDevFn, PciAddress aPosition)
2227	{
2228	NOREF(pszName);
2229	aPosition->iBus = 0;
2230	aPosition->iDeviceFunc = iDevFn;
2231	aPosition->iRegister = 0; /* N/A */
2232
2233	/* Explicit slot request */
2234	if (iDevFn >= 0 && iDevFn < (int)RT_ELEMENTS(pBus->apDevices))
2235	return true;
2236
2237	int iStartPos = 0;
2238
2239	/* Otherwise when assigning a slot, we need to make sure all its functions are available */
2240	for (int iPos = iStartPos; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
2241	{
2242	if ( !pBus->apDevices[iPos]
2243	&& !pBus->apDevices[iPos + 1]
2244	&& !pBus->apDevices[iPos + 2]
2245	&& !pBus->apDevices[iPos + 3]
2246	&& !pBus->apDevices[iPos + 4]
2247	&& !pBus->apDevices[iPos + 5]
2248	&& !pBus->apDevices[iPos + 6]
2249	&& !pBus->apDevices[iPos + 7])
2250	{
2251	pciDevClearRequestedDevfunc(pPciDev);
2252	aPosition->iDeviceFunc = iPos;
2253	return true;
2254	}
2255	}
2256
2257	return false;
2258	}
2259
2260	#ifdef SOME_UNUSED_FUNCTION
2261	static bool hasHardAssignedDevsInSlot(PICH9PCIBUS pBus, int iSlot)
2262	{
2263	PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
2264
2265	return (aSlot[0] && pciDevIsRequestedDevfunc(aSlot[0]))
2266	\|\| (aSlot[1] && pciDevIsRequestedDevfunc(aSlot[1]))
2267	\|\| (aSlot[2] && pciDevIsRequestedDevfunc(aSlot[2]))
2268	\|\| (aSlot[3] && pciDevIsRequestedDevfunc(aSlot[3]))
2269	\|\| (aSlot[4] && pciDevIsRequestedDevfunc(aSlot[4]))
2270	\|\| (aSlot[5] && pciDevIsRequestedDevfunc(aSlot[5]))
2271	\|\| (aSlot[6] && pciDevIsRequestedDevfunc(aSlot[6]))
2272	\|\| (aSlot[7] && pciDevIsRequestedDevfunc(aSlot[7]))
2273	;
2274	}
2275	#endif
2276
2277	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
2278	{
2279	PciAddress aPosition;
2280	aPosition.iBus = 0;
2281	aPosition.iDeviceFunc = 0;
2282	aPosition.iRegister = 0;
2283
2284	/*
2285	* Find device position
2286	*/
2287	if (!assignPosition(pBus, pPciDev, pszName, iDev, &aPosition))
2288	{
2289	AssertMsgFailed(("Couldn't asssign position!\n"));
2290	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2291	}
2292
2293	AssertMsgReturn(aPosition.iBus == 0,
2294	("Assigning behind the bridge not implemented yet\n"),
2295	VERR_PDM_TOO_PCI_MANY_DEVICES);
2296
2297
2298	iDev = aPosition.iDeviceFunc;
2299	/*
2300	* Check if we can really take this slot, possibly by relocating
2301	* its current habitant, if it wasn't hard assigned too.
2302	*/
2303	if (pciDevIsRequestedDevfunc(pPciDev) &&
2304	pBus->apDevices[iDev] &&
2305	pciDevIsRequestedDevfunc(pBus->apDevices[iDev]))
2306	{
2307	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
2308	pszName, pBus->apDevices[iDev]->name, iDev));
2309	return VERR_INTERNAL_ERROR;
2310	}
2311
2312	if (pBus->apDevices[iDev])
2313	{
2314	/* if we got here, we shall (and usually can) relocate the device */
2315	bool assigned = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name, -1, &aPosition);
2316	AssertMsgReturn(aPosition.iBus == 0,
2317	("Assigning behind the bridge not implemented yet\n"),
2318	VERR_PDM_TOO_PCI_MANY_DEVICES);
2319	int iRelDev = aPosition.iDeviceFunc;
2320	if (!assigned \|\| iRelDev == iDev)
2321	{
2322	AssertMsgFailed(("Couldn't find free spot!\n"));
2323	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2324	}
2325	/* Copy device function by function to its new position */
2326	for (int i = 0; i < 8; i++)
2327	{
2328	if (!pBus->apDevices[iDev + i])
2329	continue;
2330	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
2331	pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
2332	pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
2333	pBus->apDevices[iDev + i] = NULL;
2334	}
2335	}
2336
2337	/*
2338	* Fill in device information.
2339	*/
2340	pPciDev->devfn = iDev;
2341	pPciDev->name = pszName;
2342	pPciDev->Int.s.pBusR3 = pBus;
2343	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2344	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2345	pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
2346	pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
2347	pBus->apDevices[iDev] = pPciDev;
2348	if (pciDevIsPci2PciBridge(pPciDev))
2349	{
2350	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2351	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2352	("device is a bridge but does not implement read/write functions\n"));
2353	Log2(("Setting bridge %d on bus %p\n", pBus->cBridges, pBus));
2354	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2355	pBus->cBridges++;
2356	}
2357
2358	Log(("PCI: Registered device %d function %d on bus %d (%#x) '%s'.\n",
2359	iDev >> 3, iDev & 7, pBus->iBus, 0x80000000 \| (iDev << 8), pszName));
2360
2361	return VINF_SUCCESS;
2362	}
2363
2364	static void printIndent(PCDBGFINFOHLP pHlp, int iIndent)
2365	{
2366	for (int i = 0; i < iIndent; i++)
2367	{
2368	pHlp->pfnPrintf(pHlp, " ");
2369	}
2370	}
2371
2372	static void ich9pciBusInfo(PICH9PCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
2373	{
2374	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2375	{
2376	PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2377	if (pPciDev != NULL)
2378	{
2379	printIndent(pHlp, iIndent);
2380
2381	/*
2382	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2383	* as host driver handles real devices interrupts.
2384	*/
2385	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x",
2386	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2387	pPciDev->name,
2388	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2389	ich9pciGetWord(pPciDev, VBOX_PCI_VENDOR_ID), ich9pciGetWord(pPciDev, VBOX_PCI_DEVICE_ID)
2390	);
2391	if (ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2392	{
2393	pHlp->pfnPrintf(pHlp, " IRQ%d", ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2394	pHlp->pfnPrintf(pHlp, " (INTA#->IRQ%d)", 0x10 + ich9pciSlot2ApicIrq(iDev >> 3, 0));
2395	}
2396	pHlp->pfnPrintf(pHlp, "\n");
2397
2398	if (pciDevIsMsiCapable(pPciDev) \|\| pciDevIsMsixCapable(pPciDev))
2399	{
2400	printIndent(pHlp, iIndent + 2);
2401
2402	if (pciDevIsMsiCapable(pPciDev))
2403	pHlp->pfnPrintf(pHlp, "MSI:%s ", MsiIsEnabled(pPciDev) ? "on" : "off");
2404
2405	if (pciDevIsMsixCapable(pPciDev))
2406	pHlp->pfnPrintf(pHlp, "MSI-X:%s ", MsixIsEnabled(pPciDev) ? "on" : "off");
2407
2408	pHlp->pfnPrintf(pHlp, "\n");
2409	}
2410
2411	uint16_t iCmd = ich9pciGetWord(pPciDev, VBOX_PCI_COMMAND);
2412	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
2413	{
2414	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2415	{
2416	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2417	uint64_t iRegionSize = pRegion->size;
2418
2419	if (iRegionSize == 0)
2420	continue;
2421
2422	uint32_t u32Addr = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion));
2423	const char * pszDesc;
2424	char szDescBuf[128];
2425
2426	bool f64Bit = !!(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
2427	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2428	{
2429	pszDesc = "IO";
2430	u32Addr &= ~0x3;
2431	}
2432	else
2433	{
2434	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2435	f64Bit ? "64" : "32",
2436	(pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
2437	pszDesc = szDescBuf;
2438	u32Addr &= ~0xf;
2439	}
2440
2441	printIndent(pHlp, iIndent + 2);
2442	pHlp->pfnPrintf(pHlp, "%s region #%d: %x..%x\n",
2443	pszDesc, iRegion, u32Addr, u32Addr+iRegionSize);
2444	if (f64Bit)
2445	iRegion++;
2446	}
2447	}
2448
2449	printIndent(pHlp, iIndent + 2);
2450	uint16_t iStatus = ich9pciGetWord(pPciDev, VBOX_PCI_STATUS);
2451	pHlp->pfnPrintf(pHlp, "Command: %04X, Status: %04X\n",
2452	iCmd, iStatus);
2453	printIndent(pHlp, iIndent + 2);
2454	pHlp->pfnPrintf(pHlp, "Bus master: %s\n",
2455	iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2456
2457	if (fRegisters)
2458	{
2459	printIndent(pHlp, iIndent + 2);
2460	pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2461	for (int iReg = 0; iReg < 0x100; )
2462	{
2463	int iPerLine = 0x10;
2464	Assert (0x100 % iPerLine == 0);
2465	printIndent(pHlp, iIndent + 3);
2466
2467	while (iPerLine-- > 0)
2468	{
2469	pHlp->pfnPrintf(pHlp, "%02x ", ich9pciGetByte(pPciDev, iReg++));
2470	}
2471	pHlp->pfnPrintf(pHlp, "\n");
2472	}
2473	}
2474	}
2475	}
2476
2477	if (pBus->cBridges > 0)
2478	{
2479	printIndent(pHlp, iIndent);
2480	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2481	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2482	{
2483	PICH9PCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PICH9PCIBUS);
2484	ich9pciBusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2485	}
2486	}
2487	}
2488
2489	/**
2490	* Info handler, device version.
2491	*
2492	* @param pDevIns Device instance which registered the info.
2493	* @param pHlp Callback functions for doing output.
2494	* @param pszArgs Argument string. Optional and specific to the handler.
2495	*/
2496	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2497	{
2498	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2499
2500	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2501	{
2502	ich9pciBusInfo(pBus, pHlp, 0, false);
2503	}
2504	else if (!strcmp(pszArgs, "verbose"))
2505	{
2506	ich9pciBusInfo(pBus, pHlp, 0, true);
2507	}
2508	else
2509	{
2510	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2511	}
2512	}
2513
2514
2515	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2516	{
2517	RT_NOREF1(iInstance);
2518	Assert(iInstance == 0);
2519	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2520
2521	/*
2522	* Validate and read configuration.
2523	*/
2524	if (!CFGMR3AreValuesValid(pCfg,
2525	"IOAPIC\0"
2526	"GCEnabled\0"
2527	"R0Enabled\0"
2528	"McfgBase\0"
2529	"McfgLength\0"
2530	))
2531	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2532
2533	/* query whether we got an IOAPIC */
2534	bool fUseIoApic;
2535	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2536	if (RT_FAILURE(rc))
2537	return PDMDEV_SET_ERROR(pDevIns, rc,
2538	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2539
2540	/* check if RC code is enabled. */
2541	bool fGCEnabled;
2542	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2543	if (RT_FAILURE(rc))
2544	return PDMDEV_SET_ERROR(pDevIns, rc,
2545	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2546	/* check if R0 code is enabled. */
2547	bool fR0Enabled;
2548	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2549	if (RT_FAILURE(rc))
2550	return PDMDEV_SET_ERROR(pDevIns, rc,
2551	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2552
2553	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2554
2555	/*
2556	* Init data.
2557	*/
2558	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2559	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2560	/* Zero out everything */
2561	memset(pGlobals, 0, sizeof(*pGlobals));
2562	/* And fill values */
2563	if (!fUseIoApic)
2564	return PDMDEV_SET_ERROR(pDevIns, rc,
2565	N_("Must use IO-APIC with ICH9 chipset"));
2566	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2567	if (RT_FAILURE(rc))
2568	return PDMDEV_SET_ERROR(pDevIns, rc,
2569	N_("Configuration error: Failed to read \"McfgBase\""));
2570	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2571	if (RT_FAILURE(rc))
2572	return PDMDEV_SET_ERROR(pDevIns, rc,
2573	N_("Configuration error: Failed to read \"McfgLength\""));
2574
2575	pGlobals->pDevInsR3 = pDevIns;
2576	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2577	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2578
2579	pGlobals->aPciBus.pDevInsR3 = pDevIns;
2580	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2581	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2582	pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2583
2584	/*
2585	* Register bus
2586	*/
2587	PDMPCIBUSREG PciBusReg;
2588	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2589	PciBusReg.pfnRegisterR3 = ich9pciRegister;
2590	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2591	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2592	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2593	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2594	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2595	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2596	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2597	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2598	if (RT_FAILURE(rc))
2599	return PDMDEV_SET_ERROR(pDevIns, rc,
2600	N_("Failed to register ourselves as a PCI Bus"));
2601	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2602	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2603	N_("PCI helper version mismatch; got %#x expected %#x"),
2604	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2605
2606	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2607	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2608
2609	/*
2610	* Fill in PCI configs and add them to the bus.
2611	*/
2612	/** @todo: Disabled for now because this causes error messages with Linux guests.
2613	* The guest loads the x38_edac device which tries to map a memory region
2614	* using an address given at place 0x48 - 0x4f in the PCi config space.
2615	* This fails. because we don't register such a region.
2616	*/
2617	#if 0
2618	/* Host bridge device */
2619	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2620	PCIDevSetDeviceId( &pBus->aPciDev, 0x29e0); /* Desktop */
2621	PCIDevSetRevisionId(&pBus->aPciDev, 0x01); /* rev. 01 */
2622	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2623	PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2624	PCIDevSetClassProg( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2625	PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* bridge */
2626	PCIDevSetWord(&pBus->aPciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
2627
2628	pBus->aPciDev.pDevIns = pDevIns;
2629	/* We register Host<->PCI controller on the bus */
2630	ich9pciRegisterInternal(pBus, 0, &pBus->aPciDev, "dram");
2631	#endif
2632
2633	/*
2634	* Register I/O ports and save state.
2635	*/
2636	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2637	if (RT_FAILURE(rc))
2638	return rc;
2639	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2640	if (RT_FAILURE(rc))
2641	return rc;
2642	if (fGCEnabled)
2643	{
2644	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2645	if (RT_FAILURE(rc))
2646	return rc;
2647	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2648	if (RT_FAILURE(rc))
2649	return rc;
2650	}
2651	if (fR0Enabled)
2652	{
2653	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2654	if (RT_FAILURE(rc))
2655	return rc;
2656	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2657	if (RT_FAILURE(rc))
2658	return rc;
2659	}
2660
2661	if (pGlobals->u64PciConfigMMioAddress != 0)
2662	{
2663	rc = PDMDevHlpMMIORegister(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength, NULL /pvUser/,
2664	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
2665	ich9pciMcfgMMIOWrite, ich9pciMcfgMMIORead, "MCFG ranges");
2666	AssertMsgRCReturn(rc, ("rc=%Rrc %#llx/%#llx\n", rc, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength), rc);
2667
2668	if (fGCEnabled)
2669	{
2670	rc = PDMDevHlpMMIORegisterRC(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2671	NIL_RTRCPTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2672	AssertRCReturn(rc, rc);
2673	}
2674
2675
2676	if (fR0Enabled)
2677	{
2678	rc = PDMDevHlpMMIORegisterR0(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2679	NIL_RTR0PTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2680	AssertRCReturn(rc, rc);
2681	}
2682	}
2683
2684	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2685	sizeof(pBus) + 16128, "pgm",
2686	NULL, NULL, NULL,
2687	NULL, ich9pciR3SaveExec, NULL,
2688	NULL, ich9pciR3LoadExec, NULL);
2689	if (RT_FAILURE(rc))
2690	return rc;
2691
2692
2693	/** @todo: other chipset devices shall be registered too */
2694
2695	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. Recognizes 'basic' or 'verbose' "
2696	"as arguments, defaults to 'basic'.", ich9pciInfo);
2697
2698	return VINF_SUCCESS;
2699	}
2700
2701	static void ich9pciResetDevice(PPCIDEVICE pDev)
2702	{
2703	/* Clear regions */
2704	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2705	{
2706	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
2707	if (pRegion->size == 0)
2708	continue;
2709
2710	ich9pciUnmapRegion(pDev, iRegion);
2711	}
2712
2713	if (pciDevIsPassthrough(pDev))
2714	{
2715	// no reset handler - we can do what we need in PDM reset handler
2716	// @todo: is it correct?
2717	}
2718	else
2719	{
2720	PCIDevSetCommand(pDev,
2721	PCIDevGetCommand(pDev)
2722	&
2723	~(VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY \|
2724	VBOX_PCI_COMMAND_MASTER \| VBOX_PCI_COMMAND_SPECIAL \|
2725	VBOX_PCI_COMMAND_PARITY \| VBOX_PCI_COMMAND_SERR \|
2726	VBOX_PCI_COMMAND_FAST_BACK \| VBOX_PCI_COMMAND_INTX_DISABLE));
2727
2728	/* Bridge device reset handlers processed later */
2729	if (!pciDevIsPci2PciBridge(pDev))
2730	{
2731	PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2732	PCIDevSetInterruptLine(pDev, 0x0);
2733	}
2734
2735	/* Reset MSI message control. */
2736	if (pciDevIsMsiCapable(pDev))
2737	{
2738	/* Extracted from MsiPciConfigWrite(). */
2739	pDev->config[pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL] &= 0x8e;
2740	}
2741
2742	/* Reset MSI-X message control. */
2743	if (pciDevIsMsixCapable(pDev))
2744	{
2745	/* Extracted from MsixPciConfigWrite(); no side effects. */
2746	pDev->config[pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL + 1] &= 0x3f;
2747	}
2748	}
2749	}
2750
2751
2752	/**
2753	* @copydoc FNPDMDEVRESET
2754	*/
2755	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2756	{
2757	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2758	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2759
2760	/* PCI-specific reset for each device. */
2761	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2762	{
2763	if (pBus->apDevices[i])
2764	ich9pciResetDevice(pBus->apDevices[i]);
2765	}
2766
2767	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2768	{
2769	if (pBus->papBridgesR3[iBridge])
2770	ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->pDevIns);
2771	}
2772
2773	ich9pciFakePCIBIOS(pDevIns);
2774	}
2775
2776	static void ich9pciRelocateDevice(PPCIDEVICE pDev, RTGCINTPTR offDelta)
2777	{
2778	if (pDev)
2779	{
2780	pDev->Int.s.pBusRC += offDelta;
2781	if (pDev->Int.s.pMsixPageRC)
2782	pDev->Int.s.pMsixPageRC += offDelta;
2783	}
2784	}
2785
2786	/**
2787	* @copydoc FNPDMDEVRELOCATE
2788	*/
2789	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2790	{
2791	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2792	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2793	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2794
2795	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2796	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2797
2798	/* Relocate RC pointers for the attached pci devices. */
2799	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2800	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2801
2802	}
2803
2804	/**
2805	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2806	*/
2807	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2808	int iInstance,
2809	PCFGMNODE pCfg)
2810	{
2811	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2812
2813	/*
2814	* Validate and read configuration.
2815	*/
2816	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2817	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2818
2819	/* check if RC code is enabled. */
2820	bool fGCEnabled;
2821	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2822	if (RT_FAILURE(rc))
2823	return PDMDEV_SET_ERROR(pDevIns, rc,
2824	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2825
2826	/* check if R0 code is enabled. */
2827	bool fR0Enabled;
2828	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2829	if (RT_FAILURE(rc))
2830	return PDMDEV_SET_ERROR(pDevIns, rc,
2831	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2832	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2833
2834	/*
2835	* Init data and register the PCI bus.
2836	*/
2837	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2838	pBus->pDevInsR3 = pDevIns;
2839	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2840	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2841	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->apDevices));
2842
2843	PDMPCIBUSREG PciBusReg;
2844	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2845	PciBusReg.pfnRegisterR3 = ich9pcibridgeRegister;
2846	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2847	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2848	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2849	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2850	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2851	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2852	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2853	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2854	if (RT_FAILURE(rc))
2855	return PDMDEV_SET_ERROR(pDevIns, rc,
2856	N_("Failed to register ourselves as a PCI Bus"));
2857	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2858	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2859	N_("PCI helper version mismatch; got %#x expected %#x"),
2860	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2861
2862	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2863	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2864
2865	/* Disable default device locking. */
2866	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2867	AssertRCReturn(rc, rc);
2868
2869	/*
2870	* Fill in PCI configs and add them to the bus.
2871	*/
2872	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2873	PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2874	PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2875	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2876	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2877	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2878	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2879	PCIDevSetCommand( &pBus->aPciDev, 0x00);
2880	PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2881	PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2882
2883	/*
2884	* This device does not generate interrupts. Interrupt delivery from
2885	* devices attached to the bus is unaffected.
2886	*/
2887	PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2888
2889	pBus->aPciDev.pDevIns = pDevIns;
2890
2891	/* Bridge-specific data */
2892	pciDevSetPci2PciBridge(&pBus->aPciDev);
2893	pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2894	pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2895
2896	/*
2897	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2898	*/
2899	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2900	if (RT_FAILURE(rc))
2901	return rc;
2902
2903	/*
2904	* The iBus property doesn't really represent the bus number
2905	* because the guest and the BIOS can choose different bus numbers
2906	* for them.
2907	* The bus number is mainly for the setIrq function to indicate
2908	* when the host bus is reached which will have iBus = 0.
2909	* That's why the + 1.
2910	*/
2911	pBus->iBus = iInstance + 1;
2912
2913	/*
2914	* Register SSM handlers. We use the same saved state version as for the host bridge
2915	* to make changes easier.
2916	*/
2917	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2918	sizeof(pBus) + 16128,
2919	"pgm" /* before */,
2920	NULL, NULL, NULL,
2921	NULL, ich9pcibridgeR3SaveExec, NULL,
2922	NULL, ich9pcibridgeR3LoadExec, NULL);
2923	if (RT_FAILURE(rc))
2924	return rc;
2925
2926
2927	return VINF_SUCCESS;
2928	}
2929
2930	/**
2931	* @copydoc FNPDMDEVRESET
2932	*/
2933	static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
2934	{
2935	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2936
2937	/* Reset config space to default values. */
2938	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2939	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2940	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2941
2942	/* PCI-specific reset for each device. */
2943	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2944	{
2945	if (pBus->apDevices[i])
2946	ich9pciResetDevice(pBus->apDevices[i]);
2947	}
2948	}
2949
2950
2951	/**
2952	* @copydoc FNPDMDEVRELOCATE
2953	*/
2954	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2955	{
2956	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2957	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2958
2959	/* Relocate RC pointers for the attached pci devices. */
2960	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2961	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2962	}
2963
2964	/**
2965	* The PCI bus device registration structure.
2966	*/
2967	const PDMDEVREG g_DevicePciIch9 =
2968	{
2969	/* u32Version */
2970	PDM_DEVREG_VERSION,
2971	/* szName */
2972	"ich9pci",
2973	/* szRCMod */
2974	"VBoxDDRC.rc",
2975	/* szR0Mod */
2976	"VBoxDDR0.r0",
2977	/* pszDescription */
2978	"ICH9 PCI bridge",
2979	/* fFlags */
2980	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2981	/* fClass */
2982	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2983	/* cMaxInstances */
2984	1,
2985	/* cbInstance */
2986	sizeof(ICH9PCIGLOBALS),
2987	/* pfnConstruct */
2988	ich9pciConstruct,
2989	/* pfnDestruct */
2990	NULL,
2991	/* pfnRelocate */
2992	ich9pciRelocate,
2993	/* pfnMemSetup */
2994	NULL,
2995	/* pfnPowerOn */
2996	NULL,
2997	/* pfnReset */
2998	ich9pciReset,
2999	/* pfnSuspend */
3000	NULL,
3001	/* pfnResume */
3002	NULL,
3003	/* pfnAttach */
3004	NULL,
3005	/* pfnDetach */
3006	NULL,
3007	/* pfnQueryInterface */
3008	NULL,
3009	/* pfnInitComplete */
3010	NULL,
3011	/* pfnPowerOff */
3012	NULL,
3013	/* pfnSoftReset */
3014	NULL,
3015	/* u32VersionEnd */
3016	PDM_DEVREG_VERSION
3017	};
3018
3019	/**
3020	* The device registration structure
3021	* for the PCI-to-PCI bridge.
3022	*/
3023	const PDMDEVREG g_DevicePciIch9Bridge =
3024	{
3025	/* u32Version */
3026	PDM_DEVREG_VERSION,
3027	/* szName */
3028	"ich9pcibridge",
3029	/* szRCMod */
3030	"VBoxDDRC.rc",
3031	/* szR0Mod */
3032	"VBoxDDR0.r0",
3033	/* pszDescription */
3034	"ICH9 PCI to PCI bridge",
3035	/* fFlags */
3036	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
3037	/* fClass */
3038	PDM_DEVREG_CLASS_BUS_PCI,
3039	/* cMaxInstances */
3040	~0U,
3041	/* cbInstance */
3042	sizeof(ICH9PCIBUS),
3043	/* pfnConstruct */
3044	ich9pcibridgeConstruct,
3045	/* pfnDestruct */
3046	NULL,
3047	/* pfnRelocate */
3048	ich9pcibridgeRelocate,
3049	/* pfnMemSetup */
3050	NULL,
3051	/* pfnPowerOn */
3052	NULL,
3053	/* pfnReset */
3054	NULL, /* Must be NULL, to make sure only bus driver handles reset */
3055	/* pfnSuspend */
3056	NULL,
3057	/* pfnResume */
3058	NULL,
3059	/* pfnAttach */
3060	NULL,
3061	/* pfnDetach */
3062	NULL,
3063	/* pfnQueryInterface */
3064	NULL,
3065	/* pfnInitComplete */
3066	NULL,
3067	/* pfnPowerOff */
3068	NULL,
3069	/* pfnSoftReset */
3070	NULL,
3071	/* u32VersionEnd */
3072	PDM_DEVREG_VERSION
3073	};
3074
3075	#endif /* IN_RING3 */
3076	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 63009

Download in other formats: