DevPciIch9.cpp@ 37324

Last change on this file since 37324 was 36836, checked in by vboxsync, 13 years ago
PCI: don't fail on extended caps access, just record
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1	/* $Id: DevPciIch9.cpp 36836 2011-04-25 07:09:56Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation device.
4	*/
5
6	/*
7	* Copyright (C) 2010-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_PCI
22	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
23	#define PCI_INCLUDE_PRIVATE
24	#define PCIBus ICH9PCIBus
25	#include <VBox/pci.h>
26	#include <VBox/msi.h>
27	#include <VBox/vmm/pdmdev.h>
28	#include <iprt/asm.h>
29	#include <iprt/assert.h>
30	#include <iprt/string.h>
31	#ifdef IN_RING3
32	#include <iprt/alloc.h>
33	#endif
34
35	#include "VBoxDD.h"
36
37	#include "MsiCommon.h"
38
39
40	/*******************************************************************************
41	* Structures and Typedefs *
42	*******************************************************************************/
43	/**
44	* PCI Bus instance.
45	*/
46	typedef struct ICH9PCIBus
47	{
48	/** Bus number. */
49	int32_t iBus;
50	/** Number of bridges attached to the bus. */
51	uint32_t cBridges;
52
53	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
54	R3PTRTYPE(PPCIDEVICE) apDevices[256];
55	/** Array of bridges attached to the bus. */
56	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
57
58	/** R3 pointer to the device instance. */
59	PPDMDEVINSR3 pDevInsR3;
60	/** Pointer to the PCI R3 helpers. */
61	PCPDMPCIHLPR3 pPciHlpR3;
62
63	/** R0 pointer to the device instance. */
64	PPDMDEVINSR0 pDevInsR0;
65	/** Pointer to the PCI R0 helpers. */
66	PCPDMPCIHLPR0 pPciHlpR0;
67
68	/** RC pointer to the device instance. */
69	PPDMDEVINSRC pDevInsRC;
70	/** Pointer to the PCI RC helpers. */
71	PCPDMPCIHLPRC pPciHlpRC;
72
73	/** The PCI device for the PCI bridge. */
74	PCIDEVICE aPciDev;
75
76	} ICH9PCIBUS, *PICH9PCIBUS;
77
78
79	/** @def PCI_APIC_IRQ_PINS
80	* Number of pins for interrupts if the APIC is used.
81	*/
82	#define PCI_APIC_IRQ_PINS 8
83
84	/**
85	* PCI Globals - This is the host-to-pci bridge and the root bus.
86	*/
87	typedef struct
88	{
89	/** R3 pointer to the device instance. */
90	PPDMDEVINSR3 pDevInsR3;
91	/** R0 pointer to the device instance. */
92	PPDMDEVINSR0 pDevInsR0;
93	/** RC pointer to the device instance. */
94	PPDMDEVINSRC pDevInsRC;
95
96	#if HC_ARCH_BITS == 64
97	uint32_t Alignment0;
98	#endif
99
100	/** Config register. */
101	uint32_t uConfigReg;
102
103	/** I/O APIC irq levels */
104	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
105
106	#if 1 /* Will be moved into the BIOS soon. */
107	/** The next I/O port address which the PCI BIOS will use. */
108	uint32_t uPciBiosIo;
109	/** The next MMIO address which the PCI BIOS will use. */
110	uint32_t uPciBiosMmio;
111	/** Actual bus number. */
112	uint8_t uBus;
113	#endif
114	/* Physical address of PCI config space MMIO region */
115	uint64_t u64PciConfigMMioAddress;
116	/* Length of PCI config space MMIO region */
117	uint64_t u64PciConfigMMioLength;
118
119	/** PCI bus which is attached to the host-to-PCI bridge. */
120	ICH9PCIBUS aPciBus;
121	} ICH9PCIGLOBALS, *PICH9PCIGLOBALS;
122
123
124	typedef struct
125	{
126	uint8_t iBus;
127	uint8_t iDeviceFunc;
128	uint16_t iRegister;
129	} PciAddress;
130
131	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
132
133	/*******************************************************************************
134	* Defined Constants And Macros *
135	*******************************************************************************/
136
137	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
138	* Saved state version of the ICH9 PCI bus device.
139	*/
140	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
141	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
142	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
143
144	/** Converts a bus instance pointer to a device instance pointer. */
145	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
146	/** Converts a device instance pointer to a ICH9PCIGLOBALS pointer. */
147	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PICH9PCIGLOBALS)(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)))
148	/** Converts a device instance pointer to a PCIBUS pointer. */
149	#define DEVINS_2_PCIBUS(pDevIns) ((PICH9PCIBUS)(&PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)->aPciBus))
150	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer. */
151	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PICH9PCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(ICH9PCIGLOBALS, aPciBus)) )
152
153	/** @def PCI_LOCK
154	* Acquires the PDM lock. This is a NOP if locking is disabled. */
155	/** @def PCI_UNLOCK
156	* Releases the PDM lock. This is a NOP if locking is disabled. */
157	#define PCI_LOCK(pDevIns, rc) \
158	do { \
159	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
160	if (rc2 != VINF_SUCCESS) \
161	return rc2; \
162	} while (0)
163	#define PCI_UNLOCK(pDevIns) \
164	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
165
166	RT_C_DECLS_BEGIN
167
168	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
169	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
170	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
171	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
172	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
173	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
174	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
175	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
176
177	RT_C_DECLS_END
178
179	/* Prototypes */
180	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel);
181	#ifdef IN_RING3
182	static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
183	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
184	static void ich9pciUpdateMappings(PCIDevice *pDev);
185	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
186	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus);
187	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn);
188	#endif
189
190	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
191	// mapping, we take n=6 approach
192	DECLINLINE(void) ich9pciPhysToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
193	{
194	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<6) - 1);
195	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
196	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
197	}
198
199	DECLINLINE(void) ich9pciStateToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
200	{
201	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
202	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
203	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
204	}
205
206	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
207	{
208	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
209	}
210
211	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
212	{
213	/*
214	* The PCI-to-PCI bridge specification defines how the interrupt pins
215	* are routed from the secondary to the primary bus (see chapter 9).
216	* iIrq gives the interrupt pin the pci device asserted.
217	* We change iIrq here according to the spec and call the SetIrq function
218	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
219	*/
220	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
221	PPCIDEVICE pPciDevBus = pPciDev;
222	int iIrqPinBridge = iIrq;
223	uint8_t uDevFnBridge = 0;
224
225	/* Walk the chain until we reach the host bus. */
226	do
227	{
228	uDevFnBridge = pBus->aPciDev.devfn;
229	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
230
231	/* Get the parent. */
232	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
233	pPciDevBus = &pBus->aPciDev;
234	} while (pBus->iBus != 0);
235
236	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
237	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel);
238	}
239
240	/**
241	* Port I/O Handler for PCI address OUT operations.
242	*
243	* @returns VBox status code.
244	*
245	* @param pDevIns The device instance.
246	* @param pvUser User argument - ignored.
247	* @param uPort Port number used for the OUT operation.
248	* @param u32 The value to output.
249	* @param cb The value size in bytes.
250	*/
251	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
252	{
253	LogFlow(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
254	NOREF(pvUser);
255	if (cb == 4)
256	{
257	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
258
259	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
260	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
261	PCI_UNLOCK(pDevIns);
262	}
263
264	return VINF_SUCCESS;
265	}
266
267	/**
268	* Port I/O Handler for PCI address IN operations.
269	*
270	* @returns VBox status code.
271	*
272	* @param pDevIns The device instance.
273	* @param pvUser User argument - ignored.
274	* @param uPort Port number used for the IN operation.
275	* @param pu32 Where to store the result.
276	* @param cb Number of bytes read.
277	*/
278	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
279	{
280	NOREF(pvUser);
281	if (cb == 4)
282	{
283	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
284	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
285	*pu32 = pThis->uConfigReg;
286	PCI_UNLOCK(pDevIns);
287	LogFlow(("ich9pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
288	return VINF_SUCCESS;
289	}
290
291	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
292
293	return VERR_IOM_IOPORT_UNUSED;
294	}
295
296	static int ich9pciDataWriteAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pAddr,
297	uint32_t val, int cb, int rcReschedule)
298	{
299	int rc = VINF_SUCCESS;
300
301	if (pAddr->iBus != 0)
302	{
303	if (pGlobals->aPciBus.cBridges)
304	{
305	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
306	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
307	if (pBridgeDevice)
308	{
309	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
310	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc, pAddr->iRegister, val, cb);
311	}
312	else
313	{
314	// do nothing, bridge not found
315	}
316	#else
317	rc = rcReschedule;
318	goto out;
319	#endif
320	}
321	}
322	else
323	{
324	if (pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc])
325	{
326	#ifdef IN_RING3
327	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
328	aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, cb);
329	#else
330	rc = rcReschedule;
331	goto out;
332	#endif
333	}
334	}
335
336	out:
337	Log2(("ich9pciDataWriteAddr: %02x:%02x:%02x reg %x(%d) %x %Rrc\n",
338	pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister,
339	cb, val, rc));
340
341	return rc;
342	}
343
344	static int ich9pciDataWrite(PICH9PCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
345	{
346	PciAddress aPciAddr;
347
348	LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
349
350	if (!(pGlobals->uConfigReg & (1 << 31)))
351	return VINF_SUCCESS;
352
353	if ((pGlobals->uConfigReg & 0x3) != 0)
354	return VINF_SUCCESS;
355
356	/* Compute destination device */
357	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
358
359	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VINF_IOM_HC_IOPORT_WRITE);
360	}
361
362	static void ich9pciNoMem(void* ptr, int cb)
363	{
364	for (int i = 0; i < cb; i++)
365	((uint8_t*)ptr)[i] = 0xff;
366	}
367
368	/**
369	* Port I/O Handler for PCI data OUT operations.
370	*
371	* @returns VBox status code.
372	*
373	* @param pDevIns The device instance.
374	* @param pvUser User argument - ignored.
375	* @param uPort Port number used for the OUT operation.
376	* @param u32 The value to output.
377	* @param cb The value size in bytes.
378	*/
379	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
380	{
381	LogFlow(("ich9pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
382	NOREF(pvUser);
383	int rc = VINF_SUCCESS;
384	if (!(Port % cb))
385	{
386	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
387	rc = ich9pciDataWrite(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), Port, u32, cb);
388	PCI_UNLOCK(pDevIns);
389	}
390	else
391	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
392	return rc;
393	}
394
395	static int ich9pciDataReadAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pPciAddr, int cb,
396	uint32_t *pu32, int rcReschedule)
397	{
398	int rc = VINF_SUCCESS;
399
400	if (pPciAddr->iBus != 0)
401	{
402	if (pGlobals->aPciBus.cBridges)
403	{
404	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
405	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
406	if (pBridgeDevice)
407	{
408	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
409	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
410	}
411	else
412	ich9pciNoMem(pu32, cb);
413	#else
414	rc = rcReschedule;
415	goto out;
416	#endif
417	} else
418	ich9pciNoMem(pu32, cb);
419	}
420	else
421	{
422	if (pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc])
423	{
424	#ifdef IN_RING3
425	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
426	*pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, cb);
427	#else
428	rc = rcReschedule;
429	goto out;
430	#endif
431	}
432	else
433	ich9pciNoMem(pu32, cb);
434	}
435
436	out:
437	Log3(("ich9pciDataReadAddr: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n",
438	pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister,
439	cb, *pu32, rc));
440
441	return rc;
442	}
443
444	static int ich9pciDataRead(PICH9PCIGLOBALS pGlobals, uint32_t addr, int cb, uint32_t *pu32)
445	{
446	PciAddress aPciAddr;
447
448	LogFlow(("ich9pciDataRead: config=%x cb=%d\n", pGlobals->uConfigReg, cb));
449
450	*pu32 = 0xffffffff;
451
452	if (!(pGlobals->uConfigReg & (1 << 31)))
453	return VINF_SUCCESS;
454
455	if ((pGlobals->uConfigReg & 0x3) != 0)
456	return VINF_SUCCESS;
457
458	/* Compute destination device */
459	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
460
461	return ich9pciDataReadAddr(pGlobals, &aPciAddr, cb, pu32, VINF_IOM_HC_IOPORT_READ);
462	}
463
464	/**
465	* Port I/O Handler for PCI data IN operations.
466	*
467	* @returns VBox status code.
468	*
469	* @param pDevIns The device instance.
470	* @param pvUser User argument - ignored.
471	* @param uPort Port number used for the IN operation.
472	* @param pu32 Where to store the result.
473	* @param cb Number of bytes read.
474	*/
475	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
476	{
477	NOREF(pvUser);
478	if (!(Port % cb))
479	{
480	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
481	int rc = ich9pciDataRead(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), Port, cb, pu32);
482	PCI_UNLOCK(pDevIns);
483	LogFlow(("ich9pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
484	return rc;
485	}
486	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
487	return VERR_IOM_IOPORT_UNUSED;
488	}
489
490	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
491	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
492	{
493	return (irq_num + uSlot) & 7;
494	}
495
496	/* return the global irq number corresponding to a given device irq
497	pin. We could also use the bus number to have a more precise
498	mapping. This is the implementation note described in the PCI spec chapter 2.2.6 */
499	DECLINLINE(int) ich9pciSlotGetPirq(uint8_t uBus, uint8_t uDevFn, int iIrqNum)
500	{
501	int iSlotAddend = (uDevFn >> 3) - 1;
502	return (iIrqNum + iSlotAddend) & 3;
503	}
504
505	/* irqs corresponding to PCI irqs A-D, must match pci_irq_list in rombios.c */
506	static const uint8_t aPciIrqs[4] = { 11, 10, 9, 5 };
507
508	/* Add one more level up request on APIC input line */
509	DECLINLINE(void) ich9pciApicLevelUp(PICH9PCIGLOBALS pGlobals, int irq_num)
510	{
511	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
512	}
513
514	/* Remove one level up request on APIC input line */
515	DECLINLINE(void) ich9pciApicLevelDown(PICH9PCIGLOBALS pGlobals, int irq_num)
516	{
517	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
518	}
519
520	static void ich9pciApicSetIrq(PICH9PCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int iForcedIrq)
521	{
522	/* This is only allowed to be called with a pointer to the root bus. */
523	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
524
525	if (iForcedIrq == -1)
526	{
527	int apic_irq, apic_level;
528	PICH9PCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
529	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
530
531	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
532	ich9pciApicLevelUp(pGlobals, irq_num);
533	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
534	ich9pciApicLevelDown(pGlobals, irq_num);
535
536	apic_irq = irq_num + 0x10;
537	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
538	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
539	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
540	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
541
542	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
543	{
544	/*
545	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
546	* PDM_IRQ_LEVEL_HIGH bit set
547	*/
548	ich9pciApicLevelDown(pGlobals, irq_num);
549	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
550	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
551	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
552	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
553	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
554	}
555	} else {
556	Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d\n",
557	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq));
558	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel);
559	}
560	}
561
562	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
563	{
564
565	if (PCIDevIsIntxDisabled(pPciDev))
566	{
567	if (MsiIsEnabled(pPciDev))
568	{
569	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
570	MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel);
571	}
572
573	if (MsixIsEnabled(pPciDev))
574	{
575	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
576	MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel);
577	}
578	return;
579	}
580
581	PICH9PCIBUS pBus = &pGlobals->aPciBus;
582	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
583
584	/* Check if the state changed. */
585	if (pPciDev->Int.s.uIrqPinState != iLevel)
586	{
587	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
588
589	/* Send interrupt to I/O APIC only now. */
590	if (fIsAcpiDevice)
591	/*
592	* ACPI needs special treatment since SCI is hardwired and
593	* should not be affected by PCI IRQ routing tables at the
594	* same time SCI IRQ is shared in PCI sense hence this
595	* kludge (i.e. we fetch the hardwired value from ACPIs
596	* PCI device configuration space).
597	*/
598	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, PCIDevGetInterruptLine(pPciDev));
599	else
600	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);
601	}
602	}
603
604	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
605	{
606	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
607	PciAddress aDest;
608	uint32_t u32 = 0;
609
610	Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
611
612	PCI_LOCK(pDevIns, VINF_IOM_HC_MMIO_WRITE);
613
614	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
615
616	switch (cb)
617	{
618	case 1:
619	u32 = (uint8_t)pv;
620	break;
621	case 2:
622	u32 = (uint16_t)pv;
623	break;
624	case 4:
625	u32 = (uint32_t)pv;
626	break;
627	default:
628	Assert(false);
629	break;
630	}
631	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb, VINF_IOM_HC_MMIO_WRITE);
632	PCI_UNLOCK(pDevIns);
633
634	return rc;
635	}
636
637	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
638	{
639	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
640	PciAddress aDest;
641	uint32_t rv;
642
643	LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
644
645	PCI_LOCK(pDevIns, VINF_IOM_HC_MMIO_READ);
646
647	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
648
649	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv, VINF_IOM_HC_MMIO_READ);
650
651	if (RT_SUCCESS(rc))
652	{
653	switch (cb)
654	{
655	case 1:
656	(uint8_t)pv = (uint8_t)rv;
657	break;
658	case 2:
659	(uint16_t)pv = (uint16_t)rv;
660	break;
661	case 4:
662	(uint32_t)pv = (uint32_t)rv;
663	break;
664	default:
665	Assert(false);
666	break;
667	}
668	}
669	PCI_UNLOCK(pDevIns);
670
671	return rc;
672	}
673
674	#ifdef IN_RING3
675
676	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus)
677	{
678	/* Search for a fitting bridge. */
679	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
680	{
681	/*
682	* Examine secondary and subordinate bus number.
683	* If the target bus is in the range we pass the request on to the bridge.
684	*/
685	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
686	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
687	("Device is not a PCI bridge but on the list of PCI bridges\n"));
688	uint32_t uSecondary = PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS);
689	uint32_t uSubordinate = PCIDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS);
690	Log3(("ich9pciFindBridge on bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, iBus, uSecondary, uSubordinate));
691	if (iBus >= uSecondary && iBus <= uSubordinate)
692	return pBridge;
693	}
694
695	/* Nothing found. */
696	return NULL;
697	}
698
699	static uint32_t ich9pciGetCfg(PCIDevice* aDev, int32_t iRegister, int cb)
700	{
701	return aDev->Int.s.pfnConfigRead(aDev, iRegister, cb);
702	}
703
704	static uint8_t ich9pciGetByte(PCIDevice* aDev, int32_t iRegister)
705	{
706	return (uint8_t)ich9pciGetCfg(aDev, iRegister, 1);
707	}
708
709	static uint16_t ich9pciGetWord(PCIDevice* aDev, int32_t iRegister)
710	{
711	return (uint16_t)ich9pciGetCfg(aDev, iRegister, 2);
712	}
713
714	static uint32_t ich9pciGetDWord(PCIDevice* aDev, int32_t iRegister)
715	{
716	return (uint32_t)ich9pciGetCfg(aDev, iRegister, 4);
717	}
718
719	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
720	{
721	return (iRegion == VBOX_PCI_ROM_SLOT) ?
722	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
723	}
724
725	#define INVALID_PCI_ADDRESS ~0U
726
727	static int ich9pciUnmapRegion(PPCIDEVICE pDev, int iRegion)
728	{
729	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
730	int rc = VINF_SUCCESS;
731	PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
732
733	Assert (pRegion->size != 0);
734
735	if (pRegion->addr != INVALID_PCI_ADDRESS)
736	{
737	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
738	{
739	/* Port IO */
740	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
741	AssertRC(rc);
742	}
743	else
744	{
745	RTGCPHYS GCPhysBase = pRegion->addr;
746	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
747	{
748	/* unmap it. */
749	rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
750	AssertRC(rc);
751	rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
752	}
753	else
754	rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
755	}
756
757	pRegion->addr = INVALID_PCI_ADDRESS;
758	}
759
760	return rc;
761	}
762
763	static void ich9pciUpdateMappings(PCIDevice* pDev)
764	{
765	PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
766	uint64_t uLast, uNew;
767
768	int iCmd = ich9pciGetWord(pDev, VBOX_PCI_COMMAND);
769	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
770	{
771	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
772	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
773	int64_t iRegionSize = pRegion->size;
774	int rc;
775
776	if (iRegionSize == 0)
777	continue;
778
779	bool f64Bit = (pRegion->type & PCI_ADDRESS_SPACE_BAR64) != 0;
780
781	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
782	{
783	/* port IO region */
784	if (iCmd & PCI_COMMAND_IOACCESS)
785	{
786	/* IO access allowed */
787	uNew = ich9pciGetDWord(pDev, uConfigReg);
788	uNew &= ~(iRegionSize - 1);
789	uLast = uNew + iRegionSize - 1;
790	/* only 64K ioports on PC */
791	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
792	uNew = INVALID_PCI_ADDRESS;
793	} else
794	uNew = INVALID_PCI_ADDRESS;
795	}
796	else
797	{
798	/* MMIO region */
799	if (iCmd & PCI_COMMAND_MEMACCESS)
800	{
801	uNew = ich9pciGetDWord(pDev, uConfigReg);
802
803	if (f64Bit)
804	{
805	uNew \|= ((uint64_t)ich9pciGetDWord(pDev, uConfigReg+4)) << 32;
806	if (uNew > UINT64_C(0x0000010000000000))
807	{
808	/* Workaround for REM being unhapping with mapping very lange 64-bit addresses */
809	Log(("Ignoring too 64-bit BAR: %llx\n", uNew));
810	uNew = INVALID_PCI_ADDRESS;
811	}
812	}
813
814	/* the ROM slot has a specific enable bit */
815	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
816	uNew = INVALID_PCI_ADDRESS;
817	else
818	{
819	uNew &= ~(iRegionSize - 1);
820	uLast = uNew + iRegionSize - 1;
821	/* NOTE: we do not support wrapping */
822	/* XXX: as we cannot support really dynamic
823	mappings, we handle specific values as invalid
824	mappings. */
825	if (uLast <= uNew \|\| uNew == 0 \|\| uLast == INVALID_PCI_ADDRESS)
826	uNew = INVALID_PCI_ADDRESS;
827	}
828	} else
829	uNew = INVALID_PCI_ADDRESS;
830	}
831	/* now do the real mapping */
832	if (uNew != pRegion->addr)
833	{
834	if (pRegion->addr != INVALID_PCI_ADDRESS)
835	ich9pciUnmapRegion(pDev, iRegion);
836
837	pRegion->addr = uNew;
838	if (pRegion->addr != INVALID_PCI_ADDRESS)
839	{
840
841	/* finally, map the region */
842	rc = pRegion->map_func(pDev, iRegion,
843	pRegion->addr, pRegion->size,
844	(PCIADDRESSSPACE)(pRegion->type));
845	AssertRC(rc);
846	}
847	}
848	}
849	}
850
851	static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
852	{
853	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
854
855	/*
856	* Check input.
857	*/
858	if ( !pszName
859	\|\| !pPciDev
860	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices)
861	)
862	{
863	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
864	return VERR_INVALID_PARAMETER;
865	}
866
867	/*
868	* Register the device.
869	*/
870	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
871	}
872
873
874	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
875	{
876	int rc;
877
878	rc = MsiInit(pPciDev, pMsiReg);
879	if (RT_FAILURE(rc))
880	return rc;
881
882	rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
883	if (RT_FAILURE(rc))
884	return rc;
885
886	return VINF_SUCCESS;
887	}
888
889
890	static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
891	{
892
893	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
894
895	/*
896	* Check input.
897	*/
898	if ( !pszName
899	\|\| !pPciDev
900	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices))
901	{
902	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
903	return VERR_INVALID_PARAMETER;
904	}
905
906	/*
907	* Register the device.
908	*/
909	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
910	}
911
912	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
913	{
914	/*
915	* Validate.
916	*/
917	AssertMsgReturn( enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR32)
918	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR32)
919	\|\| enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR64)
920	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR64)
921	\|\| enmType == PCI_ADDRESS_SPACE_IO
922	,
923	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
924	VERR_INVALID_PARAMETER);
925	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
926	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
927	VERR_INVALID_PARAMETER);
928	int iLastSet = ASMBitLastSetU32(cbRegion);
929	AssertMsgReturn( iLastSet != 0
930	&& RT_BIT_32(iLastSet - 1) == cbRegion,
931	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
932	VERR_INVALID_PARAMETER);
933
934	Log(("ich9pciIORegionRegister: %s region %d size %d type %x\n",
935	pPciDev->name, iRegion, cbRegion, enmType));
936
937	/* Make sure that we haven't marked this region as continuation of 64-bit region. */
938	Assert(pPciDev->Int.s.aIORegions[iRegion].type != 0xff);
939
940	/*
941	* Register the I/O region.
942	*/
943	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
944	pRegion->addr = INVALID_PCI_ADDRESS;
945	pRegion->size = cbRegion;
946	pRegion->type = enmType;
947	pRegion->map_func = pfnCallback;
948
949	if ((enmType & PCI_ADDRESS_SPACE_BAR64) != 0)
950	{
951	AssertMsgReturn(iRegion < 4,
952	("Region %d cannot be 64-bit\n", iRegion),
953	VERR_INVALID_PARAMETER);
954	/* Mark next region as continuation of this one. */
955	pPciDev->Int.s.aIORegions[iRegion+1].type = 0xff;
956	}
957
958	/* Set type in the PCI config space. */
959	uint32_t u32Value = ((uint32_t)enmType) & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH);
960	PCIDevSetDWord(pPciDev, ich9pciGetRegionReg(iRegion), u32Value);
961
962	return VINF_SUCCESS;
963	}
964
965	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
966	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
967	{
968	if (ppfnReadOld)
969	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
970	pPciDev->Int.s.pfnConfigRead = pfnRead;
971
972	if (ppfnWriteOld)
973	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
974	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
975	}
976
977	/**
978	* Saves a state of the PCI device.
979	*
980	* @returns VBox status code.
981	* @param pDevIns Device instance of the PCI Bus.
982	* @param pPciDev Pointer to PCI device.
983	* @param pSSM The handle to save the state to.
984	*/
985	static DECLCALLBACK(int) ich9pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
986	{
987	Assert(!pciDevIsPassthrough(pPciDev));
988	return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
989	}
990
991	static int ich9pciR3CommonSaveExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM)
992	{
993	/*
994	* Iterate thru all the devices.
995	*/
996	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
997	{
998	PPCIDEVICE pDev = pBus->apDevices[i];
999	if (pDev)
1000	{
1001	/* Device position */
1002	SSMR3PutU32(pSSM, i);
1003	/* PCI config registers */
1004	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1005
1006	/* Device flags */
1007	int rc = SSMR3PutU32(pSSM, pDev->Int.s.fFlags);
1008	if (RT_FAILURE(rc))
1009	return rc;
1010
1011	/* IRQ pin state */
1012	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1013	if (RT_FAILURE(rc))
1014	return rc;
1015
1016	/* MSI info */
1017	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
1018	if (RT_FAILURE(rc))
1019	return rc;
1020	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
1021	if (RT_FAILURE(rc))
1022	return rc;
1023
1024	/* MSI-X info */
1025	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
1026	if (RT_FAILURE(rc))
1027	return rc;
1028	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
1029	if (RT_FAILURE(rc))
1030	return rc;
1031	/* Save MSI-X page state */
1032	if (pDev->Int.s.u8MsixCapOffset != 0)
1033	{
1034	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1035	SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
1036	if (RT_FAILURE(rc))
1037	return rc;
1038	}
1039	}
1040	}
1041	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1042	}
1043
1044	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1045	{
1046	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1047
1048	/*
1049	* Bus state data.
1050	*/
1051	SSMR3PutU32(pSSM, pThis->uConfigReg);
1052
1053	/*
1054	* Save IRQ states.
1055	*/
1056	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1057	SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
1058
1059	SSMR3PutU32(pSSM, ~0); /* separator */
1060
1061	return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
1062	}
1063
1064
1065	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1066	{
1067	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1068	return ich9pciR3CommonSaveExec(pThis, pSSM);
1069	}
1070
1071
1072	static void ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1073	{
1074	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1075
1076	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1077
1078	/* If the current bus is not the target bus search for the bus which contains the device. */
1079	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1080	{
1081	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1082	if (pBridgeDevice)
1083	{
1084	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1085	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
1086	}
1087	}
1088	else
1089	{
1090	/* This is the target bus, pass the write to the device. */
1091	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1092	if (pPciDev)
1093	{
1094	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1095	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
1096	}
1097	}
1098	}
1099
1100	static uint32_t ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1101	{
1102	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1103	uint32_t u32Value;
1104
1105	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1106
1107	/* If the current bus is not the target bus search for the bus which contains the device. */
1108	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1109	{
1110	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1111	if (pBridgeDevice)
1112	{
1113	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1114	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
1115	}
1116	else
1117	ich9pciNoMem(&u32Value, 4);
1118	}
1119	else
1120	{
1121	/* This is the target bus, pass the read to the device. */
1122	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1123	if (pPciDev)
1124	{
1125	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
1126	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1127	}
1128	else
1129	ich9pciNoMem(&u32Value, 4);
1130	}
1131
1132	return u32Value;
1133	}
1134
1135
1136	/**
1137	* Common routine for restoring the config registers of a PCI device.
1138	*
1139	* @param pDev The PCI device.
1140	* @param pbSrcConfig The configuration register values to be loaded.
1141	* @param fIsBridge Whether this is a bridge device or not.
1142	*/
1143	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1144	{
1145	/*
1146	* This table defines the fields for normal devices and bridge devices, and
1147	* the order in which they need to be restored.
1148	*/
1149	static const struct PciField
1150	{
1151	uint8_t off;
1152	uint8_t cb;
1153	uint8_t fWritable;
1154	uint8_t fBridge;
1155	const char *pszName;
1156	} s_aFields[] =
1157	{
1158	/* off,cb,fW,fB, pszName */
1159	{ VBOX_PCI_VENDOR_ID, 2, 0, 3, "VENDOR_ID" },
1160	{ VBOX_PCI_DEVICE_ID, 2, 0, 3, "DEVICE_ID" },
1161	{ VBOX_PCI_STATUS, 2, 1, 3, "STATUS" },
1162	{ VBOX_PCI_REVISION_ID, 1, 0, 3, "REVISION_ID" },
1163	{ VBOX_PCI_CLASS_PROG, 1, 0, 3, "CLASS_PROG" },
1164	{ VBOX_PCI_CLASS_SUB, 1, 0, 3, "CLASS_SUB" },
1165	{ VBOX_PCI_CLASS_BASE, 1, 0, 3, "CLASS_BASE" },
1166	{ VBOX_PCI_CACHE_LINE_SIZE, 1, 1, 3, "CACHE_LINE_SIZE" },
1167	{ VBOX_PCI_LATENCY_TIMER, 1, 1, 3, "LATENCY_TIMER" },
1168	{ VBOX_PCI_HEADER_TYPE, 1, 0, 3, "HEADER_TYPE" },
1169	{ VBOX_PCI_BIST, 1, 1, 3, "BIST" },
1170	{ VBOX_PCI_BASE_ADDRESS_0, 4, 1, 3, "BASE_ADDRESS_0" },
1171	{ VBOX_PCI_BASE_ADDRESS_1, 4, 1, 3, "BASE_ADDRESS_1" },
1172	{ VBOX_PCI_BASE_ADDRESS_2, 4, 1, 1, "BASE_ADDRESS_2" },
1173	{ VBOX_PCI_PRIMARY_BUS, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1174	{ VBOX_PCI_SECONDARY_BUS, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1175	{ VBOX_PCI_SUBORDINATE_BUS, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1176	{ VBOX_PCI_SEC_LATENCY_TIMER, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1177	{ VBOX_PCI_BASE_ADDRESS_3, 4, 1, 1, "BASE_ADDRESS_3" },
1178	{ VBOX_PCI_IO_BASE, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1179	{ VBOX_PCI_IO_LIMIT, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1180	{ VBOX_PCI_SEC_STATUS, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1181	{ VBOX_PCI_BASE_ADDRESS_4, 4, 1, 1, "BASE_ADDRESS_4" },
1182	{ VBOX_PCI_MEMORY_BASE, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1183	{ VBOX_PCI_MEMORY_LIMIT, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1184	{ VBOX_PCI_BASE_ADDRESS_5, 4, 1, 1, "BASE_ADDRESS_5" },
1185	{ VBOX_PCI_PREF_MEMORY_BASE, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1186	{ VBOX_PCI_PREF_MEMORY_LIMIT, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1187	{ VBOX_PCI_CARDBUS_CIS, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1188	{ VBOX_PCI_PREF_BASE_UPPER32, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1189	{ VBOX_PCI_SUBSYSTEM_VENDOR_ID, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1190	{ VBOX_PCI_PREF_LIMIT_UPPER32, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1191	{ VBOX_PCI_SUBSYSTEM_ID, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1192	{ VBOX_PCI_ROM_ADDRESS, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1193	{ VBOX_PCI_IO_BASE_UPPER16, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1194	{ VBOX_PCI_IO_LIMIT_UPPER16, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1195	{ VBOX_PCI_CAPABILITY_LIST, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1196	{ VBOX_PCI_RESERVED_38, 4, 1, 1, "RESERVED_38" }, // ???
1197	{ VBOX_PCI_ROM_ADDRESS_BR, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1198	{ VBOX_PCI_INTERRUPT_LINE, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1199	{ VBOX_PCI_INTERRUPT_PIN, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1200	{ VBOX_PCI_MIN_GNT, 1, 0, 1, "MIN_GNT" },
1201	{ VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1202	{ VBOX_PCI_MAX_LAT, 1, 0, 1, "MAX_LAT" },
1203	/* The COMMAND register must come last as it requires the ADDRESS
1204	registers to be restored before we pretent to change it from 0 to
1205	whatever value the guest assigned it. */
1206	{ VBOX_PCI_COMMAND, 2, 1, 3, "COMMAND" },
1207	};
1208
1209	#ifdef RT_STRICT
1210	/* Check that we've got full register coverage. */
1211	uint32_t bmDevice[0x40 / 32];
1212	uint32_t bmBridge[0x40 / 32];
1213	RT_ZERO(bmDevice);
1214	RT_ZERO(bmBridge);
1215	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1216	{
1217	uint8_t off = s_aFields[i].off;
1218	uint8_t cb = s_aFields[i].cb;
1219	uint8_t f = s_aFields[i].fBridge;
1220	while (cb-- > 0)
1221	{
1222	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1223	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1224	if (f & 1) ASMBitSet(bmDevice, off);
1225	if (f & 2) ASMBitSet(bmBridge, off);
1226	off++;
1227	}
1228	}
1229	for (uint32_t off = 0; off < 0x40; off++)
1230	{
1231	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1232	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1233	}
1234	#endif
1235
1236	/*
1237	* Loop thru the fields covering the 64 bytes of standard registers.
1238	*/
1239	uint8_t const fBridge = fIsBridge ? 2 : 1;
1240	Assert(!pciDevIsPassthrough(pDev));
1241	uint8_t *pbDstConfig = &pDev->config[0];
1242
1243	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1244	if (s_aFields[i].fBridge & fBridge)
1245	{
1246	uint8_t const off = s_aFields[i].off;
1247	uint8_t const cb = s_aFields[i].cb;
1248	uint32_t u32Src;
1249	uint32_t u32Dst;
1250	switch (cb)
1251	{
1252	case 1:
1253	u32Src = pbSrcConfig[off];
1254	u32Dst = pbDstConfig[off];
1255	break;
1256	case 2:
1257	u32Src = (uint16_t const )&pbSrcConfig[off];
1258	u32Dst = (uint16_t const )&pbDstConfig[off];
1259	break;
1260	case 4:
1261	u32Src = (uint32_t const )&pbSrcConfig[off];
1262	u32Dst = (uint32_t const )&pbDstConfig[off];
1263	break;
1264	default:
1265	AssertFailed();
1266	continue;
1267	}
1268
1269	if ( u32Src != u32Dst
1270	\|\| off == VBOX_PCI_COMMAND)
1271	{
1272	if (u32Src != u32Dst)
1273	{
1274	if (!s_aFields[i].fWritable)
1275	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1276	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1277	else
1278	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1279	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1280	}
1281	if (off == VBOX_PCI_COMMAND)
1282	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1283	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1284	}
1285	}
1286
1287	/*
1288	* The device dependent registers.
1289	*
1290	* We will not use ConfigWrite here as we have no clue about the size
1291	* of the registers, so the device is responsible for correctly
1292	* restoring functionality governed by these registers.
1293	*/
1294	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1295	if (pbDstConfig[off] != pbSrcConfig[off])
1296	{
1297	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1298	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1299	pbDstConfig[off] = pbSrcConfig[off];
1300	}
1301	}
1302
1303	/**
1304	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1305	*
1306	* @returns VBox status code.
1307	* @param pBus The bus which data is being loaded.
1308	* @param pSSM The saved state handle.
1309	* @param uVersion The data version.
1310	* @param uPass The pass.
1311	*/
1312	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1313	{
1314	uint32_t u32;
1315	uint32_t i;
1316	int rc;
1317
1318	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1319
1320	/*
1321	* Iterate thru all the devices and write 0 to the COMMAND register so
1322	* that all the memory is unmapped before we start restoring the saved
1323	* mapping locations.
1324	*
1325	* The register value is restored afterwards so we can do proper
1326	* LogRels in pciR3CommonRestoreConfig.
1327	*/
1328	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1329	{
1330	PPCIDEVICE pDev = pBus->apDevices[i];
1331	if (pDev)
1332	{
1333	uint16_t u16 = PCIDevGetCommand(pDev);
1334	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1335	PCIDevSetCommand(pDev, u16);
1336	Assert(PCIDevGetCommand(pDev) == u16);
1337	}
1338	}
1339
1340	void* pvMsixPage = RTMemTmpAllocZ(0x1000);
1341	/*
1342	* Iterate all the devices.
1343	*/
1344	for (i = 0;; i++)
1345	{
1346	PPCIDEVICE pDev;
1347	PCIDEVICE DevTmp;
1348
1349	/* index / terminator */
1350	rc = SSMR3GetU32(pSSM, &u32);
1351	if (RT_FAILURE(rc))
1352	return rc;
1353	if (u32 == (uint32_t)~0)
1354	break;
1355	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1356	\|\| u32 < i)
1357	{
1358	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1359	goto out;
1360	}
1361
1362	/* skip forward to the device checking that no new devices are present. */
1363	for (; i < u32; i++)
1364	{
1365	pDev = pBus->apDevices[i];
1366	if (pDev)
1367	{
1368	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1369	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1370	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1371	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1372	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1373	}
1374	}
1375
1376	/* get the data */
1377	DevTmp.Int.s.fFlags = 0;
1378	DevTmp.Int.s.u8MsiCapOffset = 0;
1379	DevTmp.Int.s.u8MsiCapSize = 0;
1380	DevTmp.Int.s.u8MsixCapOffset = 0;
1381	DevTmp.Int.s.u8MsixCapSize = 0;
1382	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1383	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1384
1385	rc = SSMR3GetU32(pSSM, &DevTmp.Int.s.fFlags);
1386	if (RT_FAILURE(rc))
1387	goto out;
1388
1389	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1390	if (RT_FAILURE(rc))
1391	goto out;
1392
1393	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1394	if (RT_FAILURE(rc))
1395	goto out;
1396
1397	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1398	if (RT_FAILURE(rc))
1399	goto out;
1400
1401	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1402	if (RT_FAILURE(rc))
1403	goto out;
1404
1405	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1406	if (RT_FAILURE(rc))
1407	goto out;
1408
1409	/* Load MSI-X page state */
1410	if (DevTmp.Int.s.u8MsixCapOffset != 0)
1411	{
1412	Assert(pvMsixPage != NULL);
1413	SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1414	if (RT_FAILURE(rc))
1415	goto out;
1416	}
1417
1418	/* check that it's still around. */
1419	pDev = pBus->apDevices[i];
1420	if (!pDev)
1421	{
1422	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1423	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1424	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1425	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1426	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1427	continue;
1428	}
1429
1430	/* match the vendor id assuming that this will never be changed. */
1431	if ( PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1432	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1433	i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1434
1435	/* commit the loaded device config. */
1436	Assert(!pciDevIsPassthrough(pDev));
1437	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1438
1439	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1440	pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1441	pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1442	pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1443	pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1444	if (DevTmp.Int.s.u8MsixCapSize != 0)
1445	{
1446	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1447	memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1448	}
1449	}
1450
1451	out:
1452	if (pvMsixPage)
1453	RTMemTmpFree(pvMsixPage);
1454
1455	return rc;
1456	}
1457
1458	/**
1459	* Loads a saved PCI device state.
1460	*
1461	* @returns VBox status code.
1462	* @param pDevIns Device instance of the PCI Bus.
1463	* @param pPciDev Pointer to PCI device.
1464	* @param pSSM The handle to the saved state.
1465	*/
1466	static DECLCALLBACK(int) ich9pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1467	{
1468	Assert(!pciDevIsPassthrough(pPciDev));
1469	return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1470	}
1471
1472	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1473	{
1474	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1475	PICH9PCIBUS pBus = &pThis->aPciBus;
1476	uint32_t u32;
1477	int rc;
1478
1479	/* We ignore this version as there's no saved state with it anyway */
1480	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1481	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1482	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1483	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1484
1485	/*
1486	* Bus state data.
1487	*/
1488	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1489
1490	/*
1491	* Load IRQ states.
1492	*/
1493	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1494	SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1495
1496	/* separator */
1497	rc = SSMR3GetU32(pSSM, &u32);
1498	if (RT_FAILURE(rc))
1499	return rc;
1500	if (u32 != (uint32_t)~0)
1501	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1502
1503	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1504	}
1505
1506	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1507	{
1508	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1509	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1510	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1511	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1512	}
1513
1514	static uint32_t ich9pciConfigRead(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1515	{
1516	/* Will only work in LSB case */
1517	uint32_t u32Val;
1518	PciAddress aPciAddr;
1519
1520	aPciAddr.iBus = uBus;
1521	aPciAddr.iDeviceFunc = uDevFn;
1522	aPciAddr.iRegister = addr;
1523
1524	/* cannot be rescheduled, as already in R3 */
1525	int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR);
1526	AssertRC(rc);
1527	return u32Val;
1528	}
1529
1530	static void ich9pciConfigWrite(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1531	{
1532	PciAddress aPciAddr;
1533
1534	aPciAddr.iBus = uBus;
1535	aPciAddr.iDeviceFunc = uDevFn;
1536	aPciAddr.iRegister = addr;
1537
1538	/* cannot be rescheduled, as already in R3 */
1539	int rc = ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VERR_INTERNAL_ERROR);
1540	AssertRC(rc);
1541	}
1542
1543	static void ich9pciSetRegionAddress(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
1544	{
1545	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1546
1547	/* Read memory type first. */
1548	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1549	/* Read command register. */
1550	uint16_t uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1551
1552	Log(("Set region address: %02x:%02x.%d region %d address=%lld\n",
1553	uBus, uDevFn>>3, uDevFn&7, addr));
1554
1555	if ( iRegion == PCI_ROM_SLOT )
1556	uCmd \|= PCI_COMMAND_MEMACCESS;
1557	else if ((uResourceType & PCI_ADDRESS_SPACE_IO) == PCI_ADDRESS_SPACE_IO)
1558	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1559	else /* The region is MMIO. */
1560	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1561
1562	bool f64Bit = (uResourceType & PCI_ADDRESS_SPACE_BAR64) != 0;
1563
1564	/* Write address of the device. */
1565	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, (uint32_t)addr, 4);
1566	if (f64Bit)
1567	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg + 4, (uint32_t)(addr >> 32), 4);
1568
1569	/* enable memory mappings */
1570	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1571	}
1572
1573
1574	static void ich9pciBiosInitBridge(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1575	{
1576	Log(("BIOS init bridge: %02x::%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1577
1578	/*
1579	* The I/O range for the bridge must be aligned to a 4KB boundary.
1580	* This does not change anything really as the access to the device is not going
1581	* through the bridge but we want to be compliant to the spec.
1582	*/
1583	if ((pGlobals->uPciBiosIo % 4096) != 0)
1584	{
1585	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1586	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1587	}
1588	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1589
1590	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1591	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1592	{
1593	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1594	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1595	}
1596	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1597
1598	/* Save values to compare later to. */
1599	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1600	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1601	uint8_t uBridgeBus = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, 1);
1602
1603	/* Init devices behind the bridge and possibly other bridges as well. */
1604	for (int iDev = 0; iDev <= 255; iDev++)
1605	ich9pciBiosInitDevice(pGlobals, uBridgeBus, iDev);
1606
1607	/*
1608	* Set I/O limit register. If there is no device with I/O space behind the bridge
1609	* we set a lower value than in the base register.
1610	* The result with a real bridge is that no I/O transactions are passed to the secondary
1611	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1612	*/
1613	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1614	{
1615	/* The upper boundary must be one byte less than a 4KB boundary. */
1616	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1617	}
1618
1619	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1620
1621	/* Same with the MMIO limit register but with 1MB boundary here. */
1622	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1623	{
1624	/* The upper boundary must be one byte less than a 1MB boundary. */
1625	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1626	}
1627	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1628
1629	/*
1630	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1631	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1632	* the base register than in the limit register.
1633	*/
1634	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1635	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1636	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1637	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1638	}
1639
1640	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1641	{
1642	uint16_t uDevClass, uVendor, uDevice;
1643	uint8_t uCmd;
1644
1645	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1646	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1647	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1648
1649	/* If device is present */
1650	if (uVendor == 0xffff)
1651	return;
1652
1653	Log(("BIOS init device: %02x:%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1654
1655	switch (uDevClass)
1656	{
1657	case 0x0101:
1658	/* IDE controller */
1659	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1660	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1661	goto default_map;
1662	break;
1663	case 0x0300:
1664	/* VGA controller */
1665	if (uVendor != 0x80ee)
1666	goto default_map;
1667	/* VGA: map frame buffer to default Bochs VBE address */
1668	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0xE0000000);
1669	/*
1670	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1671	* only the framebuffer (i.e., a memory region) is explicitly registered via
1672	* ich9pciSetRegionAddress, so I/O decoding must be enabled manually.
1673	*/
1674	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1675	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1676	/* Enable I/O space access. */
1677	uCmd \| PCI_COMMAND_IOACCESS,
1678	1);
1679	break;
1680	case 0x0604:
1681	/* PCI-to-PCI bridge. */
1682	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1683	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn);
1684	break;
1685	default:
1686	default_map:
1687	{
1688	/* default memory mappings */
1689	/*
1690	* We ignore ROM region here.
1691	*/
1692	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1693	{
1694	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1695
1696	/* Calculate size - we write all 1s into the BAR, and then evaluate which bits
1697	are cleared. . */
1698	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1699
1700	bool f64bit = (u8ResourceType & PCI_ADDRESS_SPACE_BAR64) != 0;
1701	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1702	uint64_t cbRegSize64 = 0;
1703
1704	if (f64bit)
1705	{
1706	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1707	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0xffffffff), 4);
1708	cbRegSize64 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1709	cbRegSize64 \|= ((uint64_t)ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address+4, 4) << 32);
1710	cbRegSize64 &= ~UINT64_C(0x0f);
1711	cbRegSize64 = (~cbRegSize64) + 1;
1712
1713	/* No 64-bit PIO regions possible. */
1714	Assert((u8ResourceType & PCI_COMMAND_IOACCESS) == 0);
1715	}
1716	else
1717	{
1718	uint32_t cbRegSize32;
1719	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1720	cbRegSize32 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1721
1722	/* Clear resource information depending on resource type. */
1723	if (fIsPio) /* PIO */
1724	cbRegSize32 &= ~UINT32_C(0x01);
1725	else /* MMIO */
1726	cbRegSize32 &= ~UINT32_C(0x0f);
1727
1728	/*
1729	* Invert all bits and add 1 to get size of the region.
1730	* (From PCI implementation note)
1731	*/
1732	if (fIsPio && (cbRegSize32 & UINT32_C(0xffff0000)) == 0)
1733	cbRegSize32 = (~(cbRegSize32 \| UINT32_C(0xffff0000))) + 1;
1734	else
1735	cbRegSize32 = (~cbRegSize32) + 1;
1736
1737	cbRegSize64 = cbRegSize32;
1738	}
1739	Assert(cbRegSize64 == (uint32_t)cbRegSize64);
1740	Log2(("%s: Size of region %u for device %d on bus %d is %lld\n", __FUNCTION__, iRegion, uDevFn, uBus, cbRegSize64));
1741
1742	if (cbRegSize64)
1743	{
1744	uint32_t cbRegSize32 = (uint32_t)cbRegSize64;
1745	uint32_t* paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1746	paddr = (paddr + cbRegSize32 - 1) & ~(cbRegSize32 - 1);
1747	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, *paddr));
1748	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, *paddr);
1749	*paddr += cbRegSize32;
1750	Log2(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1751
1752	if (f64bit)
1753	iRegion++; /* skip next region */
1754	}
1755	}
1756	break;
1757	}
1758	}
1759
1760	/* map the interrupt */
1761	uint32_t iPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1762	if (iPin != 0)
1763	{
1764	iPin--;
1765
1766	if (uBus != 0)
1767	{
1768	/* Find bus this device attached to. */
1769	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1770	while (1)
1771	{
1772	PPCIDEVICE pBridge = ich9pciFindBridge(pBus, uBus);
1773	if (!pBridge)
1774	{
1775	Assert(false);
1776	break;
1777	}
1778	if (uBus == PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS))
1779	{
1780	/* OK, found bus this device attached to. */
1781	break;
1782	}
1783	pBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1784	}
1785
1786	/* We need to go up to the host bus to see which irq pin this
1787	* device will use there. See logic in ich9pcibridgeSetIrq().
1788	*/
1789	while (pBus->iBus != 0)
1790	{
1791	/* Get the pin the device would assert on the bridge. */
1792	iPin = ((pBus->aPciDev.devfn >> 3) + iPin) & 3;
1793	pBus = pBus->aPciDev.Int.s.pBusR3;
1794	};
1795	}
1796
1797	int iIrq = aPciIrqs[ich9pciSlotGetPirq(uBus, uDevFn, iPin)];
1798	Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
1799	iPin, iIrq, uBus, uDevFn>>3, uDevFn&7));
1800	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
1801	}
1802	}
1803
1804	/* Initializes bridges registers used for routing. */
1805	static void ich9pciInitBridgeTopology(PICH9PCIGLOBALS pGlobals, PICH9PCIBUS pBus)
1806	{
1807	PPCIDEVICE pBridgeDev = &pBus->aPciDev;
1808
1809	/* Set only if we are not on the root bus, it has no primary bus attached. */
1810	if (pGlobals->uBus != 0)
1811	{
1812	PCIDevSetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, pGlobals->uBus);
1813	PCIDevSetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
1814	}
1815
1816	pGlobals->uBus++;
1817	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1818	{
1819	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
1820	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
1821	("Device is not a PCI bridge but on the list of PCI bridges\n"));
1822	PICH9PCIBUS pChildBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1823	ich9pciInitBridgeTopology(pGlobals, pChildBus);
1824	}
1825	PCIDevSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1826	Log2(("ich9pciInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
1827	pBus,
1828	PCIDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
1829	PCIDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
1830	PCIDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS)
1831	));
1832	}
1833
1834
1835	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1836	{
1837	unsigned i;
1838	uint8_t elcr[2] = {0, 0};
1839	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1840	PVM pVM = PDMDevHlpGetVM(pDevIns);
1841	Assert(pVM);
1842
1843	/*
1844	* Set the start addresses.
1845	*/
1846	pGlobals->uPciBiosIo = 0xd000;
1847	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
1848	pGlobals->uBus = 0;
1849
1850	/*
1851	* Assign bridge topology, for further routing to work.
1852	*/
1853	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1854	ich9pciInitBridgeTopology(pGlobals, pBus);
1855
1856	/*
1857	* Init the devices.
1858	*/
1859	for (i = 0; i < 256; i++)
1860	{
1861	ich9pciBiosInitDevice(pGlobals, 0, i);
1862	}
1863
1864	return VINF_SUCCESS;
1865	}
1866
1867	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len)
1868	{
1869	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1870	{
1871	LogRel(("Read from extended register %d fallen back to generic code\n",
1872	u32Address));
1873	return 0;
1874	}
1875
1876	AssertMsgReturn(u32Address + len <= 256, ("Read after the end of PCI config space\n"),
1877	0);
1878	if ( pciDevIsMsiCapable(aDev)
1879	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1880	&& (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1881	)
1882	{
1883	return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1884	}
1885
1886	if ( pciDevIsMsixCapable(aDev)
1887	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
1888	&& (u32Address < aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize)
1889	)
1890	{
1891	return MsixPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1892	}
1893
1894	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
1895	0);
1896	switch (len)
1897	{
1898	case 1:
1899	return PCIDevGetByte(aDev, u32Address);
1900	case 2:
1901	return PCIDevGetWord(aDev, u32Address);
1902	case 4:
1903	return PCIDevGetDWord(aDev, u32Address);
1904	default:
1905	Assert(false);
1906	return 0;
1907	}
1908	}
1909
1910	DECLINLINE(void) ich9pciWriteBarByte(PCIDevice *aDev, int iRegion, int iOffset, uint8_t u8Val)
1911	{
1912	PCIIORegion * pRegion = &aDev->Int.s.aIORegions[iRegion];
1913	int64_t iRegionSize = pRegion->size;
1914
1915	Log3(("ich9pciWriteBarByte: region=%d off=%d val=%x size=%d\n",
1916	iRegion, iOffset, u8Val, iRegionSize));
1917
1918	if (iOffset > 3)
1919	Assert((aDev->Int.s.aIORegions[iRegion].type & PCI_ADDRESS_SPACE_BAR64) != 0);
1920
1921	/* Check if we're writing to upper part of 64-bit BAR. */
1922	if (aDev->Int.s.aIORegions[iRegion].type == 0xff)
1923	{
1924	ich9pciWriteBarByte(aDev, iRegion-1, iOffset+4, u8Val);
1925	return;
1926	}
1927
1928	/* Region doesn't exist */
1929	if (iRegionSize == 0)
1930	return;
1931
1932	uint32_t uAddr = ich9pciGetRegionReg(iRegion) + iOffset;
1933	/* Region size must be power of two */
1934	Assert((iRegionSize & (iRegionSize - 1)) == 0);
1935	uint8_t uMask = ((iRegionSize - 1) >> (iOffset*8) ) & 0xff;
1936
1937	if (iOffset == 0)
1938	{
1939	uMask \|= (pRegion->type & PCI_ADDRESS_SPACE_IO) ?
1940	(1 << 2) - 1 /* 2 lowest bits for IO region */ :
1941	(1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
1942
1943	}
1944
1945	uint8_t u8Old = PCIDevGetByte(aDev, uAddr) & uMask;
1946	u8Val = (u8Old & uMask) \| (u8Val & ~uMask);
1947
1948	Log3(("ich9pciWriteBarByte: was %x writing %x\n", u8Old, u8Val));
1949
1950	PCIDevSetByte(aDev, uAddr, u8Val);
1951	}
1952
1953	/**
1954	* See paragraph 7.5 of PCI Express specification (p. 349) for definition of
1955	* registers and their writability policy.
1956	*/
1957	static DECLCALLBACK(void) ich9pciConfigWriteDev(PCIDevice *aDev, uint32_t u32Address,
1958	uint32_t val, unsigned len)
1959	{
1960	Assert(len <= 4);
1961
1962	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1963	{
1964	LogRel(("Write to extended register %d fallen back to generic code\n",
1965	u32Address));
1966	return;
1967	}
1968
1969	AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
1970
1971	if ( pciDevIsMsiCapable(aDev)
1972	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1973	&& (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1974	)
1975	{
1976	MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1977	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1978	aDev, u32Address, val, len);
1979	return;
1980	}
1981
1982	if ( pciDevIsMsixCapable(aDev)
1983	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
1984	&& (u32Address < aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize)
1985	)
1986	{
1987	MsixPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1988	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1989	aDev, u32Address, val, len);
1990	return;
1991	}
1992
1993	uint32_t addr = u32Address;
1994	bool fUpdateMappings = false;
1995	bool fP2PBridge = false;
1996	bool fPassthrough = pciDevIsPassthrough(aDev);
1997	uint8_t u8HeaderType = ich9pciGetByte(aDev, VBOX_PCI_HEADER_TYPE);
1998
1999	for (uint32_t i = 0; i < len; i++)
2000	{
2001	bool fWritable = false;
2002	bool fRom = false;
2003	switch (u8HeaderType)
2004	{
2005	case 0x00: /* normal device */
2006	case 0x80: /* multi-function device */
2007	switch (addr)
2008	{
2009	/* Read-only registers */
2010	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2011	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2012	case VBOX_PCI_REVISION_ID:
2013	case VBOX_PCI_CLASS_PROG:
2014	case VBOX_PCI_CLASS_SUB:
2015	case VBOX_PCI_CLASS_BASE:
2016	case VBOX_PCI_HEADER_TYPE:
2017	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
2018	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
2019	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
2020	case VBOX_PCI_CAPABILITY_LIST:
2021	case VBOX_PCI_INTERRUPT_PIN:
2022	fWritable = false;
2023	break;
2024	/* Others can be written */
2025	default:
2026	fWritable = true;
2027	break;
2028	}
2029	break;
2030	case 0x01: /* PCI-PCI bridge */
2031	fP2PBridge = true;
2032	switch (addr)
2033	{
2034	/* Read-only registers */
2035	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2036	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2037	case VBOX_PCI_REVISION_ID:
2038	case VBOX_PCI_CLASS_PROG:
2039	case VBOX_PCI_CLASS_SUB:
2040	case VBOX_PCI_CLASS_BASE:
2041	case VBOX_PCI_HEADER_TYPE:
2042	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
2043	case VBOX_PCI_INTERRUPT_PIN:
2044	fWritable = false;
2045	break;
2046	default:
2047	fWritable = true;
2048	break;
2049	}
2050	break;
2051	default:
2052	AssertMsgFailed(("Unknown header type %x\n", PCIDevGetHeaderType(aDev)));
2053	fWritable = false;
2054	break;
2055	}
2056
2057	uint8_t u8Val = (uint8_t)val;
2058	switch (addr)
2059	{
2060	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
2061	fUpdateMappings = true;
2062	goto default_case;
2063	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
2064	/* don't change reserved bits (11-15) */
2065	u8Val &= UINT32_C(~0xf8);
2066	fUpdateMappings = true;
2067	goto default_case;
2068	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
2069	/* don't change read-only bits => actually all lower bits are read-only */
2070	u8Val &= UINT32_C(~0xff);
2071	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
2072	aDev->config[addr] &= ~u8Val;
2073	break;
2074	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
2075	/* don't change read-only bits */
2076	u8Val &= UINT32_C(~0x06);
2077	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
2078	aDev->config[addr] &= ~u8Val;
2079	break;
2080	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3:
2081	fRom = true;
2082	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
2083	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
2084	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
2085	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
2086	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
2087	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
2088	{
2089	/* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
2090	if (fP2PBridge)
2091	goto default_case;
2092	else
2093	{
2094	int iRegion = fRom ? VBOX_PCI_ROM_SLOT : (addr - VBOX_PCI_BASE_ADDRESS_0) >> 2;
2095	int iOffset = addr & 0x3;
2096	ich9pciWriteBarByte(aDev, iRegion, iOffset, u8Val);
2097	fUpdateMappings = true;
2098	}
2099	break;
2100	}
2101	default:
2102	default_case:
2103	if (fWritable)
2104	PCIDevSetByte(aDev, addr, u8Val);
2105	}
2106	addr++;
2107	val >>= 8;
2108	}
2109
2110	if (fUpdateMappings)
2111	/* if the command/base address register is modified, we must modify the mappings */
2112	ich9pciUpdateMappings(aDev);
2113	}
2114
2115	static bool assignPosition(PICH9PCIBUS pBus, PPCIDEVICE pPciDev, const char pszName, int iDevFn, PciAddress aPosition)
2116	{
2117	aPosition->iBus = 0;
2118	aPosition->iDeviceFunc = iDevFn;
2119	aPosition->iRegister = 0; /* N/A */
2120
2121	/* Explicit slot request */
2122	if (iDevFn >=0 && iDevFn < (int)RT_ELEMENTS(pBus->apDevices))
2123	return true;
2124
2125	int iStartPos = 0;
2126
2127	/* Otherwise when assigning a slot, we need to make sure all its functions are available */
2128	for (int iPos = iStartPos; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
2129	{
2130	if ( !pBus->apDevices[iPos]
2131	&& !pBus->apDevices[iPos + 1]
2132	&& !pBus->apDevices[iPos + 2]
2133	&& !pBus->apDevices[iPos + 3]
2134	&& !pBus->apDevices[iPos + 4]
2135	&& !pBus->apDevices[iPos + 5]
2136	&& !pBus->apDevices[iPos + 6]
2137	&& !pBus->apDevices[iPos + 7])
2138	{
2139	pciDevClearRequestedDevfunc(pPciDev);
2140	aPosition->iDeviceFunc = iPos;
2141	return true;
2142	}
2143	}
2144
2145	return false;
2146	}
2147
2148	static bool hasHardAssignedDevsInSlot(PICH9PCIBUS pBus, int iSlot)
2149	{
2150	PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
2151
2152	return (aSlot[0] && pciDevIsRequestedDevfunc(aSlot[0]))
2153	\|\| (aSlot[1] && pciDevIsRequestedDevfunc(aSlot[1]))
2154	\|\| (aSlot[2] && pciDevIsRequestedDevfunc(aSlot[2]))
2155	\|\| (aSlot[3] && pciDevIsRequestedDevfunc(aSlot[3]))
2156	\|\| (aSlot[4] && pciDevIsRequestedDevfunc(aSlot[4]))
2157	\|\| (aSlot[5] && pciDevIsRequestedDevfunc(aSlot[5]))
2158	\|\| (aSlot[6] && pciDevIsRequestedDevfunc(aSlot[6]))
2159	\|\| (aSlot[7] && pciDevIsRequestedDevfunc(aSlot[7]))
2160	;
2161	}
2162
2163	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
2164	{
2165	PciAddress aPosition = {0, 0, 0};
2166
2167	/*
2168	* Find device position
2169	*/
2170	if (!assignPosition(pBus, pPciDev, pszName, iDev, &aPosition))
2171	{
2172	AssertMsgFailed(("Couldn't asssign position!\n"));
2173	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2174	}
2175
2176	AssertMsgReturn(aPosition.iBus == 0,
2177	("Assigning behind the bridge not implemented yet\n"),
2178	VERR_PDM_TOO_PCI_MANY_DEVICES);
2179
2180
2181	iDev = aPosition.iDeviceFunc;
2182	/*
2183	* Check if we can really take this slot, possibly by relocating
2184	* its current habitant, if it wasn't hard assigned too.
2185	*/
2186	if (pciDevIsRequestedDevfunc(pPciDev) &&
2187	pBus->apDevices[iDev] &&
2188	pciDevIsRequestedDevfunc(pBus->apDevices[iDev]))
2189	{
2190	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
2191	pszName, pBus->apDevices[iDev]->name, iDev));
2192	return VERR_INTERNAL_ERROR;
2193	}
2194
2195	if (pBus->apDevices[iDev])
2196	{
2197	/* if we got here, we shall (and usually can) relocate the device */
2198	bool assigned = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name, -1, &aPosition);
2199	AssertMsgReturn(aPosition.iBus == 0,
2200	("Assigning behind the bridge not implemented yet\n"),
2201	VERR_PDM_TOO_PCI_MANY_DEVICES);
2202	int iRelDev = aPosition.iDeviceFunc;
2203	if (!assigned \|\| iRelDev == iDev)
2204	{
2205	AssertMsgFailed(("Couldn't find free spot!\n"));
2206	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2207	}
2208	/* Copy device function by function to its new position */
2209	for (int i = 0; i < 8; i++)
2210	{
2211	if (!pBus->apDevices[iDev + i])
2212	continue;
2213	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
2214	pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
2215	pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
2216	pBus->apDevices[iDev + i] = NULL;
2217	}
2218	}
2219
2220	/*
2221	* Fill in device information.
2222	*/
2223	pPciDev->devfn = iDev;
2224	pPciDev->name = pszName;
2225	pPciDev->Int.s.pBusR3 = pBus;
2226	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2227	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2228	pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
2229	pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
2230	pBus->apDevices[iDev] = pPciDev;
2231	if (pciDevIsPci2PciBridge(pPciDev))
2232	{
2233	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2234	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2235	("device is a bridge but does not implement read/write functions\n"));
2236	Log2(("Setting bridge %d on bus %p\n", pBus->cBridges, pBus));
2237	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2238	pBus->cBridges++;
2239	}
2240
2241	Log(("PCI: Registered device %d function %d on bus %d (%#x) '%s'.\n",
2242	iDev >> 3, iDev & 7, pBus->iBus, 0x80000000 \| (iDev << 8), pszName));
2243
2244	return VINF_SUCCESS;
2245	}
2246
2247	static void printIndent(PCDBGFINFOHLP pHlp, int iIndent)
2248	{
2249	for (int i = 0; i < iIndent; i++)
2250	{
2251	pHlp->pfnPrintf(pHlp, " ");
2252	}
2253	}
2254
2255	static void ich9pciBusInfo(PICH9PCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
2256	{
2257	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2258	{
2259	PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2260	if (pPciDev != NULL)
2261	{
2262	printIndent(pHlp, iIndent);
2263
2264	/*
2265	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2266	* as host driver handles real devices interrupts.
2267	*/
2268	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x%s%s",
2269	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2270	pPciDev->name,
2271	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2272	ich9pciGetWord(pPciDev, VBOX_PCI_VENDOR_ID), ich9pciGetWord(pPciDev, VBOX_PCI_DEVICE_ID),
2273	pciDevIsMsiCapable(pPciDev) ? " MSI" : "",
2274	pciDevIsMsixCapable(pPciDev) ? " MSI-X" : ""
2275	);
2276	if (ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2277	pHlp->pfnPrintf(pHlp, " IRQ%d", ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2278
2279	pHlp->pfnPrintf(pHlp, "\n");
2280
2281	int iCmd = ich9pciGetWord(pPciDev, VBOX_PCI_COMMAND);
2282	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
2283	{
2284	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2285	{
2286	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2287	int32_t iRegionSize = pRegion->size;
2288
2289	if (iRegionSize == 0)
2290	continue;
2291
2292	uint32_t u32Addr = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion));
2293	const char * pszDesc;
2294	char szDescBuf[128];
2295
2296	bool f64Bit = (pRegion->type & PCI_ADDRESS_SPACE_BAR64);
2297	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2298	{
2299	pszDesc = "IO";
2300	u32Addr &= ~0x3;
2301	}
2302	else
2303	{
2304	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2305	f64Bit ? "64" : "32",
2306	(pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
2307	pszDesc = szDescBuf;
2308	u32Addr &= ~0xf;
2309	}
2310
2311	printIndent(pHlp, iIndent + 2);
2312	pHlp->pfnPrintf(pHlp, " %s region #%d: %x..%x\n",
2313	pszDesc, iRegion, u32Addr, u32Addr+iRegionSize);
2314	if (f64Bit)
2315	iRegion++;
2316	}
2317	}
2318
2319	if (fRegisters)
2320	{
2321	printIndent(pHlp, iIndent + 2);
2322	pHlp->pfnPrintf(pHlp, " PCI registers:\n");
2323	for (int iReg = 0; iReg < 0x100; )
2324	{
2325	int iPerLine = 0x10;
2326	Assert (0x100 % iPerLine == 0);
2327	printIndent(pHlp, iIndent + 3);
2328
2329	while (iPerLine-- > 0)
2330	{
2331	pHlp->pfnPrintf(pHlp, "%02x ", ich9pciGetByte(pPciDev, iReg++));
2332	}
2333	pHlp->pfnPrintf(pHlp, "\n");
2334	}
2335	}
2336	}
2337	}
2338
2339	if (pBus->cBridges > 0)
2340	{
2341	printIndent(pHlp, iIndent);
2342	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2343	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2344	{
2345	PICH9PCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PICH9PCIBUS);
2346	ich9pciBusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2347	}
2348	}
2349	}
2350
2351	/**
2352	* Info handler, device version.
2353	*
2354	* @param pDevIns Device instance which registered the info.
2355	* @param pHlp Callback functions for doing output.
2356	* @param pszArgs Argument string. Optional and specific to the handler.
2357	*/
2358	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2359	{
2360	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2361
2362	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2363	{
2364	ich9pciBusInfo(pBus, pHlp, 0, false);
2365	}
2366	else if (!strcmp(pszArgs, "verbose"))
2367	{
2368	ich9pciBusInfo(pBus, pHlp, 0, true);
2369	}
2370	else
2371	{
2372	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2373	}
2374	}
2375
2376
2377	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns,
2378	int iInstance,
2379	PCFGMNODE pCfg)
2380	{
2381	Assert(iInstance == 0);
2382	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2383
2384	/*
2385	* Validate and read configuration.
2386	*/
2387	if (!CFGMR3AreValuesValid(pCfg,
2388	"IOAPIC\0"
2389	"GCEnabled\0"
2390	"R0Enabled\0"
2391	"McfgBase\0"
2392	"McfgLength\0"
2393	))
2394	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2395
2396	/* query whether we got an IOAPIC */
2397	bool fUseIoApic;
2398	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2399	if (RT_FAILURE(rc))
2400	return PDMDEV_SET_ERROR(pDevIns, rc,
2401	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2402
2403	/* check if RC code is enabled. */
2404	bool fGCEnabled;
2405	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2406	if (RT_FAILURE(rc))
2407	return PDMDEV_SET_ERROR(pDevIns, rc,
2408	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2409	/* check if R0 code is enabled. */
2410	bool fR0Enabled;
2411	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2412	if (RT_FAILURE(rc))
2413	return PDMDEV_SET_ERROR(pDevIns, rc,
2414	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2415
2416	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2417
2418	/*
2419	* Init data.
2420	*/
2421	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2422	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2423	/* Zero out everything */
2424	memset(pGlobals, 0, sizeof(*pGlobals));
2425	/* And fill values */
2426	if (!fUseIoApic)
2427	return PDMDEV_SET_ERROR(pDevIns, rc,
2428	N_("Must use IO-APIC with ICH9 chipset"));
2429	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2430	if (RT_FAILURE(rc))
2431	return PDMDEV_SET_ERROR(pDevIns, rc,
2432	N_("Configuration error: Failed to read \"McfgBase\""));
2433	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2434	if (RT_FAILURE(rc))
2435	return PDMDEV_SET_ERROR(pDevIns, rc,
2436	N_("Configuration error: Failed to read \"McfgLength\""));
2437
2438	pGlobals->pDevInsR3 = pDevIns;
2439	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2440	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2441
2442	pGlobals->aPciBus.pDevInsR3 = pDevIns;
2443	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2444	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2445	pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2446
2447	/*
2448	* Register bus
2449	*/
2450	PDMPCIBUSREG PciBusReg;
2451	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2452	PciBusReg.pfnRegisterR3 = ich9pciRegister;
2453	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2454	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2455	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2456	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2457	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2458	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2459	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2460	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2461	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2462	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2463	if (RT_FAILURE(rc))
2464	return PDMDEV_SET_ERROR(pDevIns, rc,
2465	N_("Failed to register ourselves as a PCI Bus"));
2466	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2467	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2468	N_("PCI helper version mismatch; got %#x expected %#x"),
2469	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2470
2471	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2472	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2473
2474	/*
2475	* Fill in PCI configs and add them to the bus.
2476	*/
2477	/** @todo: Disabled for now because this causes error messages with Linux guests.
2478	* The guest loads the x38_edac device which tries to map a memory region
2479	* using an address given at place 0x48 - 0x4f in the PCi config space.
2480	* This fails. because we don't register such a region.
2481	*/
2482	#if 0
2483	/* Host bridge device */
2484	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2485	PCIDevSetDeviceId( &pBus->aPciDev, 0x29e0); /* Desktop */
2486	PCIDevSetRevisionId(&pBus->aPciDev, 0x01); /* rev. 01 */
2487	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2488	PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2489	PCIDevSetClassProg( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2490	PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* bridge */
2491	PCIDevSetWord(&pBus->aPciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
2492
2493	pBus->aPciDev.pDevIns = pDevIns;
2494	/* We register Host<->PCI controller on the bus */
2495	ich9pciRegisterInternal(pBus, 0, &pBus->aPciDev, "dram");
2496	#endif
2497
2498	/*
2499	* Register I/O ports and save state.
2500	*/
2501	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2502	if (RT_FAILURE(rc))
2503	return rc;
2504	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2505	if (RT_FAILURE(rc))
2506	return rc;
2507	if (fGCEnabled)
2508	{
2509	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2510	if (RT_FAILURE(rc))
2511	return rc;
2512	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2513	if (RT_FAILURE(rc))
2514	return rc;
2515	}
2516	if (fR0Enabled)
2517	{
2518	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2519	if (RT_FAILURE(rc))
2520	return rc;
2521	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2522	if (RT_FAILURE(rc))
2523	return rc;
2524	}
2525
2526	if (pGlobals->u64PciConfigMMioAddress != 0)
2527	{
2528	rc = PDMDevHlpMMIORegister(pDevIns,
2529	pGlobals->u64PciConfigMMioAddress,
2530	pGlobals->u64PciConfigMMioLength,
2531	0,
2532	ich9pciMcfgMMIOWrite,
2533	ich9pciMcfgMMIORead,
2534	NULL /* fill */,
2535	"MCFG ranges");
2536	if (RT_FAILURE(rc))
2537	{
2538	AssertMsgRC(rc, ("Cannot register MCFG MMIO: %Rrc\n", rc));
2539	return rc;
2540	}
2541
2542	if (fGCEnabled)
2543	{
2544
2545	rc = PDMDevHlpMMIORegisterRC(pDevIns,
2546	pGlobals->u64PciConfigMMioAddress,
2547	pGlobals->u64PciConfigMMioLength,
2548	0,
2549	"ich9pciMcfgMMIOWrite",
2550	"ich9pciMcfgMMIORead",
2551	NULL /* fill */);
2552	if (RT_FAILURE(rc))
2553	{
2554	AssertMsgRC(rc, ("Cannot register MCFG MMIO (GC): %Rrc\n", rc));
2555	return rc;
2556	}
2557	}
2558
2559
2560	if (fR0Enabled)
2561	{
2562
2563	rc = PDMDevHlpMMIORegisterR0(pDevIns,
2564	pGlobals->u64PciConfigMMioAddress,
2565	pGlobals->u64PciConfigMMioLength,
2566	0,
2567	"ich9pciMcfgMMIOWrite",
2568	"ich9pciMcfgMMIORead",
2569	NULL /* fill */);
2570	if (RT_FAILURE(rc))
2571	{
2572	AssertMsgRC(rc, ("Cannot register MCFG MMIO (R0): %Rrc\n", rc));
2573	return rc;
2574	}
2575	}
2576	}
2577
2578	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2579	sizeof(pBus) + 16128, "pgm",
2580	NULL, NULL, NULL,
2581	NULL, ich9pciR3SaveExec, NULL,
2582	NULL, ich9pciR3LoadExec, NULL);
2583	if (RT_FAILURE(rc))
2584	return rc;
2585
2586
2587	/** @todo: other chipset devices shall be registered too */
2588
2589	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. (no arguments)", ich9pciInfo);
2590
2591	return VINF_SUCCESS;
2592	}
2593
2594	static void ich9pciResetDevice(PPCIDEVICE pDev)
2595	{
2596	PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
2597	int rc;
2598
2599	/* Clear regions */
2600	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2601	{
2602	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
2603	if (pRegion->size == 0)
2604	continue;
2605
2606	ich9pciUnmapRegion(pDev, iRegion);
2607	}
2608
2609	if (pciDevIsPassthrough(pDev))
2610	{
2611	// no reset handler - we can do what we need in PDM reset handler
2612	// @todo: is it correct?
2613	}
2614	else
2615	{
2616	PCIDevSetCommand(pDev,
2617	PCIDevGetCommand(pDev)
2618	&
2619	~(VBOX_PCI_COMMAND_IO \|
2620	VBOX_PCI_COMMAND_MEMORY \|
2621	VBOX_PCI_COMMAND_MASTER));
2622
2623	/* Bridge device reset handlers processed later */
2624	if (!pciDevIsPci2PciBridge(pDev))
2625	{
2626	PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2627	PCIDevSetInterruptLine(pDev, 0x0);
2628	}
2629	}
2630	}
2631
2632
2633	/**
2634	* @copydoc FNPDMDEVRESET
2635	*/
2636	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2637	{
2638	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2639	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2640
2641	/* PCI-specific reset for each device. */
2642	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2643	{
2644	if (pBus->apDevices[i])
2645	ich9pciResetDevice(pBus->apDevices[i]);
2646	}
2647
2648	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2649	{
2650	if (pBus->papBridgesR3[iBridge])
2651	ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->pDevIns);
2652	}
2653
2654	ich9pciFakePCIBIOS(pDevIns);
2655	}
2656
2657	static void ich9pciRelocateDevice(PPCIDEVICE pDev, RTGCINTPTR offDelta)
2658	{
2659	if (pDev)
2660	{
2661	pDev->Int.s.pBusRC += offDelta;
2662	if (pDev->Int.s.pMsixPageRC)
2663	pDev->Int.s.pMsixPageRC += offDelta;
2664	}
2665	}
2666
2667	/**
2668	* @copydoc FNPDMDEVRELOCATE
2669	*/
2670	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2671	{
2672	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2673	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2674	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2675
2676	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2677	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2678
2679	/* Relocate RC pointers for the attached pci devices. */
2680	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2681	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2682
2683	}
2684
2685	/**
2686	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2687	*/
2688	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2689	int iInstance,
2690	PCFGMNODE pCfg)
2691	{
2692	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2693
2694	/*
2695	* Validate and read configuration.
2696	*/
2697	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2698	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2699
2700	/* check if RC code is enabled. */
2701	bool fGCEnabled;
2702	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2703	if (RT_FAILURE(rc))
2704	return PDMDEV_SET_ERROR(pDevIns, rc,
2705	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2706
2707	/* check if R0 code is enabled. */
2708	bool fR0Enabled;
2709	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2710	if (RT_FAILURE(rc))
2711	return PDMDEV_SET_ERROR(pDevIns, rc,
2712	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2713	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2714
2715	/*
2716	* Init data and register the PCI bus.
2717	*/
2718	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2719	pBus->pDevInsR3 = pDevIns;
2720	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2721	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2722	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->apDevices));
2723
2724	PDMPCIBUSREG PciBusReg;
2725	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2726	PciBusReg.pfnRegisterR3 = ich9pcibridgeRegister;
2727	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2728	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2729	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2730	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2731	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2732	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2733	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2734	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2735	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2736	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2737	if (RT_FAILURE(rc))
2738	return PDMDEV_SET_ERROR(pDevIns, rc,
2739	N_("Failed to register ourselves as a PCI Bus"));
2740	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2741	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2742	N_("PCI helper version mismatch; got %#x expected %#x"),
2743	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2744
2745	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2746	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2747
2748	/*
2749	* Fill in PCI configs and add them to the bus.
2750	*/
2751	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2752	PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2753	PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2754	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2755	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2756	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2757	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2758	PCIDevSetCommand( &pBus->aPciDev, 0x00);
2759	PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2760	PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2761
2762	/*
2763	* This device does not generate interrupts. Interrupt delivery from
2764	* devices attached to the bus is unaffected.
2765	*/
2766	PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2767
2768	pBus->aPciDev.pDevIns = pDevIns;
2769
2770	/* Bridge-specific data */
2771	pciDevSetPci2PciBridge(&pBus->aPciDev);
2772	pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2773	pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2774
2775	/*
2776	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2777	*/
2778	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2779	if (RT_FAILURE(rc))
2780	return rc;
2781
2782	/*
2783	* The iBus property doesn't really represent the bus number
2784	* because the guest and the BIOS can choose different bus numbers
2785	* for them.
2786	* The bus number is mainly for the setIrq function to indicate
2787	* when the host bus is reached which will have iBus = 0.
2788	* That's why the + 1.
2789	*/
2790	pBus->iBus = iInstance + 1;
2791
2792	/*
2793	* Register SSM handlers. We use the same saved state version as for the host bridge
2794	* to make changes easier.
2795	*/
2796	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2797	sizeof(pBus) + 16128,
2798	"pgm" /* before */,
2799	NULL, NULL, NULL,
2800	NULL, ich9pcibridgeR3SaveExec, NULL,
2801	NULL, ich9pcibridgeR3LoadExec, NULL);
2802	if (RT_FAILURE(rc))
2803	return rc;
2804
2805
2806	return VINF_SUCCESS;
2807	}
2808
2809	/**
2810	* @copydoc FNPDMDEVRESET
2811	*/
2812	static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
2813	{
2814	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2815
2816	/* Reset config space to default values. */
2817	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2818	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2819	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2820
2821	/* PCI-specific reset for each device. */
2822	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2823	{
2824	if (pBus->apDevices[i])
2825	ich9pciResetDevice(pBus->apDevices[i]);
2826	}
2827	}
2828
2829
2830	/**
2831	* @copydoc FNPDMDEVRELOCATE
2832	*/
2833	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2834	{
2835	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2836	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2837
2838	/* Relocate RC pointers for the attached pci devices. */
2839	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2840	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2841	}
2842
2843	/**
2844	* The PCI bus device registration structure.
2845	*/
2846	const PDMDEVREG g_DevicePciIch9 =
2847	{
2848	/* u32Version */
2849	PDM_DEVREG_VERSION,
2850	/* szName */
2851	"ich9pci",
2852	/* szRCMod */
2853	"VBoxDDGC.gc",
2854	/* szR0Mod */
2855	"VBoxDDR0.r0",
2856	/* pszDescription */
2857	"ICH9 PCI bridge",
2858	/* fFlags */
2859	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2860	/* fClass */
2861	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2862	/* cMaxInstances */
2863	1,
2864	/* cbInstance */
2865	sizeof(ICH9PCIGLOBALS),
2866	/* pfnConstruct */
2867	ich9pciConstruct,
2868	/* pfnDestruct */
2869	NULL,
2870	/* pfnRelocate */
2871	ich9pciRelocate,
2872	/* pfnIOCtl */
2873	NULL,
2874	/* pfnPowerOn */
2875	NULL,
2876	/* pfnReset */
2877	ich9pciReset,
2878	/* pfnSuspend */
2879	NULL,
2880	/* pfnResume */
2881	NULL,
2882	/* pfnAttach */
2883	NULL,
2884	/* pfnDetach */
2885	NULL,
2886	/* pfnQueryInterface */
2887	NULL,
2888	/* pfnInitComplete */
2889	NULL,
2890	/* pfnPowerOff */
2891	NULL,
2892	/* pfnSoftReset */
2893	NULL,
2894	/* u32VersionEnd */
2895	PDM_DEVREG_VERSION
2896	};
2897
2898	/**
2899	* The device registration structure
2900	* for the PCI-to-PCI bridge.
2901	*/
2902	const PDMDEVREG g_DevicePciIch9Bridge =
2903	{
2904	/* u32Version */
2905	PDM_DEVREG_VERSION,
2906	/* szName */
2907	"ich9pcibridge",
2908	/* szRCMod */
2909	"VBoxDDGC.gc",
2910	/* szR0Mod */
2911	"VBoxDDR0.r0",
2912	/* pszDescription */
2913	"ICH9 PCI to PCI bridge",
2914	/* fFlags */
2915	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2916	/* fClass */
2917	PDM_DEVREG_CLASS_BUS_PCI,
2918	/* cMaxInstances */
2919	~0,
2920	/* cbInstance */
2921	sizeof(ICH9PCIBUS),
2922	/* pfnConstruct */
2923	ich9pcibridgeConstruct,
2924	/* pfnDestruct */
2925	NULL,
2926	/* pfnRelocate */
2927	ich9pcibridgeRelocate,
2928	/* pfnIOCtl */
2929	NULL,
2930	/* pfnPowerOn */
2931	NULL,
2932	/* pfnReset */
2933	NULL, /* Must be NULL, to make sure only bus driver handles reset */
2934	/* pfnSuspend */
2935	NULL,
2936	/* pfnResume */
2937	NULL,
2938	/* pfnAttach */
2939	NULL,
2940	/* pfnDetach */
2941	NULL,
2942	/* pfnQueryInterface */
2943	NULL,
2944	/* pfnInitComplete */
2945	NULL,
2946	/* pfnPowerOff */
2947	NULL,
2948	/* pfnSoftReset */
2949	NULL,
2950	/* u32VersionEnd */
2951	PDM_DEVREG_VERSION
2952	};
2953
2954	#endif /* IN_RING3 */
2955	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 37324

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