DevPciIch9.cpp@ 40894

Last change on this file since 40894 was 40282, checked in by vboxsync, 13 years ago
: gcc-4.7: ~0 => ~0U in initializers (warning: narrowing conversion of `-1' from` int' to `unsigned int' inside { } is ill-formed in C++11 [-Wnarrowing]*)
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1	/* $Id: DevPciIch9.cpp 40282 2012-02-28 21:02:40Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation device.
4	*/
5
6	/*
7	* Copyright (C) 2010-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_PCI
22	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
23	#define PCI_INCLUDE_PRIVATE
24	#define PCIBus ICH9PCIBus
25	#include <VBox/pci.h>
26	#include <VBox/msi.h>
27	#include <VBox/vmm/pdmdev.h>
28	#include <iprt/asm.h>
29	#include <iprt/assert.h>
30	#include <iprt/string.h>
31	#ifdef IN_RING3
32	#include <iprt/alloc.h>
33	#endif
34
35	#include "VBoxDD.h"
36
37	#include "MsiCommon.h"
38
39
40	/*******************************************************************************
41	* Structures and Typedefs *
42	*******************************************************************************/
43	/**
44	* PCI Bus instance.
45	*/
46	typedef struct ICH9PCIBus
47	{
48	/** Bus number. */
49	int32_t iBus;
50	/** Number of bridges attached to the bus. */
51	uint32_t cBridges;
52
53	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
54	R3PTRTYPE(PPCIDEVICE) apDevices[256];
55	/** Array of bridges attached to the bus. */
56	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
57
58	/** R3 pointer to the device instance. */
59	PPDMDEVINSR3 pDevInsR3;
60	/** Pointer to the PCI R3 helpers. */
61	PCPDMPCIHLPR3 pPciHlpR3;
62
63	/** R0 pointer to the device instance. */
64	PPDMDEVINSR0 pDevInsR0;
65	/** Pointer to the PCI R0 helpers. */
66	PCPDMPCIHLPR0 pPciHlpR0;
67
68	/** RC pointer to the device instance. */
69	PPDMDEVINSRC pDevInsRC;
70	/** Pointer to the PCI RC helpers. */
71	PCPDMPCIHLPRC pPciHlpRC;
72
73	/** The PCI device for the PCI bridge. */
74	PCIDEVICE aPciDev;
75
76	} ICH9PCIBUS, *PICH9PCIBUS;
77
78
79	/** @def PCI_APIC_IRQ_PINS
80	* Number of pins for interrupts if the APIC is used.
81	*/
82	#define PCI_APIC_IRQ_PINS 8
83
84	/**
85	* PCI Globals - This is the host-to-pci bridge and the root bus.
86	*/
87	typedef struct
88	{
89	/** R3 pointer to the device instance. */
90	PPDMDEVINSR3 pDevInsR3;
91	/** R0 pointer to the device instance. */
92	PPDMDEVINSR0 pDevInsR0;
93	/** RC pointer to the device instance. */
94	PPDMDEVINSRC pDevInsRC;
95
96	#if HC_ARCH_BITS == 64
97	uint32_t Alignment0;
98	#endif
99
100	/** Config register. */
101	uint32_t uConfigReg;
102
103	/** I/O APIC irq levels */
104	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
105
106	#if 1 /* Will be moved into the BIOS soon. */
107	/** The next I/O port address which the PCI BIOS will use. */
108	uint32_t uPciBiosIo;
109	/** The next MMIO address which the PCI BIOS will use. */
110	uint32_t uPciBiosMmio;
111	/** Actual bus number. */
112	uint8_t uBus;
113	#endif
114	/** Physical address of PCI config space MMIO region. */
115	uint64_t u64PciConfigMMioAddress;
116	/** Length of PCI config space MMIO region. */
117	uint64_t u64PciConfigMMioLength;
118
119	/** PCI bus which is attached to the host-to-PCI bridge. */
120	ICH9PCIBUS aPciBus;
121	} ICH9PCIGLOBALS, *PICH9PCIGLOBALS;
122
123
124	typedef struct
125	{
126	uint8_t iBus;
127	uint8_t iDeviceFunc;
128	uint16_t iRegister;
129	} PciAddress;
130
131	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
132
133	/*******************************************************************************
134	* Defined Constants And Macros *
135	*******************************************************************************/
136
137	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
138	* Saved state version of the ICH9 PCI bus device.
139	*/
140	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
141	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
142	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
143
144	/** Converts a bus instance pointer to a device instance pointer. */
145	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
146	/** Converts a device instance pointer to a ICH9PCIGLOBALS pointer. */
147	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PICH9PCIGLOBALS)(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)))
148	/** Converts a device instance pointer to a PCIBUS pointer. */
149	#define DEVINS_2_PCIBUS(pDevIns) ((PICH9PCIBUS)(&PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)->aPciBus))
150	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer. */
151	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PICH9PCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(ICH9PCIGLOBALS, aPciBus)) )
152
153	/** @def PCI_LOCK
154	* Acquires the PDM lock. This is a NOP if locking is disabled. */
155	/** @def PCI_UNLOCK
156	* Releases the PDM lock. This is a NOP if locking is disabled. */
157	#define PCI_LOCK(pDevIns, rc) \
158	do { \
159	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
160	if (rc2 != VINF_SUCCESS) \
161	return rc2; \
162	} while (0)
163	#define PCI_UNLOCK(pDevIns) \
164	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
165
166	/* Prototypes */
167	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel);
168	#ifdef IN_RING3
169	static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
170	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
171	static void ich9pciUpdateMappings(PCIDevice *pDev);
172	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
173	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus);
174	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn);
175	#endif
176
177	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
178	// mapping, we take n=6 approach
179	DECLINLINE(void) ich9pciPhysToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
180	{
181	NOREF(pGlobals);
182	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<6) - 1);
183	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
184	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
185	}
186
187	DECLINLINE(void) ich9pciStateToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
188	{
189	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
190	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
191	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
192	}
193
194	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
195	{
196	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
197	}
198
199	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
200	{
201	/*
202	* The PCI-to-PCI bridge specification defines how the interrupt pins
203	* are routed from the secondary to the primary bus (see chapter 9).
204	* iIrq gives the interrupt pin the pci device asserted.
205	* We change iIrq here according to the spec and call the SetIrq function
206	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
207	*/
208	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
209	PPCIDEVICE pPciDevBus = pPciDev;
210	int iIrqPinBridge = iIrq;
211	uint8_t uDevFnBridge = 0;
212
213	/* Walk the chain until we reach the host bus. */
214	do
215	{
216	uDevFnBridge = pBus->aPciDev.devfn;
217	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
218
219	/* Get the parent. */
220	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
221	pPciDevBus = &pBus->aPciDev;
222	} while (pBus->iBus != 0);
223
224	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
225	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel);
226	}
227
228	/**
229	* Port I/O Handler for PCI address OUT operations.
230	*
231	* @returns VBox status code.
232	*
233	* @param pDevIns The device instance.
234	* @param pvUser User argument - ignored.
235	* @param uPort Port number used for the OUT operation.
236	* @param u32 The value to output.
237	* @param cb The value size in bytes.
238	*/
239	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
240	{
241	LogFlow(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
242	NOREF(pvUser);
243	if (cb == 4)
244	{
245	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
246
247	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
248	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
249	PCI_UNLOCK(pDevIns);
250	}
251
252	return VINF_SUCCESS;
253	}
254
255	/**
256	* Port I/O Handler for PCI address IN operations.
257	*
258	* @returns VBox status code.
259	*
260	* @param pDevIns The device instance.
261	* @param pvUser User argument - ignored.
262	* @param uPort Port number used for the IN operation.
263	* @param pu32 Where to store the result.
264	* @param cb Number of bytes read.
265	*/
266	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
267	{
268	NOREF(pvUser);
269	if (cb == 4)
270	{
271	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
272	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
273	*pu32 = pThis->uConfigReg;
274	PCI_UNLOCK(pDevIns);
275	LogFlow(("ich9pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
276	return VINF_SUCCESS;
277	}
278
279	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
280
281	return VERR_IOM_IOPORT_UNUSED;
282	}
283
284	static int ich9pciDataWriteAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pAddr,
285	uint32_t val, int cb, int rcReschedule)
286	{
287	int rc = VINF_SUCCESS;
288
289	if (pAddr->iBus != 0)
290	{
291	if (pGlobals->aPciBus.cBridges)
292	{
293	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
294	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
295	if (pBridgeDevice)
296	{
297	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
298	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc,
299	pAddr->iRegister, val, cb);
300	}
301	else
302	{
303	// do nothing, bridge not found
304	}
305	NOREF(rcReschedule);
306	#else
307	rc = rcReschedule;
308	#endif
309	}
310	}
311	else
312	{
313	if (pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc])
314	{
315	#ifdef IN_RING3
316	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
317	aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, cb);
318	#else
319	rc = rcReschedule;
320	#endif
321	}
322	}
323
324	Log2(("ich9pciDataWriteAddr: %02x:%02x:%02x reg %x(%d) %x %Rrc\n",
325	pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister,
326	cb, val, rc));
327
328	return rc;
329	}
330
331	static int ich9pciDataWrite(PICH9PCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
332	{
333	PciAddress aPciAddr;
334
335	LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
336
337	if (!(pGlobals->uConfigReg & (1 << 31)))
338	return VINF_SUCCESS;
339
340	if ((pGlobals->uConfigReg & 0x3) != 0)
341	return VINF_SUCCESS;
342
343	/* Compute destination device */
344	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
345
346	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VINF_IOM_R3_IOPORT_WRITE);
347	}
348
349	static void ich9pciNoMem(void* ptr, int cb)
350	{
351	for (int i = 0; i < cb; i++)
352	((uint8_t*)ptr)[i] = 0xff;
353	}
354
355	/**
356	* Port I/O Handler for PCI data OUT operations.
357	*
358	* @returns VBox status code.
359	*
360	* @param pDevIns The device instance.
361	* @param pvUser User argument - ignored.
362	* @param uPort Port number used for the OUT operation.
363	* @param u32 The value to output.
364	* @param cb The value size in bytes.
365	*/
366	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
367	{
368	LogFlow(("ich9pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
369	NOREF(pvUser);
370	int rc = VINF_SUCCESS;
371	if (!(Port % cb))
372	{
373	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
374	rc = ich9pciDataWrite(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), Port, u32, cb);
375	PCI_UNLOCK(pDevIns);
376	}
377	else
378	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
379	return rc;
380	}
381
382	static int ich9pciDataReadAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pPciAddr, int cb,
383	uint32_t *pu32, int rcReschedule)
384	{
385	int rc = VINF_SUCCESS;
386
387	if (pPciAddr->iBus != 0)
388	{
389	if (pGlobals->aPciBus.cBridges)
390	{
391	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
392	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
393	if (pBridgeDevice)
394	{
395	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
396	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
397	}
398	else
399	ich9pciNoMem(pu32, cb);
400	NOREF(rcReschedule);
401	#else
402	rc = rcReschedule;
403	#endif
404	} else
405	ich9pciNoMem(pu32, cb);
406	}
407	else
408	{
409	if (pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc])
410	{
411	#ifdef IN_RING3
412	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
413	*pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, cb);
414	#else
415	rc = rcReschedule;
416	#endif
417	}
418	else
419	ich9pciNoMem(pu32, cb);
420	}
421
422	Log3(("ich9pciDataReadAddr: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n",
423	pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister,
424	cb, *pu32, rc));
425
426	return rc;
427	}
428
429	static int ich9pciDataRead(PICH9PCIGLOBALS pGlobals, uint32_t addr, int cb, uint32_t *pu32)
430	{
431	PciAddress aPciAddr;
432
433	LogFlow(("ich9pciDataRead: config=%x cb=%d\n", pGlobals->uConfigReg, cb));
434
435	*pu32 = 0xffffffff;
436
437	if (!(pGlobals->uConfigReg & (1 << 31)))
438	return VINF_SUCCESS;
439
440	if ((pGlobals->uConfigReg & 0x3) != 0)
441	return VINF_SUCCESS;
442
443	/* Compute destination device */
444	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
445
446	return ich9pciDataReadAddr(pGlobals, &aPciAddr, cb, pu32, VINF_IOM_R3_IOPORT_READ);
447	}
448
449	/**
450	* Port I/O Handler for PCI data IN operations.
451	*
452	* @returns VBox status code.
453	*
454	* @param pDevIns The device instance.
455	* @param pvUser User argument - ignored.
456	* @param uPort Port number used for the IN operation.
457	* @param pu32 Where to store the result.
458	* @param cb Number of bytes read.
459	*/
460	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
461	{
462	NOREF(pvUser);
463	if (!(Port % cb))
464	{
465	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
466	int rc = ich9pciDataRead(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), Port, cb, pu32);
467	PCI_UNLOCK(pDevIns);
468	LogFlow(("ich9pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
469	return rc;
470	}
471	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
472	return VERR_IOM_IOPORT_UNUSED;
473	}
474
475	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
476	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
477	{
478	return (irq_num + uSlot) & 7;
479	}
480
481	/* return the global irq number corresponding to a given device irq
482	pin. We could also use the bus number to have a more precise
483	mapping. This is the implementation note described in the PCI spec chapter 2.2.6 */
484	DECLINLINE(int) ich9pciSlotGetPirq(uint8_t uBus, uint8_t uDevFn, int iIrqNum)
485	{
486	NOREF(uBus);
487	int iSlotAddend = (uDevFn >> 3) - 1;
488	return (iIrqNum + iSlotAddend) & 3;
489	}
490
491	/* irqs corresponding to PCI irqs A-D, must match pci_irq_list in rombios.c */
492	static const uint8_t aPciIrqs[4] = { 11, 10, 9, 5 };
493
494	/* Add one more level up request on APIC input line */
495	DECLINLINE(void) ich9pciApicLevelUp(PICH9PCIGLOBALS pGlobals, int irq_num)
496	{
497	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
498	}
499
500	/* Remove one level up request on APIC input line */
501	DECLINLINE(void) ich9pciApicLevelDown(PICH9PCIGLOBALS pGlobals, int irq_num)
502	{
503	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
504	}
505
506	static void ich9pciApicSetIrq(PICH9PCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int iForcedIrq)
507	{
508	/* This is only allowed to be called with a pointer to the root bus. */
509	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
510
511	if (iForcedIrq == -1)
512	{
513	int apic_irq, apic_level;
514	PICH9PCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
515	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
516
517	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
518	ich9pciApicLevelUp(pGlobals, irq_num);
519	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
520	ich9pciApicLevelDown(pGlobals, irq_num);
521
522	apic_irq = irq_num + 0x10;
523	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
524	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
525	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
526	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
527
528	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
529	{
530	/*
531	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
532	* PDM_IRQ_LEVEL_HIGH bit set
533	*/
534	ich9pciApicLevelDown(pGlobals, irq_num);
535	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
536	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
537	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
538	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
539	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
540	}
541	} else {
542	Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d\n",
543	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq));
544	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel);
545	}
546	}
547
548	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
549	{
550
551	if (PCIDevIsIntxDisabled(pPciDev))
552	{
553	if (MsiIsEnabled(pPciDev))
554	{
555	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
556	MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel);
557	}
558
559	if (MsixIsEnabled(pPciDev))
560	{
561	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
562	MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel);
563	}
564	return;
565	}
566
567	PICH9PCIBUS pBus = &pGlobals->aPciBus;
568	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
569
570	/* Check if the state changed. */
571	if (pPciDev->Int.s.uIrqPinState != iLevel)
572	{
573	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
574
575	/* Send interrupt to I/O APIC only now. */
576	if (fIsAcpiDevice)
577	/*
578	* ACPI needs special treatment since SCI is hardwired and
579	* should not be affected by PCI IRQ routing tables at the
580	* same time SCI IRQ is shared in PCI sense hence this
581	* kludge (i.e. we fetch the hardwired value from ACPIs
582	* PCI device configuration space).
583	*/
584	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, PCIDevGetInterruptLine(pPciDev));
585	else
586	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);
587	}
588	}
589
590	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
591	{
592	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
593	PciAddress aDest;
594	uint32_t u32 = 0;
595	NOREF(pvUser);
596
597	Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
598
599	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_WRITE);
600
601	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
602
603	switch (cb)
604	{
605	case 1:
606	u32 = (uint8_t)pv;
607	break;
608	case 2:
609	u32 = (uint16_t)pv;
610	break;
611	case 4:
612	u32 = (uint32_t)pv;
613	break;
614	default:
615	Assert(false);
616	break;
617	}
618	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb, VINF_IOM_R3_MMIO_WRITE);
619	PCI_UNLOCK(pDevIns);
620
621	return rc;
622	}
623
624	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
625	{
626	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
627	PciAddress aDest;
628	uint32_t rv;
629	NOREF(pvUser);
630
631	LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
632
633	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_READ);
634
635	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
636
637	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv, VINF_IOM_R3_MMIO_READ);
638
639	if (RT_SUCCESS(rc))
640	{
641	switch (cb)
642	{
643	case 1:
644	(uint8_t)pv = (uint8_t)rv;
645	break;
646	case 2:
647	(uint16_t)pv = (uint16_t)rv;
648	break;
649	case 4:
650	(uint32_t)pv = (uint32_t)rv;
651	break;
652	default:
653	Assert(false);
654	break;
655	}
656	}
657	PCI_UNLOCK(pDevIns);
658
659	return rc;
660	}
661
662	#ifdef IN_RING3
663
664	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus)
665	{
666	/* Search for a fitting bridge. */
667	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
668	{
669	/*
670	* Examine secondary and subordinate bus number.
671	* If the target bus is in the range we pass the request on to the bridge.
672	*/
673	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
674	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
675	("Device is not a PCI bridge but on the list of PCI bridges\n"));
676	uint32_t uSecondary = PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS);
677	uint32_t uSubordinate = PCIDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS);
678	Log3(("ich9pciFindBridge on bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, iBus, uSecondary, uSubordinate));
679	if (iBus >= uSecondary && iBus <= uSubordinate)
680	return pBridge;
681	}
682
683	/* Nothing found. */
684	return NULL;
685	}
686
687	static uint32_t ich9pciGetCfg(PCIDevice* aDev, int32_t iRegister, int cb)
688	{
689	return aDev->Int.s.pfnConfigRead(aDev, iRegister, cb);
690	}
691
692	static uint8_t ich9pciGetByte(PCIDevice* aDev, int32_t iRegister)
693	{
694	return (uint8_t)ich9pciGetCfg(aDev, iRegister, 1);
695	}
696
697	static uint16_t ich9pciGetWord(PCIDevice* aDev, int32_t iRegister)
698	{
699	return (uint16_t)ich9pciGetCfg(aDev, iRegister, 2);
700	}
701
702	static uint32_t ich9pciGetDWord(PCIDevice* aDev, int32_t iRegister)
703	{
704	return (uint32_t)ich9pciGetCfg(aDev, iRegister, 4);
705	}
706
707	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
708	{
709	return (iRegion == VBOX_PCI_ROM_SLOT) ?
710	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
711	}
712
713	#define INVALID_PCI_ADDRESS ~0U
714
715	static int ich9pciUnmapRegion(PPCIDEVICE pDev, int iRegion)
716	{
717	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
718	int rc = VINF_SUCCESS;
719	PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
720
721	Assert (pRegion->size != 0);
722
723	if (pRegion->addr != INVALID_PCI_ADDRESS)
724	{
725	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
726	{
727	/* Port IO */
728	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
729	AssertRC(rc);
730	}
731	else
732	{
733	RTGCPHYS GCPhysBase = pRegion->addr;
734	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
735	{
736	/* unmap it. */
737	rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
738	AssertRC(rc);
739	rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
740	}
741	else
742	rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
743	}
744
745	pRegion->addr = INVALID_PCI_ADDRESS;
746	}
747
748	return rc;
749	}
750
751	static void ich9pciUpdateMappings(PCIDevice* pDev)
752	{
753	uint64_t uLast, uNew;
754
755	int iCmd = ich9pciGetWord(pDev, VBOX_PCI_COMMAND);
756	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
757	{
758	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
759	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
760	int64_t iRegionSize = pRegion->size;
761	int rc;
762
763	if (iRegionSize == 0)
764	continue;
765
766	bool f64Bit = (pRegion->type & PCI_ADDRESS_SPACE_BAR64) != 0;
767
768	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
769	{
770	/* port IO region */
771	if (iCmd & PCI_COMMAND_IOACCESS)
772	{
773	/* IO access allowed */
774	uNew = ich9pciGetDWord(pDev, uConfigReg);
775	uNew &= ~(iRegionSize - 1);
776	uLast = uNew + iRegionSize - 1;
777	/* only 64K ioports on PC */
778	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
779	uNew = INVALID_PCI_ADDRESS;
780	} else
781	uNew = INVALID_PCI_ADDRESS;
782	}
783	else
784	{
785	/* MMIO region */
786	if (iCmd & PCI_COMMAND_MEMACCESS)
787	{
788	uNew = ich9pciGetDWord(pDev, uConfigReg);
789
790	if (f64Bit)
791	{
792	uNew \|= ((uint64_t)ich9pciGetDWord(pDev, uConfigReg+4)) << 32;
793	if (uNew > UINT64_C(0x0000010000000000))
794	{
795	/* Workaround for REM being unhapping with mapping very lange 64-bit addresses */
796	Log(("Ignoring too 64-bit BAR: %llx\n", uNew));
797	uNew = INVALID_PCI_ADDRESS;
798	}
799	}
800
801	/* the ROM slot has a specific enable bit */
802	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
803	uNew = INVALID_PCI_ADDRESS;
804	else
805	{
806	uNew &= ~(iRegionSize - 1);
807	uLast = uNew + iRegionSize - 1;
808	/* NOTE: we do not support wrapping */
809	/* XXX: as we cannot support really dynamic
810	mappings, we handle specific values as invalid
811	mappings. */
812	if (uLast <= uNew \|\| uNew == 0 \|\| uLast == INVALID_PCI_ADDRESS)
813	uNew = INVALID_PCI_ADDRESS;
814	}
815	} else
816	uNew = INVALID_PCI_ADDRESS;
817	}
818	/* now do the real mapping */
819	if (uNew != pRegion->addr)
820	{
821	if (pRegion->addr != INVALID_PCI_ADDRESS)
822	ich9pciUnmapRegion(pDev, iRegion);
823
824	pRegion->addr = uNew;
825	if (pRegion->addr != INVALID_PCI_ADDRESS)
826	{
827
828	/* finally, map the region */
829	rc = pRegion->map_func(pDev, iRegion,
830	pRegion->addr, pRegion->size,
831	(PCIADDRESSSPACE)(pRegion->type));
832	AssertRC(rc);
833	}
834	}
835	}
836	}
837
838	static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
839	{
840	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
841
842	/*
843	* Check input.
844	*/
845	if ( !pszName
846	\|\| !pPciDev
847	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices)
848	)
849	{
850	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
851	return VERR_INVALID_PARAMETER;
852	}
853
854	/*
855	* Register the device.
856	*/
857	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
858	}
859
860
861	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
862	{
863	NOREF(pDevIns);
864	int rc;
865
866	rc = MsiInit(pPciDev, pMsiReg);
867	if (RT_FAILURE(rc))
868	return rc;
869
870	rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
871	if (RT_FAILURE(rc))
872	return rc;
873
874	return VINF_SUCCESS;
875	}
876
877
878	static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
879	{
880
881	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
882
883	/*
884	* Check input.
885	*/
886	if ( !pszName
887	\|\| !pPciDev
888	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices))
889	{
890	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
891	return VERR_INVALID_PARAMETER;
892	}
893
894	/*
895	* Register the device.
896	*/
897	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
898	}
899
900	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
901	{
902	NOREF(pDevIns);
903
904	/*
905	* Validate.
906	*/
907	AssertMsgReturn( enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR32)
908	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR32)
909	\|\| enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR64)
910	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR64)
911	\|\| enmType == PCI_ADDRESS_SPACE_IO
912	,
913	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
914	VERR_INVALID_PARAMETER);
915	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
916	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
917	VERR_INVALID_PARAMETER);
918	int iLastSet = ASMBitLastSetU32(cbRegion);
919	AssertMsgReturn( iLastSet != 0
920	&& RT_BIT_32(iLastSet - 1) == cbRegion,
921	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
922	VERR_INVALID_PARAMETER);
923
924	Log(("ich9pciIORegionRegister: %s region %d size %d type %x\n",
925	pPciDev->name, iRegion, cbRegion, enmType));
926
927	/* Make sure that we haven't marked this region as continuation of 64-bit region. */
928	Assert(pPciDev->Int.s.aIORegions[iRegion].type != 0xff);
929
930	/*
931	* Register the I/O region.
932	*/
933	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
934	pRegion->addr = INVALID_PCI_ADDRESS;
935	pRegion->size = cbRegion;
936	pRegion->type = enmType;
937	pRegion->map_func = pfnCallback;
938
939	if ((enmType & PCI_ADDRESS_SPACE_BAR64) != 0)
940	{
941	AssertMsgReturn(iRegion < 4,
942	("Region %d cannot be 64-bit\n", iRegion),
943	VERR_INVALID_PARAMETER);
944	/* Mark next region as continuation of this one. */
945	pPciDev->Int.s.aIORegions[iRegion+1].type = 0xff;
946	}
947
948	/* Set type in the PCI config space. */
949	uint32_t u32Value = ((uint32_t)enmType) & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH);
950	PCIDevSetDWord(pPciDev, ich9pciGetRegionReg(iRegion), u32Value);
951
952	return VINF_SUCCESS;
953	}
954
955	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
956	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
957	{
958	NOREF(pDevIns);
959
960	if (ppfnReadOld)
961	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
962	pPciDev->Int.s.pfnConfigRead = pfnRead;
963
964	if (ppfnWriteOld)
965	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
966	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
967	}
968
969	/**
970	* Saves a state of the PCI device.
971	*
972	* @returns VBox status code.
973	* @param pDevIns Device instance of the PCI Bus.
974	* @param pPciDev Pointer to PCI device.
975	* @param pSSM The handle to save the state to.
976	*/
977	static DECLCALLBACK(int) ich9pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
978	{
979	NOREF(pDevIns);
980	Assert(!pciDevIsPassthrough(pPciDev));
981	return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
982	}
983
984	static int ich9pciR3CommonSaveExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM)
985	{
986	/*
987	* Iterate thru all the devices.
988	*/
989	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
990	{
991	PPCIDEVICE pDev = pBus->apDevices[i];
992	if (pDev)
993	{
994	/* Device position */
995	SSMR3PutU32(pSSM, i);
996	/* PCI config registers */
997	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
998
999	/* Device flags */
1000	int rc = SSMR3PutU32(pSSM, pDev->Int.s.fFlags);
1001	if (RT_FAILURE(rc))
1002	return rc;
1003
1004	/* IRQ pin state */
1005	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1006	if (RT_FAILURE(rc))
1007	return rc;
1008
1009	/* MSI info */
1010	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
1011	if (RT_FAILURE(rc))
1012	return rc;
1013	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
1014	if (RT_FAILURE(rc))
1015	return rc;
1016
1017	/* MSI-X info */
1018	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
1019	if (RT_FAILURE(rc))
1020	return rc;
1021	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
1022	if (RT_FAILURE(rc))
1023	return rc;
1024	/* Save MSI-X page state */
1025	if (pDev->Int.s.u8MsixCapOffset != 0)
1026	{
1027	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1028	SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
1029	if (RT_FAILURE(rc))
1030	return rc;
1031	}
1032	}
1033	}
1034	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1035	}
1036
1037	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1038	{
1039	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1040
1041	/*
1042	* Bus state data.
1043	*/
1044	SSMR3PutU32(pSSM, pThis->uConfigReg);
1045
1046	/*
1047	* Save IRQ states.
1048	*/
1049	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1050	SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
1051
1052	SSMR3PutU32(pSSM, ~0); /* separator */
1053
1054	return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
1055	}
1056
1057
1058	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1059	{
1060	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1061	return ich9pciR3CommonSaveExec(pThis, pSSM);
1062	}
1063
1064
1065	static void ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1066	{
1067	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1068
1069	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1070
1071	/* If the current bus is not the target bus search for the bus which contains the device. */
1072	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1073	{
1074	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1075	if (pBridgeDevice)
1076	{
1077	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1078	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
1079	}
1080	}
1081	else
1082	{
1083	/* This is the target bus, pass the write to the device. */
1084	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1085	if (pPciDev)
1086	{
1087	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1088	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
1089	}
1090	}
1091	}
1092
1093	static uint32_t ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1094	{
1095	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1096	uint32_t u32Value;
1097
1098	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1099
1100	/* If the current bus is not the target bus search for the bus which contains the device. */
1101	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1102	{
1103	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1104	if (pBridgeDevice)
1105	{
1106	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1107	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
1108	}
1109	else
1110	ich9pciNoMem(&u32Value, 4);
1111	}
1112	else
1113	{
1114	/* This is the target bus, pass the read to the device. */
1115	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1116	if (pPciDev)
1117	{
1118	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
1119	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1120	}
1121	else
1122	ich9pciNoMem(&u32Value, 4);
1123	}
1124
1125	return u32Value;
1126	}
1127
1128
1129	/**
1130	* Common routine for restoring the config registers of a PCI device.
1131	*
1132	* @param pDev The PCI device.
1133	* @param pbSrcConfig The configuration register values to be loaded.
1134	* @param fIsBridge Whether this is a bridge device or not.
1135	*/
1136	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1137	{
1138	/*
1139	* This table defines the fields for normal devices and bridge devices, and
1140	* the order in which they need to be restored.
1141	*/
1142	static const struct PciField
1143	{
1144	uint8_t off;
1145	uint8_t cb;
1146	uint8_t fWritable;
1147	uint8_t fBridge;
1148	const char *pszName;
1149	} s_aFields[] =
1150	{
1151	/* off,cb,fW,fB, pszName */
1152	{ VBOX_PCI_VENDOR_ID, 2, 0, 3, "VENDOR_ID" },
1153	{ VBOX_PCI_DEVICE_ID, 2, 0, 3, "DEVICE_ID" },
1154	{ VBOX_PCI_STATUS, 2, 1, 3, "STATUS" },
1155	{ VBOX_PCI_REVISION_ID, 1, 0, 3, "REVISION_ID" },
1156	{ VBOX_PCI_CLASS_PROG, 1, 0, 3, "CLASS_PROG" },
1157	{ VBOX_PCI_CLASS_SUB, 1, 0, 3, "CLASS_SUB" },
1158	{ VBOX_PCI_CLASS_BASE, 1, 0, 3, "CLASS_BASE" },
1159	{ VBOX_PCI_CACHE_LINE_SIZE, 1, 1, 3, "CACHE_LINE_SIZE" },
1160	{ VBOX_PCI_LATENCY_TIMER, 1, 1, 3, "LATENCY_TIMER" },
1161	{ VBOX_PCI_HEADER_TYPE, 1, 0, 3, "HEADER_TYPE" },
1162	{ VBOX_PCI_BIST, 1, 1, 3, "BIST" },
1163	{ VBOX_PCI_BASE_ADDRESS_0, 4, 1, 3, "BASE_ADDRESS_0" },
1164	{ VBOX_PCI_BASE_ADDRESS_1, 4, 1, 3, "BASE_ADDRESS_1" },
1165	{ VBOX_PCI_BASE_ADDRESS_2, 4, 1, 1, "BASE_ADDRESS_2" },
1166	{ VBOX_PCI_PRIMARY_BUS, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1167	{ VBOX_PCI_SECONDARY_BUS, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1168	{ VBOX_PCI_SUBORDINATE_BUS, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1169	{ VBOX_PCI_SEC_LATENCY_TIMER, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1170	{ VBOX_PCI_BASE_ADDRESS_3, 4, 1, 1, "BASE_ADDRESS_3" },
1171	{ VBOX_PCI_IO_BASE, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1172	{ VBOX_PCI_IO_LIMIT, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1173	{ VBOX_PCI_SEC_STATUS, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1174	{ VBOX_PCI_BASE_ADDRESS_4, 4, 1, 1, "BASE_ADDRESS_4" },
1175	{ VBOX_PCI_MEMORY_BASE, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1176	{ VBOX_PCI_MEMORY_LIMIT, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1177	{ VBOX_PCI_BASE_ADDRESS_5, 4, 1, 1, "BASE_ADDRESS_5" },
1178	{ VBOX_PCI_PREF_MEMORY_BASE, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1179	{ VBOX_PCI_PREF_MEMORY_LIMIT, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1180	{ VBOX_PCI_CARDBUS_CIS, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1181	{ VBOX_PCI_PREF_BASE_UPPER32, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1182	{ VBOX_PCI_SUBSYSTEM_VENDOR_ID, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1183	{ VBOX_PCI_PREF_LIMIT_UPPER32, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1184	{ VBOX_PCI_SUBSYSTEM_ID, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1185	{ VBOX_PCI_ROM_ADDRESS, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1186	{ VBOX_PCI_IO_BASE_UPPER16, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1187	{ VBOX_PCI_IO_LIMIT_UPPER16, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1188	{ VBOX_PCI_CAPABILITY_LIST, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1189	{ VBOX_PCI_RESERVED_38, 4, 1, 1, "RESERVED_38" }, // ???
1190	{ VBOX_PCI_ROM_ADDRESS_BR, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1191	{ VBOX_PCI_INTERRUPT_LINE, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1192	{ VBOX_PCI_INTERRUPT_PIN, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1193	{ VBOX_PCI_MIN_GNT, 1, 0, 1, "MIN_GNT" },
1194	{ VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1195	{ VBOX_PCI_MAX_LAT, 1, 0, 1, "MAX_LAT" },
1196	/* The COMMAND register must come last as it requires the ADDRESS
1197	registers to be restored before we pretent to change it from 0 to
1198	whatever value the guest assigned it. */
1199	{ VBOX_PCI_COMMAND, 2, 1, 3, "COMMAND" },
1200	};
1201
1202	#ifdef RT_STRICT
1203	/* Check that we've got full register coverage. */
1204	uint32_t bmDevice[0x40 / 32];
1205	uint32_t bmBridge[0x40 / 32];
1206	RT_ZERO(bmDevice);
1207	RT_ZERO(bmBridge);
1208	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1209	{
1210	uint8_t off = s_aFields[i].off;
1211	uint8_t cb = s_aFields[i].cb;
1212	uint8_t f = s_aFields[i].fBridge;
1213	while (cb-- > 0)
1214	{
1215	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1216	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1217	if (f & 1) ASMBitSet(bmDevice, off);
1218	if (f & 2) ASMBitSet(bmBridge, off);
1219	off++;
1220	}
1221	}
1222	for (uint32_t off = 0; off < 0x40; off++)
1223	{
1224	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1225	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1226	}
1227	#endif
1228
1229	/*
1230	* Loop thru the fields covering the 64 bytes of standard registers.
1231	*/
1232	uint8_t const fBridge = fIsBridge ? 2 : 1;
1233	Assert(!pciDevIsPassthrough(pDev));
1234	uint8_t *pbDstConfig = &pDev->config[0];
1235
1236	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1237	if (s_aFields[i].fBridge & fBridge)
1238	{
1239	uint8_t const off = s_aFields[i].off;
1240	uint8_t const cb = s_aFields[i].cb;
1241	uint32_t u32Src;
1242	uint32_t u32Dst;
1243	switch (cb)
1244	{
1245	case 1:
1246	u32Src = pbSrcConfig[off];
1247	u32Dst = pbDstConfig[off];
1248	break;
1249	case 2:
1250	u32Src = (uint16_t const )&pbSrcConfig[off];
1251	u32Dst = (uint16_t const )&pbDstConfig[off];
1252	break;
1253	case 4:
1254	u32Src = (uint32_t const )&pbSrcConfig[off];
1255	u32Dst = (uint32_t const )&pbDstConfig[off];
1256	break;
1257	default:
1258	AssertFailed();
1259	continue;
1260	}
1261
1262	if ( u32Src != u32Dst
1263	\|\| off == VBOX_PCI_COMMAND)
1264	{
1265	if (u32Src != u32Dst)
1266	{
1267	if (!s_aFields[i].fWritable)
1268	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1269	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1270	else
1271	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1272	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1273	}
1274	if (off == VBOX_PCI_COMMAND)
1275	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1276	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1277	}
1278	}
1279
1280	/*
1281	* The device dependent registers.
1282	*
1283	* We will not use ConfigWrite here as we have no clue about the size
1284	* of the registers, so the device is responsible for correctly
1285	* restoring functionality governed by these registers.
1286	*/
1287	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1288	if (pbDstConfig[off] != pbSrcConfig[off])
1289	{
1290	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1291	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1292	pbDstConfig[off] = pbSrcConfig[off];
1293	}
1294	}
1295
1296	/**
1297	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1298	*
1299	* @returns VBox status code.
1300	* @param pBus The bus which data is being loaded.
1301	* @param pSSM The saved state handle.
1302	* @param uVersion The data version.
1303	* @param uPass The pass.
1304	*/
1305	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1306	{
1307	uint32_t u32;
1308	uint32_t i;
1309	int rc;
1310
1311	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1312	if (uVersion != VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT)
1313	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1314
1315	/*
1316	* Iterate thru all the devices and write 0 to the COMMAND register so
1317	* that all the memory is unmapped before we start restoring the saved
1318	* mapping locations.
1319	*
1320	* The register value is restored afterwards so we can do proper
1321	* LogRels in pciR3CommonRestoreConfig.
1322	*/
1323	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1324	{
1325	PPCIDEVICE pDev = pBus->apDevices[i];
1326	if (pDev)
1327	{
1328	uint16_t u16 = PCIDevGetCommand(pDev);
1329	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1330	PCIDevSetCommand(pDev, u16);
1331	Assert(PCIDevGetCommand(pDev) == u16);
1332	}
1333	}
1334
1335	void *pvMsixPage = RTMemTmpAllocZ(0x1000);
1336	AssertReturn(pvMsixPage, VERR_NO_TMP_MEMORY);
1337
1338	/*
1339	* Iterate all the devices.
1340	*/
1341	for (i = 0;; i++)
1342	{
1343	PPCIDEVICE pDev;
1344	PCIDEVICE DevTmp;
1345
1346	/* index / terminator */
1347	rc = SSMR3GetU32(pSSM, &u32);
1348	if (RT_FAILURE(rc))
1349	break;
1350	if (u32 == (uint32_t)~0)
1351	break;
1352	AssertMsgBreak(u32 < RT_ELEMENTS(pBus->apDevices) && u32 >= i, ("u32=%#x i=%#x\n", u32, i));
1353
1354	/* skip forward to the device checking that no new devices are present. */
1355	for (; i < u32; i++)
1356	{
1357	pDev = pBus->apDevices[i];
1358	if (pDev)
1359	{
1360	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1361	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1362	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1363	{
1364	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1365	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1366	break;
1367	}
1368	}
1369	}
1370	if (RT_FAILURE(rc))
1371	break;
1372
1373	/* get the data */
1374	DevTmp.Int.s.fFlags = 0;
1375	DevTmp.Int.s.u8MsiCapOffset = 0;
1376	DevTmp.Int.s.u8MsiCapSize = 0;
1377	DevTmp.Int.s.u8MsixCapOffset = 0;
1378	DevTmp.Int.s.u8MsixCapSize = 0;
1379	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1380	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1381
1382	SSMR3GetU32(pSSM, &DevTmp.Int.s.fFlags);
1383	SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1384	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1385	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1386	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1387	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1388	if (RT_FAILURE(rc))
1389	break;
1390
1391	/* Load MSI-X page state */
1392	if (DevTmp.Int.s.u8MsixCapOffset != 0)
1393	{
1394	Assert(pvMsixPage != NULL);
1395	rc = SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1396	if (RT_FAILURE(rc))
1397	break;
1398	}
1399
1400	/* check that it's still around. */
1401	pDev = pBus->apDevices[i];
1402	if (!pDev)
1403	{
1404	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1405	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1406	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1407	{
1408	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1409	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1410	break;
1411	}
1412	continue;
1413	}
1414
1415	/* match the vendor id assuming that this will never be changed. */
1416	if (PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1417	{
1418	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1419	i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1420	break;
1421	}
1422
1423	/* commit the loaded device config. */
1424	Assert(!pciDevIsPassthrough(pDev));
1425	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1426
1427	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1428	pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1429	pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1430	pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1431	pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1432	if (DevTmp.Int.s.u8MsixCapSize != 0)
1433	{
1434	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1435	memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1436	}
1437	}
1438
1439	RTMemTmpFree(pvMsixPage);
1440
1441	return rc;
1442	}
1443
1444	/**
1445	* Loads a saved PCI device state.
1446	*
1447	* @returns VBox status code.
1448	* @param pDevIns Device instance of the PCI Bus.
1449	* @param pPciDev Pointer to PCI device.
1450	* @param pSSM The handle to the saved state.
1451	*/
1452	static DECLCALLBACK(int) ich9pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1453	{
1454	NOREF(pDevIns);
1455	Assert(!pciDevIsPassthrough(pPciDev));
1456	return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1457	}
1458
1459	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1460	{
1461	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1462	PICH9PCIBUS pBus = &pThis->aPciBus;
1463	uint32_t u32;
1464	int rc;
1465
1466	/* We ignore this version as there's no saved state with it anyway */
1467	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1468	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1469	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1470	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1471
1472	/*
1473	* Bus state data.
1474	*/
1475	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1476
1477	/*
1478	* Load IRQ states.
1479	*/
1480	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1481	SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1482
1483	/* separator */
1484	rc = SSMR3GetU32(pSSM, &u32);
1485	if (RT_FAILURE(rc))
1486	return rc;
1487	if (u32 != (uint32_t)~0)
1488	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1489
1490	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1491	}
1492
1493	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1494	{
1495	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1496	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1497	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1498	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1499	}
1500
1501	static uint32_t ich9pciConfigRead(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1502	{
1503	/* Will only work in LSB case */
1504	uint32_t u32Val;
1505	PciAddress aPciAddr;
1506
1507	aPciAddr.iBus = uBus;
1508	aPciAddr.iDeviceFunc = uDevFn;
1509	aPciAddr.iRegister = addr;
1510
1511	/* cannot be rescheduled, as already in R3 */
1512	int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR);
1513	AssertRC(rc);
1514	return u32Val;
1515	}
1516
1517	static void ich9pciConfigWrite(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1518	{
1519	PciAddress aPciAddr;
1520
1521	aPciAddr.iBus = uBus;
1522	aPciAddr.iDeviceFunc = uDevFn;
1523	aPciAddr.iRegister = addr;
1524
1525	/* cannot be rescheduled, as already in R3 */
1526	int rc = ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VERR_INTERNAL_ERROR);
1527	AssertRC(rc);
1528	}
1529
1530	static void ich9pciSetRegionAddress(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
1531	{
1532	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1533
1534	/* Read memory type first. */
1535	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1536	/* Read command register. */
1537	uint16_t uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1538
1539	Log(("Set region address: %02x:%02x.%d region %d address=%lld\n",
1540	uBus, uDevFn>>3, uDevFn&7, addr));
1541
1542	if ( iRegion == PCI_ROM_SLOT )
1543	uCmd \|= PCI_COMMAND_MEMACCESS;
1544	else if ((uResourceType & PCI_ADDRESS_SPACE_IO) == PCI_ADDRESS_SPACE_IO)
1545	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1546	else /* The region is MMIO. */
1547	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1548
1549	bool f64Bit = (uResourceType & PCI_ADDRESS_SPACE_BAR64) != 0;
1550
1551	/* Write address of the device. */
1552	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, (uint32_t)addr, 4);
1553	if (f64Bit)
1554	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg + 4, (uint32_t)(addr >> 32), 4);
1555
1556	/* enable memory mappings */
1557	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1558	}
1559
1560
1561	static void ich9pciBiosInitBridge(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1562	{
1563	Log(("BIOS init bridge: %02x::%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1564
1565	/*
1566	* The I/O range for the bridge must be aligned to a 4KB boundary.
1567	* This does not change anything really as the access to the device is not going
1568	* through the bridge but we want to be compliant to the spec.
1569	*/
1570	if ((pGlobals->uPciBiosIo % 4096) != 0)
1571	{
1572	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1573	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1574	}
1575	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1576
1577	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1578	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1579	{
1580	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1581	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1582	}
1583	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1584
1585	/* Save values to compare later to. */
1586	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1587	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1588	uint8_t uBridgeBus = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, 1);
1589
1590	/* Init devices behind the bridge and possibly other bridges as well. */
1591	for (int iDev = 0; iDev <= 255; iDev++)
1592	ich9pciBiosInitDevice(pGlobals, uBridgeBus, iDev);
1593
1594	/*
1595	* Set I/O limit register. If there is no device with I/O space behind the bridge
1596	* we set a lower value than in the base register.
1597	* The result with a real bridge is that no I/O transactions are passed to the secondary
1598	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1599	*/
1600	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1601	{
1602	/* The upper boundary must be one byte less than a 4KB boundary. */
1603	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1604	}
1605
1606	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1607
1608	/* Same with the MMIO limit register but with 1MB boundary here. */
1609	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1610	{
1611	/* The upper boundary must be one byte less than a 1MB boundary. */
1612	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1613	}
1614	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1615
1616	/*
1617	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1618	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1619	* the base register than in the limit register.
1620	*/
1621	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1622	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1623	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1624	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1625	}
1626
1627	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1628	{
1629	uint16_t uDevClass, uVendor, uDevice;
1630	uint8_t uCmd;
1631
1632	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1633	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1634	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1635
1636	/* If device is present */
1637	if (uVendor == 0xffff)
1638	return;
1639
1640	Log(("BIOS init device: %02x:%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1641
1642	switch (uDevClass)
1643	{
1644	case 0x0101:
1645	/* IDE controller */
1646	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1647	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1648	goto default_map;
1649	break;
1650	case 0x0300:
1651	/* VGA controller */
1652	if (uVendor != 0x80ee)
1653	goto default_map;
1654	/* VGA: map frame buffer to default Bochs VBE address */
1655	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0xE0000000);
1656	/*
1657	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1658	* only the framebuffer (i.e., a memory region) is explicitly registered via
1659	* ich9pciSetRegionAddress, so I/O decoding must be enabled manually.
1660	*/
1661	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1662	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1663	/* Enable I/O space access. */
1664	uCmd \| PCI_COMMAND_IOACCESS,
1665	1);
1666	break;
1667	case 0x0604:
1668	/* PCI-to-PCI bridge. */
1669	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1670	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn);
1671	break;
1672	default:
1673	default_map:
1674	{
1675	/* default memory mappings */
1676	/*
1677	* We ignore ROM region here.
1678	*/
1679	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1680	{
1681	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1682
1683	/* Calculate size - we write all 1s into the BAR, and then evaluate which bits
1684	are cleared. . */
1685	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1686
1687	bool f64bit = (u8ResourceType & PCI_ADDRESS_SPACE_BAR64) != 0;
1688	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1689	uint64_t cbRegSize64 = 0;
1690
1691	if (f64bit)
1692	{
1693	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1694	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0xffffffff), 4);
1695	cbRegSize64 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1696	cbRegSize64 \|= ((uint64_t)ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address+4, 4) << 32);
1697	cbRegSize64 &= ~UINT64_C(0x0f);
1698	cbRegSize64 = (~cbRegSize64) + 1;
1699
1700	/* No 64-bit PIO regions possible. */
1701	Assert((u8ResourceType & PCI_COMMAND_IOACCESS) == 0);
1702	}
1703	else
1704	{
1705	uint32_t cbRegSize32;
1706	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1707	cbRegSize32 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1708
1709	/* Clear resource information depending on resource type. */
1710	if (fIsPio) /* PIO */
1711	cbRegSize32 &= ~UINT32_C(0x01);
1712	else /* MMIO */
1713	cbRegSize32 &= ~UINT32_C(0x0f);
1714
1715	/*
1716	* Invert all bits and add 1 to get size of the region.
1717	* (From PCI implementation note)
1718	*/
1719	if (fIsPio && (cbRegSize32 & UINT32_C(0xffff0000)) == 0)
1720	cbRegSize32 = (~(cbRegSize32 \| UINT32_C(0xffff0000))) + 1;
1721	else
1722	cbRegSize32 = (~cbRegSize32) + 1;
1723
1724	cbRegSize64 = cbRegSize32;
1725	}
1726	Assert(cbRegSize64 == (uint32_t)cbRegSize64);
1727	Log2(("%s: Size of region %u for device %d on bus %d is %lld\n", __FUNCTION__, iRegion, uDevFn, uBus, cbRegSize64));
1728
1729	if (cbRegSize64)
1730	{
1731	uint32_t cbRegSize32 = (uint32_t)cbRegSize64;
1732	uint32_t* paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1733	paddr = (paddr + cbRegSize32 - 1) & ~(cbRegSize32 - 1);
1734	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, *paddr));
1735	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, *paddr);
1736	*paddr += cbRegSize32;
1737	Log2(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1738
1739	if (f64bit)
1740	iRegion++; /* skip next region */
1741	}
1742	}
1743	break;
1744	}
1745	}
1746
1747	/* map the interrupt */
1748	uint32_t iPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1749	if (iPin != 0)
1750	{
1751	iPin--;
1752
1753	if (uBus != 0)
1754	{
1755	/* Find bus this device attached to. */
1756	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1757	while (1)
1758	{
1759	PPCIDEVICE pBridge = ich9pciFindBridge(pBus, uBus);
1760	if (!pBridge)
1761	{
1762	Assert(false);
1763	break;
1764	}
1765	if (uBus == PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS))
1766	{
1767	/* OK, found bus this device attached to. */
1768	break;
1769	}
1770	pBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1771	}
1772
1773	/* We need to go up to the host bus to see which irq pin this
1774	* device will use there. See logic in ich9pcibridgeSetIrq().
1775	*/
1776	while (pBus->iBus != 0)
1777	{
1778	/* Get the pin the device would assert on the bridge. */
1779	iPin = ((pBus->aPciDev.devfn >> 3) + iPin) & 3;
1780	pBus = pBus->aPciDev.Int.s.pBusR3;
1781	};
1782	}
1783
1784	int iIrq = aPciIrqs[ich9pciSlotGetPirq(uBus, uDevFn, iPin)];
1785	Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
1786	iPin, iIrq, uBus, uDevFn>>3, uDevFn&7));
1787	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
1788	}
1789	}
1790
1791	/* Initializes bridges registers used for routing. */
1792	static void ich9pciInitBridgeTopology(PICH9PCIGLOBALS pGlobals, PICH9PCIBUS pBus)
1793	{
1794	PPCIDEVICE pBridgeDev = &pBus->aPciDev;
1795
1796	/* Set only if we are not on the root bus, it has no primary bus attached. */
1797	if (pGlobals->uBus != 0)
1798	{
1799	PCIDevSetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, pGlobals->uBus);
1800	PCIDevSetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
1801	}
1802
1803	pGlobals->uBus++;
1804	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1805	{
1806	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
1807	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
1808	("Device is not a PCI bridge but on the list of PCI bridges\n"));
1809	PICH9PCIBUS pChildBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1810	ich9pciInitBridgeTopology(pGlobals, pChildBus);
1811	}
1812	PCIDevSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1813	Log2(("ich9pciInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
1814	pBus,
1815	PCIDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
1816	PCIDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
1817	PCIDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS)
1818	));
1819	}
1820
1821
1822	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1823	{
1824	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1825	PVM pVM = PDMDevHlpGetVM(pDevIns);
1826	Assert(pVM);
1827
1828	/*
1829	* Set the start addresses.
1830	*/
1831	pGlobals->uPciBiosIo = 0xd000;
1832	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
1833	pGlobals->uBus = 0;
1834
1835	/*
1836	* Assign bridge topology, for further routing to work.
1837	*/
1838	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1839	ich9pciInitBridgeTopology(pGlobals, pBus);
1840
1841	/*
1842	* Init the devices.
1843	*/
1844	for (int i = 0; i < 256; i++)
1845	{
1846	ich9pciBiosInitDevice(pGlobals, 0, i);
1847	}
1848
1849	return VINF_SUCCESS;
1850	}
1851
1852	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len)
1853	{
1854	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1855	{
1856	LogRel(("Read from extended register %d fallen back to generic code\n",
1857	u32Address));
1858	return 0;
1859	}
1860
1861	AssertMsgReturn(u32Address + len <= 256, ("Read after the end of PCI config space\n"),
1862	0);
1863	if ( pciDevIsMsiCapable(aDev)
1864	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1865	&& (u32Address < (unsigned)(aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize))
1866	)
1867	{
1868	return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1869	}
1870
1871	if ( pciDevIsMsixCapable(aDev)
1872	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
1873	&& (u32Address < (unsigned)(aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize))
1874	)
1875	{
1876	return MsixPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1877	}
1878
1879	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
1880	0);
1881	switch (len)
1882	{
1883	case 1:
1884	return PCIDevGetByte(aDev, u32Address);
1885	case 2:
1886	return PCIDevGetWord(aDev, u32Address);
1887	case 4:
1888	return PCIDevGetDWord(aDev, u32Address);
1889	default:
1890	Assert(false);
1891	return 0;
1892	}
1893	}
1894
1895	DECLINLINE(void) ich9pciWriteBarByte(PCIDevice *aDev, int iRegion, int iOffset, uint8_t u8Val)
1896	{
1897	PCIIORegion * pRegion = &aDev->Int.s.aIORegions[iRegion];
1898	int64_t iRegionSize = pRegion->size;
1899
1900	Log3(("ich9pciWriteBarByte: region=%d off=%d val=%x size=%d\n",
1901	iRegion, iOffset, u8Val, iRegionSize));
1902
1903	if (iOffset > 3)
1904	Assert((aDev->Int.s.aIORegions[iRegion].type & PCI_ADDRESS_SPACE_BAR64) != 0);
1905
1906	/* Check if we're writing to upper part of 64-bit BAR. */
1907	if (aDev->Int.s.aIORegions[iRegion].type == 0xff)
1908	{
1909	ich9pciWriteBarByte(aDev, iRegion-1, iOffset+4, u8Val);
1910	return;
1911	}
1912
1913	/* Region doesn't exist */
1914	if (iRegionSize == 0)
1915	return;
1916
1917	uint32_t uAddr = ich9pciGetRegionReg(iRegion) + iOffset;
1918	/* Region size must be power of two */
1919	Assert((iRegionSize & (iRegionSize - 1)) == 0);
1920	uint8_t uMask = ((iRegionSize - 1) >> (iOffset*8) ) & 0xff;
1921
1922	if (iOffset == 0)
1923	{
1924	uMask \|= (pRegion->type & PCI_ADDRESS_SPACE_IO) ?
1925	(1 << 2) - 1 /* 2 lowest bits for IO region */ :
1926	(1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
1927
1928	}
1929
1930	uint8_t u8Old = PCIDevGetByte(aDev, uAddr) & uMask;
1931	u8Val = (u8Old & uMask) \| (u8Val & ~uMask);
1932
1933	Log3(("ich9pciWriteBarByte: was %x writing %x\n", u8Old, u8Val));
1934
1935	PCIDevSetByte(aDev, uAddr, u8Val);
1936	}
1937
1938	/**
1939	* See paragraph 7.5 of PCI Express specification (p. 349) for definition of
1940	* registers and their writability policy.
1941	*/
1942	static DECLCALLBACK(void) ich9pciConfigWriteDev(PCIDevice *aDev, uint32_t u32Address,
1943	uint32_t val, unsigned len)
1944	{
1945	Assert(len <= 4);
1946
1947	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1948	{
1949	LogRel(("Write to extended register %d fallen back to generic code\n",
1950	u32Address));
1951	return;
1952	}
1953
1954	AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
1955
1956	if ( pciDevIsMsiCapable(aDev)
1957	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1958	&& (u32Address < (unsigned)(aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize))
1959	)
1960	{
1961	MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1962	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1963	aDev, u32Address, val, len);
1964	return;
1965	}
1966
1967	if ( pciDevIsMsixCapable(aDev)
1968	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
1969	&& (u32Address < (unsigned)(aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize))
1970	)
1971	{
1972	MsixPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1973	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1974	aDev, u32Address, val, len);
1975	return;
1976	}
1977
1978	uint32_t addr = u32Address;
1979	bool fUpdateMappings = false;
1980	bool fP2PBridge = false;
1981	/bool fPassthrough = pciDevIsPassthrough(aDev);/
1982	uint8_t u8HeaderType = ich9pciGetByte(aDev, VBOX_PCI_HEADER_TYPE);
1983
1984	for (uint32_t i = 0; i < len; i++)
1985	{
1986	bool fWritable = false;
1987	bool fRom = false;
1988	switch (u8HeaderType)
1989	{
1990	case 0x00: /* normal device */
1991	case 0x80: /* multi-function device */
1992	switch (addr)
1993	{
1994	/* Read-only registers */
1995	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1996	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1997	case VBOX_PCI_REVISION_ID:
1998	case VBOX_PCI_CLASS_PROG:
1999	case VBOX_PCI_CLASS_SUB:
2000	case VBOX_PCI_CLASS_BASE:
2001	case VBOX_PCI_HEADER_TYPE:
2002	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
2003	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
2004	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
2005	case VBOX_PCI_CAPABILITY_LIST:
2006	case VBOX_PCI_INTERRUPT_PIN:
2007	fWritable = false;
2008	break;
2009	/* Others can be written */
2010	default:
2011	fWritable = true;
2012	break;
2013	}
2014	break;
2015	case 0x01: /* PCI-PCI bridge */
2016	fP2PBridge = true;
2017	switch (addr)
2018	{
2019	/* Read-only registers */
2020	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2021	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2022	case VBOX_PCI_REVISION_ID:
2023	case VBOX_PCI_CLASS_PROG:
2024	case VBOX_PCI_CLASS_SUB:
2025	case VBOX_PCI_CLASS_BASE:
2026	case VBOX_PCI_HEADER_TYPE:
2027	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
2028	case VBOX_PCI_INTERRUPT_PIN:
2029	fWritable = false;
2030	break;
2031	default:
2032	fWritable = true;
2033	break;
2034	}
2035	break;
2036	default:
2037	AssertMsgFailed(("Unknown header type %x\n", PCIDevGetHeaderType(aDev)));
2038	fWritable = false;
2039	break;
2040	}
2041
2042	uint8_t u8Val = (uint8_t)val;
2043	switch (addr)
2044	{
2045	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
2046	fUpdateMappings = true;
2047	goto default_case;
2048	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
2049	/* don't change reserved bits (11-15) */
2050	u8Val &= UINT32_C(~0xf8);
2051	fUpdateMappings = true;
2052	goto default_case;
2053	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
2054	/* don't change read-only bits => actually all lower bits are read-only */
2055	u8Val &= UINT32_C(~0xff);
2056	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
2057	aDev->config[addr] &= ~u8Val;
2058	break;
2059	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
2060	/* don't change read-only bits */
2061	u8Val &= UINT32_C(~0x06);
2062	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
2063	aDev->config[addr] &= ~u8Val;
2064	break;
2065	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3:
2066	fRom = true;
2067	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
2068	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
2069	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
2070	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
2071	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
2072	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
2073	{
2074	/* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
2075	if (fP2PBridge)
2076	goto default_case;
2077	else
2078	{
2079	int iRegion = fRom ? VBOX_PCI_ROM_SLOT : (addr - VBOX_PCI_BASE_ADDRESS_0) >> 2;
2080	int iOffset = addr & 0x3;
2081	ich9pciWriteBarByte(aDev, iRegion, iOffset, u8Val);
2082	fUpdateMappings = true;
2083	}
2084	break;
2085	}
2086	default:
2087	default_case:
2088	if (fWritable)
2089	PCIDevSetByte(aDev, addr, u8Val);
2090	}
2091	addr++;
2092	val >>= 8;
2093	}
2094
2095	if (fUpdateMappings)
2096	/* if the command/base address register is modified, we must modify the mappings */
2097	ich9pciUpdateMappings(aDev);
2098	}
2099
2100	static bool assignPosition(PICH9PCIBUS pBus, PPCIDEVICE pPciDev, const char pszName, int iDevFn, PciAddress aPosition)
2101	{
2102	NOREF(pszName);
2103	aPosition->iBus = 0;
2104	aPosition->iDeviceFunc = iDevFn;
2105	aPosition->iRegister = 0; /* N/A */
2106
2107	/* Explicit slot request */
2108	if (iDevFn >= 0 && iDevFn < (int)RT_ELEMENTS(pBus->apDevices))
2109	return true;
2110
2111	int iStartPos = 0;
2112
2113	/* Otherwise when assigning a slot, we need to make sure all its functions are available */
2114	for (int iPos = iStartPos; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
2115	{
2116	if ( !pBus->apDevices[iPos]
2117	&& !pBus->apDevices[iPos + 1]
2118	&& !pBus->apDevices[iPos + 2]
2119	&& !pBus->apDevices[iPos + 3]
2120	&& !pBus->apDevices[iPos + 4]
2121	&& !pBus->apDevices[iPos + 5]
2122	&& !pBus->apDevices[iPos + 6]
2123	&& !pBus->apDevices[iPos + 7])
2124	{
2125	pciDevClearRequestedDevfunc(pPciDev);
2126	aPosition->iDeviceFunc = iPos;
2127	return true;
2128	}
2129	}
2130
2131	return false;
2132	}
2133
2134	#ifdef SOME_UNUSED_FUNCTION
2135	static bool hasHardAssignedDevsInSlot(PICH9PCIBUS pBus, int iSlot)
2136	{
2137	PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
2138
2139	return (aSlot[0] && pciDevIsRequestedDevfunc(aSlot[0]))
2140	\|\| (aSlot[1] && pciDevIsRequestedDevfunc(aSlot[1]))
2141	\|\| (aSlot[2] && pciDevIsRequestedDevfunc(aSlot[2]))
2142	\|\| (aSlot[3] && pciDevIsRequestedDevfunc(aSlot[3]))
2143	\|\| (aSlot[4] && pciDevIsRequestedDevfunc(aSlot[4]))
2144	\|\| (aSlot[5] && pciDevIsRequestedDevfunc(aSlot[5]))
2145	\|\| (aSlot[6] && pciDevIsRequestedDevfunc(aSlot[6]))
2146	\|\| (aSlot[7] && pciDevIsRequestedDevfunc(aSlot[7]))
2147	;
2148	}
2149	#endif
2150
2151	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
2152	{
2153	PciAddress aPosition = {0, 0, 0};
2154
2155	/*
2156	* Find device position
2157	*/
2158	if (!assignPosition(pBus, pPciDev, pszName, iDev, &aPosition))
2159	{
2160	AssertMsgFailed(("Couldn't asssign position!\n"));
2161	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2162	}
2163
2164	AssertMsgReturn(aPosition.iBus == 0,
2165	("Assigning behind the bridge not implemented yet\n"),
2166	VERR_PDM_TOO_PCI_MANY_DEVICES);
2167
2168
2169	iDev = aPosition.iDeviceFunc;
2170	/*
2171	* Check if we can really take this slot, possibly by relocating
2172	* its current habitant, if it wasn't hard assigned too.
2173	*/
2174	if (pciDevIsRequestedDevfunc(pPciDev) &&
2175	pBus->apDevices[iDev] &&
2176	pciDevIsRequestedDevfunc(pBus->apDevices[iDev]))
2177	{
2178	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
2179	pszName, pBus->apDevices[iDev]->name, iDev));
2180	return VERR_INTERNAL_ERROR;
2181	}
2182
2183	if (pBus->apDevices[iDev])
2184	{
2185	/* if we got here, we shall (and usually can) relocate the device */
2186	bool assigned = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name, -1, &aPosition);
2187	AssertMsgReturn(aPosition.iBus == 0,
2188	("Assigning behind the bridge not implemented yet\n"),
2189	VERR_PDM_TOO_PCI_MANY_DEVICES);
2190	int iRelDev = aPosition.iDeviceFunc;
2191	if (!assigned \|\| iRelDev == iDev)
2192	{
2193	AssertMsgFailed(("Couldn't find free spot!\n"));
2194	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2195	}
2196	/* Copy device function by function to its new position */
2197	for (int i = 0; i < 8; i++)
2198	{
2199	if (!pBus->apDevices[iDev + i])
2200	continue;
2201	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
2202	pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
2203	pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
2204	pBus->apDevices[iDev + i] = NULL;
2205	}
2206	}
2207
2208	/*
2209	* Fill in device information.
2210	*/
2211	pPciDev->devfn = iDev;
2212	pPciDev->name = pszName;
2213	pPciDev->Int.s.pBusR3 = pBus;
2214	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2215	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2216	pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
2217	pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
2218	pBus->apDevices[iDev] = pPciDev;
2219	if (pciDevIsPci2PciBridge(pPciDev))
2220	{
2221	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2222	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2223	("device is a bridge but does not implement read/write functions\n"));
2224	Log2(("Setting bridge %d on bus %p\n", pBus->cBridges, pBus));
2225	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2226	pBus->cBridges++;
2227	}
2228
2229	Log(("PCI: Registered device %d function %d on bus %d (%#x) '%s'.\n",
2230	iDev >> 3, iDev & 7, pBus->iBus, 0x80000000 \| (iDev << 8), pszName));
2231
2232	return VINF_SUCCESS;
2233	}
2234
2235	static void printIndent(PCDBGFINFOHLP pHlp, int iIndent)
2236	{
2237	for (int i = 0; i < iIndent; i++)
2238	{
2239	pHlp->pfnPrintf(pHlp, " ");
2240	}
2241	}
2242
2243	static void ich9pciBusInfo(PICH9PCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
2244	{
2245	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2246	{
2247	PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2248	if (pPciDev != NULL)
2249	{
2250	printIndent(pHlp, iIndent);
2251
2252	/*
2253	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2254	* as host driver handles real devices interrupts.
2255	*/
2256	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x%s%s",
2257	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2258	pPciDev->name,
2259	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2260	ich9pciGetWord(pPciDev, VBOX_PCI_VENDOR_ID), ich9pciGetWord(pPciDev, VBOX_PCI_DEVICE_ID),
2261	pciDevIsMsiCapable(pPciDev) ? " MSI" : "",
2262	pciDevIsMsixCapable(pPciDev) ? " MSI-X" : ""
2263	);
2264	if (ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2265	pHlp->pfnPrintf(pHlp, " IRQ%d", ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2266
2267	pHlp->pfnPrintf(pHlp, "\n");
2268
2269	int iCmd = ich9pciGetWord(pPciDev, VBOX_PCI_COMMAND);
2270	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
2271	{
2272	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2273	{
2274	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2275	int32_t iRegionSize = pRegion->size;
2276
2277	if (iRegionSize == 0)
2278	continue;
2279
2280	uint32_t u32Addr = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion));
2281	const char * pszDesc;
2282	char szDescBuf[128];
2283
2284	bool f64Bit = !!(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
2285	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2286	{
2287	pszDesc = "IO";
2288	u32Addr &= ~0x3;
2289	}
2290	else
2291	{
2292	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2293	f64Bit ? "64" : "32",
2294	(pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
2295	pszDesc = szDescBuf;
2296	u32Addr &= ~0xf;
2297	}
2298
2299	printIndent(pHlp, iIndent + 2);
2300	pHlp->pfnPrintf(pHlp, " %s region #%d: %x..%x\n",
2301	pszDesc, iRegion, u32Addr, u32Addr+iRegionSize);
2302	if (f64Bit)
2303	iRegion++;
2304	}
2305	}
2306
2307	if (fRegisters)
2308	{
2309	printIndent(pHlp, iIndent + 2);
2310	pHlp->pfnPrintf(pHlp, " PCI registers:\n");
2311	for (int iReg = 0; iReg < 0x100; )
2312	{
2313	int iPerLine = 0x10;
2314	Assert (0x100 % iPerLine == 0);
2315	printIndent(pHlp, iIndent + 3);
2316
2317	while (iPerLine-- > 0)
2318	{
2319	pHlp->pfnPrintf(pHlp, "%02x ", ich9pciGetByte(pPciDev, iReg++));
2320	}
2321	pHlp->pfnPrintf(pHlp, "\n");
2322	}
2323	}
2324	}
2325	}
2326
2327	if (pBus->cBridges > 0)
2328	{
2329	printIndent(pHlp, iIndent);
2330	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2331	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2332	{
2333	PICH9PCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PICH9PCIBUS);
2334	ich9pciBusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2335	}
2336	}
2337	}
2338
2339	/**
2340	* Info handler, device version.
2341	*
2342	* @param pDevIns Device instance which registered the info.
2343	* @param pHlp Callback functions for doing output.
2344	* @param pszArgs Argument string. Optional and specific to the handler.
2345	*/
2346	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2347	{
2348	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2349
2350	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2351	{
2352	ich9pciBusInfo(pBus, pHlp, 0, false);
2353	}
2354	else if (!strcmp(pszArgs, "verbose"))
2355	{
2356	ich9pciBusInfo(pBus, pHlp, 0, true);
2357	}
2358	else
2359	{
2360	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2361	}
2362	}
2363
2364
2365	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns,
2366	int iInstance,
2367	PCFGMNODE pCfg)
2368	{
2369	Assert(iInstance == 0);
2370	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2371
2372	/*
2373	* Validate and read configuration.
2374	*/
2375	if (!CFGMR3AreValuesValid(pCfg,
2376	"IOAPIC\0"
2377	"GCEnabled\0"
2378	"R0Enabled\0"
2379	"McfgBase\0"
2380	"McfgLength\0"
2381	))
2382	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2383
2384	/* query whether we got an IOAPIC */
2385	bool fUseIoApic;
2386	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2387	if (RT_FAILURE(rc))
2388	return PDMDEV_SET_ERROR(pDevIns, rc,
2389	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2390
2391	/* check if RC code is enabled. */
2392	bool fGCEnabled;
2393	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2394	if (RT_FAILURE(rc))
2395	return PDMDEV_SET_ERROR(pDevIns, rc,
2396	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2397	/* check if R0 code is enabled. */
2398	bool fR0Enabled;
2399	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2400	if (RT_FAILURE(rc))
2401	return PDMDEV_SET_ERROR(pDevIns, rc,
2402	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2403
2404	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2405
2406	/*
2407	* Init data.
2408	*/
2409	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2410	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2411	/* Zero out everything */
2412	memset(pGlobals, 0, sizeof(*pGlobals));
2413	/* And fill values */
2414	if (!fUseIoApic)
2415	return PDMDEV_SET_ERROR(pDevIns, rc,
2416	N_("Must use IO-APIC with ICH9 chipset"));
2417	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2418	if (RT_FAILURE(rc))
2419	return PDMDEV_SET_ERROR(pDevIns, rc,
2420	N_("Configuration error: Failed to read \"McfgBase\""));
2421	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2422	if (RT_FAILURE(rc))
2423	return PDMDEV_SET_ERROR(pDevIns, rc,
2424	N_("Configuration error: Failed to read \"McfgLength\""));
2425
2426	pGlobals->pDevInsR3 = pDevIns;
2427	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2428	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2429
2430	pGlobals->aPciBus.pDevInsR3 = pDevIns;
2431	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2432	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2433	pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2434
2435	/*
2436	* Register bus
2437	*/
2438	PDMPCIBUSREG PciBusReg;
2439	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2440	PciBusReg.pfnRegisterR3 = ich9pciRegister;
2441	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2442	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2443	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2444	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2445	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2446	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2447	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2448	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2449	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2450	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2451	if (RT_FAILURE(rc))
2452	return PDMDEV_SET_ERROR(pDevIns, rc,
2453	N_("Failed to register ourselves as a PCI Bus"));
2454	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2455	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2456	N_("PCI helper version mismatch; got %#x expected %#x"),
2457	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2458
2459	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2460	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2461
2462	/*
2463	* Fill in PCI configs and add them to the bus.
2464	*/
2465	/** @todo: Disabled for now because this causes error messages with Linux guests.
2466	* The guest loads the x38_edac device which tries to map a memory region
2467	* using an address given at place 0x48 - 0x4f in the PCi config space.
2468	* This fails. because we don't register such a region.
2469	*/
2470	#if 0
2471	/* Host bridge device */
2472	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2473	PCIDevSetDeviceId( &pBus->aPciDev, 0x29e0); /* Desktop */
2474	PCIDevSetRevisionId(&pBus->aPciDev, 0x01); /* rev. 01 */
2475	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2476	PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2477	PCIDevSetClassProg( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2478	PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* bridge */
2479	PCIDevSetWord(&pBus->aPciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
2480
2481	pBus->aPciDev.pDevIns = pDevIns;
2482	/* We register Host<->PCI controller on the bus */
2483	ich9pciRegisterInternal(pBus, 0, &pBus->aPciDev, "dram");
2484	#endif
2485
2486	/*
2487	* Register I/O ports and save state.
2488	*/
2489	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2490	if (RT_FAILURE(rc))
2491	return rc;
2492	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2493	if (RT_FAILURE(rc))
2494	return rc;
2495	if (fGCEnabled)
2496	{
2497	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2498	if (RT_FAILURE(rc))
2499	return rc;
2500	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2501	if (RT_FAILURE(rc))
2502	return rc;
2503	}
2504	if (fR0Enabled)
2505	{
2506	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2507	if (RT_FAILURE(rc))
2508	return rc;
2509	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2510	if (RT_FAILURE(rc))
2511	return rc;
2512	}
2513
2514	if (pGlobals->u64PciConfigMMioAddress != 0)
2515	{
2516	rc = PDMDevHlpMMIORegister(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength, NULL /pvUser/,
2517	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
2518	ich9pciMcfgMMIOWrite, ich9pciMcfgMMIORead, "MCFG ranges");
2519	AssertMsgRCReturn(rc, ("rc=%Rrc %#llx/%#llx\n", rc, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength), rc);
2520
2521	if (fGCEnabled)
2522	{
2523	rc = PDMDevHlpMMIORegisterRC(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2524	NIL_RTRCPTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2525	AssertRCReturn(rc, rc);
2526	}
2527
2528
2529	if (fR0Enabled)
2530	{
2531	rc = PDMDevHlpMMIORegisterR0(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2532	NIL_RTR0PTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2533	AssertRCReturn(rc, rc);
2534	}
2535	}
2536
2537	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2538	sizeof(pBus) + 16128, "pgm",
2539	NULL, NULL, NULL,
2540	NULL, ich9pciR3SaveExec, NULL,
2541	NULL, ich9pciR3LoadExec, NULL);
2542	if (RT_FAILURE(rc))
2543	return rc;
2544
2545
2546	/** @todo: other chipset devices shall be registered too */
2547
2548	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. Recognizes 'basic' or 'verbose' "
2549	"as arguments, defaults to 'basic'.", ich9pciInfo);
2550
2551	return VINF_SUCCESS;
2552	}
2553
2554	static void ich9pciResetDevice(PPCIDEVICE pDev)
2555	{
2556	/* Clear regions */
2557	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2558	{
2559	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
2560	if (pRegion->size == 0)
2561	continue;
2562
2563	ich9pciUnmapRegion(pDev, iRegion);
2564	}
2565
2566	if (pciDevIsPassthrough(pDev))
2567	{
2568	// no reset handler - we can do what we need in PDM reset handler
2569	// @todo: is it correct?
2570	}
2571	else
2572	{
2573	PCIDevSetCommand(pDev,
2574	PCIDevGetCommand(pDev)
2575	&
2576	~(VBOX_PCI_COMMAND_IO \|
2577	VBOX_PCI_COMMAND_MEMORY \|
2578	VBOX_PCI_COMMAND_MASTER));
2579
2580	/* Bridge device reset handlers processed later */
2581	if (!pciDevIsPci2PciBridge(pDev))
2582	{
2583	PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2584	PCIDevSetInterruptLine(pDev, 0x0);
2585	}
2586	}
2587	}
2588
2589
2590	/**
2591	* @copydoc FNPDMDEVRESET
2592	*/
2593	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2594	{
2595	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2596	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2597
2598	/* PCI-specific reset for each device. */
2599	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2600	{
2601	if (pBus->apDevices[i])
2602	ich9pciResetDevice(pBus->apDevices[i]);
2603	}
2604
2605	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2606	{
2607	if (pBus->papBridgesR3[iBridge])
2608	ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->pDevIns);
2609	}
2610
2611	ich9pciFakePCIBIOS(pDevIns);
2612	}
2613
2614	static void ich9pciRelocateDevice(PPCIDEVICE pDev, RTGCINTPTR offDelta)
2615	{
2616	if (pDev)
2617	{
2618	pDev->Int.s.pBusRC += offDelta;
2619	if (pDev->Int.s.pMsixPageRC)
2620	pDev->Int.s.pMsixPageRC += offDelta;
2621	}
2622	}
2623
2624	/**
2625	* @copydoc FNPDMDEVRELOCATE
2626	*/
2627	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2628	{
2629	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2630	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2631	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2632
2633	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2634	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2635
2636	/* Relocate RC pointers for the attached pci devices. */
2637	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2638	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2639
2640	}
2641
2642	/**
2643	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2644	*/
2645	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2646	int iInstance,
2647	PCFGMNODE pCfg)
2648	{
2649	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2650
2651	/*
2652	* Validate and read configuration.
2653	*/
2654	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2655	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2656
2657	/* check if RC code is enabled. */
2658	bool fGCEnabled;
2659	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2660	if (RT_FAILURE(rc))
2661	return PDMDEV_SET_ERROR(pDevIns, rc,
2662	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2663
2664	/* check if R0 code is enabled. */
2665	bool fR0Enabled;
2666	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2667	if (RT_FAILURE(rc))
2668	return PDMDEV_SET_ERROR(pDevIns, rc,
2669	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2670	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2671
2672	/*
2673	* Init data and register the PCI bus.
2674	*/
2675	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2676	pBus->pDevInsR3 = pDevIns;
2677	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2678	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2679	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->apDevices));
2680
2681	PDMPCIBUSREG PciBusReg;
2682	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2683	PciBusReg.pfnRegisterR3 = ich9pcibridgeRegister;
2684	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2685	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2686	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2687	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2688	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2689	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2690	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2691	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2692	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2693	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2694	if (RT_FAILURE(rc))
2695	return PDMDEV_SET_ERROR(pDevIns, rc,
2696	N_("Failed to register ourselves as a PCI Bus"));
2697	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2698	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2699	N_("PCI helper version mismatch; got %#x expected %#x"),
2700	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2701
2702	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2703	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2704
2705	/* Disable default device locking. */
2706	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2707	AssertRCReturn(rc, rc);
2708
2709	/*
2710	* Fill in PCI configs and add them to the bus.
2711	*/
2712	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2713	PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2714	PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2715	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2716	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2717	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2718	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2719	PCIDevSetCommand( &pBus->aPciDev, 0x00);
2720	PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2721	PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2722
2723	/*
2724	* This device does not generate interrupts. Interrupt delivery from
2725	* devices attached to the bus is unaffected.
2726	*/
2727	PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2728
2729	pBus->aPciDev.pDevIns = pDevIns;
2730
2731	/* Bridge-specific data */
2732	pciDevSetPci2PciBridge(&pBus->aPciDev);
2733	pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2734	pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2735
2736	/*
2737	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2738	*/
2739	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2740	if (RT_FAILURE(rc))
2741	return rc;
2742
2743	/*
2744	* The iBus property doesn't really represent the bus number
2745	* because the guest and the BIOS can choose different bus numbers
2746	* for them.
2747	* The bus number is mainly for the setIrq function to indicate
2748	* when the host bus is reached which will have iBus = 0.
2749	* That's why the + 1.
2750	*/
2751	pBus->iBus = iInstance + 1;
2752
2753	/*
2754	* Register SSM handlers. We use the same saved state version as for the host bridge
2755	* to make changes easier.
2756	*/
2757	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2758	sizeof(pBus) + 16128,
2759	"pgm" /* before */,
2760	NULL, NULL, NULL,
2761	NULL, ich9pcibridgeR3SaveExec, NULL,
2762	NULL, ich9pcibridgeR3LoadExec, NULL);
2763	if (RT_FAILURE(rc))
2764	return rc;
2765
2766
2767	return VINF_SUCCESS;
2768	}
2769
2770	/**
2771	* @copydoc FNPDMDEVRESET
2772	*/
2773	static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
2774	{
2775	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2776
2777	/* Reset config space to default values. */
2778	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2779	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2780	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2781
2782	/* PCI-specific reset for each device. */
2783	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2784	{
2785	if (pBus->apDevices[i])
2786	ich9pciResetDevice(pBus->apDevices[i]);
2787	}
2788	}
2789
2790
2791	/**
2792	* @copydoc FNPDMDEVRELOCATE
2793	*/
2794	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2795	{
2796	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2797	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2798
2799	/* Relocate RC pointers for the attached pci devices. */
2800	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2801	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2802	}
2803
2804	/**
2805	* The PCI bus device registration structure.
2806	*/
2807	const PDMDEVREG g_DevicePciIch9 =
2808	{
2809	/* u32Version */
2810	PDM_DEVREG_VERSION,
2811	/* szName */
2812	"ich9pci",
2813	/* szRCMod */
2814	"VBoxDDGC.gc",
2815	/* szR0Mod */
2816	"VBoxDDR0.r0",
2817	/* pszDescription */
2818	"ICH9 PCI bridge",
2819	/* fFlags */
2820	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2821	/* fClass */
2822	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2823	/* cMaxInstances */
2824	1,
2825	/* cbInstance */
2826	sizeof(ICH9PCIGLOBALS),
2827	/* pfnConstruct */
2828	ich9pciConstruct,
2829	/* pfnDestruct */
2830	NULL,
2831	/* pfnRelocate */
2832	ich9pciRelocate,
2833	/* pfnIOCtl */
2834	NULL,
2835	/* pfnPowerOn */
2836	NULL,
2837	/* pfnReset */
2838	ich9pciReset,
2839	/* pfnSuspend */
2840	NULL,
2841	/* pfnResume */
2842	NULL,
2843	/* pfnAttach */
2844	NULL,
2845	/* pfnDetach */
2846	NULL,
2847	/* pfnQueryInterface */
2848	NULL,
2849	/* pfnInitComplete */
2850	NULL,
2851	/* pfnPowerOff */
2852	NULL,
2853	/* pfnSoftReset */
2854	NULL,
2855	/* u32VersionEnd */
2856	PDM_DEVREG_VERSION
2857	};
2858
2859	/**
2860	* The device registration structure
2861	* for the PCI-to-PCI bridge.
2862	*/
2863	const PDMDEVREG g_DevicePciIch9Bridge =
2864	{
2865	/* u32Version */
2866	PDM_DEVREG_VERSION,
2867	/* szName */
2868	"ich9pcibridge",
2869	/* szRCMod */
2870	"VBoxDDGC.gc",
2871	/* szR0Mod */
2872	"VBoxDDR0.r0",
2873	/* pszDescription */
2874	"ICH9 PCI to PCI bridge",
2875	/* fFlags */
2876	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2877	/* fClass */
2878	PDM_DEVREG_CLASS_BUS_PCI,
2879	/* cMaxInstances */
2880	~0U,
2881	/* cbInstance */
2882	sizeof(ICH9PCIBUS),
2883	/* pfnConstruct */
2884	ich9pcibridgeConstruct,
2885	/* pfnDestruct */
2886	NULL,
2887	/* pfnRelocate */
2888	ich9pcibridgeRelocate,
2889	/* pfnIOCtl */
2890	NULL,
2891	/* pfnPowerOn */
2892	NULL,
2893	/* pfnReset */
2894	NULL, /* Must be NULL, to make sure only bus driver handles reset */
2895	/* pfnSuspend */
2896	NULL,
2897	/* pfnResume */
2898	NULL,
2899	/* pfnAttach */
2900	NULL,
2901	/* pfnDetach */
2902	NULL,
2903	/* pfnQueryInterface */
2904	NULL,
2905	/* pfnInitComplete */
2906	NULL,
2907	/* pfnPowerOff */
2908	NULL,
2909	/* pfnSoftReset */
2910	NULL,
2911	/* u32VersionEnd */
2912	PDM_DEVREG_VERSION
2913	};
2914
2915	#endif /* IN_RING3 */
2916	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 40894

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