DevPciGenericEcam.cpp@ 106129

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1	/* $Id: DevPciGenericEcam.cpp 106061 2024-09-16 14:03:52Z vboxsync $ */
2	/** @file
3	* DevPciGeneric - Generic host to PCIe bridge emulation.
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_DEV_PCI
33	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
34	#include <VBox/vmm/pdmpcidev.h>
35
36	#include <VBox/AssertGuest.h>
37	#include <VBox/msi.h>
38	#include <VBox/vmm/pdmdev.h>
39	#include <VBox/vmm/mm.h>
40	#include <iprt/asm.h>
41	#include <iprt/assert.h>
42	#include <iprt/string.h>
43	#ifdef IN_RING3
44	# include <iprt/mem.h>
45	# include <iprt/uuid.h>
46	#endif
47
48	#include "PciInline.h"
49	#include "VBoxDD.h"
50	#include "MsiCommon.h"
51	#include "DevPciInternal.h"
52
53
54	/*********************************************************************************************************************************
55	* Structures and Typedefs *
56	*********************************************************************************************************************************/
57
58
59	/*********************************************************************************************************************************
60	* Defined Constants And Macros *
61	*********************************************************************************************************************************/
62	/** @todo As this shares a lot of code with the ICH9 PCI device we have to also keep the saved state version in sync. */
63	/** Saved state version of the generic ECAM PCI bus device. */
64	#define VBOX_PCIGENECAM_SAVED_STATE_VERSION VBOX_ICH9PCI_SAVED_STATE_VERSION_4KB_CFG_SPACE
65	/** 4KB config space */
66	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_4KB_CFG_SPACE 4
67
68
69	/*********************************************************************************************************************************
70	* Internal Functions *
71	*********************************************************************************************************************************/
72
73	/**
74	* Returns the interrupt pin for a given device slot on the root port
75	* due to swizzeling.
76	*
77	* @returns Interrupt pin on the root port.
78	* @param uDevFn The device.
79	* @param uPin The interrupt pin on the device.
80	*/
81	DECLINLINE(uint8_t) pciGenEcamGetPirq(uint8_t uDevFn, uint8_t uPin)
82	{
83	uint8_t uSlot = (uDevFn >> 3) - 1;
84	return (uPin + uSlot) & 3;
85	}
86
87
88	/**
89	* Returns whether the interrupt line is asserted on the PCI root for the given pin.
90	*
91	* @returns Flag whther the interrupt line is asserted (true) or not (false).
92	* @param pPciRoot The PCI root bus.
93	* @param u8IrqPin The IRQ pin being checked.
94	*/
95	DECLINLINE(bool) pciGenEcamGetIrqLvl(PDEVPCIROOT pPciRoot, uint8_t u8IrqPin)
96	{
97	return (pPciRoot->u.GenericEcam.auPciIrqLevels[u8IrqPin] != 0);
98	}
99
100
101	/**
102	* Internal IRQ update worker for the root bus and bridges.
103	*
104	* @param pDevIns The PDM device instance updating the interrupt.
105	* @param pPciRoot The PCI root bus.
106	* @param pBusCC Current context PCI bus data.
107	* @param uDevFn Device and function number of the device/bridge updating the interrupt on the root bus.
108	* @param pPciDev The PCI device data of the device updating the interrupt.
109	* @param iIrq The interrupt number or MSI message.
110	* @param iLevel The level of the interrupt.
111	* @param uTagSrc The source tag of the interrupt.
112	*/
113	static void pciGenEcamSetIrqInternal(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUSCC pBusCC,
114	uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
115	{
116	PDEVPCIBUS pBus = &pPciRoot->PciBus;
117	uint16_t const uBusDevFn = PCIBDF_MAKE(pBus->iBus, uDevFn);
118
119	/* If MSI or MSI-X is enabled, PCI INTx# signals are disabled regardless of the PCI command
120	* register interrupt bit state.
121	* PCI 3.0 (section 6.8) forbids MSI and MSI-X to be enabled at the same time and makes
122	* that undefined behavior. We check for MSI first, then MSI-X.
123	*/
124	if (MsiIsEnabled(pPciDev))
125	{
126	Assert(!MsixIsEnabled(pPciDev)); /* Not allowed -- see note above. */
127	LogFlowFunc(("PCI Dev %p : MSI\n", pPciDev));
128	MsiNotify(pDevIns, pBusCC->CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
129	return;
130	}
131
132	if (MsixIsEnabled(pPciDev))
133	{
134	LogFlowFunc(("PCI Dev %p : MSI-X\n", pPciDev));
135	MsixNotify(pDevIns, pBusCC->CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
136	return;
137	}
138
139	LogFlowFunc(("PCI Dev %p : IRQ\n", pPciDev));
140
141	/* Check if the state changed. */
142	if (pPciDev->Int.s.uIrqPinState != iLevel)
143	{
144	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
145
146	/* Get the pin. */
147	uint8_t uIrqPin = devpciR3GetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN);
148	uint8_t uIrq = pciGenEcamGetPirq(pPciDev->uDevFn, uIrqPin);
149
150	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
151	ASMAtomicIncU32(&pPciRoot->u.GenericEcam.auPciIrqLevels[uIrq]);
152	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
153	ASMAtomicDecU32(&pPciRoot->u.GenericEcam.auPciIrqLevels[uIrq]);
154
155	bool fIrqLvl = pciGenEcamGetIrqLvl(pPciRoot, uIrq);
156	uint32_t u32IrqNr = pPciRoot->u.GenericEcam.auPciIrqNr[uIrq];
157
158	Log3Func(("%s: uIrqPin=%u uIrqRoot=%u fIrqLvl=%RTbool uIrqNr=%u\n",
159	R3STRING(pPciDev->pszNameR3), uIrqPin, uIrq, fIrqLvl, u32IrqNr));
160	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, u32IrqNr, fIrqLvl, uTagSrc);
161
162	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
163	ASMAtomicDecU32(&pPciRoot->u.GenericEcam.auPciIrqLevels[uIrq]);
164	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
165	fIrqLvl = pciGenEcamGetIrqLvl(pPciRoot, uIrq);
166	Log3Func(("%s: uIrqPin=%u uIrqRoot=%u fIrqLvl=%RTbool uIrqNr=%u\n",
167	R3STRING(pPciDev->pszNameR3), uIrqPin, uIrq, fIrqLvl, u32IrqNr));
168	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, u32IrqNr, fIrqLvl, uTagSrc);
169	}
170	}
171	}
172
173
174	/**
175	* @interface_method_impl{PDMPCIBUSREGCC,pfnSetIrqR3}
176	*/
177	static DECLCALLBACK(void) pciGenEcamSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
178	{
179	LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
180	pciGenEcamSetIrqInternal(pDevIns, PDMINS_2_DATA(pDevIns, PDEVPCIROOT), PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
181	pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
182	}
183
184
185	static DECLCALLBACK(void) pciGenEcamBridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
186	{
187	/*
188	* The PCI-to-PCI bridge specification defines how the interrupt pins
189	* are routed from the secondary to the primary bus (see chapter 9).
190	* iIrq gives the interrupt pin the pci device asserted.
191	* We change iIrq here according to the spec and call the SetIrq function
192	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
193	*
194	* See ich9pciBiosInitAllDevicesOnBus for corresponding configuration code.
195	*/
196	PDEVPCIBUS pBus;
197	uint8_t uDevFnBridge;
198	int iIrqPinBridge;
199	PPDMDEVINS pDevInsBus = devpcibridgeCommonSetIrqRootWalk(pDevIns, pPciDev, iIrq, &pBus, &uDevFnBridge, &iIrqPinBridge);
200	AssertReturnVoid(pDevInsBus);
201	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
202	Assert(pDevInsBus->pReg == &g_DevicePciGenericEcam); /* ASSUMPTION: Same style root bus. Need callback interface to mix types. */
203
204	/*
205	* For MSI/MSI-X enabled devices the iIrq doesn't denote the pin but rather a vector which is completely
206	* orthogonal to the pin based approach. The vector is not subject to the pin based routing with PCI bridges.
207	*/
208	int iIrqPinVector = iIrqPinBridge;
209	if ( MsiIsEnabled(pPciDev)
210	\|\| MsixIsEnabled(pPciDev))
211	iIrqPinVector = iIrq;
212	pciGenEcamSetIrqInternal(pDevIns, DEVPCIBUS_2_DEVPCIROOT(pBus), PDMINS_2_DATA_CC(pDevInsBus, PDEVPCIBUSCC),
213	uDevFnBridge, pPciDev, iIrqPinVector, iLevel, uTagSrc);
214	}
215
216
217	/**
218	* @callback_method_impl{FNIOMMMIONEWWRITE,
219	* Emulates writes to PIO space.}
220	*/
221	static DECLCALLBACK(VBOXSTRICTRC) pciHostR3MmioPioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
222	{
223	Log2Func(("%RGp LB %d\n", off, cb));
224	RT_NOREF(pvUser);
225
226	AssertReturn(off < _64K, VERR_INVALID_PARAMETER);
227	AssertReturn(cb <= 4, VERR_INVALID_PARAMETER);
228
229	/* Get the value. */
230	uint32_t u32;
231	switch (cb)
232	{
233	case 1:
234	u32 = (uint8_t const )pv;
235	break;
236	case 2:
237	u32 = (uint16_t const )pv;
238	break;
239	case 4:
240	u32 = (uint32_t const )pv;
241	break;
242	default:
243	ASSERT_GUEST_MSG_FAILED(("cb=%u off=%RGp\n", cb, off)); /** @todo how the heck should this work? Split it, right? */
244	u32 = 0;
245	break;
246	}
247
248	return PDMDevHlpIoPortWrite(pDevIns, (RTIOPORT)off, u32, cb);
249	}
250
251
252	/**
253	* @callback_method_impl{FNIOMMMIONEWWRITE,
254	* Emulates reads from PIO space.}
255	*/
256	static DECLCALLBACK(VBOXSTRICTRC) pciHostR3MmioPioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
257	{
258	LogFlowFunc(("%RGp LB %u\n", off, cb));
259	RT_NOREF(pvUser);
260
261	AssertReturn(off < _64K, VERR_INVALID_PARAMETER);
262	AssertReturn(cb <= 4, VERR_INVALID_PARAMETER);
263
264	/* Perform PIO space read */
265	uint32_t u32Value = 0;
266	VBOXSTRICTRC rcStrict = PDMDevHlpIoPortRead(pDevIns, (RTIOPORT)off, &u32Value, cb);
267
268	if (RT_SUCCESS(rcStrict))
269	{
270	switch (cb)
271	{
272	case 1:
273	(uint8_t )pv = (uint8_t)u32Value;
274	break;
275	case 2:
276	(uint16_t )pv = (uint16_t)u32Value;
277	break;
278	case 4:
279	(uint32_t )pv = u32Value;
280	break;
281	default:
282	ASSERT_GUEST_MSG_FAILED(("cb=%u off=%RGp\n", cb, off)); /** @todo how the heck should this work? Split it, right? */
283	break;
284	}
285	}
286
287	return rcStrict;
288	}
289
290
291	#ifdef IN_RING3
292
293	/* -=-=-=-=-=- PCI Config Space -=-=-=-=-=- */
294
295
296	/**
297	* @interface_method_impl{PDMDEVREG,pfnConstruct}
298	*/
299	static DECLCALLBACK(int) pciGenEcamR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
300	{
301	RT_NOREF1(iInstance);
302	Assert(iInstance == 0);
303	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
304
305	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
306	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
307	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
308	PDEVPCIBUS pBus = &pPciRoot->PciBus;
309
310	/*
311	* Validate and read configuration.
312	*/
313	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "MmioEcamBase"
314	"\|MmioEcamLength"
315	"\|MmioPioBase"
316	"\|MmioPioSize"
317	"\|IntPinA"
318	"\|IntPinB"
319	"\|IntPinC"
320	"\|IntPinD", "");
321
322	int rc = pHlp->pfnCFGMQueryU64Def(pCfg, "MmioEcamBase", &pPciRoot->u64PciConfigMMioAddress, 0);
323	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgBase\"")));
324
325	rc = pHlp->pfnCFGMQueryU64Def(pCfg, "MmioEcamLength", &pPciRoot->u64PciConfigMMioLength, 0);
326	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgLength\"")));
327
328	rc = pHlp->pfnCFGMQueryU64Def(pCfg, "MmioPioBase", &pPciRoot->GCPhysMmioPioEmuBase, 0);
329	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"MmioPioBase\"")));
330
331	rc = pHlp->pfnCFGMQueryU64Def(pCfg, "MmioPioSize", &pPciRoot->GCPhysMmioPioEmuSize, 0);
332	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"MmioPioSize\"")));
333
334	rc = pHlp->pfnCFGMQueryU32(pCfg, "IntPinA", &pPciRoot->u.GenericEcam.auPciIrqNr[0]);
335	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IntPinA\"")));
336
337	rc = pHlp->pfnCFGMQueryU32(pCfg, "IntPinB", &pPciRoot->u.GenericEcam.auPciIrqNr[1]);
338	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IntPinB\"")));
339
340	rc = pHlp->pfnCFGMQueryU32(pCfg, "IntPinC", &pPciRoot->u.GenericEcam.auPciIrqNr[2]);
341	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IntPinC\"")));
342
343	rc = pHlp->pfnCFGMQueryU32(pCfg, "IntPinD", &pPciRoot->u.GenericEcam.auPciIrqNr[3]);
344	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IntPinD\"")));
345
346	Log(("PCI: fUseIoApic=%RTbool McfgBase=%#RX64 McfgLength=%#RX64 fR0Enabled=%RTbool fRCEnabled=%RTbool\n", pPciRoot->fUseIoApic,
347	pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength, pDevIns->fR0Enabled, pDevIns->fRCEnabled));
348	Log(("PCI: IntPinA=%u IntPinB=%u IntPinC=%u IntPinD=%u\n", pPciRoot->u.GenericEcam.auPciIrqNr[0],
349	pPciRoot->u.GenericEcam.auPciIrqNr[1], pPciRoot->u.GenericEcam.auPciIrqNr[2], pPciRoot->u.GenericEcam.auPciIrqNr[3]));
350
351	/*
352	* Init data.
353	*/
354	/* And fill values */
355	pBusCC->pDevInsR3 = pDevIns;
356	pPciRoot->hIoPortAddress = NIL_IOMIOPORTHANDLE;
357	pPciRoot->hIoPortData = NIL_IOMIOPORTHANDLE;
358	pPciRoot->hIoPortMagic = NIL_IOMIOPORTHANDLE;
359	pPciRoot->hMmioMcfg = NIL_IOMMMIOHANDLE;
360	pPciRoot->hMmioPioEmu = NIL_IOMMMIOHANDLE;
361	pPciRoot->PciBus.enmType = DEVPCIBUSTYPE_GENERIC_ECAM;
362	pPciRoot->PciBus.fPureBridge = false;
363	pPciRoot->PciBus.papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pPciRoot->PciBus.apDevices));
364	AssertLogRelReturn(pPciRoot->PciBus.papBridgesR3, VERR_NO_MEMORY);
365
366	/*
367	* Disable default device locking.
368	*/
369	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
370	AssertRCReturn(rc, rc);
371
372	/*
373	* Register bus
374	*/
375	PDMPCIBUSREGCC PciBusReg;
376	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
377	PciBusReg.pfnRegisterR3 = devpciR3CommonRegisterDevice;
378	PciBusReg.pfnRegisterMsiR3 = NULL;
379	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
380	PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
381	PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
382	PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
383	PciBusReg.pfnSetIrqR3 = pciGenEcamSetIrq;
384	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
385	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
386	if (RT_FAILURE(rc))
387	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
388	Assert(pBus->iBus == 0);
389	if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
390	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
391	N_("PCI helper version mismatch; got %#x expected %#x"),
392	pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
393
394	/*
395	* Fill in PCI configs and add them to the bus.
396	*/
397	#if 0
398	/* Host bridge device */
399	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
400	AssertPtr(pPciDev);
401	PDMPciDevSetVendorId( pPciDev, 0x8086); /** @todo Intel */
402	PDMPciDevSetDeviceId( pPciDev, 0x29e0); /** @todo Desktop */
403	PDMPciDevSetRevisionId(pPciDev, 0x01); /* rev. 01 */
404	PDMPciDevSetClassBase( pPciDev, 0x06); /* bridge */
405	PDMPciDevSetClassSub( pPciDev, 0x00); /* Host/PCI bridge */
406	PDMPciDevSetClassProg( pPciDev, 0x00); /* Host/PCI bridge */
407	PDMPciDevSetHeaderType(pPciDev, 0x00); /* bridge */
408	PDMPciDevSetWord(pPciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
409
410	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, 0 /fFlags/, 0 /uPciDevNo/, 0 /uPciFunNo/, "Host");
411	AssertLogRelRCReturn(rc, rc);
412	#endif
413
414	/*
415	* MMIO handlers.
416	*/
417	if (pPciRoot->u64PciConfigMMioAddress != 0)
418	{
419	rc = PDMDevHlpMmioCreateAndMap(pDevIns, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength,
420	devpciCommonMcfgMmioWrite, devpciCommonMcfgMmioRead,
421	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
422	"ECAM window", &pPciRoot->hMmioMcfg);
423	AssertMsgRCReturn(rc, ("rc=%Rrc %#RX64/%#RX64\n", rc, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength), rc);
424	}
425
426	if (pPciRoot->GCPhysMmioPioEmuBase != 0)
427	{
428	rc = PDMDevHlpMmioCreateAndMap(pDevIns, pPciRoot->GCPhysMmioPioEmuBase, pPciRoot->GCPhysMmioPioEmuSize,
429	pciHostR3MmioPioWrite, pciHostR3MmioPioRead,
430	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
431	"PIO range", &pPciRoot->hMmioPioEmu);
432	AssertMsgRCReturn(rc, ("rc=%Rrc %#RGp/%#RGp\n", rc, pPciRoot->GCPhysMmioPioEmuBase, pPciRoot->GCPhysMmioPioEmuSize), rc);
433	}
434
435	/*
436	* Saved state and info handlers.
437	*/
438	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCIGENECAM_SAVED_STATE_VERSION,
439	sizeof(pBus) + 16128, "pgm",
440	NULL, NULL, NULL,
441	NULL, devpciR3CommonSaveExec, NULL,
442	NULL, devpciR3CommonLoadExec, NULL);
443	AssertRCReturn(rc, rc);
444
445	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
446	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
447	devpciR3InfoPci);
448	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", devpciR3InfoPciIrq);
449
450	return VINF_SUCCESS;
451	}
452
453
454	/**
455	* @interface_method_impl{PDMDEVREG,pfnDestruct}
456	*/
457	static DECLCALLBACK(int) pciGenEcamR3Destruct(PPDMDEVINS pDevIns)
458	{
459	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
460	if (pPciRoot->PciBus.papBridgesR3)
461	{
462	PDMDevHlpMMHeapFree(pDevIns, pPciRoot->PciBus.papBridgesR3);
463	pPciRoot->PciBus.papBridgesR3 = NULL;
464	}
465	return VINF_SUCCESS;
466	}
467
468
469	/**
470	* @interface_method_impl{PDMDEVREG,pfnReset}
471	*/
472	static DECLCALLBACK(void) pciGenEcamR3Reset(PPDMDEVINS pDevIns)
473	{
474	/* Reset everything under the root bridge. */
475	devpciR3CommonResetBridge(pDevIns);
476	}
477
478
479	/**
480	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
481	*/
482	static DECLCALLBACK(void ) pciGenEcamBridgeQueryInterface(PPDMIBASE pInterface, const char pszIID)
483	{
484	PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
485	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
486
487	/* HACK ALERT! Special access to the PDMPCIDEV structure of an ich9pcibridge
488	instance (see PDMIICH9BRIDGEPDMPCIDEV_IID for details). */
489	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIICH9BRIDGEPDMPCIDEV, pDevIns->apPciDevs[0]);
490	return NULL;
491	}
492
493
494	/**
495	* @interface_method_impl{PDMDEVREG,pfnDestruct}
496	*/
497	static DECLCALLBACK(int) pciGenEcamBridgeR3Destruct(PPDMDEVINS pDevIns)
498	{
499	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
500	if (pBus->papBridgesR3)
501	{
502	PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
503	pBus->papBridgesR3 = NULL;
504	}
505	return VINF_SUCCESS;
506	}
507
508
509	/**
510	* @interface_method_impl{PDMDEVREG,pfnConstruct}
511	*/
512	static DECLCALLBACK(int) pciGenEcamBridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
513	{
514	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
515	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
516
517	/*
518	* Validate and read configuration.
519	*/
520	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "ExpressEnabled\|ExpressPortType", "");
521
522	/* check if we're supposed to implement a PCIe bridge. */
523	bool fExpress;
524	int rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ExpressEnabled", &fExpress, false);
525	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"ExpressEnabled\"")));
526
527	char szExpressPortType[80];
528	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ExpressPortType", szExpressPortType, sizeof(szExpressPortType), "RootCmplxIntEp");
529	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: failed to read \"ExpressPortType\" as string")));
530
531	uint8_t const uExpressPortType = devpciR3BridgeCommonGetExpressPortTypeFromString(szExpressPortType);
532	Log(("PCI/bridge#%u: fR0Enabled=%RTbool fRCEnabled=%RTbool fExpress=%RTbool uExpressPortType=%u (%s)\n",
533	iInstance, pDevIns->fR0Enabled, pDevIns->fRCEnabled, fExpress, uExpressPortType, szExpressPortType));
534
535	/*
536	* Init data and register the PCI bus.
537	*/
538	pDevIns->IBase.pfnQueryInterface = pciGenEcamBridgeQueryInterface;
539
540	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
541	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
542
543	pBus->enmType = DEVPCIBUSTYPE_ICH9;
544	pBus->fPureBridge = true;
545	pBusCC->pDevInsR3 = pDevIns;
546	pBus->papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pBus->apDevices));
547	AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
548
549	PDMPCIBUSREGCC PciBusReg;
550	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
551	PciBusReg.pfnRegisterR3 = devpcibridgeR3CommonRegisterDevice;
552	PciBusReg.pfnRegisterMsiR3 = NULL;
553	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
554	PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
555	PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
556	PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
557	PciBusReg.pfnSetIrqR3 = pciGenEcamBridgeSetIrq;
558	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
559	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
560	if (RT_FAILURE(rc))
561	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
562	Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
563	if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
564	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
565	N_("PCI helper version mismatch; got %#x expected %#x"),
566	pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
567
568	LogRel(("PCI: Registered bridge instance #%u as PDM bus no %u.\n", iInstance, pBus->iBus));
569
570
571	/* Disable default device locking. */
572	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
573	AssertRCReturn(rc, rc);
574
575	/** @todo r=aeichner This is the same as the ICH9 bridge. */
576	/*
577	* Fill in PCI configs and add them to the bus.
578	*/
579	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
580	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
581
582	PDMPciDevSetVendorId( pPciDev, 0x8086); /* Intel */
583	if (fExpress)
584	{
585	PDMPciDevSetDeviceId(pPciDev, 0x29e1); /* 82X38/X48 Express Host-Primary PCI Express Bridge. */
586	PDMPciDevSetRevisionId(pPciDev, 0x01);
587	}
588	else
589	{
590	PDMPciDevSetDeviceId(pPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
591	PDMPciDevSetRevisionId(pPciDev, 0xf2);
592	}
593	PDMPciDevSetClassSub( pPciDev, 0x04); /* pci2pci */
594	PDMPciDevSetClassBase( pPciDev, 0x06); /* PCI_bridge */
595	if (fExpress)
596	PDMPciDevSetClassProg(pPciDev, 0x00); /* Normal decoding. */
597	else
598	PDMPciDevSetClassProg(pPciDev, 0x01); /* Supports subtractive decoding. */
599	PDMPciDevSetHeaderType(pPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
600	if (fExpress)
601	{
602	PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_SERR);
603	PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Has capabilities. */
604	PDMPciDevSetByte(pPciDev, VBOX_PCI_CACHE_LINE_SIZE, 8); /* 32 bytes */
605	/* PCI Express */
606	PDMPciDevSetByte(pPciDev, 0xa0 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
607	PDMPciDevSetByte(pPciDev, 0xa0 + 1, 0); /* next */
608	PDMPciDevSetWord(pPciDev, 0xa0 + 2,
609	/* version */ 0x2
610	\| (uExpressPortType << 4));
611	PDMPciDevSetDWord(pPciDev, 0xa0 + 4, VBOX_PCI_EXP_DEVCAP_RBE); /* Device capabilities. */
612	PDMPciDevSetWord(pPciDev, 0xa0 + 8, 0x0000); /* Device control. */
613	PDMPciDevSetWord(pPciDev, 0xa0 + 10, 0x0000); /* Device status. */
614	PDMPciDevSetDWord(pPciDev, 0xa0 + 12,
615	/* Max Link Speed */ 2
616	\| /* Maximum Link Width */ (16 << 4)
617	\| /* Active State Power Management (ASPM) Sopport */ (0 << 10)
618	\| VBOX_PCI_EXP_LNKCAP_LBNC
619	\| /* Port Number / ((2 + iInstance) << 24)); / Link capabilities. */
620	PDMPciDevSetWord(pPciDev, 0xa0 + 16, VBOX_PCI_EXP_LNKCTL_CLOCK); /* Link control. */
621	PDMPciDevSetWord(pPciDev, 0xa0 + 18,
622	/* Current Link Speed */ 2
623	\| /* Negotiated Link Width */ (16 << 4)
624	\| VBOX_PCI_EXP_LNKSTA_SL_CLK); /* Link status. */
625	PDMPciDevSetDWord(pPciDev, 0xa0 + 20,
626	/* Slot Power Limit Value */ (75 << 7)
627	\| /* Physical Slot Number / (0 << 19)); / Slot capabilities. */
628	PDMPciDevSetWord(pPciDev, 0xa0 + 24, 0x0000); /* Slot control. */
629	PDMPciDevSetWord(pPciDev, 0xa0 + 26, 0x0000); /* Slot status. */
630	PDMPciDevSetWord(pPciDev, 0xa0 + 28, 0x0000); /* Root control. */
631	PDMPciDevSetWord(pPciDev, 0xa0 + 30, 0x0000); /* Root capabilities. */
632	PDMPciDevSetDWord(pPciDev, 0xa0 + 32, 0x00000000); /* Root status. */
633	PDMPciDevSetDWord(pPciDev, 0xa0 + 36, 0x00000000); /* Device capabilities 2. */
634	PDMPciDevSetWord(pPciDev, 0xa0 + 40, 0x0000); /* Device control 2. */
635	PDMPciDevSetWord(pPciDev, 0xa0 + 42, 0x0000); /* Device status 2. */
636	PDMPciDevSetDWord(pPciDev, 0xa0 + 44,
637	/* Supported Link Speeds Vector / (2 << 1)); / Link capabilities 2. */
638	PDMPciDevSetWord(pPciDev, 0xa0 + 48,
639	/* Target Link Speed / 2); / Link control 2. */
640	PDMPciDevSetWord(pPciDev, 0xa0 + 50, 0x0000); /* Link status 2. */
641	PDMPciDevSetDWord(pPciDev, 0xa0 + 52, 0x00000000); /* Slot capabilities 2. */
642	PDMPciDevSetWord(pPciDev, 0xa0 + 56, 0x0000); /* Slot control 2. */
643	PDMPciDevSetWord(pPciDev, 0xa0 + 58, 0x0000); /* Slot status 2. */
644	PDMPciDevSetCapabilityList(pPciDev, 0xa0);
645	}
646	else
647	{
648	PDMPciDevSetCommand(pPciDev, 0x00);
649	PDMPciDevSetStatus(pPciDev, 0x20); /* 66MHz Capable. */
650	}
651	PDMPciDevSetInterruptLine(pPciDev, 0x00); /* This device does not assert interrupts. */
652
653	/*
654	* This device does not generate interrupts. Interrupt delivery from
655	* devices attached to the bus is unaffected.
656	*/
657	PDMPciDevSetInterruptPin (pPciDev, 0x00);
658
659	if (fExpress)
660	{
661	/** @todo r=klaus set up the PCIe config space beyond the old 256 byte
662	* limit, containing additional capability descriptors. */
663	}
664
665	/*
666	* Register this PCI bridge. The called function will take care on which bus we will get registered.
667	*/
668	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, PDMPCIDEVREG_F_PCI_BRIDGE, PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
669	PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "pci-generic-ecam-bridge");
670	AssertLogRelRCReturn(rc, rc);
671
672	pPciDev->Int.s.pfnBridgeConfigRead = devpciR3BridgeCommonConfigRead;
673	pPciDev->Int.s.pfnBridgeConfigWrite = devpciR3BridgeCommonConfigWrite;
674
675	/*
676	* Register SSM handlers. We use the same saved state version as for the host bridge
677	* to make changes easier.
678	*/
679	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCIGENECAM_SAVED_STATE_VERSION,
680	sizeof(pBus) + 16128,
681	"pgm" /* before */,
682	NULL, NULL, NULL,
683	NULL, devpciR3BridgeCommonSaveExec, NULL,
684	NULL, devpciR3BridgeCommonLoadExec, NULL);
685	AssertLogRelRCReturn(rc, rc);
686
687	return VINF_SUCCESS;
688	}
689
690	#else /* !IN_RING3 */
691
692	/**
693	* @interface_method_impl{PDMDEVREGR0,pfnConstruct}
694	*/
695	DECLCALLBACK(int) pciGenEcamRZConstruct(PPDMDEVINS pDevIns)
696	{
697	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
698	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
699	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
700
701	/* Mirror the ring-3 device lock disabling: */
702	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
703	AssertRCReturn(rc, rc);
704
705	/* Set up the RZ PCI bus callbacks: */
706	PDMPCIBUSREGCC PciBusReg;
707	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
708	PciBusReg.iBus = pPciRoot->PciBus.iBus;
709	PciBusReg.pfnSetIrq = pciGenEcamSetIrq;
710	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
711	rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
712	AssertRCReturn(rc, rc);
713
714	/* Set up MMIO callbacks: */
715	if (pPciRoot->hMmioMcfg != NIL_IOMMMIOHANDLE)
716	{
717	rc = PDMDevHlpMmioSetUpContext(pDevIns, pPciRoot->hMmioMcfg, devpciCommonMcfgMmioWrite, devpciCommonMcfgMmioRead, NULL /pvUser/);
718	AssertLogRelRCReturn(rc, rc);
719	}
720
721	return rc;
722	}
723
724
725	/**
726	* @interface_method_impl{PDMDEVREGR0,pfnConstruct}
727	*/
728	static DECLCALLBACK(int) pciGenEcamBridgeRZConstruct(PPDMDEVINS pDevIns)
729	{
730	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
731	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
732	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
733
734	/* Mirror the ring-3 device lock disabling: */
735	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
736	AssertRCReturn(rc, rc);
737
738	/* Set up the RZ PCI bus callbacks: */
739	PDMPCIBUSREGCC PciBusReg;
740	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
741	PciBusReg.iBus = pBus->iBus;
742	PciBusReg.pfnSetIrq = pciGenEcamBridgeSetIrq;
743	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
744	rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
745	AssertRCReturn(rc, rc);
746
747	return rc;
748	}
749
750	#endif /* !IN_RING3 */
751
752	/**
753	* The PCI bus device registration structure.
754	*/
755	const PDMDEVREG g_DevicePciGenericEcam =
756	{
757	/* .u32Version = */ PDM_DEVREG_VERSION,
758	/* .uReserved0 = */ 0,
759	/* .szName = */ "pci-generic-ecam",
760	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
761	/* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI,
762	/* .cMaxInstances = */ 1,
763	/* .uSharedVersion = */ 42,
764	/* .cbInstanceShared = */ sizeof(DEVPCIROOT),
765	/* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
766	/* .cbInstanceRC = */ sizeof(DEVPCIBUSRC),
767	/* .cMaxPciDevices = */ 1,
768	/* .cMaxMsixVectors = */ 0,
769	/* .pszDescription = */ "Generic PCI host bridge (working with pci-host-ecam-generic driver)",
770	#if defined(IN_RING3)
771	/* .pszRCMod = */ "VBoxDDRC.rc",
772	/* .pszR0Mod = */ "VBoxDDR0.r0",
773	/* .pfnConstruct = */ pciGenEcamR3Construct,
774	/* .pfnDestruct = */ pciGenEcamR3Destruct,
775	/* .pfnRelocate = */ NULL,
776	/* .pfnMemSetup = */ NULL,
777	/* .pfnPowerOn = */ NULL,
778	/* .pfnReset = */ pciGenEcamR3Reset,
779	/* .pfnSuspend = */ NULL,
780	/* .pfnResume = */ NULL,
781	/* .pfnAttach = */ NULL,
782	/* .pfnDetach = */ NULL,
783	/* .pfnQueryInterface = */ NULL,
784	/* .pfnInitComplete = */ NULL,
785	/* .pfnPowerOff = */ NULL,
786	/* .pfnSoftReset = */ NULL,
787	/* .pfnReserved0 = */ NULL,
788	/* .pfnReserved1 = */ NULL,
789	/* .pfnReserved2 = */ NULL,
790	/* .pfnReserved3 = */ NULL,
791	/* .pfnReserved4 = */ NULL,
792	/* .pfnReserved5 = */ NULL,
793	/* .pfnReserved6 = */ NULL,
794	/* .pfnReserved7 = */ NULL,
795	#elif defined(IN_RING0)
796	/* .pfnEarlyConstruct = */ NULL,
797	/* .pfnConstruct = */ pciGenEcamRZConstruct,
798	/* .pfnDestruct = */ NULL,
799	/* .pfnFinalDestruct = */ NULL,
800	/* .pfnRequest = */ NULL,
801	/* .pfnReserved0 = */ NULL,
802	/* .pfnReserved1 = */ NULL,
803	/* .pfnReserved2 = */ NULL,
804	/* .pfnReserved3 = */ NULL,
805	/* .pfnReserved4 = */ NULL,
806	/* .pfnReserved5 = */ NULL,
807	/* .pfnReserved6 = */ NULL,
808	/* .pfnReserved7 = */ NULL,
809	#elif defined(IN_RC)
810	/* .pfnConstruct = */ pciGenEcamRZConstruct,
811	/* .pfnReserved0 = */ NULL,
812	/* .pfnReserved1 = */ NULL,
813	/* .pfnReserved2 = */ NULL,
814	/* .pfnReserved3 = */ NULL,
815	/* .pfnReserved4 = */ NULL,
816	/* .pfnReserved5 = */ NULL,
817	/* .pfnReserved6 = */ NULL,
818	/* .pfnReserved7 = */ NULL,
819	#else
820	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
821	#endif
822	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
823	};
824
825	/**
826	* The device registration structure
827	* for the PCI-to-PCI bridge.
828	*/
829	const PDMDEVREG g_DevicePciGenericEcamBridge =
830	{
831	/* .u32Version = */ PDM_DEVREG_VERSION,
832	/* .uReserved0 = */ 0,
833	/* .szName = */ "pci-generic-ecam-bridge",
834	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
835	/* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI,
836	/* .cMaxInstances = */ ~0U,
837	/* .uSharedVersion = */ 42,
838	/* .cbInstanceShared = */ sizeof(DEVPCIBUS),
839	/* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
840	/* .cbInstanceRC = */ 0,
841	/* .cMaxPciDevices = */ 1,
842	/* .cMaxMsixVectors = */ 0,
843	/* .pszDescription = */ "Generic ECAM PCI to PCI bridge",
844	#if defined(IN_RING3)
845	/* .pszRCMod = */ "VBoxDDRC.rc",
846	/* .pszR0Mod = */ "VBoxDDR0.r0",
847	/* .pfnConstruct = */ pciGenEcamBridgeR3Construct,
848	/* .pfnDestruct = */ pciGenEcamBridgeR3Destruct,
849	/* .pfnRelocate = */ NULL,
850	/* .pfnMemSetup = */ NULL,
851	/* .pfnPowerOn = */ NULL,
852	/* .pfnReset = / NULL, / Must be NULL, to make sure only bus driver handles reset */
853	/* .pfnSuspend = */ NULL,
854	/* .pfnResume = */ NULL,
855	/* .pfnAttach = */ NULL,
856	/* .pfnDetach = */ NULL,
857	/* .pfnQueryInterface = */ NULL,
858	/* .pfnInitComplete = */ NULL,
859	/* .pfnPowerOff = */ NULL,
860	/* .pfnSoftReset = */ NULL,
861	/* .pfnReserved0 = */ NULL,
862	/* .pfnReserved1 = */ NULL,
863	/* .pfnReserved2 = */ NULL,
864	/* .pfnReserved3 = */ NULL,
865	/* .pfnReserved4 = */ NULL,
866	/* .pfnReserved5 = */ NULL,
867	/* .pfnReserved6 = */ NULL,
868	/* .pfnReserved7 = */ NULL,
869	#elif defined(IN_RING0)
870	/* .pfnEarlyConstruct = */ NULL,
871	/* .pfnConstruct = */ pciGenEcamBridgeRZConstruct,
872	/* .pfnDestruct = */ NULL,
873	/* .pfnFinalDestruct = */ NULL,
874	/* .pfnRequest = */ NULL,
875	/* .pfnReserved0 = */ NULL,
876	/* .pfnReserved1 = */ NULL,
877	/* .pfnReserved2 = */ NULL,
878	/* .pfnReserved3 = */ NULL,
879	/* .pfnReserved4 = */ NULL,
880	/* .pfnReserved5 = */ NULL,
881	/* .pfnReserved6 = */ NULL,
882	/* .pfnReserved7 = */ NULL,
883	#elif defined(IN_RC)
884	/* .pfnConstruct = */ pciGenEcamBridgeRZConstruct,
885	/* .pfnReserved0 = */ NULL,
886	/* .pfnReserved1 = */ NULL,
887	/* .pfnReserved2 = */ NULL,
888	/* .pfnReserved3 = */ NULL,
889	/* .pfnReserved4 = */ NULL,
890	/* .pfnReserved5 = */ NULL,
891	/* .pfnReserved6 = */ NULL,
892	/* .pfnReserved7 = */ NULL,
893	#else
894	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
895	#endif
896	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
897	};

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciGenericEcam.cpp@ 106129

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