DevPCI.cpp@ 97698

Last change on this file since 97698 was 96407, checked in by vboxsync, 2 years ago
scm copyright and license note update
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 75.3 KB

Line
1	/* $Id: DevPCI.cpp 96407 2022-08-22 17:43:14Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*
5	* @remarks New code shall be added to DevPciIch9.cpp as that will become
6	* the common PCI bus code soon. Don't fix code in both DevPCI.cpp
7	* and DevPciIch9.cpp when it's possible to just make the latter
8	* version common. Common code uses the 'devpci' prefix, is
9	* prototyped in DevPciInternal.h, and is defined in DevPciIch9.cpp.
10	*/
11
12	/*
13	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
14	*
15	* This file is part of VirtualBox base platform packages, as
16	* available from https://www.virtualbox.org.
17	*
18	* This program is free software; you can redistribute it and/or
19	* modify it under the terms of the GNU General Public License
20	* as published by the Free Software Foundation, in version 3 of the
21	* License.
22	*
23	* This program is distributed in the hope that it will be useful, but
24	* WITHOUT ANY WARRANTY; without even the implied warranty of
25	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
26	* General Public License for more details.
27	*
28	* You should have received a copy of the GNU General Public License
29	* along with this program; if not, see <https://www.gnu.org/licenses>.
30	*
31	* SPDX-License-Identifier: GPL-3.0-only
32	* --------------------------------------------------------------------
33	*
34	* This code is based on:
35	*
36	* QEMU PCI bus manager
37	*
38	* Copyright (c) 2004 Fabrice Bellard
39	*
40	* Permission is hereby granted, free of charge, to any person obtaining a copy
41	* of this software and associated documentation files (the "Software"), to deal
42	* in the Software without restriction, including without limitation the rights
43	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
44	* copies of the Software, and to permit persons to whom the Software is
45	* furnished to do so, subject to the following conditions:
46	*
47	* The above copyright notice and this permission notice shall be included in
48	* all copies or substantial portions of the Software.
49	*
50	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
51	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
52	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
53	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
54	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
55	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
56	* THE SOFTWARE.
57	*/
58
59
60	/*********************************************************************************************************************************
61	* Header Files *
62	*********************************************************************************************************************************/
63	#define LOG_GROUP LOG_GROUP_DEV_PCI
64	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
65	#include <VBox/vmm/pdmpcidev.h>
66	#include <VBox/vmm/pdmdev.h>
67	#include <VBox/vmm/mm.h>
68	#include <iprt/asm.h>
69	#include <iprt/assert.h>
70	#include <iprt/string.h>
71
72	#include "PciInline.h"
73	#include "VBoxDD.h"
74	#include "DevPciInternal.h"
75
76
77	/*********************************************************************************************************************************
78	* Defined Constants And Macros *
79	*********************************************************************************************************************************/
80	/** Saved state version of the PCI bus device. */
81	#define VBOX_PCI_SAVED_STATE_VERSION VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES
82	/** Adds I/O region types and sizes for dealing changes in resource regions. */
83	#define VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES 4
84	/** Before region sizes, the first named one.
85	* Looking at the code though, we support even older version. */
86	#define VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES 3
87	/** Notes whether we use the I/O APIC. */
88	#define VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC 2
89
90
91	/*********************************************************************************************************************************
92	* Internal Functions *
93	*********************************************************************************************************************************/
94	RT_C_DECLS_BEGIN
95
96	static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
97
98	#ifdef IN_RING3
99	DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus);
100	#endif
101
102	RT_C_DECLS_END
103
104	#define DEBUG_PCI
105
106	#define PCI_VENDOR_ID 0x00 /* 16 bits */
107	#define PCI_DEVICE_ID 0x02 /* 16 bits */
108	#define PCI_COMMAND 0x04 /* 16 bits */
109	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
110	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
111	#define PCI_CLASS_DEVICE 0x0a /* Device class */
112	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
113	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
114	#define PCI_MIN_GNT 0x3e /* 8 bits */
115	#define PCI_MAX_LAT 0x3f /* 8 bits */
116
117
118	static VBOXSTRICTRC pci_data_write(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, uint32_t addr, uint32_t u32Value, int cb)
119	{
120	LogFunc(("addr=%08x u32Value=%08x cb=%d\n", pGlobals->uConfigReg, u32Value, cb));
121
122	if (!(pGlobals->uConfigReg & (1 << 31)))
123	return VINF_SUCCESS;
124	if ((pGlobals->uConfigReg & 0x3) != 0)
125	return VINF_SUCCESS;
126
127	uint8_t const iBus = (pGlobals->uConfigReg >> 16) & 0xff;
128	uint8_t const iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
129	#ifdef IN_RING3
130	uint32_t const config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
131	#endif
132	RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
133
134	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
135	if (iBus != 0)
136	{
137	if (pGlobals->PciBus.cBridges)
138	{
139	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
140	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
141	if (pBridgeDevice)
142	{
143	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
144	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus,
145	iDevice, config_addr, cb, u32Value);
146	}
147	#else
148	RT_NOREF(pDevIns, addr, u32Value, cb);
149	rcStrict = VINF_IOM_R3_IOPORT_WRITE;
150	#endif
151	}
152	}
153	else
154	{
155	R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[iDevice];
156	if (pPciDev)
157	{
158	#ifdef IN_RING3
159	LogFunc(("%s: addr=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, config_addr, u32Value, cb));
160	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
161	if (pPciDev->Int.s.pfnConfigWrite)
162	rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, config_addr, cb, u32Value);
163	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
164	rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
165	pPciDev, config_addr, cb, u32Value);
166	#else
167	rcStrict = VINF_IOM_R3_IOPORT_WRITE;
168	#endif
169	}
170	}
171	return rcStrict;
172	}
173
174	static VBOXSTRICTRC pci_data_read(PDEVPCIROOT pGlobals, uint32_t addr, int cb, uint32_t *pu32Value)
175	{
176	*pu32Value = UINT32_MAX;
177
178	if (!(pGlobals->uConfigReg & (1 << 31)))
179	return VINF_SUCCESS;
180	if ((pGlobals->uConfigReg & 0x3) != 0)
181	return VINF_SUCCESS;
182	uint8_t const iBus = (pGlobals->uConfigReg >> 16) & 0xff;
183	uint8_t const iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
184	#ifdef IN_RING3
185	uint32_t const config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
186	#endif
187	RT_UNTRUSTED_VALIDATED_FENCE();
188
189	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
190	if (iBus != 0)
191	{
192	if (pGlobals->PciBus.cBridges)
193	{
194	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
195	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
196	if (pBridgeDevice)
197	{
198	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
199	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns),
200	iBus, iDevice, config_addr, cb, pu32Value);
201	}
202	#else
203	RT_NOREF(addr, cb);
204	rcStrict = VINF_IOM_R3_IOPORT_READ;
205	#endif
206	}
207	}
208	else
209	{
210	R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[iDevice];
211	if (pPciDev)
212	{
213	#ifdef IN_RING3
214	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
215	if (pPciDev->Int.s.pfnConfigRead)
216	rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, config_addr, cb, pu32Value);
217	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
218	rcStrict = devpciR3CommonConfigReadWorker(pPciDev, config_addr, cb, pu32Value);
219	LogFunc(("%s: addr=%02x val=%08x cb=%d\n", pPciDev->pszNameR3, config_addr, *pu32Value, cb));
220	#else
221	NOREF(cb);
222	rcStrict = VINF_IOM_R3_IOPORT_READ;
223	#endif
224	}
225	}
226
227	return rcStrict;
228	}
229
230
231
232	/* return the global irq number corresponding to a given device irq
233	pin. We could also use the bus number to have a more precise
234	mapping.
235	This is the implementation note described in the PCI spec chapter 2.2.6 */
236	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
237	{
238	int slot_addend;
239	slot_addend = (uDevFn >> 3) - 1;
240	return (irq_num + slot_addend) & 3;
241	}
242
243	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
244	{
245	return (irq_num + (uDevFn >> 3)) & 7;
246	}
247
248	static inline int get_pci_irq_apic_level(PDEVPCIROOT pGlobals, int irq_num)
249	{
250	return (pGlobals->auPciApicIrqLevels[irq_num] != 0);
251	}
252
253	static void apic_set_irq(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PDEVPCIBUSCC pBusCC,
254	uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, int iAcpiIrq, uint32_t uTagSrc)
255	{
256	/* This is only allowed to be called with a pointer to the host bus. */
257	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
258	uint16_t const uBusDevFn = PCIBDF_MAKE(pBus->iBus, uDevFn);
259
260	if (iAcpiIrq == -1) {
261	int apic_irq, apic_level;
262	PDEVPCIROOT pGlobals = DEVPCIBUS_2_DEVPCIROOT(pBus);
263	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
264
265	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
266	ASMAtomicIncU32(&pGlobals->auPciApicIrqLevels[irq_num]);
267	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
268	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
269
270	apic_irq = irq_num + 0x10;
271	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
272	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
273	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
274	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, apic_irq, apic_level, uTagSrc);
275
276	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
277	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
278	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
279	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
280	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
281	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
282	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, apic_irq, apic_level, uTagSrc);
283	}
284	} else {
285	Log3Func(("%s: irq_num1=%d level=%d iAcpiIrq=%d\n", R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iAcpiIrq));
286	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, iAcpiIrq, iLevel, uTagSrc);
287	}
288	}
289
290	DECLINLINE(int) get_pci_irq_level(PDEVPCIROOT pGlobals, int irq_num)
291	{
292	return (pGlobals->Piix3.auPciLegacyIrqLevels[irq_num] != 0);
293	}
294
295	/**
296	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
297	*
298	* @param pDevIns The PDM device instance for the PCI bus.
299	* @param pGlobals Device instance of the host PCI bus.
300	* @param pBusCC Context specific data for the PCI bus.
301	* @param uDevFn The device number on the host bus which will raise the IRQ
302	* @param pPciDev The PCI device structure which raised the interrupt.
303	* @param iIrq IRQ number to set.
304	* @param iLevel IRQ level.
305	* @param uTagSrc The IRQ tag and source ID (for tracing).
306	* @remark uDevFn and pPciDev->uDevFn are not the same if the device is behind
307	* a bridge. In that case uDevFn will be the slot of the bridge which
308	* is needed to calculate the PIRQ value.
309	*/
310	static void pciSetIrqInternal(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, PDEVPCIBUSCC pBusCC,
311	uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
312	{
313	PDEVPCIBUS pBus = &pGlobals->PciBus;
314	uint8_t *pbCfg = pDevIns->apPciDevs[1]->abConfig;
315	const bool fIsAcpiDevice = pPciDev->abConfig[2] == 0x13 && pPciDev->abConfig[3] == 0x71;
316	/* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
317	* is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
318	* See the \_SB_.PCI0._PRT method in vbox.dsl.
319	*/
320	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
321	int pic_irq, pic_level;
322
323	/* Check if the state changed. */
324	if (pPciDev->Int.s.uIrqPinState != iLevel)
325	{
326	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
327
328	/* Send interrupt to I/O APIC only. */
329	if (fIsApicEnabled)
330	{
331	if (fIsAcpiDevice)
332	/*
333	* ACPI needs special treatment since SCI is hardwired and
334	* should not be affected by PCI IRQ routing tables at the
335	* same time SCI IRQ is shared in PCI sense hence this
336	* kludge (i.e. we fetch the hardwired value from ACPIs
337	* PCI device configuration space).
338	*/
339	apic_set_irq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, -1, iLevel, pPciDev->abConfig[PCI_INTERRUPT_LINE], uTagSrc);
340	else
341	apic_set_irq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
342	return;
343	}
344
345	if (fIsAcpiDevice)
346	{
347	/* As per above treat ACPI in a special way */
348	pic_irq = pPciDev->abConfig[PCI_INTERRUPT_LINE];
349	pGlobals->Piix3.iAcpiIrq = pic_irq;
350	pGlobals->Piix3.iAcpiIrqLevel = iLevel & PDM_IRQ_LEVEL_HIGH;
351	}
352	else
353	{
354	int irq_num;
355	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
356
357	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
358	ASMAtomicIncU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
359	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
360	ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
361
362	/* now we change the pic irq level according to the piix irq mappings */
363	pic_irq = pbCfg[0x60 + irq_num];
364	if (pic_irq >= 16)
365	{
366	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
367	{
368	ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
369	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
370	}
371
372	return;
373	}
374	}
375
376	/* the pic level is the logical OR of all the PCI irqs mapped to it */
377	pic_level = 0;
378	if (pic_irq == pbCfg[0x60])
379	pic_level \|= get_pci_irq_level(pGlobals, 0); /* PIRQA */
380	if (pic_irq == pbCfg[0x61])
381	pic_level \|= get_pci_irq_level(pGlobals, 1); /* PIRQB */
382	if (pic_irq == pbCfg[0x62])
383	pic_level \|= get_pci_irq_level(pGlobals, 2); /* PIRQC */
384	if (pic_irq == pbCfg[0x63])
385	pic_level \|= get_pci_irq_level(pGlobals, 3); /* PIRQD */
386	if (pic_irq == pGlobals->Piix3.iAcpiIrq)
387	pic_level \|= pGlobals->Piix3.iAcpiIrqLevel;
388
389	Log3Func(("%s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
390	R3STRING(pPciDev->pszNameR3), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
391	pBusCC->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pDevIns, pic_irq, pic_level, uTagSrc);
392
393	/** @todo optimize pci irq flip-flop some rainy day. */
394	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
395	pciSetIrqInternal(pDevIns, pGlobals, pBusCC, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
396	}
397	}
398
399
400	/**
401	* @interface_method_impl{PDMPCIBUSREGR3,pfnSetIrqR3}
402	*/
403	static DECLCALLBACK(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
404	{
405	PDEVPCIROOT pBus = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
406	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
407	LogFlow(("pciSetIrq: %p %u %u %#x\n", pPciDev, iIrq, iLevel, uTagSrc));
408	pciSetIrqInternal(pDevIns, pBus, pBusCC, pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
409	}
410
411	#ifdef IN_RING3
412
413	/**
414	* Finds a bridge on the bus which contains the destination bus.
415	*
416	* @return Pointer to the device instance data of the bus or
417	* NULL if no bridge was found.
418	* @param pBus Pointer to the bus to search on.
419	* @param iBus Destination bus number.
420	*/
421	DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus)
422	{
423	/* Search for a fitting bridge. */
424	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
425	{
426	/*
427	* Examine secondary and subordinate bus number.
428	* If the target bus is in the range we pass the request on to the bridge.
429	*/
430	PPDMPCIDEV pBridgeTemp = pBus->papBridgesR3[iBridge];
431	AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
432	("Device is not a PCI bridge but on the list of PCI bridges\n"));
433
434	if ( iBus >= pBridgeTemp->abConfig[VBOX_PCI_SECONDARY_BUS]
435	&& iBus <= pBridgeTemp->abConfig[VBOX_PCI_SUBORDINATE_BUS])
436	return pBridgeTemp;
437	}
438
439	/* Nothing found. */
440	return NULL;
441	}
442
443	static void pciR3Piix3Reset(PPDMPCIDEV pPiix3PciDev)
444	{
445	uint8_t *pci_conf = pPiix3PciDev->abConfig;
446
447	pci_conf[0x04] = 0x07; /* master, memory and I/O */
448	pci_conf[0x05] = 0x00;
449	pci_conf[0x06] = 0x00;
450	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
451	pci_conf[0x4c] = 0x4d;
452	pci_conf[0x4e] = 0x03;
453	pci_conf[0x4f] = 0x00;
454	pci_conf[0x60] = 0x80;
455	pci_conf[0x69] = 0x02;
456	pci_conf[0x70] = 0x80;
457	pci_conf[0x76] = 0x0c;
458	pci_conf[0x77] = 0x0c;
459	pci_conf[0x78] = 0x02;
460	pci_conf[0x79] = 0x00;
461	pci_conf[0x80] = 0x00;
462	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
463	pci_conf[0xa0] = 0x08;
464	pci_conf[0xa2] = 0x00;
465	pci_conf[0xa3] = 0x00;
466	pci_conf[0xa4] = 0x00;
467	pci_conf[0xa5] = 0x00;
468	pci_conf[0xa6] = 0x00;
469	pci_conf[0xa7] = 0x00;
470	pci_conf[0xa8] = 0x0f;
471	pci_conf[0xaa] = 0x00;
472	pci_conf[0xab] = 0x00;
473	pci_conf[0xac] = 0x00;
474	pci_conf[0xae] = 0x00;
475	}
476
477	/* host irqs corresponding to PCI irqs A-D */
478	static const uint8_t pci_irqs[4] = { 11, 10, 9, 11 }; /* bird: added const */
479
480	static void pci_bios_init_device(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, PDEVPCIBUS pBus,
481	PPDMPCIDEV pPciDev, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
482	{
483	uint32_t uPciBiosSpecialVRAM = 0xe0000000;
484	uint32_t *paddr;
485	int pin, pic_irq;
486	uint16_t devclass, vendor_id, device_id;
487
488	devclass = devpciR3GetWord(pPciDev, PCI_CLASS_DEVICE);
489	vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
490	device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
491
492	/* Check if device is present. */
493	if (vendor_id != 0xffff)
494	{
495	switch (devclass)
496	{
497	case 0x0101:
498	if ( (vendor_id == 0x8086)
499	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
500	{
501	/* PIIX3, PIIX4 or ICH6 IDE */
502	devpciR3SetWord(pDevIns, pPciDev, 0x40, 0x8011); /* enable IDE0 + fast timing */
503	devpciR3SetWord(pDevIns, pPciDev, 0x42, 0x8011); /* enable IDE1 + fast timing */
504	goto default_map;
505	}
506	else
507	{
508	/* IDE: we map it as in ISA mode */
509	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x1f0);
510	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 1, 0x3f4);
511	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 2, 0x170);
512	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 3, 0x374);
513	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
514	devpciR3GetWord(pPciDev, PCI_COMMAND)
515	\| PCI_COMMAND_IOACCESS);
516	}
517	break;
518	case 0x0800:
519	/* PIC */
520	vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
521	device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
522	if (vendor_id == 0x1014)
523	{
524	/* IBM */
525	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
526	{
527	/* MPIC & MPIC2 */
528	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x80800000 + 0x00040000);
529	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
530	devpciR3GetWord(pPciDev, PCI_COMMAND)
531	\| PCI_COMMAND_MEMACCESS);
532	}
533	}
534	break;
535	case 0xff00:
536	if ( (vendor_id == 0x0106b)
537	&& (device_id == 0x0017 \|\| device_id == 0x0022))
538	{
539	/* macio bridge */
540	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x80800000);
541	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
542	devpciR3GetWord(pPciDev, PCI_COMMAND)
543	\| PCI_COMMAND_MEMACCESS);
544	}
545	break;
546	case 0x0604:
547	{
548	/* Init PCI-to-PCI bridge. */
549	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_PRIMARY_BUS, pBus->iBus);
550
551	AssertMsg(pGlobals->uPciBiosBus < 255, ("Too many bridges on the bus\n"));
552	pGlobals->uPciBiosBus++;
553	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uPciBiosBus);
554	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
555
556	/* Add position of this bridge into the array. */
557	paBridgePositions[cBridgeDepth+1] = (pPciDev->uDevFn >> 3);
558
559	/*
560	* The I/O range for the bridge must be aligned to a 4KB boundary.
561	* This does not change anything really as the access to the device is not going
562	* through the bridge but we want to be compliant to the spec.
563	*/
564	if ((pGlobals->uPciBiosIo % _4K) != 0)
565	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
566	LogFunc(("Aligned I/O start address. New address %#x\n", pGlobals->uPciBiosIo));
567	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0);
568
569	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
570	if ((pGlobals->uPciBiosMmio % _1M) != 0)
571	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
572	LogFunc(("Aligned MMIO start address. New address %#x\n", pGlobals->uPciBiosMmio));
573	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
574
575	/* Save values to compare later to. */
576	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
577	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
578
579	/* Init devices behind the bridge and possibly other bridges as well. */
580	PDEVPCIBUS pChildBus = PDMINS_2_DATA(pPciDev->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
581	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pChildBus->apDevices); uDevFn++)
582	{
583	PPDMPCIDEV pChildPciDev = pChildBus->apDevices[uDevFn];
584	if (pChildPciDev)
585	pci_bios_init_device(pDevIns, pGlobals, pChildBus, pChildPciDev, cBridgeDepth + 1, paBridgePositions);
586	}
587
588	/* The number of bridges behind the this one is now available. */
589	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
590
591	/*
592	* Set I/O limit register. If there is no device with I/O space behind the bridge
593	* we set a lower value than in the base register.
594	* The result with a real bridge is that no I/O transactions are passed to the secondary
595	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
596	*/
597	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % _4K) != 0))
598	{
599	/* The upper boundary must be one byte less than a 4KB boundary. */
600	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
601	}
602	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1);
603
604	/* Same with the MMIO limit register but with 1MB boundary here. */
605	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % _1M) != 0))
606	{
607	/* The upper boundary must be one byte less than a 1MB boundary. */
608	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
609	}
610	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1);
611
612	/*
613	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
614	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
615	* the base register than in the limit register.
616	*/
617	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
618	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
619	devpciR3SetDWord(pDevIns, pPciDev, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
620	devpciR3SetDWord(pDevIns, pPciDev, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
621	break;
622	}
623	default:
624	default_map:
625	{
626	/* default memory mappings */
627	bool fActiveMemRegion = false;
628	bool fActiveIORegion = false;
629	/*
630	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
631	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
632	*/
633	for (unsigned i = 0; i < (PCI_NUM_REGIONS-1); i++)
634	{
635	uint32_t u32Size;
636	uint8_t u8ResourceType;
637	uint32_t u32Address = 0x10 + i * 4;
638
639	/* Calculate size. */
640	u8ResourceType = devpciR3GetByte(pPciDev, u32Address);
641	devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0xffffffff));
642	u32Size = devpciR3GetDWord(pPciDev, u32Address);
643	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
644	/* Clear resource information depending on resource type. */
645	if (fIsPio) /* I/O */
646	u32Size &= ~(0x01);
647	else /* MMIO */
648	u32Size &= ~(0x0f);
649
650	/*
651	* Invert all bits and add 1 to get size of the region.
652	* (From PCI implementation note)
653	*/
654	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
655	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
656	else
657	u32Size = (~u32Size) + 1;
658
659	Log2Func(("Size of region %u for device %d on bus %d is %u\n", i, pPciDev->uDevFn, pBus->iBus, u32Size));
660
661	if (u32Size)
662	{
663	if (fIsPio)
664	paddr = &pGlobals->uPciBiosIo;
665	else
666	{
667	paddr = &pGlobals->uPciBiosMmio;
668	if (devclass == 0x0300)
669	{
670	/*
671	* Because legacy VGA I/O ports are implicitly decoded
672	* by a VGA class device without needing a BAR, we must
673	* enable I/O decoding for such devices.
674	*/
675	fActiveIORegion = true;
676
677	if (vendor_id == 0x80ee \|\| vendor_id == 0x15ad)
678	{
679	bool fPrefetch = (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_IO)))
680	== PCI_ADDRESS_SPACE_MEM_PREFETCH;
681	/* VGA: map frame buffer to default Bochs VBE address. Only
682	* needed for legacy guest drivers. */
683	if (fPrefetch)
684	paddr = &uPciBiosSpecialVRAM;
685	}
686	}
687	}
688	uint32_t uNew = *paddr;
689	uNew = (uNew + u32Size - 1) & ~(u32Size - 1);
690	if (fIsPio)
691	uNew &= UINT32_C(0xffff);
692	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
693	if (!uNew \|\| (uNew <= UINT32_C(0xffffffff) && uNew + u32Size - 1 >= UINT32_C(0xfec00000)))
694	{
695	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
696	i, pBus->iBus, pPciDev->uDevFn >> 3, pPciDev->uDevFn & 7, vendor_id, device_id)); /** @todo make this a VM start failure later. */
697	/* Undo the mapping mess caused by the size probing. */
698	devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0));
699	}
700	else
701	{
702	LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), i, uNew));
703	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, i, uNew);
704	if (fIsPio)
705	fActiveIORegion = true;
706	else
707	fActiveMemRegion = true;
708	*paddr = uNew + u32Size;
709	Log2Func(("New address is %#x\n", *paddr));
710	}
711	}
712	}
713
714	/* Update the command word appropriately. */
715	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
716	devpciR3GetWord(pPciDev, PCI_COMMAND)
717	\| (fActiveMemRegion ? PCI_COMMAND_MEMACCESS : 0)
718	\| (fActiveIORegion ? PCI_COMMAND_IOACCESS : 0));
719
720	break;
721	}
722	}
723
724	/* map the interrupt */
725	pin = devpciR3GetByte(pPciDev, PCI_INTERRUPT_PIN);
726	if (pin != 0)
727	{
728	uint8_t uBridgeDevFn = pPciDev->uDevFn;
729	pin--;
730
731	/* We need to go up to the host bus to see which irq this device will assert there. */
732	while (cBridgeDepth != 0)
733	{
734	/* Get the pin the device would assert on the bridge. */
735	pin = ((uBridgeDevFn >> 3) + pin) & 3;
736	uBridgeDevFn = paBridgePositions[cBridgeDepth];
737	cBridgeDepth--;
738	}
739
740	pin = pci_slot_get_pirq(pPciDev->uDevFn, pin);
741	pic_irq = pci_irqs[pin];
742	devpciR3SetByte(pDevIns, pPciDev, PCI_INTERRUPT_LINE, pic_irq);
743	}
744	}
745	}
746
747	/**
748	* Worker for Fake PCI BIOS config, triggered by magic port access by BIOS.
749	*
750	* @returns VBox status code.
751	*
752	* @param pDevIns i440FX device instance.
753	*/
754	static int pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
755	{
756	uint8_t elcr[2] = {0, 0};
757	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
758
759	LogRel(("PCI: Setting up resources and interrupts\n"));
760
761	/*
762	* Set the start addresses.
763	*/
764	pGlobals->uPciBiosBus = 0;
765	pGlobals->uPciBiosIo = 0xd000;
766	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
767
768	/*
769	* Activate IRQ mappings.
770	*/
771	PPDMPCIDEV pPIIX3 = pDevIns->apPciDevs[1];
772	for (unsigned i = 0; i < 4; i++)
773	{
774	uint8_t irq = pci_irqs[i];
775	/* Set to trigger level. */
776	elcr[irq >> 3] \|= (1 << (irq & 7));
777	/* Activate irq remapping in PIIX3. */
778	devpciR3SetByte(pDevIns, pPIIX3, 0x60 + i, irq);
779	}
780
781	/* Tell to the PIC. */
782	/** @todo r=aeichner We should really move this to the BIOS code and get rid of this fake PCI BIOS thing,
783	* DevPciIch9.cpp lacks this code and has a todo for this.
784	*/
785	VBOXSTRICTRC rcStrict = pDevIns->pHlpR3->pfnIoPortWrite(pDevIns, 0x4d0, elcr[0], sizeof(uint8_t));
786	if (rcStrict == VINF_SUCCESS)
787	rcStrict = pDevIns->pHlpR3->pfnIoPortWrite(pDevIns, 0x4d1, elcr[1], sizeof(uint8_t));
788	if (rcStrict != VINF_SUCCESS)
789	{
790	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
791	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
792	}
793
794	/*
795	* Init the devices.
796	*/
797	PDEVPCIBUS pBus = &pGlobals->PciBus;
798	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
799	{
800	PPDMPCIDEV pPciDev = pBus->apDevices[uDevFn];
801	if (pPciDev)
802	{
803	Log2(("PCI: Initializing device %d (%#x)\n", uDevFn, 0x80000000 \| (uDevFn << 8)));
804	uint8_t aBridgePositions[256];
805	RT_ZERO(aBridgePositions);
806	pci_bios_init_device(pDevIns, pGlobals, pBus, pPciDev, 0, aBridgePositions);
807	}
808	}
809
810	return VINF_SUCCESS;
811	}
812
813	#endif /* IN_RING3 */
814
815
816	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
817
818	/**
819	* @callback_method_impl{FNIOMIOPORTNEWOUT, PCI address}
820	*/
821	static DECLCALLBACK(VBOXSTRICTRC)
822	pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
823	{
824	LogFunc(("offPort=%#x u32=%#x cb=%d\n", offPort, u32, cb));
825	Assert(offPort == 0); RT_NOREF2(offPort, pvUser);
826	if (cb == 4)
827	{
828	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
829	PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
830	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
831	PCI_UNLOCK(pDevIns);
832	}
833	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
834	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
835	return VINF_SUCCESS;
836	}
837
838
839	/**
840	* @callback_method_impl{FNIOMIOPORTNEWIN, PCI address}
841	*/
842	static DECLCALLBACK(VBOXSTRICTRC)
843	pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
844	{
845	Assert(offPort == 0); RT_NOREF2(offPort, pvUser);
846	if (cb == 4)
847	{
848	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
849	PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_READ);
850	*pu32 = pThis->uConfigReg;
851	PCI_UNLOCK(pDevIns);
852	LogFunc(("offPort=%#x cb=%d -> %#x\n", offPort, cb, *pu32));
853	return VINF_SUCCESS;
854	}
855	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
856	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
857	LogFunc(("offPort=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", offPort, cb));
858	return VERR_IOM_IOPORT_UNUSED;
859	}
860
861
862	/**
863	* @callback_method_impl{FNIOMIOPORTNEWOUT, PCI data}
864	*/
865	static DECLCALLBACK(VBOXSTRICTRC)
866	pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
867	{
868	LogFunc(("offPort=%#x u32=%#x cb=%d\n", offPort, u32, cb));
869	Assert(offPort < 4); NOREF(pvUser);
870	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
871	if (!(offPort % cb))
872	{
873	PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
874	rcStrict = pci_data_write(pDevIns, PDMINS_2_DATA(pDevIns, PDEVPCIROOT), offPort, u32, cb);
875	PCI_UNLOCK(pDevIns);
876	}
877	else
878	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", offPort, u32, cb));
879	return rcStrict;
880	}
881
882
883	/**
884	* @callback_method_impl{FNIOMIOPORTNEWIN, PCI data}
885	*/
886	static DECLCALLBACK(VBOXSTRICTRC)
887	pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
888	{
889	Assert(offPort < 4); NOREF(pvUser);
890	if (!(offPort % cb))
891	{
892	PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_READ);
893	VBOXSTRICTRC rcStrict = pci_data_read(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), offPort, cb, pu32);
894	PCI_UNLOCK(pDevIns);
895	LogFunc(("offPort=%#x cb=%#x -> %#x (%Rrc)\n", offPort, cb, *pu32, VBOXSTRICTRC_VAL(rcStrict)));
896	return rcStrict;
897	}
898	AssertMsgFailed(("Read from port %#x cb=%d\n", offPort, cb));
899	return VERR_IOM_IOPORT_UNUSED;
900	}
901
902	#ifdef IN_RING3
903
904	/**
905	* @callback_method_impl{FNIOMIOPORTNEWOUT, PCI data}
906	*/
907	static DECLCALLBACK(VBOXSTRICTRC)
908	pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
909	{
910	Assert(offPort == 0); RT_NOREF2(pvUser, offPort);
911	LogFunc(("offPort=%#x u32=%#x cb=%d\n", offPort, u32, cb));
912	if (cb == 4)
913	{
914	if (u32 == UINT32_C(19200509)) // Richard Adams - Note! In decimal rather hex.
915	{
916	int rc = pciR3FakePCIBIOS(pDevIns);
917	AssertRC(rc);
918	}
919	}
920
921	return VINF_SUCCESS;
922	}
923
924	/**
925	* @callback_method_impl{FNIOMIOPORTNEWIN, PCI data}
926	*/
927	static DECLCALLBACK(VBOXSTRICTRC)
928	pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
929	{
930	Assert(offPort == 0); RT_NOREF5(pDevIns, pvUser, offPort, pu32, cb);
931	LogFunc(("offPort=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", offPort, cb));
932	return VERR_IOM_IOPORT_UNUSED;
933	}
934
935
936	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
937
938	/**
939	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
940	*
941	* @returns VBox status code.
942	* @param pHlp The device helpers.
943	* @param pBus The bus to save.
944	* @param pSSM The saved state handle.
945	*/
946	static int pciR3CommonSaveExec(PCPDMDEVHLPR3 pHlp, PDEVPCIBUS pBus, PSSMHANDLE pSSM)
947	{
948	/*
949	* Iterate thru all the devices.
950	*/
951	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
952	{
953	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
954	if (pDev)
955	{
956	pHlp->pfnSSMPutU32(pSSM, uDevFn);
957	pHlp->pfnSSMPutMem(pSSM, pDev->abConfig, 256); /* Only save 256 bytes here! */
958
959	pHlp->pfnSSMPutS32(pSSM, pDev->Int.s.uIrqPinState);
960
961	/* Save the type an size of all the regions. */
962	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
963	{
964	pHlp->pfnSSMPutU8(pSSM, pDev->Int.s.aIORegions[iRegion].type);
965	pHlp->pfnSSMPutU64(pSSM, pDev->Int.s.aIORegions[iRegion].size);
966	}
967	}
968	}
969	return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* terminator */
970	}
971
972
973	/**
974	* @callback_method_impl{FNSSMDEVSAVEEXEC}
975	*/
976	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
977	{
978	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
979	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
980
981	/*
982	* Bus state data.
983	*/
984	pHlp->pfnSSMPutU32(pSSM, pThis->uConfigReg);
985	pHlp->pfnSSMPutBool(pSSM, pThis->fUseIoApic);
986
987	/*
988	* Save IRQ states.
989	*/
990	for (unsigned i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
991	pHlp->pfnSSMPutU32(pSSM, pThis->Piix3.auPciLegacyIrqLevels[i]);
992	for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
993	pHlp->pfnSSMPutU32(pSSM, pThis->auPciApicIrqLevels[i]);
994
995	pHlp->pfnSSMPutU32(pSSM, pThis->Piix3.iAcpiIrqLevel);
996	pHlp->pfnSSMPutS32(pSSM, pThis->Piix3.iAcpiIrq);
997
998	pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* separator */
999
1000	/*
1001	* Join paths with pcibridgeR3SaveExec.
1002	*/
1003	return pciR3CommonSaveExec(pHlp, &pThis->PciBus, pSSM);
1004	}
1005
1006
1007	/**
1008	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
1009	*
1010	* @returns VBox status code.
1011	* @param pDevIns The device instance.
1012	* @param pBus The bus which data is being loaded.
1013	* @param pSSM The saved state handle.
1014	* @param uVersion The data version.
1015	* @param uPass The pass.
1016	*/
1017	static int pciR3CommonLoadExec(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1018	{
1019	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1020	uint32_t u32;
1021	int rc;
1022
1023	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1024
1025	/*
1026	* Iterate thru all the devices and write 0 to the COMMAND register so
1027	* that all the memory is unmapped before we start restoring the saved
1028	* mapping locations.
1029	*
1030	* The register value is restored afterwards so we can do proper
1031	* LogRels in devpciR3CommonRestoreConfig.
1032	*/
1033	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1034	{
1035	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1036	if (pDev)
1037	{
1038	uint16_t u16 = PCIDevGetCommand(pDev);
1039	devpciR3SetCfg(pDevIns, pDev, VBOX_PCI_COMMAND, 0 /u32Value/, 2 /cb/);
1040	PCIDevSetCommand(pDev, u16);
1041	Assert(PCIDevGetCommand(pDev) == u16);
1042	}
1043	}
1044
1045	/*
1046	* Iterate all the devices.
1047	*/
1048	for (uint32_t uDevFn = 0;; uDevFn++)
1049	{
1050	/* index / terminator */
1051	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
1052	if (RT_FAILURE(rc))
1053	return rc;
1054	if (u32 == UINT32_MAX)
1055	break;
1056	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1057	\|\| u32 < uDevFn)
1058	{
1059	AssertMsgFailed(("u32=%#x uDevFn=%#x\n", u32, uDevFn));
1060	return rc;
1061	}
1062
1063	/* skip forward to the device checking that no new devices are present. */
1064	for (; uDevFn < u32; uDevFn++)
1065	{
1066	if (pBus->apDevices[uDevFn])
1067	{
1068	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", uDevFn, pBus->apDevices[uDevFn]->pszNameR3,
1069	PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn])));
1070	if (pHlp->pfnSSMHandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1071	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1072	uDevFn, pBus->apDevices[uDevFn]->pszNameR3, PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn]));
1073	}
1074	}
1075
1076	/* get the data */
1077	union
1078	{
1079	PDMPCIDEV DevTmp;
1080	uint8_t abDevTmpPadding[RT_UOFFSETOF(PDMPCIDEV, abMsixState)];
1081	} u;
1082	RT_ZERO(u.DevTmp);
1083	u.DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1084	pHlp->pfnSSMGetMem(pSSM, u.DevTmp.abConfig, 256);
1085	if (uVersion < VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1086	{
1087	int32_t i32Temp;
1088	/* Irq value not needed anymore. */
1089	rc = pHlp->pfnSSMGetS32(pSSM, &i32Temp);
1090	if (RT_FAILURE(rc))
1091	return rc;
1092	}
1093	else
1094	{
1095	rc = pHlp->pfnSSMGetS32(pSSM, &u.DevTmp.Int.s.uIrqPinState);
1096	if (RT_FAILURE(rc))
1097	return rc;
1098	}
1099
1100	/* Load the region types and sizes. */
1101	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES)
1102	{
1103	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
1104	{
1105	pHlp->pfnSSMGetU8(pSSM, &u.DevTmp.Int.s.aIORegions[iRegion].type);
1106	rc = pHlp->pfnSSMGetU64(pSSM, &u.DevTmp.Int.s.aIORegions[iRegion].size);
1107	AssertLogRelRCReturn(rc, rc);
1108	}
1109	}
1110
1111	/* check that it's still around. */
1112	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1113	if (!pDev)
1114	{
1115	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", uDevFn,
1116	PCIDevGetVendorId(&u.DevTmp), PCIDevGetDeviceId(&u.DevTmp)));
1117	if (pHlp->pfnSSMHandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1118	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1119	uDevFn, PCIDevGetVendorId(&u.DevTmp), PCIDevGetDeviceId(&u.DevTmp));
1120	continue;
1121	}
1122
1123	/* match the vendor id assuming that this will never be changed. */
1124	if ( u.DevTmp.abConfig[0] != pDev->abConfig[0]
1125	\|\| u.DevTmp.abConfig[1] != pDev->abConfig[1])
1126	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1127	N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1128	uDevFn, pDev->pszNameR3, u.DevTmp.abConfig, pDev->abConfig);
1129
1130	/* commit the loaded device config. */
1131	rc = devpciR3CommonRestoreRegions(pHlp, pSSM, pDev, u.DevTmp.Int.s.aIORegions,
1132	uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES);
1133	if (RT_FAILURE(rc))
1134	break;
1135	devpciR3CommonRestoreConfig(pDevIns, pDev, &u.DevTmp.abConfig[0]);
1136
1137	pDev->Int.s.uIrqPinState = u.DevTmp.Int.s.uIrqPinState;
1138	}
1139
1140	return VINF_SUCCESS;
1141	}
1142
1143
1144	/**
1145	* @callback_method_impl{FNSSMDEVLOADEXEC}
1146	*/
1147	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1148	{
1149	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1150	PDEVPCIBUS pBus = &pThis->PciBus;
1151	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1152	uint32_t u32;
1153	int rc;
1154
1155	/*
1156	* Check the version.
1157	*/
1158	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1159	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1160	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1161
1162	/*
1163	* Bus state data.
1164	*/
1165	pHlp->pfnSSMGetU32(pSSM, &pThis->uConfigReg);
1166	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC)
1167	pHlp->pfnSSMGetBool(pSSM, &pThis->fUseIoApic);
1168
1169	/* Load IRQ states. */
1170	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1171	{
1172	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
1173	pHlp->pfnSSMGetU32V(pSSM, &pThis->Piix3.auPciLegacyIrqLevels[i]);
1174	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
1175	pHlp->pfnSSMGetU32V(pSSM, &pThis->auPciApicIrqLevels[i]);
1176
1177	pHlp->pfnSSMGetU32(pSSM, &pThis->Piix3.iAcpiIrqLevel);
1178	pHlp->pfnSSMGetS32(pSSM, &pThis->Piix3.iAcpiIrq);
1179	}
1180
1181	/* separator */
1182	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
1183	if (RT_FAILURE(rc))
1184	return rc;
1185	if (u32 != UINT32_MAX)
1186	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1187
1188	/*
1189	* The devices.
1190	*/
1191	return pciR3CommonLoadExec(pDevIns, pBus, pSSM, uVersion, uPass);
1192	}
1193
1194
1195	/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
1196
1197
1198	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
1199
1200	/**
1201	* @callback_method_impl{FNDBGFHANDLERDEV}
1202	*/
1203	static DECLCALLBACK(void) pciR3IrqRouteInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1204	{
1205	PPDMPCIDEV pPIIX3 = pDevIns->apPciDevs[1];
1206	NOREF(pszArgs);
1207
1208	uint16_t router = pPIIX3->uDevFn;
1209	pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1210	router >> 8, (router >> 3) & 0x1f, router & 0x7);
1211
1212	for (int i = 0; i < 4; ++i)
1213	{
1214	uint8_t irq_map = devpciR3GetByte(pPIIX3, 0x60 + i);
1215	if (irq_map & 0x80)
1216	pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1217	else
1218	pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1219	}
1220	}
1221
1222	/**
1223	* @callback_method_impl{FNDBGFHANDLERDEV, 'pirq'}
1224	*/
1225	DECLCALLBACK(void) devpciR3InfoPIRQ(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1226	{
1227	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1228	NOREF(pszArgs);
1229
1230	pHlp->pfnPrintf(pHlp, "PCI IRQ levels:\n");
1231	for (int i = 0; i < DEVPCI_LEGACY_IRQ_PINS; ++i)
1232	pHlp->pfnPrintf(pHlp, " IRQ%c: %u\n", 'A' + i, pGlobals->Piix3.auPciLegacyIrqLevels[i]);
1233	}
1234
1235
1236	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1237
1238	/**
1239	* @interface_method_impl{PDMDEVREG,pfnReset}
1240	*/
1241	static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
1242	{
1243	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1244	PDEVPCIBUS pBus = &pGlobals->PciBus;
1245
1246	/* PCI-specific reset for each device. */
1247	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1248	{
1249	if (pBus->apDevices[uDevFn])
1250	devpciR3ResetDevice(pDevIns, pBus->apDevices[uDevFn]);
1251	}
1252
1253	pciR3Piix3Reset(pDevIns->apPciDevs[1]);
1254	}
1255
1256
1257	/**
1258	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1259	*/
1260	static DECLCALLBACK(int) pciR3Destruct(PPDMDEVINS pDevIns)
1261	{
1262	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1263	if (pGlobals->PciBus.papBridgesR3)
1264	{
1265	PDMDevHlpMMHeapFree(pDevIns, pGlobals->PciBus.papBridgesR3);
1266	pGlobals->PciBus.papBridgesR3 = NULL;
1267	}
1268	return VINF_SUCCESS;
1269	}
1270
1271
1272	/**
1273	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1274	*/
1275	static DECLCALLBACK(int) pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1276	{
1277	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1278	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1279	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1280	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1281	RT_NOREF(iInstance);
1282	Assert(iInstance == 0);
1283
1284	/*
1285	* Validate and read configuration.
1286	*/
1287	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "IOAPIC", "");
1288
1289	/* query whether we got an IOAPIC */
1290	bool fUseIoApic;
1291	int rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
1292	if (RT_FAILURE(rc))
1293	return PDMDEV_SET_ERROR(pDevIns, rc,
1294	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
1295
1296	Log(("PCI: fUseIoApic=%RTbool fR0Enabled=%RTbool fRCEnabled=%RTbool\n", fUseIoApic, pDevIns->fR0Enabled, pDevIns->fRCEnabled));
1297
1298	/*
1299	* Init data and register the PCI bus.
1300	*/
1301	pGlobals->uPciBiosIo = 0xc000;
1302	pGlobals->uPciBiosMmio = 0xf0000000;
1303	memset((void *)&pGlobals->Piix3.auPciLegacyIrqLevels, 0, sizeof(pGlobals->Piix3.auPciLegacyIrqLevels));
1304	pGlobals->fUseIoApic = fUseIoApic;
1305	memset((void *)&pGlobals->auPciApicIrqLevels, 0, sizeof(pGlobals->auPciApicIrqLevels));
1306
1307	pGlobals->PciBus.fTypePiix3 = true;
1308	pGlobals->PciBus.fTypeIch9 = false;
1309	pGlobals->PciBus.fPureBridge = false;
1310	pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns,
1311	sizeof(PPDMPCIDEV)
1312	* RT_ELEMENTS(pGlobals->PciBus.apDevices));
1313	AssertLogRelReturn(pGlobals->PciBus.papBridgesR3, VERR_NO_MEMORY);
1314
1315	PDEVPCIBUS pBus = &pGlobals->PciBus;
1316	PDMPCIBUSREGCC PciBusReg;
1317	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1318	PciBusReg.pfnRegisterR3 = devpciR3CommonRegisterDevice;
1319	PciBusReg.pfnRegisterMsiR3 = NULL;
1320	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1321	PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
1322	PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
1323	PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
1324	PciBusReg.pfnSetIrqR3 = pciSetIrq;
1325	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1326	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
1327	if (RT_FAILURE(rc))
1328	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
1329	Assert(pBus->iBus == 0);
1330	if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1331	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1332	N_("PCI helper version mismatch; got %#x expected %#x"),
1333	pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1334
1335	/* Disable default device locking. */
1336	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1337	AssertRCReturn(rc, rc);
1338
1339	/*
1340	* Fill in PCI configs and add them to the bus.
1341	*/
1342	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1343	AssertPtr(pPciDev);
1344
1345	/* i440FX */
1346	PCIDevSetVendorId( pPciDev, 0x8086); /* Intel */
1347	PCIDevSetDeviceId( pPciDev, 0x1237);
1348	PCIDevSetRevisionId(pPciDev, 0x02);
1349	PCIDevSetClassSub( pPciDev, 0x00); /* host2pci */
1350	PCIDevSetClassBase( pPciDev, 0x06); /* PCI_bridge */
1351	PCIDevSetHeaderType(pPciDev, 0x00);
1352	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, 0 /fFlags/, 0 /uPciDevNo/, 0 /uPciFunNo/, "i440FX");
1353	AssertLogRelRCReturn(rc, rc);
1354
1355	/* PIIX3 */
1356	PPDMPCIDEV pPiix3PciDev = pDevIns->apPciDevs[1];
1357	PCIDevSetVendorId( pPiix3PciDev, 0x8086); /* Intel */
1358	PCIDevSetDeviceId( pPiix3PciDev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
1359	PCIDevSetClassSub( pPiix3PciDev, 0x01); /* PCI_ISA */
1360	PCIDevSetClassBase( pPiix3PciDev, 0x06); /* PCI_bridge */
1361	PCIDevSetHeaderType(pPiix3PciDev, 0x80); /* PCI_multifunction, generic */
1362	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPiix3PciDev, 0 /fFlags/, 1 /uPciDevNo/, 0 /uPciFunNo/, "PIIX3");
1363	AssertLogRelRCReturn(rc, rc);
1364	pciR3Piix3Reset(pDevIns->apPciDevs[1]);
1365
1366	pBus->iDevSearch = 16;
1367
1368	/*
1369	* Register I/O ports and save state.
1370	*/
1371	static const IOMIOPORTDESC s_aAddrDesc[] = { { "PCI address", "PCI address", NULL, NULL }, { NULL, NULL, NULL, NULL } };
1372	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cf8, 1, pciIOPortAddressWrite, pciIOPortAddressRead, "i440FX (PCI)", s_aAddrDesc,
1373	&pGlobals->hIoPortAddress);
1374	AssertLogRelRCReturn(rc, rc);
1375
1376	static const IOMIOPORTDESC s_aDataDesc[] = { { "PCI data", "PCI data", NULL, NULL }, { NULL, NULL, NULL, NULL } };
1377	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cfc, 4, pciIOPortDataWrite, pciIOPortDataRead, "i440FX (PCI)", s_aDataDesc,
1378	&pGlobals->hIoPortData);
1379	AssertLogRelRCReturn(rc, rc);
1380
1381	static const IOMIOPORTDESC s_aMagicDesc[] = { { "PCI magic", NULL, NULL, NULL }, { NULL, NULL, NULL, NULL } };
1382	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0410, 1, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead,
1383	"i440FX (Fake PCI BIOS trigger)", s_aMagicDesc, &pGlobals->hIoPortMagic);
1384	AssertLogRelRCReturn(rc, rc);
1385
1386
1387	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
1388	NULL, NULL, NULL,
1389	NULL, pciR3SaveExec, NULL,
1390	NULL, pciR3LoadExec, NULL);
1391	AssertLogRelRCReturn(rc, rc);
1392
1393	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
1394	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
1395	devpciR3InfoPci);
1396	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", devpciR3InfoPciIrq);
1397	PDMDevHlpDBGFInfoRegister(pDevIns, "pirq", "Display PIRQ state. (no arguments)", devpciR3InfoPIRQ);
1398	PDMDevHlpDBGFInfoRegister(pDevIns, "irqroute", "Display PCI IRQ routing. (no arguments)", pciR3IrqRouteInfo);
1399
1400	return VINF_SUCCESS;
1401	}
1402
1403	#else /* !IN_RING3 */
1404
1405	/**
1406	* @interface_method_impl{PDMDEVREGR0,pfnConstruct}
1407	*/
1408	static DECLCALLBACK(int) pciRZRootConstruct(PPDMDEVINS pDevIns)
1409	{
1410	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1411	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1412	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1413
1414	/* Mirror the ring-3 device lock disabling: */
1415	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1416	AssertRCReturn(rc, rc);
1417
1418	/* Set up the RZ PCI bus callbacks: */
1419	PDMPCIBUSREGCC PciBusReg;
1420	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1421	PciBusReg.iBus = pGlobals->PciBus.iBus;
1422	PciBusReg.pfnSetIrq = pciSetIrq;
1423	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1424	rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
1425	AssertRCReturn(rc, rc);
1426
1427	/* Set up I/O port callbacks, except for the magic port: */
1428	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pGlobals->hIoPortAddress, pciIOPortAddressWrite, pciIOPortAddressRead, NULL);
1429	AssertLogRelRCReturn(rc, rc);
1430
1431	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pGlobals->hIoPortData, pciIOPortDataWrite, pciIOPortDataRead, NULL);
1432	AssertLogRelRCReturn(rc, rc);
1433
1434	return rc;
1435	}
1436
1437	#endif /* !IN_RING3 */
1438
1439	/**
1440	* The device registration structure.
1441	*/
1442	const PDMDEVREG g_DevicePCI =
1443	{
1444	/* .u32Version = */ PDM_DEVREG_VERSION,
1445	/* .uReserved0 = */ 0,
1446	/* .szName = */ "pci",
1447	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1448	/* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI,
1449	/* .cMaxInstances = */ 1,
1450	/* .uSharedVersion = */ 42,
1451	/* .cbInstanceShared = */ sizeof(DEVPCIROOT),
1452	/* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
1453	/* .cbInstanceRC = */ sizeof(DEVPCIBUSRC),
1454	/* .cMaxPciDevices = */ 2,
1455	/* .cMaxMsixVectors = */ 0,
1456	/* .pszDescription = */ "i440FX PCI bridge and PIIX3 ISA bridge.",
1457	#if defined(IN_RING3)
1458	/* .pszRCMod = */ "VBoxDDRC.rc",
1459	/* .pszR0Mod = */ "VBoxDDR0.r0",
1460	/* .pfnConstruct = */ pciR3Construct,
1461	/* .pfnDestruct = */ pciR3Destruct,
1462	/* .pfnRelocate = */ NULL,
1463	/* .pfnMemSetup = */ NULL,
1464	/* .pfnPowerOn = */ NULL,
1465	/* .pfnReset = */ pciR3Reset,
1466	/* .pfnSuspend = */ NULL,
1467	/* .pfnResume = */ NULL,
1468	/* .pfnAttach = */ NULL,
1469	/* .pfnDetach = */ NULL,
1470	/* .pfnQueryInterface = */ NULL,
1471	/* .pfnInitComplete = */ NULL,
1472	/* .pfnPowerOff = */ NULL,
1473	/* .pfnSoftReset = */ NULL,
1474	/* .pfnReserved0 = */ NULL,
1475	/* .pfnReserved1 = */ NULL,
1476	/* .pfnReserved2 = */ NULL,
1477	/* .pfnReserved3 = */ NULL,
1478	/* .pfnReserved4 = */ NULL,
1479	/* .pfnReserved5 = */ NULL,
1480	/* .pfnReserved6 = */ NULL,
1481	/* .pfnReserved7 = */ NULL,
1482	#elif defined(IN_RING0)
1483	/* .pfnEarlyConstruct = */ NULL,
1484	/* .pfnConstruct = */ pciRZRootConstruct,
1485	/* .pfnDestruct = */ NULL,
1486	/* .pfnFinalDestruct = */ NULL,
1487	/* .pfnRequest = */ NULL,
1488	/* .pfnReserved0 = */ NULL,
1489	/* .pfnReserved1 = */ NULL,
1490	/* .pfnReserved2 = */ NULL,
1491	/* .pfnReserved3 = */ NULL,
1492	/* .pfnReserved4 = */ NULL,
1493	/* .pfnReserved5 = */ NULL,
1494	/* .pfnReserved6 = */ NULL,
1495	/* .pfnReserved7 = */ NULL,
1496	#elif defined(IN_RC)
1497	/* .pfnConstruct = */ pciRZRootConstruct,
1498	/* .pfnReserved0 = */ NULL,
1499	/* .pfnReserved1 = */ NULL,
1500	/* .pfnReserved2 = */ NULL,
1501	/* .pfnReserved3 = */ NULL,
1502	/* .pfnReserved4 = */ NULL,
1503	/* .pfnReserved5 = */ NULL,
1504	/* .pfnReserved6 = */ NULL,
1505	/* .pfnReserved7 = */ NULL,
1506	#else
1507	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1508	#endif
1509	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1510
1511	};
1512
1513
1514
1515	/* -=-=-=-=-=- The PCI bridge specific bits -=-=-=-=-=- */
1516
1517	/**
1518	* @interface_method_impl{PDMPCIBUSREGR3,pfnSetIrqR3}
1519	*/
1520	static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
1521	{
1522	LogFlow(("pcibridgeSetIrq: %p %u %u %#x\n", pPciDev, iIrq, iLevel, uTagSrc));
1523
1524	/*
1525	* The PCI-to-PCI bridge specification defines how the interrupt pins
1526	* are routed from the secondary to the primary bus (see chapter 9).
1527	* iIrq gives the interrupt pin the pci device asserted.
1528	* We change iIrq here according to the spec and call the SetIrq function
1529	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
1530	*/
1531	PDEVPCIBUS pBus;
1532	uint8_t uDevFnBridge;
1533	int iIrqPinBridge;
1534	PPDMDEVINS pDevInsBus = devpcibridgeCommonSetIrqRootWalk(pDevIns, pPciDev, iIrq, &pBus, &uDevFnBridge, &iIrqPinBridge);
1535	AssertReturnVoid(pDevInsBus);
1536	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
1537	Assert(pDevInsBus->pReg == &g_DevicePCI);
1538
1539	pciSetIrqInternal(pDevInsBus, DEVPCIBUS_2_DEVPCIROOT(pBus), PDMINS_2_DATA_CC(pDevInsBus, PDEVPCIBUSCC),
1540	uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
1541	}
1542
1543	#ifdef IN_RING3
1544
1545	/**
1546	* @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
1547	*/
1548	static DECLCALLBACK(VBOXSTRICTRC) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
1549	uint32_t u32Address, unsigned cb, uint32_t u32Value)
1550	{
1551	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d u32Value=%u\n", pDevIns, iBus, iDevice, u32Address, cb, u32Value));
1552	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1553	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1554
1555	/* If the current bus is not the target bus search for the bus which contains the device. */
1556	if (iBus != pDevIns->apPciDevs[0]->abConfig[VBOX_PCI_SECONDARY_BUS])
1557	{
1558	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1559	if (pBridgeDevice)
1560	{
1561	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1562	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice,
1563	u32Address, cb, u32Value);
1564	}
1565	}
1566	else
1567	{
1568	/* This is the target bus, pass the write to the device. */
1569	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1570	if (pPciDev)
1571	{
1572	LogFunc(("%s: addr=%02x val=%08x len=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
1573	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
1574	if (pPciDev->Int.s.pfnConfigWrite)
1575	rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, u32Value);
1576	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
1577	rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
1578	pPciDev, u32Address, cb, u32Value);
1579	}
1580	}
1581	return rcStrict;
1582	}
1583
1584
1585	/**
1586	* @callback_method_impl{FNPCIBRIDGECONFIGREAD}
1587	*/
1588	static DECLCALLBACK(VBOXSTRICTRC) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
1589	uint32_t u32Address, unsigned cb, uint32_t *pu32Value)
1590	{
1591	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1592	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1593	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1594
1595	/* If the current bus is not the target bus search for the bus which contains the device. */
1596	if (iBus != pDevIns->apPciDevs[0]->abConfig[VBOX_PCI_SECONDARY_BUS])
1597	{
1598	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1599	if (pBridgeDevice)
1600	{
1601	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
1602	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns),
1603	iBus, iDevice, u32Address, cb, pu32Value);
1604	}
1605	else
1606	*pu32Value = UINT32_MAX;
1607	}
1608	else
1609	{
1610	/* This is the target bus, pass the read to the device. */
1611	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1612	if (pPciDev)
1613	{
1614	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
1615	if (pPciDev->Int.s.pfnConfigRead)
1616	rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, pu32Value);
1617	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
1618	rcStrict = devpciR3CommonConfigReadWorker(pPciDev, u32Address, cb, pu32Value);
1619
1620	LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, *pu32Value, cb));
1621	}
1622	else
1623	*pu32Value = UINT32_MAX;
1624	}
1625
1626	return rcStrict;
1627	}
1628
1629
1630	/**
1631	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1632	*/
1633	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1634	{
1635	return pciR3CommonSaveExec(pDevIns->pHlpR3, PDMINS_2_DATA(pDevIns, PDEVPCIBUS), pSSM);
1636	}
1637
1638
1639	/**
1640	* @callback_method_impl{FNSSMDEVLOADEXEC}
1641	*/
1642	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1643	{
1644	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1645	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1646	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1647	return pciR3CommonLoadExec(pDevIns, pThis, pSSM, uVersion, uPass);
1648	}
1649
1650
1651	/**
1652	* @interface_method_impl{PDMDEVREG,pfnReset}
1653	*/
1654	static DECLCALLBACK(void) pcibridgeR3Reset(PPDMDEVINS pDevIns)
1655	{
1656	/* Reset config space to default values. */
1657	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1658	pPciDev->abConfig[VBOX_PCI_PRIMARY_BUS] = 0;
1659	pPciDev->abConfig[VBOX_PCI_SECONDARY_BUS] = 0;
1660	pPciDev->abConfig[VBOX_PCI_SUBORDINATE_BUS] = 0;
1661	}
1662
1663
1664	/**
1665	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1666	*/
1667	static DECLCALLBACK(int) pcibridgeR3Destruct(PPDMDEVINS pDevIns)
1668	{
1669	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1670	if (pBus->papBridgesR3)
1671	{
1672	PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
1673	pBus->papBridgesR3 = NULL;
1674	}
1675	return VINF_SUCCESS;
1676	}
1677
1678
1679	/**
1680	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1681	*/
1682	static DECLCALLBACK(int) pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1683	{
1684	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1685	RT_NOREF(iInstance, pCfg);
1686	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1687	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1688
1689	/*
1690	* Validate and read configuration (none left).
1691	*/
1692	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "", "");
1693	Log(("PCI: fRCEnabled=%RTbool fR0Enabled=%RTbool\n", pDevIns->fRCEnabled, pDevIns->fR0Enabled));
1694
1695	/*
1696	* Init data and register the PCI bus.
1697	*/
1698	pBus->fTypePiix3 = true;
1699	pBus->fTypeIch9 = false;
1700	pBus->fPureBridge = true;
1701	pBus->papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pBus->apDevices));
1702	AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
1703
1704	PDMPCIBUSREGCC PciBusReg;
1705	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1706	PciBusReg.pfnRegisterR3 = devpcibridgeR3CommonRegisterDevice;
1707	PciBusReg.pfnRegisterMsiR3 = NULL;
1708	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1709	PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
1710	PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
1711	PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
1712	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
1713	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1714	int rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
1715	if (RT_FAILURE(rc))
1716	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
1717	Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
1718	if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1719	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1720	N_("PCI helper version mismatch; got %#x expected %#x"),
1721	pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1722
1723	/*
1724	* Fill in PCI configs and add them to the bus.
1725	*/
1726	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1727	PCIDevSetVendorId( pPciDev, 0x8086); /* Intel */
1728	PCIDevSetDeviceId( pPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
1729	PCIDevSetRevisionId(pPciDev, 0xf2);
1730	PCIDevSetClassSub( pPciDev, 0x04); /* pci2pci */
1731	PCIDevSetClassBase( pPciDev, 0x06); /* PCI_bridge */
1732	PCIDevSetClassProg( pPciDev, 0x01); /* Supports subtractive decoding. */
1733	PCIDevSetHeaderType(pPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
1734	PCIDevSetCommand( pPciDev, 0x0000);
1735	PCIDevSetStatus( pPciDev, 0x0020); /* 66MHz Capable. */
1736	PCIDevSetInterruptLine(pPciDev, 0x00); /* This device does not assert interrupts. */
1737
1738	/*
1739	* This device does not generate interrupts. Interrupt delivery from
1740	* devices attached to the bus is unaffected.
1741	*/
1742	PCIDevSetInterruptPin(pPciDev, 0x00);
1743
1744	/*
1745	* Register this PCI bridge. The called function will take care on which bus we will get registered.
1746	*/
1747	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, PDMPCIDEVREG_F_PCI_BRIDGE, PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
1748	PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "pcibridge");
1749	if (RT_FAILURE(rc))
1750	return rc;
1751	pPciDev->Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
1752	pPciDev->Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
1753
1754	pBus->iDevSearch = 0;
1755
1756	/*
1757	* Register SSM handlers. We use the same saved state version as for the host bridge
1758	* to make changes easier.
1759	*/
1760	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
1761	NULL, NULL, NULL,
1762	NULL, pcibridgeR3SaveExec, NULL,
1763	NULL, pcibridgeR3LoadExec, NULL);
1764	if (RT_FAILURE(rc))
1765	return rc;
1766
1767	return VINF_SUCCESS;
1768	}
1769
1770	#else /* !IN_RING3 */
1771
1772	/**
1773	* @interface_method_impl{PDMDEVREGR0,pfnConstruct}
1774	*/
1775	static DECLCALLBACK(int) pcibridgeRZConstruct(PPDMDEVINS pDevIns)
1776	{
1777	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1778	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1779	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1780
1781	PDMPCIBUSREGCC PciBusReg;
1782	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1783	PciBusReg.iBus = pBus->iBus;
1784	PciBusReg.pfnSetIrq = pcibridgeSetIrq;
1785	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1786	int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
1787	AssertRC(rc);
1788
1789	return rc;
1790	}
1791
1792	#endif /* !IN_RING3 */
1793
1794	/**
1795	* The device registration structure
1796	* for the PCI-to-PCI bridge.
1797	*/
1798	const PDMDEVREG g_DevicePCIBridge =
1799	{
1800	/* .u32Version = */ PDM_DEVREG_VERSION,
1801	/* .uReserved0 = */ 0,
1802	/* .szName = */ "pcibridge",
1803	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1804	/* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI,
1805	/* .cMaxInstances = */ ~0U,
1806	/* .uSharedVersion = */ 42,
1807	/* .cbInstanceShared = */ sizeof(DEVPCIBUS),
1808	/* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
1809	/* .cbInstanceRC = */ 0,
1810	/* .cMaxPciDevices = */ 1,
1811	/* .cMaxMsixVectors = */ 0,
1812	/* .pszDescription = */ "82801 Mobile PCI to PCI bridge",
1813	#if defined(IN_RING3)
1814	/* .pszRCMod = */ "VBoxDDRC.rc",
1815	/* .pszR0Mod = */ "VBoxDDR0.r0",
1816	/* .pfnConstruct = */ pcibridgeR3Construct,
1817	/* .pfnDestruct = */ pcibridgeR3Destruct,
1818	/* .pfnRelocate = */ NULL,
1819	/* .pfnMemSetup = */ NULL,
1820	/* .pfnPowerOn = */ NULL,
1821	/* .pfnReset = */ pcibridgeR3Reset,
1822	/* .pfnSuspend = */ NULL,
1823	/* .pfnResume = */ NULL,
1824	/* .pfnAttach = */ NULL,
1825	/* .pfnDetach = */ NULL,
1826	/* .pfnQueryInterface = */ NULL,
1827	/* .pfnInitComplete = */ NULL,
1828	/* .pfnPowerOff = */ NULL,
1829	/* .pfnSoftReset = */ NULL,
1830	/* .pfnReserved0 = */ NULL,
1831	/* .pfnReserved1 = */ NULL,
1832	/* .pfnReserved2 = */ NULL,
1833	/* .pfnReserved3 = */ NULL,
1834	/* .pfnReserved4 = */ NULL,
1835	/* .pfnReserved5 = */ NULL,
1836	/* .pfnReserved6 = */ NULL,
1837	/* .pfnReserved7 = */ NULL,
1838	#elif defined(IN_RING0)
1839	/* .pfnEarlyConstruct = */ NULL,
1840	/* .pfnConstruct = */ pcibridgeRZConstruct,
1841	/* .pfnDestruct = */ NULL,
1842	/* .pfnFinalDestruct = */ NULL,
1843	/* .pfnRequest = */ NULL,
1844	/* .pfnReserved0 = */ NULL,
1845	/* .pfnReserved1 = */ NULL,
1846	/* .pfnReserved2 = */ NULL,
1847	/* .pfnReserved3 = */ NULL,
1848	/* .pfnReserved4 = */ NULL,
1849	/* .pfnReserved5 = */ NULL,
1850	/* .pfnReserved6 = */ NULL,
1851	/* .pfnReserved7 = */ NULL,
1852	#elif defined(IN_RC)
1853	/* .pfnConstruct = */ pcibridgeRZConstruct,
1854	/* .pfnReserved0 = */ NULL,
1855	/* .pfnReserved1 = */ NULL,
1856	/* .pfnReserved2 = */ NULL,
1857	/* .pfnReserved3 = */ NULL,
1858	/* .pfnReserved4 = */ NULL,
1859	/* .pfnReserved5 = */ NULL,
1860	/* .pfnReserved6 = */ NULL,
1861	/* .pfnReserved7 = */ NULL,
1862	#else
1863	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1864	#endif
1865	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1866	};
1867

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 97698

Download in other formats: