DevPCI.cpp@ 91968

Last change on this file since 91968 was 91936, checked in by vboxsync, 3 years ago
Devices/Bus/DevPCI: Remove unused code, bugref:10074
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
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1	/* $Id: DevPCI.cpp 91936 2021-10-21 11:12:40Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*
5	* @remarks New code shall be added to DevPciIch9.cpp as that will become
6	* the common PCI bus code soon. Don't fix code in both DevPCI.cpp
7	* and DevPciIch9.cpp when it's possible to just make the latter
8	* version common. Common code uses the 'devpci' prefix, is
9	* prototyped in DevPciInternal.h, and is defined in DevPciIch9.cpp.
10	*/
11
12	/*
13	* Copyright (C) 2006-2020 Oracle Corporation
14	*
15	* This file is part of VirtualBox Open Source Edition (OSE), as
16	* available from http://www.virtualbox.org. This file is free software;
17	* you can redistribute it and/or modify it under the terms of the GNU
18	* General Public License (GPL) as published by the Free Software
19	* Foundation, in version 2 as it comes in the "COPYING" file of the
20	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
21	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* QEMU PCI bus manager
27	*
28	* Copyright (c) 2004 Fabrice Bellard
29	*
30	* Permission is hereby granted, free of charge, to any person obtaining a copy
31	* of this software and associated documentation files (the "Software"), to deal
32	* in the Software without restriction, including without limitation the rights
33	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
34	* copies of the Software, and to permit persons to whom the Software is
35	* furnished to do so, subject to the following conditions:
36	*
37	* The above copyright notice and this permission notice shall be included in
38	* all copies or substantial portions of the Software.
39	*
40	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
41	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
42	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
44	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
45	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
46	* THE SOFTWARE.
47	*/
48
49
50	/*********************************************************************************************************************************
51	* Header Files *
52	*********************************************************************************************************************************/
53	#define LOG_GROUP LOG_GROUP_DEV_PCI
54	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
55	#include <VBox/vmm/pdmpcidev.h>
56	#include <VBox/vmm/pdmdev.h>
57	#include <VBox/vmm/mm.h>
58	#include <iprt/asm.h>
59	#include <iprt/assert.h>
60	#include <iprt/string.h>
61
62	#include "PciInline.h"
63	#include "VBoxDD.h"
64	#include "DevPciInternal.h"
65
66
67	/*********************************************************************************************************************************
68	* Defined Constants And Macros *
69	*********************************************************************************************************************************/
70	/** Saved state version of the PCI bus device. */
71	#define VBOX_PCI_SAVED_STATE_VERSION VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES
72	/** Adds I/O region types and sizes for dealing changes in resource regions. */
73	#define VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES 4
74	/** Before region sizes, the first named one.
75	* Looking at the code though, we support even older version. */
76	#define VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES 3
77	/** Notes whether we use the I/O APIC. */
78	#define VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC 2
79
80
81	/*********************************************************************************************************************************
82	* Internal Functions *
83	*********************************************************************************************************************************/
84	RT_C_DECLS_BEGIN
85
86	static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
87
88	#ifdef IN_RING3
89	DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus);
90	#endif
91
92	RT_C_DECLS_END
93
94	#define DEBUG_PCI
95
96	#define PCI_VENDOR_ID 0x00 /* 16 bits */
97	#define PCI_DEVICE_ID 0x02 /* 16 bits */
98	#define PCI_COMMAND 0x04 /* 16 bits */
99	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
100	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
101	#define PCI_CLASS_DEVICE 0x0a /* Device class */
102	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
103	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
104	#define PCI_MIN_GNT 0x3e /* 8 bits */
105	#define PCI_MAX_LAT 0x3f /* 8 bits */
106
107
108	static VBOXSTRICTRC pci_data_write(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, uint32_t addr, uint32_t u32Value, int cb)
109	{
110	LogFunc(("addr=%08x u32Value=%08x cb=%d\n", pGlobals->uConfigReg, u32Value, cb));
111
112	if (!(pGlobals->uConfigReg & (1 << 31)))
113	return VINF_SUCCESS;
114	if ((pGlobals->uConfigReg & 0x3) != 0)
115	return VINF_SUCCESS;
116
117	uint8_t const iBus = (pGlobals->uConfigReg >> 16) & 0xff;
118	uint8_t const iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
119	#ifdef IN_RING3
120	uint32_t const config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
121	#endif
122	RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
123
124	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
125	if (iBus != 0)
126	{
127	if (pGlobals->PciBus.cBridges)
128	{
129	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
130	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
131	if (pBridgeDevice)
132	{
133	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
134	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus,
135	iDevice, config_addr, cb, u32Value);
136	}
137	#else
138	RT_NOREF(pDevIns, addr, u32Value, cb);
139	rcStrict = VINF_IOM_R3_IOPORT_WRITE;
140	#endif
141	}
142	}
143	else
144	{
145	R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[iDevice];
146	if (pPciDev)
147	{
148	#ifdef IN_RING3
149	LogFunc(("%s: addr=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, config_addr, u32Value, cb));
150	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
151	if (pPciDev->Int.s.pfnConfigWrite)
152	rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, config_addr, cb, u32Value);
153	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
154	rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
155	pPciDev, config_addr, cb, u32Value);
156	#else
157	rcStrict = VINF_IOM_R3_IOPORT_WRITE;
158	#endif
159	}
160	}
161	return rcStrict;
162	}
163
164	static VBOXSTRICTRC pci_data_read(PDEVPCIROOT pGlobals, uint32_t addr, int cb, uint32_t *pu32Value)
165	{
166	*pu32Value = UINT32_MAX;
167
168	if (!(pGlobals->uConfigReg & (1 << 31)))
169	return VINF_SUCCESS;
170	if ((pGlobals->uConfigReg & 0x3) != 0)
171	return VINF_SUCCESS;
172	uint8_t const iBus = (pGlobals->uConfigReg >> 16) & 0xff;
173	uint8_t const iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
174	#ifdef IN_RING3
175	uint32_t const config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
176	#endif
177	RT_UNTRUSTED_VALIDATED_FENCE();
178
179	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
180	if (iBus != 0)
181	{
182	if (pGlobals->PciBus.cBridges)
183	{
184	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
185	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
186	if (pBridgeDevice)
187	{
188	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
189	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns),
190	iBus, iDevice, config_addr, cb, pu32Value);
191	}
192	#else
193	RT_NOREF(addr, cb);
194	rcStrict = VINF_IOM_R3_IOPORT_READ;
195	#endif
196	}
197	}
198	else
199	{
200	R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[iDevice];
201	if (pPciDev)
202	{
203	#ifdef IN_RING3
204	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
205	if (pPciDev->Int.s.pfnConfigRead)
206	rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, config_addr, cb, pu32Value);
207	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
208	rcStrict = devpciR3CommonConfigReadWorker(pPciDev, config_addr, cb, pu32Value);
209	LogFunc(("%s: addr=%02x val=%08x cb=%d\n", pPciDev->pszNameR3, config_addr, *pu32Value, cb));
210	#else
211	NOREF(cb);
212	rcStrict = VINF_IOM_R3_IOPORT_READ;
213	#endif
214	}
215	}
216
217	return rcStrict;
218	}
219
220
221
222	/* return the global irq number corresponding to a given device irq
223	pin. We could also use the bus number to have a more precise
224	mapping.
225	This is the implementation note described in the PCI spec chapter 2.2.6 */
226	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
227	{
228	int slot_addend;
229	slot_addend = (uDevFn >> 3) - 1;
230	return (irq_num + slot_addend) & 3;
231	}
232
233	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
234	{
235	return (irq_num + (uDevFn >> 3)) & 7;
236	}
237
238	static inline int get_pci_irq_apic_level(PDEVPCIROOT pGlobals, int irq_num)
239	{
240	return (pGlobals->auPciApicIrqLevels[irq_num] != 0);
241	}
242
243	static void apic_set_irq(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PDEVPCIBUSCC pBusCC,
244	uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, int iAcpiIrq, uint32_t uTagSrc)
245	{
246	/* This is only allowed to be called with a pointer to the host bus. */
247	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
248	uint16_t const uBusDevFn = PCIBDF_MAKE(pBus->iBus, uDevFn);
249
250	if (iAcpiIrq == -1) {
251	int apic_irq, apic_level;
252	PDEVPCIROOT pGlobals = DEVPCIBUS_2_DEVPCIROOT(pBus);
253	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
254
255	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
256	ASMAtomicIncU32(&pGlobals->auPciApicIrqLevels[irq_num]);
257	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
258	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
259
260	apic_irq = irq_num + 0x10;
261	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
262	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
263	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
264	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, apic_irq, apic_level, uTagSrc);
265
266	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
267	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
268	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
269	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
270	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
271	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
272	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, apic_irq, apic_level, uTagSrc);
273	}
274	} else {
275	Log3Func(("%s: irq_num1=%d level=%d iAcpiIrq=%d\n", R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iAcpiIrq));
276	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, iAcpiIrq, iLevel, uTagSrc);
277	}
278	}
279
280	DECLINLINE(int) get_pci_irq_level(PDEVPCIROOT pGlobals, int irq_num)
281	{
282	return (pGlobals->Piix3.auPciLegacyIrqLevels[irq_num] != 0);
283	}
284
285	/**
286	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
287	*
288	* @param pDevIns The PDM device instance for the PCI bus.
289	* @param pGlobals Device instance of the host PCI bus.
290	* @param pBusCC Context specific data for the PCI bus.
291	* @param uDevFn The device number on the host bus which will raise the IRQ
292	* @param pPciDev The PCI device structure which raised the interrupt.
293	* @param iIrq IRQ number to set.
294	* @param iLevel IRQ level.
295	* @param uTagSrc The IRQ tag and source ID (for tracing).
296	* @remark uDevFn and pPciDev->uDevFn are not the same if the device is behind
297	* a bridge. In that case uDevFn will be the slot of the bridge which
298	* is needed to calculate the PIRQ value.
299	*/
300	static void pciSetIrqInternal(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, PDEVPCIBUSCC pBusCC,
301	uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
302	{
303	PDEVPCIBUS pBus = &pGlobals->PciBus;
304	uint8_t *pbCfg = pDevIns->apPciDevs[1]->abConfig;
305	const bool fIsAcpiDevice = pPciDev->abConfig[2] == 0x13 && pPciDev->abConfig[3] == 0x71;
306	/* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
307	* is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
308	* See the \_SB_.PCI0._PRT method in vbox.dsl.
309	*/
310	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
311	int pic_irq, pic_level;
312
313	/* Check if the state changed. */
314	if (pPciDev->Int.s.uIrqPinState != iLevel)
315	{
316	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
317
318	/* Send interrupt to I/O APIC only. */
319	if (fIsApicEnabled)
320	{
321	if (fIsAcpiDevice)
322	/*
323	* ACPI needs special treatment since SCI is hardwired and
324	* should not be affected by PCI IRQ routing tables at the
325	* same time SCI IRQ is shared in PCI sense hence this
326	* kludge (i.e. we fetch the hardwired value from ACPIs
327	* PCI device configuration space).
328	*/
329	apic_set_irq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, -1, iLevel, pPciDev->abConfig[PCI_INTERRUPT_LINE], uTagSrc);
330	else
331	apic_set_irq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
332	return;
333	}
334
335	if (fIsAcpiDevice)
336	{
337	/* As per above treat ACPI in a special way */
338	pic_irq = pPciDev->abConfig[PCI_INTERRUPT_LINE];
339	pGlobals->Piix3.iAcpiIrq = pic_irq;
340	pGlobals->Piix3.iAcpiIrqLevel = iLevel & PDM_IRQ_LEVEL_HIGH;
341	}
342	else
343	{
344	int irq_num;
345	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
346
347	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
348	ASMAtomicIncU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
349	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
350	ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
351
352	/* now we change the pic irq level according to the piix irq mappings */
353	pic_irq = pbCfg[0x60 + irq_num];
354	if (pic_irq >= 16)
355	{
356	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
357	{
358	ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
359	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
360	}
361
362	return;
363	}
364	}
365
366	/* the pic level is the logical OR of all the PCI irqs mapped to it */
367	pic_level = 0;
368	if (pic_irq == pbCfg[0x60])
369	pic_level \|= get_pci_irq_level(pGlobals, 0); /* PIRQA */
370	if (pic_irq == pbCfg[0x61])
371	pic_level \|= get_pci_irq_level(pGlobals, 1); /* PIRQB */
372	if (pic_irq == pbCfg[0x62])
373	pic_level \|= get_pci_irq_level(pGlobals, 2); /* PIRQC */
374	if (pic_irq == pbCfg[0x63])
375	pic_level \|= get_pci_irq_level(pGlobals, 3); /* PIRQD */
376	if (pic_irq == pGlobals->Piix3.iAcpiIrq)
377	pic_level \|= pGlobals->Piix3.iAcpiIrqLevel;
378
379	Log3Func(("%s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
380	R3STRING(pPciDev->pszNameR3), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
381	pBusCC->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pDevIns, pic_irq, pic_level, uTagSrc);
382
383	/** @todo optimize pci irq flip-flop some rainy day. */
384	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
385	pciSetIrqInternal(pDevIns, pGlobals, pBusCC, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
386	}
387	}
388
389
390	/**
391	* @interface_method_impl{PDMPCIBUSREGR3,pfnSetIrqR3}
392	*/
393	static DECLCALLBACK(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
394	{
395	PDEVPCIROOT pBus = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
396	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
397	LogFlow(("pciSetIrq: %p %u %u %#x\n", pPciDev, iIrq, iLevel, uTagSrc));
398	pciSetIrqInternal(pDevIns, pBus, pBusCC, pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
399	}
400
401	#ifdef IN_RING3
402
403	/**
404	* Finds a bridge on the bus which contains the destination bus.
405	*
406	* @return Pointer to the device instance data of the bus or
407	* NULL if no bridge was found.
408	* @param pBus Pointer to the bus to search on.
409	* @param iBus Destination bus number.
410	*/
411	DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus)
412	{
413	/* Search for a fitting bridge. */
414	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
415	{
416	/*
417	* Examine secondary and subordinate bus number.
418	* If the target bus is in the range we pass the request on to the bridge.
419	*/
420	PPDMPCIDEV pBridgeTemp = pBus->papBridgesR3[iBridge];
421	AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
422	("Device is not a PCI bridge but on the list of PCI bridges\n"));
423
424	if ( iBus >= pBridgeTemp->abConfig[VBOX_PCI_SECONDARY_BUS]
425	&& iBus <= pBridgeTemp->abConfig[VBOX_PCI_SUBORDINATE_BUS])
426	return pBridgeTemp;
427	}
428
429	/* Nothing found. */
430	return NULL;
431	}
432
433	static void pciR3Piix3Reset(PPDMPCIDEV pPiix3PciDev)
434	{
435	uint8_t *pci_conf = pPiix3PciDev->abConfig;
436
437	pci_conf[0x04] = 0x07; /* master, memory and I/O */
438	pci_conf[0x05] = 0x00;
439	pci_conf[0x06] = 0x00;
440	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
441	pci_conf[0x4c] = 0x4d;
442	pci_conf[0x4e] = 0x03;
443	pci_conf[0x4f] = 0x00;
444	pci_conf[0x60] = 0x80;
445	pci_conf[0x69] = 0x02;
446	pci_conf[0x70] = 0x80;
447	pci_conf[0x76] = 0x0c;
448	pci_conf[0x77] = 0x0c;
449	pci_conf[0x78] = 0x02;
450	pci_conf[0x79] = 0x00;
451	pci_conf[0x80] = 0x00;
452	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
453	pci_conf[0xa0] = 0x08;
454	pci_conf[0xa2] = 0x00;
455	pci_conf[0xa3] = 0x00;
456	pci_conf[0xa4] = 0x00;
457	pci_conf[0xa5] = 0x00;
458	pci_conf[0xa6] = 0x00;
459	pci_conf[0xa7] = 0x00;
460	pci_conf[0xa8] = 0x0f;
461	pci_conf[0xaa] = 0x00;
462	pci_conf[0xab] = 0x00;
463	pci_conf[0xac] = 0x00;
464	pci_conf[0xae] = 0x00;
465	}
466
467	/* host irqs corresponding to PCI irqs A-D */
468	static const uint8_t pci_irqs[4] = { 11, 10, 9, 11 }; /* bird: added const */
469
470	static void pci_bios_init_device(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, PDEVPCIBUS pBus,
471	PPDMPCIDEV pPciDev, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
472	{
473	uint32_t uPciBiosSpecialVRAM = 0xe0000000;
474	uint32_t *paddr;
475	int pin, pic_irq;
476	uint16_t devclass, vendor_id, device_id;
477
478	devclass = devpciR3GetWord(pPciDev, PCI_CLASS_DEVICE);
479	vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
480	device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
481
482	/* Check if device is present. */
483	if (vendor_id != 0xffff)
484	{
485	switch (devclass)
486	{
487	case 0x0101:
488	if ( (vendor_id == 0x8086)
489	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
490	{
491	/* PIIX3, PIIX4 or ICH6 IDE */
492	devpciR3SetWord(pDevIns, pPciDev, 0x40, 0x8011); /* enable IDE0 + fast timing */
493	devpciR3SetWord(pDevIns, pPciDev, 0x42, 0x8011); /* enable IDE1 + fast timing */
494	goto default_map;
495	}
496	else
497	{
498	/* IDE: we map it as in ISA mode */
499	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x1f0);
500	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 1, 0x3f4);
501	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 2, 0x170);
502	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 3, 0x374);
503	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
504	devpciR3GetWord(pPciDev, PCI_COMMAND)
505	\| PCI_COMMAND_IOACCESS);
506	}
507	break;
508	case 0x0800:
509	/* PIC */
510	vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
511	device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
512	if (vendor_id == 0x1014)
513	{
514	/* IBM */
515	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
516	{
517	/* MPIC & MPIC2 */
518	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x80800000 + 0x00040000);
519	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
520	devpciR3GetWord(pPciDev, PCI_COMMAND)
521	\| PCI_COMMAND_MEMACCESS);
522	}
523	}
524	break;
525	case 0xff00:
526	if ( (vendor_id == 0x0106b)
527	&& (device_id == 0x0017 \|\| device_id == 0x0022))
528	{
529	/* macio bridge */
530	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x80800000);
531	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
532	devpciR3GetWord(pPciDev, PCI_COMMAND)
533	\| PCI_COMMAND_MEMACCESS);
534	}
535	break;
536	case 0x0604:
537	{
538	/* Init PCI-to-PCI bridge. */
539	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_PRIMARY_BUS, pBus->iBus);
540
541	AssertMsg(pGlobals->uPciBiosBus < 255, ("Too many bridges on the bus\n"));
542	pGlobals->uPciBiosBus++;
543	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uPciBiosBus);
544	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
545
546	/* Add position of this bridge into the array. */
547	paBridgePositions[cBridgeDepth+1] = (pPciDev->uDevFn >> 3);
548
549	/*
550	* The I/O range for the bridge must be aligned to a 4KB boundary.
551	* This does not change anything really as the access to the device is not going
552	* through the bridge but we want to be compliant to the spec.
553	*/
554	if ((pGlobals->uPciBiosIo % _4K) != 0)
555	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
556	LogFunc(("Aligned I/O start address. New address %#x\n", pGlobals->uPciBiosIo));
557	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0);
558
559	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
560	if ((pGlobals->uPciBiosMmio % _1M) != 0)
561	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
562	LogFunc(("Aligned MMIO start address. New address %#x\n", pGlobals->uPciBiosMmio));
563	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
564
565	/* Save values to compare later to. */
566	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
567	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
568
569	/* Init devices behind the bridge and possibly other bridges as well. */
570	PDEVPCIBUS pChildBus = PDMINS_2_DATA(pPciDev->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
571	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pChildBus->apDevices); uDevFn++)
572	{
573	PPDMPCIDEV pChildPciDev = pChildBus->apDevices[uDevFn];
574	if (pChildPciDev)
575	pci_bios_init_device(pDevIns, pGlobals, pChildBus, pChildPciDev, cBridgeDepth + 1, paBridgePositions);
576	}
577
578	/* The number of bridges behind the this one is now available. */
579	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
580
581	/*
582	* Set I/O limit register. If there is no device with I/O space behind the bridge
583	* we set a lower value than in the base register.
584	* The result with a real bridge is that no I/O transactions are passed to the secondary
585	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
586	*/
587	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % _4K) != 0))
588	{
589	/* The upper boundary must be one byte less than a 4KB boundary. */
590	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
591	}
592	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1);
593
594	/* Same with the MMIO limit register but with 1MB boundary here. */
595	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % _1M) != 0))
596	{
597	/* The upper boundary must be one byte less than a 1MB boundary. */
598	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
599	}
600	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1);
601
602	/*
603	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
604	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
605	* the base register than in the limit register.
606	*/
607	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
608	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
609	devpciR3SetDWord(pDevIns, pPciDev, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
610	devpciR3SetDWord(pDevIns, pPciDev, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
611	break;
612	}
613	default:
614	default_map:
615	{
616	/* default memory mappings */
617	bool fActiveMemRegion = false;
618	bool fActiveIORegion = false;
619	/*
620	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
621	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
622	*/
623	for (unsigned i = 0; i < (PCI_NUM_REGIONS-1); i++)
624	{
625	uint32_t u32Size;
626	uint8_t u8ResourceType;
627	uint32_t u32Address = 0x10 + i * 4;
628
629	/* Calculate size. */
630	u8ResourceType = devpciR3GetByte(pPciDev, u32Address);
631	devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0xffffffff));
632	u32Size = devpciR3GetDWord(pPciDev, u32Address);
633	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
634	/* Clear resource information depending on resource type. */
635	if (fIsPio) /* I/O */
636	u32Size &= ~(0x01);
637	else /* MMIO */
638	u32Size &= ~(0x0f);
639
640	/*
641	* Invert all bits and add 1 to get size of the region.
642	* (From PCI implementation note)
643	*/
644	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
645	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
646	else
647	u32Size = (~u32Size) + 1;
648
649	Log2Func(("Size of region %u for device %d on bus %d is %u\n", i, pPciDev->uDevFn, pBus->iBus, u32Size));
650
651	if (u32Size)
652	{
653	if (fIsPio)
654	paddr = &pGlobals->uPciBiosIo;
655	else
656	{
657	paddr = &pGlobals->uPciBiosMmio;
658	if (devclass == 0x0300)
659	{
660	/*
661	* Because legacy VGA I/O ports are implicitly decoded
662	* by a VGA class device without needing a BAR, we must
663	* enable I/O decoding for such devices.
664	*/
665	fActiveIORegion = true;
666
667	if (vendor_id == 0x80ee \|\| vendor_id == 0x15ad)
668	{
669	bool fPrefetch = (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_IO)))
670	== PCI_ADDRESS_SPACE_MEM_PREFETCH;
671	/* VGA: map frame buffer to default Bochs VBE address. Only
672	* needed for legacy guest drivers. */
673	if (fPrefetch)
674	paddr = &uPciBiosSpecialVRAM;
675	}
676	}
677	}
678	uint32_t uNew = *paddr;
679	uNew = (uNew + u32Size - 1) & ~(u32Size - 1);
680	if (fIsPio)
681	uNew &= UINT32_C(0xffff);
682	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
683	if (!uNew \|\| (uNew <= UINT32_C(0xffffffff) && uNew + u32Size - 1 >= UINT32_C(0xfec00000)))
684	{
685	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
686	i, pBus->iBus, pPciDev->uDevFn >> 3, pPciDev->uDevFn & 7, vendor_id, device_id)); /** @todo make this a VM start failure later. */
687	/* Undo the mapping mess caused by the size probing. */
688	devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0));
689	}
690	else
691	{
692	LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), i, uNew));
693	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, i, uNew);
694	if (fIsPio)
695	fActiveIORegion = true;
696	else
697	fActiveMemRegion = true;
698	*paddr = uNew + u32Size;
699	Log2Func(("New address is %#x\n", *paddr));
700	}
701	}
702	}
703
704	/* Update the command word appropriately. */
705	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
706	devpciR3GetWord(pPciDev, PCI_COMMAND)
707	\| (fActiveMemRegion ? PCI_COMMAND_MEMACCESS : 0)
708	\| (fActiveIORegion ? PCI_COMMAND_IOACCESS : 0));
709
710	break;
711	}
712	}
713
714	/* map the interrupt */
715	pin = devpciR3GetByte(pPciDev, PCI_INTERRUPT_PIN);
716	if (pin != 0)
717	{
718	uint8_t uBridgeDevFn = pPciDev->uDevFn;
719	pin--;
720
721	/* We need to go up to the host bus to see which irq this device will assert there. */
722	while (cBridgeDepth != 0)
723	{
724	/* Get the pin the device would assert on the bridge. */
725	pin = ((uBridgeDevFn >> 3) + pin) & 3;
726	uBridgeDevFn = paBridgePositions[cBridgeDepth];
727	cBridgeDepth--;
728	}
729
730	pin = pci_slot_get_pirq(pPciDev->uDevFn, pin);
731	pic_irq = pci_irqs[pin];
732	devpciR3SetByte(pDevIns, pPciDev, PCI_INTERRUPT_LINE, pic_irq);
733	}
734	}
735	}
736
737	/**
738	* Worker for Fake PCI BIOS config, triggered by magic port access by BIOS.
739	*
740	* @returns VBox status code.
741	*
742	* @param pDevIns i440FX device instance.
743	*/
744	static int pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
745	{
746	uint8_t elcr[2] = {0, 0};
747	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
748
749	LogRel(("PCI: Setting up resources and interrupts\n"));
750
751	/*
752	* Set the start addresses.
753	*/
754	pGlobals->uPciBiosBus = 0;
755	pGlobals->uPciBiosIo = 0xd000;
756	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
757
758	/*
759	* Activate IRQ mappings.
760	*/
761	PPDMPCIDEV pPIIX3 = pDevIns->apPciDevs[1];
762	for (unsigned i = 0; i < 4; i++)
763	{
764	uint8_t irq = pci_irqs[i];
765	/* Set to trigger level. */
766	elcr[irq >> 3] \|= (1 << (irq & 7));
767	/* Activate irq remapping in PIIX3. */
768	devpciR3SetByte(pDevIns, pPIIX3, 0x60 + i, irq);
769	}
770
771	/* Tell to the PIC. */
772	/** @todo r=aeichner We should really move this to the BIOS code and get rid of this fake PCI BIOS thing,
773	* DevPciIch9.cpp lacks this code and has a todo for this.
774	*/
775	VBOXSTRICTRC rcStrict = pDevIns->pHlpR3->pfnIoPortWrite(pDevIns, 0x4d0, elcr[0], sizeof(uint8_t));
776	if (rcStrict == VINF_SUCCESS)
777	rcStrict = pDevIns->pHlpR3->pfnIoPortWrite(pDevIns, 0x4d1, elcr[1], sizeof(uint8_t));
778	if (rcStrict != VINF_SUCCESS)
779	{
780	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
781	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
782	}
783
784	/*
785	* Init the devices.
786	*/
787	PDEVPCIBUS pBus = &pGlobals->PciBus;
788	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
789	{
790	PPDMPCIDEV pPciDev = pBus->apDevices[uDevFn];
791	if (pPciDev)
792	{
793	Log2(("PCI: Initializing device %d (%#x)\n", uDevFn, 0x80000000 \| (uDevFn << 8)));
794	uint8_t aBridgePositions[256];
795	RT_ZERO(aBridgePositions);
796	pci_bios_init_device(pDevIns, pGlobals, pBus, pPciDev, 0, aBridgePositions);
797	}
798	}
799
800	return VINF_SUCCESS;
801	}
802
803	#endif /* IN_RING3 */
804
805
806	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
807
808	/**
809	* @callback_method_impl{FNIOMIOPORTNEWOUT, PCI address}
810	*/
811	static DECLCALLBACK(VBOXSTRICTRC)
812	pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
813	{
814	LogFunc(("offPort=%#x u32=%#x cb=%d\n", offPort, u32, cb));
815	Assert(offPort == 0); RT_NOREF2(offPort, pvUser);
816	if (cb == 4)
817	{
818	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
819	PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
820	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
821	PCI_UNLOCK(pDevIns);
822	}
823	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
824	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
825	return VINF_SUCCESS;
826	}
827
828
829	/**
830	* @callback_method_impl{FNIOMIOPORTNEWIN, PCI address}
831	*/
832	static DECLCALLBACK(VBOXSTRICTRC)
833	pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
834	{
835	Assert(offPort == 0); RT_NOREF2(offPort, pvUser);
836	if (cb == 4)
837	{
838	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
839	PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_READ);
840	*pu32 = pThis->uConfigReg;
841	PCI_UNLOCK(pDevIns);
842	LogFunc(("offPort=%#x cb=%d -> %#x\n", offPort, cb, *pu32));
843	return VINF_SUCCESS;
844	}
845	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
846	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
847	LogFunc(("offPort=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", offPort, cb));
848	return VERR_IOM_IOPORT_UNUSED;
849	}
850
851
852	/**
853	* @callback_method_impl{FNIOMIOPORTNEWOUT, PCI data}
854	*/
855	static DECLCALLBACK(VBOXSTRICTRC)
856	pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
857	{
858	LogFunc(("offPort=%#x u32=%#x cb=%d\n", offPort, u32, cb));
859	Assert(offPort < 4); NOREF(pvUser);
860	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
861	if (!(offPort % cb))
862	{
863	PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
864	rcStrict = pci_data_write(pDevIns, PDMINS_2_DATA(pDevIns, PDEVPCIROOT), offPort, u32, cb);
865	PCI_UNLOCK(pDevIns);
866	}
867	else
868	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", offPort, u32, cb));
869	return rcStrict;
870	}
871
872
873	/**
874	* @callback_method_impl{FNIOMIOPORTNEWIN, PCI data}
875	*/
876	static DECLCALLBACK(VBOXSTRICTRC)
877	pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
878	{
879	Assert(offPort < 4); NOREF(pvUser);
880	if (!(offPort % cb))
881	{
882	PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_READ);
883	VBOXSTRICTRC rcStrict = pci_data_read(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), offPort, cb, pu32);
884	PCI_UNLOCK(pDevIns);
885	LogFunc(("offPort=%#x cb=%#x -> %#x (%Rrc)\n", offPort, cb, *pu32, VBOXSTRICTRC_VAL(rcStrict)));
886	return rcStrict;
887	}
888	AssertMsgFailed(("Read from port %#x cb=%d\n", offPort, cb));
889	return VERR_IOM_IOPORT_UNUSED;
890	}
891
892	#ifdef IN_RING3
893
894	/**
895	* @callback_method_impl{FNIOMIOPORTNEWOUT, PCI data}
896	*/
897	static DECLCALLBACK(VBOXSTRICTRC)
898	pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
899	{
900	Assert(offPort == 0); RT_NOREF2(pvUser, offPort);
901	LogFunc(("offPort=%#x u32=%#x cb=%d\n", offPort, u32, cb));
902	if (cb == 4)
903	{
904	if (u32 == UINT32_C(19200509)) // Richard Adams - Note! In decimal rather hex.
905	{
906	int rc = pciR3FakePCIBIOS(pDevIns);
907	AssertRC(rc);
908	}
909	}
910
911	return VINF_SUCCESS;
912	}
913
914	/**
915	* @callback_method_impl{FNIOMIOPORTNEWIN, PCI data}
916	*/
917	static DECLCALLBACK(VBOXSTRICTRC)
918	pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
919	{
920	Assert(offPort == 0); RT_NOREF5(pDevIns, pvUser, offPort, pu32, cb);
921	LogFunc(("offPort=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", offPort, cb));
922	return VERR_IOM_IOPORT_UNUSED;
923	}
924
925
926	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
927
928	/**
929	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
930	*
931	* @returns VBox status code.
932	* @param pHlp The device helpers.
933	* @param pBus The bus to save.
934	* @param pSSM The saved state handle.
935	*/
936	static int pciR3CommonSaveExec(PCPDMDEVHLPR3 pHlp, PDEVPCIBUS pBus, PSSMHANDLE pSSM)
937	{
938	/*
939	* Iterate thru all the devices.
940	*/
941	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
942	{
943	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
944	if (pDev)
945	{
946	pHlp->pfnSSMPutU32(pSSM, uDevFn);
947	pHlp->pfnSSMPutMem(pSSM, pDev->abConfig, 256); /* Only save 256 bytes here! */
948
949	pHlp->pfnSSMPutS32(pSSM, pDev->Int.s.uIrqPinState);
950
951	/* Save the type an size of all the regions. */
952	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
953	{
954	pHlp->pfnSSMPutU8(pSSM, pDev->Int.s.aIORegions[iRegion].type);
955	pHlp->pfnSSMPutU64(pSSM, pDev->Int.s.aIORegions[iRegion].size);
956	}
957	}
958	}
959	return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* terminator */
960	}
961
962
963	/**
964	* @callback_method_impl{FNSSMDEVSAVEEXEC}
965	*/
966	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
967	{
968	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
969	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
970
971	/*
972	* Bus state data.
973	*/
974	pHlp->pfnSSMPutU32(pSSM, pThis->uConfigReg);
975	pHlp->pfnSSMPutBool(pSSM, pThis->fUseIoApic);
976
977	/*
978	* Save IRQ states.
979	*/
980	for (unsigned i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
981	pHlp->pfnSSMPutU32(pSSM, pThis->Piix3.auPciLegacyIrqLevels[i]);
982	for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
983	pHlp->pfnSSMPutU32(pSSM, pThis->auPciApicIrqLevels[i]);
984
985	pHlp->pfnSSMPutU32(pSSM, pThis->Piix3.iAcpiIrqLevel);
986	pHlp->pfnSSMPutS32(pSSM, pThis->Piix3.iAcpiIrq);
987
988	pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* separator */
989
990	/*
991	* Join paths with pcibridgeR3SaveExec.
992	*/
993	return pciR3CommonSaveExec(pHlp, &pThis->PciBus, pSSM);
994	}
995
996
997	/**
998	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
999	*
1000	* @returns VBox status code.
1001	* @param pDevIns The device instance.
1002	* @param pBus The bus which data is being loaded.
1003	* @param pSSM The saved state handle.
1004	* @param uVersion The data version.
1005	* @param uPass The pass.
1006	*/
1007	static int pciR3CommonLoadExec(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1008	{
1009	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1010	uint32_t u32;
1011	int rc;
1012
1013	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1014
1015	/*
1016	* Iterate thru all the devices and write 0 to the COMMAND register so
1017	* that all the memory is unmapped before we start restoring the saved
1018	* mapping locations.
1019	*
1020	* The register value is restored afterwards so we can do proper
1021	* LogRels in devpciR3CommonRestoreConfig.
1022	*/
1023	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1024	{
1025	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1026	if (pDev)
1027	{
1028	uint16_t u16 = PCIDevGetCommand(pDev);
1029	devpciR3SetCfg(pDevIns, pDev, VBOX_PCI_COMMAND, 0 /u32Value/, 2 /cb/);
1030	PCIDevSetCommand(pDev, u16);
1031	Assert(PCIDevGetCommand(pDev) == u16);
1032	}
1033	}
1034
1035	/*
1036	* Iterate all the devices.
1037	*/
1038	for (uint32_t uDevFn = 0;; uDevFn++)
1039	{
1040	/* index / terminator */
1041	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
1042	if (RT_FAILURE(rc))
1043	return rc;
1044	if (u32 == UINT32_MAX)
1045	break;
1046	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1047	\|\| u32 < uDevFn)
1048	{
1049	AssertMsgFailed(("u32=%#x uDevFn=%#x\n", u32, uDevFn));
1050	return rc;
1051	}
1052
1053	/* skip forward to the device checking that no new devices are present. */
1054	for (; uDevFn < u32; uDevFn++)
1055	{
1056	if (pBus->apDevices[uDevFn])
1057	{
1058	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", uDevFn, pBus->apDevices[uDevFn]->pszNameR3,
1059	PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn])));
1060	if (pHlp->pfnSSMHandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1061	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1062	uDevFn, pBus->apDevices[uDevFn]->pszNameR3, PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn]));
1063	}
1064	}
1065
1066	/* get the data */
1067	union
1068	{
1069	PDMPCIDEV DevTmp;
1070	uint8_t abDevTmpPadding[RT_UOFFSETOF(PDMPCIDEV, abMsixState)];
1071	} u;
1072	RT_ZERO(u.DevTmp);
1073	u.DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1074	pHlp->pfnSSMGetMem(pSSM, u.DevTmp.abConfig, 256);
1075	if (uVersion < VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1076	{
1077	int32_t i32Temp;
1078	/* Irq value not needed anymore. */
1079	rc = pHlp->pfnSSMGetS32(pSSM, &i32Temp);
1080	if (RT_FAILURE(rc))
1081	return rc;
1082	}
1083	else
1084	{
1085	rc = pHlp->pfnSSMGetS32(pSSM, &u.DevTmp.Int.s.uIrqPinState);
1086	if (RT_FAILURE(rc))
1087	return rc;
1088	}
1089
1090	/* Load the region types and sizes. */
1091	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES)
1092	{
1093	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
1094	{
1095	pHlp->pfnSSMGetU8(pSSM, &u.DevTmp.Int.s.aIORegions[iRegion].type);
1096	rc = pHlp->pfnSSMGetU64(pSSM, &u.DevTmp.Int.s.aIORegions[iRegion].size);
1097	AssertLogRelRCReturn(rc, rc);
1098	}
1099	}
1100
1101	/* check that it's still around. */
1102	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1103	if (!pDev)
1104	{
1105	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", uDevFn,
1106	PCIDevGetVendorId(&u.DevTmp), PCIDevGetDeviceId(&u.DevTmp)));
1107	if (pHlp->pfnSSMHandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1108	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1109	uDevFn, PCIDevGetVendorId(&u.DevTmp), PCIDevGetDeviceId(&u.DevTmp));
1110	continue;
1111	}
1112
1113	/* match the vendor id assuming that this will never be changed. */
1114	if ( u.DevTmp.abConfig[0] != pDev->abConfig[0]
1115	\|\| u.DevTmp.abConfig[1] != pDev->abConfig[1])
1116	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1117	N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1118	uDevFn, pDev->pszNameR3, u.DevTmp.abConfig, pDev->abConfig);
1119
1120	/* commit the loaded device config. */
1121	rc = devpciR3CommonRestoreRegions(pHlp, pSSM, pDev, u.DevTmp.Int.s.aIORegions,
1122	uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES);
1123	if (RT_FAILURE(rc))
1124	break;
1125	devpciR3CommonRestoreConfig(pDevIns, pDev, &u.DevTmp.abConfig[0]);
1126
1127	pDev->Int.s.uIrqPinState = u.DevTmp.Int.s.uIrqPinState;
1128	}
1129
1130	return VINF_SUCCESS;
1131	}
1132
1133
1134	/**
1135	* @callback_method_impl{FNSSMDEVLOADEXEC}
1136	*/
1137	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1138	{
1139	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1140	PDEVPCIBUS pBus = &pThis->PciBus;
1141	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1142	uint32_t u32;
1143	int rc;
1144
1145	/*
1146	* Check the version.
1147	*/
1148	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1149	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1150	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1151
1152	/*
1153	* Bus state data.
1154	*/
1155	pHlp->pfnSSMGetU32(pSSM, &pThis->uConfigReg);
1156	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC)
1157	pHlp->pfnSSMGetBool(pSSM, &pThis->fUseIoApic);
1158
1159	/* Load IRQ states. */
1160	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1161	{
1162	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
1163	pHlp->pfnSSMGetU32V(pSSM, &pThis->Piix3.auPciLegacyIrqLevels[i]);
1164	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
1165	pHlp->pfnSSMGetU32V(pSSM, &pThis->auPciApicIrqLevels[i]);
1166
1167	pHlp->pfnSSMGetU32(pSSM, &pThis->Piix3.iAcpiIrqLevel);
1168	pHlp->pfnSSMGetS32(pSSM, &pThis->Piix3.iAcpiIrq);
1169	}
1170
1171	/* separator */
1172	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
1173	if (RT_FAILURE(rc))
1174	return rc;
1175	if (u32 != UINT32_MAX)
1176	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1177
1178	/*
1179	* The devices.
1180	*/
1181	return pciR3CommonLoadExec(pDevIns, pBus, pSSM, uVersion, uPass);
1182	}
1183
1184
1185	/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
1186
1187
1188	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
1189
1190	/**
1191	* @callback_method_impl{FNDBGFHANDLERDEV}
1192	*/
1193	static DECLCALLBACK(void) pciR3IrqRouteInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1194	{
1195	PPDMPCIDEV pPIIX3 = pDevIns->apPciDevs[1];
1196	NOREF(pszArgs);
1197
1198	uint16_t router = pPIIX3->uDevFn;
1199	pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1200	router >> 8, (router >> 3) & 0x1f, router & 0x7);
1201
1202	for (int i = 0; i < 4; ++i)
1203	{
1204	uint8_t irq_map = devpciR3GetByte(pPIIX3, 0x60 + i);
1205	if (irq_map & 0x80)
1206	pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1207	else
1208	pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1209	}
1210	}
1211
1212	/**
1213	* @callback_method_impl{FNDBGFHANDLERDEV, 'pirq'}
1214	*/
1215	DECLCALLBACK(void) devpciR3InfoPIRQ(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1216	{
1217	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1218	NOREF(pszArgs);
1219
1220	pHlp->pfnPrintf(pHlp, "PCI IRQ levels:\n");
1221	for (int i = 0; i < DEVPCI_LEGACY_IRQ_PINS; ++i)
1222	pHlp->pfnPrintf(pHlp, " IRQ%c: %u\n", 'A' + i, pGlobals->Piix3.auPciLegacyIrqLevels[i]);
1223	}
1224
1225
1226	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1227
1228	/**
1229	* @interface_method_impl{PDMDEVREG,pfnReset}
1230	*/
1231	static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
1232	{
1233	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1234	PDEVPCIBUS pBus = &pGlobals->PciBus;
1235
1236	/* PCI-specific reset for each device. */
1237	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1238	{
1239	if (pBus->apDevices[uDevFn])
1240	devpciR3ResetDevice(pDevIns, pBus->apDevices[uDevFn]);
1241	}
1242
1243	pciR3Piix3Reset(pDevIns->apPciDevs[1]);
1244	}
1245
1246
1247	/**
1248	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1249	*/
1250	static DECLCALLBACK(int) pciR3Destruct(PPDMDEVINS pDevIns)
1251	{
1252	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1253	if (pGlobals->PciBus.papBridgesR3)
1254	{
1255	PDMDevHlpMMHeapFree(pDevIns, pGlobals->PciBus.papBridgesR3);
1256	pGlobals->PciBus.papBridgesR3 = NULL;
1257	}
1258	return VINF_SUCCESS;
1259	}
1260
1261
1262	/**
1263	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1264	*/
1265	static DECLCALLBACK(int) pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1266	{
1267	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1268	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1269	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1270	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1271	RT_NOREF(iInstance);
1272	Assert(iInstance == 0);
1273
1274	/*
1275	* Validate and read configuration.
1276	*/
1277	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "IOAPIC", "");
1278
1279	/* query whether we got an IOAPIC */
1280	bool fUseIoApic;
1281	int rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
1282	if (RT_FAILURE(rc))
1283	return PDMDEV_SET_ERROR(pDevIns, rc,
1284	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
1285
1286	Log(("PCI: fUseIoApic=%RTbool fR0Enabled=%RTbool fRCEnabled=%RTbool\n", fUseIoApic, pDevIns->fR0Enabled, pDevIns->fRCEnabled));
1287
1288	/*
1289	* Init data and register the PCI bus.
1290	*/
1291	pGlobals->uPciBiosIo = 0xc000;
1292	pGlobals->uPciBiosMmio = 0xf0000000;
1293	memset((void *)&pGlobals->Piix3.auPciLegacyIrqLevels, 0, sizeof(pGlobals->Piix3.auPciLegacyIrqLevels));
1294	pGlobals->fUseIoApic = fUseIoApic;
1295	memset((void *)&pGlobals->auPciApicIrqLevels, 0, sizeof(pGlobals->auPciApicIrqLevels));
1296
1297	pGlobals->PciBus.fTypePiix3 = true;
1298	pGlobals->PciBus.fTypeIch9 = false;
1299	pGlobals->PciBus.fPureBridge = false;
1300	pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns,
1301	sizeof(PPDMPCIDEV)
1302	* RT_ELEMENTS(pGlobals->PciBus.apDevices));
1303	AssertLogRelReturn(pGlobals->PciBus.papBridgesR3, VERR_NO_MEMORY);
1304
1305	PDEVPCIBUS pBus = &pGlobals->PciBus;
1306	PDMPCIBUSREGCC PciBusReg;
1307	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1308	PciBusReg.pfnRegisterR3 = devpciR3CommonRegisterDevice;
1309	PciBusReg.pfnRegisterMsiR3 = NULL;
1310	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1311	PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
1312	PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
1313	PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
1314	PciBusReg.pfnSetIrqR3 = pciSetIrq;
1315	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1316	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
1317	if (RT_FAILURE(rc))
1318	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
1319	Assert(pBus->iBus == 0);
1320	if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1321	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1322	N_("PCI helper version mismatch; got %#x expected %#x"),
1323	pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1324
1325	/* Disable default device locking. */
1326	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1327	AssertRCReturn(rc, rc);
1328
1329	/*
1330	* Fill in PCI configs and add them to the bus.
1331	*/
1332	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1333	AssertPtr(pPciDev);
1334
1335	/* i440FX */
1336	PCIDevSetVendorId( pPciDev, 0x8086); /* Intel */
1337	PCIDevSetDeviceId( pPciDev, 0x1237);
1338	PCIDevSetRevisionId(pPciDev, 0x02);
1339	PCIDevSetClassSub( pPciDev, 0x00); /* host2pci */
1340	PCIDevSetClassBase( pPciDev, 0x06); /* PCI_bridge */
1341	PCIDevSetHeaderType(pPciDev, 0x00);
1342	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, 0 /fFlags/, 0 /uPciDevNo/, 0 /uPciFunNo/, "i440FX");
1343	AssertLogRelRCReturn(rc, rc);
1344
1345	/* PIIX3 */
1346	PPDMPCIDEV pPiix3PciDev = pDevIns->apPciDevs[1];
1347	PCIDevSetVendorId( pPiix3PciDev, 0x8086); /* Intel */
1348	PCIDevSetDeviceId( pPiix3PciDev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
1349	PCIDevSetClassSub( pPiix3PciDev, 0x01); /* PCI_ISA */
1350	PCIDevSetClassBase( pPiix3PciDev, 0x06); /* PCI_bridge */
1351	PCIDevSetHeaderType(pPiix3PciDev, 0x80); /* PCI_multifunction, generic */
1352	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPiix3PciDev, 0 /fFlags/, 1 /uPciDevNo/, 0 /uPciFunNo/, "PIIX3");
1353	AssertLogRelRCReturn(rc, rc);
1354	pciR3Piix3Reset(pDevIns->apPciDevs[1]);
1355
1356	pBus->iDevSearch = 16;
1357
1358	/*
1359	* Register I/O ports and save state.
1360	*/
1361	static const IOMIOPORTDESC s_aAddrDesc[] = { { "PCI address", "PCI address", NULL, NULL }, { NULL, NULL, NULL, NULL } };
1362	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cf8, 1, pciIOPortAddressWrite, pciIOPortAddressRead, "i440FX (PCI)", s_aAddrDesc,
1363	&pGlobals->hIoPortAddress);
1364	AssertLogRelRCReturn(rc, rc);
1365
1366	static const IOMIOPORTDESC s_aDataDesc[] = { { "PCI data", "PCI data", NULL, NULL }, { NULL, NULL, NULL, NULL } };
1367	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cfc, 4, pciIOPortDataWrite, pciIOPortDataRead, "i440FX (PCI)", s_aDataDesc,
1368	&pGlobals->hIoPortData);
1369	AssertLogRelRCReturn(rc, rc);
1370
1371	static const IOMIOPORTDESC s_aMagicDesc[] = { { "PCI magic", NULL, NULL, NULL }, { NULL, NULL, NULL, NULL } };
1372	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0410, 1, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead,
1373	"i440FX (Fake PCI BIOS trigger)", s_aMagicDesc, &pGlobals->hIoPortMagic);
1374	AssertLogRelRCReturn(rc, rc);
1375
1376
1377	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
1378	NULL, NULL, NULL,
1379	NULL, pciR3SaveExec, NULL,
1380	NULL, pciR3LoadExec, NULL);
1381	AssertLogRelRCReturn(rc, rc);
1382
1383	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
1384	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
1385	devpciR3InfoPci);
1386	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", devpciR3InfoPciIrq);
1387	PDMDevHlpDBGFInfoRegister(pDevIns, "pirq", "Display PIRQ state. (no arguments)", devpciR3InfoPIRQ);
1388	PDMDevHlpDBGFInfoRegister(pDevIns, "irqroute", "Display PCI IRQ routing. (no arguments)", pciR3IrqRouteInfo);
1389
1390	return VINF_SUCCESS;
1391	}
1392
1393	#else /* !IN_RING3 */
1394
1395	/**
1396	* @interface_method_impl{PDMDEVREGR0,pfnConstruct}
1397	*/
1398	static DECLCALLBACK(int) pciRZRootConstruct(PPDMDEVINS pDevIns)
1399	{
1400	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1401	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1402	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1403
1404	/* Mirror the ring-3 device lock disabling: */
1405	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1406	AssertRCReturn(rc, rc);
1407
1408	/* Set up the RZ PCI bus callbacks: */
1409	PDMPCIBUSREGCC PciBusReg;
1410	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1411	PciBusReg.iBus = pGlobals->PciBus.iBus;
1412	PciBusReg.pfnSetIrq = pciSetIrq;
1413	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1414	rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
1415	AssertRCReturn(rc, rc);
1416
1417	/* Set up I/O port callbacks, except for the magic port: */
1418	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pGlobals->hIoPortAddress, pciIOPortAddressWrite, pciIOPortAddressRead, NULL);
1419	AssertLogRelRCReturn(rc, rc);
1420
1421	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pGlobals->hIoPortData, pciIOPortDataWrite, pciIOPortDataRead, NULL);
1422	AssertLogRelRCReturn(rc, rc);
1423
1424	return rc;
1425	}
1426
1427	#endif /* !IN_RING3 */
1428
1429	/**
1430	* The device registration structure.
1431	*/
1432	const PDMDEVREG g_DevicePCI =
1433	{
1434	/* .u32Version = */ PDM_DEVREG_VERSION,
1435	/* .uReserved0 = */ 0,
1436	/* .szName = */ "pci",
1437	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1438	/* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI,
1439	/* .cMaxInstances = */ 1,
1440	/* .uSharedVersion = */ 42,
1441	/* .cbInstanceShared = */ sizeof(DEVPCIROOT),
1442	/* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
1443	/* .cbInstanceRC = */ sizeof(DEVPCIBUSRC),
1444	/* .cMaxPciDevices = */ 2,
1445	/* .cMaxMsixVectors = */ 0,
1446	/* .pszDescription = */ "i440FX PCI bridge and PIIX3 ISA bridge.",
1447	#if defined(IN_RING3)
1448	/* .pszRCMod = */ "VBoxDDRC.rc",
1449	/* .pszR0Mod = */ "VBoxDDR0.r0",
1450	/* .pfnConstruct = */ pciR3Construct,
1451	/* .pfnDestruct = */ pciR3Destruct,
1452	/* .pfnRelocate = */ NULL,
1453	/* .pfnMemSetup = */ NULL,
1454	/* .pfnPowerOn = */ NULL,
1455	/* .pfnReset = */ pciR3Reset,
1456	/* .pfnSuspend = */ NULL,
1457	/* .pfnResume = */ NULL,
1458	/* .pfnAttach = */ NULL,
1459	/* .pfnDetach = */ NULL,
1460	/* .pfnQueryInterface = */ NULL,
1461	/* .pfnInitComplete = */ NULL,
1462	/* .pfnPowerOff = */ NULL,
1463	/* .pfnSoftReset = */ NULL,
1464	/* .pfnReserved0 = */ NULL,
1465	/* .pfnReserved1 = */ NULL,
1466	/* .pfnReserved2 = */ NULL,
1467	/* .pfnReserved3 = */ NULL,
1468	/* .pfnReserved4 = */ NULL,
1469	/* .pfnReserved5 = */ NULL,
1470	/* .pfnReserved6 = */ NULL,
1471	/* .pfnReserved7 = */ NULL,
1472	#elif defined(IN_RING0)
1473	/* .pfnEarlyConstruct = */ NULL,
1474	/* .pfnConstruct = */ pciRZRootConstruct,
1475	/* .pfnDestruct = */ NULL,
1476	/* .pfnFinalDestruct = */ NULL,
1477	/* .pfnRequest = */ NULL,
1478	/* .pfnReserved0 = */ NULL,
1479	/* .pfnReserved1 = */ NULL,
1480	/* .pfnReserved2 = */ NULL,
1481	/* .pfnReserved3 = */ NULL,
1482	/* .pfnReserved4 = */ NULL,
1483	/* .pfnReserved5 = */ NULL,
1484	/* .pfnReserved6 = */ NULL,
1485	/* .pfnReserved7 = */ NULL,
1486	#elif defined(IN_RC)
1487	/* .pfnConstruct = */ pciRZRootConstruct,
1488	/* .pfnReserved0 = */ NULL,
1489	/* .pfnReserved1 = */ NULL,
1490	/* .pfnReserved2 = */ NULL,
1491	/* .pfnReserved3 = */ NULL,
1492	/* .pfnReserved4 = */ NULL,
1493	/* .pfnReserved5 = */ NULL,
1494	/* .pfnReserved6 = */ NULL,
1495	/* .pfnReserved7 = */ NULL,
1496	#else
1497	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1498	#endif
1499	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1500
1501	};
1502
1503
1504
1505	/* -=-=-=-=-=- The PCI bridge specific bits -=-=-=-=-=- */
1506
1507	/**
1508	* @interface_method_impl{PDMPCIBUSREGR3,pfnSetIrqR3}
1509	*/
1510	static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
1511	{
1512	LogFlow(("pcibridgeSetIrq: %p %u %u %#x\n", pPciDev, iIrq, iLevel, uTagSrc));
1513
1514	/*
1515	* The PCI-to-PCI bridge specification defines how the interrupt pins
1516	* are routed from the secondary to the primary bus (see chapter 9).
1517	* iIrq gives the interrupt pin the pci device asserted.
1518	* We change iIrq here according to the spec and call the SetIrq function
1519	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
1520	*/
1521	PDEVPCIBUS pBus;
1522	uint8_t uDevFnBridge;
1523	int iIrqPinBridge;
1524	PPDMDEVINS pDevInsBus = devpcibridgeCommonSetIrqRootWalk(pDevIns, pPciDev, iIrq, &pBus, &uDevFnBridge, &iIrqPinBridge);
1525	AssertReturnVoid(pDevInsBus);
1526	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
1527	Assert(pDevInsBus->pReg == &g_DevicePCI);
1528
1529	pciSetIrqInternal(pDevInsBus, DEVPCIBUS_2_DEVPCIROOT(pBus), PDMINS_2_DATA_CC(pDevInsBus, PDEVPCIBUSCC),
1530	uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
1531	}
1532
1533	#ifdef IN_RING3
1534
1535	/**
1536	* @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
1537	*/
1538	static DECLCALLBACK(VBOXSTRICTRC) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
1539	uint32_t u32Address, unsigned cb, uint32_t u32Value)
1540	{
1541	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d u32Value=%u\n", pDevIns, iBus, iDevice, u32Address, cb, u32Value));
1542	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1543	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1544
1545	/* If the current bus is not the target bus search for the bus which contains the device. */
1546	if (iBus != pDevIns->apPciDevs[0]->abConfig[VBOX_PCI_SECONDARY_BUS])
1547	{
1548	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1549	if (pBridgeDevice)
1550	{
1551	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1552	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice,
1553	u32Address, cb, u32Value);
1554	}
1555	}
1556	else
1557	{
1558	/* This is the target bus, pass the write to the device. */
1559	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1560	if (pPciDev)
1561	{
1562	LogFunc(("%s: addr=%02x val=%08x len=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
1563	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
1564	if (pPciDev->Int.s.pfnConfigWrite)
1565	rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, u32Value);
1566	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
1567	rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
1568	pPciDev, u32Address, cb, u32Value);
1569	}
1570	}
1571	return rcStrict;
1572	}
1573
1574
1575	/**
1576	* @callback_method_impl{FNPCIBRIDGECONFIGREAD}
1577	*/
1578	static DECLCALLBACK(VBOXSTRICTRC) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
1579	uint32_t u32Address, unsigned cb, uint32_t *pu32Value)
1580	{
1581	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1582	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1583	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1584
1585	/* If the current bus is not the target bus search for the bus which contains the device. */
1586	if (iBus != pDevIns->apPciDevs[0]->abConfig[VBOX_PCI_SECONDARY_BUS])
1587	{
1588	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1589	if (pBridgeDevice)
1590	{
1591	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
1592	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns),
1593	iBus, iDevice, u32Address, cb, pu32Value);
1594	}
1595	else
1596	*pu32Value = UINT32_MAX;
1597	}
1598	else
1599	{
1600	/* This is the target bus, pass the read to the device. */
1601	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1602	if (pPciDev)
1603	{
1604	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
1605	if (pPciDev->Int.s.pfnConfigRead)
1606	rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, pu32Value);
1607	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
1608	rcStrict = devpciR3CommonConfigReadWorker(pPciDev, u32Address, cb, pu32Value);
1609
1610	LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, *pu32Value, cb));
1611	}
1612	else
1613	*pu32Value = UINT32_MAX;
1614	}
1615
1616	return rcStrict;
1617	}
1618
1619
1620	/**
1621	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1622	*/
1623	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1624	{
1625	return pciR3CommonSaveExec(pDevIns->pHlpR3, PDMINS_2_DATA(pDevIns, PDEVPCIBUS), pSSM);
1626	}
1627
1628
1629	/**
1630	* @callback_method_impl{FNSSMDEVLOADEXEC}
1631	*/
1632	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1633	{
1634	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1635	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1636	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1637	return pciR3CommonLoadExec(pDevIns, pThis, pSSM, uVersion, uPass);
1638	}
1639
1640
1641	/**
1642	* @interface_method_impl{PDMDEVREG,pfnReset}
1643	*/
1644	static DECLCALLBACK(void) pcibridgeR3Reset(PPDMDEVINS pDevIns)
1645	{
1646	/* Reset config space to default values. */
1647	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1648	pPciDev->abConfig[VBOX_PCI_PRIMARY_BUS] = 0;
1649	pPciDev->abConfig[VBOX_PCI_SECONDARY_BUS] = 0;
1650	pPciDev->abConfig[VBOX_PCI_SUBORDINATE_BUS] = 0;
1651	}
1652
1653
1654	/**
1655	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1656	*/
1657	static DECLCALLBACK(int) pcibridgeR3Destruct(PPDMDEVINS pDevIns)
1658	{
1659	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1660	if (pBus->papBridgesR3)
1661	{
1662	PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
1663	pBus->papBridgesR3 = NULL;
1664	}
1665	return VINF_SUCCESS;
1666	}
1667
1668
1669	/**
1670	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1671	*/
1672	static DECLCALLBACK(int) pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1673	{
1674	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1675	RT_NOREF(iInstance, pCfg);
1676	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1677	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1678
1679	/*
1680	* Validate and read configuration (none left).
1681	*/
1682	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "", "");
1683	Log(("PCI: fRCEnabled=%RTbool fR0Enabled=%RTbool\n", pDevIns->fRCEnabled, pDevIns->fR0Enabled));
1684
1685	/*
1686	* Init data and register the PCI bus.
1687	*/
1688	pBus->fTypePiix3 = true;
1689	pBus->fTypeIch9 = false;
1690	pBus->fPureBridge = true;
1691	pBus->papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pBus->apDevices));
1692	AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
1693
1694	PDMPCIBUSREGCC PciBusReg;
1695	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1696	PciBusReg.pfnRegisterR3 = devpcibridgeR3CommonRegisterDevice;
1697	PciBusReg.pfnRegisterMsiR3 = NULL;
1698	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1699	PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
1700	PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
1701	PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
1702	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
1703	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1704	int rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
1705	if (RT_FAILURE(rc))
1706	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
1707	Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
1708	if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1709	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1710	N_("PCI helper version mismatch; got %#x expected %#x"),
1711	pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1712
1713	/*
1714	* Fill in PCI configs and add them to the bus.
1715	*/
1716	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1717	PCIDevSetVendorId( pPciDev, 0x8086); /* Intel */
1718	PCIDevSetDeviceId( pPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
1719	PCIDevSetRevisionId(pPciDev, 0xf2);
1720	PCIDevSetClassSub( pPciDev, 0x04); /* pci2pci */
1721	PCIDevSetClassBase( pPciDev, 0x06); /* PCI_bridge */
1722	PCIDevSetClassProg( pPciDev, 0x01); /* Supports subtractive decoding. */
1723	PCIDevSetHeaderType(pPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
1724	PCIDevSetCommand( pPciDev, 0x0000);
1725	PCIDevSetStatus( pPciDev, 0x0020); /* 66MHz Capable. */
1726	PCIDevSetInterruptLine(pPciDev, 0x00); /* This device does not assert interrupts. */
1727
1728	/*
1729	* This device does not generate interrupts. Interrupt delivery from
1730	* devices attached to the bus is unaffected.
1731	*/
1732	PCIDevSetInterruptPin(pPciDev, 0x00);
1733
1734	/*
1735	* Register this PCI bridge. The called function will take care on which bus we will get registered.
1736	*/
1737	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, PDMPCIDEVREG_F_PCI_BRIDGE, PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
1738	PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "pcibridge");
1739	if (RT_FAILURE(rc))
1740	return rc;
1741	pPciDev->Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
1742	pPciDev->Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
1743
1744	pBus->iDevSearch = 0;
1745
1746	/*
1747	* Register SSM handlers. We use the same saved state version as for the host bridge
1748	* to make changes easier.
1749	*/
1750	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
1751	NULL, NULL, NULL,
1752	NULL, pcibridgeR3SaveExec, NULL,
1753	NULL, pcibridgeR3LoadExec, NULL);
1754	if (RT_FAILURE(rc))
1755	return rc;
1756
1757	return VINF_SUCCESS;
1758	}
1759
1760	#else /* !IN_RING3 */
1761
1762	/**
1763	* @interface_method_impl{PDMDEVREGR0,pfnConstruct}
1764	*/
1765	static DECLCALLBACK(int) pcibridgeRZConstruct(PPDMDEVINS pDevIns)
1766	{
1767	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1768	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1769	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1770
1771	PDMPCIBUSREGCC PciBusReg;
1772	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1773	PciBusReg.iBus = pBus->iBus;
1774	PciBusReg.pfnSetIrq = pcibridgeSetIrq;
1775	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1776	int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
1777	AssertRC(rc);
1778
1779	return rc;
1780	}
1781
1782	#endif /* !IN_RING3 */
1783
1784	/**
1785	* The device registration structure
1786	* for the PCI-to-PCI bridge.
1787	*/
1788	const PDMDEVREG g_DevicePCIBridge =
1789	{
1790	/* .u32Version = */ PDM_DEVREG_VERSION,
1791	/* .uReserved0 = */ 0,
1792	/* .szName = */ "pcibridge",
1793	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1794	/* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI,
1795	/* .cMaxInstances = */ ~0U,
1796	/* .uSharedVersion = */ 42,
1797	/* .cbInstanceShared = */ sizeof(DEVPCIBUS),
1798	/* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
1799	/* .cbInstanceRC = */ 0,
1800	/* .cMaxPciDevices = */ 1,
1801	/* .cMaxMsixVectors = */ 0,
1802	/* .pszDescription = */ "82801 Mobile PCI to PCI bridge",
1803	#if defined(IN_RING3)
1804	/* .pszRCMod = */ "VBoxDDRC.rc",
1805	/* .pszR0Mod = */ "VBoxDDR0.r0",
1806	/* .pfnConstruct = */ pcibridgeR3Construct,
1807	/* .pfnDestruct = */ pcibridgeR3Destruct,
1808	/* .pfnRelocate = */ NULL,
1809	/* .pfnMemSetup = */ NULL,
1810	/* .pfnPowerOn = */ NULL,
1811	/* .pfnReset = */ pcibridgeR3Reset,
1812	/* .pfnSuspend = */ NULL,
1813	/* .pfnResume = */ NULL,
1814	/* .pfnAttach = */ NULL,
1815	/* .pfnDetach = */ NULL,
1816	/* .pfnQueryInterface = */ NULL,
1817	/* .pfnInitComplete = */ NULL,
1818	/* .pfnPowerOff = */ NULL,
1819	/* .pfnSoftReset = */ NULL,
1820	/* .pfnReserved0 = */ NULL,
1821	/* .pfnReserved1 = */ NULL,
1822	/* .pfnReserved2 = */ NULL,
1823	/* .pfnReserved3 = */ NULL,
1824	/* .pfnReserved4 = */ NULL,
1825	/* .pfnReserved5 = */ NULL,
1826	/* .pfnReserved6 = */ NULL,
1827	/* .pfnReserved7 = */ NULL,
1828	#elif defined(IN_RING0)
1829	/* .pfnEarlyConstruct = */ NULL,
1830	/* .pfnConstruct = */ pcibridgeRZConstruct,
1831	/* .pfnDestruct = */ NULL,
1832	/* .pfnFinalDestruct = */ NULL,
1833	/* .pfnRequest = */ NULL,
1834	/* .pfnReserved0 = */ NULL,
1835	/* .pfnReserved1 = */ NULL,
1836	/* .pfnReserved2 = */ NULL,
1837	/* .pfnReserved3 = */ NULL,
1838	/* .pfnReserved4 = */ NULL,
1839	/* .pfnReserved5 = */ NULL,
1840	/* .pfnReserved6 = */ NULL,
1841	/* .pfnReserved7 = */ NULL,
1842	#elif defined(IN_RC)
1843	/* .pfnConstruct = */ pcibridgeRZConstruct,
1844	/* .pfnReserved0 = */ NULL,
1845	/* .pfnReserved1 = */ NULL,
1846	/* .pfnReserved2 = */ NULL,
1847	/* .pfnReserved3 = */ NULL,
1848	/* .pfnReserved4 = */ NULL,
1849	/* .pfnReserved5 = */ NULL,
1850	/* .pfnReserved6 = */ NULL,
1851	/* .pfnReserved7 = */ NULL,
1852	#else
1853	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1854	#endif
1855	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1856	};
1857

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 91968

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