VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 81077

Last change on this file since 81077 was 81048, checked in by vboxsync, 5 years ago

DevPCI: Only save 256 bytes of config space to match the load code and old state. (PIIX3/4 offers no mechanism for accessing extended config space anyway, so why save/restore it). bugref:9218

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1/* $Id: DevPCI.cpp 81048 2019-09-27 12:17:45Z vboxsync $ */
2/** @file
3 * DevPCI - PCI BUS Device.
4 *
5 * @remarks New code shall be added to DevPciIch9.cpp as that will become
6 * the common PCI bus code soon. Don't fix code in both DevPCI.cpp
7 * and DevPciIch9.cpp when it's possible to just make the latter
8 * version common. Common code uses the 'devpci' prefix, is
9 * prototyped in DevPciInternal.h, and is defined in DevPciIch9.cpp.
10 */
11
12/*
13 * Copyright (C) 2006-2019 Oracle Corporation
14 *
15 * This file is part of VirtualBox Open Source Edition (OSE), as
16 * available from http://www.virtualbox.org. This file is free software;
17 * you can redistribute it and/or modify it under the terms of the GNU
18 * General Public License (GPL) as published by the Free Software
19 * Foundation, in version 2 as it comes in the "COPYING" file of the
20 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
21 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
22 * --------------------------------------------------------------------
23 *
24 * This code is based on:
25 *
26 * QEMU PCI bus manager
27 *
28 * Copyright (c) 2004 Fabrice Bellard
29 *
30 * Permission is hereby granted, free of charge, to any person obtaining a copy
31 * of this software and associated documentation files (the "Software"), to deal
32 * in the Software without restriction, including without limitation the rights
33 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
34 * copies of the Software, and to permit persons to whom the Software is
35 * furnished to do so, subject to the following conditions:
36 *
37 * The above copyright notice and this permission notice shall be included in
38 * all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
41 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
42 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
44 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
45 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
46 * THE SOFTWARE.
47 */
48
49
50/*********************************************************************************************************************************
51* Header Files *
52*********************************************************************************************************************************/
53#define LOG_GROUP LOG_GROUP_DEV_PCI
54#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
55#include <VBox/vmm/pdmpcidev.h>
56#include <VBox/vmm/pdmdev.h>
57#include <VBox/vmm/mm.h>
58#include <iprt/asm.h>
59#include <iprt/assert.h>
60#include <iprt/string.h>
61
62#include "PciInline.h"
63#include "VBoxDD.h"
64#include "DevPciInternal.h"
65
66
67/*********************************************************************************************************************************
68* Defined Constants And Macros *
69*********************************************************************************************************************************/
70/** Saved state version of the PCI bus device. */
71#define VBOX_PCI_SAVED_STATE_VERSION VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES
72/** Adds I/O region types and sizes for dealing changes in resource regions. */
73#define VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES 4
74/** Before region sizes, the first named one.
75 * Looking at the code though, we support even older version. */
76#define VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES 3
77/** Notes whether we use the I/O APIC. */
78#define VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC 2
79
80
81/*********************************************************************************************************************************
82* Internal Functions *
83*********************************************************************************************************************************/
84RT_C_DECLS_BEGIN
85
86static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
87
88#ifdef IN_RING3
89DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus);
90#endif
91
92RT_C_DECLS_END
93
94#define DEBUG_PCI
95
96#define PCI_VENDOR_ID 0x00 /* 16 bits */
97#define PCI_DEVICE_ID 0x02 /* 16 bits */
98#define PCI_COMMAND 0x04 /* 16 bits */
99#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
100#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
101#define PCI_CLASS_DEVICE 0x0a /* Device class */
102#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
103#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
104#define PCI_MIN_GNT 0x3e /* 8 bits */
105#define PCI_MAX_LAT 0x3f /* 8 bits */
106
107
108static VBOXSTRICTRC pci_data_write(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, uint32_t addr, uint32_t u32Value, int cb)
109{
110 LogFunc(("addr=%08x u32Value=%08x cb=%d\n", pGlobals->uConfigReg, u32Value, cb));
111
112 if (!(pGlobals->uConfigReg & (1 << 31)))
113 return VINF_SUCCESS;
114 if ((pGlobals->uConfigReg & 0x3) != 0)
115 return VINF_SUCCESS;
116
117 uint8_t const iBus = (pGlobals->uConfigReg >> 16) & 0xff;
118 uint8_t const iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
119#ifdef IN_RING3
120 uint32_t const config_addr = (pGlobals->uConfigReg & 0xfc) | (addr & 3);
121#endif
122 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
123
124 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
125 if (iBus != 0)
126 {
127 if (pGlobals->PciBus.cBridges)
128 {
129#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
130 PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
131 if (pBridgeDevice)
132 {
133 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
134 rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus,
135 iDevice, config_addr, cb, u32Value);
136 }
137#else
138 RT_NOREF(pDevIns, addr, u32Value, cb);
139 rcStrict = VINF_IOM_R3_IOPORT_WRITE;
140#endif
141 }
142 }
143 else
144 {
145 R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[iDevice];
146 if (pPciDev)
147 {
148#ifdef IN_RING3
149 LogFunc(("%s: addr=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, config_addr, u32Value, cb));
150 rcStrict = VINF_PDM_PCI_DO_DEFAULT;
151 if (pPciDev->Int.s.pfnConfigWrite)
152 rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, config_addr, cb, u32Value);
153 if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
154 rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
155 pPciDev, config_addr, cb, u32Value);
156#else
157 rcStrict = VINF_IOM_R3_IOPORT_WRITE;
158#endif
159 }
160 }
161 return rcStrict;
162}
163
164static VBOXSTRICTRC pci_data_read(PDEVPCIROOT pGlobals, uint32_t addr, int cb, uint32_t *pu32Value)
165{
166 *pu32Value = UINT32_MAX;
167
168 if (!(pGlobals->uConfigReg & (1 << 31)))
169 return VINF_SUCCESS;
170 if ((pGlobals->uConfigReg & 0x3) != 0)
171 return VINF_SUCCESS;
172 uint8_t const iBus = (pGlobals->uConfigReg >> 16) & 0xff;
173 uint8_t const iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
174#ifdef IN_RING3
175 uint32_t const config_addr = (pGlobals->uConfigReg & 0xfc) | (addr & 3);
176#endif
177 RT_UNTRUSTED_VALIDATED_FENCE();
178
179 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
180 if (iBus != 0)
181 {
182 if (pGlobals->PciBus.cBridges)
183 {
184#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
185 PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
186 if (pBridgeDevice)
187 {
188 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
189 rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns),
190 iBus, iDevice, config_addr, cb, pu32Value);
191 }
192#else
193 RT_NOREF(addr, cb);
194 rcStrict = VINF_IOM_R3_IOPORT_READ;
195#endif
196 }
197 }
198 else
199 {
200 R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[iDevice];
201 if (pPciDev)
202 {
203#ifdef IN_RING3
204 rcStrict = VINF_PDM_PCI_DO_DEFAULT;
205 if (pPciDev->Int.s.pfnConfigRead)
206 rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, config_addr, cb, pu32Value);
207 if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
208 rcStrict = devpciR3CommonConfigReadWorker(pPciDev, config_addr, cb, pu32Value);
209 LogFunc(("%s: addr=%02x val=%08x cb=%d\n", pPciDev->pszNameR3, config_addr, *pu32Value, cb));
210#else
211 NOREF(cb);
212 rcStrict = VINF_IOM_R3_IOPORT_READ;
213#endif
214 }
215 }
216
217 return rcStrict;
218}
219
220
221
222/* return the global irq number corresponding to a given device irq
223 pin. We could also use the bus number to have a more precise
224 mapping.
225 This is the implementation note described in the PCI spec chapter 2.2.6 */
226static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
227{
228 int slot_addend;
229 slot_addend = (uDevFn >> 3) - 1;
230 return (irq_num + slot_addend) & 3;
231}
232
233static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
234{
235 return (irq_num + (uDevFn >> 3)) & 7;
236}
237
238static inline int get_pci_irq_apic_level(PDEVPCIROOT pGlobals, int irq_num)
239{
240 return (pGlobals->auPciApicIrqLevels[irq_num] != 0);
241}
242
243static void apic_set_irq(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PDEVPCIBUSCC pBusCC,
244 uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, int iAcpiIrq, uint32_t uTagSrc)
245{
246 /* This is only allowed to be called with a pointer to the host bus. */
247 AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
248
249 if (iAcpiIrq == -1) {
250 int apic_irq, apic_level;
251 PDEVPCIROOT pGlobals = DEVPCIBUS_2_DEVPCIROOT(pBus);
252 int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
253
254 if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
255 ASMAtomicIncU32(&pGlobals->auPciApicIrqLevels[irq_num]);
256 else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
257 ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
258
259 apic_irq = irq_num + 0x10;
260 apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
261 Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
262 R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
263 pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, apic_irq, apic_level, uTagSrc);
264
265 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
266 ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
267 pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
268 apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
269 Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
270 R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
271 pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, apic_irq, apic_level, uTagSrc);
272 }
273 } else {
274 Log3Func(("%s: irq_num1=%d level=%d iAcpiIrq=%d\n",
275 R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iAcpiIrq));
276 pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, iAcpiIrq, iLevel, uTagSrc);
277 }
278}
279
280DECLINLINE(int) get_pci_irq_level(PDEVPCIROOT pGlobals, int irq_num)
281{
282 return (pGlobals->Piix3.auPciLegacyIrqLevels[irq_num] != 0);
283}
284
285/**
286 * Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
287 *
288 * @param pDevIns The PDM device instance for the PCI bus.
289 * @param pGlobals Device instance of the host PCI bus.
290 * @param pBusCC Context specific data for the PCI bus.
291 * @param uDevFn The device number on the host bus which will raise the IRQ
292 * @param pPciDev The PCI device structure which raised the interrupt.
293 * @param iIrq IRQ number to set.
294 * @param iLevel IRQ level.
295 * @param uTagSrc The IRQ tag and source ID (for tracing).
296 * @remark uDevFn and pPciDev->uDevFn are not the same if the device is behind
297 * a bridge. In that case uDevFn will be the slot of the bridge which
298 * is needed to calculate the PIRQ value.
299 */
300static void pciSetIrqInternal(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, PDEVPCIBUSCC pBusCC,
301 uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
302{
303 PDEVPCIBUS pBus = &pGlobals->PciBus;
304 uint8_t *pbCfg = pDevIns->apPciDevs[1]->abConfig;
305 const bool fIsAcpiDevice = pPciDev->abConfig[2] == 0x13 && pPciDev->abConfig[3] == 0x71;
306 /* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
307 * is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
308 * See the \_SB_.PCI0._PRT method in vbox.dsl.
309 */
310 const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
311 int pic_irq, pic_level;
312
313 /* Check if the state changed. */
314 if (pPciDev->Int.s.uIrqPinState != iLevel)
315 {
316 pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
317
318 /* Send interrupt to I/O APIC only. */
319 if (fIsApicEnabled)
320 {
321 if (fIsAcpiDevice)
322 /*
323 * ACPI needs special treatment since SCI is hardwired and
324 * should not be affected by PCI IRQ routing tables at the
325 * same time SCI IRQ is shared in PCI sense hence this
326 * kludge (i.e. we fetch the hardwired value from ACPIs
327 * PCI device configuration space).
328 */
329 apic_set_irq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, -1, iLevel, pPciDev->abConfig[PCI_INTERRUPT_LINE], uTagSrc);
330 else
331 apic_set_irq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
332 return;
333 }
334
335 if (fIsAcpiDevice)
336 {
337 /* As per above treat ACPI in a special way */
338 pic_irq = pPciDev->abConfig[PCI_INTERRUPT_LINE];
339 pGlobals->Piix3.iAcpiIrq = pic_irq;
340 pGlobals->Piix3.iAcpiIrqLevel = iLevel & PDM_IRQ_LEVEL_HIGH;
341 }
342 else
343 {
344 int irq_num;
345 irq_num = pci_slot_get_pirq(uDevFn, iIrq);
346
347 if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
348 ASMAtomicIncU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
349 else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
350 ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
351
352 /* now we change the pic irq level according to the piix irq mappings */
353 pic_irq = pbCfg[0x60 + irq_num];
354 if (pic_irq >= 16)
355 {
356 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
357 {
358 ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
359 pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
360 }
361
362 return;
363 }
364 }
365
366 /* the pic level is the logical OR of all the PCI irqs mapped to it */
367 pic_level = 0;
368 if (pic_irq == pbCfg[0x60])
369 pic_level |= get_pci_irq_level(pGlobals, 0); /* PIRQA */
370 if (pic_irq == pbCfg[0x61])
371 pic_level |= get_pci_irq_level(pGlobals, 1); /* PIRQB */
372 if (pic_irq == pbCfg[0x62])
373 pic_level |= get_pci_irq_level(pGlobals, 2); /* PIRQC */
374 if (pic_irq == pbCfg[0x63])
375 pic_level |= get_pci_irq_level(pGlobals, 3); /* PIRQD */
376 if (pic_irq == pGlobals->Piix3.iAcpiIrq)
377 pic_level |= pGlobals->Piix3.iAcpiIrqLevel;
378
379 Log3Func(("%s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
380 R3STRING(pPciDev->pszNameR3), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
381 pBusCC->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pDevIns, pic_irq, pic_level, uTagSrc);
382
383 /** @todo optimize pci irq flip-flop some rainy day. */
384 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
385 pciSetIrqInternal(pDevIns, pGlobals, pBusCC, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
386 }
387}
388
389
390/**
391 * @interface_method_impl{PDMPCIBUSREGR3,pfnSetIrqR3}
392 */
393static DECLCALLBACK(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
394{
395 PDEVPCIROOT pBus = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
396 PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
397 LogFlow(("pciSetIrq: %p %u %u %#x\n", pPciDev, iIrq, iLevel, uTagSrc));
398 pciSetIrqInternal(pDevIns, pBus, pBusCC, pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
399}
400
401#ifdef IN_RING3
402
403/**
404 * Finds a bridge on the bus which contains the destination bus.
405 *
406 * @return Pointer to the device instance data of the bus or
407 * NULL if no bridge was found.
408 * @param pBus Pointer to the bus to search on.
409 * @param iBus Destination bus number.
410 */
411DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus)
412{
413 /* Search for a fitting bridge. */
414 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
415 {
416 /*
417 * Examine secondary and subordinate bus number.
418 * If the target bus is in the range we pass the request on to the bridge.
419 */
420 PPDMPCIDEV pBridgeTemp = pBus->papBridgesR3[iBridge];
421 AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
422 ("Device is not a PCI bridge but on the list of PCI bridges\n"));
423
424 if ( iBus >= pBridgeTemp->abConfig[VBOX_PCI_SECONDARY_BUS]
425 && iBus <= pBridgeTemp->abConfig[VBOX_PCI_SUBORDINATE_BUS])
426 return pBridgeTemp;
427 }
428
429 /* Nothing found. */
430 return NULL;
431}
432
433static void pciR3Piix3Reset(PPDMPCIDEV pPiix3PciDev)
434{
435 uint8_t *pci_conf = pPiix3PciDev->abConfig;
436
437 pci_conf[0x04] = 0x07; /* master, memory and I/O */
438 pci_conf[0x05] = 0x00;
439 pci_conf[0x06] = 0x00;
440 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
441 pci_conf[0x4c] = 0x4d;
442 pci_conf[0x4e] = 0x03;
443 pci_conf[0x4f] = 0x00;
444 pci_conf[0x60] = 0x80;
445 pci_conf[0x69] = 0x02;
446 pci_conf[0x70] = 0x80;
447 pci_conf[0x76] = 0x0c;
448 pci_conf[0x77] = 0x0c;
449 pci_conf[0x78] = 0x02;
450 pci_conf[0x79] = 0x00;
451 pci_conf[0x80] = 0x00;
452 pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
453 pci_conf[0xa0] = 0x08;
454 pci_conf[0xa2] = 0x00;
455 pci_conf[0xa3] = 0x00;
456 pci_conf[0xa4] = 0x00;
457 pci_conf[0xa5] = 0x00;
458 pci_conf[0xa6] = 0x00;
459 pci_conf[0xa7] = 0x00;
460 pci_conf[0xa8] = 0x0f;
461 pci_conf[0xaa] = 0x00;
462 pci_conf[0xab] = 0x00;
463 pci_conf[0xac] = 0x00;
464 pci_conf[0xae] = 0x00;
465}
466
467/* host irqs corresponding to PCI irqs A-D */
468static const uint8_t pci_irqs[4] = { 11, 10, 9, 11 }; /* bird: added const */
469
470static void pci_bios_init_device(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, PDEVPCIBUS pBus,
471 PPDMPCIDEV pPciDev, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
472{
473 uint32_t *paddr;
474 int pin, pic_irq;
475 uint16_t devclass, vendor_id, device_id;
476
477 devclass = devpciR3GetWord(pPciDev, PCI_CLASS_DEVICE);
478 vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
479 device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
480
481 /* Check if device is present. */
482 if (vendor_id != 0xffff)
483 {
484 switch(devclass)
485 {
486 case 0x0101:
487 if ( (vendor_id == 0x8086)
488 && (device_id == 0x7010 || device_id == 0x7111 || device_id == 0x269e))
489 {
490 /* PIIX3, PIIX4 or ICH6 IDE */
491 devpciR3SetWord(pDevIns, pPciDev, 0x40, 0x8011); /* enable IDE0 + fast timing */
492 devpciR3SetWord(pDevIns, pPciDev, 0x42, 0x8011); /* enable IDE1 + fast timing */
493 goto default_map;
494 }
495 else
496 {
497 /* IDE: we map it as in ISA mode */
498 devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x1f0);
499 devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 1, 0x3f4);
500 devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 2, 0x170);
501 devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 3, 0x374);
502 devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
503 devpciR3GetWord(pPciDev, PCI_COMMAND)
504 | PCI_COMMAND_IOACCESS);
505 }
506 break;
507 case 0x0300:
508 {
509 if (vendor_id != 0x80ee)
510 goto default_map;
511 /* VGA: map frame buffer to default Bochs VBE address */
512 devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0xe0000000);
513 /*
514 * Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
515 * only the framebuffer (i.e., a memory region) is explicitly registered via
516 * devpciR3BiosInitSetRegionAddress, so don't forget to enable I/O decoding.
517 */
518 devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
519 devpciR3GetWord(pPciDev, PCI_COMMAND)
520 | PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS);
521 break;
522 }
523 case 0x0800:
524 /* PIC */
525 vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
526 device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
527 if (vendor_id == 0x1014)
528 {
529 /* IBM */
530 if (device_id == 0x0046 || device_id == 0xFFFF)
531 {
532 /* MPIC & MPIC2 */
533 devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x80800000 + 0x00040000);
534 devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
535 devpciR3GetWord(pPciDev, PCI_COMMAND)
536 | PCI_COMMAND_MEMACCESS);
537 }
538 }
539 break;
540 case 0xff00:
541 if ( (vendor_id == 0x0106b)
542 && (device_id == 0x0017 || device_id == 0x0022))
543 {
544 /* macio bridge */
545 devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x80800000);
546 devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
547 devpciR3GetWord(pPciDev, PCI_COMMAND)
548 | PCI_COMMAND_MEMACCESS);
549 }
550 break;
551 case 0x0604:
552 {
553 /* Init PCI-to-PCI bridge. */
554 devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_PRIMARY_BUS, pBus->iBus);
555
556 AssertMsg(pGlobals->uPciBiosBus < 255, ("Too many bridges on the bus\n"));
557 pGlobals->uPciBiosBus++;
558 devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uPciBiosBus);
559 devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
560
561 /* Add position of this bridge into the array. */
562 paBridgePositions[cBridgeDepth+1] = (pPciDev->uDevFn >> 3);
563
564 /*
565 * The I/O range for the bridge must be aligned to a 4KB boundary.
566 * This does not change anything really as the access to the device is not going
567 * through the bridge but we want to be compliant to the spec.
568 */
569 if ((pGlobals->uPciBiosIo % _4K) != 0)
570 pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
571 LogFunc(("Aligned I/O start address. New address %#x\n", pGlobals->uPciBiosIo));
572 devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0);
573
574 /* The MMIO range for the bridge must be aligned to a 1MB boundary. */
575 if ((pGlobals->uPciBiosMmio % _1M) != 0)
576 pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
577 LogFunc(("Aligned MMIO start address. New address %#x\n", pGlobals->uPciBiosMmio));
578 devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
579
580 /* Save values to compare later to. */
581 uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
582 uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
583
584 /* Init devices behind the bridge and possibly other bridges as well. */
585 PDEVPCIBUS pChildBus = PDMINS_2_DATA(pPciDev->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
586 for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pChildBus->apDevices); uDevFn++)
587 {
588 PPDMPCIDEV pChildPciDev = pChildBus->apDevices[uDevFn];
589 if (pChildPciDev)
590 pci_bios_init_device(pDevIns, pGlobals, pChildBus, pChildPciDev, cBridgeDepth + 1, paBridgePositions);
591 }
592
593 /* The number of bridges behind the this one is now available. */
594 devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
595
596 /*
597 * Set I/O limit register. If there is no device with I/O space behind the bridge
598 * we set a lower value than in the base register.
599 * The result with a real bridge is that no I/O transactions are passed to the secondary
600 * interface. Again this doesn't really matter here but we want to be compliant to the spec.
601 */
602 if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % _4K) != 0))
603 {
604 /* The upper boundary must be one byte less than a 4KB boundary. */
605 pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
606 }
607 devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1);
608
609 /* Same with the MMIO limit register but with 1MB boundary here. */
610 if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % _1M) != 0))
611 {
612 /* The upper boundary must be one byte less than a 1MB boundary. */
613 pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
614 }
615 devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1);
616
617 /*
618 * Set the prefetch base and limit registers. We currently have no device with a prefetchable region
619 * which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
620 * the base register than in the limit register.
621 */
622 devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
623 devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
624 devpciR3SetDWord(pDevIns, pPciDev, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
625 devpciR3SetDWord(pDevIns, pPciDev, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
626 break;
627 }
628 default:
629 default_map:
630 {
631 /* default memory mappings */
632 bool fActiveMemRegion = false;
633 bool fActiveIORegion = false;
634 /*
635 * PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
636 * Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
637 */
638 for (unsigned i = 0; i < (PCI_NUM_REGIONS-1); i++)
639 {
640 uint32_t u32Size;
641 uint8_t u8RessourceType;
642 uint32_t u32Address = 0x10 + i * 4;
643
644 /* Calculate size. */
645 u8RessourceType = devpciR3GetByte(pPciDev, u32Address);
646 devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0xffffffff));
647 u32Size = devpciR3GetDWord(pPciDev, u32Address);
648 bool fIsPio = ((u8RessourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
649 /* Clear resource information depending on resource type. */
650 if (fIsPio) /* I/O */
651 u32Size &= ~(0x01);
652 else /* MMIO */
653 u32Size &= ~(0x0f);
654
655 /*
656 * Invert all bits and add 1 to get size of the region.
657 * (From PCI implementation note)
658 */
659 if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
660 u32Size = (~(u32Size | UINT32_C(0xffff0000))) + 1;
661 else
662 u32Size = (~u32Size) + 1;
663
664 Log2Func(("Size of region %u for device %d on bus %d is %u\n", i, pPciDev->uDevFn, pBus->iBus, u32Size));
665
666 if (u32Size)
667 {
668 if (fIsPio)
669 paddr = &pGlobals->uPciBiosIo;
670 else
671 paddr = &pGlobals->uPciBiosMmio;
672 uint32_t uNew = *paddr;
673 uNew = (uNew + u32Size - 1) & ~(u32Size - 1);
674 if (fIsPio)
675 uNew &= UINT32_C(0xffff);
676 /* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
677 if (!uNew || (uNew <= UINT32_C(0xffffffff) && uNew + u32Size - 1 >= UINT32_C(0xfec00000)))
678 {
679 LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
680 i, pBus->iBus, pPciDev->uDevFn >> 3, pPciDev->uDevFn & 7, vendor_id, device_id)); /** @todo make this a VM start failure later. */
681 /* Undo the mapping mess caused by the size probing. */
682 devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0));
683 }
684 else
685 {
686 LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), i, uNew));
687 devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, i, uNew);
688 if (fIsPio)
689 fActiveIORegion = true;
690 else
691 fActiveMemRegion = true;
692 *paddr = uNew + u32Size;
693 Log2Func(("New address is %#x\n", *paddr));
694 }
695 }
696 }
697
698 /* Update the command word appropriately. */
699 devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
700 devpciR3GetWord(pPciDev, PCI_COMMAND)
701 | (fActiveMemRegion ? PCI_COMMAND_MEMACCESS : 0)
702 | (fActiveIORegion ? PCI_COMMAND_IOACCESS : 0));
703
704 break;
705 }
706 }
707
708 /* map the interrupt */
709 pin = devpciR3GetByte(pPciDev, PCI_INTERRUPT_PIN);
710 if (pin != 0)
711 {
712 uint8_t uBridgeDevFn = pPciDev->uDevFn;
713 pin--;
714
715 /* We need to go up to the host bus to see which irq this device will assert there. */
716 while (cBridgeDepth != 0)
717 {
718 /* Get the pin the device would assert on the bridge. */
719 pin = ((uBridgeDevFn >> 3) + pin) & 3;
720 uBridgeDevFn = paBridgePositions[cBridgeDepth];
721 cBridgeDepth--;
722 }
723
724 pin = pci_slot_get_pirq(pPciDev->uDevFn, pin);
725 pic_irq = pci_irqs[pin];
726 devpciR3SetByte(pDevIns, pPciDev, PCI_INTERRUPT_LINE, pic_irq);
727 }
728 }
729}
730
731/**
732 * Worker for Fake PCI BIOS config, triggered by magic port access by BIOS.
733 *
734 * @returns VBox status code.
735 *
736 * @param pDevIns i440FX device instance.
737 */
738static int pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
739{
740 uint8_t elcr[2] = {0, 0};
741 PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
742 PVM pVM = PDMDevHlpGetVM(pDevIns); Assert(pVM);
743 PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns); Assert(pVM);
744 uint32_t const cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
745 uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
746 RT_NOREF(cbBelow4GB, cbAbove4GB);
747
748 LogRel(("PCI: Setting up resources and interrupts\n"));
749
750 /*
751 * Set the start addresses.
752 */
753 pGlobals->uPciBiosBus = 0;
754 pGlobals->uPciBiosIo = 0xd000;
755 pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
756
757 /*
758 * Activate IRQ mappings.
759 */
760 PPDMPCIDEV pPIIX3 = pDevIns->apPciDevs[1];
761 for (unsigned i = 0; i < 4; i++)
762 {
763 uint8_t irq = pci_irqs[i];
764 /* Set to trigger level. */
765 elcr[irq >> 3] |= (1 << (irq & 7));
766 /* Activate irq remapping in PIIX3. */
767 devpciR3SetByte(pDevIns, pPIIX3, 0x60 + i, irq);
768 }
769
770 /* Tell to the PIC. */
771 VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d0, elcr[0], sizeof(uint8_t));
772 if (rcStrict == VINF_SUCCESS)
773 rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d1, elcr[1], sizeof(uint8_t));
774 if (rcStrict != VINF_SUCCESS)
775 {
776 AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
777 return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
778 }
779
780 /*
781 * Init the devices.
782 */
783 PDEVPCIBUS pBus = &pGlobals->PciBus;
784 for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
785 {
786 PPDMPCIDEV pPciDev = pBus->apDevices[uDevFn];
787 if (pPciDev)
788 {
789 Log2(("PCI: Initializing device %d (%#x)\n", uDevFn, 0x80000000 | (uDevFn << 8)));
790 uint8_t aBridgePositions[256];
791 RT_ZERO(aBridgePositions);
792 pci_bios_init_device(pDevIns, pGlobals, pBus, pPciDev, 0, aBridgePositions);
793 }
794 }
795
796 return VINF_SUCCESS;
797}
798
799#endif /* IN_RING3 */
800
801
802/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
803
804/**
805 * @callback_method_impl{FNIOMIOPORTNEWOUT, PCI address}
806 */
807static DECLCALLBACK(VBOXSTRICTRC)
808pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
809{
810 LogFunc(("uPort=%#x u32=%#x cb=%d\n", uPort, u32, cb));
811 RT_NOREF2(uPort, pvUser);
812 if (cb == 4)
813 {
814 PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
815 PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
816 pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
817 PCI_UNLOCK(pDevIns);
818 }
819 /* else: 440FX does "pass through to the bus" for other writes, what ever that means.
820 * Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
821 return VINF_SUCCESS;
822}
823
824
825/**
826 * @callback_method_impl{FNIOMIOPORTNEWIN, PCI address}
827 */
828static DECLCALLBACK(VBOXSTRICTRC)
829pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
830{
831 RT_NOREF2(uPort, pvUser);
832 if (cb == 4)
833 {
834 PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
835 PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
836 *pu32 = pThis->uConfigReg;
837 PCI_UNLOCK(pDevIns);
838 LogFunc(("uPort=%#x cb=%d -> %#x\n", uPort, cb, *pu32));
839 return VINF_SUCCESS;
840 }
841 /* else: 440FX does "pass through to the bus" for other writes, what ever that means.
842 * Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
843 LogFunc(("uPort=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", uPort, cb));
844 return VERR_IOM_IOPORT_UNUSED;
845}
846
847
848/**
849 * @callback_method_impl{FNIOMIOPORTNEWOUT, PCI data}
850 */
851static DECLCALLBACK(VBOXSTRICTRC)
852pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
853{
854 LogFunc(("uPort=%#x u32=%#x cb=%d\n", uPort, u32, cb));
855 NOREF(pvUser);
856 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
857 if (!(uPort % cb))
858 {
859 PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
860 rcStrict = pci_data_write(pDevIns, PDMINS_2_DATA(pDevIns, PDEVPCIROOT), uPort, u32, cb);
861 PCI_UNLOCK(pDevIns);
862 }
863 else
864 AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", uPort, u32, cb));
865 return rcStrict;
866}
867
868
869/**
870 * @callback_method_impl{FNIOMIOPORTNEWIN, PCI data}
871 */
872static DECLCALLBACK(VBOXSTRICTRC)
873pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
874{
875 NOREF(pvUser);
876 if (!(uPort % cb))
877 {
878 PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
879 VBOXSTRICTRC rcStrict = pci_data_read(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), uPort, cb, pu32);
880 PCI_UNLOCK(pDevIns);
881 LogFunc(("uPort=%#x cb=%#x -> %#x (%Rrc)\n", uPort, cb, *pu32, VBOXSTRICTRC_VAL(rcStrict)));
882 return rcStrict;
883 }
884 AssertMsgFailed(("Read from port %#x cb=%d\n", uPort, cb));
885 return VERR_IOM_IOPORT_UNUSED;
886}
887
888#ifdef IN_RING3
889
890/**
891 * @callback_method_impl{FNIOMIOPORTNEWOUT, PCI data}
892 */
893static DECLCALLBACK(VBOXSTRICTRC)
894pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
895{
896 RT_NOREF2(pvUser, uPort);
897 LogFunc(("uPort=%#x u32=%#x cb=%d\n", uPort, u32, cb));
898 if (cb == 4)
899 {
900 if (u32 == UINT32_C(19200509)) // Richard Adams - Note! In decimal rather hex.
901 {
902 int rc = pciR3FakePCIBIOS(pDevIns);
903 AssertRC(rc);
904 }
905 }
906
907 return VINF_SUCCESS;
908}
909
910/**
911 * @callback_method_impl{FNIOMIOPORTNEWIN, PCI data}
912 */
913static DECLCALLBACK(VBOXSTRICTRC)
914pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
915{
916 RT_NOREF5(pDevIns, pvUser, uPort, pu32, cb);
917 LogFunc(("uPort=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", uPort, cb));
918 return VERR_IOM_IOPORT_UNUSED;
919}
920
921
922/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
923
924/**
925 * Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
926 *
927 * @returns VBox status code.
928 * @param pBus The bus to save.
929 * @param pSSM The saved state handle.
930 */
931static int pciR3CommonSaveExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM)
932{
933 /*
934 * Iterate thru all the devices.
935 */
936 for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
937 {
938 PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
939 if (pDev)
940 {
941 SSMR3PutU32(pSSM, uDevFn);
942 SSMR3PutMem(pSSM, pDev->abConfig, 256); /* Only save 256 bytes here! */
943
944 SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
945
946 /* Save the type an size of all the regions. */
947 for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
948 {
949 SSMR3PutU8(pSSM, pDev->Int.s.aIORegions[iRegion].type);
950 SSMR3PutU64(pSSM, pDev->Int.s.aIORegions[iRegion].size);
951 }
952 }
953 }
954 return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
955}
956
957
958/**
959 * @callback_method_impl{FNSSMDEVSAVEEXEC}
960 */
961static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
962{
963 PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
964
965 /*
966 * Bus state data.
967 */
968 SSMR3PutU32(pSSM, pThis->uConfigReg);
969 SSMR3PutBool(pSSM, pThis->fUseIoApic);
970
971 /*
972 * Save IRQ states.
973 */
974 for (unsigned i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
975 SSMR3PutU32(pSSM, pThis->Piix3.auPciLegacyIrqLevels[i]);
976 for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
977 SSMR3PutU32(pSSM, pThis->auPciApicIrqLevels[i]);
978
979 SSMR3PutU32(pSSM, pThis->Piix3.iAcpiIrqLevel);
980 SSMR3PutS32(pSSM, pThis->Piix3.iAcpiIrq);
981
982 SSMR3PutU32(pSSM, UINT32_MAX); /* separator */
983
984 /*
985 * Join paths with pcibridgeR3SaveExec.
986 */
987 return pciR3CommonSaveExec(&pThis->PciBus, pSSM);
988}
989
990
991/**
992 * Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
993 *
994 * @returns VBox status code.
995 * @param pDevIns The device instance.
996 * @param pBus The bus which data is being loaded.
997 * @param pSSM The saved state handle.
998 * @param uVersion The data version.
999 * @param uPass The pass.
1000 */
1001static int pciR3CommonLoadExec(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1002{
1003 uint32_t u32;
1004 int rc;
1005
1006 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1007
1008 /*
1009 * Iterate thru all the devices and write 0 to the COMMAND register so
1010 * that all the memory is unmapped before we start restoring the saved
1011 * mapping locations.
1012 *
1013 * The register value is restored afterwards so we can do proper
1014 * LogRels in devpciR3CommonRestoreConfig.
1015 */
1016 for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1017 {
1018 PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1019 if (pDev)
1020 {
1021 uint16_t u16 = PCIDevGetCommand(pDev);
1022 devpciR3SetCfg(pDevIns, pDev, VBOX_PCI_COMMAND, 0 /*u32Value*/, 2 /*cb*/);
1023 PCIDevSetCommand(pDev, u16);
1024 Assert(PCIDevGetCommand(pDev) == u16);
1025 }
1026 }
1027
1028 /*
1029 * Iterate all the devices.
1030 */
1031 for (uint32_t uDevFn = 0;; uDevFn++)
1032 {
1033 /* index / terminator */
1034 rc = SSMR3GetU32(pSSM, &u32);
1035 if (RT_FAILURE(rc))
1036 return rc;
1037 if (u32 == UINT32_MAX)
1038 break;
1039 if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1040 || u32 < uDevFn)
1041 {
1042 AssertMsgFailed(("u32=%#x uDevFn=%#x\n", u32, uDevFn));
1043 return rc;
1044 }
1045
1046 /* skip forward to the device checking that no new devices are present. */
1047 for (; uDevFn < u32; uDevFn++)
1048 {
1049 if (pBus->apDevices[uDevFn])
1050 {
1051 LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", uDevFn, pBus->apDevices[uDevFn]->pszNameR3,
1052 PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn])));
1053 if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1054 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1055 uDevFn, pBus->apDevices[uDevFn]->pszNameR3, PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn]));
1056 }
1057 }
1058
1059 /* get the data */
1060 union
1061 {
1062 PDMPCIDEV DevTmp;
1063 uint8_t abDevTmpPadding[RT_UOFFSETOF(PDMPCIDEV, abMsixState)];
1064 } u;
1065 RT_ZERO(u.DevTmp);
1066 u.DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1067 SSMR3GetMem(pSSM, u.DevTmp.abConfig, 256);
1068 if (uVersion < VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1069 {
1070 int32_t i32Temp;
1071 /* Irq value not needed anymore. */
1072 rc = SSMR3GetS32(pSSM, &i32Temp);
1073 if (RT_FAILURE(rc))
1074 return rc;
1075 }
1076 else
1077 {
1078 rc = SSMR3GetS32(pSSM, &u.DevTmp.Int.s.uIrqPinState);
1079 if (RT_FAILURE(rc))
1080 return rc;
1081 }
1082
1083 /* Load the region types and sizes. */
1084 if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES)
1085 {
1086 for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
1087 {
1088 SSMR3GetU8(pSSM, &u.DevTmp.Int.s.aIORegions[iRegion].type);
1089 rc = SSMR3GetU64(pSSM, &u.DevTmp.Int.s.aIORegions[iRegion].size);
1090 AssertLogRelRCReturn(rc, rc);
1091 }
1092 }
1093
1094 /* check that it's still around. */
1095 PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1096 if (!pDev)
1097 {
1098 LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", uDevFn,
1099 PCIDevGetVendorId(&u.DevTmp), PCIDevGetDeviceId(&u.DevTmp)));
1100 if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1101 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1102 uDevFn, PCIDevGetVendorId(&u.DevTmp), PCIDevGetDeviceId(&u.DevTmp));
1103 continue;
1104 }
1105
1106 /* match the vendor id assuming that this will never be changed. */
1107 if ( u.DevTmp.abConfig[0] != pDev->abConfig[0]
1108 || u.DevTmp.abConfig[1] != pDev->abConfig[1])
1109 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
1110 N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1111 uDevFn, pDev->pszNameR3, u.DevTmp.abConfig, pDev->abConfig);
1112
1113 /* commit the loaded device config. */
1114 rc = devpciR3CommonRestoreRegions(pSSM, pDev, u.DevTmp.Int.s.aIORegions,
1115 uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES);
1116 if (RT_FAILURE(rc))
1117 break;
1118 devpciR3CommonRestoreConfig(pDevIns, pDev, &u.DevTmp.abConfig[0]);
1119
1120 pDev->Int.s.uIrqPinState = u.DevTmp.Int.s.uIrqPinState;
1121 }
1122
1123 return VINF_SUCCESS;
1124}
1125
1126
1127/**
1128 * @callback_method_impl{FNSSMDEVLOADEXEC}
1129 */
1130static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1131{
1132 PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1133 PDEVPCIBUS pBus = &pThis->PciBus;
1134 uint32_t u32;
1135 int rc;
1136
1137 /*
1138 * Check the version.
1139 */
1140 if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1141 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1142 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1143
1144 /*
1145 * Bus state data.
1146 */
1147 SSMR3GetU32(pSSM, &pThis->uConfigReg);
1148 if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC)
1149 SSMR3GetBool(pSSM, &pThis->fUseIoApic);
1150
1151 /* Load IRQ states. */
1152 if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1153 {
1154 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
1155 SSMR3GetU32(pSSM, (uint32_t *)&pThis->Piix3.auPciLegacyIrqLevels[i]);
1156 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
1157 SSMR3GetU32(pSSM, (uint32_t *)&pThis->auPciApicIrqLevels[i]);
1158
1159 SSMR3GetU32(pSSM, &pThis->Piix3.iAcpiIrqLevel);
1160 SSMR3GetS32(pSSM, &pThis->Piix3.iAcpiIrq);
1161 }
1162
1163 /* separator */
1164 rc = SSMR3GetU32(pSSM, &u32);
1165 if (RT_FAILURE(rc))
1166 return rc;
1167 if (u32 != UINT32_MAX)
1168 AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1169
1170 /*
1171 * The devices.
1172 */
1173 return pciR3CommonLoadExec(pDevIns, pBus, pSSM, uVersion, uPass);
1174}
1175
1176
1177/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
1178
1179
1180/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
1181
1182/**
1183 * @callback_method_impl{FNDBGFHANDLERDEV}
1184 */
1185static DECLCALLBACK(void) pciR3IrqRouteInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1186{
1187 PPDMPCIDEV pPIIX3 = pDevIns->apPciDevs[1];
1188 NOREF(pszArgs);
1189
1190 uint16_t router = pPIIX3->uDevFn;
1191 pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1192 router >> 8, (router >> 3) & 0x1f, router & 0x7);
1193
1194 for (int i = 0; i < 4; ++i)
1195 {
1196 uint8_t irq_map = devpciR3GetByte(pPIIX3, 0x60 + i);
1197 if (irq_map & 0x80)
1198 pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1199 else
1200 pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1201 }
1202}
1203
1204/**
1205 * @callback_method_impl{FNDBGFHANDLERDEV, 'pirq'}
1206 */
1207DECLCALLBACK(void) devpciR3InfoPIRQ(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1208{
1209 PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1210 NOREF(pszArgs);
1211
1212 pHlp->pfnPrintf(pHlp, "PCI IRQ levels:\n");
1213 for (int i = 0; i < DEVPCI_LEGACY_IRQ_PINS; ++i)
1214 pHlp->pfnPrintf(pHlp, " IRQ%c: %u\n", 'A' + i, pGlobals->Piix3.auPciLegacyIrqLevels[i]);
1215}
1216
1217
1218/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1219
1220/**
1221 * @interface_method_impl{PDMDEVREG,pfnReset}
1222 */
1223static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
1224{
1225 PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1226 PDEVPCIBUS pBus = &pGlobals->PciBus;
1227
1228 /* PCI-specific reset for each device. */
1229 for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1230 {
1231 if (pBus->apDevices[uDevFn])
1232 devpciR3ResetDevice(pDevIns, pBus->apDevices[uDevFn]);
1233 }
1234
1235 pciR3Piix3Reset(pDevIns->apPciDevs[1]);
1236}
1237
1238
1239/**
1240 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1241 */
1242static DECLCALLBACK(int) pciR3Destruct(PPDMDEVINS pDevIns)
1243{
1244 PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1245 if (pGlobals->PciBus.papBridgesR3)
1246 {
1247 PDMDevHlpMMHeapFree(pDevIns, pGlobals->PciBus.papBridgesR3);
1248 pGlobals->PciBus.papBridgesR3 = NULL;
1249 }
1250 return VINF_SUCCESS;
1251}
1252
1253
1254/**
1255 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1256 */
1257static DECLCALLBACK(int) pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1258{
1259 RT_NOREF1(iInstance);
1260 Assert(iInstance == 0);
1261 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1262
1263 /*
1264 * Validate and read configuration.
1265 */
1266 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "IOAPIC", "");
1267
1268 /* query whether we got an IOAPIC */
1269 bool fUseIoApic;
1270 int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
1271 if (RT_FAILURE(rc))
1272 return PDMDEV_SET_ERROR(pDevIns, rc,
1273 N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
1274
1275 Log(("PCI: fUseIoApic=%RTbool fR0Enabled=%RTbool fRCEnabled=%RTbool\n", fUseIoApic, pDevIns->fR0Enabled, pDevIns->fRCEnabled));
1276
1277 /*
1278 * Init data and register the PCI bus.
1279 */
1280 PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1281 PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1282
1283 pGlobals->uPciBiosIo = 0xc000;
1284 pGlobals->uPciBiosMmio = 0xf0000000;
1285 memset((void *)&pGlobals->Piix3.auPciLegacyIrqLevels, 0, sizeof(pGlobals->Piix3.auPciLegacyIrqLevels));
1286 pGlobals->fUseIoApic = fUseIoApic;
1287 memset((void *)&pGlobals->auPciApicIrqLevels, 0, sizeof(pGlobals->auPciApicIrqLevels));
1288
1289 pGlobals->PciBus.fTypePiix3 = true;
1290 pGlobals->PciBus.fTypeIch9 = false;
1291 pGlobals->PciBus.fPureBridge = false;
1292 pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns,
1293 sizeof(PPDMPCIDEV)
1294 * RT_ELEMENTS(pGlobals->PciBus.apDevices));
1295 AssertLogRelReturn(pGlobals->PciBus.papBridgesR3, VERR_NO_MEMORY);
1296
1297 PDEVPCIBUS pBus = &pGlobals->PciBus;
1298 PDMPCIBUSREGCC PciBusReg;
1299 PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1300 PciBusReg.pfnRegisterR3 = devpciR3CommonRegisterDevice;
1301 PciBusReg.pfnRegisterMsiR3 = NULL;
1302 PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1303 PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
1304 PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
1305 PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
1306 PciBusReg.pfnSetIrqR3 = pciSetIrq;
1307 PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1308 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
1309 if (RT_FAILURE(rc))
1310 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
1311 Assert(pBus->iBus == 0);
1312 if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1313 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1314 N_("PCI helper version mismatch; got %#x expected %#x"),
1315 pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1316
1317 /* Disable default device locking. */
1318 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1319 AssertRCReturn(rc, rc);
1320
1321 /*
1322 * Fill in PCI configs and add them to the bus.
1323 */
1324 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1325 AssertPtr(pPciDev);
1326
1327 /* i440FX */
1328 PCIDevSetVendorId( pPciDev, 0x8086); /* Intel */
1329 PCIDevSetDeviceId( pPciDev, 0x1237);
1330 PCIDevSetRevisionId(pPciDev, 0x02);
1331 PCIDevSetClassSub( pPciDev, 0x00); /* host2pci */
1332 PCIDevSetClassBase( pPciDev, 0x06); /* PCI_bridge */
1333 PCIDevSetHeaderType(pPciDev, 0x00);
1334 rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, 0 /*fFlags*/, 0 /*uPciDevNo*/, 0 /*uPciFunNo*/, "i440FX");
1335 AssertLogRelRCReturn(rc, rc);
1336
1337 /* PIIX3 */
1338 PPDMPCIDEV pPiix3PciDev = pDevIns->apPciDevs[1];
1339 PCIDevSetVendorId( pPiix3PciDev, 0x8086); /* Intel */
1340 PCIDevSetDeviceId( pPiix3PciDev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
1341 PCIDevSetClassSub( pPiix3PciDev, 0x01); /* PCI_ISA */
1342 PCIDevSetClassBase( pPiix3PciDev, 0x06); /* PCI_bridge */
1343 PCIDevSetHeaderType(pPiix3PciDev, 0x80); /* PCI_multifunction, generic */
1344 rc = PDMDevHlpPCIRegisterEx(pDevIns, pPiix3PciDev, 0 /*fFlags*/, 1 /*uPciDevNo*/, 0 /*uPciFunNo*/, "PIIX3");
1345 AssertLogRelRCReturn(rc, rc);
1346 pciR3Piix3Reset(pDevIns->apPciDevs[1]);
1347
1348 pBus->iDevSearch = 16;
1349
1350 /*
1351 * Register I/O ports and save state.
1352 */
1353 static const IOMIOPORTDESC s_aAddrDesc[] = { { "PCI address", "PCI address", NULL, NULL }, { NULL, NULL, NULL, NULL } };
1354 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cf8, 1, pciIOPortAddressWrite, pciIOPortAddressRead, "i440FX (PCI)", s_aAddrDesc,
1355 &pGlobals->hIoPortAddress);
1356 AssertLogRelRCReturn(rc, rc);
1357
1358 static const IOMIOPORTDESC s_aDataDesc[] = { { "PCI data", "PCI data", NULL, NULL }, { NULL, NULL, NULL, NULL } };
1359 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cfc, 4, pciIOPortDataWrite, pciIOPortDataRead, "i440FX (PCI)", s_aDataDesc,
1360 &pGlobals->hIoPortData);
1361 AssertLogRelRCReturn(rc, rc);
1362
1363 static const IOMIOPORTDESC s_aMagicDesc[] = { { "PCI magic", NULL, NULL, NULL }, { NULL, NULL, NULL, NULL } };
1364 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0410, 1, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead,
1365 "i440FX (Fake PCI BIOS trigger)", s_aMagicDesc, &pGlobals->hIoPortMagic);
1366 AssertLogRelRCReturn(rc, rc);
1367
1368
1369 rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(*pBus) + 16*128, "pgm",
1370 NULL, NULL, NULL,
1371 NULL, pciR3SaveExec, NULL,
1372 NULL, pciR3LoadExec, NULL);
1373 AssertLogRelRCReturn(rc, rc);
1374
1375 PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
1376 "Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
1377 devpciR3InfoPci);
1378 PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", devpciR3InfoPciIrq);
1379 PDMDevHlpDBGFInfoRegister(pDevIns, "pirq", "Display PIRQ state. (no arguments)", devpciR3InfoPIRQ);
1380 PDMDevHlpDBGFInfoRegister(pDevIns, "irqroute", "Display PCI IRQ routing. (no arguments)", pciR3IrqRouteInfo);
1381
1382 return VINF_SUCCESS;
1383}
1384
1385#else /* !IN_RING3 */
1386
1387/**
1388 * @interface_method_impl{PDMDEVREGR0,pfnConstruct}
1389 */
1390static DECLCALLBACK(int) pciRZRootConstruct(PPDMDEVINS pDevIns)
1391{
1392 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1393 PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1394 PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1395
1396 /* Mirror the ring-3 device lock disabling: */
1397 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1398 AssertRCReturn(rc, rc);
1399
1400 /* Set up the RZ PCI bus callbacks: */
1401 PDMPCIBUSREGCC PciBusReg;
1402 PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1403 PciBusReg.iBus = pGlobals->PciBus.iBus;
1404 PciBusReg.pfnSetIrq = pciSetIrq;
1405 PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1406 rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
1407 AssertRCReturn(rc, rc);
1408
1409 /* Set up I/O port callbacks, except for the magic port: */
1410 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pGlobals->hIoPortAddress, pciIOPortAddressWrite, pciIOPortAddressRead, NULL);
1411 AssertLogRelRCReturn(rc, rc);
1412
1413 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pGlobals->hIoPortData, pciIOPortDataWrite, pciIOPortDataRead, NULL);
1414 AssertLogRelRCReturn(rc, rc);
1415
1416 return rc;
1417}
1418
1419#endif /* !IN_RING3 */
1420
1421/**
1422 * The device registration structure.
1423 */
1424const PDMDEVREG g_DevicePCI =
1425{
1426 /* .u32Version = */ PDM_DEVREG_VERSION,
1427 /* .uReserved0 = */ 0,
1428 /* .szName = */ "pci",
1429 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 | PDM_DEVREG_FLAGS_NEW_STYLE,
1430 /* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI | PDM_DEVREG_CLASS_BUS_ISA,
1431 /* .cMaxInstances = */ 1,
1432 /* .uSharedVersion = */ 42,
1433 /* .cbInstanceShared = */ sizeof(DEVPCIROOT),
1434 /* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
1435 /* .cbInstanceRC = */ sizeof(DEVPCIBUSRC),
1436 /* .cMaxPciDevices = */ 2,
1437 /* .cMaxMsixVectors = */ 0,
1438 /* .pszDescription = */ "i440FX PCI bridge and PIIX3 ISA bridge.",
1439#if defined(IN_RING3)
1440 /* .pszRCMod = */ "VBoxDDRC.rc",
1441 /* .pszR0Mod = */ "VBoxDDR0.r0",
1442 /* .pfnConstruct = */ pciR3Construct,
1443 /* .pfnDestruct = */ pciR3Destruct,
1444 /* .pfnRelocate = */ NULL,
1445 /* .pfnMemSetup = */ NULL,
1446 /* .pfnPowerOn = */ NULL,
1447 /* .pfnReset = */ pciR3Reset,
1448 /* .pfnSuspend = */ NULL,
1449 /* .pfnResume = */ NULL,
1450 /* .pfnAttach = */ NULL,
1451 /* .pfnDetach = */ NULL,
1452 /* .pfnQueryInterface = */ NULL,
1453 /* .pfnInitComplete = */ NULL,
1454 /* .pfnPowerOff = */ NULL,
1455 /* .pfnSoftReset = */ NULL,
1456 /* .pfnReserved0 = */ NULL,
1457 /* .pfnReserved1 = */ NULL,
1458 /* .pfnReserved2 = */ NULL,
1459 /* .pfnReserved3 = */ NULL,
1460 /* .pfnReserved4 = */ NULL,
1461 /* .pfnReserved5 = */ NULL,
1462 /* .pfnReserved6 = */ NULL,
1463 /* .pfnReserved7 = */ NULL,
1464#elif defined(IN_RING0)
1465 /* .pfnEarlyConstruct = */ NULL,
1466 /* .pfnConstruct = */ pciRZRootConstruct,
1467 /* .pfnDestruct = */ NULL,
1468 /* .pfnFinalDestruct = */ NULL,
1469 /* .pfnRequest = */ NULL,
1470 /* .pfnReserved0 = */ NULL,
1471 /* .pfnReserved1 = */ NULL,
1472 /* .pfnReserved2 = */ NULL,
1473 /* .pfnReserved3 = */ NULL,
1474 /* .pfnReserved4 = */ NULL,
1475 /* .pfnReserved5 = */ NULL,
1476 /* .pfnReserved6 = */ NULL,
1477 /* .pfnReserved7 = */ NULL,
1478#elif defined(IN_RC)
1479 /* .pfnConstruct = */ pciRZRootConstruct,
1480 /* .pfnReserved0 = */ NULL,
1481 /* .pfnReserved1 = */ NULL,
1482 /* .pfnReserved2 = */ NULL,
1483 /* .pfnReserved3 = */ NULL,
1484 /* .pfnReserved4 = */ NULL,
1485 /* .pfnReserved5 = */ NULL,
1486 /* .pfnReserved6 = */ NULL,
1487 /* .pfnReserved7 = */ NULL,
1488#else
1489# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1490#endif
1491 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
1492
1493};
1494
1495
1496
1497/* -=-=-=-=-=- The PCI bridge specific bits -=-=-=-=-=- */
1498
1499/**
1500 * @interface_method_impl{PDMPCIBUSREGR3,pfnSetIrqR3}
1501 */
1502static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
1503{
1504 LogFlow(("pcibridgeSetIrq: %p %u %u %#x\n", pPciDev, iIrq, iLevel, uTagSrc));
1505
1506 /*
1507 * The PCI-to-PCI bridge specification defines how the interrupt pins
1508 * are routed from the secondary to the primary bus (see chapter 9).
1509 * iIrq gives the interrupt pin the pci device asserted.
1510 * We change iIrq here according to the spec and call the SetIrq function
1511 * of our parent passing the device which asserted the interrupt instead of the device of the bridge.
1512 */
1513 PDEVPCIBUS pBus;
1514 uint8_t uDevFnBridge;
1515 int iIrqPinBridge;
1516 PPDMDEVINS pDevInsBus = devpcibridgeCommonSetIrqRootWalk(pDevIns, pPciDev, iIrq, &pBus, &uDevFnBridge, &iIrqPinBridge);
1517 AssertReturnVoid(pDevInsBus);
1518 AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
1519 Assert(pDevInsBus->pReg == &g_DevicePCI);
1520
1521 pciSetIrqInternal(pDevInsBus, DEVPCIBUS_2_DEVPCIROOT(pBus), PDMINS_2_DATA_CC(pDevInsBus, PDEVPCIBUSCC),
1522 uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
1523}
1524
1525#ifdef IN_RING3
1526
1527/**
1528 * @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
1529 */
1530static DECLCALLBACK(VBOXSTRICTRC) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
1531 uint32_t u32Address, unsigned cb, uint32_t u32Value)
1532{
1533 LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d u32Value=%u\n", pDevIns, iBus, iDevice, u32Address, cb, u32Value));
1534 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1535 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1536
1537 /* If the current bus is not the target bus search for the bus which contains the device. */
1538 if (iBus != pDevIns->apPciDevs[0]->abConfig[VBOX_PCI_SECONDARY_BUS])
1539 {
1540 PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1541 if (pBridgeDevice)
1542 {
1543 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1544 rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice,
1545 u32Address, cb, u32Value);
1546 }
1547 }
1548 else
1549 {
1550 /* This is the target bus, pass the write to the device. */
1551 PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1552 if (pPciDev)
1553 {
1554 LogFunc(("%s: addr=%02x val=%08x len=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
1555 rcStrict = VINF_PDM_PCI_DO_DEFAULT;
1556 if (pPciDev->Int.s.pfnConfigWrite)
1557 rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, u32Value);
1558 if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
1559 rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
1560 pPciDev, u32Address, cb, u32Value);
1561 }
1562 }
1563 return rcStrict;
1564}
1565
1566
1567/**
1568 * @callback_method_impl{FNPCIBRIDGECONFIGREAD}
1569 */
1570static DECLCALLBACK(VBOXSTRICTRC) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
1571 uint32_t u32Address, unsigned cb, uint32_t *pu32Value)
1572{
1573 LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1574 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1575 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1576
1577 /* If the current bus is not the target bus search for the bus which contains the device. */
1578 if (iBus != pDevIns->apPciDevs[0]->abConfig[VBOX_PCI_SECONDARY_BUS])
1579 {
1580 PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1581 if (pBridgeDevice)
1582 {
1583 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
1584 rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns),
1585 iBus, iDevice, u32Address, cb, pu32Value);
1586 }
1587 else
1588 *pu32Value = UINT32_MAX;
1589 }
1590 else
1591 {
1592 /* This is the target bus, pass the read to the device. */
1593 PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1594 if (pPciDev)
1595 {
1596 rcStrict = VINF_PDM_PCI_DO_DEFAULT;
1597 if (pPciDev->Int.s.pfnConfigRead)
1598 rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, pu32Value);
1599 if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
1600 rcStrict = devpciR3CommonConfigReadWorker(pPciDev, u32Address, cb, pu32Value);
1601
1602 LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, *pu32Value, cb));
1603 }
1604 else
1605 *pu32Value = UINT32_MAX;
1606 }
1607
1608 return rcStrict;
1609}
1610
1611
1612/**
1613 * @callback_method_impl{FNSSMDEVSAVEEXEC}
1614 */
1615static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1616{
1617 PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1618 return pciR3CommonSaveExec(pThis, pSSM);
1619}
1620
1621
1622/**
1623 * @callback_method_impl{FNSSMDEVLOADEXEC}
1624 */
1625static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1626{
1627 PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1628 if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1629 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1630 return pciR3CommonLoadExec(pDevIns, pThis, pSSM, uVersion, uPass);
1631}
1632
1633
1634/**
1635 * @interface_method_impl{PDMDEVREG,pfnReset}
1636 */
1637static DECLCALLBACK(void) pcibridgeR3Reset(PPDMDEVINS pDevIns)
1638{
1639 /* Reset config space to default values. */
1640 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1641 pPciDev->abConfig[VBOX_PCI_PRIMARY_BUS] = 0;
1642 pPciDev->abConfig[VBOX_PCI_SECONDARY_BUS] = 0;
1643 pPciDev->abConfig[VBOX_PCI_SUBORDINATE_BUS] = 0;
1644}
1645
1646
1647/**
1648 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1649 */
1650static DECLCALLBACK(int) pcibridgeR3Destruct(PPDMDEVINS pDevIns)
1651{
1652 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1653 if (pBus->papBridgesR3)
1654 {
1655 PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
1656 pBus->papBridgesR3 = NULL;
1657 }
1658 return VINF_SUCCESS;
1659}
1660
1661
1662/**
1663 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1664 */
1665static DECLCALLBACK(int) pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1666{
1667 RT_NOREF(iInstance);
1668 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1669
1670 /*
1671 * Validate and read configuration.
1672 */
1673 if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
1674 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1675
1676 /* check if RC code is enabled. */
1677 bool fGCEnabled;
1678 int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1679 if (RT_FAILURE(rc))
1680 return PDMDEV_SET_ERROR(pDevIns, rc,
1681 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
1682
1683 /* check if R0 code is enabled. */
1684 bool fR0Enabled;
1685 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1686 if (RT_FAILURE(rc))
1687 return PDMDEV_SET_ERROR(pDevIns, rc,
1688 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
1689 Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
1690
1691 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1692 PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1693
1694 /*
1695 * Init data and register the PCI bus.
1696 */
1697 pBus->fTypePiix3 = true;
1698 pBus->fTypeIch9 = false;
1699 pBus->fPureBridge = true;
1700 pBus->papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pBus->apDevices));
1701 AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
1702
1703 PDMPCIBUSREGCC PciBusReg;
1704 PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1705 PciBusReg.pfnRegisterR3 = devpcibridgeR3CommonRegisterDevice;
1706 PciBusReg.pfnRegisterMsiR3 = NULL;
1707 PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1708 PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
1709 PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
1710 PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
1711 PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
1712 PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1713 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
1714 if (RT_FAILURE(rc))
1715 return PDMDEV_SET_ERROR(pDevIns, rc,
1716 N_("Failed to register ourselves as a PCI Bus"));
1717 Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
1718 if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1719 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1720 N_("PCI helper version mismatch; got %#x expected %#x"),
1721 pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1722
1723 /*
1724 * Fill in PCI configs and add them to the bus.
1725 */
1726 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1727 PCIDevSetVendorId( pPciDev, 0x8086); /* Intel */
1728 PCIDevSetDeviceId( pPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
1729 PCIDevSetRevisionId(pPciDev, 0xf2);
1730 PCIDevSetClassSub( pPciDev, 0x04); /* pci2pci */
1731 PCIDevSetClassBase( pPciDev, 0x06); /* PCI_bridge */
1732 PCIDevSetClassProg( pPciDev, 0x01); /* Supports subtractive decoding. */
1733 PCIDevSetHeaderType(pPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
1734 PCIDevSetCommand( pPciDev, 0x0000);
1735 PCIDevSetStatus( pPciDev, 0x0020); /* 66MHz Capable. */
1736 PCIDevSetInterruptLine(pPciDev, 0x00); /* This device does not assert interrupts. */
1737
1738 /*
1739 * This device does not generate interrupts. Interrupt delivery from
1740 * devices attached to the bus is unaffected.
1741 */
1742 PCIDevSetInterruptPin(pPciDev, 0x00);
1743
1744 /*
1745 * Register this PCI bridge. The called function will take care on which bus we will get registered.
1746 */
1747 rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, PDMPCIDEVREG_F_PCI_BRIDGE, PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
1748 PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "pcibridge");
1749 if (RT_FAILURE(rc))
1750 return rc;
1751 pPciDev->Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
1752 pPciDev->Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
1753
1754 pBus->iDevSearch = 0;
1755
1756 /*
1757 * Register SSM handlers. We use the same saved state version as for the host bridge
1758 * to make changes easier.
1759 */
1760 rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(*pBus) + 16*128, "pgm",
1761 NULL, NULL, NULL,
1762 NULL, pcibridgeR3SaveExec, NULL,
1763 NULL, pcibridgeR3LoadExec, NULL);
1764 if (RT_FAILURE(rc))
1765 return rc;
1766
1767 return VINF_SUCCESS;
1768}
1769
1770#else /* !IN_RING3 */
1771
1772/**
1773 * @interface_method_impl{PDMDEVREGR0,pfnConstruct}
1774 */
1775static DECLCALLBACK(int) pcibridgeRZConstruct(PPDMDEVINS pDevIns)
1776{
1777 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1778 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1779 PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1780
1781 PDMPCIBUSREGCC PciBusReg;
1782 PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1783 PciBusReg.iBus = pBus->iBus;
1784 PciBusReg.pfnSetIrq = pcibridgeSetIrq;
1785 PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1786 int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
1787 AssertRC(rc);
1788
1789 return rc;
1790}
1791
1792#endif /* !IN_RING3 */
1793
1794/**
1795 * The device registration structure
1796 * for the PCI-to-PCI bridge.
1797 */
1798const PDMDEVREG g_DevicePCIBridge =
1799{
1800 /* .u32Version = */ PDM_DEVREG_VERSION,
1801 /* .uReserved0 = */ 0,
1802 /* .szName = */ "pcibridge",
1803 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 | PDM_DEVREG_FLAGS_NEW_STYLE,
1804 /* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI,
1805 /* .cMaxInstances = */ ~0U,
1806 /* .uSharedVersion = */ 42,
1807 /* .cbInstanceShared = */ sizeof(DEVPCIBUS),
1808 /* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
1809 /* .cbInstanceRC = */ 0,
1810 /* .cMaxPciDevices = */ 1,
1811 /* .cMaxMsixVectors = */ 0,
1812 /* .pszDescription = */ "82801 Mobile PCI to PCI bridge",
1813#if defined(IN_RING3)
1814 /* .pszRCMod = */ "VBoxDDRC.rc",
1815 /* .pszR0Mod = */ "VBoxDDR0.r0",
1816 /* .pfnConstruct = */ pcibridgeR3Construct,
1817 /* .pfnDestruct = */ pcibridgeR3Destruct,
1818 /* .pfnRelocate = */ NULL,
1819 /* .pfnMemSetup = */ NULL,
1820 /* .pfnPowerOn = */ NULL,
1821 /* .pfnReset = */ pcibridgeR3Reset,
1822 /* .pfnSuspend = */ NULL,
1823 /* .pfnResume = */ NULL,
1824 /* .pfnAttach = */ NULL,
1825 /* .pfnDetach = */ NULL,
1826 /* .pfnQueryInterface = */ NULL,
1827 /* .pfnInitComplete = */ NULL,
1828 /* .pfnPowerOff = */ NULL,
1829 /* .pfnSoftReset = */ NULL,
1830 /* .pfnReserved0 = */ NULL,
1831 /* .pfnReserved1 = */ NULL,
1832 /* .pfnReserved2 = */ NULL,
1833 /* .pfnReserved3 = */ NULL,
1834 /* .pfnReserved4 = */ NULL,
1835 /* .pfnReserved5 = */ NULL,
1836 /* .pfnReserved6 = */ NULL,
1837 /* .pfnReserved7 = */ NULL,
1838#elif defined(IN_RING0)
1839 /* .pfnEarlyConstruct = */ NULL,
1840 /* .pfnConstruct = */ pcibridgeRZConstruct,
1841 /* .pfnDestruct = */ NULL,
1842 /* .pfnFinalDestruct = */ NULL,
1843 /* .pfnRequest = */ NULL,
1844 /* .pfnReserved0 = */ NULL,
1845 /* .pfnReserved1 = */ NULL,
1846 /* .pfnReserved2 = */ NULL,
1847 /* .pfnReserved3 = */ NULL,
1848 /* .pfnReserved4 = */ NULL,
1849 /* .pfnReserved5 = */ NULL,
1850 /* .pfnReserved6 = */ NULL,
1851 /* .pfnReserved7 = */ NULL,
1852#elif defined(IN_RC)
1853 /* .pfnConstruct = */ pcibridgeRZConstruct,
1854 /* .pfnReserved0 = */ NULL,
1855 /* .pfnReserved1 = */ NULL,
1856 /* .pfnReserved2 = */ NULL,
1857 /* .pfnReserved3 = */ NULL,
1858 /* .pfnReserved4 = */ NULL,
1859 /* .pfnReserved5 = */ NULL,
1860 /* .pfnReserved6 = */ NULL,
1861 /* .pfnReserved7 = */ NULL,
1862#else
1863# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1864#endif
1865 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
1866};
1867
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