DevPCI.cpp@ 77807

Last change on this file since 77807 was 77663, checked in by vboxsync, 6 years ago
FakeBios: Enable fast timing in PIIX/ICH IDETIM register. This convinces NetWare's IDEATA.HAM driver to use BMDMA.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 67.8 KB

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1	/* $Id: DevPCI.cpp 77663 2019-03-12 12:51:54Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*
5	* @remarks New code shall be added to DevPciIch9.cpp as that will become
6	* the common PCI bus code soon. Don't fix code in both DevPCI.cpp
7	* and DevPciIch9.cpp when it's possible to just make the latter
8	* version common. Common code uses the 'devpci' prefix, is
9	* prototyped in DevPciInternal.h, and is defined in DevPciIch9.cpp.
10	*/
11
12	/*
13	* Copyright (C) 2006-2019 Oracle Corporation
14	*
15	* This file is part of VirtualBox Open Source Edition (OSE), as
16	* available from http://www.virtualbox.org. This file is free software;
17	* you can redistribute it and/or modify it under the terms of the GNU
18	* General Public License (GPL) as published by the Free Software
19	* Foundation, in version 2 as it comes in the "COPYING" file of the
20	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
21	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* QEMU PCI bus manager
27	*
28	* Copyright (c) 2004 Fabrice Bellard
29	*
30	* Permission is hereby granted, free of charge, to any person obtaining a copy
31	* of this software and associated documentation files (the "Software"), to deal
32	* in the Software without restriction, including without limitation the rights
33	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
34	* copies of the Software, and to permit persons to whom the Software is
35	* furnished to do so, subject to the following conditions:
36	*
37	* The above copyright notice and this permission notice shall be included in
38	* all copies or substantial portions of the Software.
39	*
40	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
41	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
42	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
44	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
45	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
46	* THE SOFTWARE.
47	*/
48
49
50	/*********************************************************************************************************************************
51	* Header Files *
52	*********************************************************************************************************************************/
53	#define LOG_GROUP LOG_GROUP_DEV_PCI
54	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
55	#include <VBox/vmm/pdmpcidev.h>
56	#include <VBox/vmm/pdmdev.h>
57	#include <VBox/vmm/mm.h>
58	#include <iprt/asm.h>
59	#include <iprt/assert.h>
60	#include <iprt/string.h>
61
62	#include "PciInline.h"
63	#include "VBoxDD.h"
64	#include "DevPciInternal.h"
65
66
67	/*********************************************************************************************************************************
68	* Defined Constants And Macros *
69	*********************************************************************************************************************************/
70	/** Saved state version of the PCI bus device. */
71	#define VBOX_PCI_SAVED_STATE_VERSION VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES
72	/** Adds I/O region types and sizes for dealing changes in resource regions. */
73	#define VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES 4
74	/** Before region sizes, the first named one.
75	* Looking at the code though, we support even older version. */
76	#define VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES 3
77	/** Notes whether we use the I/O APIC. */
78	#define VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC 2
79
80
81	/*********************************************************************************************************************************
82	* Internal Functions *
83	*********************************************************************************************************************************/
84	RT_C_DECLS_BEGIN
85
86	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
87	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
88	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
89	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
90	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
91	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
92
93	#ifdef IN_RING3
94	DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus);
95	#endif
96
97	RT_C_DECLS_END
98
99	#define DEBUG_PCI
100
101	#define PCI_VENDOR_ID 0x00 /* 16 bits */
102	#define PCI_DEVICE_ID 0x02 /* 16 bits */
103	#define PCI_COMMAND 0x04 /* 16 bits */
104	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
105	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
106	#define PCI_CLASS_DEVICE 0x0a /* Device class */
107	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
108	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
109	#define PCI_MIN_GNT 0x3e /* 8 bits */
110	#define PCI_MAX_LAT 0x3f /* 8 bits */
111
112
113	static int pci_data_write(PDEVPCIROOT pGlobals, uint32_t addr, uint32_t val, int len)
114	{
115	uint8_t iBus, iDevice;
116	uint32_t config_addr;
117
118	LogFunc(("addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
119
120	if (!(pGlobals->uConfigReg & (1 << 31))) {
121	return VINF_SUCCESS;
122	}
123	if ((pGlobals->uConfigReg & 0x3) != 0) {
124	return VINF_SUCCESS;
125	}
126	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
127	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
128	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
129	RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
130	if (iBus != 0)
131	{
132	if (pGlobals->PciBus.cBridges)
133	{
134	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
135	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
136	if (pBridgeDevice)
137	{
138	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
139	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, config_addr, val, len);
140	}
141	#else
142	RT_NOREF2(val, len);
143	return VINF_IOM_R3_IOPORT_WRITE;
144	#endif
145	}
146	}
147	else
148	{
149	R3PTRTYPE(PDMPCIDEV *) pci_dev = pGlobals->PciBus.apDevices[iDevice];
150	if (pci_dev)
151	{
152	#ifdef IN_RING3
153	LogFunc(("%s: addr=%02x val=%08x len=%d\n", pci_dev->pszNameR3, config_addr, val, len));
154	return VBOXSTRICTRC_TODO(pci_dev->Int.s.pfnConfigWrite(pci_dev->Int.s.CTX_SUFF(pDevIns), pci_dev, config_addr, val, len));
155	#else
156	return VINF_IOM_R3_IOPORT_WRITE;
157	#endif
158	}
159	}
160	return VINF_SUCCESS;
161	}
162
163	static int pci_data_read(PDEVPCIROOT pGlobals, uint32_t addr, int len, uint32_t *pu32)
164	{
165	uint8_t iBus, iDevice;
166	uint32_t config_addr;
167
168	*pu32 = 0xffffffff;
169
170	if (!(pGlobals->uConfigReg & (1 << 31)))
171	return VINF_SUCCESS;
172	if ((pGlobals->uConfigReg & 0x3) != 0)
173	return VINF_SUCCESS;
174	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
175	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
176	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
177	RT_UNTRUSTED_VALIDATED_FENCE();
178	if (iBus != 0)
179	{
180	if (pGlobals->PciBus.cBridges)
181	{
182	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
183	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
184	if (pBridgeDevice)
185	{
186	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
187	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, config_addr, len);
188	}
189	#else
190	NOREF(len);
191	return VINF_IOM_R3_IOPORT_READ;
192	#endif
193	}
194	}
195	else
196	{
197	R3PTRTYPE(PDMPCIDEV *) pci_dev = pGlobals->PciBus.apDevices[iDevice];
198	if (pci_dev)
199	{
200	#ifdef IN_RING3
201	*pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev->Int.s.CTX_SUFF(pDevIns), pci_dev, config_addr, len);
202	LogFunc(("%s: addr=%02x val=%08x len=%d\n", pci_dev->pszNameR3, config_addr, *pu32, len));
203	#else
204	NOREF(len);
205	return VINF_IOM_R3_IOPORT_READ;
206	#endif
207	}
208	}
209
210	return VINF_SUCCESS;
211	}
212
213
214
215	/* return the global irq number corresponding to a given device irq
216	pin. We could also use the bus number to have a more precise
217	mapping.
218	This is the implementation note described in the PCI spec chapter 2.2.6 */
219	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
220	{
221	int slot_addend;
222	slot_addend = (uDevFn >> 3) - 1;
223	return (irq_num + slot_addend) & 3;
224	}
225
226	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
227	{
228	return (irq_num + (uDevFn >> 3)) & 7;
229	}
230
231	static inline int get_pci_irq_apic_level(PDEVPCIROOT pGlobals, int irq_num)
232	{
233	return (pGlobals->auPciApicIrqLevels[irq_num] != 0);
234	}
235
236	static void apic_set_irq(PDEVPCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, int iAcpiIrq, uint32_t uTagSrc)
237	{
238	/* This is only allowed to be called with a pointer to the host bus. */
239	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
240
241	if (iAcpiIrq == -1) {
242	int apic_irq, apic_level;
243	PDEVPCIROOT pGlobals = DEVPCIBUS_2_DEVPCIROOT(pBus);
244	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
245
246	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
247	ASMAtomicIncU32(&pGlobals->auPciApicIrqLevels[irq_num]);
248	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
249	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
250
251	apic_irq = irq_num + 0x10;
252	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
253	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
254	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
255	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
256
257	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
258	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
259	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
260	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
261	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
262	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
263	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
264	}
265	} else {
266	Log3Func(("%s: irq_num1=%d level=%d iAcpiIrq=%d\n",
267	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iAcpiIrq));
268	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iAcpiIrq, iLevel, uTagSrc);
269	}
270	}
271
272	DECLINLINE(int) get_pci_irq_level(PDEVPCIROOT pGlobals, int irq_num)
273	{
274	return (pGlobals->Piix3.auPciLegacyIrqLevels[irq_num] != 0);
275	}
276
277	/**
278	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
279	*
280	* @param pGlobals Device instance of the host PCI Bus.
281	* @param uDevFn The device number on the host bus which will raise the IRQ
282	* @param pPciDev The PCI device structure which raised the interrupt.
283	* @param iIrq IRQ number to set.
284	* @param iLevel IRQ level.
285	* @param uTagSrc The IRQ tag and source ID (for tracing).
286	* @remark uDevFn and pPciDev->uDevFn are not the same if the device is behind
287	* a bridge. In that case uDevFn will be the slot of the bridge which
288	* is needed to calculate the PIRQ value.
289	*/
290	static void pciSetIrqInternal(PDEVPCIROOT pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
291	{
292	PDEVPCIBUS pBus = &pGlobals->PciBus;
293	uint8_t *pbCfg = pGlobals->Piix3.PIIX3State.dev.abConfig;
294	const bool fIsAcpiDevice = pPciDev->abConfig[2] == 0x13 && pPciDev->abConfig[3] == 0x71;
295	/* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
296	* is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
297	* See the \_SB_.PCI0._PRT method in vbox.dsl.
298	*/
299	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
300	int pic_irq, pic_level;
301
302	/* Check if the state changed. */
303	if (pPciDev->Int.s.uIrqPinState != iLevel)
304	{
305	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
306
307	/* Send interrupt to I/O APIC only. */
308	if (fIsApicEnabled)
309	{
310	if (fIsAcpiDevice)
311	/*
312	* ACPI needs special treatment since SCI is hardwired and
313	* should not be affected by PCI IRQ routing tables at the
314	* same time SCI IRQ is shared in PCI sense hence this
315	* kludge (i.e. we fetch the hardwired value from ACPIs
316	* PCI device configuration space).
317	*/
318	apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->abConfig[PCI_INTERRUPT_LINE], uTagSrc);
319	else
320	apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
321	return;
322	}
323
324	if (fIsAcpiDevice)
325	{
326	/* As per above treat ACPI in a special way */
327	pic_irq = pPciDev->abConfig[PCI_INTERRUPT_LINE];
328	pGlobals->Piix3.iAcpiIrq = pic_irq;
329	pGlobals->Piix3.iAcpiIrqLevel = iLevel & PDM_IRQ_LEVEL_HIGH;
330	}
331	else
332	{
333	int irq_num;
334	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
335
336	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
337	ASMAtomicIncU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
338	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
339	ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
340
341	/* now we change the pic irq level according to the piix irq mappings */
342	pic_irq = pbCfg[0x60 + irq_num];
343	if (pic_irq >= 16)
344	{
345	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
346	{
347	ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
348	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
349	}
350
351	return;
352	}
353	}
354
355	/* the pic level is the logical OR of all the PCI irqs mapped to it */
356	pic_level = 0;
357	if (pic_irq == pbCfg[0x60])
358	pic_level \|= get_pci_irq_level(pGlobals, 0);
359	if (pic_irq == pbCfg[0x61])
360	pic_level \|= get_pci_irq_level(pGlobals, 1);
361	if (pic_irq == pbCfg[0x62])
362	pic_level \|= get_pci_irq_level(pGlobals, 2);
363	if (pic_irq == pbCfg[0x63])
364	pic_level \|= get_pci_irq_level(pGlobals, 3);
365	if (pic_irq == pGlobals->Piix3.iAcpiIrq)
366	pic_level \|= pGlobals->Piix3.iAcpiIrqLevel;
367
368	Log3Func(("%s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
369	R3STRING(pPciDev->pszNameR3), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
370	pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level, uTagSrc);
371
372	/** @todo optimize pci irq flip-flop some rainy day. */
373	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
374	pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
375	}
376	}
377
378
379	/**
380	* @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
381	*/
382	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
383	{
384	pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
385	}
386
387	#ifdef IN_RING3
388
389	/**
390	* Finds a bridge on the bus which contains the destination bus.
391	*
392	* @return Pointer to the device instance data of the bus or
393	* NULL if no bridge was found.
394	* @param pBus Pointer to the bus to search on.
395	* @param iBus Destination bus number.
396	*/
397	DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus)
398	{
399	/* Search for a fitting bridge. */
400	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
401	{
402	/*
403	* Examine secondary and subordinate bus number.
404	* If the target bus is in the range we pass the request on to the bridge.
405	*/
406	PPDMPCIDEV pBridgeTemp = pBus->papBridgesR3[iBridge];
407	AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
408	("Device is not a PCI bridge but on the list of PCI bridges\n"));
409
410	if ( iBus >= pBridgeTemp->abConfig[VBOX_PCI_SECONDARY_BUS]
411	&& iBus <= pBridgeTemp->abConfig[VBOX_PCI_SUBORDINATE_BUS])
412	return pBridgeTemp;
413	}
414
415	/* Nothing found. */
416	return NULL;
417	}
418
419	static void pciR3Piix3Reset(PIIX3ISABRIDGE *d)
420	{
421	uint8_t *pci_conf = d->dev.abConfig;
422
423	pci_conf[0x04] = 0x07; /* master, memory and I/O */
424	pci_conf[0x05] = 0x00;
425	pci_conf[0x06] = 0x00;
426	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
427	pci_conf[0x4c] = 0x4d;
428	pci_conf[0x4e] = 0x03;
429	pci_conf[0x4f] = 0x00;
430	pci_conf[0x60] = 0x80;
431	pci_conf[0x69] = 0x02;
432	pci_conf[0x70] = 0x80;
433	pci_conf[0x76] = 0x0c;
434	pci_conf[0x77] = 0x0c;
435	pci_conf[0x78] = 0x02;
436	pci_conf[0x79] = 0x00;
437	pci_conf[0x80] = 0x00;
438	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
439	pci_conf[0xa0] = 0x08;
440	pci_conf[0xa2] = 0x00;
441	pci_conf[0xa3] = 0x00;
442	pci_conf[0xa4] = 0x00;
443	pci_conf[0xa5] = 0x00;
444	pci_conf[0xa6] = 0x00;
445	pci_conf[0xa7] = 0x00;
446	pci_conf[0xa8] = 0x0f;
447	pci_conf[0xaa] = 0x00;
448	pci_conf[0xab] = 0x00;
449	pci_conf[0xac] = 0x00;
450	pci_conf[0xae] = 0x00;
451	}
452
453	/* host irqs corresponding to PCI irqs A-D */
454	static const uint8_t pci_irqs[4] = { 11, 10, 9, 11 }; /* bird: added const */
455
456	static void pci_bios_init_device(PDEVPCIROOT pGlobals, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
457	{
458	uint32_t *paddr;
459	int pin, pic_irq;
460	uint16_t devclass, vendor_id, device_id;
461
462	devclass = devpciR3GetWord(pPciDev, PCI_CLASS_DEVICE);
463	vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
464	device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
465
466	/* Check if device is present. */
467	if (vendor_id != 0xffff)
468	{
469	switch(devclass)
470	{
471	case 0x0101:
472	if ( (vendor_id == 0x8086)
473	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
474	{
475	/* PIIX3, PIIX4 or ICH6 IDE */
476	devpciR3SetWord(pPciDev, 0x40, 0x8011); /* enable IDE0 + fast timing */
477	devpciR3SetWord(pPciDev, 0x42, 0x8011); /* enable IDE1 + fast timing */
478	goto default_map;
479	}
480	else
481	{
482	/* IDE: we map it as in ISA mode */
483	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0x1f0);
484	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 1, 0x3f4);
485	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 2, 0x170);
486	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 3, 0x374);
487	devpciR3SetWord(pPciDev, PCI_COMMAND,
488	devpciR3GetWord(pPciDev, PCI_COMMAND)
489	\| PCI_COMMAND_IOACCESS);
490	}
491	break;
492	case 0x0300:
493	{
494	if (vendor_id != 0x80ee)
495	goto default_map;
496	/* VGA: map frame buffer to default Bochs VBE address */
497	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0xe0000000);
498	/*
499	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
500	* only the framebuffer (i.e., a memory region) is explicitly registered via
501	* devpciR3BiosInitSetRegionAddress, so don't forget to enable I/O decoding.
502	*/
503	devpciR3SetWord(pPciDev, PCI_COMMAND,
504	devpciR3GetWord(pPciDev, PCI_COMMAND)
505	\| PCI_COMMAND_IOACCESS \| PCI_COMMAND_MEMACCESS);
506	break;
507	}
508	case 0x0800:
509	/* PIC */
510	vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
511	device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
512	if (vendor_id == 0x1014)
513	{
514	/* IBM */
515	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
516	{
517	/* MPIC & MPIC2 */
518	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0x80800000 + 0x00040000);
519	devpciR3SetWord(pPciDev, PCI_COMMAND,
520	devpciR3GetWord(pPciDev, PCI_COMMAND)
521	\| PCI_COMMAND_MEMACCESS);
522	}
523	}
524	break;
525	case 0xff00:
526	if ( (vendor_id == 0x0106b)
527	&& (device_id == 0x0017 \|\| device_id == 0x0022))
528	{
529	/* macio bridge */
530	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0x80800000);
531	devpciR3SetWord(pPciDev, PCI_COMMAND,
532	devpciR3GetWord(pPciDev, PCI_COMMAND)
533	\| PCI_COMMAND_MEMACCESS);
534	}
535	break;
536	case 0x0604:
537	{
538	/* Init PCI-to-PCI bridge. */
539	devpciR3SetByte(pPciDev, VBOX_PCI_PRIMARY_BUS, pBus->iBus);
540
541	AssertMsg(pGlobals->uPciBiosBus < 255, ("Too many bridges on the bus\n"));
542	pGlobals->uPciBiosBus++;
543	devpciR3SetByte(pPciDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uPciBiosBus);
544	devpciR3SetByte(pPciDev, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
545
546	/* Add position of this bridge into the array. */
547	paBridgePositions[cBridgeDepth+1] = (pPciDev->uDevFn >> 3);
548
549	/*
550	* The I/O range for the bridge must be aligned to a 4KB boundary.
551	* This does not change anything really as the access to the device is not going
552	* through the bridge but we want to be compliant to the spec.
553	*/
554	if ((pGlobals->uPciBiosIo % _4K) != 0)
555	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
556	LogFunc(("Aligned I/O start address. New address %#x\n", pGlobals->uPciBiosIo));
557	devpciR3SetByte(pPciDev, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0);
558
559	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
560	if ((pGlobals->uPciBiosMmio % _1M) != 0)
561	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
562	LogFunc(("Aligned MMIO start address. New address %#x\n", pGlobals->uPciBiosMmio));
563	devpciR3SetWord(pPciDev, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
564
565	/* Save values to compare later to. */
566	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
567	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
568
569	/* Init devices behind the bridge and possibly other bridges as well. */
570	PDEVPCIBUS pChildBus = PDMINS_2_DATA(pPciDev->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
571	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pChildBus->apDevices); uDevFn++)
572	{
573	PPDMPCIDEV pChildPciDev = pChildBus->apDevices[uDevFn];
574	if (pChildPciDev)
575	pci_bios_init_device(pGlobals, pChildBus, pChildPciDev, cBridgeDepth + 1, paBridgePositions);
576	}
577
578	/* The number of bridges behind the this one is now available. */
579	devpciR3SetByte(pPciDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
580
581	/*
582	* Set I/O limit register. If there is no device with I/O space behind the bridge
583	* we set a lower value than in the base register.
584	* The result with a real bridge is that no I/O transactions are passed to the secondary
585	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
586	*/
587	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % _4K) != 0))
588	{
589	/* The upper boundary must be one byte less than a 4KB boundary. */
590	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
591	}
592	devpciR3SetByte(pPciDev, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1);
593
594	/* Same with the MMIO limit register but with 1MB boundary here. */
595	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % _1M) != 0))
596	{
597	/* The upper boundary must be one byte less than a 1MB boundary. */
598	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
599	}
600	devpciR3SetWord(pPciDev, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1);
601
602	/*
603	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
604	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
605	* the base register than in the limit register.
606	*/
607	devpciR3SetWord(pPciDev, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
608	devpciR3SetWord(pPciDev, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
609	devpciR3SetDWord(pPciDev, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
610	devpciR3SetDWord(pPciDev, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
611	break;
612	}
613	default:
614	default_map:
615	{
616	/* default memory mappings */
617	bool fActiveMemRegion = false;
618	bool fActiveIORegion = false;
619	/*
620	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
621	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
622	*/
623	for (unsigned i = 0; i < (PCI_NUM_REGIONS-1); i++)
624	{
625	uint32_t u32Size;
626	uint8_t u8RessourceType;
627	uint32_t u32Address = 0x10 + i * 4;
628
629	/* Calculate size. */
630	u8RessourceType = devpciR3GetByte(pPciDev, u32Address);
631	devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0xffffffff));
632	u32Size = devpciR3GetDWord(pPciDev, u32Address);
633	bool fIsPio = ((u8RessourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
634	/* Clear resource information depending on resource type. */
635	if (fIsPio) /* I/O */
636	u32Size &= ~(0x01);
637	else /* MMIO */
638	u32Size &= ~(0x0f);
639
640	/*
641	* Invert all bits and add 1 to get size of the region.
642	* (From PCI implementation note)
643	*/
644	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
645	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
646	else
647	u32Size = (~u32Size) + 1;
648
649	Log2Func(("Size of region %u for device %d on bus %d is %u\n", i, pPciDev->uDevFn, pBus->iBus, u32Size));
650
651	if (u32Size)
652	{
653	if (fIsPio)
654	paddr = &pGlobals->uPciBiosIo;
655	else
656	paddr = &pGlobals->uPciBiosMmio;
657	uint32_t uNew = *paddr;
658	uNew = (uNew + u32Size - 1) & ~(u32Size - 1);
659	if (fIsPio)
660	uNew &= UINT32_C(0xffff);
661	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
662	if (!uNew \|\| (uNew <= UINT32_C(0xffffffff) && uNew + u32Size - 1 >= UINT32_C(0xfec00000)))
663	{
664	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
665	i, pBus->iBus, pPciDev->uDevFn >> 3, pPciDev->uDevFn & 7, vendor_id, device_id)); /** @todo make this a VM start failure later. */
666	/* Undo the mapping mess caused by the size probing. */
667	devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0));
668	}
669	else
670	{
671	LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), i, uNew));
672	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, i, uNew);
673	if (fIsPio)
674	fActiveIORegion = true;
675	else
676	fActiveMemRegion = true;
677	*paddr = uNew + u32Size;
678	Log2Func(("New address is %#x\n", *paddr));
679	}
680	}
681	}
682
683	/* Update the command word appropriately. */
684	devpciR3SetWord(pPciDev, PCI_COMMAND,
685	devpciR3GetWord(pPciDev, PCI_COMMAND)
686	\| (fActiveMemRegion ? PCI_COMMAND_MEMACCESS : 0)
687	\| (fActiveIORegion ? PCI_COMMAND_IOACCESS : 0));
688
689	break;
690	}
691	}
692
693	/* map the interrupt */
694	pin = devpciR3GetByte(pPciDev, PCI_INTERRUPT_PIN);
695	if (pin != 0)
696	{
697	uint8_t uBridgeDevFn = pPciDev->uDevFn;
698	pin--;
699
700	/* We need to go up to the host bus to see which irq this device will assert there. */
701	while (cBridgeDepth != 0)
702	{
703	/* Get the pin the device would assert on the bridge. */
704	pin = ((uBridgeDevFn >> 3) + pin) & 3;
705	uBridgeDevFn = paBridgePositions[cBridgeDepth];
706	cBridgeDepth--;
707	}
708
709	pin = pci_slot_get_pirq(pPciDev->uDevFn, pin);
710	pic_irq = pci_irqs[pin];
711	devpciR3SetByte(pPciDev, PCI_INTERRUPT_LINE, pic_irq);
712	}
713	}
714	}
715
716	/**
717	* Worker for Fake PCI BIOS config, triggered by magic port access by BIOS.
718	*
719	* @returns VBox status code.
720	*
721	* @param pDevIns i440FX device instance.
722	*/
723	static int pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
724	{
725	uint8_t elcr[2] = {0, 0};
726	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
727	PVM pVM = PDMDevHlpGetVM(pDevIns); Assert(pVM);
728	PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns); Assert(pVM);
729	uint32_t const cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
730	uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
731	RT_NOREF(cbBelow4GB, cbAbove4GB);
732
733	LogRel(("PCI: Setting up resources and interrupts\n"));
734
735	/*
736	* Set the start addresses.
737	*/
738	pGlobals->uPciBiosBus = 0;
739	pGlobals->uPciBiosIo = 0xd000;
740	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
741
742	/*
743	* Activate IRQ mappings.
744	*/
745	PPDMPCIDEV pPIIX3 = &pGlobals->Piix3.PIIX3State.dev;
746	for (unsigned i = 0; i < 4; i++)
747	{
748	uint8_t irq = pci_irqs[i];
749	/* Set to trigger level. */
750	elcr[irq >> 3] \|= (1 << (irq & 7));
751	/* Activate irq remapping in PIIX3. */
752	devpciR3SetByte(pPIIX3, 0x60 + i, irq);
753	}
754
755	/* Tell to the PIC. */
756	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d0, elcr[0], sizeof(uint8_t));
757	if (rcStrict == VINF_SUCCESS)
758	rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d1, elcr[1], sizeof(uint8_t));
759	if (rcStrict != VINF_SUCCESS)
760	{
761	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
762	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
763	}
764
765	/*
766	* Init the devices.
767	*/
768	PDEVPCIBUS pBus = &pGlobals->PciBus;
769	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
770	{
771	PPDMPCIDEV pPciDev = pBus->apDevices[uDevFn];
772	uint8_t aBridgePositions[256];
773
774	if (pPciDev)
775	{
776	memset(aBridgePositions, 0, sizeof(aBridgePositions));
777	Log2(("PCI: Initializing device %d (%#x)\n",
778	uDevFn, 0x80000000 \| (uDevFn << 8)));
779	pci_bios_init_device(pGlobals, pBus, pPciDev, 0, aBridgePositions);
780	}
781	}
782
783	return VINF_SUCCESS;
784	}
785
786	#endif /* IN_RING3 */
787
788
789	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
790
791	/**
792	* @callback_method_impl{FNIOMIOPORTOUT, PCI address}
793	*/
794	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
795	{
796	LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
797	RT_NOREF2(Port, pvUser);
798	if (cb == 4)
799	{
800	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
801	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
802	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
803	PCI_UNLOCK(pDevIns);
804	}
805	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
806	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
807	return VINF_SUCCESS;
808	}
809
810
811	/**
812	* @callback_method_impl{FNIOMIOPORTIN, PCI address}
813	*/
814	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
815	{
816	RT_NOREF2(Port, pvUser);
817	if (cb == 4)
818	{
819	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
820	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
821	*pu32 = pThis->uConfigReg;
822	PCI_UNLOCK(pDevIns);
823	LogFunc(("Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
824	return VINF_SUCCESS;
825	}
826	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
827	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
828	LogFunc(("Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
829	return VERR_IOM_IOPORT_UNUSED;
830	}
831
832
833	/**
834	* @callback_method_impl{FNIOMIOPORTOUT, PCI data}
835	*/
836	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
837	{
838	LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
839	NOREF(pvUser);
840	int rc = VINF_SUCCESS;
841	if (!(Port % cb))
842	{
843	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
844	rc = pci_data_write(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), Port, u32, cb);
845	PCI_UNLOCK(pDevIns);
846	}
847	else
848	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
849	return rc;
850	}
851
852
853	/**
854	* @callback_method_impl{FNIOMIOPORTIN, PCI data}
855	*/
856	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
857	{
858	NOREF(pvUser);
859	if (!(Port % cb))
860	{
861	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
862	int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), Port, cb, pu32);
863	PCI_UNLOCK(pDevIns);
864	LogFunc(("Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
865	return rc;
866	}
867	AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
868	return VERR_IOM_IOPORT_UNUSED;
869	}
870
871	#ifdef IN_RING3
872
873	/**
874	* @callback_method_impl{FNIOMIOPORTOUT, PCI data}
875	*/
876	DECLCALLBACK(int) pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
877	{
878	RT_NOREF2(pvUser, Port);
879	LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
880	if (cb == 4)
881	{
882	if (u32 == UINT32_C(19200509)) // Richard Adams
883	{
884	int rc = pciR3FakePCIBIOS(pDevIns);
885	AssertRC(rc);
886	}
887	}
888
889	return VINF_SUCCESS;
890	}
891
892	/**
893	* @callback_method_impl{FNIOMIOPORTIN, PCI data}
894	*/
895	DECLCALLBACK(int) pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
896	{
897	RT_NOREF5(pDevIns, pvUser, Port, pu32, cb);
898	LogFunc(("Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
899	return VERR_IOM_IOPORT_UNUSED;
900	}
901
902
903	/*
904	* Include code we share with the other PCI bus implementation.
905	*
906	* Note! No #ifdefs, use instant data booleans/flags/whatever. Goal is to
907	* completely merge these files! File #1 contains code we write, where
908	* as a possible file #2 contains external code if there's any left.
909	*/
910	# include "DevPciMerge1.cpp.h"
911
912
913	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
914
915	/**
916	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
917	*
918	* @returns VBox status code.
919	* @param pBus The bus to save.
920	* @param pSSM The saved state handle.
921	*/
922	static int pciR3CommonSaveExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM)
923	{
924	/*
925	* Iterate thru all the devices.
926	*/
927	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
928	{
929	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
930	if (pDev)
931	{
932	SSMR3PutU32(pSSM, uDevFn);
933	SSMR3PutMem(pSSM, pDev->abConfig, sizeof(pDev->abConfig));
934
935	SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
936
937	/* Save the type an size of all the regions. */
938	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
939	{
940	SSMR3PutU8(pSSM, pDev->Int.s.aIORegions[iRegion].type);
941	SSMR3PutU64(pSSM, pDev->Int.s.aIORegions[iRegion].size);
942	}
943	}
944	}
945	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
946	}
947
948
949	/**
950	* @callback_method_impl{FNSSMDEVSAVEEXEC}
951	*/
952	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
953	{
954	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
955
956	/*
957	* Bus state data.
958	*/
959	SSMR3PutU32(pSSM, pThis->uConfigReg);
960	SSMR3PutBool(pSSM, pThis->fUseIoApic);
961
962	/*
963	* Save IRQ states.
964	*/
965	for (unsigned i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
966	SSMR3PutU32(pSSM, pThis->Piix3.auPciLegacyIrqLevels[i]);
967	for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
968	SSMR3PutU32(pSSM, pThis->auPciApicIrqLevels[i]);
969
970	SSMR3PutU32(pSSM, pThis->Piix3.iAcpiIrqLevel);
971	SSMR3PutS32(pSSM, pThis->Piix3.iAcpiIrq);
972
973	SSMR3PutU32(pSSM, UINT32_MAX); /* separator */
974
975	/*
976	* Join paths with pcibridgeR3SaveExec.
977	*/
978	return pciR3CommonSaveExec(&pThis->PciBus, pSSM);
979	}
980
981
982	/**
983	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
984	*
985	* @returns VBox status code.
986	* @param pBus The bus which data is being loaded.
987	* @param pSSM The saved state handle.
988	* @param uVersion The data version.
989	* @param uPass The pass.
990	*/
991	static DECLCALLBACK(int) pciR3CommonLoadExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
992	{
993	uint32_t u32;
994	int rc;
995
996	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
997
998	/*
999	* Iterate thru all the devices and write 0 to the COMMAND register so
1000	* that all the memory is unmapped before we start restoring the saved
1001	* mapping locations.
1002	*
1003	* The register value is restored afterwards so we can do proper
1004	* LogRels in devpciR3CommonRestoreConfig.
1005	*/
1006	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1007	{
1008	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1009	if (pDev)
1010	{
1011	uint16_t u16 = PCIDevGetCommand(pDev);
1012	pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, VBOX_PCI_COMMAND, 0, 2);
1013	PCIDevSetCommand(pDev, u16);
1014	Assert(PCIDevGetCommand(pDev) == u16);
1015	}
1016	}
1017
1018	/*
1019	* Iterate all the devices.
1020	*/
1021	for (uint32_t uDevFn = 0;; uDevFn++)
1022	{
1023	/* index / terminator */
1024	rc = SSMR3GetU32(pSSM, &u32);
1025	if (RT_FAILURE(rc))
1026	return rc;
1027	if (u32 == UINT32_MAX)
1028	break;
1029	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1030	\|\| u32 < uDevFn)
1031	{
1032	AssertMsgFailed(("u32=%#x uDevFn=%#x\n", u32, uDevFn));
1033	return rc;
1034	}
1035
1036	/* skip forward to the device checking that no new devices are present. */
1037	for (; uDevFn < u32; uDevFn++)
1038	{
1039	if (pBus->apDevices[uDevFn])
1040	{
1041	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", uDevFn, pBus->apDevices[uDevFn]->pszNameR3,
1042	PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn])));
1043	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1044	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1045	uDevFn, pBus->apDevices[uDevFn]->pszNameR3, PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn]));
1046	}
1047	}
1048
1049	/* get the data */
1050	PDMPCIDEV DevTmp;
1051	RT_ZERO(DevTmp);
1052	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1053	SSMR3GetMem(pSSM, DevTmp.abConfig, sizeof(DevTmp.abConfig));
1054	if (uVersion < VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1055	{
1056	int32_t i32Temp;
1057	/* Irq value not needed anymore. */
1058	rc = SSMR3GetS32(pSSM, &i32Temp);
1059	if (RT_FAILURE(rc))
1060	return rc;
1061	}
1062	else
1063	{
1064	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1065	if (RT_FAILURE(rc))
1066	return rc;
1067	}
1068
1069	/* Load the region types and sizes. */
1070	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES)
1071	{
1072	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
1073	{
1074	SSMR3GetU8(pSSM, &DevTmp.Int.s.aIORegions[iRegion].type);
1075	rc = SSMR3GetU64(pSSM, &DevTmp.Int.s.aIORegions[iRegion].size);
1076	AssertLogRelRCReturn(rc, rc);
1077	}
1078	}
1079
1080	/* check that it's still around. */
1081	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1082	if (!pDev)
1083	{
1084	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", uDevFn,
1085	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1086	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1087	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1088	uDevFn, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1089	continue;
1090	}
1091
1092	/* match the vendor id assuming that this will never be changed. */
1093	if ( DevTmp.abConfig[0] != pDev->abConfig[0]
1094	\|\| DevTmp.abConfig[1] != pDev->abConfig[1])
1095	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
1096	N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1097	uDevFn, pDev->pszNameR3, DevTmp.abConfig, pDev->abConfig);
1098
1099	/* commit the loaded device config. */
1100	rc = devpciR3CommonRestoreRegions(pSSM, pDev, DevTmp.Int.s.aIORegions,
1101	uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES);
1102	if (RT_FAILURE(rc))
1103	break;
1104	devpciR3CommonRestoreConfig(pDev, &DevTmp.abConfig[0]);
1105
1106	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1107	}
1108
1109	return VINF_SUCCESS;
1110	}
1111
1112
1113	/**
1114	* @callback_method_impl{FNSSMDEVLOADEXEC}
1115	*/
1116	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1117	{
1118	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1119	PDEVPCIBUS pBus = &pThis->PciBus;
1120	uint32_t u32;
1121	int rc;
1122
1123	/*
1124	* Check the version.
1125	*/
1126	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1127	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1128	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1129
1130	/*
1131	* Bus state data.
1132	*/
1133	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1134	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC)
1135	SSMR3GetBool(pSSM, &pThis->fUseIoApic);
1136
1137	/* Load IRQ states. */
1138	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1139	{
1140	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
1141	SSMR3GetU32(pSSM, (uint32_t *)&pThis->Piix3.auPciLegacyIrqLevels[i]);
1142	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
1143	SSMR3GetU32(pSSM, (uint32_t *)&pThis->auPciApicIrqLevels[i]);
1144
1145	SSMR3GetU32(pSSM, &pThis->Piix3.iAcpiIrqLevel);
1146	SSMR3GetS32(pSSM, &pThis->Piix3.iAcpiIrq);
1147	}
1148
1149	/* separator */
1150	rc = SSMR3GetU32(pSSM, &u32);
1151	if (RT_FAILURE(rc))
1152	return rc;
1153	if (u32 != UINT32_MAX)
1154	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1155
1156	/*
1157	* The devices.
1158	*/
1159	return pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1160	}
1161
1162
1163	/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
1164
1165
1166	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
1167
1168	/**
1169	* @callback_method_impl{FNDBGFHANDLERDEV}
1170	*/
1171	static DECLCALLBACK(void) pciR3IrqRouteInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1172	{
1173	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1174	PPDMPCIDEV pPIIX3 = &pGlobals->Piix3.PIIX3State.dev;
1175	NOREF(pszArgs);
1176
1177	uint16_t router = pPIIX3->uDevFn;
1178	pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1179	router >> 8, (router >> 3) & 0x1f, router & 0x7);
1180
1181	for (int i = 0; i < 4; ++i)
1182	{
1183	uint8_t irq_map = devpciR3GetByte(pPIIX3, 0x60 + i);
1184	if (irq_map & 0x80)
1185	pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1186	else
1187	pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1188	}
1189	}
1190
1191
1192	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1193
1194
1195	/**
1196	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1197	*/
1198	static DECLCALLBACK(int) pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1199	{
1200	RT_NOREF1(iInstance);
1201	Assert(iInstance == 0);
1202	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1203
1204	/*
1205	* Validate and read configuration.
1206	*/
1207	if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
1208	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1209
1210	/* query whether we got an IOAPIC */
1211	bool fUseIoApic;
1212	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
1213	if (RT_FAILURE(rc))
1214	return PDMDEV_SET_ERROR(pDevIns, rc,
1215	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
1216
1217	/* check if RC code is enabled. */
1218	bool fGCEnabled;
1219	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1220	if (RT_FAILURE(rc))
1221	return PDMDEV_SET_ERROR(pDevIns, rc,
1222	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
1223
1224	/* check if R0 code is enabled. */
1225	bool fR0Enabled;
1226	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1227	if (RT_FAILURE(rc))
1228	return PDMDEV_SET_ERROR(pDevIns, rc,
1229	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
1230	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
1231
1232	/*
1233	* Init data and register the PCI bus.
1234	*/
1235	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1236	pGlobals->uPciBiosIo = 0xc000;
1237	pGlobals->uPciBiosMmio = 0xf0000000;
1238	memset((void *)&pGlobals->Piix3.auPciLegacyIrqLevels, 0, sizeof(pGlobals->Piix3.auPciLegacyIrqLevels));
1239	pGlobals->fUseIoApic = fUseIoApic;
1240	memset((void *)&pGlobals->auPciApicIrqLevels, 0, sizeof(pGlobals->auPciApicIrqLevels));
1241
1242	pGlobals->pDevInsR3 = pDevIns;
1243	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1244	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1245
1246	pGlobals->PciBus.fTypePiix3 = true;
1247	pGlobals->PciBus.fTypeIch9 = false;
1248	pGlobals->PciBus.fPureBridge = false;
1249	pGlobals->PciBus.pDevInsR3 = pDevIns;
1250	pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1251	pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1252	pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns,
1253	sizeof(PPDMPCIDEV)
1254	* RT_ELEMENTS(pGlobals->PciBus.apDevices));
1255	AssertLogRelReturn(pGlobals->PciBus.papBridgesR3, VERR_NO_MEMORY);
1256
1257
1258	PDMPCIBUSREG PciBusReg;
1259	PDEVPCIBUS pBus = &pGlobals->PciBus;
1260	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
1261	PciBusReg.pfnRegisterR3 = pciR3MergedRegister;
1262	PciBusReg.pfnRegisterMsiR3 = NULL;
1263	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1264	PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
1265	PciBusReg.pfnSetIrqR3 = pciSetIrq;
1266	PciBusReg.pszSetIrqRC = fGCEnabled ? "pciSetIrq" : NULL;
1267	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
1268	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
1269	if (RT_FAILURE(rc))
1270	return PDMDEV_SET_ERROR(pDevIns, rc,
1271	N_("Failed to register ourselves as a PCI Bus"));
1272	Assert(pBus->iBus == 0);
1273	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1274	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1275	N_("PCI helper version mismatch; got %#x expected %#x"),
1276	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1277
1278	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1279	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
1280
1281	/* Disable default device locking. */
1282	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1283	AssertRCReturn(rc, rc);
1284
1285	/*
1286	* Fill in PCI configs and add them to the bus.
1287	*/
1288	/* i440FX */
1289	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
1290	PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
1291	PCIDevSetRevisionId(&pBus->PciDev, 0x02);
1292	PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
1293	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
1294	PCIDevSetHeaderType(&pBus->PciDev, 0x00);
1295	rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->PciDev, PDMPCIDEVREG_CFG_PRIMARY, 0 /fFlags/,
1296	0 /uPciDevNo/, 0 /uPciFunNo/, "i440FX");
1297	AssertLogRelRCReturn(rc, rc);
1298
1299	/* PIIX3 */
1300	PCIDevSetVendorId( &pGlobals->Piix3.PIIX3State.dev, 0x8086); /* Intel */
1301	PCIDevSetDeviceId( &pGlobals->Piix3.PIIX3State.dev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
1302	PCIDevSetClassSub( &pGlobals->Piix3.PIIX3State.dev, 0x01); /* PCI_ISA */
1303	PCIDevSetClassBase( &pGlobals->Piix3.PIIX3State.dev, 0x06); /* PCI_bridge */
1304	PCIDevSetHeaderType(&pGlobals->Piix3.PIIX3State.dev, 0x80); /* PCI_multifunction, generic */
1305	rc = PDMDevHlpPCIRegisterEx(pDevIns, &pGlobals->Piix3.PIIX3State.dev, PDMPCIDEVREG_CFG_NEXT, 0 /fFlags/,
1306	1 /uPciDevNo/, 0 /uPciFunNo/, "PIIX3");
1307	AssertLogRelRCReturn(rc, rc);
1308	pciR3Piix3Reset(&pGlobals->Piix3.PIIX3State);
1309
1310	pBus->iDevSearch = 16;
1311
1312	/*
1313	* Register I/O ports and save state.
1314	*/
1315	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
1316	if (RT_FAILURE(rc))
1317	return rc;
1318	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
1319	if (RT_FAILURE(rc))
1320	return rc;
1321	if (fGCEnabled)
1322	{
1323	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
1324	if (RT_FAILURE(rc))
1325	return rc;
1326	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
1327	if (RT_FAILURE(rc))
1328	return rc;
1329	}
1330	if (fR0Enabled)
1331	{
1332	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
1333	if (RT_FAILURE(rc))
1334	return rc;
1335	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
1336	if (RT_FAILURE(rc))
1337	return rc;
1338	}
1339
1340	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0410, 1, NULL, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead, NULL, NULL, "i440FX (Fake PCI BIOS trigger)")
1341	;
1342	if (RT_FAILURE(rc))
1343	return rc;
1344
1345
1346	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
1347	NULL, NULL, NULL,
1348	NULL, pciR3SaveExec, NULL,
1349	NULL, pciR3LoadExec, NULL);
1350	if (RT_FAILURE(rc))
1351	return rc;
1352
1353	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
1354	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
1355	devpciR3InfoPci);
1356	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", devpciR3InfoPciIrq);
1357	PDMDevHlpDBGFInfoRegister(pDevIns, "irqroute", "Display PCI IRQ routing. (no arguments)", pciR3IrqRouteInfo);
1358
1359	return VINF_SUCCESS;
1360	}
1361
1362
1363	/**
1364	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1365	*/
1366	static DECLCALLBACK(int) pciR3Destruct(PPDMDEVINS pDevIns)
1367	{
1368	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1369	if (pGlobals->PciBus.papBridgesR3)
1370	{
1371	PDMDevHlpMMHeapFree(pDevIns, pGlobals->PciBus.papBridgesR3);
1372	pGlobals->PciBus.papBridgesR3 = NULL;
1373	}
1374	return VINF_SUCCESS;
1375	}
1376
1377
1378	/**
1379	* @interface_method_impl{PDMDEVREG,pfnReset}
1380	*/
1381	static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
1382	{
1383	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1384	PDEVPCIBUS pBus = &pGlobals->PciBus;
1385
1386	/* PCI-specific reset for each device. */
1387	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1388	{
1389	if (pBus->apDevices[uDevFn])
1390	devpciR3ResetDevice(pBus->apDevices[uDevFn]);
1391	}
1392
1393	pciR3Piix3Reset(&pGlobals->Piix3.PIIX3State);
1394	}
1395
1396
1397	/**
1398	* The device registration structure.
1399	*/
1400	const PDMDEVREG g_DevicePCI =
1401	{
1402	/* u32Version */
1403	PDM_DEVREG_VERSION,
1404	/* szName */
1405	"pci",
1406	/* szRCMod */
1407	"VBoxDDRC.rc",
1408	/* szR0Mod */
1409	"VBoxDDR0.r0",
1410	/* pszDescription */
1411	"i440FX PCI bridge and PIIX3 ISA bridge.",
1412	/* fFlags */
1413	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1414	/* fClass */
1415	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
1416	/* cMaxInstances */
1417	1,
1418	/* cbInstance */
1419	sizeof(DEVPCIROOT),
1420	/* pfnConstruct */
1421	pciR3Construct,
1422	/* pfnDestruct */
1423	pciR3Destruct,
1424	/* pfnRelocate */
1425	devpciR3RootRelocate,
1426	/* pfnMemSetup */
1427	NULL,
1428	/* pfnPowerOn */
1429	NULL,
1430	/* pfnReset */
1431	pciR3Reset,
1432	/* pfnSuspend */
1433	NULL,
1434	/* pfnResume */
1435	NULL,
1436	/* pfnAttach */
1437	NULL,
1438	/* pfnDetach */
1439	NULL,
1440	/* pfnQueryInterface */
1441	NULL,
1442	/* pfnInitComplete */
1443	NULL,
1444	/* pfnPowerOff */
1445	NULL,
1446	/* pfnSoftReset */
1447	NULL,
1448	/* u32VersionEnd */
1449	PDM_DEVREG_VERSION
1450
1451	};
1452	#endif /* IN_RING3 */
1453
1454
1455
1456	/* -=-=-=-=-=- The PCI bridge specific bits -=-=-=-=-=- */
1457
1458	/**
1459	* @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
1460	*/
1461	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
1462	{
1463	/*
1464	* The PCI-to-PCI bridge specification defines how the interrupt pins
1465	* are routed from the secondary to the primary bus (see chapter 9).
1466	* iIrq gives the interrupt pin the pci device asserted.
1467	* We change iIrq here according to the spec and call the SetIrq function
1468	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
1469	*/
1470	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1471	PPDMPCIDEV pPciDevBus = pPciDev;
1472	int iIrqPinBridge = iIrq;
1473	uint8_t uDevFnBridge = 0;
1474
1475	/* Walk the chain until we reach the host bus. */
1476	do
1477	{
1478	uDevFnBridge = pBus->PciDev.uDevFn;
1479	iIrqPinBridge = ((pPciDevBus->uDevFn >> 3) + iIrqPinBridge) & 3;
1480
1481	/* Get the parent. */
1482	pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
1483	pPciDevBus = &pBus->PciDev;
1484	} while (pBus->iBus != 0);
1485
1486	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
1487	pciSetIrqInternal(DEVPCIBUS_2_DEVPCIROOT(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
1488	}
1489
1490	#ifdef IN_RING3
1491
1492	/**
1493	* @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
1494	*/
1495	static DECLCALLBACK(void) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1496	{
1497	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1498
1499	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1500
1501	/* If the current bus is not the target bus search for the bus which contains the device. */
1502	if (iBus != pBus->PciDev.abConfig[VBOX_PCI_SECONDARY_BUS])
1503	{
1504	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1505	if (pBridgeDevice)
1506	{
1507	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1508	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, u32Address, u32Value, cb);
1509	}
1510	}
1511	else
1512	{
1513	/* This is the target bus, pass the write to the device. */
1514	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1515	if (pPciDev)
1516	{
1517	LogFunc(("%s: addr=%02x val=%08x len=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
1518	/** @todo return rc */
1519	pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, u32Value, cb);
1520	}
1521	}
1522	}
1523
1524
1525	/**
1526	* @callback_method_impl{FNPCIBRIDGECONFIGREAD}
1527	*/
1528	static DECLCALLBACK(uint32_t) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1529	{
1530	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1531	uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
1532
1533	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1534
1535	/* If the current bus is not the target bus search for the bus which contains the device. */
1536	if (iBus != pBus->PciDev.abConfig[VBOX_PCI_SECONDARY_BUS])
1537	{
1538	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1539	if (pBridgeDevice)
1540	{
1541	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1542	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, u32Address, cb);
1543	}
1544	}
1545	else
1546	{
1547	/* This is the target bus, pass the read to the device. */
1548	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1549	if (pPciDev)
1550	{
1551	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb);
1552	LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
1553	}
1554	}
1555
1556	return u32Value;
1557	}
1558
1559
1560	/**
1561	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1562	*/
1563	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1564	{
1565	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1566	return pciR3CommonSaveExec(pThis, pSSM);
1567	}
1568
1569
1570	/**
1571	* @callback_method_impl{FNSSMDEVLOADEXEC}
1572	*/
1573	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1574	{
1575	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1576	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1577	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1578	return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1579	}
1580
1581
1582	/**
1583	* @interface_method_impl{PDMDEVREG,pfnReset}
1584	*/
1585	static DECLCALLBACK(void) pcibridgeR3Reset(PPDMDEVINS pDevIns)
1586	{
1587	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1588
1589	/* Reset config space to default values. */
1590	pBus->PciDev.abConfig[VBOX_PCI_PRIMARY_BUS] = 0;
1591	pBus->PciDev.abConfig[VBOX_PCI_SECONDARY_BUS] = 0;
1592	pBus->PciDev.abConfig[VBOX_PCI_SUBORDINATE_BUS] = 0;
1593	}
1594
1595
1596	/**
1597	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1598	*/
1599	static DECLCALLBACK(int) pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1600	{
1601	RT_NOREF(iInstance);
1602	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1603
1604	/*
1605	* Validate and read configuration.
1606	*/
1607	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
1608	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1609
1610	/* check if RC code is enabled. */
1611	bool fGCEnabled;
1612	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1613	if (RT_FAILURE(rc))
1614	return PDMDEV_SET_ERROR(pDevIns, rc,
1615	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
1616
1617	/* check if R0 code is enabled. */
1618	bool fR0Enabled;
1619	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1620	if (RT_FAILURE(rc))
1621	return PDMDEV_SET_ERROR(pDevIns, rc,
1622	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
1623	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
1624
1625	/*
1626	* Init data and register the PCI bus.
1627	*/
1628	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1629	pBus->fTypePiix3 = true;
1630	pBus->fTypeIch9 = false;
1631	pBus->fPureBridge = true;
1632	pBus->pDevInsR3 = pDevIns;
1633	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1634	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1635	pBus->papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pBus->apDevices));
1636	AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
1637
1638	PDMPCIBUSREG PciBusReg;
1639	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
1640	PciBusReg.pfnRegisterR3 = pcibridgeR3MergedRegisterDevice;
1641	PciBusReg.pfnRegisterMsiR3 = NULL;
1642	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1643	PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
1644	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
1645	PciBusReg.pszSetIrqRC = fGCEnabled ? "pcibridgeSetIrq" : NULL;
1646	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pcibridgeSetIrq" : NULL;
1647	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
1648	if (RT_FAILURE(rc))
1649	return PDMDEV_SET_ERROR(pDevIns, rc,
1650	N_("Failed to register ourselves as a PCI Bus"));
1651	Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
1652	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1653	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1654	N_("PCI helper version mismatch; got %#x expected %#x"),
1655	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1656
1657	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1658	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
1659
1660	/*
1661	* Fill in PCI configs and add them to the bus.
1662	*/
1663	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
1664	PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
1665	PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
1666	PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
1667	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
1668	PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
1669	PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
1670	PCIDevSetCommand( &pBus->PciDev, 0x0000);
1671	PCIDevSetStatus( &pBus->PciDev, 0x0020); /* 66MHz Capable. */
1672	PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
1673
1674	/*
1675	* This device does not generate interrupts. Interrupt delivery from
1676	* devices attached to the bus is unaffected.
1677	*/
1678	PCIDevSetInterruptPin(&pBus->PciDev, 0x00);
1679
1680	/*
1681	* Register this PCI bridge. The called function will take care on which bus we will get registered.
1682	*/
1683	rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->PciDev, PDMPCIDEVREG_CFG_PRIMARY, PDMPCIDEVREG_F_PCI_BRIDGE,
1684	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "pcibridge");
1685	if (RT_FAILURE(rc))
1686	return rc;
1687	pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
1688	pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
1689
1690	pBus->iDevSearch = 0;
1691
1692	/*
1693	* Register SSM handlers. We use the same saved state version as for the host bridge
1694	* to make changes easier.
1695	*/
1696	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
1697	NULL, NULL, NULL,
1698	NULL, pcibridgeR3SaveExec, NULL,
1699	NULL, pcibridgeR3LoadExec, NULL);
1700	if (RT_FAILURE(rc))
1701	return rc;
1702
1703	return VINF_SUCCESS;
1704	}
1705
1706
1707	/**
1708	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1709	*/
1710	static DECLCALLBACK(int) pcibridgeR3Destruct(PPDMDEVINS pDevIns)
1711	{
1712	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1713	if (pBus->papBridgesR3)
1714	{
1715	PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
1716	pBus->papBridgesR3 = NULL;
1717	}
1718	return VINF_SUCCESS;
1719	}
1720
1721
1722	/**
1723	* The device registration structure
1724	* for the PCI-to-PCI bridge.
1725	*/
1726	const PDMDEVREG g_DevicePCIBridge =
1727	{
1728	/* u32Version */
1729	PDM_DEVREG_VERSION,
1730	/* szName */
1731	"pcibridge",
1732	/* szRCMod */
1733	"VBoxDDRC.rc",
1734	/* szR0Mod */
1735	"VBoxDDR0.r0",
1736	/* pszDescription */
1737	"82801 Mobile PCI to PCI bridge",
1738	/* fFlags */
1739	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1740	/* fClass */
1741	PDM_DEVREG_CLASS_BUS_PCI,
1742	/* cMaxInstances */
1743	~0U,
1744	/* cbInstance */
1745	sizeof(DEVPCIBUS),
1746	/* pfnConstruct */
1747	pcibridgeR3Construct,
1748	/* pfnDestruct */
1749	pcibridgeR3Destruct,
1750	/* pfnRelocate */
1751	devpciR3BusRelocate,
1752	/* pfnMemSetup */
1753	NULL,
1754	/* pfnPowerOn */
1755	NULL,
1756	/* pfnReset */
1757	pcibridgeR3Reset,
1758	/* pfnSuspend */
1759	NULL,
1760	/* pfnResume */
1761	NULL,
1762	/* pfnAttach */
1763	NULL,
1764	/* pfnDetach */
1765	NULL,
1766	/* pfnQueryInterface */
1767	NULL,
1768	/* pfnInitComplete */
1769	NULL,
1770	/* pfnPowerOff */
1771	NULL,
1772	/* pfnSoftReset */
1773	NULL,
1774	/* u32VersionEnd */
1775	PDM_DEVREG_VERSION
1776	};
1777
1778	#endif /* IN_RING3 */
1779

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 77807

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