DevPCI.cpp@ 73705

Last change on this file since 73705 was 72270, checked in by vboxsync, 6 years ago
DevPCI: LogRel nit.
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1	/* $Id: DevPCI.cpp 72270 2018-05-21 06:33:10Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*
5	* @remarks New code shall be added to DevPciIch9.cpp as that will become
6	* the common PCI bus code soon. Don't fix code in both DevPCI.cpp
7	* and DevPciIch9.cpp when it's possible to just make the latter
8	* version common. Common code uses the 'devpci' prefix, is
9	* prototyped in DevPciInternal.h, and is defined in DevPciIch9.cpp.
10	*/
11
12	/*
13	* Copyright (C) 2006-2017 Oracle Corporation
14	*
15	* This file is part of VirtualBox Open Source Edition (OSE), as
16	* available from http://www.virtualbox.org. This file is free software;
17	* you can redistribute it and/or modify it under the terms of the GNU
18	* General Public License (GPL) as published by the Free Software
19	* Foundation, in version 2 as it comes in the "COPYING" file of the
20	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
21	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* QEMU PCI bus manager
27	*
28	* Copyright (c) 2004 Fabrice Bellard
29	*
30	* Permission is hereby granted, free of charge, to any person obtaining a copy
31	* of this software and associated documentation files (the "Software"), to deal
32	* in the Software without restriction, including without limitation the rights
33	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
34	* copies of the Software, and to permit persons to whom the Software is
35	* furnished to do so, subject to the following conditions:
36	*
37	* The above copyright notice and this permission notice shall be included in
38	* all copies or substantial portions of the Software.
39	*
40	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
41	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
42	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
44	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
45	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
46	* THE SOFTWARE.
47	*/
48
49
50	/*********************************************************************************************************************************
51	* Header Files *
52	*********************************************************************************************************************************/
53	#define LOG_GROUP LOG_GROUP_DEV_PCI
54	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
55	#include <VBox/vmm/pdmpcidev.h>
56	#include <VBox/vmm/pdmdev.h>
57	#include <VBox/vmm/mm.h>
58	#include <iprt/asm.h>
59	#include <iprt/assert.h>
60	#include <iprt/string.h>
61
62	#include "PciInline.h"
63	#include "VBoxDD.h"
64	#include "DevPciInternal.h"
65
66
67	/*********************************************************************************************************************************
68	* Defined Constants And Macros *
69	*********************************************************************************************************************************/
70	/** Saved state version of the PCI bus device. */
71	#define VBOX_PCI_SAVED_STATE_VERSION VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES
72	/** Adds I/O region types and sizes for dealing changes in resource regions. */
73	#define VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES 4
74	/** Before region sizes, the first named one.
75	* Looking at the code though, we support even older version. */
76	#define VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES 3
77	/** Notes whether we use the I/O APIC. */
78	#define VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC 2
79
80
81	/*********************************************************************************************************************************
82	* Internal Functions *
83	*********************************************************************************************************************************/
84	RT_C_DECLS_BEGIN
85
86	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
87	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
88	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
89	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
90	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
91	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
92
93	#ifdef IN_RING3
94	DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus);
95	#endif
96
97	RT_C_DECLS_END
98
99	#define DEBUG_PCI
100
101	#define PCI_VENDOR_ID 0x00 /* 16 bits */
102	#define PCI_DEVICE_ID 0x02 /* 16 bits */
103	#define PCI_COMMAND 0x04 /* 16 bits */
104	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
105	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
106	#define PCI_CLASS_DEVICE 0x0a /* Device class */
107	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
108	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
109	#define PCI_MIN_GNT 0x3e /* 8 bits */
110	#define PCI_MAX_LAT 0x3f /* 8 bits */
111
112
113	static int pci_data_write(PDEVPCIROOT pGlobals, uint32_t addr, uint32_t val, int len)
114	{
115	uint8_t iBus, iDevice;
116	uint32_t config_addr;
117
118	LogFunc(("addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
119
120	if (!(pGlobals->uConfigReg & (1 << 31))) {
121	return VINF_SUCCESS;
122	}
123	if ((pGlobals->uConfigReg & 0x3) != 0) {
124	return VINF_SUCCESS;
125	}
126	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
127	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
128	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
129	RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
130	if (iBus != 0)
131	{
132	if (pGlobals->PciBus.cBridges)
133	{
134	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
135	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
136	if (pBridgeDevice)
137	{
138	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
139	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, config_addr, val, len);
140	}
141	#else
142	RT_NOREF2(val, len);
143	return VINF_IOM_R3_IOPORT_WRITE;
144	#endif
145	}
146	}
147	else
148	{
149	R3PTRTYPE(PDMPCIDEV *) pci_dev = pGlobals->PciBus.apDevices[iDevice];
150	if (pci_dev)
151	{
152	#ifdef IN_RING3
153	LogFunc(("%s: addr=%02x val=%08x len=%d\n", pci_dev->pszNameR3, config_addr, val, len));
154	return VBOXSTRICTRC_TODO(pci_dev->Int.s.pfnConfigWrite(pci_dev->Int.s.CTX_SUFF(pDevIns), pci_dev, config_addr, val, len));
155	#else
156	return VINF_IOM_R3_IOPORT_WRITE;
157	#endif
158	}
159	}
160	return VINF_SUCCESS;
161	}
162
163	static int pci_data_read(PDEVPCIROOT pGlobals, uint32_t addr, int len, uint32_t *pu32)
164	{
165	uint8_t iBus, iDevice;
166	uint32_t config_addr;
167
168	*pu32 = 0xffffffff;
169
170	if (!(pGlobals->uConfigReg & (1 << 31)))
171	return VINF_SUCCESS;
172	if ((pGlobals->uConfigReg & 0x3) != 0)
173	return VINF_SUCCESS;
174	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
175	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
176	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
177	RT_UNTRUSTED_VALIDATED_FENCE();
178	if (iBus != 0)
179	{
180	if (pGlobals->PciBus.cBridges)
181	{
182	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
183	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
184	if (pBridgeDevice)
185	{
186	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
187	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, config_addr, len);
188	}
189	#else
190	NOREF(len);
191	return VINF_IOM_R3_IOPORT_READ;
192	#endif
193	}
194	}
195	else
196	{
197	R3PTRTYPE(PDMPCIDEV *) pci_dev = pGlobals->PciBus.apDevices[iDevice];
198	if (pci_dev)
199	{
200	#ifdef IN_RING3
201	*pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev->Int.s.CTX_SUFF(pDevIns), pci_dev, config_addr, len);
202	LogFunc(("%s: addr=%02x val=%08x len=%d\n", pci_dev->pszNameR3, config_addr, *pu32, len));
203	#else
204	NOREF(len);
205	return VINF_IOM_R3_IOPORT_READ;
206	#endif
207	}
208	}
209
210	return VINF_SUCCESS;
211	}
212
213
214
215	/* return the global irq number corresponding to a given device irq
216	pin. We could also use the bus number to have a more precise
217	mapping.
218	This is the implementation note described in the PCI spec chapter 2.2.6 */
219	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
220	{
221	int slot_addend;
222	slot_addend = (uDevFn >> 3) - 1;
223	return (irq_num + slot_addend) & 3;
224	}
225
226	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
227	{
228	return (irq_num + (uDevFn >> 3)) & 7;
229	}
230
231	static inline int get_pci_irq_apic_level(PDEVPCIROOT pGlobals, int irq_num)
232	{
233	return (pGlobals->auPciApicIrqLevels[irq_num] != 0);
234	}
235
236	static void apic_set_irq(PDEVPCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, int iAcpiIrq, uint32_t uTagSrc)
237	{
238	/* This is only allowed to be called with a pointer to the host bus. */
239	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
240
241	if (iAcpiIrq == -1) {
242	int apic_irq, apic_level;
243	PDEVPCIROOT pGlobals = DEVPCIBUS_2_DEVPCIROOT(pBus);
244	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
245
246	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
247	ASMAtomicIncU32(&pGlobals->auPciApicIrqLevels[irq_num]);
248	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
249	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
250
251	apic_irq = irq_num + 0x10;
252	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
253	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
254	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
255	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
256
257	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
258	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
259	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
260	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
261	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
262	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
263	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
264	}
265	} else {
266	Log3Func(("%s: irq_num1=%d level=%d iAcpiIrq=%d\n",
267	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iAcpiIrq));
268	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iAcpiIrq, iLevel, uTagSrc);
269	}
270	}
271
272	DECLINLINE(int) get_pci_irq_level(PDEVPCIROOT pGlobals, int irq_num)
273	{
274	return (pGlobals->Piix3.auPciLegacyIrqLevels[irq_num] != 0);
275	}
276
277	/**
278	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
279	*
280	* @param pGlobals Device instance of the host PCI Bus.
281	* @param uDevFn The device number on the host bus which will raise the IRQ
282	* @param pPciDev The PCI device structure which raised the interrupt.
283	* @param iIrq IRQ number to set.
284	* @param iLevel IRQ level.
285	* @param uTagSrc The IRQ tag and source ID (for tracing).
286	* @remark uDevFn and pPciDev->uDevFn are not the same if the device is behind
287	* a bridge. In that case uDevFn will be the slot of the bridge which
288	* is needed to calculate the PIRQ value.
289	*/
290	static void pciSetIrqInternal(PDEVPCIROOT pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
291	{
292	PDEVPCIBUS pBus = &pGlobals->PciBus;
293	uint8_t *pbCfg = pGlobals->Piix3.PIIX3State.dev.abConfig;
294	const bool fIsAcpiDevice = pPciDev->abConfig[2] == 0x13 && pPciDev->abConfig[3] == 0x71;
295	/* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
296	* is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
297	* See the \_SB_.PCI0._PRT method in vbox.dsl.
298	*/
299	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
300	int pic_irq, pic_level;
301
302	/* Check if the state changed. */
303	if (pPciDev->Int.s.uIrqPinState != iLevel)
304	{
305	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
306
307	/* Send interrupt to I/O APIC only. */
308	if (fIsApicEnabled)
309	{
310	if (fIsAcpiDevice)
311	/*
312	* ACPI needs special treatment since SCI is hardwired and
313	* should not be affected by PCI IRQ routing tables at the
314	* same time SCI IRQ is shared in PCI sense hence this
315	* kludge (i.e. we fetch the hardwired value from ACPIs
316	* PCI device configuration space).
317	*/
318	apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->abConfig[PCI_INTERRUPT_LINE], uTagSrc);
319	else
320	apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
321	return;
322	}
323
324	if (fIsAcpiDevice)
325	{
326	/* As per above treat ACPI in a special way */
327	pic_irq = pPciDev->abConfig[PCI_INTERRUPT_LINE];
328	pGlobals->Piix3.iAcpiIrq = pic_irq;
329	pGlobals->Piix3.iAcpiIrqLevel = iLevel & PDM_IRQ_LEVEL_HIGH;
330	}
331	else
332	{
333	int irq_num;
334	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
335
336	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
337	ASMAtomicIncU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
338	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
339	ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
340
341	/* now we change the pic irq level according to the piix irq mappings */
342	pic_irq = pbCfg[0x60 + irq_num];
343	if (pic_irq >= 16)
344	{
345	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
346	{
347	ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
348	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
349	}
350
351	return;
352	}
353	}
354
355	/* the pic level is the logical OR of all the PCI irqs mapped to it */
356	pic_level = 0;
357	if (pic_irq == pbCfg[0x60])
358	pic_level \|= get_pci_irq_level(pGlobals, 0);
359	if (pic_irq == pbCfg[0x61])
360	pic_level \|= get_pci_irq_level(pGlobals, 1);
361	if (pic_irq == pbCfg[0x62])
362	pic_level \|= get_pci_irq_level(pGlobals, 2);
363	if (pic_irq == pbCfg[0x63])
364	pic_level \|= get_pci_irq_level(pGlobals, 3);
365	if (pic_irq == pGlobals->Piix3.iAcpiIrq)
366	pic_level \|= pGlobals->Piix3.iAcpiIrqLevel;
367
368	Log3Func(("%s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
369	R3STRING(pPciDev->pszNameR3), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
370	pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level, uTagSrc);
371
372	/** @todo optimize pci irq flip-flop some rainy day. */
373	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
374	pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
375	}
376	}
377
378
379	/**
380	* @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
381	*/
382	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
383	{
384	pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
385	}
386
387	#ifdef IN_RING3
388
389	/**
390	* Finds a bridge on the bus which contains the destination bus.
391	*
392	* @return Pointer to the device instance data of the bus or
393	* NULL if no bridge was found.
394	* @param pBus Pointer to the bus to search on.
395	* @param iBus Destination bus number.
396	*/
397	DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus)
398	{
399	/* Search for a fitting bridge. */
400	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
401	{
402	/*
403	* Examine secondary and subordinate bus number.
404	* If the target bus is in the range we pass the request on to the bridge.
405	*/
406	PPDMPCIDEV pBridgeTemp = pBus->papBridgesR3[iBridge];
407	AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
408	("Device is not a PCI bridge but on the list of PCI bridges\n"));
409
410	if ( iBus >= pBridgeTemp->abConfig[VBOX_PCI_SECONDARY_BUS]
411	&& iBus <= pBridgeTemp->abConfig[VBOX_PCI_SUBORDINATE_BUS])
412	return pBridgeTemp;
413	}
414
415	/* Nothing found. */
416	return NULL;
417	}
418
419	static void pciR3Piix3Reset(PIIX3ISABRIDGE *d)
420	{
421	uint8_t *pci_conf = d->dev.abConfig;
422
423	pci_conf[0x04] = 0x07; /* master, memory and I/O */
424	pci_conf[0x05] = 0x00;
425	pci_conf[0x06] = 0x00;
426	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
427	pci_conf[0x4c] = 0x4d;
428	pci_conf[0x4e] = 0x03;
429	pci_conf[0x4f] = 0x00;
430	pci_conf[0x60] = 0x80;
431	pci_conf[0x69] = 0x02;
432	pci_conf[0x70] = 0x80;
433	pci_conf[0x76] = 0x0c;
434	pci_conf[0x77] = 0x0c;
435	pci_conf[0x78] = 0x02;
436	pci_conf[0x79] = 0x00;
437	pci_conf[0x80] = 0x00;
438	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
439	pci_conf[0xa0] = 0x08;
440	pci_conf[0xa2] = 0x00;
441	pci_conf[0xa3] = 0x00;
442	pci_conf[0xa4] = 0x00;
443	pci_conf[0xa5] = 0x00;
444	pci_conf[0xa6] = 0x00;
445	pci_conf[0xa7] = 0x00;
446	pci_conf[0xa8] = 0x0f;
447	pci_conf[0xaa] = 0x00;
448	pci_conf[0xab] = 0x00;
449	pci_conf[0xac] = 0x00;
450	pci_conf[0xae] = 0x00;
451	}
452
453	/* host irqs corresponding to PCI irqs A-D */
454	static const uint8_t pci_irqs[4] = { 11, 10, 9, 11 }; /* bird: added const */
455
456	static void pci_bios_init_device(PDEVPCIROOT pGlobals, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
457	{
458	uint32_t *paddr;
459	int pin, pic_irq;
460	uint16_t devclass, vendor_id, device_id;
461
462	devclass = devpciR3GetWord(pPciDev, PCI_CLASS_DEVICE);
463	vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
464	device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
465
466	/* Check if device is present. */
467	if (vendor_id != 0xffff)
468	{
469	switch(devclass)
470	{
471	case 0x0101:
472	if ( (vendor_id == 0x8086)
473	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
474	{
475	/* PIIX3, PIIX4 or ICH6 IDE */
476	devpciR3SetWord(pPciDev, 0x40, 0x8000); /* enable IDE0 */
477	devpciR3SetWord(pPciDev, 0x42, 0x8000); /* enable IDE1 */
478	goto default_map;
479	}
480	else
481	{
482	/* IDE: we map it as in ISA mode */
483	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0x1f0);
484	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 1, 0x3f4);
485	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 2, 0x170);
486	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 3, 0x374);
487	devpciR3SetWord(pPciDev, PCI_COMMAND,
488	devpciR3GetWord(pPciDev, PCI_COMMAND)
489	\| PCI_COMMAND_IOACCESS);
490	}
491	break;
492	case 0x0300:
493	if (vendor_id != 0x80ee)
494	goto default_map;
495	/* VGA: map frame buffer to default Bochs VBE address */
496	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0xe0000000);
497	/*
498	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
499	* only the framebuffer (i.e., a memory region) is explicitly registered via
500	* devpciR3BiosInitSetRegionAddress, so don't forget to enable I/O decoding.
501	*/
502	devpciR3SetWord(pPciDev, PCI_COMMAND,
503	devpciR3GetWord(pPciDev, PCI_COMMAND)
504	\| PCI_COMMAND_IOACCESS \| PCI_COMMAND_MEMACCESS);
505	break;
506	case 0x0800:
507	/* PIC */
508	vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
509	device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
510	if (vendor_id == 0x1014)
511	{
512	/* IBM */
513	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
514	{
515	/* MPIC & MPIC2 */
516	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0x80800000 + 0x00040000);
517	devpciR3SetWord(pPciDev, PCI_COMMAND,
518	devpciR3GetWord(pPciDev, PCI_COMMAND)
519	\| PCI_COMMAND_MEMACCESS);
520	}
521	}
522	break;
523	case 0xff00:
524	if ( (vendor_id == 0x0106b)
525	&& (device_id == 0x0017 \|\| device_id == 0x0022))
526	{
527	/* macio bridge */
528	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0x80800000);
529	devpciR3SetWord(pPciDev, PCI_COMMAND,
530	devpciR3GetWord(pPciDev, PCI_COMMAND)
531	\| PCI_COMMAND_MEMACCESS);
532	}
533	break;
534	case 0x0604:
535	{
536	/* Init PCI-to-PCI bridge. */
537	devpciR3SetByte(pPciDev, VBOX_PCI_PRIMARY_BUS, pBus->iBus);
538
539	AssertMsg(pGlobals->uPciBiosBus < 255, ("Too many bridges on the bus\n"));
540	pGlobals->uPciBiosBus++;
541	devpciR3SetByte(pPciDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uPciBiosBus);
542	devpciR3SetByte(pPciDev, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
543
544	/* Add position of this bridge into the array. */
545	paBridgePositions[cBridgeDepth+1] = (pPciDev->uDevFn >> 3);
546
547	/*
548	* The I/O range for the bridge must be aligned to a 4KB boundary.
549	* This does not change anything really as the access to the device is not going
550	* through the bridge but we want to be compliant to the spec.
551	*/
552	if ((pGlobals->uPciBiosIo % _4K) != 0)
553	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
554	LogFunc(("Aligned I/O start address. New address %#x\n", pGlobals->uPciBiosIo));
555	devpciR3SetByte(pPciDev, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0);
556
557	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
558	if ((pGlobals->uPciBiosMmio % _1M) != 0)
559	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
560	LogFunc(("Aligned MMIO start address. New address %#x\n", pGlobals->uPciBiosMmio));
561	devpciR3SetWord(pPciDev, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
562
563	/* Save values to compare later to. */
564	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
565	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
566
567	/* Init devices behind the bridge and possibly other bridges as well. */
568	PDEVPCIBUS pChildBus = PDMINS_2_DATA(pPciDev->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
569	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pChildBus->apDevices); uDevFn++)
570	{
571	PPDMPCIDEV pChildPciDev = pChildBus->apDevices[uDevFn];
572	if (pChildPciDev)
573	pci_bios_init_device(pGlobals, pChildBus, pChildPciDev, cBridgeDepth + 1, paBridgePositions);
574	}
575
576	/* The number of bridges behind the this one is now available. */
577	devpciR3SetByte(pPciDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
578
579	/*
580	* Set I/O limit register. If there is no device with I/O space behind the bridge
581	* we set a lower value than in the base register.
582	* The result with a real bridge is that no I/O transactions are passed to the secondary
583	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
584	*/
585	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % _4K) != 0))
586	{
587	/* The upper boundary must be one byte less than a 4KB boundary. */
588	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
589	}
590	devpciR3SetByte(pPciDev, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1);
591
592	/* Same with the MMIO limit register but with 1MB boundary here. */
593	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % _1M) != 0))
594	{
595	/* The upper boundary must be one byte less than a 1MB boundary. */
596	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
597	}
598	devpciR3SetWord(pPciDev, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1);
599
600	/*
601	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
602	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
603	* the base register than in the limit register.
604	*/
605	devpciR3SetWord(pPciDev, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
606	devpciR3SetWord(pPciDev, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
607	devpciR3SetDWord(pPciDev, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
608	devpciR3SetDWord(pPciDev, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
609	break;
610	}
611	default:
612	default_map:
613	{
614	/* default memory mappings */
615	bool fActiveMemRegion = false;
616	bool fActiveIORegion = false;
617	/*
618	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
619	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
620	*/
621	for (unsigned i = 0; i < (PCI_NUM_REGIONS-1); i++)
622	{
623	uint32_t u32Size;
624	uint8_t u8RessourceType;
625	uint32_t u32Address = 0x10 + i * 4;
626
627	/* Calculate size. */
628	u8RessourceType = devpciR3GetByte(pPciDev, u32Address);
629	devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0xffffffff));
630	u32Size = devpciR3GetDWord(pPciDev, u32Address);
631	bool fIsPio = ((u8RessourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
632	/* Clear resource information depending on resource type. */
633	if (fIsPio) /* I/O */
634	u32Size &= ~(0x01);
635	else /* MMIO */
636	u32Size &= ~(0x0f);
637
638	/*
639	* Invert all bits and add 1 to get size of the region.
640	* (From PCI implementation note)
641	*/
642	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
643	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
644	else
645	u32Size = (~u32Size) + 1;
646
647	Log2Func(("Size of region %u for device %d on bus %d is %u\n", i, pPciDev->uDevFn, pBus->iBus, u32Size));
648
649	if (u32Size)
650	{
651	if (fIsPio)
652	paddr = &pGlobals->uPciBiosIo;
653	else
654	paddr = &pGlobals->uPciBiosMmio;
655	uint32_t uNew = *paddr;
656	uNew = (uNew + u32Size - 1) & ~(u32Size - 1);
657	if (fIsPio)
658	uNew &= UINT32_C(0xffff);
659	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
660	if (!uNew \|\| (uNew <= UINT32_C(0xffffffff) && uNew + u32Size - 1 >= UINT32_C(0xfec00000)))
661	{
662	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
663	i, pBus->iBus, pPciDev->uDevFn >> 3, pPciDev->uDevFn & 7, vendor_id, device_id)); /** @todo make this a VM start failure later. */
664	/* Undo the mapping mess caused by the size probing. */
665	devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0));
666	}
667	else
668	{
669	LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), i, uNew));
670	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, i, uNew);
671	if (fIsPio)
672	fActiveIORegion = true;
673	else
674	fActiveMemRegion = true;
675	*paddr = uNew + u32Size;
676	Log2Func(("New address is %#x\n", *paddr));
677	}
678	}
679	}
680
681	/* Update the command word appropriately. */
682	devpciR3SetWord(pPciDev, PCI_COMMAND,
683	devpciR3GetWord(pPciDev, PCI_COMMAND)
684	\| (fActiveMemRegion ? PCI_COMMAND_MEMACCESS : 0)
685	\| (fActiveIORegion ? PCI_COMMAND_IOACCESS : 0));
686
687	break;
688	}
689	}
690
691	/* map the interrupt */
692	pin = devpciR3GetByte(pPciDev, PCI_INTERRUPT_PIN);
693	if (pin != 0)
694	{
695	uint8_t uBridgeDevFn = pPciDev->uDevFn;
696	pin--;
697
698	/* We need to go up to the host bus to see which irq this device will assert there. */
699	while (cBridgeDepth != 0)
700	{
701	/* Get the pin the device would assert on the bridge. */
702	pin = ((uBridgeDevFn >> 3) + pin) & 3;
703	uBridgeDevFn = paBridgePositions[cBridgeDepth];
704	cBridgeDepth--;
705	}
706
707	pin = pci_slot_get_pirq(pPciDev->uDevFn, pin);
708	pic_irq = pci_irqs[pin];
709	devpciR3SetByte(pPciDev, PCI_INTERRUPT_LINE, pic_irq);
710	}
711	}
712	}
713
714	/**
715	* Worker for Fake PCI BIOS config, triggered by magic port access by BIOS.
716	*
717	* @returns VBox status code.
718	*
719	* @param pDevIns i440FX device instance.
720	*/
721	static int pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
722	{
723	uint8_t elcr[2] = {0, 0};
724	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
725	PVM pVM = PDMDevHlpGetVM(pDevIns); Assert(pVM);
726	PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns); Assert(pVM);
727	uint32_t const cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
728	uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
729	RT_NOREF(cbBelow4GB, cbAbove4GB);
730
731	LogRel(("PCI: Setting up resources and interrupts\n"));
732
733	/*
734	* Set the start addresses.
735	*/
736	pGlobals->uPciBiosBus = 0;
737	pGlobals->uPciBiosIo = 0xd000;
738	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
739
740	/*
741	* Activate IRQ mappings.
742	*/
743	PPDMPCIDEV pPIIX3 = &pGlobals->Piix3.PIIX3State.dev;
744	for (unsigned i = 0; i < 4; i++)
745	{
746	uint8_t irq = pci_irqs[i];
747	/* Set to trigger level. */
748	elcr[irq >> 3] \|= (1 << (irq & 7));
749	/* Activate irq remapping in PIIX3. */
750	devpciR3SetByte(pPIIX3, 0x60 + i, irq);
751	}
752
753	/* Tell to the PIC. */
754	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d0, elcr[0], sizeof(uint8_t));
755	if (rcStrict == VINF_SUCCESS)
756	rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d1, elcr[1], sizeof(uint8_t));
757	if (rcStrict != VINF_SUCCESS)
758	{
759	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
760	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
761	}
762
763	/*
764	* Init the devices.
765	*/
766	PDEVPCIBUS pBus = &pGlobals->PciBus;
767	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
768	{
769	PPDMPCIDEV pPciDev = pBus->apDevices[uDevFn];
770	uint8_t aBridgePositions[256];
771
772	if (pPciDev)
773	{
774	memset(aBridgePositions, 0, sizeof(aBridgePositions));
775	Log2(("PCI: Initializing device %d (%#x)\n",
776	uDevFn, 0x80000000 \| (uDevFn << 8)));
777	pci_bios_init_device(pGlobals, pBus, pPciDev, 0, aBridgePositions);
778	}
779	}
780
781	return VINF_SUCCESS;
782	}
783
784	#endif /* IN_RING3 */
785
786
787	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
788
789	/**
790	* @callback_method_impl{FNIOMIOPORTOUT, PCI address}
791	*/
792	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
793	{
794	LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
795	RT_NOREF2(Port, pvUser);
796	if (cb == 4)
797	{
798	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
799	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
800	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
801	PCI_UNLOCK(pDevIns);
802	}
803	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
804	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
805	return VINF_SUCCESS;
806	}
807
808
809	/**
810	* @callback_method_impl{FNIOMIOPORTIN, PCI address}
811	*/
812	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
813	{
814	RT_NOREF2(Port, pvUser);
815	if (cb == 4)
816	{
817	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
818	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
819	*pu32 = pThis->uConfigReg;
820	PCI_UNLOCK(pDevIns);
821	LogFunc(("Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
822	return VINF_SUCCESS;
823	}
824	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
825	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
826	LogFunc(("Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
827	return VERR_IOM_IOPORT_UNUSED;
828	}
829
830
831	/**
832	* @callback_method_impl{FNIOMIOPORTOUT, PCI data}
833	*/
834	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
835	{
836	LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
837	NOREF(pvUser);
838	int rc = VINF_SUCCESS;
839	if (!(Port % cb))
840	{
841	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
842	rc = pci_data_write(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), Port, u32, cb);
843	PCI_UNLOCK(pDevIns);
844	}
845	else
846	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
847	return rc;
848	}
849
850
851	/**
852	* @callback_method_impl{FNIOMIOPORTIN, PCI data}
853	*/
854	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
855	{
856	NOREF(pvUser);
857	if (!(Port % cb))
858	{
859	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
860	int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), Port, cb, pu32);
861	PCI_UNLOCK(pDevIns);
862	LogFunc(("Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
863	return rc;
864	}
865	AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
866	return VERR_IOM_IOPORT_UNUSED;
867	}
868
869	#ifdef IN_RING3
870
871	/**
872	* @callback_method_impl{FNIOMIOPORTOUT, PCI data}
873	*/
874	DECLCALLBACK(int) pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
875	{
876	RT_NOREF2(pvUser, Port);
877	LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
878	if (cb == 4)
879	{
880	if (u32 == UINT32_C(19200509)) // Richard Adams
881	{
882	int rc = pciR3FakePCIBIOS(pDevIns);
883	AssertRC(rc);
884	}
885	}
886
887	return VINF_SUCCESS;
888	}
889
890	/**
891	* @callback_method_impl{FNIOMIOPORTIN, PCI data}
892	*/
893	DECLCALLBACK(int) pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
894	{
895	RT_NOREF5(pDevIns, pvUser, Port, pu32, cb);
896	LogFunc(("Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
897	return VERR_IOM_IOPORT_UNUSED;
898	}
899
900
901	/*
902	* Include code we share with the other PCI bus implementation.
903	*
904	* Note! No #ifdefs, use instant data booleans/flags/whatever. Goal is to
905	* completely merge these files! File #1 contains code we write, where
906	* as a possible file #2 contains external code if there's any left.
907	*/
908	# include "DevPciMerge1.cpp.h"
909
910
911	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
912
913	/**
914	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
915	*
916	* @returns VBox status code.
917	* @param pBus The bus to save.
918	* @param pSSM The saved state handle.
919	*/
920	static int pciR3CommonSaveExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM)
921	{
922	/*
923	* Iterate thru all the devices.
924	*/
925	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
926	{
927	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
928	if (pDev)
929	{
930	SSMR3PutU32(pSSM, uDevFn);
931	SSMR3PutMem(pSSM, pDev->abConfig, sizeof(pDev->abConfig));
932
933	SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
934
935	/* Save the type an size of all the regions. */
936	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
937	{
938	SSMR3PutU8(pSSM, pDev->Int.s.aIORegions[iRegion].type);
939	SSMR3PutU64(pSSM, pDev->Int.s.aIORegions[iRegion].size);
940	}
941	}
942	}
943	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
944	}
945
946
947	/**
948	* @callback_method_impl{FNSSMDEVSAVEEXEC}
949	*/
950	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
951	{
952	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
953
954	/*
955	* Bus state data.
956	*/
957	SSMR3PutU32(pSSM, pThis->uConfigReg);
958	SSMR3PutBool(pSSM, pThis->fUseIoApic);
959
960	/*
961	* Save IRQ states.
962	*/
963	for (unsigned i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
964	SSMR3PutU32(pSSM, pThis->Piix3.auPciLegacyIrqLevels[i]);
965	for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
966	SSMR3PutU32(pSSM, pThis->auPciApicIrqLevels[i]);
967
968	SSMR3PutU32(pSSM, pThis->Piix3.iAcpiIrqLevel);
969	SSMR3PutS32(pSSM, pThis->Piix3.iAcpiIrq);
970
971	SSMR3PutU32(pSSM, UINT32_MAX); /* separator */
972
973	/*
974	* Join paths with pcibridgeR3SaveExec.
975	*/
976	return pciR3CommonSaveExec(&pThis->PciBus, pSSM);
977	}
978
979
980	/**
981	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
982	*
983	* @returns VBox status code.
984	* @param pBus The bus which data is being loaded.
985	* @param pSSM The saved state handle.
986	* @param uVersion The data version.
987	* @param uPass The pass.
988	*/
989	static DECLCALLBACK(int) pciR3CommonLoadExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
990	{
991	uint32_t u32;
992	int rc;
993
994	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
995
996	/*
997	* Iterate thru all the devices and write 0 to the COMMAND register so
998	* that all the memory is unmapped before we start restoring the saved
999	* mapping locations.
1000	*
1001	* The register value is restored afterwards so we can do proper
1002	* LogRels in devpciR3CommonRestoreConfig.
1003	*/
1004	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1005	{
1006	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1007	if (pDev)
1008	{
1009	uint16_t u16 = PCIDevGetCommand(pDev);
1010	pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, VBOX_PCI_COMMAND, 0, 2);
1011	PCIDevSetCommand(pDev, u16);
1012	Assert(PCIDevGetCommand(pDev) == u16);
1013	}
1014	}
1015
1016	/*
1017	* Iterate all the devices.
1018	*/
1019	for (uint32_t uDevFn = 0;; uDevFn++)
1020	{
1021	/* index / terminator */
1022	rc = SSMR3GetU32(pSSM, &u32);
1023	if (RT_FAILURE(rc))
1024	return rc;
1025	if (u32 == UINT32_MAX)
1026	break;
1027	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1028	\|\| u32 < uDevFn)
1029	{
1030	AssertMsgFailed(("u32=%#x uDevFn=%#x\n", u32, uDevFn));
1031	return rc;
1032	}
1033
1034	/* skip forward to the device checking that no new devices are present. */
1035	for (; uDevFn < u32; uDevFn++)
1036	{
1037	if (pBus->apDevices[uDevFn])
1038	{
1039	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", uDevFn, pBus->apDevices[uDevFn]->pszNameR3,
1040	PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn])));
1041	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1042	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1043	uDevFn, pBus->apDevices[uDevFn]->pszNameR3, PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn]));
1044	}
1045	}
1046
1047	/* get the data */
1048	PDMPCIDEV DevTmp;
1049	RT_ZERO(DevTmp);
1050	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1051	SSMR3GetMem(pSSM, DevTmp.abConfig, sizeof(DevTmp.abConfig));
1052	if (uVersion < VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1053	{
1054	int32_t i32Temp;
1055	/* Irq value not needed anymore. */
1056	rc = SSMR3GetS32(pSSM, &i32Temp);
1057	if (RT_FAILURE(rc))
1058	return rc;
1059	}
1060	else
1061	{
1062	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1063	if (RT_FAILURE(rc))
1064	return rc;
1065	}
1066
1067	/* Load the region types and sizes. */
1068	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES)
1069	{
1070	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
1071	{
1072	SSMR3GetU8(pSSM, &DevTmp.Int.s.aIORegions[iRegion].type);
1073	rc = SSMR3GetU64(pSSM, &DevTmp.Int.s.aIORegions[iRegion].size);
1074	AssertLogRelRCReturn(rc, rc);
1075	}
1076	}
1077
1078	/* check that it's still around. */
1079	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1080	if (!pDev)
1081	{
1082	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", uDevFn,
1083	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1084	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1085	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1086	uDevFn, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1087	continue;
1088	}
1089
1090	/* match the vendor id assuming that this will never be changed. */
1091	if ( DevTmp.abConfig[0] != pDev->abConfig[0]
1092	\|\| DevTmp.abConfig[1] != pDev->abConfig[1])
1093	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
1094	N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1095	uDevFn, pDev->pszNameR3, DevTmp.abConfig, pDev->abConfig);
1096
1097	/* commit the loaded device config. */
1098	rc = devpciR3CommonRestoreRegions(pSSM, pDev, DevTmp.Int.s.aIORegions,
1099	uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES);
1100	if (RT_FAILURE(rc))
1101	break;
1102	devpciR3CommonRestoreConfig(pDev, &DevTmp.abConfig[0]);
1103
1104	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1105	}
1106
1107	return VINF_SUCCESS;
1108	}
1109
1110
1111	/**
1112	* @callback_method_impl{FNSSMDEVLOADEXEC}
1113	*/
1114	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1115	{
1116	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1117	PDEVPCIBUS pBus = &pThis->PciBus;
1118	uint32_t u32;
1119	int rc;
1120
1121	/*
1122	* Check the version.
1123	*/
1124	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1125	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1126	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1127
1128	/*
1129	* Bus state data.
1130	*/
1131	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1132	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC)
1133	SSMR3GetBool(pSSM, &pThis->fUseIoApic);
1134
1135	/* Load IRQ states. */
1136	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1137	{
1138	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
1139	SSMR3GetU32(pSSM, (uint32_t *)&pThis->Piix3.auPciLegacyIrqLevels[i]);
1140	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
1141	SSMR3GetU32(pSSM, (uint32_t *)&pThis->auPciApicIrqLevels[i]);
1142
1143	SSMR3GetU32(pSSM, &pThis->Piix3.iAcpiIrqLevel);
1144	SSMR3GetS32(pSSM, &pThis->Piix3.iAcpiIrq);
1145	}
1146
1147	/* separator */
1148	rc = SSMR3GetU32(pSSM, &u32);
1149	if (RT_FAILURE(rc))
1150	return rc;
1151	if (u32 != UINT32_MAX)
1152	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1153
1154	/*
1155	* The devices.
1156	*/
1157	return pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1158	}
1159
1160
1161	/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
1162
1163
1164	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
1165
1166	/**
1167	* @callback_method_impl{FNDBGFHANDLERDEV}
1168	*/
1169	static DECLCALLBACK(void) pciR3IrqRouteInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1170	{
1171	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1172	PPDMPCIDEV pPIIX3 = &pGlobals->Piix3.PIIX3State.dev;
1173	NOREF(pszArgs);
1174
1175	uint16_t router = pPIIX3->uDevFn;
1176	pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1177	router >> 8, (router >> 3) & 0x1f, router & 0x7);
1178
1179	for (int i = 0; i < 4; ++i)
1180	{
1181	uint8_t irq_map = devpciR3GetByte(pPIIX3, 0x60 + i);
1182	if (irq_map & 0x80)
1183	pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1184	else
1185	pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1186	}
1187	}
1188
1189
1190	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1191
1192
1193	/**
1194	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1195	*/
1196	static DECLCALLBACK(int) pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1197	{
1198	RT_NOREF1(iInstance);
1199	Assert(iInstance == 0);
1200	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1201
1202	/*
1203	* Validate and read configuration.
1204	*/
1205	if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
1206	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1207
1208	/* query whether we got an IOAPIC */
1209	bool fUseIoApic;
1210	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
1211	if (RT_FAILURE(rc))
1212	return PDMDEV_SET_ERROR(pDevIns, rc,
1213	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
1214
1215	/* check if RC code is enabled. */
1216	bool fGCEnabled;
1217	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1218	if (RT_FAILURE(rc))
1219	return PDMDEV_SET_ERROR(pDevIns, rc,
1220	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
1221
1222	/* check if R0 code is enabled. */
1223	bool fR0Enabled;
1224	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1225	if (RT_FAILURE(rc))
1226	return PDMDEV_SET_ERROR(pDevIns, rc,
1227	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
1228	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
1229
1230	/*
1231	* Init data and register the PCI bus.
1232	*/
1233	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1234	pGlobals->uPciBiosIo = 0xc000;
1235	pGlobals->uPciBiosMmio = 0xf0000000;
1236	memset((void *)&pGlobals->Piix3.auPciLegacyIrqLevels, 0, sizeof(pGlobals->Piix3.auPciLegacyIrqLevels));
1237	pGlobals->fUseIoApic = fUseIoApic;
1238	memset((void *)&pGlobals->auPciApicIrqLevels, 0, sizeof(pGlobals->auPciApicIrqLevels));
1239
1240	pGlobals->pDevInsR3 = pDevIns;
1241	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1242	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1243
1244	pGlobals->PciBus.fTypePiix3 = true;
1245	pGlobals->PciBus.fTypeIch9 = false;
1246	pGlobals->PciBus.fPureBridge = false;
1247	pGlobals->PciBus.pDevInsR3 = pDevIns;
1248	pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1249	pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1250	pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns,
1251	sizeof(PPDMPCIDEV)
1252	* RT_ELEMENTS(pGlobals->PciBus.apDevices));
1253	AssertLogRelReturn(pGlobals->PciBus.papBridgesR3, VERR_NO_MEMORY);
1254
1255
1256	PDMPCIBUSREG PciBusReg;
1257	PDEVPCIBUS pBus = &pGlobals->PciBus;
1258	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
1259	PciBusReg.pfnRegisterR3 = pciR3MergedRegister;
1260	PciBusReg.pfnRegisterMsiR3 = NULL;
1261	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1262	PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
1263	PciBusReg.pfnSetIrqR3 = pciSetIrq;
1264	PciBusReg.pszSetIrqRC = fGCEnabled ? "pciSetIrq" : NULL;
1265	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
1266	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
1267	if (RT_FAILURE(rc))
1268	return PDMDEV_SET_ERROR(pDevIns, rc,
1269	N_("Failed to register ourselves as a PCI Bus"));
1270	Assert(pBus->iBus == 0);
1271	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1272	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1273	N_("PCI helper version mismatch; got %#x expected %#x"),
1274	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1275
1276	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1277	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
1278
1279	/* Disable default device locking. */
1280	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1281	AssertRCReturn(rc, rc);
1282
1283	/*
1284	* Fill in PCI configs and add them to the bus.
1285	*/
1286	/* i440FX */
1287	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
1288	PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
1289	PCIDevSetRevisionId(&pBus->PciDev, 0x02);
1290	PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
1291	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
1292	PCIDevSetHeaderType(&pBus->PciDev, 0x00);
1293	rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->PciDev, PDMPCIDEVREG_CFG_PRIMARY, 0 /fFlags/,
1294	0 /uPciDevNo/, 0 /uPciFunNo/, "i440FX");
1295	AssertLogRelRCReturn(rc, rc);
1296
1297	/* PIIX3 */
1298	PCIDevSetVendorId( &pGlobals->Piix3.PIIX3State.dev, 0x8086); /* Intel */
1299	PCIDevSetDeviceId( &pGlobals->Piix3.PIIX3State.dev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
1300	PCIDevSetClassSub( &pGlobals->Piix3.PIIX3State.dev, 0x01); /* PCI_ISA */
1301	PCIDevSetClassBase( &pGlobals->Piix3.PIIX3State.dev, 0x06); /* PCI_bridge */
1302	PCIDevSetHeaderType(&pGlobals->Piix3.PIIX3State.dev, 0x80); /* PCI_multifunction, generic */
1303	rc = PDMDevHlpPCIRegisterEx(pDevIns, &pGlobals->Piix3.PIIX3State.dev, PDMPCIDEVREG_CFG_NEXT, 0 /fFlags/,
1304	1 /uPciDevNo/, 0 /uPciFunNo/, "PIIX3");
1305	AssertLogRelRCReturn(rc, rc);
1306	pciR3Piix3Reset(&pGlobals->Piix3.PIIX3State);
1307
1308	pBus->iDevSearch = 16;
1309
1310	/*
1311	* Register I/O ports and save state.
1312	*/
1313	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
1314	if (RT_FAILURE(rc))
1315	return rc;
1316	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
1317	if (RT_FAILURE(rc))
1318	return rc;
1319	if (fGCEnabled)
1320	{
1321	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
1322	if (RT_FAILURE(rc))
1323	return rc;
1324	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
1325	if (RT_FAILURE(rc))
1326	return rc;
1327	}
1328	if (fR0Enabled)
1329	{
1330	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
1331	if (RT_FAILURE(rc))
1332	return rc;
1333	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
1334	if (RT_FAILURE(rc))
1335	return rc;
1336	}
1337
1338	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0410, 1, NULL, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead, NULL, NULL, "i440FX (Fake PCI BIOS trigger)")
1339	;
1340	if (RT_FAILURE(rc))
1341	return rc;
1342
1343
1344	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
1345	NULL, NULL, NULL,
1346	NULL, pciR3SaveExec, NULL,
1347	NULL, pciR3LoadExec, NULL);
1348	if (RT_FAILURE(rc))
1349	return rc;
1350
1351	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
1352	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
1353	devpciR3InfoPci);
1354	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", devpciR3InfoPciIrq);
1355	PDMDevHlpDBGFInfoRegister(pDevIns, "irqroute", "Display PCI IRQ routing. (no arguments)", pciR3IrqRouteInfo);
1356
1357	return VINF_SUCCESS;
1358	}
1359
1360
1361	/**
1362	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1363	*/
1364	static DECLCALLBACK(int) pciR3Destruct(PPDMDEVINS pDevIns)
1365	{
1366	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1367	if (pGlobals->PciBus.papBridgesR3)
1368	{
1369	PDMDevHlpMMHeapFree(pDevIns, pGlobals->PciBus.papBridgesR3);
1370	pGlobals->PciBus.papBridgesR3 = NULL;
1371	}
1372	return VINF_SUCCESS;
1373	}
1374
1375
1376	/**
1377	* @interface_method_impl{PDMDEVREG,pfnReset}
1378	*/
1379	static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
1380	{
1381	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1382	PDEVPCIBUS pBus = &pGlobals->PciBus;
1383
1384	/* PCI-specific reset for each device. */
1385	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1386	{
1387	if (pBus->apDevices[uDevFn])
1388	devpciR3ResetDevice(pBus->apDevices[uDevFn]);
1389	}
1390
1391	pciR3Piix3Reset(&pGlobals->Piix3.PIIX3State);
1392	}
1393
1394
1395	/**
1396	* The device registration structure.
1397	*/
1398	const PDMDEVREG g_DevicePCI =
1399	{
1400	/* u32Version */
1401	PDM_DEVREG_VERSION,
1402	/* szName */
1403	"pci",
1404	/* szRCMod */
1405	"VBoxDDRC.rc",
1406	/* szR0Mod */
1407	"VBoxDDR0.r0",
1408	/* pszDescription */
1409	"i440FX PCI bridge and PIIX3 ISA bridge.",
1410	/* fFlags */
1411	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1412	/* fClass */
1413	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
1414	/* cMaxInstances */
1415	1,
1416	/* cbInstance */
1417	sizeof(DEVPCIROOT),
1418	/* pfnConstruct */
1419	pciR3Construct,
1420	/* pfnDestruct */
1421	pciR3Destruct,
1422	/* pfnRelocate */
1423	devpciR3RootRelocate,
1424	/* pfnMemSetup */
1425	NULL,
1426	/* pfnPowerOn */
1427	NULL,
1428	/* pfnReset */
1429	pciR3Reset,
1430	/* pfnSuspend */
1431	NULL,
1432	/* pfnResume */
1433	NULL,
1434	/* pfnAttach */
1435	NULL,
1436	/* pfnDetach */
1437	NULL,
1438	/* pfnQueryInterface */
1439	NULL,
1440	/* pfnInitComplete */
1441	NULL,
1442	/* pfnPowerOff */
1443	NULL,
1444	/* pfnSoftReset */
1445	NULL,
1446	/* u32VersionEnd */
1447	PDM_DEVREG_VERSION
1448
1449	};
1450	#endif /* IN_RING3 */
1451
1452
1453
1454	/* -=-=-=-=-=- The PCI bridge specific bits -=-=-=-=-=- */
1455
1456	/**
1457	* @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
1458	*/
1459	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
1460	{
1461	/*
1462	* The PCI-to-PCI bridge specification defines how the interrupt pins
1463	* are routed from the secondary to the primary bus (see chapter 9).
1464	* iIrq gives the interrupt pin the pci device asserted.
1465	* We change iIrq here according to the spec and call the SetIrq function
1466	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
1467	*/
1468	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1469	PPDMPCIDEV pPciDevBus = pPciDev;
1470	int iIrqPinBridge = iIrq;
1471	uint8_t uDevFnBridge = 0;
1472
1473	/* Walk the chain until we reach the host bus. */
1474	do
1475	{
1476	uDevFnBridge = pBus->PciDev.uDevFn;
1477	iIrqPinBridge = ((pPciDevBus->uDevFn >> 3) + iIrqPinBridge) & 3;
1478
1479	/* Get the parent. */
1480	pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
1481	pPciDevBus = &pBus->PciDev;
1482	} while (pBus->iBus != 0);
1483
1484	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
1485	pciSetIrqInternal(DEVPCIBUS_2_DEVPCIROOT(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
1486	}
1487
1488	#ifdef IN_RING3
1489
1490	/**
1491	* @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
1492	*/
1493	static DECLCALLBACK(void) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1494	{
1495	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1496
1497	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1498
1499	/* If the current bus is not the target bus search for the bus which contains the device. */
1500	if (iBus != pBus->PciDev.abConfig[VBOX_PCI_SECONDARY_BUS])
1501	{
1502	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1503	if (pBridgeDevice)
1504	{
1505	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1506	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, u32Address, u32Value, cb);
1507	}
1508	}
1509	else
1510	{
1511	/* This is the target bus, pass the write to the device. */
1512	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1513	if (pPciDev)
1514	{
1515	LogFunc(("%s: addr=%02x val=%08x len=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
1516	/** @todo return rc */
1517	pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, u32Value, cb);
1518	}
1519	}
1520	}
1521
1522
1523	/**
1524	* @callback_method_impl{FNPCIBRIDGECONFIGREAD}
1525	*/
1526	static DECLCALLBACK(uint32_t) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1527	{
1528	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1529	uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
1530
1531	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1532
1533	/* If the current bus is not the target bus search for the bus which contains the device. */
1534	if (iBus != pBus->PciDev.abConfig[VBOX_PCI_SECONDARY_BUS])
1535	{
1536	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1537	if (pBridgeDevice)
1538	{
1539	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1540	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, u32Address, cb);
1541	}
1542	}
1543	else
1544	{
1545	/* This is the target bus, pass the read to the device. */
1546	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1547	if (pPciDev)
1548	{
1549	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb);
1550	LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
1551	}
1552	}
1553
1554	return u32Value;
1555	}
1556
1557
1558	/**
1559	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1560	*/
1561	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1562	{
1563	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1564	return pciR3CommonSaveExec(pThis, pSSM);
1565	}
1566
1567
1568	/**
1569	* @callback_method_impl{FNSSMDEVLOADEXEC}
1570	*/
1571	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1572	{
1573	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1574	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1575	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1576	return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1577	}
1578
1579
1580	/**
1581	* @interface_method_impl{PDMDEVREG,pfnReset}
1582	*/
1583	static DECLCALLBACK(void) pcibridgeR3Reset(PPDMDEVINS pDevIns)
1584	{
1585	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1586
1587	/* Reset config space to default values. */
1588	pBus->PciDev.abConfig[VBOX_PCI_PRIMARY_BUS] = 0;
1589	pBus->PciDev.abConfig[VBOX_PCI_SECONDARY_BUS] = 0;
1590	pBus->PciDev.abConfig[VBOX_PCI_SUBORDINATE_BUS] = 0;
1591	}
1592
1593
1594	/**
1595	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1596	*/
1597	static DECLCALLBACK(int) pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1598	{
1599	RT_NOREF(iInstance);
1600	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1601
1602	/*
1603	* Validate and read configuration.
1604	*/
1605	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
1606	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1607
1608	/* check if RC code is enabled. */
1609	bool fGCEnabled;
1610	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1611	if (RT_FAILURE(rc))
1612	return PDMDEV_SET_ERROR(pDevIns, rc,
1613	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
1614
1615	/* check if R0 code is enabled. */
1616	bool fR0Enabled;
1617	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1618	if (RT_FAILURE(rc))
1619	return PDMDEV_SET_ERROR(pDevIns, rc,
1620	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
1621	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
1622
1623	/*
1624	* Init data and register the PCI bus.
1625	*/
1626	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1627	pBus->fTypePiix3 = true;
1628	pBus->fTypeIch9 = false;
1629	pBus->fPureBridge = true;
1630	pBus->pDevInsR3 = pDevIns;
1631	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1632	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1633	pBus->papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pBus->apDevices));
1634	AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
1635
1636	PDMPCIBUSREG PciBusReg;
1637	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
1638	PciBusReg.pfnRegisterR3 = pcibridgeR3MergedRegisterDevice;
1639	PciBusReg.pfnRegisterMsiR3 = NULL;
1640	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1641	PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
1642	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
1643	PciBusReg.pszSetIrqRC = fGCEnabled ? "pcibridgeSetIrq" : NULL;
1644	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pcibridgeSetIrq" : NULL;
1645	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
1646	if (RT_FAILURE(rc))
1647	return PDMDEV_SET_ERROR(pDevIns, rc,
1648	N_("Failed to register ourselves as a PCI Bus"));
1649	Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
1650	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1651	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1652	N_("PCI helper version mismatch; got %#x expected %#x"),
1653	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1654
1655	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1656	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
1657
1658	/*
1659	* Fill in PCI configs and add them to the bus.
1660	*/
1661	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
1662	PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
1663	PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
1664	PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
1665	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
1666	PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
1667	PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
1668	PCIDevSetCommand( &pBus->PciDev, 0x0000);
1669	PCIDevSetStatus( &pBus->PciDev, 0x0020); /* 66MHz Capable. */
1670	PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
1671
1672	/*
1673	* This device does not generate interrupts. Interrupt delivery from
1674	* devices attached to the bus is unaffected.
1675	*/
1676	PCIDevSetInterruptPin(&pBus->PciDev, 0x00);
1677
1678	/*
1679	* Register this PCI bridge. The called function will take care on which bus we will get registered.
1680	*/
1681	rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->PciDev, PDMPCIDEVREG_CFG_PRIMARY, PDMPCIDEVREG_F_PCI_BRIDGE,
1682	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "pcibridge");
1683	if (RT_FAILURE(rc))
1684	return rc;
1685	pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
1686	pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
1687
1688	pBus->iDevSearch = 0;
1689
1690	/*
1691	* Register SSM handlers. We use the same saved state version as for the host bridge
1692	* to make changes easier.
1693	*/
1694	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
1695	NULL, NULL, NULL,
1696	NULL, pcibridgeR3SaveExec, NULL,
1697	NULL, pcibridgeR3LoadExec, NULL);
1698	if (RT_FAILURE(rc))
1699	return rc;
1700
1701	return VINF_SUCCESS;
1702	}
1703
1704
1705	/**
1706	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1707	*/
1708	static DECLCALLBACK(int) pcibridgeR3Destruct(PPDMDEVINS pDevIns)
1709	{
1710	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1711	if (pBus->papBridgesR3)
1712	{
1713	PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
1714	pBus->papBridgesR3 = NULL;
1715	}
1716	return VINF_SUCCESS;
1717	}
1718
1719
1720	/**
1721	* The device registration structure
1722	* for the PCI-to-PCI bridge.
1723	*/
1724	const PDMDEVREG g_DevicePCIBridge =
1725	{
1726	/* u32Version */
1727	PDM_DEVREG_VERSION,
1728	/* szName */
1729	"pcibridge",
1730	/* szRCMod */
1731	"VBoxDDRC.rc",
1732	/* szR0Mod */
1733	"VBoxDDR0.r0",
1734	/* pszDescription */
1735	"82801 Mobile PCI to PCI bridge",
1736	/* fFlags */
1737	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1738	/* fClass */
1739	PDM_DEVREG_CLASS_BUS_PCI,
1740	/* cMaxInstances */
1741	~0U,
1742	/* cbInstance */
1743	sizeof(DEVPCIBUS),
1744	/* pfnConstruct */
1745	pcibridgeR3Construct,
1746	/* pfnDestruct */
1747	pcibridgeR3Destruct,
1748	/* pfnRelocate */
1749	devpciR3BusRelocate,
1750	/* pfnMemSetup */
1751	NULL,
1752	/* pfnPowerOn */
1753	NULL,
1754	/* pfnReset */
1755	pcibridgeR3Reset,
1756	/* pfnSuspend */
1757	NULL,
1758	/* pfnResume */
1759	NULL,
1760	/* pfnAttach */
1761	NULL,
1762	/* pfnDetach */
1763	NULL,
1764	/* pfnQueryInterface */
1765	NULL,
1766	/* pfnInitComplete */
1767	NULL,
1768	/* pfnPowerOff */
1769	NULL,
1770	/* pfnSoftReset */
1771	NULL,
1772	/* u32VersionEnd */
1773	PDM_DEVREG_VERSION
1774	};
1775
1776	#endif /* IN_RING3 */
1777

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 73705

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