DevPCI.cpp@ 63009

Last change on this file since 63009 was 62889, checked in by vboxsync, 8 years ago
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1	/* $Id: DevPCI.cpp 62889 2016-08-02 22:34:46Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU PCI bus manager
21	*
22	* Copyright (c) 2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_DEV_PCI
48	/* Hack to get PCIDEVICEINT declared at the right point - include "PCIInternal.h". */
49	#define PCI_INCLUDE_PRIVATE
50	#include <VBox/pci.h>
51	#include <VBox/vmm/pdmdev.h>
52	#include <iprt/asm.h>
53	#include <iprt/assert.h>
54	#include <iprt/string.h>
55
56	#include "VBoxDD.h"
57
58
59	/*********************************************************************************************************************************
60	* Structures and Typedefs *
61	*********************************************************************************************************************************/
62	/**
63	* PIIX3 ISA Bridge state.
64	*/
65	typedef struct PIIX3State
66	{
67	/** The PCI device of the bridge. */
68	PCIDEVICE dev;
69	} PIIX3State, PIIX3, *PPIIX3;
70
71	/**
72	* PCI Bus instance.
73	*/
74	typedef struct PCIBus
75	{
76	/** Bus number. */
77	int32_t iBus;
78	/** Start device number. */
79	int32_t iDevSearch;
80	/** Number of bridges attached to the bus. */
81	uint32_t cBridges;
82
83	uint32_t Alignment0;
84
85	/** Array of PCI devices. */
86	R3PTRTYPE(PPCIDEVICE) devices[256];
87	/** Array of bridges attached to the bus. */
88	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
89
90	/** R3 pointer to the device instance. */
91	PPDMDEVINSR3 pDevInsR3;
92	/** Pointer to the PCI R3 helpers. */
93	PCPDMPCIHLPR3 pPciHlpR3;
94
95	/** R0 pointer to the device instance. */
96	PPDMDEVINSR0 pDevInsR0;
97	/** Pointer to the PCI R0 helpers. */
98	PCPDMPCIHLPR0 pPciHlpR0;
99
100	/** RC pointer to the device instance. */
101	PPDMDEVINSRC pDevInsRC;
102	/** Pointer to the PCI RC helpers. */
103	PCPDMPCIHLPRC pPciHlpRC;
104
105	/** The PCI device for the PCI bridge. */
106	PCIDEVICE PciDev;
107
108	} PCIBUS;
109	/** Pointer to a PCIBUS instance. */
110	typedef PCIBUS *PPCIBUS;
111	typedef PCIBUS PCIBus;
112
113	/** @def PCI_IRQ_PINS
114	* Number of pins for interrupts (PIRQ#0...PIRQ#3)
115	*/
116	#define PCI_IRQ_PINS 4
117
118	/** @def PCI_APIC_IRQ_PINS
119	* Number of pins for interrupts if the APIC is used.
120	*/
121	#define PCI_APIC_IRQ_PINS 8
122
123	/**
124	* PCI Globals - This is the host-to-pci bridge and the root bus.
125	*/
126	typedef struct PCIGLOBALS
127	{
128	/** Irq levels for the four PCI Irqs.
129	* These count how many devices asserted
130	* the IRQ line. If greater 0 an IRQ is sent to the guest.
131	* If it drops to 0 the IRQ is deasserted.
132	*/
133	volatile uint32_t pci_irq_levels[PCI_IRQ_PINS];
134
135	#if 1 /* Will be moved into the BIOS soon. */
136	/** The next I/O port address which the PCI BIOS will use. */
137	uint32_t pci_bios_io_addr;
138	/** The next MMIO address which the PCI BIOS will use. */
139	uint32_t pci_bios_mem_addr;
140	/** Actual bus number. */
141	uint8_t uBus;
142	#endif
143
144	/** I/O APIC usage flag */
145	bool fUseIoApic;
146	/** I/O APIC irq levels */
147	volatile uint32_t pci_apic_irq_levels[PCI_APIC_IRQ_PINS];
148	/** ACPI IRQ level */
149	uint32_t acpi_irq_level;
150	/** ACPI PIC IRQ */
151	int acpi_irq;
152	/** Config register. */
153	uint32_t uConfigReg;
154
155	/** R3 pointer to the device instance. */
156	PPDMDEVINSR3 pDevInsR3;
157	/** R0 pointer to the device instance. */
158	PPDMDEVINSR0 pDevInsR0;
159	/** RC pointer to the device instance. */
160	PPDMDEVINSRC pDevInsRC;
161
162	#if HC_ARCH_BITS == 64
163	uint32_t Alignment0;
164	#endif
165
166	/** ISA bridge state. */
167	PIIX3 PIIX3State;
168	/** PCI bus which is attached to the host-to-PCI bridge. */
169	PCIBUS PciBus;
170
171	} PCIGLOBALS;
172	/** Pointer to per VM data. */
173	typedef PCIGLOBALS *PPCIGLOBALS;
174
175
176	/*********************************************************************************************************************************
177	* Defined Constants And Macros *
178	*********************************************************************************************************************************/
179
180	/** Converts a bus instance pointer to a device instance pointer. */
181	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
182	/** Converts a PCI bus device instance pointer to a PCIGLOBALS pointer. */
183	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
184	/** Converts a PCI bus device instance pointer to a PCIBUS pointer. */
185	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->PciBus))
186
187	/** Converts a pointer to a PCI bus instance to a PCIGLOBALS pointer.
188	* @note This works only if the bus number is 0!!!
189	*/
190	#define PCIBUS_2_PCIGLOBALS(pPciBus) RT_FROM_MEMBER(pPciBus, PCIGLOBALS, PciBus)
191
192	/** @def PCI_LOCK
193	* Acquires the PDM lock. This is a NOP if locking is disabled. */
194	/** @def PCI_UNLOCK
195	* Releases the PDM lock. This is a NOP if locking is disabled. */
196	#define PCI_LOCK(pDevIns, rc) \
197	do { \
198	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
199	if (rc2 != VINF_SUCCESS) \
200	return rc2; \
201	} while (0)
202	#define PCI_UNLOCK(pDevIns) \
203	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
204
205	/** @def VBOX_PCI_SAVED_STATE_VERSION
206	* Saved state version of the PCI bus device.
207	*/
208	#define VBOX_PCI_SAVED_STATE_VERSION 3
209
210
211	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
212
213
214	/*********************************************************************************************************************************
215	* Internal Functions *
216	*********************************************************************************************************************************/
217	RT_C_DECLS_BEGIN
218
219	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTag);
220	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTag);
221	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
222	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
223	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
224	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
225
226	#ifdef IN_RING3
227	DECLINLINE(PPCIDEVICE) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus);
228	#endif
229
230	RT_C_DECLS_END
231
232	#define DEBUG_PCI
233
234	#define PCI_VENDOR_ID 0x00 /* 16 bits */
235	#define PCI_DEVICE_ID 0x02 /* 16 bits */
236	#define PCI_COMMAND 0x04 /* 16 bits */
237	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
238	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
239	#define PCI_CLASS_DEVICE 0x0a /* Device class */
240	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
241	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
242	#define PCI_MIN_GNT 0x3e /* 8 bits */
243	#define PCI_MAX_LAT 0x3f /* 8 bits */
244
245
246	#ifdef IN_RING3
247
248	static void pci_update_mappings(PCIDevice *d)
249	{
250	PPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);
251	PCIIORegion *r;
252	int cmd, i;
253	uint32_t last_addr, new_addr, config_ofs;
254
255	cmd = RT_LE2H_U16((uint16_t )(d->config + PCI_COMMAND));
256	for(i = 0; i < PCI_NUM_REGIONS; i++) {
257	r = &d->Int.s.aIORegions[i];
258	if (i == PCI_ROM_SLOT) {
259	config_ofs = 0x30;
260	} else {
261	config_ofs = 0x10 + i * 4;
262	}
263	if (r->size != 0) {
264	if (r->type & PCI_ADDRESS_SPACE_IO) {
265	if (cmd & PCI_COMMAND_IO) {
266	new_addr = RT_LE2H_U32((uint32_t )(d->config +
267	config_ofs));
268	new_addr = new_addr & ~(r->size - 1);
269	last_addr = new_addr + r->size - 1;
270	/* NOTE: we have only 64K ioports on PC */
271	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
272	last_addr >= 0x10000) {
273	new_addr = ~0U;
274	}
275	} else {
276	new_addr = ~0U;
277	}
278	} else {
279	if (cmd & PCI_COMMAND_MEMORY) {
280	new_addr = RT_LE2H_U32((uint32_t )(d->config +
281	config_ofs));
282	/* the ROM slot has a specific enable bit */
283	if (i == PCI_ROM_SLOT && !(new_addr & 1))
284	goto no_mem_map;
285	new_addr = new_addr & ~(r->size - 1);
286	last_addr = new_addr + r->size - 1;
287	/* NOTE: we do not support wrapping */
288	/* XXX: as we cannot support really dynamic
289	mappings, we handle specific values as invalid
290	mappings. */
291	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
292	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
293	(new_addr <= ~0U && last_addr >= 0xfec00000U)) {
294	new_addr = ~0U;
295	}
296	} else {
297	no_mem_map:
298	new_addr = ~0U;
299	}
300	}
301	//LogRel(("PCI: config dev %u/%u BAR%i uOld=%#018llx uNew=%#018llx size=%llu\n", d->devfn >> 3, d->devfn & 7, i, r->addr, new_addr, r->size));
302	/* now do the real mapping */
303	if (new_addr != r->addr) {
304	if (r->addr != ~0U) {
305	if (r->type & PCI_ADDRESS_SPACE_IO) {
306	int devclass;
307	/* NOTE: specific hack for IDE in PC case:
308	only one byte must be mapped. */
309	devclass = d->config[0x0a] \| (d->config[0x0b] << 8);
310	if (devclass == 0x0101 && r->size == 4) {
311	int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr + 2, 1);
312	AssertRC(rc);
313	} else {
314	int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr, r->size);
315	AssertRC(rc);
316	}
317	} else {
318	RTGCPHYS GCPhysBase = r->addr;
319	int rc;
320	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, d->pDevIns, GCPhysBase))
321	{
322	/* unmap it. */
323	rc = r->map_func(d, i, NIL_RTGCPHYS, r->size, (PCIADDRESSSPACE)(r->type));
324	AssertRC(rc);
325	rc = PDMDevHlpMMIO2Unmap(d->pDevIns, i, GCPhysBase);
326	}
327	else
328	rc = PDMDevHlpMMIODeregister(d->pDevIns, GCPhysBase, r->size);
329	AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, d->name, i, GCPhysBase, r->size));
330	}
331	}
332	r->addr = new_addr;
333	if (r->addr != ~0U) {
334	int rc = r->map_func(d, i,
335	r->addr + (r->type & PCI_ADDRESS_SPACE_IO ? 0 : 0),
336	r->size, (PCIADDRESSSPACE)(r->type));
337	AssertRC(rc);
338	}
339	}
340	}
341	}
342	}
343
344
345	static DECLCALLBACK(uint32_t) pci_default_read_config(PCIDevice *d, uint32_t address, unsigned len)
346	{
347	uint32_t val;
348	switch(len) {
349	case 1:
350	val = d->config[address];
351	break;
352	case 2:
353	val = RT_LE2H_U16((uint16_t )(d->config + address));
354	break;
355	default:
356	case 4:
357	val = RT_LE2H_U32((uint32_t )(d->config + address));
358	break;
359	}
360	return val;
361	}
362
363	static DECLCALLBACK(void) pci_default_write_config(PCIDevice *d, uint32_t address, uint32_t val, unsigned len)
364	{
365	int can_write;
366	unsigned i;
367	uint32_t end, addr;
368
369	if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) \|\|
370	(address >= 0x30 && address < 0x34))) {
371	PCIIORegion *r;
372	int reg;
373
374	if ( address >= 0x30 ) {
375	reg = PCI_ROM_SLOT;
376	}else{
377	reg = (address - 0x10) >> 2;
378	}
379	r = &d->Int.s.aIORegions[reg];
380	if (r->size == 0)
381	goto default_config;
382	/* compute the stored value */
383	if (reg == PCI_ROM_SLOT) {
384	/* keep ROM enable bit */
385	val &= (~(r->size - 1)) \| 1;
386	} else {
387	val &= ~(r->size - 1);
388	val \|= r->type;
389	}
390	(uint32_t )(d->config + address) = RT_H2LE_U32(val);
391	pci_update_mappings(d);
392	return;
393	}
394	default_config:
395	/* not efficient, but simple */
396	addr = address;
397	for(i = 0; i < len; i++) {
398	/* default read/write accesses */
399	switch(d->config[0x0e]) {
400	case 0x00: /* normal device */
401	case 0x80: /* multi-function device */
402	switch(addr) {
403	case 0x00:
404	case 0x01:
405	case 0x02:
406	case 0x03:
407	case 0x08:
408	case 0x09:
409	case 0x0a:
410	case 0x0b:
411	case 0x0e:
412	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: /* base */
413	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
414	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
415	case 0x2c: case 0x2d: /* subsystem ID */
416	case 0x2e: case 0x2f: /* vendor ID */
417	case 0x30: case 0x31: case 0x32: case 0x33: /* rom */
418	case 0x34: /* Capabilities pointer. */
419	case 0x3d: /* Interrupt pin. */
420	can_write = 0;
421	break;
422	default:
423	can_write = 1;
424	break;
425	}
426	break;
427	default:
428	case 0x01: /* bridge */
429	switch(addr) {
430	case 0x00:
431	case 0x01:
432	case 0x02:
433	case 0x03:
434	case 0x08:
435	case 0x09:
436	case 0x0a:
437	case 0x0b:
438	case 0x0e:
439	case 0x38: case 0x39: case 0x3a: case 0x3b: /* rom */
440	case 0x3d:
441	can_write = 0;
442	break;
443	default:
444	can_write = 1;
445	break;
446	}
447	break;
448	}
449	#ifdef VBOX
450	if (addr == 0x05) /* Command register, bits 8-15. */
451	{
452	/* don't change reserved bits (11-15) */
453	val &= ~UINT32_C(0xf8);
454	d->config[addr] = val;
455	}
456	else if (addr == 0x06) /* Status register, bits 0-7. */
457	{
458	/* don't change read-only bits => actually all lower bits are read-only */
459	val &= ~UINT32_C(0xff);
460	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
461	d->config[addr] &= ~val;
462	}
463	else if (addr == 0x07) /* Status register, bits 8-15. */
464	{
465	/* don't change read-only bits */
466	val &= ~UINT32_C(0x06);
467	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
468	d->config[addr] &= ~val;
469	}
470	else
471	#endif
472	if (can_write) {
473	d->config[addr] = val;
474	}
475	addr++;
476	val >>= 8;
477	}
478
479	end = address + len;
480	if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
481	/* if the command register is modified, we must modify the mappings */
482	pci_update_mappings(d);
483	}
484	}
485
486	#endif /* IN_RING3 */
487
488	static int pci_data_write(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
489	{
490	uint8_t iBus, iDevice;
491	uint32_t config_addr;
492
493	Log(("pci_data_write: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
494
495	if (!(pGlobals->uConfigReg & (1 << 31))) {
496	return VINF_SUCCESS;
497	}
498	if ((pGlobals->uConfigReg & 0x3) != 0) {
499	return VINF_SUCCESS;
500	}
501	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
502	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
503	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
504	if (iBus != 0)
505	{
506	if (pGlobals->PciBus.cBridges)
507	{
508	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
509	PPCIDEVICE pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
510	if (pBridgeDevice)
511	{
512	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
513	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, val, len);
514	}
515	#else
516	RT_NOREF2(val, len);
517	return VINF_IOM_R3_IOPORT_WRITE;
518	#endif
519	}
520	}
521	else
522	{
523	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
524	if (pci_dev)
525	{
526	#ifdef IN_RING3
527	Log(("pci_config_write: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
528	pci_dev->Int.s.pfnConfigWrite(pci_dev, config_addr, val, len);
529	#else
530	return VINF_IOM_R3_IOPORT_WRITE;
531	#endif
532	}
533	}
534	return VINF_SUCCESS;
535	}
536
537	static int pci_data_read(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
538	{
539	uint8_t iBus, iDevice;
540	uint32_t config_addr;
541
542	*pu32 = 0xffffffff;
543
544	if (!(pGlobals->uConfigReg & (1 << 31)))
545	return VINF_SUCCESS;
546	if ((pGlobals->uConfigReg & 0x3) != 0)
547	return VINF_SUCCESS;
548	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
549	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
550	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
551	if (iBus != 0)
552	{
553	if (pGlobals->PciBus.cBridges)
554	{
555	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
556	PPCIDEVICE pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
557	if (pBridgeDevice)
558	{
559	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
560	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, len);
561	}
562	#else
563	NOREF(len);
564	return VINF_IOM_R3_IOPORT_READ;
565	#endif
566	}
567	}
568	else
569	{
570	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
571	if (pci_dev)
572	{
573	#ifdef IN_RING3
574	*pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev, config_addr, len);
575	Log(("pci_config_read: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, *pu32, len));
576	#else
577	NOREF(len);
578	return VINF_IOM_R3_IOPORT_READ;
579	#endif
580	}
581	}
582
583	return VINF_SUCCESS;
584	}
585
586
587
588	/* return the global irq number corresponding to a given device irq
589	pin. We could also use the bus number to have a more precise
590	mapping.
591	This is the implementation note described in the PCI spec chapter 2.2.6 */
592	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
593	{
594	int slot_addend;
595	slot_addend = (uDevFn >> 3) - 1;
596	return (irq_num + slot_addend) & 3;
597	}
598
599	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
600	{
601	return (irq_num + (uDevFn >> 3)) & 7;
602	}
603
604	static inline int get_pci_irq_apic_level(PPCIGLOBALS pGlobals, int irq_num)
605	{
606	return (pGlobals->pci_apic_irq_levels[irq_num] != 0);
607	}
608
609	static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int acpi_irq, uint32_t uTagSrc)
610	{
611	/* This is only allowed to be called with a pointer to the host bus. */
612	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
613
614	if (acpi_irq == -1) {
615	int apic_irq, apic_level;
616	PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pBus);
617	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
618
619	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
620	ASMAtomicIncU32(&pGlobals->pci_apic_irq_levels[irq_num]);
621	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
622	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
623
624	apic_irq = irq_num + 0x10;
625	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
626	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
627	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
628	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
629
630	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
631	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
632	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
633	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
634	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
635	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
636	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
637	}
638	} else {
639	Log3(("apic_set_irq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
640	R3STRING(pPciDev->name), irq_num1, iLevel, acpi_irq));
641	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), acpi_irq, iLevel, uTagSrc);
642	}
643	}
644
645	DECLINLINE(int) get_pci_irq_level(PPCIGLOBALS pGlobals, int irq_num)
646	{
647	return (pGlobals->pci_irq_levels[irq_num] != 0);
648	}
649
650	/**
651	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
652	*
653	* @param pDevIns Device instance of the host PCI Bus.
654	* @param uDevFn The device number on the host bus which will raise the IRQ
655	* @param pPciDev The PCI device structure which raised the interrupt.
656	* @param iIrq IRQ number to set.
657	* @param iLevel IRQ level.
658	* @param uTagSrc The IRQ tag and source ID (for tracing).
659	* @remark uDevFn and pPciDev->devfn are not the same if the device is behind a bridge.
660	* In that case uDevFn will be the slot of the bridge which is needed to calculate the
661	* PIRQ value.
662	*/
663	static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
664	{
665	PPCIBUS pBus = &pGlobals->PciBus;
666	uint8_t *pbCfg = pGlobals->PIIX3State.dev.config;
667	const bool fIsAcpiDevice = pPciDev->config[2] == 0x13 && pPciDev->config[3] == 0x71;
668	/* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
669	* is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
670	* See the \_SB_.PCI0._PRT method in vbox.dsl.
671	*/
672	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
673	int pic_irq, pic_level;
674
675	/* Check if the state changed. */
676	if (pPciDev->Int.s.uIrqPinState != iLevel)
677	{
678	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
679
680	/* Send interrupt to I/O APIC only. */
681	if (fIsApicEnabled)
682	{
683	if (fIsAcpiDevice)
684	/*
685	* ACPI needs special treatment since SCI is hardwired and
686	* should not be affected by PCI IRQ routing tables at the
687	* same time SCI IRQ is shared in PCI sense hence this
688	* kludge (i.e. we fetch the hardwired value from ACPIs
689	* PCI device configuration space).
690	*/
691	apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->config[PCI_INTERRUPT_LINE], uTagSrc);
692	else
693	apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
694	return;
695	}
696
697	if (fIsAcpiDevice)
698	{
699	/* As per above treat ACPI in a special way */
700	pic_irq = pPciDev->config[PCI_INTERRUPT_LINE];
701	pGlobals->acpi_irq = pic_irq;
702	pGlobals->acpi_irq_level = iLevel & PDM_IRQ_LEVEL_HIGH;
703	}
704	else
705	{
706	int irq_num;
707	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
708
709	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
710	ASMAtomicIncU32(&pGlobals->pci_irq_levels[irq_num]);
711	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
712	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
713
714	/* now we change the pic irq level according to the piix irq mappings */
715	pic_irq = pbCfg[0x60 + irq_num];
716	if (pic_irq >= 16)
717	{
718	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
719	{
720	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
721	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
722	}
723
724	return;
725	}
726	}
727
728	/* the pic level is the logical OR of all the PCI irqs mapped to it */
729	pic_level = 0;
730	if (pic_irq == pbCfg[0x60])
731	pic_level \|= get_pci_irq_level(pGlobals, 0);
732	if (pic_irq == pbCfg[0x61])
733	pic_level \|= get_pci_irq_level(pGlobals, 1);
734	if (pic_irq == pbCfg[0x62])
735	pic_level \|= get_pci_irq_level(pGlobals, 2);
736	if (pic_irq == pbCfg[0x63])
737	pic_level \|= get_pci_irq_level(pGlobals, 3);
738	if (pic_irq == pGlobals->acpi_irq)
739	pic_level \|= pGlobals->acpi_irq_level;
740
741	Log3(("pciSetIrq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
742	R3STRING(pPciDev->name), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
743	pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level, uTagSrc);
744
745	/** @todo optimize pci irq flip-flop some rainy day. */
746	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
747	pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
748	}
749	}
750
751
752	/**
753	* @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
754	*/
755	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
756	{
757	pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc);
758	}
759
760	#ifdef IN_RING3
761
762	/**
763	* Finds a bridge on the bus which contains the destination bus.
764	*
765	* @return Pointer to the device instance data of the bus or
766	* NULL if no bridge was found.
767	* @param pBus Pointer to the bus to search on.
768	* @param iBus Destination bus number.
769	*/
770	DECLINLINE(PPCIDEVICE) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus)
771	{
772	/* Search for a fitting bridge. */
773	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
774	{
775	/*
776	* Examine secondary and subordinate bus number.
777	* If the target bus is in the range we pass the request on to the bridge.
778	*/
779	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
780	AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
781	("Device is not a PCI bridge but on the list of PCI bridges\n"));
782
783	if ( iBus >= pBridgeTemp->config[VBOX_PCI_SECONDARY_BUS]
784	&& iBus <= pBridgeTemp->config[VBOX_PCI_SUBORDINATE_BUS])
785	return pBridgeTemp;
786	}
787
788	/* Nothing found. */
789	return NULL;
790	}
791
792	static void pciR3Piix3Reset(PIIX3State *d)
793	{
794	uint8_t *pci_conf = d->dev.config;
795
796	pci_conf[0x04] = 0x07; /* master, memory and I/O */
797	pci_conf[0x05] = 0x00;
798	pci_conf[0x06] = 0x00;
799	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
800	pci_conf[0x4c] = 0x4d;
801	pci_conf[0x4e] = 0x03;
802	pci_conf[0x4f] = 0x00;
803	pci_conf[0x60] = 0x80;
804	pci_conf[0x69] = 0x02;
805	pci_conf[0x70] = 0x80;
806	pci_conf[0x76] = 0x0c;
807	pci_conf[0x77] = 0x0c;
808	pci_conf[0x78] = 0x02;
809	pci_conf[0x79] = 0x00;
810	pci_conf[0x80] = 0x00;
811	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
812	pci_conf[0xa0] = 0x08;
813	pci_conf[0xa2] = 0x00;
814	pci_conf[0xa3] = 0x00;
815	pci_conf[0xa4] = 0x00;
816	pci_conf[0xa5] = 0x00;
817	pci_conf[0xa6] = 0x00;
818	pci_conf[0xa7] = 0x00;
819	pci_conf[0xa8] = 0x0f;
820	pci_conf[0xaa] = 0x00;
821	pci_conf[0xab] = 0x00;
822	pci_conf[0xac] = 0x00;
823	pci_conf[0xae] = 0x00;
824	}
825
826	static void pci_config_writel(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
827	{
828	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
829	(uDevFn << 8) \| addr;
830	pci_data_write(pGlobals, 0, val, 4);
831	}
832
833	static void pci_config_writew(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
834	{
835	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
836	(uDevFn << 8) \| (addr & ~3);
837	pci_data_write(pGlobals, addr & 3, val, 2);
838	}
839
840	static void pci_config_writeb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
841	{
842	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
843	(uDevFn << 8) \| (addr & ~3);
844	pci_data_write(pGlobals, addr & 3, val, 1);
845	}
846
847	static uint32_t pci_config_readl(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
848	{
849	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
850	(uDevFn << 8) \| addr;
851	uint32_t u32Val;
852	int rc = pci_data_read(pGlobals, 0, 4, &u32Val);
853	AssertRC(rc);
854	return u32Val;
855	}
856
857	static uint32_t pci_config_readw(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
858	{
859	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
860	(uDevFn << 8) \| (addr & ~3);
861	uint32_t u32Val;
862	int rc = pci_data_read(pGlobals, addr & 3, 2, &u32Val);
863	AssertRC(rc);
864	return u32Val;
865	}
866
867	static uint32_t pci_config_readb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
868	{
869	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
870	(uDevFn << 8) \| (addr & ~3);
871	uint32_t u32Val;
872	int rc = pci_data_read(pGlobals, addr & 3, 1, &u32Val);
873	AssertRC(rc);
874	return u32Val;
875	}
876
877	/* host irqs corresponding to PCI irqs A-D */
878	static const uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; /* bird: added const */
879
880	static void pci_set_io_region_addr(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int region_num, uint32_t addr)
881	{
882	uint32_t ofs;
883
884	if ( region_num == PCI_ROM_SLOT )
885	ofs = 0x30;
886	else
887	ofs = 0x10 + region_num * 4;
888
889	Log(("Set region address: %02x:%02x.%d region %d address=%lld\n",
890	uBus, uDevFn >> 3, uDevFn & 7, region_num, addr));
891
892	/* Write address of the device. */
893	pci_config_writel(pGlobals, uBus, uDevFn, ofs, addr);
894	}
895
896	static void pci_bios_init_device(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
897	{
898	uint32_t *paddr;
899	int i, pin, pic_irq;
900	uint16_t devclass, vendor_id, device_id;
901
902	devclass = pci_config_readw(pGlobals, uBus, uDevFn, PCI_CLASS_DEVICE);
903	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
904	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
905
906	/* Check if device is present. */
907	if (vendor_id != 0xffff)
908	{
909	switch(devclass)
910	{
911	case 0x0101:
912	if ( (vendor_id == 0x8086)
913	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
914	{
915	/* PIIX3, PIIX4 or ICH6 IDE */
916	pci_config_writew(pGlobals, uBus, uDevFn, 0x40, 0x8000); /* enable IDE0 */
917	pci_config_writew(pGlobals, uBus, uDevFn, 0x42, 0x8000); /* enable IDE1 */
918	goto default_map;
919	}
920	else
921	{
922	/* IDE: we map it as in ISA mode */
923	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x1f0);
924	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 1, 0x3f4);
925	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 2, 0x170);
926	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 3, 0x374);
927	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
928	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
929	\| PCI_COMMAND_IOACCESS);
930	}
931	break;
932	case 0x0300:
933	if (vendor_id != 0x80ee)
934	goto default_map;
935	/* VGA: map frame buffer to default Bochs VBE address */
936	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0xE0000000);
937	/*
938	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
939	* only the framebuffer (i.e., a memory region) is explicitly registered via
940	* pci_set_io_region_addr, so don't forget to enable I/O decoding.
941	*/
942	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
943	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
944	\| PCI_COMMAND_IOACCESS \| PCI_COMMAND_MEMACCESS);
945	break;
946	case 0x0800:
947	/* PIC */
948	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
949	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
950	if (vendor_id == 0x1014)
951	{
952	/* IBM */
953	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
954	{
955	/* MPIC & MPIC2 */
956	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
957	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
958	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
959	\| PCI_COMMAND_MEMACCESS);
960	}
961	}
962	break;
963	case 0xff00:
964	if ( (vendor_id == 0x0106b)
965	&& (device_id == 0x0017 \|\| device_id == 0x0022))
966	{
967	/* macio bridge */
968	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000);
969	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
970	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
971	\| PCI_COMMAND_MEMACCESS);
972	}
973	break;
974	case 0x0604:
975	{
976	/* Init PCI-to-PCI bridge. */
977	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus);
978
979	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
980	pGlobals->uBus++;
981	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
982	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
983
984	/* Add position of this bridge into the array. */
985	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
986
987	/*
988	* The I/O range for the bridge must be aligned to a 4KB boundary.
989	* This does not change anything really as the access to the device is not going
990	* through the bridge but we want to be compliant to the spec.
991	*/
992	if ((pGlobals->pci_bios_io_addr % 4096) != 0)
993	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
994	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_io_addr));
995	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->pci_bios_io_addr >> 8) & 0xf0);
996
997	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
998	if ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0)
999	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1000	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_mem_addr));
1001	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xffff0));
1002
1003	/* Save values to compare later to. */
1004	uint32_t u32IoAddressBase = pGlobals->pci_bios_io_addr;
1005	uint32_t u32MMIOAddressBase = pGlobals->pci_bios_mem_addr;
1006
1007	/* Init devices behind the bridge and possibly other bridges as well. */
1008	for (int iDev = 0; iDev <= 255; iDev++)
1009	pci_bios_init_device(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1010
1011	/* The number of bridges behind the this one is now available. */
1012	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1013
1014	/*
1015	* Set I/O limit register. If there is no device with I/O space behind the bridge
1016	* we set a lower value than in the base register.
1017	* The result with a real bridge is that no I/O transactions are passed to the secondary
1018	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1019	*/
1020	if ((u32IoAddressBase != pGlobals->pci_bios_io_addr) && ((pGlobals->pci_bios_io_addr % 4096) != 0))
1021	{
1022	/* The upper boundary must be one byte less than a 4KB boundary. */
1023	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
1024	}
1025	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->pci_bios_io_addr >> 8) & 0xf0) - 1);
1026
1027	/* Same with the MMIO limit register but with 1MB boundary here. */
1028	if ((u32MMIOAddressBase != pGlobals->pci_bios_mem_addr) && ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0))
1029	{
1030	/* The upper boundary must be one byte less than a 1MB boundary. */
1031	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1032	}
1033	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xfff0)) - 1);
1034
1035	/*
1036	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1037	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1038	* the base register than in the limit register.
1039	*/
1040	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
1041	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
1042	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
1043	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
1044	break;
1045	}
1046	default:
1047	default_map:
1048	{
1049	/* default memory mappings */
1050	bool fActiveMemRegion = false;
1051	bool fActiveIORegion = false;
1052	/*
1053	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
1054	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
1055	*/
1056	for(i = 0; i < (PCI_NUM_REGIONS-1); i++)
1057	{
1058	uint32_t u32Size;
1059	uint8_t u8RessourceType;
1060	uint32_t u32Address = 0x10 + i * 4;
1061
1062	/* Calculate size. */
1063	u8RessourceType = pci_config_readb(pGlobals, uBus, uDevFn, u32Address);
1064	pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff));
1065	u32Size = pci_config_readl(pGlobals, uBus, uDevFn, u32Address);
1066	bool fIsPio = ((u8RessourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1067	/* Clear resource information depending on resource type. */
1068	if (fIsPio) /* I/O */
1069	u32Size &= ~(0x01);
1070	else /* MMIO */
1071	u32Size &= ~(0x0f);
1072
1073	/*
1074	* Invert all bits and add 1 to get size of the region.
1075	* (From PCI implementation note)
1076	*/
1077	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
1078	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1079	else
1080	u32Size = (~u32Size) + 1;
1081
1082	Log2(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, i, uDevFn, uBus, u32Size));
1083
1084	if (u32Size)
1085	{
1086	if (fIsPio)
1087	paddr = &pGlobals->pci_bios_io_addr;
1088	else
1089	paddr = &pGlobals->pci_bios_mem_addr;
1090	uint32_t uNew = *paddr;
1091	uNew = (uNew + u32Size - 1) & ~(u32Size - 1);
1092	if (fIsPio)
1093	uNew &= UINT32_C(0xffff);
1094	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
1095	if (!uNew \|\| (uNew <= UINT32_C(0xffffffff) && uNew + u32Size - 1 >= UINT32_C(0xfec00000)))
1096	{
1097	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
1098	i, uBus, uDevFn >> 3, uDevFn & 7, vendor_id, device_id)); /** @todo make this a VM start failure later. */
1099	/* Undo the mapping mess caused by the size probing. */
1100	pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0));
1101	}
1102	else
1103	{
1104	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), i, uNew));
1105	pci_set_io_region_addr(pGlobals, uBus, uDevFn, i, uNew);
1106	if (fIsPio)
1107	fActiveIORegion = true;
1108	else
1109	fActiveMemRegion = true;
1110	*paddr = uNew + u32Size;
1111	Log2(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1112	}
1113	}
1114	}
1115
1116	/* Update the command word appropriately. */
1117	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
1118	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
1119	\| (fActiveMemRegion ? PCI_COMMAND_MEMACCESS : 0)
1120	\| (fActiveIORegion ? PCI_COMMAND_IOACCESS : 0));
1121
1122	break;
1123	}
1124	}
1125
1126	/* map the interrupt */
1127	pin = pci_config_readb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_PIN);
1128	if (pin != 0)
1129	{
1130	uint8_t uBridgeDevFn = uDevFn;
1131	pin--;
1132
1133	/* We need to go up to the host bus to see which irq this device will assert there. */
1134	while (cBridgeDepth != 0)
1135	{
1136	/* Get the pin the device would assert on the bridge. */
1137	pin = ((uBridgeDevFn >> 3) + pin) & 3;
1138	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1139	cBridgeDepth--;
1140	}
1141
1142	pin = pci_slot_get_pirq(uDevFn, pin);
1143	pic_irq = pci_irqs[pin];
1144	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
1145	}
1146	}
1147	}
1148
1149	#endif /* IN_RING3 */
1150
1151
1152	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
1153
1154	/**
1155	* @callback_method_impl{FNIOMIOPORTOUT, PCI address}
1156	*/
1157	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1158	{
1159	Log(("pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1160	RT_NOREF2(Port, pvUser);
1161	if (cb == 4)
1162	{
1163	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1164	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
1165	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
1166	PCI_UNLOCK(pDevIns);
1167	}
1168	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1169	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1170	return VINF_SUCCESS;
1171	}
1172
1173
1174	/**
1175	* @callback_method_impl{FNIOMIOPORTIN, PCI address}
1176	*/
1177	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1178	{
1179	RT_NOREF2(Port, pvUser);
1180	if (cb == 4)
1181	{
1182	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1183	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
1184	*pu32 = pThis->uConfigReg;
1185	PCI_UNLOCK(pDevIns);
1186	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
1187	return VINF_SUCCESS;
1188	}
1189	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1190	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1191	Log(("pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
1192	return VERR_IOM_IOPORT_UNUSED;
1193	}
1194
1195
1196	/**
1197	* @callback_method_impl{FNIOMIOPORTOUT, PCI data}
1198	*/
1199	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1200	{
1201	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1202	NOREF(pvUser);
1203	int rc = VINF_SUCCESS;
1204	if (!(Port % cb))
1205	{
1206	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
1207	rc = pci_data_write(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
1208	PCI_UNLOCK(pDevIns);
1209	}
1210	else
1211	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
1212	return rc;
1213	}
1214
1215
1216	/**
1217	* @callback_method_impl{FNIOMIOPORTIN, PCI data}
1218	*/
1219	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1220	{
1221	NOREF(pvUser);
1222	if (!(Port % cb))
1223	{
1224	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
1225	int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
1226	PCI_UNLOCK(pDevIns);
1227	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
1228	return rc;
1229	}
1230	AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
1231	return VERR_IOM_IOPORT_UNUSED;
1232	}
1233
1234	#ifdef IN_RING3
1235
1236	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
1237
1238	/**
1239	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
1240	*
1241	* @returns VBox status code.
1242	* @param pBus The bus to save.
1243	* @param pSSM The saved state handle.
1244	*/
1245	static int pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
1246	{
1247	/*
1248	* Iterate thru all the devices.
1249	*/
1250	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1251	{
1252	PPCIDEVICE pDev = pBus->devices[i];
1253	if (pDev)
1254	{
1255	SSMR3PutU32(pSSM, i);
1256	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1257
1258	int rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1259	if (RT_FAILURE(rc))
1260	return rc;
1261	}
1262	}
1263	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1264	}
1265
1266
1267	/**
1268	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1269	*/
1270	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1271	{
1272	uint32_t i;
1273	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1274
1275	/*
1276	* Bus state data.
1277	*/
1278	SSMR3PutU32(pSSM, pThis->uConfigReg);
1279	SSMR3PutBool(pSSM, pThis->fUseIoApic);
1280
1281	/*
1282	* Save IRQ states.
1283	*/
1284	for (i = 0; i < PCI_IRQ_PINS; i++)
1285	SSMR3PutU32(pSSM, pThis->pci_irq_levels[i]);
1286	for (i = 0; i < PCI_APIC_IRQ_PINS; i++)
1287	SSMR3PutU32(pSSM, pThis->pci_apic_irq_levels[i]);
1288
1289	SSMR3PutU32(pSSM, pThis->acpi_irq_level);
1290	SSMR3PutS32(pSSM, pThis->acpi_irq);
1291
1292	SSMR3PutU32(pSSM, UINT32_MAX); /* separator */
1293
1294	/*
1295	* Join paths with pcibridgeR3SaveExec.
1296	*/
1297	return pciR3CommonSaveExec(&pThis->PciBus, pSSM);
1298	}
1299
1300
1301	/**
1302	* Common routine for restoring the config registers of a PCI device.
1303	*
1304	* @param pDev The PCI device.
1305	* @param pbSrcConfig The configuration register values to be loaded.
1306	* @param fIsBridge Whether this is a bridge device or not.
1307	*/
1308	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1309	{
1310	/*
1311	* This table defines the fields for normal devices and bridge devices, and
1312	* the order in which they need to be restored.
1313	*/
1314	static const struct PciField
1315	{
1316	uint8_t off;
1317	uint8_t cb;
1318	uint8_t fWritable;
1319	uint8_t fBridge;
1320	const char *pszName;
1321	} s_aFields[] =
1322	{
1323	/* off,cb,fW,fB, pszName */
1324	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1325	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1326	{ 0x06, 2, 1, 3, "STATUS" },
1327	{ 0x08, 1, 0, 3, "REVISION_ID" },
1328	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1329	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1330	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1331	{ 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },
1332	{ 0x0d, 1, 1, 3, "LATENCY_TIMER" },
1333	{ 0x0e, 1, 0, 3, "HEADER_TYPE" },
1334	{ 0x0f, 1, 1, 3, "BIST" },
1335	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1336	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1337	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1338	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1339	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1340	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1341	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1342	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1343	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1344	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1345	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1346	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1347	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1348	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1349	{ 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1350	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1351	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1352	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1353	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1354	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1355	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1356	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1357	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1358	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1359	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1360	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1361	{ 0x38, 4, 1, 1, "RESERVED_38" }, // ???
1362	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1363	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1364	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1365	{ 0x3e, 1, 0, 1, "MIN_GNT" },
1366	{ 0x3e, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1367	{ 0x3f, 1, 0, 1, "MAX_LAT" },
1368	/* The COMMAND register must come last as it requires the ADDRESS
1369	registers to be restored before we pretent to change it from 0 to
1370	whatever value the guest assigned it. */
1371	{ 0x04, 2, 1, 3, "COMMAND" },
1372	};
1373
1374	#ifdef RT_STRICT
1375	/* Check that we've got full register coverage. */
1376	uint32_t bmDevice[0x40 / 32];
1377	uint32_t bmBridge[0x40 / 32];
1378	RT_ZERO(bmDevice);
1379	RT_ZERO(bmBridge);
1380	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1381	{
1382	uint8_t off = s_aFields[i].off;
1383	uint8_t cb = s_aFields[i].cb;
1384	uint8_t f = s_aFields[i].fBridge;
1385	while (cb-- > 0)
1386	{
1387	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1388	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1389	if (f & 1) ASMBitSet(bmDevice, off);
1390	if (f & 2) ASMBitSet(bmBridge, off);
1391	off++;
1392	}
1393	}
1394	for (uint32_t off = 0; off < 0x40; off++)
1395	{
1396	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1397	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1398	}
1399	#endif
1400
1401	/*
1402	* Loop thru the fields covering the 64 bytes of standard registers.
1403	*/
1404	uint8_t const fBridge = fIsBridge ? 2 : 1;
1405	uint8_t *pbDstConfig = &pDev->config[0];
1406	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1407	if (s_aFields[i].fBridge & fBridge)
1408	{
1409	uint8_t const off = s_aFields[i].off;
1410	uint8_t const cb = s_aFields[i].cb;
1411	uint32_t u32Src;
1412	uint32_t u32Dst;
1413	switch (cb)
1414	{
1415	case 1:
1416	u32Src = pbSrcConfig[off];
1417	u32Dst = pbDstConfig[off];
1418	break;
1419	case 2:
1420	u32Src = (uint16_t const )&pbSrcConfig[off];
1421	u32Dst = (uint16_t const )&pbDstConfig[off];
1422	break;
1423	case 4:
1424	u32Src = (uint32_t const )&pbSrcConfig[off];
1425	u32Dst = (uint32_t const )&pbDstConfig[off];
1426	break;
1427	default:
1428	AssertFailed();
1429	continue;
1430	}
1431
1432	if ( u32Src != u32Dst
1433	\|\| off == VBOX_PCI_COMMAND)
1434	{
1435	if (u32Src != u32Dst)
1436	{
1437	if (!s_aFields[i].fWritable)
1438	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1439	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1440	else
1441	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1442	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1443	}
1444	if (off == VBOX_PCI_COMMAND)
1445	PCIDevSetCommand(pDev, 0); /* For remapping, see pciR3CommonLoadExec. */
1446	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1447	}
1448	}
1449
1450	/*
1451	* The device dependent registers.
1452	*
1453	* We will not use ConfigWrite here as we have no clue about the size
1454	* of the registers, so the device is responsible for correctly
1455	* restoring functionality governed by these registers.
1456	*/
1457	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1458	if (pbDstConfig[off] != pbSrcConfig[off])
1459	{
1460	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1461	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1462	pbDstConfig[off] = pbSrcConfig[off];
1463	}
1464	}
1465
1466
1467	/**
1468	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
1469	*
1470	* @returns VBox status code.
1471	* @param pBus The bus which data is being loaded.
1472	* @param pSSM The saved state handle.
1473	* @param uVersion The data version.
1474	* @param uPass The pass.
1475	*/
1476	static DECLCALLBACK(int) pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1477	{
1478	uint32_t u32;
1479	uint32_t i;
1480	int rc;
1481
1482	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1483
1484	/*
1485	* Iterate thru all the devices and write 0 to the COMMAND register so
1486	* that all the memory is unmapped before we start restoring the saved
1487	* mapping locations.
1488	*
1489	* The register value is restored afterwards so we can do proper
1490	* LogRels in pciR3CommonRestoreConfig.
1491	*/
1492	for (i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1493	{
1494	PPCIDEVICE pDev = pBus->devices[i];
1495	if (pDev)
1496	{
1497	uint16_t u16 = PCIDevGetCommand(pDev);
1498	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1499	PCIDevSetCommand(pDev, u16);
1500	Assert(PCIDevGetCommand(pDev) == u16);
1501	}
1502	}
1503
1504	/*
1505	* Iterate all the devices.
1506	*/
1507	for (i = 0;; i++)
1508	{
1509	PCIDEVICE DevTmp;
1510	PPCIDEVICE pDev;
1511
1512	/* index / terminator */
1513	rc = SSMR3GetU32(pSSM, &u32);
1514	if (RT_FAILURE(rc))
1515	return rc;
1516	if (u32 == (uint32_t)~0)
1517	break;
1518	if ( u32 >= RT_ELEMENTS(pBus->devices)
1519	\|\| u32 < i)
1520	{
1521	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1522	return rc;
1523	}
1524
1525	/* skip forward to the device checking that no new devices are present. */
1526	for (; i < u32; i++)
1527	{
1528	if (pBus->devices[i])
1529	{
1530	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->devices[i]->name,
1531	PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i])));
1532	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1533	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1534	i, pBus->devices[i]->name, PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i]));
1535	}
1536	}
1537
1538	/* get the data */
1539	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1540	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1541	if (uVersion < 3)
1542	{
1543	int32_t i32Temp;
1544	/* Irq value not needed anymore. */
1545	rc = SSMR3GetS32(pSSM, &i32Temp);
1546	if (RT_FAILURE(rc))
1547	return rc;
1548	}
1549	else
1550	{
1551	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1552	if (RT_FAILURE(rc))
1553	return rc;
1554	}
1555
1556	/* check that it's still around. */
1557	pDev = pBus->devices[i];
1558	if (!pDev)
1559	{
1560	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1561	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1562	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1563	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1564	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1565	continue;
1566	}
1567
1568	/* match the vendor id assuming that this will never be changed. */
1569	if ( DevTmp.config[0] != pDev->config[0]
1570	\|\| DevTmp.config[1] != pDev->config[1])
1571	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1572	i, pDev->name, DevTmp.config, pDev->config);
1573
1574	/* commit the loaded device config. */
1575	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1576
1577	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1578	}
1579
1580	return VINF_SUCCESS;
1581	}
1582
1583
1584	/**
1585	* @callback_method_impl{FNSSMDEVLOADEXEC}
1586	*/
1587	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1588	{
1589	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1590	PPCIBUS pBus = &pThis->PciBus;
1591	uint32_t u32;
1592	int rc;
1593
1594	/*
1595	* Check the version.
1596	*/
1597	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1598	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1599	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1600
1601	/*
1602	* Bus state data.
1603	*/
1604	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1605	if (uVersion > 1)
1606	SSMR3GetBool(pSSM, &pThis->fUseIoApic);
1607
1608	/* Load IRQ states. */
1609	if (uVersion > 2)
1610	{
1611	for (uint8_t i = 0; i < PCI_IRQ_PINS; i++)
1612	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_irq_levels[i]);
1613	for (uint8_t i = 0; i < PCI_APIC_IRQ_PINS; i++)
1614	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_apic_irq_levels[i]);
1615
1616	SSMR3GetU32(pSSM, &pThis->acpi_irq_level);
1617	SSMR3GetS32(pSSM, &pThis->acpi_irq);
1618	}
1619
1620	/* separator */
1621	rc = SSMR3GetU32(pSSM, &u32);
1622	if (RT_FAILURE(rc))
1623	return rc;
1624	if (u32 != (uint32_t)~0)
1625	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1626
1627	/*
1628	* The devices.
1629	*/
1630	return pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1631	}
1632
1633
1634	/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
1635
1636	/**
1637	* Registers the device with the specified PCI bus.
1638	*
1639	* @returns VBox status code.
1640	* @param pBus The bus to register with.
1641	* @param iDev The PCI device ordinal.
1642	* @param pPciDev The PCI device structure.
1643	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1644	*/
1645	static int pciR3RegisterDeviceInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1646	{
1647	/*
1648	* Find device slot.
1649	*/
1650	if (iDev < 0)
1651	{
1652	/*
1653	* Special check for the IDE controller which is our function 1 device
1654	* before searching.
1655	*/
1656	if ( !strcmp(pszName, "piix3ide")
1657	&& !pBus->devices[9])
1658	iDev = 9;
1659	/* LPC bus expected to be there by some guests, better make an additional argument to PDM
1660	device helpers, but requires significant rewrite */
1661	else if (!strcmp(pszName, "lpc")
1662	&& !pBus->devices[0xf8])
1663	iDev = 0xf8;
1664	else
1665	{
1666	Assert(!(pBus->iDevSearch % 8));
1667	for (iDev = pBus->iDevSearch; iDev < (int)RT_ELEMENTS(pBus->devices)-7; iDev += 8)
1668	if ( !pBus->devices[iDev]
1669	&& !pBus->devices[iDev + 1]
1670	&& !pBus->devices[iDev + 2]
1671	&& !pBus->devices[iDev + 3]
1672	&& !pBus->devices[iDev + 4]
1673	&& !pBus->devices[iDev + 5]
1674	&& !pBus->devices[iDev + 6]
1675	&& !pBus->devices[iDev + 7])
1676	break;
1677	if (iDev >= (int)RT_ELEMENTS(pBus->devices))
1678	{
1679	AssertMsgFailed(("Couldn't find free spot!\n"));
1680	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1681	}
1682	}
1683	pciDevClearRequestedDevfunc(pPciDev);
1684	}
1685	else
1686	{
1687	/*
1688	* An explicit request.
1689	*
1690	* If the slot is occupied we'll have to relocate the device
1691	* currently occupying it first. This can only be done if the
1692	* existing device wasn't explicitly assigned. Also we limit
1693	* ourselves to function 0 devices.
1694	*
1695	* If you start setting devices + function in the
1696	* config, do it for all pci devices!
1697	*/
1698	//AssertReleaseMsg(iDev > 8 \|\| pBus->iBus != 0, ("iDev=%d pszName=%s\n", iDev, pszName));
1699	if (pBus->devices[iDev])
1700	{
1701	int iDevRel;
1702	AssertReleaseMsg(!(iDev % 8), ("PCI Configuration Conflict! iDev=%d pszName=%s clashes with %s\n",
1703	iDev, pszName, pBus->devices[iDev]->name));
1704	if ( pciDevIsRequestedDevfunc(pBus->devices[iDev])
1705	\|\| (pBus->devices[iDev + 1] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 1]))
1706	\|\| (pBus->devices[iDev + 2] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 2]))
1707	\|\| (pBus->devices[iDev + 3] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 3]))
1708	\|\| (pBus->devices[iDev + 4] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 4]))
1709	\|\| (pBus->devices[iDev + 5] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 5]))
1710	\|\| (pBus->devices[iDev + 6] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 6]))
1711	\|\| (pBus->devices[iDev + 7] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 7])))
1712	{
1713	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1714	pszName, pBus->devices[iDev]->name, iDev));
1715	return VERR_INTERNAL_ERROR;
1716	}
1717
1718	/* Find free slot for the device(s) we're moving and move them. */
1719	for (iDevRel = pBus->iDevSearch; iDevRel < (int)RT_ELEMENTS(pBus->devices)-7; iDevRel += 8)
1720	{
1721	if ( !pBus->devices[iDevRel]
1722	&& !pBus->devices[iDevRel + 1]
1723	&& !pBus->devices[iDevRel + 2]
1724	&& !pBus->devices[iDevRel + 3]
1725	&& !pBus->devices[iDevRel + 4]
1726	&& !pBus->devices[iDevRel + 5]
1727	&& !pBus->devices[iDevRel + 6]
1728	&& !pBus->devices[iDevRel + 7])
1729	{
1730	int i = 0;
1731	for (i = 0; i < 8; i++)
1732	{
1733	if (!pBus->devices[iDev + i])
1734	continue;
1735	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->devices[iDev + i]->name, iDev + i, iDevRel + i));
1736	pBus->devices[iDevRel + i] = pBus->devices[iDev + i];
1737	pBus->devices[iDevRel + i]->devfn = iDevRel + i;
1738	pBus->devices[iDev + i] = NULL;
1739	}
1740	}
1741	}
1742	if (pBus->devices[iDev])
1743	{
1744	AssertMsgFailed(("Couldn't find free spot!\n"));
1745	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1746	}
1747	} /* if conflict */
1748	pciDevSetRequestedDevfunc(pPciDev);
1749	}
1750
1751	Assert(!pBus->devices[iDev]);
1752	pPciDev->devfn = iDev;
1753	pPciDev->name = pszName;
1754	pPciDev->Int.s.pBusR3 = pBus;
1755	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1756	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1757	pPciDev->Int.s.pfnConfigRead = pci_default_read_config;
1758	pPciDev->Int.s.pfnConfigWrite = pci_default_write_config;
1759	pBus->devices[iDev] = pPciDev;
1760	if (pciDevIsPci2PciBridge(pPciDev))
1761	{
1762	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->devices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
1763	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
1764	("device is a bridge but does not implement read/write functions\n"));
1765	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
1766	pBus->cBridges++;
1767	}
1768
1769	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
1770	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
1771
1772	return VINF_SUCCESS;
1773	}
1774
1775
1776	/**
1777	* @interface_method_impl{PDMPCIBUSREG,pfnRegisterR3}
1778	*/
1779	static DECLCALLBACK(int) pciR3Register(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
1780	{
1781	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
1782
1783	/*
1784	* Check input.
1785	*/
1786	if ( !pszName
1787	\|\| !pPciDev
1788	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices)
1789	\|\| (iDev >= 0 && iDev <= 8))
1790	{
1791	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1792	return VERR_INVALID_PARAMETER;
1793	}
1794
1795	/*
1796	* Register the device.
1797	*/
1798	return pciR3RegisterDeviceInternal(pBus, iDev, pPciDev, pszName);
1799	}
1800
1801
1802	/**
1803	* @interface_method_impl{PDMPCIBUSREG,pfnIORegionRegisterR3}
1804	*/
1805	static DECLCALLBACK(int) pciR3CommonIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion,
1806	PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1807	{
1808	NOREF(pDevIns);
1809
1810	/*
1811	* Validate.
1812	*/
1813	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
1814	\|\| enmType == PCI_ADDRESS_SPACE_IO
1815	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
1816	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1817	VERR_INVALID_PARAMETER);
1818	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1819	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1820	VERR_INVALID_PARAMETER);
1821	int iLastSet = ASMBitLastSetU32(cbRegion);
1822	AssertMsgReturn( iLastSet != 0
1823	&& RT_BIT_32(iLastSet - 1) == cbRegion,
1824	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1825	VERR_INVALID_PARAMETER);
1826
1827	/*
1828	* Register the I/O region.
1829	*/
1830	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1831	pRegion->addr = ~0U;
1832	pRegion->size = cbRegion;
1833	pRegion->type = enmType;
1834	pRegion->map_func = pfnCallback;
1835
1836	/* Set type in the config space. */
1837	uint32_t u32Address = 0x10 + iRegion * 4;
1838	uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
1839	\| (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
1840	(uint32_t )(pPciDev->config + u32Address) = RT_H2LE_U32(u32Value);
1841
1842	return VINF_SUCCESS;
1843	}
1844
1845
1846	/**
1847	* @interface_method_impl{PDMPCIBUSREG,pfnSetConfigCallbacksR3}
1848	*/
1849	static DECLCALLBACK(void)
1850	pciR3CommonSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1851	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1852	{
1853	NOREF(pDevIns);
1854
1855	if (ppfnReadOld)
1856	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1857	pPciDev->Int.s.pfnConfigRead = pfnRead;
1858
1859	if (ppfnWriteOld)
1860	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1861	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1862	}
1863
1864
1865	/**
1866	* @interface_method_impl{PDMPCIBUSREG,pfnFakePCIBIOSR3}
1867	*/
1868	static DECLCALLBACK(int) pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
1869	{
1870	unsigned i;
1871	uint8_t elcr[2] = {0, 0};
1872	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1873	PVM pVM = PDMDevHlpGetVM(pDevIns); Assert(pVM);
1874	PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns); Assert(pVM);
1875
1876	/*
1877	* Set the start addresses.
1878	*/
1879	pGlobals->pci_bios_io_addr = 0xd000;
1880	pGlobals->pci_bios_mem_addr = UINT32_C(0xf0000000);
1881	pGlobals->uBus = 0;
1882
1883	/*
1884	* Activate IRQ mappings.
1885	*/
1886	for (i = 0; i < 4; i++)
1887	{
1888	uint8_t irq = pci_irqs[i];
1889	/* Set to trigger level. */
1890	elcr[irq >> 3] \|= (1 << (irq & 7));
1891	/* Activate irq remapping in PIIX3. */
1892	pci_config_writeb(pGlobals, 0, pGlobals->PIIX3State.dev.devfn, 0x60 + i, irq);
1893	}
1894
1895	/* Tell to the PIC. */
1896	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d0, elcr[0], sizeof(uint8_t));
1897	if (rcStrict == VINF_SUCCESS)
1898	rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d1, elcr[1], sizeof(uint8_t));
1899	if (rcStrict != VINF_SUCCESS)
1900	{
1901	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1902	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
1903	}
1904
1905	/*
1906	* Init the devices.
1907	*/
1908	for (i = 0; i < 256; i++)
1909	{
1910	uint8_t aBridgePositions[256];
1911
1912	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1913	Log2(("PCI: Initializing device %d (%#x)\n",
1914	i, 0x80000000 \| (i << 8)));
1915	pci_bios_init_device(pGlobals, 0, i, 0, aBridgePositions);
1916	}
1917
1918	return VINF_SUCCESS;
1919	}
1920
1921
1922	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
1923
1924	/**
1925	* @callback_method_impl{FNDBGFHANDLERDEV}
1926	*/
1927	static DECLCALLBACK(void) pciR3IrqRouteInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1928	{
1929	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1930	NOREF(pszArgs);
1931
1932	uint16_t router = pGlobals->PIIX3State.dev.devfn;
1933	pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1934	router >> 8, (router >> 3) & 0x1f, router & 0x7);
1935
1936	for (int i = 0; i < 4; ++i)
1937	{
1938	uint8_t irq_map = pci_config_readb(pGlobals, 0, router, 0x60 + i);
1939	if (irq_map & 0x80)
1940	pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1941	else
1942	pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1943	}
1944	}
1945
1946	/**
1947	* @callback_method_impl{FNDBGFHANDLERDEV}
1948	*/
1949	static DECLCALLBACK(void) pciR3IrqInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1950	{
1951	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1952	NOREF(pszArgs);
1953
1954	pHlp->pfnPrintf(pHlp, "PCI I/O APIC IRQ levels:\n");
1955	for (int i = 0; i < PCI_APIC_IRQ_PINS; ++i)
1956	{
1957	pHlp->pfnPrintf(pHlp, " IRQ%02d: %u\n", 0x10 + i, pGlobals->pci_apic_irq_levels[i]);
1958	}
1959	}
1960
1961	/**
1962	* Outputs indent.
1963	*
1964	* @param pHlp Output helpers.
1965	* @param iIndent Indentation level.
1966	*/
1967	static void pciR3PrintIndent(PCDBGFINFOHLP pHlp, int iIndent)
1968	{
1969	while (iIndent-- > 0)
1970	pHlp->pfnPrintf(pHlp, " ");
1971	}
1972
1973	/**
1974	* Recursive worker for pciR3Info.
1975	*
1976	* @param pBus The bus to display.
1977	* @param pHlp Output helpers.
1978	* @param iIndent Indentation level.
1979	* @param fRegisters Whether to also display the PCI configuration registers
1980	* of each device on the bus.
1981	*/
1982	static void pciR3BusInfo(PPCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
1983	{
1984	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->devices); iDev++)
1985	{
1986	PPCIDEVICE pPciDev = pBus->devices[iDev];
1987	if (pPciDev != NULL)
1988	{
1989	pciR3PrintIndent(pHlp, iIndent);
1990
1991	/*
1992	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
1993	* as host driver handles real devices interrupts.
1994	*/
1995	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x%s%s",
1996	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
1997	pPciDev->name,
1998	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
1999	PCIDevGetWord(pPciDev, VBOX_PCI_VENDOR_ID), PCIDevGetWord(pPciDev, VBOX_PCI_DEVICE_ID),
2000	pciDevIsMsiCapable(pPciDev) ? " MSI" : "",
2001	pciDevIsMsixCapable(pPciDev) ? " MSI-X" : ""
2002	);
2003	if (PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2004	{
2005	pHlp->pfnPrintf(pHlp, " IRQ%d", PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2006	pHlp->pfnPrintf(pHlp, " (INTA#->IRQ%d)", 0x10 + pci_slot_get_apic_pirq(iDev, 0));
2007	}
2008
2009	pHlp->pfnPrintf(pHlp, "\n");
2010
2011	uint16_t iCmd = PCIDevGetWord(pPciDev, VBOX_PCI_COMMAND);
2012	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
2013	{
2014	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2015	{
2016	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2017	uint64_t iRegionSize = pRegion->size;
2018
2019	if (iRegionSize == 0)
2020	continue;
2021
2022	uint32_t u32Addr = PCIDevGetDWord(pPciDev, PCIDevGetRegionReg(iRegion));
2023	const char * pszDesc;
2024	char szDescBuf[128];
2025
2026	bool f64Bit = !!(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
2027	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2028	{
2029	pszDesc = "IO";
2030	u32Addr &= ~0x3;
2031	}
2032	else
2033	{
2034	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2035	f64Bit ? "64" : "32",
2036	(pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
2037	pszDesc = szDescBuf;
2038	u32Addr &= ~0xf;
2039	}
2040
2041	pciR3PrintIndent(pHlp, iIndent + 2);
2042	pHlp->pfnPrintf(pHlp, "%s region #%d: %x..%x\n",
2043	pszDesc, iRegion, u32Addr, u32Addr+iRegionSize);
2044	if (f64Bit)
2045	iRegion++;
2046	}
2047	}
2048
2049	pciR3PrintIndent(pHlp, iIndent + 2);
2050	uint16_t iStatus = PCIDevGetWord(pPciDev, VBOX_PCI_STATUS);
2051	pHlp->pfnPrintf(pHlp, "Command: %.Rhxs, Status: %.Rhxs\n",
2052	sizeof(uint16_t), &iCmd, sizeof(uint16_t), &iStatus);
2053	pciR3PrintIndent(pHlp, iIndent + 2);
2054	pHlp->pfnPrintf(pHlp, "Bus master: %s\n",
2055	iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2056
2057	if (fRegisters)
2058	{
2059	pciR3PrintIndent(pHlp, iIndent + 2);
2060	pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2061	for (int iReg = 0; iReg < 0x100; )
2062	{
2063	int iPerLine = 0x10;
2064	Assert (0x100 % iPerLine == 0);
2065	pciR3PrintIndent(pHlp, iIndent + 3);
2066
2067	while (iPerLine-- > 0)
2068	{
2069	pHlp->pfnPrintf(pHlp, "%02x ", PCIDevGetByte(pPciDev, iReg++));
2070	}
2071	pHlp->pfnPrintf(pHlp, "\n");
2072	}
2073	}
2074	}
2075	}
2076
2077	if (pBus->cBridges > 0)
2078	{
2079	pciR3PrintIndent(pHlp, iIndent);
2080	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2081	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2082	{
2083	PPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PPCIBUS);
2084	pciR3BusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2085	}
2086	}
2087	}
2088
2089
2090	/**
2091	* @callback_method_impl{FNDBGFHANDLERDEV}
2092	*/
2093	static DECLCALLBACK(void) pciR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2094	{
2095	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2096
2097	if (pszArgs == NULL \|\| !*pszArgs \|\| !strcmp(pszArgs, "basic"))
2098	pciR3BusInfo(pBus, pHlp, 0, false);
2099	else if (!strcmp(pszArgs, "verbose"))
2100	pciR3BusInfo(pBus, pHlp, 0, true);
2101	else
2102	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2103	}
2104
2105
2106	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
2107
2108	/**
2109	* @interface_method_impl{PDMDEVREG,pfnRelocate}
2110	*/
2111	static DECLCALLBACK(void) pciR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2112	{
2113	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2114	PPCIBUS pBus = &pGlobals->PciBus;
2115	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2116
2117	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2118	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2119
2120	/* Relocate RC pointers for the attached pci devices. */
2121	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2122	{
2123	if (pBus->devices[i])
2124	pBus->devices[i]->Int.s.pBusRC += offDelta;
2125	}
2126	}
2127
2128
2129	/**
2130	* @interface_method_impl{PDMDEVREG,pfnReset}
2131	*/
2132	static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
2133	{
2134	pciR3FakePCIBIOS(pDevIns);
2135	}
2136
2137
2138	/**
2139	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2140	*/
2141	static DECLCALLBACK(int) pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2142	{
2143	RT_NOREF1(iInstance);
2144	Assert(iInstance == 0);
2145	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2146
2147	/*
2148	* Validate and read configuration.
2149	*/
2150	if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
2151	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2152
2153	/* query whether we got an IOAPIC */
2154	bool fUseIoApic;
2155	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2156	if (RT_FAILURE(rc))
2157	return PDMDEV_SET_ERROR(pDevIns, rc,
2158	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2159
2160	/* check if RC code is enabled. */
2161	bool fGCEnabled;
2162	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2163	if (RT_FAILURE(rc))
2164	return PDMDEV_SET_ERROR(pDevIns, rc,
2165	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2166
2167	/* check if R0 code is enabled. */
2168	bool fR0Enabled;
2169	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2170	if (RT_FAILURE(rc))
2171	return PDMDEV_SET_ERROR(pDevIns, rc,
2172	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2173	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2174
2175	/*
2176	* Init data and register the PCI bus.
2177	*/
2178	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2179	pGlobals->pci_bios_io_addr = 0xc000;
2180	pGlobals->pci_bios_mem_addr = 0xf0000000;
2181	memset((void *)&pGlobals->pci_irq_levels, 0, sizeof(pGlobals->pci_irq_levels));
2182	pGlobals->fUseIoApic = fUseIoApic;
2183	memset((void *)&pGlobals->pci_apic_irq_levels, 0, sizeof(pGlobals->pci_apic_irq_levels));
2184
2185	pGlobals->pDevInsR3 = pDevIns;
2186	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2187	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2188
2189	pGlobals->PciBus.pDevInsR3 = pDevIns;
2190	pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2191	pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2192	pGlobals->PciBus.papBridgesR3 = (PPCIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE)
2193	* RT_ELEMENTS(pGlobals->PciBus.devices));
2194
2195	PDMPCIBUSREG PciBusReg;
2196	PPCIBUS pBus = &pGlobals->PciBus;
2197	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2198	PciBusReg.pfnRegisterR3 = pciR3Register;
2199	PciBusReg.pfnRegisterMsiR3 = NULL;
2200	PciBusReg.pfnIORegionRegisterR3 = pciR3CommonIORegionRegister;
2201	PciBusReg.pfnSetConfigCallbacksR3 = pciR3CommonSetConfigCallbacks;
2202	PciBusReg.pfnSetIrqR3 = pciSetIrq;
2203	PciBusReg.pfnFakePCIBIOSR3 = pciR3FakePCIBIOS;
2204	PciBusReg.pszSetIrqRC = fGCEnabled ? "pciSetIrq" : NULL;
2205	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
2206	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2207	if (RT_FAILURE(rc))
2208	return PDMDEV_SET_ERROR(pDevIns, rc,
2209	N_("Failed to register ourselves as a PCI Bus"));
2210	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2211	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2212	N_("PCI helper version mismatch; got %#x expected %#x"),
2213	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2214
2215	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2216	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2217
2218	/* Disable default device locking. */
2219	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2220	AssertRCReturn(rc, rc);
2221
2222	/*
2223	* Fill in PCI configs and add them to the bus.
2224	*/
2225	/* i440FX */
2226	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2227	PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
2228	PCIDevSetRevisionId(&pBus->PciDev, 0x02);
2229	PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
2230	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2231	PCIDevSetHeaderType(&pBus->PciDev, 0x00);
2232
2233	pBus->PciDev.pDevIns = pDevIns;
2234	pciDevSetRequestedDevfunc(&pBus->PciDev);
2235	pciR3RegisterDeviceInternal(pBus, 0, &pBus->PciDev, "i440FX");
2236
2237	/* PIIX3 */
2238	PCIDevSetVendorId( &pGlobals->PIIX3State.dev, 0x8086); /* Intel */
2239	PCIDevSetDeviceId( &pGlobals->PIIX3State.dev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
2240	PCIDevSetClassSub( &pGlobals->PIIX3State.dev, 0x01); /* PCI_ISA */
2241	PCIDevSetClassBase( &pGlobals->PIIX3State.dev, 0x06); /* PCI_bridge */
2242	PCIDevSetHeaderType(&pGlobals->PIIX3State.dev, 0x80); /* PCI_multifunction, generic */
2243
2244	pGlobals->PIIX3State.dev.pDevIns = pDevIns;
2245	pciDevSetRequestedDevfunc(&pGlobals->PIIX3State.dev);
2246	pciR3RegisterDeviceInternal(pBus, 8, &pGlobals->PIIX3State.dev, "PIIX3");
2247	pciR3Piix3Reset(&pGlobals->PIIX3State);
2248
2249	pBus->iDevSearch = 16;
2250
2251	/*
2252	* Register I/O ports and save state.
2253	*/
2254	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
2255	if (RT_FAILURE(rc))
2256	return rc;
2257	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
2258	if (RT_FAILURE(rc))
2259	return rc;
2260	if (fGCEnabled)
2261	{
2262	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2263	if (RT_FAILURE(rc))
2264	return rc;
2265	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2266	if (RT_FAILURE(rc))
2267	return rc;
2268	}
2269	if (fR0Enabled)
2270	{
2271	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2272	if (RT_FAILURE(rc))
2273	return rc;
2274	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2275	if (RT_FAILURE(rc))
2276	return rc;
2277	}
2278
2279	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2280	NULL, NULL, NULL,
2281	NULL, pciR3SaveExec, NULL,
2282	NULL, pciR3LoadExec, NULL);
2283	if (RT_FAILURE(rc))
2284	return rc;
2285
2286	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
2287	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
2288	pciR3Info);
2289	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", pciR3IrqInfo);
2290	PDMDevHlpDBGFInfoRegister(pDevIns, "irqroute", "Display PCI IRQ routing. (no arguments)", pciR3IrqRouteInfo);
2291
2292	return VINF_SUCCESS;
2293	}
2294
2295
2296	/**
2297	* The device registration structure.
2298	*/
2299	const PDMDEVREG g_DevicePCI =
2300	{
2301	/* u32Version */
2302	PDM_DEVREG_VERSION,
2303	/* szName */
2304	"pci",
2305	/* szRCMod */
2306	"VBoxDDRC.rc",
2307	/* szR0Mod */
2308	"VBoxDDR0.r0",
2309	/* pszDescription */
2310	"i440FX PCI bridge and PIIX3 ISA bridge.",
2311	/* fFlags */
2312	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2313	/* fClass */
2314	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2315	/* cMaxInstances */
2316	1,
2317	/* cbInstance */
2318	sizeof(PCIGLOBALS),
2319	/* pfnConstruct */
2320	pciR3Construct,
2321	/* pfnDestruct */
2322	NULL,
2323	/* pfnRelocate */
2324	pciR3Relocate,
2325	/* pfnMemSetup */
2326	NULL,
2327	/* pfnPowerOn */
2328	NULL,
2329	/* pfnReset */
2330	pciR3Reset,
2331	/* pfnSuspend */
2332	NULL,
2333	/* pfnResume */
2334	NULL,
2335	/* pfnAttach */
2336	NULL,
2337	/* pfnDetach */
2338	NULL,
2339	/* pfnQueryInterface */
2340	NULL,
2341	/* pfnInitComplete */
2342	NULL,
2343	/* pfnPowerOff */
2344	NULL,
2345	/* pfnSoftReset */
2346	NULL,
2347	/* u32VersionEnd */
2348	PDM_DEVREG_VERSION
2349
2350	};
2351	#endif /* IN_RING3 */
2352
2353
2354
2355	/* -=-=-=-=-=- The PCI bridge specific bits -=-=-=-=-=- */
2356
2357	/**
2358	* @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
2359	*/
2360	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
2361	{
2362	/*
2363	* The PCI-to-PCI bridge specification defines how the interrupt pins
2364	* are routed from the secondary to the primary bus (see chapter 9).
2365	* iIrq gives the interrupt pin the pci device asserted.
2366	* We change iIrq here according to the spec and call the SetIrq function
2367	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
2368	*/
2369	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2370	PPCIDEVICE pPciDevBus = pPciDev;
2371	int iIrqPinBridge = iIrq;
2372	uint8_t uDevFnBridge = 0;
2373
2374	/* Walk the chain until we reach the host bus. */
2375	do
2376	{
2377	uDevFnBridge = pBus->PciDev.devfn;
2378	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
2379
2380	/* Get the parent. */
2381	pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
2382	pPciDevBus = &pBus->PciDev;
2383	} while (pBus->iBus != 0);
2384
2385	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
2386	pciSetIrqInternal(PCIBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
2387	}
2388
2389	#ifdef IN_RING3
2390
2391	/**
2392	* @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
2393	*/
2394	static DECLCALLBACK(void) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
2395	{
2396	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2397
2398	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
2399
2400	/* If the current bus is not the target bus search for the bus which contains the device. */
2401	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2402	{
2403	PPCIDEVICE pBridgeDevice = pciR3FindBridge(pBus, iBus);
2404	if (pBridgeDevice)
2405	{
2406	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
2407	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
2408	}
2409	}
2410	else
2411	{
2412	/* This is the target bus, pass the write to the device. */
2413	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2414	if (pPciDev)
2415	{
2416	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2417	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
2418	}
2419	}
2420	}
2421
2422
2423	/**
2424	* @callback_method_impl{FNPCIBRIDGECONFIGREAD}
2425	*/
2426	static DECLCALLBACK(uint32_t) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
2427	{
2428	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2429	uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
2430
2431	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
2432
2433	/* If the current bus is not the target bus search for the bus which contains the device. */
2434	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2435	{
2436	PPCIDEVICE pBridgeDevice = pciR3FindBridge(pBus, iBus);
2437	if (pBridgeDevice)
2438	{
2439	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
2440	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
2441	}
2442	}
2443	else
2444	{
2445	/* This is the target bus, pass the read to the device. */
2446	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2447	if (pPciDev)
2448	{
2449	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
2450	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2451	}
2452	}
2453
2454	return u32Value;
2455	}
2456
2457
2458	/**
2459	* @callback_method_impl{FNSSMDEVSAVEEXEC}
2460	*/
2461	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2462	{
2463	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2464	return pciR3CommonSaveExec(pThis, pSSM);
2465	}
2466
2467
2468	/**
2469	* @callback_method_impl{FNSSMDEVLOADEXEC}
2470	*/
2471	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2472	{
2473	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2474	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
2475	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2476	return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
2477	}
2478
2479
2480	/**
2481	* @interface_method_impl{PDMPCIBUSREG,pfnRegisterR3}
2482	*/
2483	static DECLCALLBACK(int) pcibridgeR3RegisterDevice(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
2484	{
2485	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2486
2487	/*
2488	* Check input.
2489	*/
2490	if ( !pszName
2491	\|\| !pPciDev
2492	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices))
2493	{
2494	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
2495	return VERR_INVALID_PARAMETER;
2496	}
2497
2498	/*
2499	* Register the device.
2500	*/
2501	return pciR3RegisterDeviceInternal(pBus, iDev, pPciDev, pszName);
2502	}
2503
2504
2505	/**
2506	* @interface_method_impl{PDMDEVREG,pfnReset}
2507	*/
2508	static DECLCALLBACK(void) pcibridgeR3Reset(PPDMDEVINS pDevIns)
2509	{
2510	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2511
2512	/* Reset config space to default values. */
2513	pBus->PciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
2514	pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
2515	pBus->PciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
2516	}
2517
2518
2519	/**
2520	* @interface_method_impl{PDMDEVREG,pfnRelocate}
2521	*/
2522	static DECLCALLBACK(void) pcibridgeR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2523	{
2524	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2525	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2526
2527	/* Relocate RC pointers for the attached pci devices. */
2528	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2529	{
2530	if (pBus->devices[i])
2531	pBus->devices[i]->Int.s.pBusRC += offDelta;
2532	}
2533	}
2534
2535
2536	/**
2537	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2538	*/
2539	static DECLCALLBACK(int) pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2540	{
2541	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2542
2543	/*
2544	* Validate and read configuration.
2545	*/
2546	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2547	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2548
2549	/* check if RC code is enabled. */
2550	bool fGCEnabled;
2551	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2552	if (RT_FAILURE(rc))
2553	return PDMDEV_SET_ERROR(pDevIns, rc,
2554	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2555
2556	/* check if R0 code is enabled. */
2557	bool fR0Enabled;
2558	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2559	if (RT_FAILURE(rc))
2560	return PDMDEV_SET_ERROR(pDevIns, rc,
2561	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2562	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2563
2564	/*
2565	* Init data and register the PCI bus.
2566	*/
2567	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2568	pBus->pDevInsR3 = pDevIns;
2569	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2570	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2571	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->devices));
2572
2573	PDMPCIBUSREG PciBusReg;
2574	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2575	PciBusReg.pfnRegisterR3 = pcibridgeR3RegisterDevice;
2576	PciBusReg.pfnRegisterMsiR3 = NULL;
2577	PciBusReg.pfnIORegionRegisterR3 = pciR3CommonIORegionRegister;
2578	PciBusReg.pfnSetConfigCallbacksR3 = pciR3CommonSetConfigCallbacks;
2579	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
2580	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2581	PciBusReg.pszSetIrqRC = fGCEnabled ? "pcibridgeSetIrq" : NULL;
2582	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pcibridgeSetIrq" : NULL;
2583	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2584	if (RT_FAILURE(rc))
2585	return PDMDEV_SET_ERROR(pDevIns, rc,
2586	N_("Failed to register ourselves as a PCI Bus"));
2587	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2588	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2589	N_("PCI helper version mismatch; got %#x expected %#x"),
2590	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2591
2592	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2593	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2594
2595	/*
2596	* Fill in PCI configs and add them to the bus.
2597	*/
2598	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2599	PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2600	PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
2601	PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
2602	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2603	PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
2604	PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2605	PCIDevSetCommand( &pBus->PciDev, 0x00);
2606	PCIDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
2607	PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
2608
2609	/*
2610	* This device does not generate interrupts. Interrupt delivery from
2611	* devices attached to the bus is unaffected.
2612	*/
2613	PCIDevSetInterruptPin(&pBus->PciDev, 0x00);
2614
2615	pBus->PciDev.pDevIns = pDevIns;
2616
2617	/* Bridge-specific data */
2618	pciDevSetPci2PciBridge(&pBus->PciDev);
2619	pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
2620	pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
2621
2622	/*
2623	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2624	*/
2625	rc = PDMDevHlpPCIRegister(pDevIns, &pBus->PciDev);
2626	if (RT_FAILURE(rc))
2627	return rc;
2628
2629	pBus->iDevSearch = 0;
2630	/*
2631	* The iBus property doesn't really represent the bus number
2632	* because the guest and the BIOS can choose different bus numbers
2633	* for them.
2634	* The bus number is mainly for the setIrq function to indicate
2635	* when the host bus is reached which will have iBus = 0.
2636	* That's why the + 1.
2637	*/
2638	pBus->iBus = iInstance + 1;
2639
2640	/*
2641	* Register SSM handlers. We use the same saved state version as for the host bridge
2642	* to make changes easier.
2643	*/
2644	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2645	NULL, NULL, NULL,
2646	NULL, pcibridgeR3SaveExec, NULL,
2647	NULL, pcibridgeR3LoadExec, NULL);
2648	if (RT_FAILURE(rc))
2649	return rc;
2650
2651	return VINF_SUCCESS;
2652	}
2653
2654
2655	/**
2656	* The device registration structure
2657	* for the PCI-to-PCI bridge.
2658	*/
2659	const PDMDEVREG g_DevicePCIBridge =
2660	{
2661	/* u32Version */
2662	PDM_DEVREG_VERSION,
2663	/* szName */
2664	"pcibridge",
2665	/* szRCMod */
2666	"VBoxDDRC.rc",
2667	/* szR0Mod */
2668	"VBoxDDR0.r0",
2669	/* pszDescription */
2670	"82801 Mobile PCI to PCI bridge",
2671	/* fFlags */
2672	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2673	/* fClass */
2674	PDM_DEVREG_CLASS_BUS_PCI,
2675	/* cMaxInstances */
2676	~0U,
2677	/* cbInstance */
2678	sizeof(PCIBUS),
2679	/* pfnConstruct */
2680	pcibridgeR3Construct,
2681	/* pfnDestruct */
2682	NULL,
2683	/* pfnRelocate */
2684	pcibridgeR3Relocate,
2685	/* pfnMemSetup */
2686	NULL,
2687	/* pfnPowerOn */
2688	NULL,
2689	/* pfnReset */
2690	pcibridgeR3Reset,
2691	/* pfnSuspend */
2692	NULL,
2693	/* pfnResume */
2694	NULL,
2695	/* pfnAttach */
2696	NULL,
2697	/* pfnDetach */
2698	NULL,
2699	/* pfnQueryInterface */
2700	NULL,
2701	/* pfnInitComplete */
2702	NULL,
2703	/* pfnPowerOff */
2704	NULL,
2705	/* pfnSoftReset */
2706	NULL,
2707	/* u32VersionEnd */
2708	PDM_DEVREG_VERSION
2709	};
2710
2711	#endif /* IN_RING3 */
2712	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 63009

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