VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 55394

Last change on this file since 55394 was 52829, checked in by vboxsync, 10 years ago

Removed duplicate line.

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 98.0 KB
Line 
1/* $Id: DevPCI.cpp 52829 2014-09-23 16:12:25Z vboxsync $ */
2/** @file
3 * DevPCI - PCI BUS Device.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 * --------------------------------------------------------------------
17 *
18 * This code is based on:
19 *
20 * QEMU PCI bus manager
21 *
22 * Copyright (c) 2004 Fabrice Bellard
23 *
24 * Permission is hereby granted, free of charge, to any person obtaining a copy
25 * of this software and associated documentation files (the "Software"), to deal
26 * in the Software without restriction, including without limitation the rights
27 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28 * copies of the Software, and to permit persons to whom the Software is
29 * furnished to do so, subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice shall be included in
32 * all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40 * THE SOFTWARE.
41 */
42
43/*******************************************************************************
44* Header Files *
45*******************************************************************************/
46#define LOG_GROUP LOG_GROUP_DEV_PCI
47/* Hack to get PCIDEVICEINT declared at the right point - include "PCIInternal.h". */
48#define PCI_INCLUDE_PRIVATE
49#include <VBox/pci.h>
50#include <VBox/vmm/pdmdev.h>
51#include <iprt/asm.h>
52#include <iprt/assert.h>
53#include <iprt/string.h>
54
55#include "VBoxDD.h"
56
57
58/*******************************************************************************
59* Structures and Typedefs *
60*******************************************************************************/
61/**
62 * PIIX3 ISA Bridge state.
63 */
64typedef struct PIIX3State
65{
66 /** The PCI device of the bridge. */
67 PCIDEVICE dev;
68} PIIX3State, PIIX3, *PPIIX3;
69
70/**
71 * PCI Bus instance.
72 */
73typedef struct PCIBus
74{
75 /** Bus number. */
76 int32_t iBus;
77 /** Start device number. */
78 int32_t iDevSearch;
79 /** Number of bridges attached to the bus. */
80 uint32_t cBridges;
81
82 uint32_t Alignment0;
83
84 /** Array of PCI devices. */
85 R3PTRTYPE(PPCIDEVICE) devices[256];
86 /** Array of bridges attached to the bus. */
87 R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
88
89 /** R3 pointer to the device instance. */
90 PPDMDEVINSR3 pDevInsR3;
91 /** Pointer to the PCI R3 helpers. */
92 PCPDMPCIHLPR3 pPciHlpR3;
93
94 /** R0 pointer to the device instance. */
95 PPDMDEVINSR0 pDevInsR0;
96 /** Pointer to the PCI R0 helpers. */
97 PCPDMPCIHLPR0 pPciHlpR0;
98
99 /** RC pointer to the device instance. */
100 PPDMDEVINSRC pDevInsRC;
101 /** Pointer to the PCI RC helpers. */
102 PCPDMPCIHLPRC pPciHlpRC;
103
104 /** The PCI device for the PCI bridge. */
105 PCIDEVICE PciDev;
106
107} PCIBUS;
108/** Pointer to a PCIBUS instance. */
109typedef PCIBUS *PPCIBUS;
110typedef PCIBUS PCIBus;
111
112/** @def PCI_IRQ_PINS
113 * Number of pins for interrupts (PIRQ#0...PIRQ#3)
114 */
115#define PCI_IRQ_PINS 4
116
117/** @def PCI_APIC_IRQ_PINS
118 * Number of pins for interrupts if the APIC is used.
119 */
120#define PCI_APIC_IRQ_PINS 8
121
122/**
123 * PCI Globals - This is the host-to-pci bridge and the root bus.
124 */
125typedef struct PCIGLOBALS
126{
127 /** Irq levels for the four PCI Irqs.
128 * These count how many devices asserted
129 * the IRQ line. If greater 0 an IRQ is sent to the guest.
130 * If it drops to 0 the IRQ is deasserted.
131 */
132 volatile uint32_t pci_irq_levels[PCI_IRQ_PINS];
133
134#if 1 /* Will be moved into the BIOS soon. */
135 /** The next I/O port address which the PCI BIOS will use. */
136 uint32_t pci_bios_io_addr;
137 /** The next MMIO address which the PCI BIOS will use. */
138 uint32_t pci_bios_mem_addr;
139 /** Actual bus number. */
140 uint8_t uBus;
141#endif
142
143 /** I/O APIC usage flag */
144 bool fUseIoApic;
145 /** I/O APIC irq levels */
146 volatile uint32_t pci_apic_irq_levels[PCI_APIC_IRQ_PINS];
147 /** ACPI IRQ level */
148 uint32_t acpi_irq_level;
149 /** ACPI PIC IRQ */
150 int acpi_irq;
151 /** Config register. */
152 uint32_t uConfigReg;
153
154 /** R3 pointer to the device instance. */
155 PPDMDEVINSR3 pDevInsR3;
156 /** R0 pointer to the device instance. */
157 PPDMDEVINSR0 pDevInsR0;
158 /** RC pointer to the device instance. */
159 PPDMDEVINSRC pDevInsRC;
160
161#if HC_ARCH_BITS == 64
162 uint32_t Alignment0;
163#endif
164
165 /** ISA bridge state. */
166 PIIX3 PIIX3State;
167 /** PCI bus which is attached to the host-to-PCI bridge. */
168 PCIBUS PciBus;
169
170} PCIGLOBALS;
171/** Pointer to per VM data. */
172typedef PCIGLOBALS *PPCIGLOBALS;
173
174
175/*******************************************************************************
176* Defined Constants And Macros *
177*******************************************************************************/
178
179/** Converts a bus instance pointer to a device instance pointer. */
180#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
181/** Converts a PCI bus device instance pointer to a PCIGLOBALS pointer. */
182#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
183/** Converts a PCI bus device instance pointer to a PCIBUS pointer. */
184#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->PciBus))
185
186/** Converts a pointer to a PCI bus instance to a PCIGLOBALS pointer.
187 * @note This works only if the bus number is 0!!!
188 */
189#define PCIBUS_2_PCIGLOBALS(pPciBus) RT_FROM_MEMBER(pPciBus, PCIGLOBALS, PciBus)
190
191/** @def PCI_LOCK
192 * Acquires the PDM lock. This is a NOP if locking is disabled. */
193/** @def PCI_UNLOCK
194 * Releases the PDM lock. This is a NOP if locking is disabled. */
195#define PCI_LOCK(pDevIns, rc) \
196 do { \
197 int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
198 if (rc2 != VINF_SUCCESS) \
199 return rc2; \
200 } while (0)
201#define PCI_UNLOCK(pDevIns) \
202 DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
203
204/** @def VBOX_PCI_SAVED_STATE_VERSION
205 * Saved state version of the PCI bus device.
206 */
207#define VBOX_PCI_SAVED_STATE_VERSION 3
208
209
210#ifndef VBOX_DEVICE_STRUCT_TESTCASE
211/*******************************************************************************
212* Internal Functions *
213*******************************************************************************/
214RT_C_DECLS_BEGIN
215
216PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTag);
217PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTag);
218PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
219PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
220PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
221PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
222
223#ifdef IN_RING3
224DECLINLINE(PPCIDEVICE) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus);
225#endif
226
227RT_C_DECLS_END
228
229#define DEBUG_PCI
230
231#define PCI_VENDOR_ID 0x00 /* 16 bits */
232#define PCI_DEVICE_ID 0x02 /* 16 bits */
233#define PCI_COMMAND 0x04 /* 16 bits */
234#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
235#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
236#define PCI_CLASS_DEVICE 0x0a /* Device class */
237#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
238#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
239#define PCI_MIN_GNT 0x3e /* 8 bits */
240#define PCI_MAX_LAT 0x3f /* 8 bits */
241
242
243#ifdef IN_RING3
244
245static void pci_update_mappings(PCIDevice *d)
246{
247 PPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);
248 PCIIORegion *r;
249 int cmd, i;
250 uint32_t last_addr, new_addr, config_ofs;
251
252 cmd = RT_LE2H_U16(*(uint16_t *)(d->config + PCI_COMMAND));
253 for(i = 0; i < PCI_NUM_REGIONS; i++) {
254 r = &d->Int.s.aIORegions[i];
255 if (i == PCI_ROM_SLOT) {
256 config_ofs = 0x30;
257 } else {
258 config_ofs = 0x10 + i * 4;
259 }
260 if (r->size != 0) {
261 if (r->type & PCI_ADDRESS_SPACE_IO) {
262 if (cmd & PCI_COMMAND_IO) {
263 new_addr = RT_LE2H_U32(*(uint32_t *)(d->config +
264 config_ofs));
265 new_addr = new_addr & ~(r->size - 1);
266 last_addr = new_addr + r->size - 1;
267 /* NOTE: we have only 64K ioports on PC */
268 if (last_addr <= new_addr || new_addr == 0 ||
269 last_addr >= 0x10000) {
270 new_addr = ~0U;
271 }
272 } else {
273 new_addr = ~0U;
274 }
275 } else {
276 if (cmd & PCI_COMMAND_MEMORY) {
277 new_addr = RT_LE2H_U32(*(uint32_t *)(d->config +
278 config_ofs));
279 /* the ROM slot has a specific enable bit */
280 if (i == PCI_ROM_SLOT && !(new_addr & 1))
281 goto no_mem_map;
282 new_addr = new_addr & ~(r->size - 1);
283 last_addr = new_addr + r->size - 1;
284 /* NOTE: we do not support wrapping */
285 /* XXX: as we cannot support really dynamic
286 mappings, we handle specific values as invalid
287 mappings. */
288 if (last_addr <= new_addr || new_addr == 0 ||
289 last_addr == ~0U) {
290 new_addr = ~0U;
291 }
292 } else {
293 no_mem_map:
294 new_addr = ~0U;
295 }
296 }
297 /* now do the real mapping */
298 if (new_addr != r->addr) {
299 if (r->addr != ~0U) {
300 if (r->type & PCI_ADDRESS_SPACE_IO) {
301 int devclass;
302 /* NOTE: specific hack for IDE in PC case:
303 only one byte must be mapped. */
304 devclass = d->config[0x0a] | (d->config[0x0b] << 8);
305 if (devclass == 0x0101 && r->size == 4) {
306 int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr + 2, 1);
307 AssertRC(rc);
308 } else {
309 int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr, r->size);
310 AssertRC(rc);
311 }
312 } else {
313 RTGCPHYS GCPhysBase = r->addr;
314 int rc;
315 if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, d->pDevIns, GCPhysBase))
316 {
317 /* unmap it. */
318 rc = r->map_func(d, i, NIL_RTGCPHYS, r->size, (PCIADDRESSSPACE)(r->type));
319 AssertRC(rc);
320 rc = PDMDevHlpMMIO2Unmap(d->pDevIns, i, GCPhysBase);
321 }
322 else
323 rc = PDMDevHlpMMIODeregister(d->pDevIns, GCPhysBase, r->size);
324 AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, d->name, i, GCPhysBase, r->size));
325 }
326 }
327 r->addr = new_addr;
328 if (r->addr != ~0U) {
329 int rc = r->map_func(d, i,
330 r->addr + (r->type & PCI_ADDRESS_SPACE_IO ? 0 : 0),
331 r->size, (PCIADDRESSSPACE)(r->type));
332 AssertRC(rc);
333 }
334 }
335 }
336 }
337}
338
339
340static DECLCALLBACK(uint32_t) pci_default_read_config(PCIDevice *d, uint32_t address, unsigned len)
341{
342 uint32_t val;
343 switch(len) {
344 case 1:
345 val = d->config[address];
346 break;
347 case 2:
348 val = RT_LE2H_U16(*(uint16_t *)(d->config + address));
349 break;
350 default:
351 case 4:
352 val = RT_LE2H_U32(*(uint32_t *)(d->config + address));
353 break;
354 }
355 return val;
356}
357
358static DECLCALLBACK(void) pci_default_write_config(PCIDevice *d, uint32_t address, uint32_t val, unsigned len)
359{
360 int can_write;
361 unsigned i;
362 uint32_t end, addr;
363
364 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
365 (address >= 0x30 && address < 0x34))) {
366 PCIIORegion *r;
367 int reg;
368
369 if ( address >= 0x30 ) {
370 reg = PCI_ROM_SLOT;
371 }else{
372 reg = (address - 0x10) >> 2;
373 }
374 r = &d->Int.s.aIORegions[reg];
375 if (r->size == 0)
376 goto default_config;
377 /* compute the stored value */
378 if (reg == PCI_ROM_SLOT) {
379 /* keep ROM enable bit */
380 val &= (~(r->size - 1)) | 1;
381 } else {
382 val &= ~(r->size - 1);
383 val |= r->type;
384 }
385 *(uint32_t *)(d->config + address) = RT_H2LE_U32(val);
386 pci_update_mappings(d);
387 return;
388 }
389 default_config:
390 /* not efficient, but simple */
391 addr = address;
392 for(i = 0; i < len; i++) {
393 /* default read/write accesses */
394 switch(d->config[0x0e]) {
395 case 0x00: /* normal device */
396 case 0x80: /* multi-function device */
397 switch(addr) {
398 case 0x00:
399 case 0x01:
400 case 0x02:
401 case 0x03:
402 case 0x08:
403 case 0x09:
404 case 0x0a:
405 case 0x0b:
406 case 0x0e:
407 case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: /* base */
408 case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
409 case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
410 case 0x2c: case 0x2d: /* subsystem ID */
411 case 0x2e: case 0x2f: /* vendor ID */
412 case 0x30: case 0x31: case 0x32: case 0x33: /* rom */
413 case 0x34: /* Capabilities pointer. */
414 case 0x3d: /* Interrupt pin. */
415 can_write = 0;
416 break;
417 default:
418 can_write = 1;
419 break;
420 }
421 break;
422 default:
423 case 0x01: /* bridge */
424 switch(addr) {
425 case 0x00:
426 case 0x01:
427 case 0x02:
428 case 0x03:
429 case 0x08:
430 case 0x09:
431 case 0x0a:
432 case 0x0b:
433 case 0x0e:
434 case 0x38: case 0x39: case 0x3a: case 0x3b: /* rom */
435 case 0x3d:
436 can_write = 0;
437 break;
438 default:
439 can_write = 1;
440 break;
441 }
442 break;
443 }
444#ifdef VBOX
445 if (addr == 0x05) /* Command register, bits 8-15. */
446 {
447 /* don't change reserved bits (11-15) */
448 val &= UINT32_C(~0xf8);
449 d->config[addr] = val;
450 }
451 else if (addr == 0x06) /* Status register, bits 0-7. */
452 {
453 /* don't change read-only bits => actually all lower bits are read-only */
454 val &= UINT32_C(~0xff);
455 /* status register, low part: clear bits by writing a '1' to the corresponding bit */
456 d->config[addr] &= ~val;
457 }
458 else if (addr == 0x07) /* Status register, bits 8-15. */
459 {
460 /* don't change read-only bits */
461 val &= UINT32_C(~0x06);
462 /* status register, high part: clear bits by writing a '1' to the corresponding bit */
463 d->config[addr] &= ~val;
464 }
465 else
466#endif
467 if (can_write) {
468 d->config[addr] = val;
469 }
470 addr++;
471 val >>= 8;
472 }
473
474 end = address + len;
475 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
476 /* if the command register is modified, we must modify the mappings */
477 pci_update_mappings(d);
478 }
479}
480
481#endif /* IN_RING3 */
482
483static int pci_data_write(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
484{
485 uint8_t iBus, iDevice;
486 uint32_t config_addr;
487
488 Log(("pci_data_write: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
489
490 if (!(pGlobals->uConfigReg & (1 << 31))) {
491 return VINF_SUCCESS;
492 }
493 if ((pGlobals->uConfigReg & 0x3) != 0) {
494 return VINF_SUCCESS;
495 }
496 iBus = (pGlobals->uConfigReg >> 16) & 0xff;
497 iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
498 config_addr = (pGlobals->uConfigReg & 0xfc) | (addr & 3);
499 if (iBus != 0)
500 {
501 if (pGlobals->PciBus.cBridges)
502 {
503#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
504 PPCIDEVICE pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
505 if (pBridgeDevice)
506 {
507 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
508 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, val, len);
509 }
510#else
511 return VINF_IOM_R3_IOPORT_WRITE;
512#endif
513 }
514 }
515 else
516 {
517 R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
518 if (pci_dev)
519 {
520#ifdef IN_RING3
521 Log(("pci_config_write: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
522 pci_dev->Int.s.pfnConfigWrite(pci_dev, config_addr, val, len);
523#else
524 return VINF_IOM_R3_IOPORT_WRITE;
525#endif
526 }
527 }
528 return VINF_SUCCESS;
529}
530
531static int pci_data_read(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
532{
533 uint8_t iBus, iDevice;
534 uint32_t config_addr;
535
536 *pu32 = 0xffffffff;
537
538 if (!(pGlobals->uConfigReg & (1 << 31)))
539 return VINF_SUCCESS;
540 if ((pGlobals->uConfigReg & 0x3) != 0)
541 return VINF_SUCCESS;
542 iBus = (pGlobals->uConfigReg >> 16) & 0xff;
543 iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
544 config_addr = (pGlobals->uConfigReg & 0xfc) | (addr & 3);
545 if (iBus != 0)
546 {
547 if (pGlobals->PciBus.cBridges)
548 {
549#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
550 PPCIDEVICE pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
551 if (pBridgeDevice)
552 {
553 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
554 *pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, len);
555 }
556#else
557 NOREF(len);
558 return VINF_IOM_R3_IOPORT_READ;
559#endif
560 }
561 }
562 else
563 {
564 R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
565 if (pci_dev)
566 {
567#ifdef IN_RING3
568 *pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev, config_addr, len);
569 Log(("pci_config_read: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, *pu32, len));
570#else
571 NOREF(len);
572 return VINF_IOM_R3_IOPORT_READ;
573#endif
574 }
575 }
576
577 return VINF_SUCCESS;
578}
579
580
581
582/* return the global irq number corresponding to a given device irq
583 pin. We could also use the bus number to have a more precise
584 mapping.
585 This is the implementation note described in the PCI spec chapter 2.2.6 */
586static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
587{
588 int slot_addend;
589 slot_addend = (uDevFn >> 3) - 1;
590 return (irq_num + slot_addend) & 3;
591}
592
593static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
594{
595 return (irq_num + (uDevFn >> 3)) & 7;
596}
597
598static inline int get_pci_irq_apic_level(PPCIGLOBALS pGlobals, int irq_num)
599{
600 return (pGlobals->pci_apic_irq_levels[irq_num] != 0);
601}
602
603static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int acpi_irq, uint32_t uTagSrc)
604{
605 /* This is only allowed to be called with a pointer to the host bus. */
606 AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
607
608 if (acpi_irq == -1) {
609 int apic_irq, apic_level;
610 PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pBus);
611 int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
612
613 if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
614 ASMAtomicIncU32(&pGlobals->pci_apic_irq_levels[irq_num]);
615 else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
616 ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
617
618 apic_irq = irq_num + 0x10;
619 apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
620 Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
621 R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
622 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
623
624 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
625 ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
626 pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
627 apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
628 Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
629 R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
630 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
631 }
632 } else {
633 Log3(("apic_set_irq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
634 R3STRING(pPciDev->name), irq_num1, iLevel, acpi_irq));
635 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), acpi_irq, iLevel, uTagSrc);
636 }
637}
638
639DECLINLINE(int) get_pci_irq_level(PPCIGLOBALS pGlobals, int irq_num)
640{
641 return (pGlobals->pci_irq_levels[irq_num] != 0);
642}
643
644/**
645 * Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
646 *
647 * @param pDevIns Device instance of the host PCI Bus.
648 * @param uDevFn The device number on the host bus which will raise the IRQ
649 * @param pPciDev The PCI device structure which raised the interrupt.
650 * @param iIrq IRQ number to set.
651 * @param iLevel IRQ level.
652 * @param uTagSrc The IRQ tag and source ID (for tracing).
653 * @remark uDevFn and pPciDev->devfn are not the same if the device is behind a bridge.
654 * In that case uDevFn will be the slot of the bridge which is needed to calculate the
655 * PIRQ value.
656 */
657static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
658{
659 PPCIBUS pBus = &pGlobals->PciBus;
660 uint8_t *pbCfg = pGlobals->PIIX3State.dev.config;
661 const bool fIsAcpiDevice = pPciDev->config[2] == 0x13 && pPciDev->config[3] == 0x71;
662 /* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
663 * is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
664 * See the \_SB_.PCI0._PRT method in vbox.dsl.
665 */
666 const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
667 int pic_irq, pic_level;
668
669 /* Check if the state changed. */
670 if (pPciDev->Int.s.uIrqPinState != iLevel)
671 {
672 pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
673
674 /* Send interrupt to I/O APIC only. */
675 if (fIsApicEnabled)
676 {
677 if (fIsAcpiDevice)
678 /*
679 * ACPI needs special treatment since SCI is hardwired and
680 * should not be affected by PCI IRQ routing tables at the
681 * same time SCI IRQ is shared in PCI sense hence this
682 * kludge (i.e. we fetch the hardwired value from ACPIs
683 * PCI device configuration space).
684 */
685 apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->config[PCI_INTERRUPT_LINE], uTagSrc);
686 else
687 apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
688 return;
689 }
690
691 if (fIsAcpiDevice)
692 {
693 /* As per above treat ACPI in a special way */
694 pic_irq = pPciDev->config[PCI_INTERRUPT_LINE];
695 pGlobals->acpi_irq = pic_irq;
696 pGlobals->acpi_irq_level = iLevel & PDM_IRQ_LEVEL_HIGH;
697 }
698 else
699 {
700 int irq_num;
701 irq_num = pci_slot_get_pirq(uDevFn, iIrq);
702
703 if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
704 ASMAtomicIncU32(&pGlobals->pci_irq_levels[irq_num]);
705 else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
706 ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
707
708 /* now we change the pic irq level according to the piix irq mappings */
709 pic_irq = pbCfg[0x60 + irq_num];
710 if (pic_irq >= 16)
711 {
712 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
713 {
714 ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
715 pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
716 }
717
718 return;
719 }
720 }
721
722 /* the pic level is the logical OR of all the PCI irqs mapped to it */
723 pic_level = 0;
724 if (pic_irq == pbCfg[0x60])
725 pic_level |= get_pci_irq_level(pGlobals, 0);
726 if (pic_irq == pbCfg[0x61])
727 pic_level |= get_pci_irq_level(pGlobals, 1);
728 if (pic_irq == pbCfg[0x62])
729 pic_level |= get_pci_irq_level(pGlobals, 2);
730 if (pic_irq == pbCfg[0x63])
731 pic_level |= get_pci_irq_level(pGlobals, 3);
732 if (pic_irq == pGlobals->acpi_irq)
733 pic_level |= pGlobals->acpi_irq_level;
734
735 Log3(("pciSetIrq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
736 R3STRING(pPciDev->name), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
737 pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level, uTagSrc);
738
739 /** @todo optimize pci irq flip-flop some rainy day. */
740 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
741 pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
742 }
743}
744
745
746/**
747 * @interface_method_impl{PDMPCIBUSREG,pfnSetIrq}
748 */
749PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
750{
751 pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc);
752}
753
754#ifdef IN_RING3
755
756/**
757 * Finds a bridge on the bus which contains the destination bus.
758 *
759 * @return Pointer to the device instance data of the bus or
760 * NULL if no bridge was found.
761 * @param pBus Pointer to the bus to search on.
762 * @param iBus Destination bus number.
763 */
764DECLINLINE(PPCIDEVICE) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus)
765{
766 /* Search for a fitting bridge. */
767 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
768 {
769 /*
770 * Examine secondary and subordinate bus number.
771 * If the target bus is in the range we pass the request on to the bridge.
772 */
773 PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
774 AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
775 ("Device is not a PCI bridge but on the list of PCI bridges\n"));
776
777 if ( iBus >= pBridgeTemp->config[VBOX_PCI_SECONDARY_BUS]
778 && iBus <= pBridgeTemp->config[VBOX_PCI_SUBORDINATE_BUS])
779 return pBridgeTemp;
780 }
781
782 /* Nothing found. */
783 return NULL;
784}
785
786static void pciR3Piix3Reset(PIIX3State *d)
787{
788 uint8_t *pci_conf = d->dev.config;
789
790 pci_conf[0x04] = 0x07; /* master, memory and I/O */
791 pci_conf[0x05] = 0x00;
792 pci_conf[0x06] = 0x00;
793 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
794 pci_conf[0x4c] = 0x4d;
795 pci_conf[0x4e] = 0x03;
796 pci_conf[0x4f] = 0x00;
797 pci_conf[0x60] = 0x80;
798 pci_conf[0x69] = 0x02;
799 pci_conf[0x70] = 0x80;
800 pci_conf[0x76] = 0x0c;
801 pci_conf[0x77] = 0x0c;
802 pci_conf[0x78] = 0x02;
803 pci_conf[0x79] = 0x00;
804 pci_conf[0x80] = 0x00;
805 pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
806 pci_conf[0xa0] = 0x08;
807 pci_conf[0xa2] = 0x00;
808 pci_conf[0xa3] = 0x00;
809 pci_conf[0xa4] = 0x00;
810 pci_conf[0xa5] = 0x00;
811 pci_conf[0xa6] = 0x00;
812 pci_conf[0xa7] = 0x00;
813 pci_conf[0xa8] = 0x0f;
814 pci_conf[0xaa] = 0x00;
815 pci_conf[0xab] = 0x00;
816 pci_conf[0xac] = 0x00;
817 pci_conf[0xae] = 0x00;
818}
819
820static void pci_config_writel(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
821{
822 pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
823 (uDevFn << 8) | addr;
824 pci_data_write(pGlobals, 0, val, 4);
825}
826
827static void pci_config_writew(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
828{
829 pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
830 (uDevFn << 8) | (addr & ~3);
831 pci_data_write(pGlobals, addr & 3, val, 2);
832}
833
834static void pci_config_writeb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
835{
836 pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
837 (uDevFn << 8) | (addr & ~3);
838 pci_data_write(pGlobals, addr & 3, val, 1);
839}
840
841static uint32_t pci_config_readl(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
842{
843 pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
844 (uDevFn << 8) | addr;
845 uint32_t u32Val;
846 int rc = pci_data_read(pGlobals, 0, 4, &u32Val);
847 AssertRC(rc);
848 return u32Val;
849}
850
851static uint32_t pci_config_readw(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
852{
853 pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
854 (uDevFn << 8) | (addr & ~3);
855 uint32_t u32Val;
856 int rc = pci_data_read(pGlobals, addr & 3, 2, &u32Val);
857 AssertRC(rc);
858 return u32Val;
859}
860
861static uint32_t pci_config_readb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
862{
863 pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
864 (uDevFn << 8) | (addr & ~3);
865 uint32_t u32Val;
866 int rc = pci_data_read(pGlobals, addr & 3, 1, &u32Val);
867 AssertRC(rc);
868 return u32Val;
869}
870
871/* host irqs corresponding to PCI irqs A-D */
872static const uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; /* bird: added const */
873
874static void pci_set_io_region_addr(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int region_num, uint32_t addr)
875{
876 uint16_t cmd;
877 uint32_t ofs;
878
879 if ( region_num == PCI_ROM_SLOT )
880 ofs = 0x30;
881 else
882 ofs = 0x10 + region_num * 4;
883
884 /* Read memory type first. */
885 uint8_t uRessourceType = pci_config_readb(pGlobals, uBus, uDevFn, ofs);
886
887 /* Read command register. */
888 cmd = pci_config_readw(pGlobals, uBus, uDevFn, PCI_COMMAND);
889 if ( region_num == PCI_ROM_SLOT )
890 cmd |= 2;
891 else if ((uRessourceType & 0x01) == 1) /* Test if region is I/O space. */
892 cmd |= 1; /* Enable I/O space access. */
893 else /* The region is MMIO. */
894 cmd |= 2; /* Enable MMIO access. */
895
896 /* Write address of the device. */
897 pci_config_writel(pGlobals, uBus, uDevFn, ofs, addr);
898
899 /* enable memory mappings */
900 pci_config_writew(pGlobals, uBus, uDevFn, PCI_COMMAND, cmd);
901}
902
903static void pci_bios_init_device(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
904{
905 uint32_t *paddr;
906 int i, pin, pic_irq;
907 uint16_t devclass, vendor_id, device_id;
908
909 devclass = pci_config_readw(pGlobals, uBus, uDevFn, PCI_CLASS_DEVICE);
910 vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
911 device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
912
913 /* Check if device is present. */
914 if (vendor_id != 0xffff)
915 {
916 switch(devclass)
917 {
918 case 0x0101:
919 if ( (vendor_id == 0x8086)
920 && (device_id == 0x7010 || device_id == 0x7111 || device_id == 0x269e))
921 {
922 /* PIIX3, PIIX4 or ICH6 IDE */
923 pci_config_writew(pGlobals, uBus, uDevFn, 0x40, 0x8000); /* enable IDE0 */
924 pci_config_writew(pGlobals, uBus, uDevFn, 0x42, 0x8000); /* enable IDE1 */
925 goto default_map;
926 }
927 else
928 {
929 /* IDE: we map it as in ISA mode */
930 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x1f0);
931 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 1, 0x3f4);
932 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 2, 0x170);
933 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 3, 0x374);
934 }
935 break;
936 case 0x0300:
937 if (vendor_id != 0x80ee)
938 goto default_map;
939 /* VGA: map frame buffer to default Bochs VBE address */
940 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0xE0000000);
941 /*
942 * Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
943 * only the framebuffer (i.e., a memory region) is explicitly registered via
944 * pci_set_io_region_addr, so I/O decoding must be enabled manually.
945 */
946 pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
947 pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
948 | 1 /* Enable I/O space access. */);
949 break;
950 case 0x0800:
951 /* PIC */
952 vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
953 device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
954 if (vendor_id == 0x1014)
955 {
956 /* IBM */
957 if (device_id == 0x0046 || device_id == 0xFFFF)
958 {
959 /* MPIC & MPIC2 */
960 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
961 }
962 }
963 break;
964 case 0xff00:
965 if ( (vendor_id == 0x0106b)
966 && (device_id == 0x0017 || device_id == 0x0022))
967 {
968 /* macio bridge */
969 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000);
970 }
971 break;
972 case 0x0604:
973 {
974 /* Init PCI-to-PCI bridge. */
975 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus);
976
977 AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
978 pGlobals->uBus++;
979 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
980 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
981
982 /* Add position of this bridge into the array. */
983 paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
984
985 /*
986 * The I/O range for the bridge must be aligned to a 4KB boundary.
987 * This does not change anything really as the access to the device is not going
988 * through the bridge but we want to be compliant to the spec.
989 */
990 if ((pGlobals->pci_bios_io_addr % 4096) != 0)
991 pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
992 Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_io_addr));
993 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->pci_bios_io_addr >> 8) & 0xf0);
994
995 /* The MMIO range for the bridge must be aligned to a 1MB boundary. */
996 if ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0)
997 pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
998 Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_mem_addr));
999 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xffff0));
1000
1001 /* Save values to compare later to. */
1002 uint32_t u32IoAddressBase = pGlobals->pci_bios_io_addr;
1003 uint32_t u32MMIOAddressBase = pGlobals->pci_bios_mem_addr;
1004
1005 /* Init devices behind the bridge and possibly other bridges as well. */
1006 for (int iDev = 0; iDev <= 255; iDev++)
1007 pci_bios_init_device(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1008
1009 /* The number of bridges behind the this one is now available. */
1010 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1011
1012 /*
1013 * Set I/O limit register. If there is no device with I/O space behind the bridge
1014 * we set a lower value than in the base register.
1015 * The result with a real bridge is that no I/O transactions are passed to the secondary
1016 * interface. Again this doesn't really matter here but we want to be compliant to the spec.
1017 */
1018 if ((u32IoAddressBase != pGlobals->pci_bios_io_addr) && ((pGlobals->pci_bios_io_addr % 4096) != 0))
1019 {
1020 /* The upper boundary must be one byte less than a 4KB boundary. */
1021 pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
1022 }
1023 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->pci_bios_io_addr >> 8) & 0xf0) - 1);
1024
1025 /* Same with the MMIO limit register but with 1MB boundary here. */
1026 if ((u32MMIOAddressBase != pGlobals->pci_bios_mem_addr) && ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0))
1027 {
1028 /* The upper boundary must be one byte less than a 1MB boundary. */
1029 pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1030 }
1031 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xfff0)) - 1);
1032
1033 /*
1034 * Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1035 * which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1036 * the base register than in the limit register.
1037 */
1038 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
1039 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
1040 pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
1041 pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
1042 break;
1043 }
1044 default:
1045 default_map:
1046 {
1047 /* default memory mappings */
1048 /*
1049 * PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
1050 * Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
1051 */
1052 for(i = 0; i < (PCI_NUM_REGIONS-1); i++)
1053 {
1054 uint32_t u32Size;
1055 uint8_t u8RessourceType;
1056 uint32_t u32Address = 0x10 + i * 4;
1057
1058 /* Calculate size. */
1059 u8RessourceType = pci_config_readb(pGlobals, uBus, uDevFn, u32Address);
1060 pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff));
1061 u32Size = pci_config_readl(pGlobals, uBus, uDevFn, u32Address);
1062 /* Clear resource information depending on resource type. */
1063 if ((u8RessourceType & 0x01) == 1) /* I/O */
1064 u32Size &= ~(0x01);
1065 else /* MMIO */
1066 u32Size &= ~(0x0f);
1067
1068 /*
1069 * Invert all bits and add 1 to get size of the region.
1070 * (From PCI implementation note)
1071 */
1072 if (((u8RessourceType & 0x01) == 1) && (u32Size & UINT32_C(0xffff0000)) == 0)
1073 u32Size = (~(u32Size | UINT32_C(0xffff0000))) + 1;
1074 else
1075 u32Size = (~u32Size) + 1;
1076
1077 Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, i, uDevFn, uBus, u32Size));
1078
1079 if (u32Size)
1080 {
1081 if ((u8RessourceType & 0x01) == 1)
1082 paddr = &pGlobals->pci_bios_io_addr;
1083 else
1084 paddr = &pGlobals->pci_bios_mem_addr;
1085 *paddr = (*paddr + u32Size - 1) & ~(u32Size - 1);
1086 Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, ((u8RessourceType & 0x01) == 1 ? "I/O" : "MMIO"), i, *paddr));
1087 pci_set_io_region_addr(pGlobals, uBus, uDevFn, i, *paddr);
1088 *paddr += u32Size;
1089 Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1090 }
1091 }
1092 break;
1093 }
1094 }
1095
1096 /* map the interrupt */
1097 pin = pci_config_readb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_PIN);
1098 if (pin != 0)
1099 {
1100 uint8_t uBridgeDevFn = uDevFn;
1101 pin--;
1102
1103 /* We need to go up to the host bus to see which irq this device will assert there. */
1104 while (cBridgeDepth != 0)
1105 {
1106 /* Get the pin the device would assert on the bridge. */
1107 pin = ((uBridgeDevFn >> 3) + pin) & 3;
1108 uBridgeDevFn = paBridgePositions[cBridgeDepth];
1109 cBridgeDepth--;
1110 }
1111
1112 pin = pci_slot_get_pirq(uDevFn, pin);
1113 pic_irq = pci_irqs[pin];
1114 pci_config_writeb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
1115 }
1116 }
1117}
1118
1119#endif /* IN_RING3 */
1120
1121
1122/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
1123
1124/**
1125 * @callback_method_impl{FNIOMIOPORTOUT, PCI address}
1126 */
1127PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1128{
1129 Log(("pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1130 NOREF(pvUser);
1131 if (cb == 4)
1132 {
1133 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1134 PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
1135 pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
1136 PCI_UNLOCK(pDevIns);
1137 }
1138 /* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1139 * Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1140 return VINF_SUCCESS;
1141}
1142
1143
1144/**
1145 * @callback_method_impl{FNIOMIOPORTIN, PCI address}
1146 */
1147PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1148{
1149 NOREF(pvUser);
1150 if (cb == 4)
1151 {
1152 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1153 PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
1154 *pu32 = pThis->uConfigReg;
1155 PCI_UNLOCK(pDevIns);
1156 Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
1157 return VINF_SUCCESS;
1158 }
1159 /* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1160 * Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1161 Log(("pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
1162 return VERR_IOM_IOPORT_UNUSED;
1163}
1164
1165
1166/**
1167 * @callback_method_impl{FNIOMIOPORTOUT, PCI data}
1168 */
1169PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1170{
1171 Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1172 NOREF(pvUser);
1173 int rc = VINF_SUCCESS;
1174 if (!(Port % cb))
1175 {
1176 PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
1177 rc = pci_data_write(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
1178 PCI_UNLOCK(pDevIns);
1179 }
1180 else
1181 AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
1182 return rc;
1183}
1184
1185
1186/**
1187 * @callback_method_impl{FNIOMIOPORTIN, PCI data}
1188 */
1189PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1190{
1191 NOREF(pvUser);
1192 if (!(Port % cb))
1193 {
1194 PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
1195 int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
1196 PCI_UNLOCK(pDevIns);
1197 Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
1198 return rc;
1199 }
1200 AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
1201 return VERR_IOM_IOPORT_UNUSED;
1202}
1203
1204#ifdef IN_RING3
1205
1206/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
1207
1208/**
1209 * Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
1210 *
1211 * @returns VBox status code.
1212 * @param pBus The bus to save.
1213 * @param pSSM The saved state handle.
1214 */
1215static int pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
1216{
1217 /*
1218 * Iterate thru all the devices.
1219 */
1220 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1221 {
1222 PPCIDEVICE pDev = pBus->devices[i];
1223 if (pDev)
1224 {
1225 SSMR3PutU32(pSSM, i);
1226 SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1227
1228 int rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1229 if (RT_FAILURE(rc))
1230 return rc;
1231 }
1232 }
1233 return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1234}
1235
1236
1237/**
1238 * @callback_method_impl{FNSSMDEVSAVEEXEC}
1239 */
1240static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1241{
1242 uint32_t i;
1243 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1244
1245 /*
1246 * Bus state data.
1247 */
1248 SSMR3PutU32(pSSM, pThis->uConfigReg);
1249 SSMR3PutBool(pSSM, pThis->fUseIoApic);
1250
1251 /*
1252 * Save IRQ states.
1253 */
1254 for (i = 0; i < PCI_IRQ_PINS; i++)
1255 SSMR3PutU32(pSSM, pThis->pci_irq_levels[i]);
1256 for (i = 0; i < PCI_APIC_IRQ_PINS; i++)
1257 SSMR3PutU32(pSSM, pThis->pci_apic_irq_levels[i]);
1258
1259 SSMR3PutU32(pSSM, pThis->acpi_irq_level);
1260 SSMR3PutS32(pSSM, pThis->acpi_irq);
1261
1262 SSMR3PutU32(pSSM, ~0); /* separator */
1263
1264 /*
1265 * Join paths with pcibridgeR3SaveExec.
1266 */
1267 return pciR3CommonSaveExec(&pThis->PciBus, pSSM);
1268}
1269
1270
1271/**
1272 * Common routine for restoring the config registers of a PCI device.
1273 *
1274 * @param pDev The PCI device.
1275 * @param pbSrcConfig The configuration register values to be loaded.
1276 * @param fIsBridge Whether this is a bridge device or not.
1277 */
1278static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1279{
1280 /*
1281 * This table defines the fields for normal devices and bridge devices, and
1282 * the order in which they need to be restored.
1283 */
1284 static const struct PciField
1285 {
1286 uint8_t off;
1287 uint8_t cb;
1288 uint8_t fWritable;
1289 uint8_t fBridge;
1290 const char *pszName;
1291 } s_aFields[] =
1292 {
1293 /* off,cb,fW,fB, pszName */
1294 { 0x00, 2, 0, 3, "VENDOR_ID" },
1295 { 0x02, 2, 0, 3, "DEVICE_ID" },
1296 { 0x06, 2, 1, 3, "STATUS" },
1297 { 0x08, 1, 0, 3, "REVISION_ID" },
1298 { 0x09, 1, 0, 3, "CLASS_PROG" },
1299 { 0x0a, 1, 0, 3, "CLASS_SUB" },
1300 { 0x0b, 1, 0, 3, "CLASS_BASE" },
1301 { 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },
1302 { 0x0d, 1, 1, 3, "LATENCY_TIMER" },
1303 { 0x0e, 1, 0, 3, "HEADER_TYPE" },
1304 { 0x0f, 1, 1, 3, "BIST" },
1305 { 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1306 { 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1307 { 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1308 { 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1309 { 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1310 { 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1311 { 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1312 { 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1313 { 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1314 { 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1315 { 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1316 { 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1317 { 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1318 { 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1319 { 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1320 { 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1321 { 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1322 { 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1323 { 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1324 { 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1325 { 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1326 { 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1327 { 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1328 { 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1329 { 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1330 { 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1331 { 0x38, 4, 1, 1, "RESERVED_38" }, // ???
1332 { 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1333 { 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1334 { 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1335 { 0x3e, 1, 0, 1, "MIN_GNT" },
1336 { 0x3e, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1337 { 0x3f, 1, 0, 1, "MAX_LAT" },
1338 /* The COMMAND register must come last as it requires the *ADDRESS*
1339 registers to be restored before we pretent to change it from 0 to
1340 whatever value the guest assigned it. */
1341 { 0x04, 2, 1, 3, "COMMAND" },
1342 };
1343
1344#ifdef RT_STRICT
1345 /* Check that we've got full register coverage. */
1346 uint32_t bmDevice[0x40 / 32];
1347 uint32_t bmBridge[0x40 / 32];
1348 RT_ZERO(bmDevice);
1349 RT_ZERO(bmBridge);
1350 for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1351 {
1352 uint8_t off = s_aFields[i].off;
1353 uint8_t cb = s_aFields[i].cb;
1354 uint8_t f = s_aFields[i].fBridge;
1355 while (cb-- > 0)
1356 {
1357 if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1358 if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1359 if (f & 1) ASMBitSet(bmDevice, off);
1360 if (f & 2) ASMBitSet(bmBridge, off);
1361 off++;
1362 }
1363 }
1364 for (uint32_t off = 0; off < 0x40; off++)
1365 {
1366 AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1367 AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1368 }
1369#endif
1370
1371 /*
1372 * Loop thru the fields covering the 64 bytes of standard registers.
1373 */
1374 uint8_t const fBridge = fIsBridge ? 2 : 1;
1375 uint8_t *pbDstConfig = &pDev->config[0];
1376 for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1377 if (s_aFields[i].fBridge & fBridge)
1378 {
1379 uint8_t const off = s_aFields[i].off;
1380 uint8_t const cb = s_aFields[i].cb;
1381 uint32_t u32Src;
1382 uint32_t u32Dst;
1383 switch (cb)
1384 {
1385 case 1:
1386 u32Src = pbSrcConfig[off];
1387 u32Dst = pbDstConfig[off];
1388 break;
1389 case 2:
1390 u32Src = *(uint16_t const *)&pbSrcConfig[off];
1391 u32Dst = *(uint16_t const *)&pbDstConfig[off];
1392 break;
1393 case 4:
1394 u32Src = *(uint32_t const *)&pbSrcConfig[off];
1395 u32Dst = *(uint32_t const *)&pbDstConfig[off];
1396 break;
1397 default:
1398 AssertFailed();
1399 continue;
1400 }
1401
1402 if ( u32Src != u32Dst
1403 || off == VBOX_PCI_COMMAND)
1404 {
1405 if (u32Src != u32Dst)
1406 {
1407 if (!s_aFields[i].fWritable)
1408 LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1409 pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1410 else
1411 LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1412 pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1413 }
1414 if (off == VBOX_PCI_COMMAND)
1415 PCIDevSetCommand(pDev, 0); /* For remapping, see pciR3CommonLoadExec. */
1416 pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1417 }
1418 }
1419
1420 /*
1421 * The device dependent registers.
1422 *
1423 * We will not use ConfigWrite here as we have no clue about the size
1424 * of the registers, so the device is responsible for correctly
1425 * restoring functionality governed by these registers.
1426 */
1427 for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1428 if (pbDstConfig[off] != pbSrcConfig[off])
1429 {
1430 LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1431 pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1432 pbDstConfig[off] = pbSrcConfig[off];
1433 }
1434}
1435
1436
1437/**
1438 * Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
1439 *
1440 * @returns VBox status code.
1441 * @param pBus The bus which data is being loaded.
1442 * @param pSSM The saved state handle.
1443 * @param uVersion The data version.
1444 * @param uPass The pass.
1445 */
1446static DECLCALLBACK(int) pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1447{
1448 uint32_t u32;
1449 uint32_t i;
1450 int rc;
1451
1452 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1453
1454 /*
1455 * Iterate thru all the devices and write 0 to the COMMAND register so
1456 * that all the memory is unmapped before we start restoring the saved
1457 * mapping locations.
1458 *
1459 * The register value is restored afterwards so we can do proper
1460 * LogRels in pciR3CommonRestoreConfig.
1461 */
1462 for (i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1463 {
1464 PPCIDEVICE pDev = pBus->devices[i];
1465 if (pDev)
1466 {
1467 uint16_t u16 = PCIDevGetCommand(pDev);
1468 pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1469 PCIDevSetCommand(pDev, u16);
1470 Assert(PCIDevGetCommand(pDev) == u16);
1471 }
1472 }
1473
1474 /*
1475 * Iterate all the devices.
1476 */
1477 for (i = 0;; i++)
1478 {
1479 PCIDEVICE DevTmp;
1480 PPCIDEVICE pDev;
1481
1482 /* index / terminator */
1483 rc = SSMR3GetU32(pSSM, &u32);
1484 if (RT_FAILURE(rc))
1485 return rc;
1486 if (u32 == (uint32_t)~0)
1487 break;
1488 if ( u32 >= RT_ELEMENTS(pBus->devices)
1489 || u32 < i)
1490 {
1491 AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1492 return rc;
1493 }
1494
1495 /* skip forward to the device checking that no new devices are present. */
1496 for (; i < u32; i++)
1497 {
1498 if (pBus->devices[i])
1499 {
1500 LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->devices[i]->name,
1501 PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i])));
1502 if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1503 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1504 i, pBus->devices[i]->name, PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i]));
1505 }
1506 }
1507
1508 /* get the data */
1509 DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1510 SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1511 if (uVersion < 3)
1512 {
1513 int32_t i32Temp;
1514 /* Irq value not needed anymore. */
1515 rc = SSMR3GetS32(pSSM, &i32Temp);
1516 if (RT_FAILURE(rc))
1517 return rc;
1518 }
1519 else
1520 {
1521 rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1522 if (RT_FAILURE(rc))
1523 return rc;
1524 }
1525
1526 /* check that it's still around. */
1527 pDev = pBus->devices[i];
1528 if (!pDev)
1529 {
1530 LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1531 PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1532 if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1533 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1534 i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1535 continue;
1536 }
1537
1538 /* match the vendor id assuming that this will never be changed. */
1539 if ( DevTmp.config[0] != pDev->config[0]
1540 || DevTmp.config[1] != pDev->config[1])
1541 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1542 i, pDev->name, DevTmp.config, pDev->config);
1543
1544 /* commit the loaded device config. */
1545 pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1546
1547 pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1548 }
1549
1550 return VINF_SUCCESS;
1551}
1552
1553
1554/**
1555 * @callback_method_impl{FNSSMDEVLOADEXEC}
1556 */
1557static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1558{
1559 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1560 PPCIBUS pBus = &pThis->PciBus;
1561 uint32_t u32;
1562 int rc;
1563
1564 /*
1565 * Check the version.
1566 */
1567 if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1568 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1569 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1570
1571 /*
1572 * Bus state data.
1573 */
1574 SSMR3GetU32(pSSM, &pThis->uConfigReg);
1575 if (uVersion > 1)
1576 SSMR3GetBool(pSSM, &pThis->fUseIoApic);
1577
1578 /* Load IRQ states. */
1579 if (uVersion > 2)
1580 {
1581 for (uint8_t i = 0; i < PCI_IRQ_PINS; i++)
1582 SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_irq_levels[i]);
1583 for (uint8_t i = 0; i < PCI_APIC_IRQ_PINS; i++)
1584 SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_apic_irq_levels[i]);
1585
1586 SSMR3GetU32(pSSM, &pThis->acpi_irq_level);
1587 SSMR3GetS32(pSSM, &pThis->acpi_irq);
1588 }
1589
1590 /* separator */
1591 rc = SSMR3GetU32(pSSM, &u32);
1592 if (RT_FAILURE(rc))
1593 return rc;
1594 if (u32 != (uint32_t)~0)
1595 AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1596
1597 /*
1598 * The devices.
1599 */
1600 return pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1601}
1602
1603
1604/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
1605
1606/**
1607 * Registers the device with the specified PCI bus.
1608 *
1609 * @returns VBox status code.
1610 * @param pBus The bus to register with.
1611 * @param iDev The PCI device ordinal.
1612 * @param pPciDev The PCI device structure.
1613 * @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1614 */
1615static int pciR3RegisterDeviceInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1616{
1617 /*
1618 * Find device slot.
1619 */
1620 if (iDev < 0)
1621 {
1622 /*
1623 * Special check for the IDE controller which is our function 1 device
1624 * before searching.
1625 */
1626 if ( !strcmp(pszName, "piix3ide")
1627 && !pBus->devices[9])
1628 iDev = 9;
1629 /* LPC bus expected to be there by some guests, better make an additional argument to PDM
1630 device helpers, but requires significant rewrite */
1631 else if (!strcmp(pszName, "lpc")
1632 && !pBus->devices[0xf8])
1633 iDev = 0xf8;
1634 else
1635 {
1636 Assert(!(pBus->iDevSearch % 8));
1637 for (iDev = pBus->iDevSearch; iDev < (int)RT_ELEMENTS(pBus->devices); iDev += 8)
1638 if ( !pBus->devices[iDev]
1639 && !pBus->devices[iDev + 1]
1640 && !pBus->devices[iDev + 2]
1641 && !pBus->devices[iDev + 3]
1642 && !pBus->devices[iDev + 4]
1643 && !pBus->devices[iDev + 5]
1644 && !pBus->devices[iDev + 6]
1645 && !pBus->devices[iDev + 7])
1646 break;
1647 if (iDev >= (int)RT_ELEMENTS(pBus->devices))
1648 {
1649 AssertMsgFailed(("Couldn't find free spot!\n"));
1650 return VERR_PDM_TOO_PCI_MANY_DEVICES;
1651 }
1652 }
1653 pciDevClearRequestedDevfunc(pPciDev);
1654 }
1655 else
1656 {
1657 /*
1658 * An explicit request.
1659 *
1660 * If the slot is occupied we'll have to relocate the device
1661 * currently occupying it first. This can only be done if the
1662 * existing device wasn't explicitly assigned. Also we limit
1663 * ourselves to function 0 devices.
1664 *
1665 * If you start setting devices + function in the
1666 * config, do it for all pci devices!
1667 */
1668 //AssertReleaseMsg(iDev > 8 || pBus->iBus != 0, ("iDev=%d pszName=%s\n", iDev, pszName));
1669 if (pBus->devices[iDev])
1670 {
1671 int iDevRel;
1672 AssertReleaseMsg(!(iDev % 8), ("PCI Configuration Conflict! iDev=%d pszName=%s clashes with %s\n",
1673 iDev, pszName, pBus->devices[iDev]->name));
1674 if ( pciDevIsRequestedDevfunc(pBus->devices[iDev])
1675 || (pBus->devices[iDev + 1] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 1]))
1676 || (pBus->devices[iDev + 2] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 2]))
1677 || (pBus->devices[iDev + 3] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 3]))
1678 || (pBus->devices[iDev + 4] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 4]))
1679 || (pBus->devices[iDev + 5] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 5]))
1680 || (pBus->devices[iDev + 6] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 6]))
1681 || (pBus->devices[iDev + 7] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 7])))
1682 {
1683 AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1684 pszName, pBus->devices[iDev]->name, iDev));
1685 return VERR_INTERNAL_ERROR;
1686 }
1687
1688 /* Find free slot for the device(s) we're moving and move them. */
1689 for (iDevRel = pBus->iDevSearch; iDevRel < (int)RT_ELEMENTS(pBus->devices); iDevRel += 8)
1690 {
1691 if ( !pBus->devices[iDevRel]
1692 && !pBus->devices[iDevRel + 1]
1693 && !pBus->devices[iDevRel + 2]
1694 && !pBus->devices[iDevRel + 3]
1695 && !pBus->devices[iDevRel + 4]
1696 && !pBus->devices[iDevRel + 5]
1697 && !pBus->devices[iDevRel + 6]
1698 && !pBus->devices[iDevRel + 7])
1699 {
1700 int i = 0;
1701 for (i = 0; i < 8; i++)
1702 {
1703 if (!pBus->devices[iDev + i])
1704 continue;
1705 Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->devices[iDev + i]->name, iDev + i, iDevRel + i));
1706 pBus->devices[iDevRel + i] = pBus->devices[iDev + i];
1707 pBus->devices[iDevRel + i]->devfn = iDevRel + i;
1708 pBus->devices[iDev + i] = NULL;
1709 }
1710 }
1711 }
1712 if (pBus->devices[iDev])
1713 {
1714 AssertMsgFailed(("Couldn't find free spot!\n"));
1715 return VERR_PDM_TOO_PCI_MANY_DEVICES;
1716 }
1717 } /* if conflict */
1718 pciDevSetRequestedDevfunc(pPciDev);
1719 }
1720
1721 Assert(!pBus->devices[iDev]);
1722 pPciDev->devfn = iDev;
1723 pPciDev->name = pszName;
1724 pPciDev->Int.s.pBusR3 = pBus;
1725 pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1726 pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1727 pPciDev->Int.s.pfnConfigRead = pci_default_read_config;
1728 pPciDev->Int.s.pfnConfigWrite = pci_default_write_config;
1729 pBus->devices[iDev] = pPciDev;
1730 if (pciDevIsPci2PciBridge(pPciDev))
1731 {
1732 AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->devices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
1733 AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
1734 ("device is a bridge but does not implement read/write functions\n"));
1735 pBus->papBridgesR3[pBus->cBridges] = pPciDev;
1736 pBus->cBridges++;
1737 }
1738
1739 Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
1740 iDev >> 3, iDev & 7, 0x80000000 | (iDev << 8), pszName));
1741
1742 return VINF_SUCCESS;
1743}
1744
1745
1746/**
1747 * @interface_method_impl{PDMPCIBUSREG,pfnRegister}
1748 */
1749static DECLCALLBACK(int) pciR3Register(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
1750{
1751 PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
1752
1753 /*
1754 * Check input.
1755 */
1756 if ( !pszName
1757 || !pPciDev
1758 || iDev >= (int)RT_ELEMENTS(pBus->devices)
1759 || (iDev >= 0 && iDev <= 8))
1760 {
1761 AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1762 return VERR_INVALID_PARAMETER;
1763 }
1764
1765 /*
1766 * Register the device.
1767 */
1768 return pciR3RegisterDeviceInternal(pBus, iDev, pPciDev, pszName);
1769}
1770
1771
1772/**
1773 * @interface_method_impl{PDMPCIBUSREG,pfnIORegionRegisterR3}
1774 */
1775static DECLCALLBACK(int) pciR3CommonIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion,
1776 PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1777{
1778 NOREF(pDevIns);
1779
1780 /*
1781 * Validate.
1782 */
1783 AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
1784 || enmType == PCI_ADDRESS_SPACE_IO
1785 || enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
1786 ("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1787 VERR_INVALID_PARAMETER);
1788 AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1789 ("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1790 VERR_INVALID_PARAMETER);
1791 int iLastSet = ASMBitLastSetU32(cbRegion);
1792 AssertMsgReturn( iLastSet != 0
1793 && RT_BIT_32(iLastSet - 1) == cbRegion,
1794 ("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1795 VERR_INVALID_PARAMETER);
1796
1797 /*
1798 * Register the I/O region.
1799 */
1800 PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1801 pRegion->addr = ~0U;
1802 pRegion->size = cbRegion;
1803 pRegion->type = enmType;
1804 pRegion->map_func = pfnCallback;
1805
1806 /* Set type in the config space. */
1807 uint32_t u32Address = 0x10 + iRegion * 4;
1808 uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
1809 | (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
1810 *(uint32_t *)(pPciDev->config + u32Address) = RT_H2LE_U32(u32Value);
1811
1812 return VINF_SUCCESS;
1813}
1814
1815
1816/**
1817 * @interface_method_impl{PDMPCIBUSREG,pfnSetConfigCallbacksR3}
1818 */
1819static DECLCALLBACK(void)
1820pciR3CommonSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1821 PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1822{
1823 NOREF(pDevIns);
1824
1825 if (ppfnReadOld)
1826 *ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1827 pPciDev->Int.s.pfnConfigRead = pfnRead;
1828
1829 if (ppfnWriteOld)
1830 *ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1831 pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1832}
1833
1834
1835/**
1836 * @interface_method_impl{PDMPCIBUSREG,pfnFakePCIBIOSR3}
1837 */
1838static DECLCALLBACK(int) pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
1839{
1840 unsigned i;
1841 uint8_t elcr[2] = {0, 0};
1842 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1843 PVM pVM = PDMDevHlpGetVM(pDevIns); Assert(pVM);
1844 PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns); Assert(pVM);
1845
1846 /*
1847 * Set the start addresses.
1848 */
1849 pGlobals->pci_bios_io_addr = 0xd000;
1850 pGlobals->pci_bios_mem_addr = UINT32_C(0xf0000000);
1851 pGlobals->uBus = 0;
1852
1853 /*
1854 * Activate IRQ mappings.
1855 */
1856 for (i = 0; i < 4; i++)
1857 {
1858 uint8_t irq = pci_irqs[i];
1859 /* Set to trigger level. */
1860 elcr[irq >> 3] |= (1 << (irq & 7));
1861 /* Activate irq remapping in PIIX3. */
1862 pci_config_writeb(pGlobals, 0, pGlobals->PIIX3State.dev.devfn, 0x60 + i, irq);
1863 }
1864
1865 /* Tell to the PIC. */
1866 VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d0, elcr[0], sizeof(uint8_t));
1867 if (rcStrict == VINF_SUCCESS)
1868 rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d1, elcr[1], sizeof(uint8_t));
1869 if (rcStrict != VINF_SUCCESS)
1870 {
1871 AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1872 return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
1873 }
1874
1875 /*
1876 * Init the devices.
1877 */
1878 for (i = 0; i < 256; i++)
1879 {
1880 uint8_t aBridgePositions[256];
1881
1882 memset(aBridgePositions, 0, sizeof(aBridgePositions));
1883 Log2(("PCI: Initializing device %d (%#x)\n",
1884 i, 0x80000000 | (i << 8)));
1885 pci_bios_init_device(pGlobals, 0, i, 0, aBridgePositions);
1886 }
1887
1888 return VINF_SUCCESS;
1889}
1890
1891
1892/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
1893
1894/**
1895 * @callback_method_impl{FNDBGFHANDLERDEV}
1896 */
1897static DECLCALLBACK(void) pciR3IrqInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1898{
1899 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1900 NOREF(pszArgs);
1901
1902 uint16_t router = pGlobals->PIIX3State.dev.devfn;
1903 pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1904 router >> 8, (router >> 3) & 0x1f, router & 0x7);
1905
1906 for (int i = 0; i < 4; ++i)
1907 {
1908 uint8_t irq_map = pci_config_readb(pGlobals, 0, router, 0x60 + i);
1909 if (irq_map & 0x80)
1910 pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1911 else
1912 pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1913 }
1914}
1915
1916/**
1917 * Outputs indent.
1918 *
1919 * @param pHlp Output helpers.
1920 * @param iIndent Indentation level.
1921 */
1922static void pciR3PrintIndent(PCDBGFINFOHLP pHlp, int iIndent)
1923{
1924 while (iIndent-- > 0)
1925 pHlp->pfnPrintf(pHlp, " ");
1926}
1927
1928/**
1929 * Recursive worker for pciR3Info.
1930 *
1931 * @param pBus The bus to display.
1932 * @param pHlp Output helpers.
1933 * @param iIndent Indentation level.
1934 * @param fRegisters Whether to also display the PCI configuration registers
1935 * of each device on the bus.
1936 */
1937static void pciR3BusInfo(PPCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
1938{
1939 for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->devices); iDev++)
1940 {
1941 PPCIDEVICE pPciDev = pBus->devices[iDev];
1942 if (pPciDev != NULL)
1943 {
1944 pciR3PrintIndent(pHlp, iIndent);
1945
1946 /*
1947 * For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
1948 * as host driver handles real devices interrupts.
1949 */
1950 pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x%s%s",
1951 pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
1952 pPciDev->name,
1953 pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
1954 PCIDevGetWord(pPciDev, VBOX_PCI_VENDOR_ID), PCIDevGetWord(pPciDev, VBOX_PCI_DEVICE_ID),
1955 pciDevIsMsiCapable(pPciDev) ? " MSI" : "",
1956 pciDevIsMsixCapable(pPciDev) ? " MSI-X" : ""
1957 );
1958 if (PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
1959 pHlp->pfnPrintf(pHlp, " IRQ%d", PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
1960
1961 pHlp->pfnPrintf(pHlp, "\n");
1962
1963 uint16_t iCmd = PCIDevGetWord(pPciDev, VBOX_PCI_COMMAND);
1964 if ((iCmd & (VBOX_PCI_COMMAND_IO | VBOX_PCI_COMMAND_MEMORY)) != 0)
1965 {
1966 for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
1967 {
1968 PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1969 uint64_t iRegionSize = pRegion->size;
1970
1971 if (iRegionSize == 0)
1972 continue;
1973
1974 uint32_t u32Addr = PCIDevGetDWord(pPciDev, PCIDevGetRegionReg(iRegion));
1975 const char * pszDesc;
1976 char szDescBuf[128];
1977
1978 bool f64Bit = !!(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
1979 if (pRegion->type & PCI_ADDRESS_SPACE_IO)
1980 {
1981 pszDesc = "IO";
1982 u32Addr &= ~0x3;
1983 }
1984 else
1985 {
1986 RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
1987 f64Bit ? "64" : "32",
1988 (pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
1989 pszDesc = szDescBuf;
1990 u32Addr &= ~0xf;
1991 }
1992
1993 pciR3PrintIndent(pHlp, iIndent + 2);
1994 pHlp->pfnPrintf(pHlp, "%s region #%d: %x..%x\n",
1995 pszDesc, iRegion, u32Addr, u32Addr+iRegionSize);
1996 if (f64Bit)
1997 iRegion++;
1998 }
1999 }
2000
2001 pciR3PrintIndent(pHlp, iIndent + 2);
2002 uint16_t iStatus = PCIDevGetWord(pPciDev, VBOX_PCI_STATUS);
2003 pHlp->pfnPrintf(pHlp, "Command: %.*Rhxs, Status: %.*Rhxs\n",
2004 sizeof(uint16_t), &iCmd, sizeof(uint16_t), &iStatus);
2005 pciR3PrintIndent(pHlp, iIndent + 2);
2006 pHlp->pfnPrintf(pHlp, "Bus master: %s\n",
2007 iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2008
2009 if (fRegisters)
2010 {
2011 pciR3PrintIndent(pHlp, iIndent + 2);
2012 pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2013 for (int iReg = 0; iReg < 0x100; )
2014 {
2015 int iPerLine = 0x10;
2016 Assert (0x100 % iPerLine == 0);
2017 pciR3PrintIndent(pHlp, iIndent + 3);
2018
2019 while (iPerLine-- > 0)
2020 {
2021 pHlp->pfnPrintf(pHlp, "%02x ", PCIDevGetByte(pPciDev, iReg++));
2022 }
2023 pHlp->pfnPrintf(pHlp, "\n");
2024 }
2025 }
2026 }
2027 }
2028
2029 if (pBus->cBridges > 0)
2030 {
2031 pciR3PrintIndent(pHlp, iIndent);
2032 pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2033 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2034 {
2035 PPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PPCIBUS);
2036 pciR3BusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2037 }
2038 }
2039}
2040
2041
2042/**
2043 * @callback_method_impl{FNDBGFHANDLERDEV}
2044 */
2045static DECLCALLBACK(void) pciR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2046{
2047 PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2048
2049 if (pszArgs == NULL || !*pszArgs || !strcmp(pszArgs, "basic"))
2050 pciR3BusInfo(pBus, pHlp, 0, false);
2051 else if (!strcmp(pszArgs, "verbose"))
2052 pciR3BusInfo(pBus, pHlp, 0, true);
2053 else
2054 pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2055}
2056
2057
2058/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
2059
2060/**
2061 * @interface_method_impl{PDMDEVREG,pfnRelocate}
2062 */
2063static DECLCALLBACK(void) pciR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2064{
2065 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2066 PPCIBUS pBus = &pGlobals->PciBus;
2067 pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2068
2069 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2070 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2071
2072 /* Relocate RC pointers for the attached pci devices. */
2073 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2074 {
2075 if (pBus->devices[i])
2076 pBus->devices[i]->Int.s.pBusRC += offDelta;
2077 }
2078}
2079
2080
2081/**
2082 * @interface_method_impl{PDMDEVREG,pfnReset}
2083 */
2084static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
2085{
2086 pciR3FakePCIBIOS(pDevIns);
2087}
2088
2089
2090/**
2091 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2092 */
2093static DECLCALLBACK(int) pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2094{
2095 Assert(iInstance == 0);
2096 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2097
2098 /*
2099 * Validate and read configuration.
2100 */
2101 if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
2102 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2103
2104 /* query whether we got an IOAPIC */
2105 bool fUseIoApic;
2106 int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2107 if (RT_FAILURE(rc))
2108 return PDMDEV_SET_ERROR(pDevIns, rc,
2109 N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2110
2111 /* check if RC code is enabled. */
2112 bool fGCEnabled;
2113 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2114 if (RT_FAILURE(rc))
2115 return PDMDEV_SET_ERROR(pDevIns, rc,
2116 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2117
2118 /* check if R0 code is enabled. */
2119 bool fR0Enabled;
2120 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2121 if (RT_FAILURE(rc))
2122 return PDMDEV_SET_ERROR(pDevIns, rc,
2123 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2124 Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2125
2126 /*
2127 * Init data and register the PCI bus.
2128 */
2129 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2130 pGlobals->pci_bios_io_addr = 0xc000;
2131 pGlobals->pci_bios_mem_addr = 0xf0000000;
2132 memset((void *)&pGlobals->pci_irq_levels, 0, sizeof(pGlobals->pci_irq_levels));
2133 pGlobals->fUseIoApic = fUseIoApic;
2134 memset((void *)&pGlobals->pci_apic_irq_levels, 0, sizeof(pGlobals->pci_apic_irq_levels));
2135
2136 pGlobals->pDevInsR3 = pDevIns;
2137 pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2138 pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2139
2140 pGlobals->PciBus.pDevInsR3 = pDevIns;
2141 pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2142 pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2143 pGlobals->PciBus.papBridgesR3 = (PPCIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE)
2144 * RT_ELEMENTS(pGlobals->PciBus.devices));
2145
2146 PDMPCIBUSREG PciBusReg;
2147 PPCIBUS pBus = &pGlobals->PciBus;
2148 PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2149 PciBusReg.pfnRegisterR3 = pciR3Register;
2150 PciBusReg.pfnRegisterMsiR3 = NULL;
2151 PciBusReg.pfnIORegionRegisterR3 = pciR3CommonIORegionRegister;
2152 PciBusReg.pfnSetConfigCallbacksR3 = pciR3CommonSetConfigCallbacks;
2153 PciBusReg.pfnSetIrqR3 = pciSetIrq;
2154 PciBusReg.pfnFakePCIBIOSR3 = pciR3FakePCIBIOS;
2155 PciBusReg.pszSetIrqRC = fGCEnabled ? "pciSetIrq" : NULL;
2156 PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
2157 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2158 if (RT_FAILURE(rc))
2159 return PDMDEV_SET_ERROR(pDevIns, rc,
2160 N_("Failed to register ourselves as a PCI Bus"));
2161 if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2162 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2163 N_("PCI helper version mismatch; got %#x expected %#x"),
2164 pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION);
2165
2166 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2167 pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2168
2169 /* Disable default device locking. */
2170 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2171 AssertRCReturn(rc, rc);
2172
2173 /*
2174 * Fill in PCI configs and add them to the bus.
2175 */
2176 /* i440FX */
2177 PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2178 PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
2179 PCIDevSetRevisionId(&pBus->PciDev, 0x02);
2180 PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
2181 PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2182 PCIDevSetHeaderType(&pBus->PciDev, 0x00);
2183
2184 pBus->PciDev.pDevIns = pDevIns;
2185 pciDevSetRequestedDevfunc(&pBus->PciDev);
2186 pciR3RegisterDeviceInternal(pBus, 0, &pBus->PciDev, "i440FX");
2187
2188 /* PIIX3 */
2189 PCIDevSetVendorId( &pGlobals->PIIX3State.dev, 0x8086); /* Intel */
2190 PCIDevSetDeviceId( &pGlobals->PIIX3State.dev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
2191 PCIDevSetClassSub( &pGlobals->PIIX3State.dev, 0x01); /* PCI_ISA */
2192 PCIDevSetClassBase( &pGlobals->PIIX3State.dev, 0x06); /* PCI_bridge */
2193 PCIDevSetHeaderType(&pGlobals->PIIX3State.dev, 0x80); /* PCI_multifunction, generic */
2194
2195 pGlobals->PIIX3State.dev.pDevIns = pDevIns;
2196 pciDevSetRequestedDevfunc(&pGlobals->PIIX3State.dev);
2197 pciR3RegisterDeviceInternal(pBus, 8, &pGlobals->PIIX3State.dev, "PIIX3");
2198 pciR3Piix3Reset(&pGlobals->PIIX3State);
2199
2200 pBus->iDevSearch = 16;
2201
2202 /*
2203 * Register I/O ports and save state.
2204 */
2205 rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
2206 if (RT_FAILURE(rc))
2207 return rc;
2208 rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
2209 if (RT_FAILURE(rc))
2210 return rc;
2211 if (fGCEnabled)
2212 {
2213 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2214 if (RT_FAILURE(rc))
2215 return rc;
2216 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2217 if (RT_FAILURE(rc))
2218 return rc;
2219 }
2220 if (fR0Enabled)
2221 {
2222 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2223 if (RT_FAILURE(rc))
2224 return rc;
2225 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2226 if (RT_FAILURE(rc))
2227 return rc;
2228 }
2229
2230 rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(*pBus) + 16*128, "pgm",
2231 NULL, NULL, NULL,
2232 NULL, pciR3SaveExec, NULL,
2233 NULL, pciR3LoadExec, NULL);
2234 if (RT_FAILURE(rc))
2235 return rc;
2236
2237 PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
2238 "Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
2239 pciR3Info);
2240 PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ routing state. (no arguments)", pciR3IrqInfo);
2241
2242 return VINF_SUCCESS;
2243}
2244
2245
2246/**
2247 * The device registration structure.
2248 */
2249const PDMDEVREG g_DevicePCI =
2250{
2251 /* u32Version */
2252 PDM_DEVREG_VERSION,
2253 /* szName */
2254 "pci",
2255 /* szRCMod */
2256 "VBoxDDGC.gc",
2257 /* szR0Mod */
2258 "VBoxDDR0.r0",
2259 /* pszDescription */
2260 "i440FX PCI bridge and PIIX3 ISA bridge.",
2261 /* fFlags */
2262 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2263 /* fClass */
2264 PDM_DEVREG_CLASS_BUS_PCI | PDM_DEVREG_CLASS_BUS_ISA,
2265 /* cMaxInstances */
2266 1,
2267 /* cbInstance */
2268 sizeof(PCIGLOBALS),
2269 /* pfnConstruct */
2270 pciR3Construct,
2271 /* pfnDestruct */
2272 NULL,
2273 /* pfnRelocate */
2274 pciR3Relocate,
2275 /* pfnMemSetup */
2276 NULL,
2277 /* pfnPowerOn */
2278 NULL,
2279 /* pfnReset */
2280 pciR3Reset,
2281 /* pfnSuspend */
2282 NULL,
2283 /* pfnResume */
2284 NULL,
2285 /* pfnAttach */
2286 NULL,
2287 /* pfnDetach */
2288 NULL,
2289 /* pfnQueryInterface */
2290 NULL,
2291 /* pfnInitComplete */
2292 NULL,
2293 /* pfnPowerOff */
2294 NULL,
2295 /* pfnSoftReset */
2296 NULL,
2297 /* u32VersionEnd */
2298 PDM_DEVREG_VERSION
2299
2300};
2301#endif /* IN_RING3 */
2302
2303
2304
2305/* -=-=-=-=-=- The PCI bridge specific bits -=-=-=-=-=- */
2306
2307/**
2308 * @interface_method_impl{PDMPCIBUSREG,pfnSetIrq}
2309 */
2310PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
2311{
2312 /*
2313 * The PCI-to-PCI bridge specification defines how the interrupt pins
2314 * are routed from the secondary to the primary bus (see chapter 9).
2315 * iIrq gives the interrupt pin the pci device asserted.
2316 * We change iIrq here according to the spec and call the SetIrq function
2317 * of our parent passing the device which asserted the interrupt instead of the device of the bridge.
2318 */
2319 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2320 PPCIDEVICE pPciDevBus = pPciDev;
2321 int iIrqPinBridge = iIrq;
2322 uint8_t uDevFnBridge = 0;
2323
2324 /* Walk the chain until we reach the host bus. */
2325 do
2326 {
2327 uDevFnBridge = pBus->PciDev.devfn;
2328 iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
2329
2330 /* Get the parent. */
2331 pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
2332 pPciDevBus = &pBus->PciDev;
2333 } while (pBus->iBus != 0);
2334
2335 AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
2336 pciSetIrqInternal(PCIBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
2337}
2338
2339#ifdef IN_RING3
2340
2341/**
2342 * @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
2343 */
2344static void pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
2345{
2346 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2347
2348 LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
2349
2350 /* If the current bus is not the target bus search for the bus which contains the device. */
2351 if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2352 {
2353 PPCIDEVICE pBridgeDevice = pciR3FindBridge(pBus, iBus);
2354 if (pBridgeDevice)
2355 {
2356 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
2357 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
2358 }
2359 }
2360 else
2361 {
2362 /* This is the target bus, pass the write to the device. */
2363 PPCIDEVICE pPciDev = pBus->devices[iDevice];
2364 if (pPciDev)
2365 {
2366 Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2367 pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
2368 }
2369 }
2370}
2371
2372
2373/**
2374 * @callback_method_impl{FNPCIBRIDGECONFIGREAD}
2375 */
2376static uint32_t pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
2377{
2378 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2379 uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
2380
2381 LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
2382
2383 /* If the current bus is not the target bus search for the bus which contains the device. */
2384 if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2385 {
2386 PPCIDEVICE pBridgeDevice = pciR3FindBridge(pBus, iBus);
2387 if (pBridgeDevice)
2388 {
2389 AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
2390 u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
2391 }
2392 }
2393 else
2394 {
2395 /* This is the target bus, pass the read to the device. */
2396 PPCIDEVICE pPciDev = pBus->devices[iDevice];
2397 if (pPciDev)
2398 {
2399 u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
2400 Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2401 }
2402 }
2403
2404 return u32Value;
2405}
2406
2407
2408/**
2409 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2410 */
2411static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2412{
2413 PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2414 return pciR3CommonSaveExec(pThis, pSSM);
2415}
2416
2417
2418/**
2419 * @callback_method_impl{FNSSMDEVLOADEXEC}
2420 */
2421static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2422{
2423 PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2424 if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
2425 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2426 return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
2427}
2428
2429
2430/**
2431 * @interface_method_impl{PDMPCIBUSREG,pfnRegister}
2432 */
2433static DECLCALLBACK(int) pcibridgeR3RegisterDevice(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
2434{
2435 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2436
2437 /*
2438 * Check input.
2439 */
2440 if ( !pszName
2441 || !pPciDev
2442 || iDev >= (int)RT_ELEMENTS(pBus->devices))
2443 {
2444 AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
2445 return VERR_INVALID_PARAMETER;
2446 }
2447
2448 /*
2449 * Register the device.
2450 */
2451 return pciR3RegisterDeviceInternal(pBus, iDev, pPciDev, pszName);
2452}
2453
2454
2455/**
2456 * @interface_method_impl{PDMDEVREG, pfnReset}
2457 */
2458static DECLCALLBACK(void) pcibridgeR3Reset(PPDMDEVINS pDevIns)
2459{
2460 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2461
2462 /* Reset config space to default values. */
2463 pBus->PciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
2464 pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
2465 pBus->PciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
2466}
2467
2468
2469/**
2470 * @interface_method_impl{PDMDEVREG, pfnRelocate}
2471 */
2472static DECLCALLBACK(void) pcibridgeR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2473{
2474 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2475 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2476
2477 /* Relocate RC pointers for the attached pci devices. */
2478 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2479 {
2480 if (pBus->devices[i])
2481 pBus->devices[i]->Int.s.pBusRC += offDelta;
2482 }
2483}
2484
2485
2486/**
2487 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2488 */
2489static DECLCALLBACK(int) pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2490{
2491 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2492
2493 /*
2494 * Validate and read configuration.
2495 */
2496 if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2497 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2498
2499 /* check if RC code is enabled. */
2500 bool fGCEnabled;
2501 int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2502 if (RT_FAILURE(rc))
2503 return PDMDEV_SET_ERROR(pDevIns, rc,
2504 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2505
2506 /* check if R0 code is enabled. */
2507 bool fR0Enabled;
2508 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2509 if (RT_FAILURE(rc))
2510 return PDMDEV_SET_ERROR(pDevIns, rc,
2511 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2512 Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2513
2514 /*
2515 * Init data and register the PCI bus.
2516 */
2517 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2518 pBus->pDevInsR3 = pDevIns;
2519 pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2520 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2521 pBus->papBridgesR3 = (PPCIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) * RT_ELEMENTS(pBus->devices));
2522
2523 PDMPCIBUSREG PciBusReg;
2524 PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2525 PciBusReg.pfnRegisterR3 = pcibridgeR3RegisterDevice;
2526 PciBusReg.pfnRegisterMsiR3 = NULL;
2527 PciBusReg.pfnIORegionRegisterR3 = pciR3CommonIORegionRegister;
2528 PciBusReg.pfnSetConfigCallbacksR3 = pciR3CommonSetConfigCallbacks;
2529 PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
2530 PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2531 PciBusReg.pszSetIrqRC = fGCEnabled ? "pcibridgeSetIrq" : NULL;
2532 PciBusReg.pszSetIrqR0 = fR0Enabled ? "pcibridgeSetIrq" : NULL;
2533 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2534 if (RT_FAILURE(rc))
2535 return PDMDEV_SET_ERROR(pDevIns, rc,
2536 N_("Failed to register ourselves as a PCI Bus"));
2537 if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2538 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2539 N_("PCI helper version mismatch; got %#x expected %#x"),
2540 pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2541
2542 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2543 pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2544
2545 /*
2546 * Fill in PCI configs and add them to the bus.
2547 */
2548 PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2549 PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2550 PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
2551 PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
2552 PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2553 PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
2554 PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2555 PCIDevSetCommand( &pBus->PciDev, 0x00);
2556 PCIDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
2557 PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
2558
2559 /*
2560 * This device does not generate interrupts. Interrupt delivery from
2561 * devices attached to the bus is unaffected.
2562 */
2563 PCIDevSetInterruptPin(&pBus->PciDev, 0x00);
2564
2565 pBus->PciDev.pDevIns = pDevIns;
2566
2567 /* Bridge-specific data */
2568 pciDevSetPci2PciBridge(&pBus->PciDev);
2569 pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
2570 pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
2571
2572 /*
2573 * Register this PCI bridge. The called function will take care on which bus we will get registered.
2574 */
2575 rc = PDMDevHlpPCIRegister(pDevIns, &pBus->PciDev);
2576 if (RT_FAILURE(rc))
2577 return rc;
2578
2579 pBus->iDevSearch = 0;
2580 /*
2581 * The iBus property doesn't really represent the bus number
2582 * because the guest and the BIOS can choose different bus numbers
2583 * for them.
2584 * The bus number is mainly for the setIrq function to indicate
2585 * when the host bus is reached which will have iBus = 0.
2586 * That's why the + 1.
2587 */
2588 pBus->iBus = iInstance + 1;
2589
2590 /*
2591 * Register SSM handlers. We use the same saved state version as for the host bridge
2592 * to make changes easier.
2593 */
2594 rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(*pBus) + 16*128, "pgm",
2595 NULL, NULL, NULL,
2596 NULL, pcibridgeR3SaveExec, NULL,
2597 NULL, pcibridgeR3LoadExec, NULL);
2598 if (RT_FAILURE(rc))
2599 return rc;
2600
2601 return VINF_SUCCESS;
2602}
2603
2604
2605/**
2606 * The device registration structure
2607 * for the PCI-to-PCI bridge.
2608 */
2609const PDMDEVREG g_DevicePCIBridge =
2610{
2611 /* u32Version */
2612 PDM_DEVREG_VERSION,
2613 /* szName */
2614 "pcibridge",
2615 /* szRCMod */
2616 "VBoxDDGC.gc",
2617 /* szR0Mod */
2618 "VBoxDDR0.r0",
2619 /* pszDescription */
2620 "82801 Mobile PCI to PCI bridge",
2621 /* fFlags */
2622 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2623 /* fClass */
2624 PDM_DEVREG_CLASS_BUS_PCI,
2625 /* cMaxInstances */
2626 ~0U,
2627 /* cbInstance */
2628 sizeof(PCIBUS),
2629 /* pfnConstruct */
2630 pcibridgeR3Construct,
2631 /* pfnDestruct */
2632 NULL,
2633 /* pfnRelocate */
2634 pcibridgeR3Relocate,
2635 /* pfnMemSetup */
2636 NULL,
2637 /* pfnPowerOn */
2638 NULL,
2639 /* pfnReset */
2640 pcibridgeR3Reset,
2641 /* pfnSuspend */
2642 NULL,
2643 /* pfnResume */
2644 NULL,
2645 /* pfnAttach */
2646 NULL,
2647 /* pfnDetach */
2648 NULL,
2649 /* pfnQueryInterface */
2650 NULL,
2651 /* pfnInitComplete */
2652 NULL,
2653 /* pfnPowerOff */
2654 NULL,
2655 /* pfnSoftReset */
2656 NULL,
2657 /* u32VersionEnd */
2658 PDM_DEVREG_VERSION
2659};
2660
2661#endif /* IN_RING3 */
2662#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette